+1 -1

drivers/infiniband/core/cache.c

reviewed

··· 46 46 47 47 struct ib_pkey_cache { 48 48 int table_len; 49 49 - u16 table[]; 49 49 + u16 table[] __counted_by(table_len); 50 50 }; 51 51 52 52 struct ib_update_work {

+1

drivers/infiniband/core/core_priv.h

reviewed

··· 373 373 374 374 void ib_cq_pool_cleanup(struct ib_device *dev); 375 375 376 376 + bool rdma_nl_get_privileged_qkey(void); 376 377 #endif /* _CORE_PRIV_H */

+3 -1

drivers/infiniband/core/device.c

reviewed

··· 804 804 * empty slots at the beginning. 805 805 */ 806 806 pdata_rcu = kzalloc(struct_size(pdata_rcu, pdata, 807 807 - rdma_end_port(device) + 1), 807 807 + size_add(rdma_end_port(device), 1)), 808 808 GFP_KERNEL); 809 809 if (!pdata_rcu) 810 810 return -ENOMEM; ··· 2651 2651 SET_DEVICE_OP(dev_ops, fill_res_mr_entry_raw); 2652 2652 SET_DEVICE_OP(dev_ops, fill_res_qp_entry); 2653 2653 SET_DEVICE_OP(dev_ops, fill_res_qp_entry_raw); 2654 2654 + SET_DEVICE_OP(dev_ops, fill_res_srq_entry); 2655 2655 + SET_DEVICE_OP(dev_ops, fill_res_srq_entry_raw); 2654 2656 SET_DEVICE_OP(dev_ops, fill_stat_mr_entry); 2655 2657 SET_DEVICE_OP(dev_ops, get_dev_fw_str); 2656 2658 SET_DEVICE_OP(dev_ops, get_dma_mr);

+1 -2

drivers/infiniband/core/lag.c

reviewed

··· 102 102 103 103 void rdma_lag_put_ah_roce_slave(struct net_device *xmit_slave) 104 104 { 105 105 - if (xmit_slave) 106 106 - dev_put(xmit_slave); 105 105 + dev_put(xmit_slave); 107 106 } 108 107 109 108 struct net_device *rdma_lag_get_ah_roce_slave(struct ib_device *device,

+81 -11

drivers/infiniband/core/nldev.c

reviewed

··· 43 43 #include "restrack.h" 44 44 #include "uverbs.h" 45 45 46 46 + /* 47 47 + * This determines whether a non-privileged user is allowed to specify a 48 48 + * controlled QKEY or not, when true non-privileged user is allowed to specify 49 49 + * a controlled QKEY. 50 50 + */ 51 51 + static bool privileged_qkey; 52 52 + 46 53 typedef int (*res_fill_func_t)(struct sk_buff*, bool, 47 54 struct rdma_restrack_entry*, uint32_t); 48 55 ··· 163 156 [RDMA_NLDEV_SYS_ATTR_COPY_ON_FORK] = { .type = NLA_U8 }, 164 157 [RDMA_NLDEV_ATTR_STAT_HWCOUNTER_INDEX] = { .type = NLA_U32 }, 165 158 [RDMA_NLDEV_ATTR_STAT_HWCOUNTER_DYNAMIC] = { .type = NLA_U8 }, 159 159 + [RDMA_NLDEV_SYS_ATTR_PRIVILEGED_QKEY_MODE] = { .type = NLA_U8 }, 166 160 }; 167 161 168 162 static int put_driver_name_print_type(struct sk_buff *msg, const char *name, ··· 244 236 value); 245 237 } 246 238 EXPORT_SYMBOL(rdma_nl_put_driver_u64_hex); 239 239 + 240 240 + bool rdma_nl_get_privileged_qkey(void) 241 241 + { 242 242 + return privileged_qkey || capable(CAP_NET_RAW); 243 243 + } 244 244 + EXPORT_SYMBOL(rdma_nl_get_privileged_qkey); 247 245 248 246 static int fill_nldev_handle(struct sk_buff *msg, struct ib_device *device) 249 247 { ··· 371 357 } 372 358 373 359 out: 374 374 - if (netdev) 375 375 - dev_put(netdev); 360 360 + dev_put(netdev); 376 361 return ret; 377 362 } 378 363 ··· 831 818 struct rdma_restrack_entry *res, uint32_t port) 832 819 { 833 820 struct ib_srq *srq = container_of(res, struct ib_srq, res); 821 821 + struct ib_device *dev = srq->device; 834 822 835 823 if (nla_put_u32(msg, RDMA_NLDEV_ATTR_RES_SRQN, srq->res.id)) 836 824 goto err; ··· 851 837 if (fill_res_srq_qps(msg, srq)) 852 838 goto err; 853 839 854 854 - return fill_res_name_pid(msg, res); 840 840 + if (fill_res_name_pid(msg, res)) 841 841 + goto err; 842 842 + 843 843 + if (dev->ops.fill_res_srq_entry) 844 844 + return dev->ops.fill_res_srq_entry(msg, srq); 845 845 + 846 846 + return 0; 855 847 856 848 err: 857 849 return -EMSGSIZE; 850 850 + } 851 851 + 852 852 + static int fill_res_srq_raw_entry(struct sk_buff *msg, bool has_cap_net_admin, 853 853 + struct rdma_restrack_entry *res, uint32_t port) 854 854 + { 855 855 + struct ib_srq *srq = container_of(res, struct ib_srq, res); 856 856 + struct ib_device *dev = srq->device; 857 857 + 858 858 + if (!dev->ops.fill_res_srq_entry_raw) 859 859 + return -EINVAL; 860 860 + return dev->ops.fill_res_srq_entry_raw(msg, srq); 858 861 } 859 862 860 863 static int fill_stat_counter_mode(struct sk_buff *msg, ··· 1683 1652 RES_GET_FUNCS(counter, RDMA_RESTRACK_COUNTER); 1684 1653 RES_GET_FUNCS(ctx, RDMA_RESTRACK_CTX); 1685 1654 RES_GET_FUNCS(srq, RDMA_RESTRACK_SRQ); 1655 1655 + RES_GET_FUNCS(srq_raw, RDMA_RESTRACK_SRQ); 1686 1656 1687 1657 static LIST_HEAD(link_ops); 1688 1658 static DECLARE_RWSEM(link_ops_rwsem); ··· 1914 1882 return err; 1915 1883 } 1916 1884 1885 1885 + err = nla_put_u8(msg, RDMA_NLDEV_SYS_ATTR_PRIVILEGED_QKEY_MODE, 1886 1886 + (u8)privileged_qkey); 1887 1887 + if (err) { 1888 1888 + nlmsg_free(msg); 1889 1889 + return err; 1890 1890 + } 1917 1891 /* 1918 1892 * Copy-on-fork is supported. 1919 1893 * See commits: ··· 1936 1898 return rdma_nl_unicast(sock_net(skb->sk), msg, NETLINK_CB(skb).portid); 1937 1899 } 1938 1900 1939 1939 - static int nldev_set_sys_set_doit(struct sk_buff *skb, struct nlmsghdr *nlh, 1940 1940 - struct netlink_ext_ack *extack) 1901 1901 + static int nldev_set_sys_set_netns_doit(struct nlattr *tb[]) 1941 1902 { 1942 1942 - struct nlattr *tb[RDMA_NLDEV_ATTR_MAX]; 1943 1903 u8 enable; 1944 1904 int err; 1945 1945 - 1946 1946 - err = nlmsg_parse(nlh, 0, tb, RDMA_NLDEV_ATTR_MAX - 1, 1947 1947 - nldev_policy, extack); 1948 1948 - if (err || !tb[RDMA_NLDEV_SYS_ATTR_NETNS_MODE]) 1949 1949 - return -EINVAL; 1950 1905 1951 1906 enable = nla_get_u8(tb[RDMA_NLDEV_SYS_ATTR_NETNS_MODE]); 1952 1907 /* Only 0 and 1 are supported */ ··· 1949 1918 err = rdma_compatdev_set(enable); 1950 1919 return err; 1951 1920 } 1921 1921 + 1922 1922 + static int nldev_set_sys_set_pqkey_doit(struct nlattr *tb[]) 1923 1923 + { 1924 1924 + u8 enable; 1925 1925 + 1926 1926 + enable = nla_get_u8(tb[RDMA_NLDEV_SYS_ATTR_PRIVILEGED_QKEY_MODE]); 1927 1927 + /* Only 0 and 1 are supported */ 1928 1928 + if (enable > 1) 1929 1929 + return -EINVAL; 1930 1930 + 1931 1931 + privileged_qkey = enable; 1932 1932 + return 0; 1933 1933 + } 1934 1934 + 1935 1935 + static int nldev_set_sys_set_doit(struct sk_buff *skb, struct nlmsghdr *nlh, 1936 1936 + struct netlink_ext_ack *extack) 1937 1937 + { 1938 1938 + struct nlattr *tb[RDMA_NLDEV_ATTR_MAX]; 1939 1939 + int err; 1940 1940 + 1941 1941 + err = nlmsg_parse(nlh, 0, tb, RDMA_NLDEV_ATTR_MAX - 1, 1942 1942 + nldev_policy, extack); 1943 1943 + if (err) 1944 1944 + return -EINVAL; 1945 1945 + 1946 1946 + if (tb[RDMA_NLDEV_SYS_ATTR_NETNS_MODE]) 1947 1947 + return nldev_set_sys_set_netns_doit(tb); 1948 1948 + 1949 1949 + if (tb[RDMA_NLDEV_SYS_ATTR_PRIVILEGED_QKEY_MODE]) 1950 1950 + return nldev_set_sys_set_pqkey_doit(tb); 1951 1951 + 1952 1952 + return -EINVAL; 1953 1953 + } 1954 1954 + 1952 1955 1953 1956 static int nldev_stat_set_mode_doit(struct sk_buff *msg, 1954 1957 struct netlink_ext_ack *extack, ··· 2621 2556 [RDMA_NLDEV_CMD_RES_MR_GET_RAW] = { 2622 2557 .doit = nldev_res_get_mr_raw_doit, 2623 2558 .dump = nldev_res_get_mr_raw_dumpit, 2559 2559 + .flags = RDMA_NL_ADMIN_PERM, 2560 2560 + }, 2561 2561 + [RDMA_NLDEV_CMD_RES_SRQ_GET_RAW] = { 2562 2562 + .doit = nldev_res_get_srq_raw_doit, 2563 2563 + .dump = nldev_res_get_srq_raw_dumpit, 2624 2564 .flags = RDMA_NL_ADMIN_PERM, 2625 2565 }, 2626 2566 [RDMA_NLDEV_CMD_STAT_GET_STATUS] = {

+1 -1

drivers/infiniband/core/rw.c

reviewed

··· 666 666 factor = 1; 667 667 668 668 /* 669 669 - * If the devices needs MRs to perform RDMA READ or WRITE operations, 669 669 + * If the device needs MRs to perform RDMA READ or WRITE operations, 670 670 * we'll need two additional MRs for the registrations and the 671 671 * invalidation. 672 672 */

+3 -1

drivers/infiniband/core/sa_query.c

reviewed

··· 2159 2159 s = rdma_start_port(device); 2160 2160 e = rdma_end_port(device); 2161 2161 2162 2162 - sa_dev = kzalloc(struct_size(sa_dev, port, e - s + 1), GFP_KERNEL); 2162 2162 + sa_dev = kzalloc(struct_size(sa_dev, port, 2163 2163 + size_add(size_sub(e, s), 1)), 2164 2164 + GFP_KERNEL); 2163 2165 if (!sa_dev) 2164 2166 return -ENOMEM; 2165 2167

+9 -5

drivers/infiniband/core/sysfs.c

reviewed

··· 342 342 speed = " NDR"; 343 343 rate = 1000; 344 344 break; 345 345 + case IB_SPEED_XDR: 346 346 + speed = " XDR"; 347 347 + rate = 2000; 348 348 + break; 345 349 case IB_SPEED_SDR: 346 350 default: /* default to SDR for invalid rates */ 347 351 speed = " SDR"; ··· 907 903 * Two extra attribue elements here, one for the lifespan entry and 908 904 * one to NULL terminate the list for the sysfs core code 909 905 */ 910 910 - data = kzalloc(struct_size(data, attrs, stats->num_counters + 1), 906 906 + data = kzalloc(struct_size(data, attrs, size_add(stats->num_counters, 1)), 911 907 GFP_KERNEL); 912 908 if (!data) 913 909 goto err_free_stats; ··· 1013 1009 * Two extra attribue elements here, one for the lifespan entry and 1014 1010 * one to NULL terminate the list for the sysfs core code 1015 1011 */ 1016 1016 - data = kzalloc(struct_size(data, attrs, stats->num_counters + 1), 1012 1012 + data = kzalloc(struct_size(data, attrs, size_add(stats->num_counters, 1)), 1017 1013 GFP_KERNEL); 1018 1014 if (!data) 1019 1015 goto err_free_stats; ··· 1144 1140 int ret; 1145 1141 1146 1142 gid_attr_group = kzalloc(struct_size(gid_attr_group, attrs_list, 1147 1147 - attr->gid_tbl_len * 2), 1143 1143 + size_mul(attr->gid_tbl_len, 2)), 1148 1144 GFP_KERNEL); 1149 1145 if (!gid_attr_group) 1150 1146 return -ENOMEM; ··· 1209 1205 int ret; 1210 1206 1211 1207 p = kvzalloc(struct_size(p, attrs_list, 1212 1212 - attr->gid_tbl_len + attr->pkey_tbl_len), 1213 1213 - GFP_KERNEL); 1208 1208 + size_add(attr->gid_tbl_len, attr->pkey_tbl_len)), 1209 1209 + GFP_KERNEL); 1214 1210 if (!p) 1215 1211 return ERR_PTR(-ENOMEM); 1216 1212 p->ibdev = device;

+3 -1

drivers/infiniband/core/user_mad.c

reviewed

··· 1378 1378 s = rdma_start_port(device); 1379 1379 e = rdma_end_port(device); 1380 1380 1381 1381 - umad_dev = kzalloc(struct_size(umad_dev, ports, e - s + 1), GFP_KERNEL); 1381 1381 + umad_dev = kzalloc(struct_size(umad_dev, ports, 1382 1382 + size_add(size_sub(e, s), 1)), 1383 1383 + GFP_KERNEL); 1382 1384 if (!umad_dev) 1383 1385 return -ENOMEM; 1384 1386

+2 -1

drivers/infiniband/core/uverbs_cmd.c

reviewed

··· 1851 1851 if (cmd->base.attr_mask & IB_QP_PATH_MIG_STATE) 1852 1852 attr->path_mig_state = cmd->base.path_mig_state; 1853 1853 if (cmd->base.attr_mask & IB_QP_QKEY) { 1854 1854 - if (cmd->base.qkey & IB_QP_SET_QKEY && !capable(CAP_NET_RAW)) { 1854 1854 + if (cmd->base.qkey & IB_QP_SET_QKEY && 1855 1855 + !rdma_nl_get_privileged_qkey()) { 1855 1856 ret = -EPERM; 1856 1857 goto release_qp; 1857 1858 }

+2 -1

drivers/infiniband/core/uverbs_std_types_device.c

reviewed

··· 203 203 204 204 copy_port_attr_to_resp(&attr, &resp.legacy_resp, ib_dev, port_num); 205 205 resp.port_cap_flags2 = attr.port_cap_flags2; 206 206 + resp.active_speed_ex = attr.active_speed; 206 207 207 208 return uverbs_copy_to_struct_or_zero(attrs, UVERBS_ATTR_QUERY_PORT_RESP, 208 209 &resp, sizeof(resp)); ··· 462 461 UVERBS_ATTR_PTR_OUT( 463 462 UVERBS_ATTR_QUERY_PORT_RESP, 464 463 UVERBS_ATTR_STRUCT(struct ib_uverbs_query_port_resp_ex, 465 465 - reserved), 464 464 + active_speed_ex), 466 465 UA_MANDATORY)); 467 466 468 467 DECLARE_UVERBS_NAMED_METHOD(

+5 -2

drivers/infiniband/core/verbs.c

reviewed

··· 147 147 case IB_RATE_50_GBPS: return 20; 148 148 case IB_RATE_400_GBPS: return 160; 149 149 case IB_RATE_600_GBPS: return 240; 150 150 + case IB_RATE_800_GBPS: return 320; 150 151 default: return -1; 151 152 } 152 153 } ··· 177 176 case 20: return IB_RATE_50_GBPS; 178 177 case 160: return IB_RATE_400_GBPS; 179 178 case 240: return IB_RATE_600_GBPS; 179 179 + case 320: return IB_RATE_800_GBPS; 180 180 default: return IB_RATE_PORT_CURRENT; 181 181 } 182 182 } ··· 207 205 case IB_RATE_50_GBPS: return 53125; 208 206 case IB_RATE_400_GBPS: return 425000; 209 207 case IB_RATE_600_GBPS: return 637500; 208 208 + case IB_RATE_800_GBPS: return 850000; 210 209 default: return -1; 211 210 } 212 211 } ··· 369 366 EXPORT_SYMBOL(rdma_copy_ah_attr); 370 367 371 368 /** 372 372 - * rdma_replace_ah_attr - Replace valid ah_attr with new new one. 369 369 + * rdma_replace_ah_attr - Replace valid ah_attr with new one. 373 370 * @old: Pointer to existing ah_attr which needs to be replaced. 374 371 * old is assumed to be valid or zero'd 375 372 * @new: Pointer to the new ah_attr. ··· 747 744 748 745 /* Resolve destination mac address and hop limit for unicast destination 749 746 * GID entry, considering the source GID entry as well. 750 750 - * ah_attribute must have have valid port_num, sgid_index. 747 747 + * ah_attribute must have valid port_num, sgid_index. 751 748 */ 752 749 static int ib_resolve_unicast_gid_dmac(struct ib_device *device, 753 750 struct rdma_ah_attr *ah_attr)

+159 -14

drivers/infiniband/hw/bnxt_re/main.c

reviewed

··· 970 970 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event, 971 971 struct bnxt_re_qp *qp) 972 972 { 973 973 + struct bnxt_re_srq *srq = container_of(qp->qplib_qp.srq, struct bnxt_re_srq, 974 974 + qplib_srq); 975 975 + struct creq_qp_error_notification *err_event; 973 976 struct ib_event event = {}; 974 977 unsigned int flags; 975 978 ··· 983 980 bnxt_re_unlock_cqs(qp, flags); 984 981 } 985 982 986 986 - if (qp->qplib_qp.srq) { 987 987 - event.device = &qp->rdev->ibdev; 988 988 - event.element.qp = &qp->ib_qp; 989 989 - event.event = IB_EVENT_QP_LAST_WQE_REACHED; 983 983 + event.device = &qp->rdev->ibdev; 984 984 + event.element.qp = &qp->ib_qp; 985 985 + event.event = IB_EVENT_QP_FATAL; 986 986 + 987 987 + err_event = (struct creq_qp_error_notification *)qp_event; 988 988 + 989 989 + switch (err_event->req_err_state_reason) { 990 990 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR: 991 991 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT: 992 992 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT: 993 993 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2: 994 994 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3: 995 995 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP: 996 996 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND: 997 997 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG: 998 998 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE: 999 999 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR: 1000 1000 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR: 1001 1001 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR: 1002 1002 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR: 1003 1003 + event.event = IB_EVENT_QP_ACCESS_ERR; 1004 1004 + break; 1005 1005 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1: 1006 1006 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4: 1007 1007 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH: 1008 1008 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR: 1009 1009 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR: 1010 1010 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR: 1011 1011 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR: 1012 1012 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR: 1013 1013 + event.event = IB_EVENT_QP_REQ_ERR; 1014 1014 + break; 1015 1015 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR: 1016 1016 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR: 1017 1017 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR: 1018 1018 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR: 1019 1019 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR: 1020 1020 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR: 1021 1021 + case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR: 1022 1022 + event.event = IB_EVENT_QP_FATAL; 1023 1023 + break; 1024 1024 + 1025 1025 + default: 1026 1026 + break; 990 1027 } 991 1028 992 992 - if (event.device && qp->ib_qp.event_handler) 1029 1029 + switch (err_event->res_err_state_reason) { 1030 1030 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX: 1031 1031 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH: 1032 1032 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT: 1033 1033 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY: 1034 1034 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR: 1035 1035 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION: 1036 1036 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR: 1037 1037 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY: 1038 1038 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR: 1039 1039 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION: 1040 1040 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR: 1041 1041 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC: 1042 1042 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND: 1043 1043 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY: 1044 1044 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR: 1045 1045 + event.event = IB_EVENT_QP_ACCESS_ERR; 1046 1046 + break; 1047 1047 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE: 1048 1048 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR: 1049 1049 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE: 1050 1050 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE: 1051 1051 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR: 1052 1052 + event.event = IB_EVENT_QP_REQ_ERR; 1053 1053 + break; 1054 1054 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW: 1055 1055 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR: 1056 1056 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR: 1057 1057 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR: 1058 1058 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR: 1059 1059 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR: 1060 1060 + event.event = IB_EVENT_QP_FATAL; 1061 1061 + break; 1062 1062 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR: 1063 1063 + case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR: 1064 1064 + if (srq) 1065 1065 + event.event = IB_EVENT_SRQ_ERR; 1066 1066 + break; 1067 1067 + default: 1068 1068 + break; 1069 1069 + } 1070 1070 + 1071 1071 + if (err_event->res_err_state_reason || err_event->req_err_state_reason) { 1072 1072 + ibdev_dbg(&qp->rdev->ibdev, 1073 1073 + "%s %s qp_id: %d cons (%d %d) req (%d %d) res (%d %d)\n", 1074 1074 + __func__, rdma_is_kernel_res(&qp->ib_qp.res) ? "kernel" : "user", 1075 1075 + qp->qplib_qp.id, 1076 1076 + err_event->sq_cons_idx, 1077 1077 + err_event->rq_cons_idx, 1078 1078 + err_event->req_slow_path_state, 1079 1079 + err_event->req_err_state_reason, 1080 1080 + err_event->res_slow_path_state, 1081 1081 + err_event->res_err_state_reason); 1082 1082 + } else { 1083 1083 + if (srq) 1084 1084 + event.event = IB_EVENT_QP_LAST_WQE_REACHED; 1085 1085 + } 1086 1086 + 1087 1087 + if (event.event == IB_EVENT_SRQ_ERR && srq->ib_srq.event_handler) { 1088 1088 + (*srq->ib_srq.event_handler)(&event, 1089 1089 + srq->ib_srq.srq_context); 1090 1090 + } else if (event.device && qp->ib_qp.event_handler) { 993 1091 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context); 1092 1092 + } 1093 1093 + 1094 1094 + return 0; 1095 1095 + } 1096 1096 + 1097 1097 + static int bnxt_re_handle_cq_async_error(void *event, struct bnxt_re_cq *cq) 1098 1098 + { 1099 1099 + struct creq_cq_error_notification *cqerr; 1100 1100 + struct ib_event ibevent = {}; 1101 1101 + 1102 1102 + cqerr = event; 1103 1103 + switch (cqerr->cq_err_reason) { 1104 1104 + case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR: 1105 1105 + case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR: 1106 1106 + case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR: 1107 1107 + case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR: 1108 1108 + case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR: 1109 1109 + case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR: 1110 1110 + ibevent.event = IB_EVENT_CQ_ERR; 1111 1111 + break; 1112 1112 + default: 1113 1113 + break; 1114 1114 + } 1115 1115 + 1116 1116 + if (ibevent.event == IB_EVENT_CQ_ERR && cq->ib_cq.event_handler) { 1117 1117 + ibevent.element.cq = &cq->ib_cq; 1118 1118 + ibevent.device = &cq->rdev->ibdev; 1119 1119 + 1120 1120 + ibdev_dbg(&cq->rdev->ibdev, 1121 1121 + "%s err reason %d\n", __func__, cqerr->cq_err_reason); 1122 1122 + cq->ib_cq.event_handler(&ibevent, cq->ib_cq.cq_context); 1123 1123 + } 994 1124 995 1125 return 0; 996 1126 } ··· 1131 995 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async, 1132 996 void *obj) 1133 997 { 998 998 + struct bnxt_qplib_qp *lib_qp; 999 999 + struct bnxt_qplib_cq *lib_cq; 1000 1000 + struct bnxt_re_qp *qp; 1001 1001 + struct bnxt_re_cq *cq; 1134 1002 int rc = 0; 1135 1003 u8 event; 1136 1004 ··· 1142 1002 return rc; /* QP was already dead, still return success */ 1143 1003 1144 1004 event = affi_async->event; 1145 1145 - if (event == CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION) { 1146 1146 - struct bnxt_qplib_qp *lib_qp = obj; 1147 1147 - struct bnxt_re_qp *qp = container_of(lib_qp, struct bnxt_re_qp, 1148 1148 - qplib_qp); 1005 1005 + switch (event) { 1006 1006 + case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION: 1007 1007 + lib_qp = obj; 1008 1008 + qp = container_of(lib_qp, struct bnxt_re_qp, qplib_qp); 1149 1009 rc = bnxt_re_handle_qp_async_event(affi_async, qp); 1010 1010 + break; 1011 1011 + case CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION: 1012 1012 + lib_cq = obj; 1013 1013 + cq = container_of(lib_cq, struct bnxt_re_cq, qplib_cq); 1014 1014 + rc = bnxt_re_handle_cq_async_error(affi_async, cq); 1015 1015 + break; 1016 1016 + default: 1017 1017 + rc = -EINVAL; 1150 1018 } 1151 1019 return rc; 1152 1020 } ··· 1188 1040 1189 1041 ib_event.device = &srq->rdev->ibdev; 1190 1042 ib_event.element.srq = &srq->ib_srq; 1191 1191 - if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT) 1192 1192 - ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED; 1193 1193 - else 1194 1194 - ib_event.event = IB_EVENT_SRQ_ERR; 1195 1043 1196 1044 if (srq->ib_srq.event_handler) { 1197 1197 - /* Lock event_handler? */ 1045 1045 + if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT) 1046 1046 + ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED; 1198 1047 (*srq->ib_srq.event_handler)(&ib_event, 1199 1048 srq->ib_srq.srq_context); 1200 1049 }

+1 -1

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 3 3 #ifndef __QPLIB_TLV_H__ 4 4 #define __QPLIB_TLV_H__

+58

drivers/infiniband/hw/bnxt_re/roce_hsi.h

reviewed

··· 2919 2919 u8 status; 2920 2920 u8 req_slow_path_state; 2921 2921 u8 req_err_state_reason; 2922 2922 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR 0X0UL 2923 2923 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR 0X1UL 2924 2924 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT 0X2UL 2925 2925 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT 0X3UL 2926 2926 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1 0X4UL 2927 2927 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2 0X5UL 2928 2928 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3 0X6UL 2929 2929 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4 0X7UL 2930 2930 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR 0X8UL 2931 2931 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR 0X9UL 2932 2932 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH 0XAUL 2933 2933 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP 0XBUL 2934 2934 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND 0XCUL 2935 2935 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG 0XDUL 2936 2936 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE 0XEUL 2937 2937 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR 0XFUL 2938 2938 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR 0X10UL 2939 2939 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR 0X11UL 2940 2940 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR 0X12UL 2941 2941 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR 0X13UL 2942 2942 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR 0X14UL 2943 2943 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR 0X15UL 2944 2944 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR 0X16UL 2945 2945 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR 0X17UL 2946 2946 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR 0X18UL 2947 2947 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR 0X19UL 2948 2948 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR 0X1AUL 2949 2949 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR 0X1BUL 2950 2950 + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR 0X1CUL 2922 2951 __le32 xid; 2923 2952 u8 v; 2924 2953 #define CREQ_QP_ERROR_NOTIFICATION_V 0x1UL ··· 2957 2928 CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 2958 2929 u8 res_slow_path_state; 2959 2930 u8 res_err_state_reason; 2931 2931 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR 0x0UL 2932 2932 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX 0x1UL 2933 2933 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH 0x2UL 2934 2934 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE 0x3UL 2935 2935 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR 0x4UL 2936 2936 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT 0x5UL 2937 2937 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY 0x6UL 2938 2938 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR 0x7UL 2939 2939 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION 0x8UL 2940 2940 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR 0x9UL 2941 2941 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY 0xaUL 2942 2942 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR 0xbUL 2943 2943 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION 0xcUL 2944 2944 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR 0xdUL 2945 2945 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW 0xeUL 2946 2946 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE 0xfUL 2947 2947 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC 0x10UL 2948 2948 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE 0x11UL 2949 2949 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR 0x12UL 2950 2950 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR 0x13UL 2951 2951 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR 0x14UL 2952 2952 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY 0x15UL 2953 2953 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR 0x16UL 2954 2954 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR 0x17UL 2955 2955 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR 0x18UL 2956 2956 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR 0x19UL 2957 2957 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR 0x1bUL 2958 2958 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR 0x1cUL 2959 2959 + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND 0x1dUL 2960 2960 __le16 sq_cons_idx; 2961 2961 __le16 rq_cons_idx; 2962 2962 };

+1 -1

drivers/infiniband/hw/hfi1/affinity.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2020 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/affinity.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2020 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/aspm.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015-2017 Intel Corporation. 4 4 */

+6 -5

drivers/infiniband/hw/hfi1/chip.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2020 Intel Corporation. 4 4 * Copyright(c) 2021 Cornelis Networks. ··· 5334 5334 static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source) 5335 5335 { 5336 5336 if (source < ARRAY_SIZE(cce_misc_names)) 5337 5337 - strncpy(buf, cce_misc_names[source], bsize); 5337 5337 + strscpy_pad(buf, cce_misc_names[source], bsize); 5338 5338 else 5339 5339 snprintf(buf, bsize, "Reserved%u", 5340 5340 source + IS_GENERAL_ERR_START); ··· 5374 5374 static char *is_various_name(char *buf, size_t bsize, unsigned int source) 5375 5375 { 5376 5376 if (source < ARRAY_SIZE(various_names)) 5377 5377 - strncpy(buf, various_names[source], bsize); 5377 5377 + strscpy_pad(buf, various_names[source], bsize); 5378 5378 else 5379 5379 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START); 5380 5380 return buf; ··· 13185 13185 { 13186 13186 u64 reg; 13187 13187 u16 idx = src / BITS_PER_REGISTER; 13188 13188 + unsigned long flags; 13188 13189 13189 13189 - spin_lock(&dd->irq_src_lock); 13190 13190 + spin_lock_irqsave(&dd->irq_src_lock, flags); 13190 13191 reg = read_csr(dd, CCE_INT_MASK + (8 * idx)); 13191 13192 if (set) 13192 13193 reg |= bits; 13193 13194 else 13194 13195 reg &= ~bits; 13195 13196 write_csr(dd, CCE_INT_MASK + (8 * idx), reg); 13196 13196 - spin_unlock(&dd->irq_src_lock); 13197 13197 + spin_unlock_irqrestore(&dd->irq_src_lock, flags); 13197 13198 } 13198 13199 13199 13200 /**

+1 -1

drivers/infiniband/hw/hfi1/chip.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2020 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/chip_registers.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/common.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2020 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/debugfs.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015-2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/debugfs.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015, 2016, 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/device.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/device.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/driver.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015-2020 Intel Corporation. 4 4 * Copyright(c) 2021 Cornelis Networks.

+2 -2

drivers/infiniband/hw/hfi1/efivar.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */ ··· 112 112 unsigned long *size, void **return_data) 113 113 { 114 114 char prefix_name[64]; 115 115 - char name[64]; 115 115 + char name[128]; 116 116 int result; 117 117 118 118 /* create a common prefix */

+1 -1

drivers/infiniband/hw/hfi1/efivar.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/eprom.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/eprom.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/exp_rcv.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/exp_rcv.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/fault.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/fault.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/file_ops.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2020 Cornelis Networks, Inc. 4 4 * Copyright(c) 2015-2020 Intel Corporation.

+1 -1

drivers/infiniband/hw/hfi1/firmware.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/hfi.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2020-2023 Cornelis Networks, Inc. 4 4 * Copyright(c) 2015-2020 Intel Corporation.

+1 -2

drivers/infiniband/hw/hfi1/init.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2020 Intel Corporation. 4 4 * Copyright(c) 2021 Cornelis Networks. ··· 1027 1027 msix_clean_up_interrupts(dd); 1028 1028 1029 1029 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1030 1030 - ppd = dd->pport + pidx; 1031 1030 for (i = 0; i < dd->num_rcv_contexts; i++) { 1032 1031 rcd = hfi1_rcd_get_by_index(dd, i); 1033 1032 hfi1_rcvctrl(dd, HFI1_RCVCTRL_TAILUPD_DIS |

+1 -1

drivers/infiniband/hw/hfi1/intr.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/iowait.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/ipoib_tx.c

reviewed

··· 217 217 ret = sdma_txadd_page(dd, 218 218 txreq, 219 219 skb_frag_page(frag), 220 220 - frag->bv_offset, 220 220 + skb_frag_off(frag), 221 221 skb_frag_size(frag), 222 222 NULL, NULL, NULL); 223 223 if (unlikely(ret))

+1 -1

drivers/infiniband/hw/hfi1/mad.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015-2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/mad.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/mmu_rb.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2020 Cornelis Networks, Inc. 4 4 * Copyright(c) 2016 - 2017 Intel Corporation.

+1 -1

drivers/infiniband/hw/hfi1/mmu_rb.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2020 Cornelis Networks, Inc. 4 4 * Copyright(c) 2016 Intel Corporation.

+1 -1

drivers/infiniband/hw/hfi1/opa_compat.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+3 -8

drivers/infiniband/hw/hfi1/pcie.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2019 Intel Corporation. 4 4 */ 5 5 6 6 + #include <linux/bitfield.h> 6 7 #include <linux/pci.h> 7 8 #include <linux/io.h> 8 9 #include <linux/delay.h> ··· 211 210 return speed; 212 211 } 213 212 214 214 - /* return the PCIe link speed from the given link status */ 215 215 - static u32 extract_width(u16 linkstat) 216 216 - { 217 217 - return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; 218 218 - } 219 219 - 220 213 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ 221 214 static void update_lbus_info(struct hfi1_devdata *dd) 222 215 { ··· 223 228 return; 224 229 } 225 230 226 226 - dd->lbus_width = extract_width(linkstat); 231 231 + dd->lbus_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, linkstat); 227 232 dd->lbus_speed = extract_speed(linkstat); 228 233 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 229 234 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width);

+1 -1

drivers/infiniband/hw/hfi1/pio.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015-2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/pio.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015-2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/pio_copy.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/platform.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/platform.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/qp.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2020 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/qp.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/qsfp.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/qsfp.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/rc.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/ruc.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/sdma.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/sdma.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/sdma_txreq.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/sysfs.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015-2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/trace.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2020 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/trace.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/trace_ctxts.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2020 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/trace_dbg.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/trace_ibhdrs.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/trace_misc.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015, 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/trace_mmu.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/trace_rc.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015, 2016, 2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/trace_rx.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/trace_tx.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/uc.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/ud.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2019 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/user_exp_rcv.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2020 Cornelis Networks, Inc. 4 4 * Copyright(c) 2015-2018 Intel Corporation.

+2 -2

drivers/infiniband/hw/hfi1/user_exp_rcv.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2020 - Cornelis Networks, Inc. 4 4 * Copyright(c) 2015 - 2017 Intel Corporation. ··· 36 36 dma_addr_t dma_addr; 37 37 bool freed; 38 38 unsigned int npages; 39 39 - struct page *pages[]; 39 39 + struct page *pages[] __counted_by(npages); 40 40 }; 41 41 42 42 static inline int num_user_pages(unsigned long addr,

+1 -1

drivers/infiniband/hw/hfi1/user_pages.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015-2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/user_sdma.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2020 - 2023 Cornelis Networks, Inc. 4 4 * Copyright(c) 2015 - 2018 Intel Corporation.

+1 -1

drivers/infiniband/hw/hfi1/user_sdma.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2023 - Cornelis Networks, Inc. 4 4 * Copyright(c) 2015 - 2018 Intel Corporation.

+1 -1

drivers/infiniband/hw/hfi1/verbs.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2015 - 2020 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/verbs.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2015 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/verbs_txreq.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/verbs_txreq.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/vnic.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2017 - 2020 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/vnic_main.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2017 - 2020 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/hw/hfi1/vnic_sdma.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2017 - 2018 Intel Corporation. 4 4 */

+12 -1

drivers/infiniband/hw/hns/hns_roce_ah.c

reviewed

··· 33 33 #include <linux/pci.h> 34 34 #include <rdma/ib_addr.h> 35 35 #include <rdma/ib_cache.h> 36 36 + #include "hnae3.h" 36 37 #include "hns_roce_device.h" 38 38 + #include "hns_roce_hw_v2.h" 37 39 38 40 static inline u16 get_ah_udp_sport(const struct rdma_ah_attr *ah_attr) 39 41 { ··· 59 57 struct hns_roce_dev *hr_dev = to_hr_dev(ibah->device); 60 58 struct hns_roce_ah *ah = to_hr_ah(ibah); 61 59 int ret = 0; 60 60 + u32 max_sl; 62 61 63 62 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 && udata) 64 63 return -EOPNOTSUPP; ··· 73 70 ah->av.hop_limit = grh->hop_limit; 74 71 ah->av.flowlabel = grh->flow_label; 75 72 ah->av.udp_sport = get_ah_udp_sport(ah_attr); 76 76 - ah->av.sl = rdma_ah_get_sl(ah_attr); 77 73 ah->av.tclass = get_tclass(grh); 74 74 + 75 75 + ah->av.sl = rdma_ah_get_sl(ah_attr); 76 76 + max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 77 77 + if (unlikely(ah->av.sl > max_sl)) { 78 78 + ibdev_err_ratelimited(&hr_dev->ib_dev, 79 79 + "failed to set sl, sl (%u) shouldn't be larger than %u.\n", 80 80 + ah->av.sl, max_sl); 81 81 + return -EINVAL; 82 82 + } 78 83 79 84 memcpy(ah->av.dgid, grh->dgid.raw, HNS_ROCE_GID_SIZE); 80 85 memcpy(ah->av.mac, ah_attr->roce.dmac, ETH_ALEN);

+6

drivers/infiniband/hw/hns/hns_roce_device.h

reviewed

··· 146 146 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), 147 147 HNS_ROCE_CAP_FLAG_STASH = BIT(17), 148 148 HNS_ROCE_CAP_FLAG_CQE_INLINE = BIT(19), 149 149 + HNS_ROCE_CAP_FLAG_SRQ_RECORD_DB = BIT(22), 149 150 }; 150 151 151 152 #define HNS_ROCE_DB_TYPE_COUNT 2 ··· 454 453 spinlock_t lock; 455 454 struct mutex mutex; 456 455 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 456 456 + struct hns_roce_db rdb; 457 457 + u32 cap_flags; 457 458 }; 458 459 459 460 struct hns_roce_uar_table { ··· 911 908 int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer); 912 909 int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer); 913 910 int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer); 911 911 + int (*query_srqc)(struct hns_roce_dev *hr_dev, u32 srqn, void *buffer); 914 912 int (*query_hw_counter)(struct hns_roce_dev *hr_dev, 915 913 u64 *stats, u32 port, int *hw_counters); 916 914 const struct ib_device_ops *hns_roce_dev_ops; ··· 1243 1239 int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp); 1244 1240 int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr); 1245 1241 int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr); 1242 1242 + int hns_roce_fill_res_srq_entry(struct sk_buff *msg, struct ib_srq *ib_srq); 1243 1243 + int hns_roce_fill_res_srq_entry_raw(struct sk_buff *msg, struct ib_srq *ib_srq); 1246 1244 struct hns_user_mmap_entry * 1247 1245 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, 1248 1246 size_t length,

+67 -23

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

reviewed

··· 270 270 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 271 271 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 272 272 273 273 - if (len > qp->max_inline_data || len > mtu) { 273 273 + if (mtu < 0 || len > qp->max_inline_data || len > mtu) { 274 274 ibdev_err(&hr_dev->ib_dev, 275 275 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 276 276 len, qp->max_inline_data, mtu); ··· 941 941 idx_que->head++; 942 942 } 943 943 944 944 - static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq) 944 944 + static void update_srq_db(struct hns_roce_srq *srq) 945 945 { 946 946 - hr_reg_write(db, DB_TAG, srq->srqn); 947 947 - hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 948 948 - hr_reg_write(db, DB_PI, srq->idx_que.head); 946 946 + struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device); 947 947 + struct hns_roce_v2_db db; 948 948 + 949 949 + hr_reg_write(&db, DB_TAG, srq->srqn); 950 950 + hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 951 951 + hr_reg_write(&db, DB_PI, srq->idx_que.head); 952 952 + 953 953 + hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg); 949 954 } 950 955 951 956 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 952 957 const struct ib_recv_wr *wr, 953 958 const struct ib_recv_wr **bad_wr) 954 959 { 955 955 - struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 956 960 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 957 957 - struct hns_roce_v2_db srq_db; 958 961 unsigned long flags; 959 962 int ret = 0; 960 963 u32 max_sge; ··· 988 985 } 989 986 990 987 if (likely(nreq)) { 991 991 - update_srq_db(&srq_db, srq); 992 992 - 993 993 - hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg); 988 988 + if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) 989 989 + *srq->rdb.db_record = srq->idx_que.head & 990 990 + V2_DB_PRODUCER_IDX_M; 991 991 + else 992 992 + update_srq_db(srq); 994 993 } 995 994 996 995 spin_unlock_irqrestore(&srq->lock, flags); ··· 4730 4725 { 4731 4726 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4732 4727 4728 4728 + if (ibqp->qp_type == IB_QPT_UD) 4729 4729 + hr_dev->caps.cong_type = CONG_TYPE_DCQCN; 4730 4730 + 4733 4731 /* different congestion types match different configurations */ 4734 4732 switch (hr_dev->caps.cong_type) { 4735 4733 case CONG_TYPE_DCQCN: ··· 4829 4821 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4830 4822 struct ib_device *ibdev = &hr_dev->ib_dev; 4831 4823 const struct ib_gid_attr *gid_attr = NULL; 4824 4824 + u8 sl = rdma_ah_get_sl(&attr->ah_attr); 4832 4825 int is_roce_protocol; 4833 4826 u16 vlan_id = 0xffff; 4834 4827 bool is_udp = false; 4828 4828 + u32 max_sl; 4835 4829 u8 ib_port; 4836 4830 u8 hr_port; 4837 4831 int ret; 4832 4832 + 4833 4833 + max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 4834 4834 + if (unlikely(sl > max_sl)) { 4835 4835 + ibdev_err_ratelimited(ibdev, 4836 4836 + "failed to fill QPC, sl (%u) shouldn't be larger than %u.\n", 4837 4837 + sl, max_sl); 4838 4838 + return -EINVAL; 4839 4839 + } 4838 4840 4839 4841 /* 4840 4842 * If free_mr_en of qp is set, it means that this qp comes from ··· 4852 4834 * In the loopback scenario, only sl needs to be set. 4853 4835 */ 4854 4836 if (hr_qp->free_mr_en) { 4855 4855 - hr_reg_write(context, QPC_SL, rdma_ah_get_sl(&attr->ah_attr)); 4837 4837 + hr_reg_write(context, QPC_SL, sl); 4856 4838 hr_reg_clear(qpc_mask, QPC_SL); 4857 4857 - hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4839 4839 + hr_qp->sl = sl; 4858 4840 return 0; 4859 4841 } 4860 4842 ··· 4921 4903 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4922 4904 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4923 4905 4924 4924 - hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4925 4925 - if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) { 4926 4926 - ibdev_err(ibdev, 4927 4927 - "failed to fill QPC, sl (%u) shouldn't be larger than %d.\n", 4928 4928 - hr_qp->sl, MAX_SERVICE_LEVEL); 4929 4929 - return -EINVAL; 4930 4930 - } 4931 4931 - 4906 4906 + hr_qp->sl = sl; 4932 4907 hr_reg_write(context, QPC_SL, hr_qp->sl); 4933 4908 hr_reg_clear(qpc_mask, QPC_SL); 4934 4909 ··· 5283 5272 return ret; 5284 5273 } 5285 5274 5275 5275 + static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn, 5276 5276 + void *buffer) 5277 5277 + { 5278 5278 + struct hns_roce_srq_context *context; 5279 5279 + struct hns_roce_cmd_mailbox *mailbox; 5280 5280 + int ret; 5281 5281 + 5282 5282 + mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5283 5283 + if (IS_ERR(mailbox)) 5284 5284 + return PTR_ERR(mailbox); 5285 5285 + 5286 5286 + context = mailbox->buf; 5287 5287 + ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC, 5288 5288 + srqn); 5289 5289 + if (ret) 5290 5290 + goto out; 5291 5291 + 5292 5292 + memcpy(buffer, context, sizeof(*context)); 5293 5293 + 5294 5294 + out: 5295 5295 + hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5296 5296 + return ret; 5297 5297 + } 5298 5298 + 5286 5299 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5287 5300 struct hns_roce_v2_qp_context *context) 5288 5301 { ··· 5641 5606 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5642 5607 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5643 5608 5609 5609 + if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) { 5610 5610 + hr_reg_enable(ctx, SRQC_DB_RECORD_EN); 5611 5611 + hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L, 5612 5612 + lower_32_bits(srq->rdb.dma) >> 1); 5613 5613 + hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H, 5614 5614 + upper_32_bits(srq->rdb.dma)); 5615 5615 + } 5616 5616 + 5644 5617 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5645 5618 } 5646 5619 ··· 5847 5804 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5848 5805 break; 5849 5806 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5850 5850 - ibdev_warn(ibdev, "send queue drained.\n"); 5807 5807 + ibdev_dbg(ibdev, "send queue drained.\n"); 5851 5808 break; 5852 5809 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5853 5810 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", ··· 5862 5819 irq_work->queue_num, irq_work->sub_type); 5863 5820 break; 5864 5821 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5865 5865 - ibdev_warn(ibdev, "SRQ limit reach.\n"); 5822 5822 + ibdev_dbg(ibdev, "SRQ limit reach.\n"); 5866 5823 break; 5867 5824 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5868 5868 - ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5825 5825 + ibdev_dbg(ibdev, "SRQ last wqe reach.\n"); 5869 5826 break; 5870 5827 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5871 5828 ibdev_err(ibdev, "SRQ catas error.\n"); ··· 6675 6632 .query_cqc = hns_roce_v2_query_cqc, 6676 6633 .query_qpc = hns_roce_v2_query_qpc, 6677 6634 .query_mpt = hns_roce_v2_query_mpt, 6635 6635 + .query_srqc = hns_roce_v2_query_srqc, 6678 6636 .query_hw_counter = hns_roce_hw_v2_query_counter, 6679 6637 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6680 6638 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,

+12 -12

drivers/infiniband/hw/hns/hns_roce_main.c

reviewed

··· 547 547 struct ib_device *device, u32 port_num) 548 548 { 549 549 struct hns_roce_dev *hr_dev = to_hr_dev(device); 550 550 - u32 port = port_num - 1; 551 550 552 552 - if (port > hr_dev->caps.num_ports) { 551 551 + if (port_num > hr_dev->caps.num_ports) { 553 552 ibdev_err(device, "invalid port num.\n"); 554 553 return NULL; 555 554 } 556 556 - 557 557 - if (hr_dev->pci_dev->revision <= PCI_REVISION_ID_HIP08 || 558 558 - hr_dev->is_vf) 559 559 - return NULL; 560 555 561 556 return rdma_alloc_hw_stats_struct(hns_roce_port_stats_descs, 562 557 ARRAY_SIZE(hns_roce_port_stats_descs), ··· 571 576 572 577 if (port > hr_dev->caps.num_ports) 573 578 return -EINVAL; 574 574 - 575 575 - if (hr_dev->pci_dev->revision <= PCI_REVISION_ID_HIP08 || 576 576 - hr_dev->is_vf) 577 577 - return -EOPNOTSUPP; 578 579 579 580 ret = hr_dev->hw->query_hw_counter(hr_dev, stats->value, port, 580 581 &num_counters); ··· 625 634 .query_pkey = hns_roce_query_pkey, 626 635 .query_port = hns_roce_query_port, 627 636 .reg_user_mr = hns_roce_reg_user_mr, 628 628 - .alloc_hw_port_stats = hns_roce_alloc_hw_port_stats, 629 629 - .get_hw_stats = hns_roce_get_hw_stats, 630 637 631 638 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah), 632 639 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq), 633 640 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd), 634 641 INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp), 635 642 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext), 643 643 + }; 644 644 + 645 645 + static const struct ib_device_ops hns_roce_dev_hw_stats_ops = { 646 646 + .alloc_hw_port_stats = hns_roce_alloc_hw_port_stats, 647 647 + .get_hw_stats = hns_roce_get_hw_stats, 636 648 }; 637 649 638 650 static const struct ib_device_ops hns_roce_dev_mr_ops = { ··· 675 681 .fill_res_qp_entry_raw = hns_roce_fill_res_qp_entry_raw, 676 682 .fill_res_mr_entry = hns_roce_fill_res_mr_entry, 677 683 .fill_res_mr_entry_raw = hns_roce_fill_res_mr_entry_raw, 684 684 + .fill_res_srq_entry = hns_roce_fill_res_srq_entry, 685 685 + .fill_res_srq_entry_raw = hns_roce_fill_res_srq_entry_raw, 678 686 }; 679 687 680 688 static int hns_roce_register_device(struct hns_roce_dev *hr_dev) ··· 715 719 716 720 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 717 721 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops); 722 722 + 723 723 + if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09 && 724 724 + !hr_dev->is_vf) 725 725 + ib_set_device_ops(ib_dev, &hns_roce_dev_hw_stats_ops); 718 726 719 727 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); 720 728 ib_set_device_ops(ib_dev, &hns_roce_dev_ops);

+1 -1

drivers/infiniband/hw/hns/hns_roce_qp.c

reviewed

··· 1064 1064 { 1065 1065 struct hns_roce_ib_create_qp_resp resp = {}; 1066 1066 struct ib_device *ibdev = &hr_dev->ib_dev; 1067 1067 - struct hns_roce_ib_create_qp ucmd; 1067 1067 + struct hns_roce_ib_create_qp ucmd = {}; 1068 1068 int ret; 1069 1069 1070 1070 mutex_init(&hr_qp->mutex);

+49

drivers/infiniband/hw/hns/hns_roce_restrack.c

reviewed

··· 160 160 161 161 return ret; 162 162 } 163 163 + 164 164 + int hns_roce_fill_res_srq_entry(struct sk_buff *msg, struct ib_srq *ib_srq) 165 165 + { 166 166 + struct hns_roce_srq *hr_srq = to_hr_srq(ib_srq); 167 167 + struct nlattr *table_attr; 168 168 + 169 169 + table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER); 170 170 + if (!table_attr) 171 171 + return -EMSGSIZE; 172 172 + 173 173 + if (rdma_nl_put_driver_u32_hex(msg, "srqn", hr_srq->srqn)) 174 174 + goto err; 175 175 + 176 176 + if (rdma_nl_put_driver_u32_hex(msg, "wqe_cnt", hr_srq->wqe_cnt)) 177 177 + goto err; 178 178 + 179 179 + if (rdma_nl_put_driver_u32_hex(msg, "max_gs", hr_srq->max_gs)) 180 180 + goto err; 181 181 + 182 182 + if (rdma_nl_put_driver_u32_hex(msg, "xrcdn", hr_srq->xrcdn)) 183 183 + goto err; 184 184 + 185 185 + nla_nest_end(msg, table_attr); 186 186 + 187 187 + return 0; 188 188 + 189 189 + err: 190 190 + nla_nest_cancel(msg, table_attr); 191 191 + return -EMSGSIZE; 192 192 + } 193 193 + 194 194 + int hns_roce_fill_res_srq_entry_raw(struct sk_buff *msg, struct ib_srq *ib_srq) 195 195 + { 196 196 + struct hns_roce_dev *hr_dev = to_hr_dev(ib_srq->device); 197 197 + struct hns_roce_srq *hr_srq = to_hr_srq(ib_srq); 198 198 + struct hns_roce_srq_context context; 199 199 + int ret; 200 200 + 201 201 + if (!hr_dev->hw->query_srqc) 202 202 + return -EINVAL; 203 203 + 204 204 + ret = hr_dev->hw->query_srqc(hr_dev, hr_srq->srqn, &context); 205 205 + if (ret) 206 206 + return ret; 207 207 + 208 208 + ret = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, sizeof(context), &context); 209 209 + 210 210 + return ret; 211 211 + }

+83 -2

drivers/infiniband/hw/hns/hns_roce_srq.c

reviewed

··· 5 5 6 6 #include <linux/pci.h> 7 7 #include <rdma/ib_umem.h> 8 8 + #include <rdma/uverbs_ioctl.h> 8 9 #include "hns_roce_device.h" 9 10 #include "hns_roce_cmd.h" 10 11 #include "hns_roce_hem.h" ··· 388 387 free_srq_idx(hr_dev, srq); 389 388 } 390 389 390 390 + static int get_srq_ucmd(struct hns_roce_srq *srq, struct ib_udata *udata, 391 391 + struct hns_roce_ib_create_srq *ucmd) 392 392 + { 393 393 + struct ib_device *ibdev = srq->ibsrq.device; 394 394 + int ret; 395 395 + 396 396 + ret = ib_copy_from_udata(ucmd, udata, min(udata->inlen, sizeof(*ucmd))); 397 397 + if (ret) { 398 398 + ibdev_err(ibdev, "failed to copy SRQ udata, ret = %d.\n", ret); 399 399 + return ret; 400 400 + } 401 401 + 402 402 + return 0; 403 403 + } 404 404 + 405 405 + static void free_srq_db(struct hns_roce_dev *hr_dev, struct hns_roce_srq *srq, 406 406 + struct ib_udata *udata) 407 407 + { 408 408 + struct hns_roce_ucontext *uctx; 409 409 + 410 410 + if (!(srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB)) 411 411 + return; 412 412 + 413 413 + srq->cap_flags &= ~HNS_ROCE_SRQ_CAP_RECORD_DB; 414 414 + if (udata) { 415 415 + uctx = rdma_udata_to_drv_context(udata, 416 416 + struct hns_roce_ucontext, 417 417 + ibucontext); 418 418 + hns_roce_db_unmap_user(uctx, &srq->rdb); 419 419 + } else { 420 420 + hns_roce_free_db(hr_dev, &srq->rdb); 421 421 + } 422 422 + } 423 423 + 424 424 + static int alloc_srq_db(struct hns_roce_dev *hr_dev, struct hns_roce_srq *srq, 425 425 + struct ib_udata *udata, 426 426 + struct hns_roce_ib_create_srq_resp *resp) 427 427 + { 428 428 + struct hns_roce_ib_create_srq ucmd = {}; 429 429 + struct hns_roce_ucontext *uctx; 430 430 + int ret; 431 431 + 432 432 + if (udata) { 433 433 + ret = get_srq_ucmd(srq, udata, &ucmd); 434 434 + if (ret) 435 435 + return ret; 436 436 + 437 437 + if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ_RECORD_DB) && 438 438 + (ucmd.req_cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB)) { 439 439 + uctx = rdma_udata_to_drv_context(udata, 440 440 + struct hns_roce_ucontext, ibucontext); 441 441 + ret = hns_roce_db_map_user(uctx, ucmd.db_addr, 442 442 + &srq->rdb); 443 443 + if (ret) 444 444 + return ret; 445 445 + 446 446 + srq->cap_flags |= HNS_ROCE_RSP_SRQ_CAP_RECORD_DB; 447 447 + } 448 448 + } else { 449 449 + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ_RECORD_DB) { 450 450 + ret = hns_roce_alloc_db(hr_dev, &srq->rdb, 1); 451 451 + if (ret) 452 452 + return ret; 453 453 + 454 454 + *srq->rdb.db_record = 0; 455 455 + srq->cap_flags |= HNS_ROCE_RSP_SRQ_CAP_RECORD_DB; 456 456 + } 457 457 + srq->db_reg = hr_dev->reg_base + SRQ_DB_REG; 458 458 + } 459 459 + 460 460 + return 0; 461 461 + } 462 462 + 391 463 int hns_roce_create_srq(struct ib_srq *ib_srq, 392 464 struct ib_srq_init_attr *init_attr, 393 465 struct ib_udata *udata) ··· 481 407 if (ret) 482 408 return ret; 483 409 484 484 - ret = alloc_srqn(hr_dev, srq); 410 410 + ret = alloc_srq_db(hr_dev, srq, udata, &resp); 485 411 if (ret) 486 412 goto err_srq_buf; 413 413 + 414 414 + ret = alloc_srqn(hr_dev, srq); 415 415 + if (ret) 416 416 + goto err_srq_db; 487 417 488 418 ret = alloc_srqc(hr_dev, srq); 489 419 if (ret) 490 420 goto err_srqn; 491 421 492 422 if (udata) { 423 423 + resp.cap_flags = srq->cap_flags; 493 424 resp.srqn = srq->srqn; 494 425 if (ib_copy_to_udata(udata, &resp, 495 426 min(udata->outlen, sizeof(resp)))) { ··· 503 424 } 504 425 } 505 426 506 506 - srq->db_reg = hr_dev->reg_base + SRQ_DB_REG; 507 427 srq->event = hns_roce_ib_srq_event; 508 428 refcount_set(&srq->refcount, 1); 509 429 init_completion(&srq->free); ··· 513 435 free_srqc(hr_dev, srq); 514 436 err_srqn: 515 437 free_srqn(hr_dev, srq); 438 438 + err_srq_db: 439 439 + free_srq_db(hr_dev, srq, udata); 516 440 err_srq_buf: 517 441 free_srq_buf(hr_dev, srq); 518 442 ··· 528 448 529 449 free_srqc(hr_dev, srq); 530 450 free_srqn(hr_dev, srq); 451 451 + free_srq_db(hr_dev, srq, udata); 531 452 free_srq_buf(hr_dev, srq); 532 453 return 0; 533 454 }

+1 -1

drivers/infiniband/hw/irdma/cm.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #include "main.h" 4 4 #include "trace.h"

+1 -1

drivers/infiniband/hw/irdma/cm.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #ifndef IRDMA_CM_H 4 4 #define IRDMA_CM_H

+1 -1

drivers/infiniband/hw/irdma/ctrl.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #include <linux/etherdevice.h> 4 4

+1 -1

drivers/infiniband/hw/irdma/defs.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #ifndef IRDMA_DEFS_H 4 4 #define IRDMA_DEFS_H

+1 -1

drivers/infiniband/hw/irdma/hmc.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #include "osdep.h" 4 4 #include "hmc.h"

+1 -1

drivers/infiniband/hw/irdma/hmc.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2015 - 2020 Intel Corporation */ 3 3 #ifndef IRDMA_HMC_H 4 4 #define IRDMA_HMC_H

+1 -1

drivers/infiniband/hw/irdma/hw.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #include "main.h" 4 4

+1 -1

drivers/infiniband/hw/irdma/i40iw_hw.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #include "osdep.h" 4 4 #include "type.h"

+1 -1

drivers/infiniband/hw/irdma/i40iw_hw.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #ifndef I40IW_HW_H 4 4 #define I40IW_HW_H

+2 -2

drivers/infiniband/hw/irdma/i40iw_if.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #include "main.h" 4 4 #include "i40iw_hw.h" ··· 186 186 aux_dev); 187 187 struct i40e_info *cdev_info = i40e_adev->ldev; 188 188 189 189 - strncpy(i40iw_client.name, "irdma", I40E_CLIENT_STR_LENGTH); 189 189 + strscpy_pad(i40iw_client.name, "irdma", I40E_CLIENT_STR_LENGTH); 190 190 i40e_client_device_register(cdev_info, &i40iw_client); 191 191 192 192 return 0;

+1 -1

drivers/infiniband/hw/irdma/icrdma_hw.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2017 - 2021 Intel Corporation */ 3 3 #include "osdep.h" 4 4 #include "type.h"

+1 -1

drivers/infiniband/hw/irdma/icrdma_hw.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2017 - 2021 Intel Corporation */ 3 3 #ifndef ICRDMA_HW_H 4 4 #define ICRDMA_HW_H

+1 -1

drivers/infiniband/hw/irdma/irdma.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2017 - 2021 Intel Corporation */ 3 3 #ifndef IRDMA_H 4 4 #define IRDMA_H

+1 -1

drivers/infiniband/hw/irdma/main.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #include "main.h" 4 4 #include "../../../net/ethernet/intel/ice/ice.h"

+1 -1

drivers/infiniband/hw/irdma/main.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #ifndef IRDMA_MAIN_H 4 4 #define IRDMA_MAIN_H

+1 -1

drivers/infiniband/hw/irdma/osdep.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #ifndef IRDMA_OSDEP_H 4 4 #define IRDMA_OSDEP_H

+1 -1

drivers/infiniband/hw/irdma/pble.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #include "osdep.h" 4 4 #include "hmc.h"

+1 -1

drivers/infiniband/hw/irdma/pble.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2015 - 2019 Intel Corporation */ 3 3 #ifndef IRDMA_PBLE_H 4 4 #define IRDMA_PBLE_H

+1 -1

drivers/infiniband/hw/irdma/protos.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2016 - 2021 Intel Corporation */ 3 3 #ifndef IRDMA_PROTOS_H 4 4 #define IRDMA_PROTOS_H

+1 -1

drivers/infiniband/hw/irdma/puda.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #include "osdep.h" 4 4 #include "hmc.h"

+1 -1

drivers/infiniband/hw/irdma/puda.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2015 - 2020 Intel Corporation */ 3 3 #ifndef IRDMA_PUDA_H 4 4 #define IRDMA_PUDA_H

+1 -1

drivers/infiniband/hw/irdma/trace.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2019 Intel Corporation */ 3 3 #define CREATE_TRACE_POINTS 4 4 #include "trace.h"

+1 -1

drivers/infiniband/hw/irdma/trace.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2019 Intel Corporation */ 3 3 #include "trace_cm.h"

+1 -1

drivers/infiniband/hw/irdma/trace_cm.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2019 - 2021 Intel Corporation */ 3 3 #if !defined(__TRACE_CM_H) || defined(TRACE_HEADER_MULTI_READ) 4 4 #define __TRACE_CM_H

+1 -1

drivers/infiniband/hw/irdma/type.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #ifndef IRDMA_TYPE_H 4 4 #define IRDMA_TYPE_H

+1 -1

drivers/infiniband/hw/irdma/uda.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2016 - 2021 Intel Corporation */ 3 3 #include <linux/etherdevice.h> 4 4

+1 -1

drivers/infiniband/hw/irdma/uda.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2016 - 2021 Intel Corporation */ 3 3 #ifndef IRDMA_UDA_H 4 4 #define IRDMA_UDA_H

+1 -1

drivers/infiniband/hw/irdma/uda_d.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2016 - 2021 Intel Corporation */ 3 3 #ifndef IRDMA_UDA_D_H 4 4 #define IRDMA_UDA_D_H

+1 -1

drivers/infiniband/hw/irdma/uk.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #include "osdep.h" 4 4 #include "defs.h"

+1 -1

drivers/infiniband/hw/irdma/user.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2015 - 2020 Intel Corporation */ 3 3 #ifndef IRDMA_USER_H 4 4 #define IRDMA_USER_H

+1 -1

drivers/infiniband/hw/irdma/utils.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #include "main.h" 4 4

+190 -44

drivers/infiniband/hw/irdma/verbs.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #include "main.h" 4 4 ··· 2649 2649 cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request; 2650 2650 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2651 2651 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 2652 2652 + if (status) 2653 2653 + return status; 2652 2654 2653 2653 - return status; 2655 2655 + iwmr->is_hwreg = 1; 2656 2656 + return 0; 2654 2657 } 2655 2658 2656 2659 /** ··· 2819 2816 ret = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2820 2817 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 2821 2818 2819 2819 + if (!ret) 2820 2820 + iwmr->is_hwreg = 1; 2821 2821 + 2822 2822 return ret; 2823 2823 } 2824 2824 2825 2825 - static int irdma_reg_user_mr_type_mem(struct irdma_mr *iwmr, int access) 2825 2825 + static int irdma_reg_user_mr_type_mem(struct irdma_mr *iwmr, int access, 2826 2826 + bool create_stag) 2826 2827 { 2827 2828 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device); 2828 2829 struct irdma_pbl *iwpbl = &iwmr->iwpbl; 2829 2829 - u32 stag; 2830 2830 + u32 stag = 0; 2830 2831 u8 lvl; 2831 2832 int err; 2832 2833 ··· 2849 2842 } 2850 2843 } 2851 2844 2852 2852 - stag = irdma_create_stag(iwdev); 2853 2853 - if (!stag) { 2854 2854 - err = -ENOMEM; 2855 2855 - goto free_pble; 2845 2845 + if (create_stag) { 2846 2846 + stag = irdma_create_stag(iwdev); 2847 2847 + if (!stag) { 2848 2848 + err = -ENOMEM; 2849 2849 + goto free_pble; 2850 2850 + } 2851 2851 + 2852 2852 + iwmr->stag = stag; 2853 2853 + iwmr->ibmr.rkey = stag; 2854 2854 + iwmr->ibmr.lkey = stag; 2856 2855 } 2857 2856 2858 2858 - iwmr->stag = stag; 2859 2859 - iwmr->ibmr.rkey = stag; 2860 2860 - iwmr->ibmr.lkey = stag; 2861 2857 err = irdma_hwreg_mr(iwdev, iwmr, access); 2862 2858 if (err) 2863 2859 goto err_hwreg; ··· 2868 2858 return 0; 2869 2859 2870 2860 err_hwreg: 2871 2871 - irdma_free_stag(iwdev, stag); 2861 2861 + if (stag) 2862 2862 + irdma_free_stag(iwdev, stag); 2872 2863 2873 2864 free_pble: 2874 2865 if (iwpbl->pble_alloc.level != PBLE_LEVEL_0 && iwpbl->pbl_allocated) ··· 3044 3033 goto error; 3045 3034 break; 3046 3035 case IRDMA_MEMREG_TYPE_MEM: 3047 3047 - err = irdma_reg_user_mr_type_mem(iwmr, access); 3036 3036 + err = irdma_reg_user_mr_type_mem(iwmr, access, true); 3048 3037 if (err) 3049 3038 goto error; 3050 3039 ··· 3088 3077 goto err_release; 3089 3078 } 3090 3079 3091 3091 - err = irdma_reg_user_mr_type_mem(iwmr, access); 3080 3080 + err = irdma_reg_user_mr_type_mem(iwmr, access, true); 3092 3081 if (err) 3093 3082 goto err_iwmr; 3094 3083 ··· 3101 3090 ib_umem_release(&umem_dmabuf->umem); 3102 3091 3103 3092 return ERR_PTR(err); 3093 3093 + } 3094 3094 + 3095 3095 + static int irdma_hwdereg_mr(struct ib_mr *ib_mr) 3096 3096 + { 3097 3097 + struct irdma_device *iwdev = to_iwdev(ib_mr->device); 3098 3098 + struct irdma_mr *iwmr = to_iwmr(ib_mr); 3099 3099 + struct irdma_pd *iwpd = to_iwpd(ib_mr->pd); 3100 3100 + struct irdma_dealloc_stag_info *info; 3101 3101 + struct irdma_pbl *iwpbl = &iwmr->iwpbl; 3102 3102 + struct irdma_cqp_request *cqp_request; 3103 3103 + struct cqp_cmds_info *cqp_info; 3104 3104 + int status; 3105 3105 + 3106 3106 + /* Skip HW MR de-register when it is already de-registered 3107 3107 + * during an MR re-reregister and the re-registration fails 3108 3108 + */ 3109 3109 + if (!iwmr->is_hwreg) 3110 3110 + return 0; 3111 3111 + 3112 3112 + cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); 3113 3113 + if (!cqp_request) 3114 3114 + return -ENOMEM; 3115 3115 + 3116 3116 + cqp_info = &cqp_request->info; 3117 3117 + info = &cqp_info->in.u.dealloc_stag.info; 3118 3118 + memset(info, 0, sizeof(*info)); 3119 3119 + info->pd_id = iwpd->sc_pd.pd_id; 3120 3120 + info->stag_idx = ib_mr->rkey >> IRDMA_CQPSQ_STAG_IDX_S; 3121 3121 + info->mr = true; 3122 3122 + if (iwpbl->pbl_allocated) 3123 3123 + info->dealloc_pbl = true; 3124 3124 + 3125 3125 + cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG; 3126 3126 + cqp_info->post_sq = 1; 3127 3127 + cqp_info->in.u.dealloc_stag.dev = &iwdev->rf->sc_dev; 3128 3128 + cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request; 3129 3129 + status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 3130 3130 + irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 3131 3131 + if (status) 3132 3132 + return status; 3133 3133 + 3134 3134 + iwmr->is_hwreg = 0; 3135 3135 + return 0; 3136 3136 + } 3137 3137 + 3138 3138 + /* 3139 3139 + * irdma_rereg_mr_trans - Re-register a user MR for a change translation. 3140 3140 + * @iwmr: ptr of iwmr 3141 3141 + * @start: virtual start address 3142 3142 + * @len: length of mr 3143 3143 + * @virt: virtual address 3144 3144 + * 3145 3145 + * Re-register a user memory region when a change translation is requested. 3146 3146 + * Re-register a new region while reusing the stag from the original registration. 3147 3147 + */ 3148 3148 + static int irdma_rereg_mr_trans(struct irdma_mr *iwmr, u64 start, u64 len, 3149 3149 + u64 virt) 3150 3150 + { 3151 3151 + struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device); 3152 3152 + struct irdma_pbl *iwpbl = &iwmr->iwpbl; 3153 3153 + struct ib_pd *pd = iwmr->ibmr.pd; 3154 3154 + struct ib_umem *region; 3155 3155 + int err; 3156 3156 + 3157 3157 + region = ib_umem_get(pd->device, start, len, iwmr->access); 3158 3158 + if (IS_ERR(region)) 3159 3159 + return PTR_ERR(region); 3160 3160 + 3161 3161 + iwmr->region = region; 3162 3162 + iwmr->ibmr.iova = virt; 3163 3163 + iwmr->ibmr.pd = pd; 3164 3164 + iwmr->page_size = ib_umem_find_best_pgsz(region, 3165 3165 + iwdev->rf->sc_dev.hw_attrs.page_size_cap, 3166 3166 + virt); 3167 3167 + if (unlikely(!iwmr->page_size)) { 3168 3168 + err = -EOPNOTSUPP; 3169 3169 + goto err; 3170 3170 + } 3171 3171 + 3172 3172 + iwmr->len = region->length; 3173 3173 + iwpbl->user_base = virt; 3174 3174 + iwmr->page_cnt = ib_umem_num_dma_blocks(region, iwmr->page_size); 3175 3175 + 3176 3176 + err = irdma_reg_user_mr_type_mem(iwmr, iwmr->access, false); 3177 3177 + if (err) 3178 3178 + goto err; 3179 3179 + 3180 3180 + return 0; 3181 3181 + 3182 3182 + err: 3183 3183 + ib_umem_release(region); 3184 3184 + return err; 3185 3185 + } 3186 3186 + 3187 3187 + /* 3188 3188 + * irdma_rereg_user_mr - Re-Register a user memory region(MR) 3189 3189 + * @ibmr: ib mem to access iwarp mr pointer 3190 3190 + * @flags: bit mask to indicate which of the attr's of MR modified 3191 3191 + * @start: virtual start address 3192 3192 + * @len: length of mr 3193 3193 + * @virt: virtual address 3194 3194 + * @new_access: bit mask of access flags 3195 3195 + * @new_pd: ptr of pd 3196 3196 + * @udata: user data 3197 3197 + * 3198 3198 + * Return: 3199 3199 + * NULL - Success, existing MR updated 3200 3200 + * ERR_PTR - error occurred 3201 3201 + */ 3202 3202 + static struct ib_mr *irdma_rereg_user_mr(struct ib_mr *ib_mr, int flags, 3203 3203 + u64 start, u64 len, u64 virt, 3204 3204 + int new_access, struct ib_pd *new_pd, 3205 3205 + struct ib_udata *udata) 3206 3206 + { 3207 3207 + struct irdma_device *iwdev = to_iwdev(ib_mr->device); 3208 3208 + struct irdma_mr *iwmr = to_iwmr(ib_mr); 3209 3209 + struct irdma_pbl *iwpbl = &iwmr->iwpbl; 3210 3210 + int ret; 3211 3211 + 3212 3212 + if (len > iwdev->rf->sc_dev.hw_attrs.max_mr_size) 3213 3213 + return ERR_PTR(-EINVAL); 3214 3214 + 3215 3215 + if (flags & ~(IB_MR_REREG_TRANS | IB_MR_REREG_PD | IB_MR_REREG_ACCESS)) 3216 3216 + return ERR_PTR(-EOPNOTSUPP); 3217 3217 + 3218 3218 + ret = irdma_hwdereg_mr(ib_mr); 3219 3219 + if (ret) 3220 3220 + return ERR_PTR(ret); 3221 3221 + 3222 3222 + if (flags & IB_MR_REREG_ACCESS) 3223 3223 + iwmr->access = new_access; 3224 3224 + 3225 3225 + if (flags & IB_MR_REREG_PD) { 3226 3226 + iwmr->ibmr.pd = new_pd; 3227 3227 + iwmr->ibmr.device = new_pd->device; 3228 3228 + } 3229 3229 + 3230 3230 + if (flags & IB_MR_REREG_TRANS) { 3231 3231 + if (iwpbl->pbl_allocated) { 3232 3232 + irdma_free_pble(iwdev->rf->pble_rsrc, 3233 3233 + &iwpbl->pble_alloc); 3234 3234 + iwpbl->pbl_allocated = false; 3235 3235 + } 3236 3236 + if (iwmr->region) { 3237 3237 + ib_umem_release(iwmr->region); 3238 3238 + iwmr->region = NULL; 3239 3239 + } 3240 3240 + 3241 3241 + ret = irdma_rereg_mr_trans(iwmr, start, len, virt); 3242 3242 + } else 3243 3243 + ret = irdma_hwreg_mr(iwdev, iwmr, iwmr->access); 3244 3244 + if (ret) 3245 3245 + return ERR_PTR(ret); 3246 3246 + 3247 3247 + return NULL; 3104 3248 } 3105 3249 3106 3250 /** ··· 3365 3199 */ 3366 3200 static int irdma_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 3367 3201 { 3368 3368 - struct ib_pd *ibpd = ib_mr->pd; 3369 3369 - struct irdma_pd *iwpd = to_iwpd(ibpd); 3370 3202 struct irdma_mr *iwmr = to_iwmr(ib_mr); 3371 3203 struct irdma_device *iwdev = to_iwdev(ib_mr->device); 3372 3372 - struct irdma_dealloc_stag_info *info; 3373 3204 struct irdma_pbl *iwpbl = &iwmr->iwpbl; 3374 3374 - struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc; 3375 3375 - struct irdma_cqp_request *cqp_request; 3376 3376 - struct cqp_cmds_info *cqp_info; 3377 3377 - int status; 3205 3205 + int ret; 3378 3206 3379 3207 if (iwmr->type != IRDMA_MEMREG_TYPE_MEM) { 3380 3208 if (iwmr->region) { ··· 3382 3222 goto done; 3383 3223 } 3384 3224 3385 3385 - cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); 3386 3386 - if (!cqp_request) 3387 3387 - return -ENOMEM; 3388 3388 - 3389 3389 - cqp_info = &cqp_request->info; 3390 3390 - info = &cqp_info->in.u.dealloc_stag.info; 3391 3391 - memset(info, 0, sizeof(*info)); 3392 3392 - info->pd_id = iwpd->sc_pd.pd_id; 3393 3393 - info->stag_idx = ib_mr->rkey >> IRDMA_CQPSQ_STAG_IDX_S; 3394 3394 - info->mr = true; 3395 3395 - if (iwpbl->pbl_allocated) 3396 3396 - info->dealloc_pbl = true; 3397 3397 - 3398 3398 - cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG; 3399 3399 - cqp_info->post_sq = 1; 3400 3400 - cqp_info->in.u.dealloc_stag.dev = &iwdev->rf->sc_dev; 3401 3401 - cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request; 3402 3402 - status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 3403 3403 - irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 3404 3404 - if (status) 3405 3405 - return status; 3225 3225 + ret = irdma_hwdereg_mr(ib_mr); 3226 3226 + if (ret) 3227 3227 + return ret; 3406 3228 3407 3229 irdma_free_stag(iwdev, iwmr->stag); 3408 3230 done: 3409 3231 if (iwpbl->pbl_allocated) 3410 3410 - irdma_free_pble(iwdev->rf->pble_rsrc, palloc); 3411 3411 - ib_umem_release(iwmr->region); 3232 3232 + irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc); 3233 3233 + 3234 3234 + if (iwmr->region) 3235 3235 + ib_umem_release(iwmr->region); 3236 3236 + 3412 3237 kfree(iwmr); 3413 3238 3414 3239 return 0; ··· 4723 4578 .query_qp = irdma_query_qp, 4724 4579 .reg_user_mr = irdma_reg_user_mr, 4725 4580 .reg_user_mr_dmabuf = irdma_reg_user_mr_dmabuf, 4581 4581 + .rereg_user_mr = irdma_rereg_user_mr, 4726 4582 .req_notify_cq = irdma_req_notify_cq, 4727 4583 .resize_cq = irdma_resize_cq, 4728 4584 INIT_RDMA_OBJ_SIZE(ib_pd, irdma_pd, ibpd),

+3 -1

drivers/infiniband/hw/irdma/verbs.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 3 #ifndef IRDMA_VERBS_H 4 4 #define IRDMA_VERBS_H ··· 100 100 struct ib_mw ibmw; 101 101 }; 102 102 struct ib_umem *region; 103 103 + int access; 104 104 + u8 is_hwreg; 103 105 u16 type; 104 106 u32 page_cnt; 105 107 u64 page_size;

+1 -1

drivers/infiniband/hw/irdma/ws.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 1 1 + // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2017 - 2021 Intel Corporation */ 3 3 #include "osdep.h" 4 4 #include "hmc.h"

+1 -1

drivers/infiniband/hw/irdma/ws.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2015 - 2020 Intel Corporation */ 3 3 #ifndef IRDMA_WS_H 4 4 #define IRDMA_WS_H

+13

drivers/infiniband/hw/mlx5/mad.c

reviewed

··· 619 619 } 620 620 } 621 621 622 622 + /* Check if extended speeds 2 (XDR/...) are supported */ 623 623 + if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP && 624 624 + props->port_cap_flags2 & IB_PORT_EXTENDED_SPEEDS2_SUP) { 625 625 + ext_active_speed = (out_mad->data[56] >> 4) & 0x6; 626 626 + 627 627 + switch (ext_active_speed) { 628 628 + case 2: 629 629 + if (props->port_cap_flags2 & IB_PORT_LINK_SPEED_XDR_SUP) 630 630 + props->active_speed = IB_SPEED_XDR; 631 631 + break; 632 632 + } 633 633 + } 634 634 + 622 635 /* If reported active speed is QDR, check if is FDR-10 */ 623 636 if (props->active_speed == 4) { 624 637 if (dev->port_caps[port - 1].ext_port_cap &

+7 -5

drivers/infiniband/hw/mlx5/main.c

reviewed

··· 444 444 *active_width = IB_WIDTH_2X; 445 445 *active_speed = IB_SPEED_NDR; 446 446 break; 447 447 - case MLX5E_PROT_MASK(MLX5E_400GAUI_8): 447 447 + case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 448 448 *active_width = IB_WIDTH_8X; 449 449 *active_speed = IB_SPEED_HDR; 450 450 break; 451 451 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 452 452 *active_width = IB_WIDTH_4X; 453 453 + *active_speed = IB_SPEED_NDR; 454 454 + break; 455 455 + case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 456 456 + *active_width = IB_WIDTH_8X; 453 457 *active_speed = IB_SPEED_NDR; 454 458 break; 455 459 default: ··· 3267 3263 3268 3264 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3269 3265 3270 3270 - key = ibdev->ib_dev.index; 3266 3266 + key = mpi->mdev->priv.adev_idx; 3271 3267 mlx5_core_mp_event_replay(mpi->mdev, 3272 3268 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3273 3269 &key); ··· 4092 4088 return ret; 4093 4089 4094 4090 ret = mlx5_mkey_cache_init(dev); 4095 4095 - if (ret) { 4091 4091 + if (ret) 4096 4092 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4097 4097 - mlx5r_umr_resource_cleanup(dev); 4098 4098 - } 4099 4093 return ret; 4100 4094 } 4101 4095

+18 -3

drivers/infiniband/hw/mlx5/mlx5_ib.h

reviewed

··· 753 753 unsigned int state; 754 754 }; 755 755 756 756 + #define NUM_MKEYS_PER_PAGE \ 757 757 + ((PAGE_SIZE - sizeof(struct list_head)) / sizeof(u32)) 758 758 + 759 759 + struct mlx5_mkeys_page { 760 760 + u32 mkeys[NUM_MKEYS_PER_PAGE]; 761 761 + struct list_head list; 762 762 + }; 763 763 + static_assert(sizeof(struct mlx5_mkeys_page) == PAGE_SIZE); 764 764 + 765 765 + struct mlx5_mkeys_queue { 766 766 + struct list_head pages_list; 767 767 + u32 num_pages; 768 768 + unsigned long ci; 769 769 + spinlock_t lock; /* sync list ops */ 770 770 + }; 771 771 + 756 772 struct mlx5_cache_ent { 757 757 - struct xarray mkeys; 758 758 - unsigned long stored; 759 759 - unsigned long reserved; 773 773 + struct mlx5_mkeys_queue mkeys_queue; 774 774 + u32 pending; 760 775 761 776 char name[4]; 762 777

+151 -175

drivers/infiniband/hw/mlx5/mr.c

reviewed

··· 143 143 mlx5_cmd_out_err(dev->mdev, MLX5_CMD_OP_CREATE_MKEY, 0, out); 144 144 } 145 145 146 146 - static int push_mkey_locked(struct mlx5_cache_ent *ent, bool limit_pendings, 147 147 - void *to_store) 146 146 + static int push_mkey_locked(struct mlx5_cache_ent *ent, u32 mkey) 148 147 { 149 149 - XA_STATE(xas, &ent->mkeys, 0); 150 150 - void *curr; 148 148 + unsigned long tmp = ent->mkeys_queue.ci % NUM_MKEYS_PER_PAGE; 149 149 + struct mlx5_mkeys_page *page; 151 150 152 152 - if (limit_pendings && 153 153 - (ent->reserved - ent->stored) > MAX_PENDING_REG_MR) 154 154 - return -EAGAIN; 155 155 - 156 156 - while (1) { 157 157 - /* 158 158 - * This is cmpxchg (NULL, XA_ZERO_ENTRY) however this version 159 159 - * doesn't transparently unlock. Instead we set the xas index to 160 160 - * the current value of reserved every iteration. 161 161 - */ 162 162 - xas_set(&xas, ent->reserved); 163 163 - curr = xas_load(&xas); 164 164 - if (!curr) { 165 165 - if (to_store && ent->stored == ent->reserved) 166 166 - xas_store(&xas, to_store); 167 167 - else 168 168 - xas_store(&xas, XA_ZERO_ENTRY); 169 169 - if (xas_valid(&xas)) { 170 170 - ent->reserved++; 171 171 - if (to_store) { 172 172 - if (ent->stored != ent->reserved) 173 173 - __xa_store(&ent->mkeys, 174 174 - ent->stored, 175 175 - to_store, 176 176 - GFP_KERNEL); 177 177 - ent->stored++; 178 178 - queue_adjust_cache_locked(ent); 179 179 - WRITE_ONCE(ent->dev->cache.last_add, 180 180 - jiffies); 181 181 - } 182 182 - } 183 183 - } 184 184 - xa_unlock_irq(&ent->mkeys); 185 185 - 186 186 - /* 187 187 - * Notice xas_nomem() must always be called as it cleans 188 188 - * up any cached allocation. 189 189 - */ 190 190 - if (!xas_nomem(&xas, GFP_KERNEL)) 191 191 - break; 192 192 - xa_lock_irq(&ent->mkeys); 151 151 + lockdep_assert_held(&ent->mkeys_queue.lock); 152 152 + if (ent->mkeys_queue.ci >= 153 153 + ent->mkeys_queue.num_pages * NUM_MKEYS_PER_PAGE) { 154 154 + page = kzalloc(sizeof(*page), GFP_ATOMIC); 155 155 + if (!page) 156 156 + return -ENOMEM; 157 157 + ent->mkeys_queue.num_pages++; 158 158 + list_add_tail(&page->list, &ent->mkeys_queue.pages_list); 159 159 + } else { 160 160 + page = list_last_entry(&ent->mkeys_queue.pages_list, 161 161 + struct mlx5_mkeys_page, list); 193 162 } 194 194 - xa_lock_irq(&ent->mkeys); 195 195 - if (xas_error(&xas)) 196 196 - return xas_error(&xas); 197 197 - if (WARN_ON(curr)) 198 198 - return -EINVAL; 163 163 + 164 164 + page->mkeys[tmp] = mkey; 165 165 + ent->mkeys_queue.ci++; 199 166 return 0; 200 167 } 201 168 202 202 - static int push_mkey(struct mlx5_cache_ent *ent, bool limit_pendings, 203 203 - void *to_store) 169 169 + static int pop_mkey_locked(struct mlx5_cache_ent *ent) 204 170 { 205 205 - int ret; 171 171 + unsigned long tmp = (ent->mkeys_queue.ci - 1) % NUM_MKEYS_PER_PAGE; 172 172 + struct mlx5_mkeys_page *last_page; 173 173 + u32 mkey; 206 174 207 207 - xa_lock_irq(&ent->mkeys); 208 208 - ret = push_mkey_locked(ent, limit_pendings, to_store); 209 209 - xa_unlock_irq(&ent->mkeys); 210 210 - return ret; 211 211 - } 212 212 - 213 213 - static void undo_push_reserve_mkey(struct mlx5_cache_ent *ent) 214 214 - { 215 215 - void *old; 216 216 - 217 217 - ent->reserved--; 218 218 - old = __xa_erase(&ent->mkeys, ent->reserved); 219 219 - WARN_ON(old); 220 220 - } 221 221 - 222 222 - static void push_to_reserved(struct mlx5_cache_ent *ent, u32 mkey) 223 223 - { 224 224 - void *old; 225 225 - 226 226 - old = __xa_store(&ent->mkeys, ent->stored, xa_mk_value(mkey), 0); 227 227 - WARN_ON(old); 228 228 - ent->stored++; 229 229 - } 230 230 - 231 231 - static u32 pop_stored_mkey(struct mlx5_cache_ent *ent) 232 232 - { 233 233 - void *old, *xa_mkey; 234 234 - 235 235 - ent->stored--; 236 236 - ent->reserved--; 237 237 - 238 238 - if (ent->stored == ent->reserved) { 239 239 - xa_mkey = __xa_erase(&ent->mkeys, ent->stored); 240 240 - WARN_ON(!xa_mkey); 241 241 - return (u32)xa_to_value(xa_mkey); 175 175 + lockdep_assert_held(&ent->mkeys_queue.lock); 176 176 + last_page = list_last_entry(&ent->mkeys_queue.pages_list, 177 177 + struct mlx5_mkeys_page, list); 178 178 + mkey = last_page->mkeys[tmp]; 179 179 + last_page->mkeys[tmp] = 0; 180 180 + ent->mkeys_queue.ci--; 181 181 + if (ent->mkeys_queue.num_pages > 1 && !tmp) { 182 182 + list_del(&last_page->list); 183 183 + ent->mkeys_queue.num_pages--; 184 184 + kfree(last_page); 242 185 } 243 243 - 244 244 - xa_mkey = __xa_store(&ent->mkeys, ent->stored, XA_ZERO_ENTRY, 245 245 - GFP_KERNEL); 246 246 - WARN_ON(!xa_mkey || xa_is_err(xa_mkey)); 247 247 - old = __xa_erase(&ent->mkeys, ent->reserved); 248 248 - WARN_ON(old); 249 249 - return (u32)xa_to_value(xa_mkey); 186 186 + return mkey; 250 187 } 251 188 252 189 static void create_mkey_callback(int status, struct mlx5_async_work *context) ··· 197 260 if (status) { 198 261 create_mkey_warn(dev, status, mkey_out->out); 199 262 kfree(mkey_out); 200 200 - xa_lock_irqsave(&ent->mkeys, flags); 201 201 - undo_push_reserve_mkey(ent); 263 263 + spin_lock_irqsave(&ent->mkeys_queue.lock, flags); 264 264 + ent->pending--; 202 265 WRITE_ONCE(dev->fill_delay, 1); 203 203 - xa_unlock_irqrestore(&ent->mkeys, flags); 266 266 + spin_unlock_irqrestore(&ent->mkeys_queue.lock, flags); 204 267 mod_timer(&dev->delay_timer, jiffies + HZ); 205 268 return; 206 269 } ··· 209 272 MLX5_GET(create_mkey_out, mkey_out->out, mkey_index)); 210 273 WRITE_ONCE(dev->cache.last_add, jiffies); 211 274 212 212 - xa_lock_irqsave(&ent->mkeys, flags); 213 213 - push_to_reserved(ent, mkey_out->mkey); 275 275 + spin_lock_irqsave(&ent->mkeys_queue.lock, flags); 276 276 + push_mkey_locked(ent, mkey_out->mkey); 214 277 /* If we are doing fill_to_high_water then keep going. */ 215 278 queue_adjust_cache_locked(ent); 216 216 - xa_unlock_irqrestore(&ent->mkeys, flags); 279 279 + ent->pending--; 280 280 + spin_unlock_irqrestore(&ent->mkeys_queue.lock, flags); 217 281 kfree(mkey_out); 218 282 } 219 283 ··· 271 333 set_cache_mkc(ent, mkc); 272 334 async_create->ent = ent; 273 335 274 274 - err = push_mkey(ent, true, NULL); 275 275 - if (err) 336 336 + spin_lock_irq(&ent->mkeys_queue.lock); 337 337 + if (ent->pending >= MAX_PENDING_REG_MR) { 338 338 + err = -EAGAIN; 276 339 goto free_async_create; 340 340 + } 341 341 + ent->pending++; 342 342 + spin_unlock_irq(&ent->mkeys_queue.lock); 277 343 278 344 err = mlx5_ib_create_mkey_cb(async_create); 279 345 if (err) { 280 346 mlx5_ib_warn(ent->dev, "create mkey failed %d\n", err); 281 281 - goto err_undo_reserve; 347 347 + goto err_create_mkey; 282 348 } 283 349 } 284 350 285 351 return 0; 286 352 287 287 - err_undo_reserve: 288 288 - xa_lock_irq(&ent->mkeys); 289 289 - undo_push_reserve_mkey(ent); 290 290 - xa_unlock_irq(&ent->mkeys); 353 353 + err_create_mkey: 354 354 + spin_lock_irq(&ent->mkeys_queue.lock); 355 355 + ent->pending--; 291 356 free_async_create: 357 357 + spin_unlock_irq(&ent->mkeys_queue.lock); 292 358 kfree(async_create); 293 359 return err; 294 360 } ··· 325 383 { 326 384 u32 mkey; 327 385 328 328 - lockdep_assert_held(&ent->mkeys.xa_lock); 329 329 - if (!ent->stored) 386 386 + lockdep_assert_held(&ent->mkeys_queue.lock); 387 387 + if (!ent->mkeys_queue.ci) 330 388 return; 331 331 - mkey = pop_stored_mkey(ent); 332 332 - xa_unlock_irq(&ent->mkeys); 389 389 + mkey = pop_mkey_locked(ent); 390 390 + spin_unlock_irq(&ent->mkeys_queue.lock); 333 391 mlx5_core_destroy_mkey(ent->dev->mdev, mkey); 334 334 - xa_lock_irq(&ent->mkeys); 392 392 + spin_lock_irq(&ent->mkeys_queue.lock); 335 393 } 336 394 337 395 static int resize_available_mrs(struct mlx5_cache_ent *ent, unsigned int target, 338 396 bool limit_fill) 339 339 - __acquires(&ent->mkeys) __releases(&ent->mkeys) 397 397 + __acquires(&ent->mkeys_queue.lock) __releases(&ent->mkeys_queue.lock) 340 398 { 341 399 int err; 342 400 343 343 - lockdep_assert_held(&ent->mkeys.xa_lock); 401 401 + lockdep_assert_held(&ent->mkeys_queue.lock); 344 402 345 403 while (true) { 346 404 if (limit_fill) 347 405 target = ent->limit * 2; 348 348 - if (target == ent->reserved) 406 406 + if (target == ent->pending + ent->mkeys_queue.ci) 349 407 return 0; 350 350 - if (target > ent->reserved) { 351 351 - u32 todo = target - ent->reserved; 408 408 + if (target > ent->pending + ent->mkeys_queue.ci) { 409 409 + u32 todo = target - (ent->pending + ent->mkeys_queue.ci); 352 410 353 353 - xa_unlock_irq(&ent->mkeys); 411 411 + spin_unlock_irq(&ent->mkeys_queue.lock); 354 412 err = add_keys(ent, todo); 355 413 if (err == -EAGAIN) 356 414 usleep_range(3000, 5000); 357 357 - xa_lock_irq(&ent->mkeys); 415 415 + spin_lock_irq(&ent->mkeys_queue.lock); 358 416 if (err) { 359 417 if (err != -EAGAIN) 360 418 return err; ··· 382 440 * cannot free MRs that are in use. Compute the target value for stored 383 441 * mkeys. 384 442 */ 385 385 - xa_lock_irq(&ent->mkeys); 443 443 + spin_lock_irq(&ent->mkeys_queue.lock); 386 444 if (target < ent->in_use) { 387 445 err = -EINVAL; 388 446 goto err_unlock; ··· 395 453 err = resize_available_mrs(ent, target, false); 396 454 if (err) 397 455 goto err_unlock; 398 398 - xa_unlock_irq(&ent->mkeys); 456 456 + spin_unlock_irq(&ent->mkeys_queue.lock); 399 457 400 458 return count; 401 459 402 460 err_unlock: 403 403 - xa_unlock_irq(&ent->mkeys); 461 461 + spin_unlock_irq(&ent->mkeys_queue.lock); 404 462 return err; 405 463 } 406 464 ··· 411 469 char lbuf[20]; 412 470 int err; 413 471 414 414 - err = snprintf(lbuf, sizeof(lbuf), "%ld\n", ent->stored + ent->in_use); 472 472 + err = snprintf(lbuf, sizeof(lbuf), "%ld\n", 473 473 + ent->mkeys_queue.ci + ent->in_use); 415 474 if (err < 0) 416 475 return err; 417 476 ··· 441 498 * Upon set we immediately fill the cache to high water mark implied by 442 499 * the limit. 443 500 */ 444 444 - xa_lock_irq(&ent->mkeys); 501 501 + spin_lock_irq(&ent->mkeys_queue.lock); 445 502 ent->limit = var; 446 503 err = resize_available_mrs(ent, 0, true); 447 447 - xa_unlock_irq(&ent->mkeys); 504 504 + spin_unlock_irq(&ent->mkeys_queue.lock); 448 505 if (err) 449 506 return err; 450 507 return count; ··· 480 537 mutex_lock(&cache->rb_lock); 481 538 for (node = rb_first(&cache->rb_root); node; node = rb_next(node)) { 482 539 ent = rb_entry(node, struct mlx5_cache_ent, node); 483 483 - xa_lock_irq(&ent->mkeys); 484 484 - ret = ent->stored < ent->limit; 485 485 - xa_unlock_irq(&ent->mkeys); 540 540 + spin_lock_irq(&ent->mkeys_queue.lock); 541 541 + ret = ent->mkeys_queue.ci < ent->limit; 542 542 + spin_unlock_irq(&ent->mkeys_queue.lock); 486 543 if (ret) { 487 544 mutex_unlock(&cache->rb_lock); 488 545 return true; ··· 499 556 */ 500 557 static void queue_adjust_cache_locked(struct mlx5_cache_ent *ent) 501 558 { 502 502 - lockdep_assert_held(&ent->mkeys.xa_lock); 559 559 + lockdep_assert_held(&ent->mkeys_queue.lock); 503 560 504 561 if (ent->disabled || READ_ONCE(ent->dev->fill_delay) || ent->is_tmp) 505 562 return; 506 506 - if (ent->stored < ent->limit) { 563 563 + if (ent->mkeys_queue.ci < ent->limit) { 507 564 ent->fill_to_high_water = true; 508 565 mod_delayed_work(ent->dev->cache.wq, &ent->dwork, 0); 509 566 } else if (ent->fill_to_high_water && 510 510 - ent->reserved < 2 * ent->limit) { 567 567 + ent->mkeys_queue.ci + ent->pending < 2 * ent->limit) { 511 568 /* 512 569 * Once we start populating due to hitting a low water mark 513 570 * continue until we pass the high water mark. 514 571 */ 515 572 mod_delayed_work(ent->dev->cache.wq, &ent->dwork, 0); 516 516 - } else if (ent->stored == 2 * ent->limit) { 573 573 + } else if (ent->mkeys_queue.ci == 2 * ent->limit) { 517 574 ent->fill_to_high_water = false; 518 518 - } else if (ent->stored > 2 * ent->limit) { 575 575 + } else if (ent->mkeys_queue.ci > 2 * ent->limit) { 519 576 /* Queue deletion of excess entries */ 520 577 ent->fill_to_high_water = false; 521 521 - if (ent->stored != ent->reserved) 578 578 + if (ent->pending) 522 579 queue_delayed_work(ent->dev->cache.wq, &ent->dwork, 523 580 msecs_to_jiffies(1000)); 524 581 else ··· 532 589 struct mlx5_mkey_cache *cache = &dev->cache; 533 590 int err; 534 591 535 535 - xa_lock_irq(&ent->mkeys); 592 592 + spin_lock_irq(&ent->mkeys_queue.lock); 536 593 if (ent->disabled) 537 594 goto out; 538 595 539 539 - if (ent->fill_to_high_water && ent->reserved < 2 * ent->limit && 596 596 + if (ent->fill_to_high_water && 597 597 + ent->mkeys_queue.ci + ent->pending < 2 * ent->limit && 540 598 !READ_ONCE(dev->fill_delay)) { 541 541 - xa_unlock_irq(&ent->mkeys); 599 599 + spin_unlock_irq(&ent->mkeys_queue.lock); 542 600 err = add_keys(ent, 1); 543 543 - xa_lock_irq(&ent->mkeys); 601 601 + spin_lock_irq(&ent->mkeys_queue.lock); 544 602 if (ent->disabled) 545 603 goto out; 546 604 if (err) { ··· 559 615 msecs_to_jiffies(1000)); 560 616 } 561 617 } 562 562 - } else if (ent->stored > 2 * ent->limit) { 618 618 + } else if (ent->mkeys_queue.ci > 2 * ent->limit) { 563 619 bool need_delay; 564 620 565 621 /* ··· 574 630 * the garbage collection work to try to run in next cycle, in 575 631 * order to free CPU resources to other tasks. 576 632 */ 577 577 - xa_unlock_irq(&ent->mkeys); 633 633 + spin_unlock_irq(&ent->mkeys_queue.lock); 578 634 need_delay = need_resched() || someone_adding(cache) || 579 635 !time_after(jiffies, 580 636 READ_ONCE(cache->last_add) + 300 * HZ); 581 581 - xa_lock_irq(&ent->mkeys); 637 637 + spin_lock_irq(&ent->mkeys_queue.lock); 582 638 if (ent->disabled) 583 639 goto out; 584 640 if (need_delay) { ··· 589 645 queue_adjust_cache_locked(ent); 590 646 } 591 647 out: 592 592 - xa_unlock_irq(&ent->mkeys); 648 648 + spin_unlock_irq(&ent->mkeys_queue.lock); 593 649 } 594 650 595 651 static void delayed_cache_work_func(struct work_struct *work) ··· 697 753 if (!mr) 698 754 return ERR_PTR(-ENOMEM); 699 755 700 700 - xa_lock_irq(&ent->mkeys); 756 756 + spin_lock_irq(&ent->mkeys_queue.lock); 701 757 ent->in_use++; 702 758 703 703 - if (!ent->stored) { 759 759 + if (!ent->mkeys_queue.ci) { 704 760 queue_adjust_cache_locked(ent); 705 761 ent->miss++; 706 706 - xa_unlock_irq(&ent->mkeys); 762 762 + spin_unlock_irq(&ent->mkeys_queue.lock); 707 763 err = create_cache_mkey(ent, &mr->mmkey.key); 708 764 if (err) { 709 709 - xa_lock_irq(&ent->mkeys); 765 765 + spin_lock_irq(&ent->mkeys_queue.lock); 710 766 ent->in_use--; 711 711 - xa_unlock_irq(&ent->mkeys); 767 767 + spin_unlock_irq(&ent->mkeys_queue.lock); 712 768 kfree(mr); 713 769 return ERR_PTR(err); 714 770 } 715 771 } else { 716 716 - mr->mmkey.key = pop_stored_mkey(ent); 772 772 + mr->mmkey.key = pop_mkey_locked(ent); 717 773 queue_adjust_cache_locked(ent); 718 718 - xa_unlock_irq(&ent->mkeys); 774 774 + spin_unlock_irq(&ent->mkeys_queue.lock); 719 775 } 720 776 mr->mmkey.cache_ent = ent; 721 777 mr->mmkey.type = MLX5_MKEY_MR; ··· 769 825 u32 mkey; 770 826 771 827 cancel_delayed_work(&ent->dwork); 772 772 - xa_lock_irq(&ent->mkeys); 773 773 - while (ent->stored) { 774 774 - mkey = pop_stored_mkey(ent); 775 775 - xa_unlock_irq(&ent->mkeys); 828 828 + spin_lock_irq(&ent->mkeys_queue.lock); 829 829 + while (ent->mkeys_queue.ci) { 830 830 + mkey = pop_mkey_locked(ent); 831 831 + spin_unlock_irq(&ent->mkeys_queue.lock); 776 832 mlx5_core_destroy_mkey(dev->mdev, mkey); 777 777 - xa_lock_irq(&ent->mkeys); 833 833 + spin_lock_irq(&ent->mkeys_queue.lock); 778 834 } 779 779 - xa_unlock_irq(&ent->mkeys); 835 835 + spin_unlock_irq(&ent->mkeys_queue.lock); 780 836 } 781 837 782 838 static void mlx5_mkey_cache_debugfs_cleanup(struct mlx5_ib_dev *dev) ··· 804 860 dir = debugfs_create_dir(ent->name, dev->cache.fs_root); 805 861 debugfs_create_file("size", 0600, dir, ent, &size_fops); 806 862 debugfs_create_file("limit", 0600, dir, ent, &limit_fops); 807 807 - debugfs_create_ulong("cur", 0400, dir, &ent->stored); 863 863 + debugfs_create_ulong("cur", 0400, dir, &ent->mkeys_queue.ci); 808 864 debugfs_create_u32("miss", 0600, dir, &ent->miss); 809 865 } 810 866 ··· 826 882 WRITE_ONCE(dev->fill_delay, 0); 827 883 } 828 884 885 885 + static int mlx5r_mkeys_init(struct mlx5_cache_ent *ent) 886 886 + { 887 887 + struct mlx5_mkeys_page *page; 888 888 + 889 889 + page = kzalloc(sizeof(*page), GFP_KERNEL); 890 890 + if (!page) 891 891 + return -ENOMEM; 892 892 + INIT_LIST_HEAD(&ent->mkeys_queue.pages_list); 893 893 + spin_lock_init(&ent->mkeys_queue.lock); 894 894 + list_add_tail(&page->list, &ent->mkeys_queue.pages_list); 895 895 + ent->mkeys_queue.num_pages++; 896 896 + return 0; 897 897 + } 898 898 + 899 899 + static void mlx5r_mkeys_uninit(struct mlx5_cache_ent *ent) 900 900 + { 901 901 + struct mlx5_mkeys_page *page; 902 902 + 903 903 + WARN_ON(ent->mkeys_queue.ci || ent->mkeys_queue.num_pages > 1); 904 904 + page = list_last_entry(&ent->mkeys_queue.pages_list, 905 905 + struct mlx5_mkeys_page, list); 906 906 + list_del(&page->list); 907 907 + kfree(page); 908 908 + } 909 909 + 829 910 struct mlx5_cache_ent * 830 911 mlx5r_cache_create_ent_locked(struct mlx5_ib_dev *dev, 831 912 struct mlx5r_cache_rb_key rb_key, ··· 864 895 if (!ent) 865 896 return ERR_PTR(-ENOMEM); 866 897 867 867 - xa_init_flags(&ent->mkeys, XA_FLAGS_LOCK_IRQ); 898 898 + ret = mlx5r_mkeys_init(ent); 899 899 + if (ret) 900 900 + goto mkeys_err; 868 901 ent->rb_key = rb_key; 869 902 ent->dev = dev; 870 903 ent->is_tmp = !persistent_entry; ··· 874 903 INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func); 875 904 876 905 ret = mlx5_cache_ent_insert(&dev->cache, ent); 877 877 - if (ret) { 878 878 - kfree(ent); 879 879 - return ERR_PTR(ret); 880 880 - } 906 906 + if (ret) 907 907 + goto ent_insert_err; 881 908 882 909 if (persistent_entry) { 883 910 if (rb_key.access_mode == MLX5_MKC_ACCESS_MODE_KSM) ··· 898 929 } 899 930 900 931 return ent; 932 932 + ent_insert_err: 933 933 + mlx5r_mkeys_uninit(ent); 934 934 + mkeys_err: 935 935 + kfree(ent); 936 936 + return ERR_PTR(ret); 901 937 } 902 938 903 939 static void remove_ent_work_func(struct work_struct *work) ··· 920 946 cur = rb_prev(cur); 921 947 mutex_unlock(&cache->rb_lock); 922 948 923 923 - xa_lock_irq(&ent->mkeys); 949 949 + spin_lock_irq(&ent->mkeys_queue.lock); 924 950 if (!ent->is_tmp) { 925 925 - xa_unlock_irq(&ent->mkeys); 951 951 + spin_unlock_irq(&ent->mkeys_queue.lock); 926 952 mutex_lock(&cache->rb_lock); 927 953 continue; 928 954 } 929 929 - xa_unlock_irq(&ent->mkeys); 955 955 + spin_unlock_irq(&ent->mkeys_queue.lock); 930 956 931 957 clean_keys(ent->dev, ent); 932 958 mutex_lock(&cache->rb_lock); ··· 976 1002 mutex_unlock(&cache->rb_lock); 977 1003 for (node = rb_first(root); node; node = rb_next(node)) { 978 1004 ent = rb_entry(node, struct mlx5_cache_ent, node); 979 979 - xa_lock_irq(&ent->mkeys); 1005 1005 + spin_lock_irq(&ent->mkeys_queue.lock); 980 1006 queue_adjust_cache_locked(ent); 981 981 - xa_unlock_irq(&ent->mkeys); 1007 1007 + spin_unlock_irq(&ent->mkeys_queue.lock); 982 1008 } 983 1009 984 1010 return 0; ··· 1000 1026 return; 1001 1027 1002 1028 mutex_lock(&dev->cache.rb_lock); 1029 1029 + cancel_delayed_work(&dev->cache.remove_ent_dwork); 1003 1030 for (node = rb_first(root); node; node = rb_next(node)) { 1004 1031 ent = rb_entry(node, struct mlx5_cache_ent, node); 1005 1005 - xa_lock_irq(&ent->mkeys); 1032 1032 + spin_lock_irq(&ent->mkeys_queue.lock); 1006 1033 ent->disabled = true; 1007 1007 - xa_unlock_irq(&ent->mkeys); 1034 1034 + spin_unlock_irq(&ent->mkeys_queue.lock); 1035 1035 + cancel_delayed_work(&ent->dwork); 1008 1036 } 1009 1037 mutex_unlock(&dev->cache.rb_lock); 1010 1038 ··· 1027 1051 node = rb_next(node); 1028 1052 clean_keys(dev, ent); 1029 1053 rb_erase(&ent->node, root); 1054 1054 + mlx5r_mkeys_uninit(ent); 1030 1055 kfree(ent); 1031 1056 } 1032 1057 mutex_unlock(&dev->cache.rb_lock); ··· 1800 1823 int ret; 1801 1824 1802 1825 if (mr->mmkey.cache_ent) { 1803 1803 - xa_lock_irq(&mr->mmkey.cache_ent->mkeys); 1826 1826 + spin_lock_irq(&mr->mmkey.cache_ent->mkeys_queue.lock); 1804 1827 mr->mmkey.cache_ent->in_use--; 1805 1828 goto end; 1806 1829 } ··· 1814 1837 return -EOPNOTSUPP; 1815 1838 } 1816 1839 mr->mmkey.cache_ent = ent; 1817 1817 - xa_lock_irq(&mr->mmkey.cache_ent->mkeys); 1840 1840 + spin_lock_irq(&mr->mmkey.cache_ent->mkeys_queue.lock); 1818 1841 mutex_unlock(&cache->rb_lock); 1819 1842 goto end; 1820 1843 } ··· 1826 1849 return PTR_ERR(ent); 1827 1850 1828 1851 mr->mmkey.cache_ent = ent; 1829 1829 - xa_lock_irq(&mr->mmkey.cache_ent->mkeys); 1852 1852 + spin_lock_irq(&mr->mmkey.cache_ent->mkeys_queue.lock); 1830 1853 1831 1854 end: 1832 1832 - ret = push_mkey_locked(mr->mmkey.cache_ent, false, 1833 1833 - xa_mk_value(mr->mmkey.key)); 1834 1834 - xa_unlock_irq(&mr->mmkey.cache_ent->mkeys); 1855 1855 + ret = push_mkey_locked(mr->mmkey.cache_ent, mr->mmkey.key); 1856 1856 + spin_unlock_irq(&mr->mmkey.cache_ent->mkeys_queue.lock); 1835 1857 return ret; 1836 1858 } 1837 1859

+28 -1

drivers/infiniband/hw/mlx5/qp.c

reviewed

··· 3436 3436 if (rate == IB_RATE_PORT_CURRENT) 3437 3437 return 0; 3438 3438 3439 3439 - if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 3439 3439 + if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_800_GBPS) 3440 3440 return -EINVAL; 3441 3441 3442 3442 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support); ··· 4045 4045 return tx_affinity; 4046 4046 } 4047 4047 4048 4048 + static int __mlx5_ib_qp_set_raw_qp_counter(struct mlx5_ib_qp *qp, u32 set_id, 4049 4049 + struct mlx5_core_dev *mdev) 4050 4050 + { 4051 4051 + struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4052 4052 + struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4053 4053 + u32 in[MLX5_ST_SZ_DW(modify_rq_in)] = {}; 4054 4054 + void *rqc; 4055 4055 + 4056 4056 + if (!qp->rq.wqe_cnt) 4057 4057 + return 0; 4058 4058 + 4059 4059 + MLX5_SET(modify_rq_in, in, rq_state, rq->state); 4060 4060 + MLX5_SET(modify_rq_in, in, uid, to_mpd(qp->ibqp.pd)->uid); 4061 4061 + 4062 4062 + rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 4063 4063 + MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); 4064 4064 + 4065 4065 + MLX5_SET64(modify_rq_in, in, modify_bitmask, 4066 4066 + MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 4067 4067 + MLX5_SET(rqc, rqc, counter_set_id, set_id); 4068 4068 + 4069 4069 + return mlx5_core_modify_rq(mdev, rq->base.mqp.qpn, in); 4070 4070 + } 4071 4071 + 4048 4072 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 4049 4073 struct rdma_counter *counter) 4050 4074 { ··· 4083 4059 set_id = counter->id; 4084 4060 else 4085 4061 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 4062 4062 + 4063 4063 + if (mqp->type == IB_QPT_RAW_PACKET) 4064 4064 + return __mlx5_ib_qp_set_raw_qp_counter(mqp, set_id, dev->mdev); 4086 4065 4087 4066 base = &mqp->trans_qp.base; 4088 4067 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP);

+2 -2

drivers/infiniband/hw/mlx5/umr.c

reviewed

··· 332 332 333 333 WARN_ON_ONCE(1); 334 334 mlx5_ib_warn(dev, 335 335 - "reg umr failed (%u). Trying to recover and resubmit the flushed WQEs\n", 336 336 - umr_context.status); 335 335 + "reg umr failed (%u). Trying to recover and resubmit the flushed WQEs, mkey = %u\n", 336 336 + umr_context.status, mkey); 337 337 mutex_lock(&umrc->lock); 338 338 err = mlx5r_umr_recover(dev); 339 339 mutex_unlock(&umrc->lock);

+1 -1

drivers/infiniband/hw/mthca/mthca_memfree.h

reviewed

··· 68 68 int lowmem; 69 69 int coherent; 70 70 struct mutex mutex; 71 71 - struct mthca_icm *icm[]; 71 71 + struct mthca_icm *icm[] __counted_by(num_icm); 72 72 }; 73 73 74 74 struct mthca_icm_iter {

+1 -1

drivers/infiniband/hw/qib/qib_iba7322.c

reviewed

··· 6127 6127 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ); 6128 6128 return -EINVAL; 6129 6129 } 6130 6130 - strncpy(txselect_list, str, ARRAY_SIZE(txselect_list) - 1); 6130 6130 + strscpy(txselect_list, str, sizeof(txselect_list)); 6131 6131 6132 6132 xa_for_each(&qib_dev_table, index, dd) 6133 6133 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)

+1 -1

drivers/infiniband/hw/usnic/usnic_uiom.h

reviewed

··· 77 77 struct usnic_uiom_chunk { 78 78 struct list_head list; 79 79 int nents; 80 80 - struct scatterlist page_list[]; 80 80 + struct scatterlist page_list[] __counted_by(nents); 81 81 }; 82 82 83 83 struct usnic_uiom_pd *usnic_uiom_alloc_pd(struct device *dev);

+4 -8

drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c

reviewed

··· 1021 1021 pvrdma_free_irq(dev); 1022 1022 pci_free_irq_vectors(pdev); 1023 1023 err_free_cq_ring: 1024 1024 - if (dev->netdev) { 1025 1025 - dev_put(dev->netdev); 1026 1026 - dev->netdev = NULL; 1027 1027 - } 1024 1024 + dev_put(dev->netdev); 1025 1025 + dev->netdev = NULL; 1028 1026 pvrdma_page_dir_cleanup(dev, &dev->cq_pdir); 1029 1027 err_free_async_ring: 1030 1028 pvrdma_page_dir_cleanup(dev, &dev->async_pdir); ··· 1062 1064 1063 1065 flush_workqueue(event_wq); 1064 1066 1065 1065 - if (dev->netdev) { 1066 1066 - dev_put(dev->netdev); 1067 1067 - dev->netdev = NULL; 1068 1068 - } 1067 1067 + dev_put(dev->netdev); 1068 1068 + dev->netdev = NULL; 1069 1069 1070 1070 /* Unregister ib device */ 1071 1071 ib_unregister_device(&dev->ib_dev);

+1 -1

drivers/infiniband/sw/rdmavt/ah.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 - 2019 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/ah.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/cq.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/cq.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/mad.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/mad.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/mcast.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/mcast.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/mmap.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/mmap.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/mr.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/mr.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/pd.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/pd.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/qp.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 - 2020 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/qp.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/rc.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/srq.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/srq.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/trace.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/trace.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016, 2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/trace_cq.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/trace_mr.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/trace_qp.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/trace_rc.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2017 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/trace_rvt.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/trace_tx.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/vt.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 3 * Copyright(c) 2016 - 2018 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/rdmavt/vt.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright(c) 2016 Intel Corporation. 4 4 */

+1 -1

drivers/infiniband/sw/siw/iwarp.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Copyright (c) 2008-2019, IBM Corporation */

+2 -2

drivers/infiniband/sw/siw/siw.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Copyright (c) 2008-2019, IBM Corporation */ ··· 137 137 struct siw_pbl { 138 138 unsigned int num_buf; 139 139 unsigned int max_buf; 140 140 - struct siw_pble pbe[]; 140 140 + struct siw_pble pbe[] __counted_by(max_buf); 141 141 }; 142 142 143 143 /*

+1 -1

drivers/infiniband/sw/siw/siw_cm.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Fredy Neeser */

+1 -1

drivers/infiniband/sw/siw/siw_cm.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Greg Joyce <greg@opengridcomputing.com> */

+1 -1

drivers/infiniband/sw/siw/siw_cq.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Copyright (c) 2008-2019, IBM Corporation */

+1 -1

drivers/infiniband/sw/siw/siw_main.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Copyright (c) 2008-2019, IBM Corporation */

+1 -1

drivers/infiniband/sw/siw/siw_mem.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Copyright (c) 2008-2019, IBM Corporation */

+1 -1

drivers/infiniband/sw/siw/siw_mem.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Copyright (c) 2008-2019, IBM Corporation */

+1 -1

drivers/infiniband/sw/siw/siw_qp.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Copyright (c) 2008-2019, IBM Corporation */

+1 -1

drivers/infiniband/sw/siw/siw_qp_rx.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Copyright (c) 2008-2019, IBM Corporation */

+1 -1

drivers/infiniband/sw/siw/siw_qp_tx.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Copyright (c) 2008-2019, IBM Corporation */

+1 -1

drivers/infiniband/sw/siw/siw_verbs.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Copyright (c) 2008-2019, IBM Corporation */

+1 -1

drivers/infiniband/sw/siw/siw_verbs.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Copyright (c) 2008-2019, IBM Corporation */

+2

drivers/infiniband/ulp/ipoib/ipoib_ethtool.c

reviewed

··· 174 174 return SPEED_50000; 175 175 case IB_SPEED_NDR: 176 176 return SPEED_100000; 177 177 + case IB_SPEED_XDR: 178 178 + return SPEED_200000; 177 179 } 178 180 179 181 return SPEED_UNKNOWN;

+1 -2

drivers/infiniband/ulp/ipoib/ipoib_main.c

reviewed

··· 2005 2005 priv->wq = NULL; 2006 2006 } 2007 2007 2008 2008 - if (priv->parent) 2009 2009 - dev_put(priv->parent); 2008 2008 + dev_put(priv->parent); 2010 2009 } 2011 2010 2012 2011 static int ipoib_set_vf_link_state(struct net_device *dev, int vf, int link_state)

+6 -1

drivers/infiniband/ulp/rtrs/rtrs-clt.c

reviewed

··· 775 775 * Related to @MP_POLICY_RR 776 776 * 777 777 * Locks: 778 778 - * rcu_read_lock() must be hold. 778 778 + * rcu_read_lock() must be held. 779 779 */ 780 780 static struct rtrs_clt_path *get_next_path_rr(struct path_it *it) 781 781 { 782 782 struct rtrs_clt_path __rcu **ppcpu_path; 783 783 struct rtrs_clt_path *path; 784 784 struct rtrs_clt_sess *clt; 785 785 + 786 786 + /* 787 787 + * Assert that rcu lock must be held 788 788 + */ 789 789 + RCU_LOCKDEP_WARN(!rcu_read_lock_held(), "no rcu read lock held"); 785 790 786 791 clt = it->clt; 787 792

+1 -1

drivers/infiniband/ulp/rtrs/rtrs.c

reviewed

··· 255 255 static int create_qp(struct rtrs_con *con, struct ib_pd *pd, 256 256 u32 max_send_wr, u32 max_recv_wr, u32 max_sge) 257 257 { 258 258 - struct ib_qp_init_attr init_attr = {NULL}; 258 258 + struct ib_qp_init_attr init_attr = {}; 259 259 struct rdma_cm_id *cm_id = con->cm_id; 260 260 int ret; 261 261

+1 -1

drivers/infiniband/ulp/srp/ib_srp.h

reviewed

··· 306 306 int max_page_list_len; 307 307 spinlock_t lock; 308 308 struct list_head free_list; 309 309 - struct srp_fr_desc desc[]; 309 309 + struct srp_fr_desc desc[] __counted_by(size); 310 310 }; 311 311 312 312 /**

+2 -1

drivers/net/ethernet/mellanox/mlx5/core/port.c

reviewed

··· 1098 1098 [MLX5E_CAUI_4_100GBASE_CR4_KR4] = 100000, 1099 1099 [MLX5E_100GAUI_2_100GBASE_CR2_KR2] = 100000, 1100 1100 [MLX5E_200GAUI_4_200GBASE_CR4_KR4] = 200000, 1101 1101 - [MLX5E_400GAUI_8] = 400000, 1101 1101 + [MLX5E_400GAUI_8_400GBASE_CR8] = 400000, 1102 1102 [MLX5E_100GAUI_1_100GBASE_CR_KR] = 100000, 1103 1103 [MLX5E_200GAUI_2_200GBASE_CR2_KR2] = 200000, 1104 1104 [MLX5E_400GAUI_4_400GBASE_CR4_KR4] = 400000, 1105 1105 + [MLX5E_800GAUI_8_800GBASE_CR8_KR8] = 800000, 1105 1106 }; 1106 1107 1107 1108 int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,

+2 -1

include/linux/mlx5/port.h

reviewed

··· 115 115 MLX5E_100GAUI_1_100GBASE_CR_KR = 11, 116 116 MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12, 117 117 MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13, 118 118 - MLX5E_400GAUI_8 = 15, 118 118 + MLX5E_400GAUI_8_400GBASE_CR8 = 15, 119 119 MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16, 120 120 + MLX5E_800GAUI_8_800GBASE_CR8_KR8 = 19, 120 121 MLX5E_EXT_LINK_MODES_NUMBER, 121 122 }; 122 123

+2

include/rdma/ib_mad.h

reviewed

··· 277 277 IB_PORT_LINK_WIDTH_2X_SUP = 1 << 4, 278 278 IB_PORT_LINK_SPEED_HDR_SUP = 1 << 5, 279 279 IB_PORT_LINK_SPEED_NDR_SUP = 1 << 10, 280 280 + IB_PORT_EXTENDED_SPEEDS2_SUP = 1 << 11, 281 281 + IB_PORT_LINK_SPEED_XDR_SUP = 1 << 12, 280 282 }; 281 283 282 284 #define OPA_CLASS_PORT_INFO_PR_SUPPORT BIT(26)

+6 -2

include/rdma/ib_verbs.h

reviewed

··· 561 561 IB_SPEED_EDR = 32, 562 562 IB_SPEED_HDR = 64, 563 563 IB_SPEED_NDR = 128, 564 564 + IB_SPEED_XDR = 256, 564 565 }; 565 566 566 567 enum ib_stat_flag { ··· 608 607 const struct rdma_stat_desc *descs; 609 608 unsigned long *is_disabled; 610 609 int num_counters; 611 611 - u64 value[]; 610 610 + u64 value[] __counted_by(num_counters); 612 611 }; 613 612 614 613 #define RDMA_HW_STATS_DEFAULT_LIFESPAN 10 ··· 841 840 IB_RATE_50_GBPS = 20, 842 841 IB_RATE_400_GBPS = 21, 843 842 IB_RATE_600_GBPS = 22, 843 843 + IB_RATE_800_GBPS = 23, 844 844 }; 845 845 846 846 /** ··· 1096 1094 1097 1095 /* 1098 1096 * Maximum number of rdma_rw_ctx structures in flight at a time. 1099 1099 - * ib_create_qp() will calculate the right amount of neededed WRs 1097 1097 + * ib_create_qp() will calculate the right amount of needed WRs 1100 1098 * and MRs based on this. 1101 1099 */ 1102 1100 u32 max_rdma_ctxs; ··· 2610 2608 int (*fill_res_qp_entry)(struct sk_buff *msg, struct ib_qp *ibqp); 2611 2609 int (*fill_res_qp_entry_raw)(struct sk_buff *msg, struct ib_qp *ibqp); 2612 2610 int (*fill_res_cm_id_entry)(struct sk_buff *msg, struct rdma_cm_id *id); 2611 2611 + int (*fill_res_srq_entry)(struct sk_buff *msg, struct ib_srq *ib_srq); 2612 2612 + int (*fill_res_srq_entry_raw)(struct sk_buff *msg, struct ib_srq *ib_srq); 2613 2613 2614 2614 /* Device lifecycle callbacks */ 2615 2615 /*

+11 -1

include/uapi/rdma/hns-abi.h

reviewed

··· 52 52 __aligned_u64 cap_flags; 53 53 }; 54 54 55 55 + enum hns_roce_srq_cap_flags { 56 56 + HNS_ROCE_SRQ_CAP_RECORD_DB = 1 << 0, 57 57 + }; 58 58 + 59 59 + enum hns_roce_srq_cap_flags_resp { 60 60 + HNS_ROCE_RSP_SRQ_CAP_RECORD_DB = 1 << 0, 61 61 + }; 62 62 + 55 63 struct hns_roce_ib_create_srq { 56 64 __aligned_u64 buf_addr; 57 65 __aligned_u64 db_addr; 58 66 __aligned_u64 que_addr; 67 67 + __u32 req_cap_flags; /* Use enum hns_roce_srq_cap_flags */ 68 68 + __u32 reserved; 59 69 }; 60 70 61 71 struct hns_roce_ib_create_srq_resp { 62 72 __u32 srqn; 63 63 - __u32 reserved; 73 73 + __u32 cap_flags; /* Use enum hns_roce_srq_cap_flags */ 64 74 }; 65 75 66 76 struct hns_roce_ib_create_qp {

+2 -1

include/uapi/rdma/ib_user_ioctl_verbs.h

reviewed

··· 220 220 struct ib_uverbs_query_port_resp_ex { 221 221 struct ib_uverbs_query_port_resp legacy_resp; 222 222 __u16 port_cap_flags2; 223 223 - __u8 reserved[6]; 223 223 + __u8 reserved[2]; 224 224 + __u32 active_speed_ex; 224 225 }; 225 226 226 227 struct ib_uverbs_qp_cap {

+4

include/uapi/rdma/rdma_netlink.h

reviewed

··· 299 299 300 300 RDMA_NLDEV_CMD_STAT_GET_STATUS, 301 301 302 302 + RDMA_NLDEV_CMD_RES_SRQ_GET_RAW, 303 303 + 302 304 RDMA_NLDEV_NUM_OPS 303 305 }; 304 306 ··· 555 553 556 554 RDMA_NLDEV_ATTR_STAT_HWCOUNTER_INDEX, /* u32 */ 557 555 RDMA_NLDEV_ATTR_STAT_HWCOUNTER_DYNAMIC, /* u8 */ 556 556 + 557 557 + RDMA_NLDEV_SYS_ATTR_PRIVILEGED_QKEY_MODE, /* u8 */ 558 558 559 559 /* 560 560 * Always the end

+1 -1

include/uapi/rdma/siw-abi.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause */ 2 2 3 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 4 /* Copyright (c) 2008-2019, IBM Corporation */