Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: octeontx2 - register error interrupts for inline cptlf
Register errors interrupts for inline cptlf attached to PF driver
so that SMMU faults and other errors can be reported.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Nithin Dabilpuram
and committed by
Herbert Xu
434c1cb9
e9297111
+155
-55
+64
-37
drivers/crypto/marvell/octeontx2/otx2_cptlf.c
+64
-37
drivers/crypto/marvell/octeontx2/otx2_cptlf.c
···
151
151
irq_misc.u);
152
152
}
153
153
154
-
static void cptlf_enable_intrs(struct otx2_cptlfs_info *lfs)
154
+
static void cptlf_set_done_intrs(struct otx2_cptlfs_info *lfs, u8 enable)
155
155
{
156
-
int slot;
157
-
158
-
/* Enable done interrupts */
159
-
for (slot = 0; slot < lfs->lfs_num; slot++)
160
-
otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,
161
-
OTX2_CPT_LF_DONE_INT_ENA_W1S, 0x1);
162
-
/* Enable Misc interrupts */
163
-
cptlf_set_misc_intrs(lfs, true);
164
-
}
165
-
166
-
static void cptlf_disable_intrs(struct otx2_cptlfs_info *lfs)
167
-
{
156
+
u64 reg = enable ? OTX2_CPT_LF_DONE_INT_ENA_W1S :
157
+
OTX2_CPT_LF_DONE_INT_ENA_W1C;
168
158
int slot;
169
159
170
160
for (slot = 0; slot < lfs->lfs_num; slot++)
171
-
otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,
172
-
OTX2_CPT_LF_DONE_INT_ENA_W1C, 0x1);
173
-
cptlf_set_misc_intrs(lfs, false);
161
+
otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot, reg, 0x1);
174
162
}
175
163
176
164
static inline int cptlf_read_done_cnt(struct otx2_cptlf_info *lf)
···
245
257
return IRQ_HANDLED;
246
258
}
247
259
248
-
void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs)
260
+
void otx2_cptlf_unregister_misc_interrupts(struct otx2_cptlfs_info *lfs)
249
261
{
250
-
int i, offs, vector;
262
+
int i, irq_offs, vector;
251
263
264
+
irq_offs = OTX2_CPT_LF_INT_VEC_E_MISC;
252
265
for (i = 0; i < lfs->lfs_num; i++) {
253
-
for (offs = 0; offs < OTX2_CPT_LF_MSIX_VECTORS; offs++) {
254
-
if (!lfs->lf[i].is_irq_reg[offs])
255
-
continue;
266
+
if (!lfs->lf[i].is_irq_reg[irq_offs])
267
+
continue;
256
268
257
-
vector = pci_irq_vector(lfs->pdev,
258
-
lfs->lf[i].msix_offset + offs);
259
-
free_irq(vector, &lfs->lf[i]);
260
-
lfs->lf[i].is_irq_reg[offs] = false;
261
-
}
269
+
vector = pci_irq_vector(lfs->pdev,
270
+
lfs->lf[i].msix_offset + irq_offs);
271
+
free_irq(vector, &lfs->lf[i]);
272
+
lfs->lf[i].is_irq_reg[irq_offs] = false;
262
273
}
263
-
cptlf_disable_intrs(lfs);
274
+
275
+
cptlf_set_misc_intrs(lfs, false);
264
276
}
265
-
EXPORT_SYMBOL_NS_GPL(otx2_cptlf_unregister_interrupts,
277
+
EXPORT_SYMBOL_NS_GPL(otx2_cptlf_unregister_misc_interrupts,
278
+
CRYPTO_DEV_OCTEONTX2_CPT);
279
+
280
+
void otx2_cptlf_unregister_done_interrupts(struct otx2_cptlfs_info *lfs)
281
+
{
282
+
int i, irq_offs, vector;
283
+
284
+
irq_offs = OTX2_CPT_LF_INT_VEC_E_DONE;
285
+
for (i = 0; i < lfs->lfs_num; i++) {
286
+
if (!lfs->lf[i].is_irq_reg[irq_offs])
287
+
continue;
288
+
289
+
vector = pci_irq_vector(lfs->pdev,
290
+
lfs->lf[i].msix_offset + irq_offs);
291
+
free_irq(vector, &lfs->lf[i]);
292
+
lfs->lf[i].is_irq_reg[irq_offs] = false;
293
+
}
294
+
295
+
cptlf_set_done_intrs(lfs, false);
296
+
}
297
+
EXPORT_SYMBOL_NS_GPL(otx2_cptlf_unregister_done_interrupts,
266
298
CRYPTO_DEV_OCTEONTX2_CPT);
267
299
268
300
static int cptlf_do_register_interrrupts(struct otx2_cptlfs_info *lfs,
···
304
296
return ret;
305
297
}
306
298
307
-
int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs)
299
+
int otx2_cptlf_register_misc_interrupts(struct otx2_cptlfs_info *lfs)
308
300
{
301
+
bool is_cpt1 = (lfs->blkaddr == BLKADDR_CPT1);
309
302
int irq_offs, ret, i;
310
303
304
+
irq_offs = OTX2_CPT_LF_INT_VEC_E_MISC;
311
305
for (i = 0; i < lfs->lfs_num; i++) {
312
-
irq_offs = OTX2_CPT_LF_INT_VEC_E_MISC;
313
-
snprintf(lfs->lf[i].irq_name[irq_offs], 32, "CPTLF Misc%d", i);
306
+
snprintf(lfs->lf[i].irq_name[irq_offs], 32, "CPT%dLF Misc%d",
307
+
is_cpt1, i);
314
308
ret = cptlf_do_register_interrrupts(lfs, i, irq_offs,
315
309
cptlf_misc_intr_handler);
316
310
if (ret)
317
311
goto free_irq;
312
+
}
313
+
cptlf_set_misc_intrs(lfs, true);
314
+
return 0;
318
315
319
-
irq_offs = OTX2_CPT_LF_INT_VEC_E_DONE;
320
-
snprintf(lfs->lf[i].irq_name[irq_offs], 32, "OTX2_CPTLF Done%d",
321
-
i);
316
+
free_irq:
317
+
otx2_cptlf_unregister_misc_interrupts(lfs);
318
+
return ret;
319
+
}
320
+
EXPORT_SYMBOL_NS_GPL(otx2_cptlf_register_misc_interrupts,
321
+
CRYPTO_DEV_OCTEONTX2_CPT);
322
+
323
+
int otx2_cptlf_register_done_interrupts(struct otx2_cptlfs_info *lfs)
324
+
{
325
+
bool is_cpt1 = (lfs->blkaddr == BLKADDR_CPT1);
326
+
int irq_offs, ret, i;
327
+
328
+
irq_offs = OTX2_CPT_LF_INT_VEC_E_DONE;
329
+
for (i = 0; i < lfs->lfs_num; i++) {
330
+
snprintf(lfs->lf[i].irq_name[irq_offs], 32,
331
+
"OTX2_CPT%dLF Done%d", is_cpt1, i);
322
332
ret = cptlf_do_register_interrrupts(lfs, i, irq_offs,
323
333
cptlf_done_intr_handler);
324
334
if (ret)
325
335
goto free_irq;
326
336
}
327
-
cptlf_enable_intrs(lfs);
337
+
cptlf_set_done_intrs(lfs, true);
328
338
return 0;
329
339
330
340
free_irq:
331
-
otx2_cptlf_unregister_interrupts(lfs);
341
+
otx2_cptlf_unregister_done_interrupts(lfs);
332
342
return ret;
333
343
}
334
-
EXPORT_SYMBOL_NS_GPL(otx2_cptlf_register_interrupts, CRYPTO_DEV_OCTEONTX2_CPT);
344
+
EXPORT_SYMBOL_NS_GPL(otx2_cptlf_register_done_interrupts,
345
+
CRYPTO_DEV_OCTEONTX2_CPT);
335
346
336
347
void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs)
337
348
{
+4
-2
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
+4
-2
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
···
410
410
int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri,
411
411
int lfs_num);
412
412
void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs);
413
-
int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs);
414
-
void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs);
413
+
int otx2_cptlf_register_misc_interrupts(struct otx2_cptlfs_info *lfs);
414
+
int otx2_cptlf_register_done_interrupts(struct otx2_cptlfs_info *lfs);
415
+
void otx2_cptlf_unregister_misc_interrupts(struct otx2_cptlfs_info *lfs);
416
+
void otx2_cptlf_unregister_done_interrupts(struct otx2_cptlfs_info *lfs);
415
417
void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs);
416
418
int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs);
417
419
+4
drivers/crypto/marvell/octeontx2/otx2_cptpf.h
+4
drivers/crypto/marvell/octeontx2/otx2_cptpf.h
···
71
71
irqreturn_t otx2_cptpf_vfpf_mbox_intr(int irq, void *arg);
72
72
void otx2_cptpf_vfpf_mbox_handler(struct work_struct *work);
73
73
74
+
int otx2_inline_cptlf_setup(struct otx2_cptpf_dev *cptpf,
75
+
struct otx2_cptlfs_info *lfs, u8 egrp, int num_lfs);
76
+
void otx2_inline_cptlf_cleanup(struct otx2_cptlfs_info *lfs);
77
+
74
78
#endif /* __OTX2_CPTPF_H */
+16
-3
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
+16
-3
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
···
722
722
{
723
723
struct device *dev = &pdev->dev;
724
724
struct otx2_cptpf_dev *cptpf;
725
-
int err;
725
+
int err, num_vec;
726
726
727
727
cptpf = devm_kzalloc(dev, sizeof(*cptpf), GFP_KERNEL);
728
728
if (!cptpf)
···
757
757
if (err)
758
758
goto clear_drvdata;
759
759
760
-
err = pci_alloc_irq_vectors(pdev, RVU_PF_INT_VEC_CNT,
761
-
RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX);
760
+
num_vec = pci_msix_vec_count(cptpf->pdev);
761
+
if (num_vec <= 0) {
762
+
err = -EINVAL;
763
+
goto clear_drvdata;
764
+
}
765
+
766
+
err = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSIX);
762
767
if (err < 0) {
763
768
dev_err(dev, "Request for %d msix vectors failed\n",
764
769
RVU_PF_INT_VEC_CNT);
···
828
823
829
824
cptpf_sriov_disable(pdev);
830
825
otx2_cpt_unregister_dl(cptpf);
826
+
827
+
/* Cleanup Inline CPT LF's if attached */
828
+
if (cptpf->lfs.lfs_num)
829
+
otx2_inline_cptlf_cleanup(&cptpf->lfs);
830
+
831
+
if (cptpf->cpt1_lfs.lfs_num)
832
+
otx2_inline_cptlf_cleanup(&cptpf->cpt1_lfs);
833
+
831
834
/* Delete sysfs entry created for kernel VF limits */
832
835
sysfs_remove_group(&pdev->dev.kobj, &cptpf_sysfs_group);
833
836
/* Cleanup engine groups */
+58
-10
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
+58
-10
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
···
199
199
return send_inline_ipsec_inbound_msg(cptpf, req->sso_pf_func, 0);
200
200
}
201
201
202
+
int
203
+
otx2_inline_cptlf_setup(struct otx2_cptpf_dev *cptpf,
204
+
struct otx2_cptlfs_info *lfs, u8 egrp, int num_lfs)
205
+
{
206
+
int ret;
207
+
208
+
ret = otx2_cptlf_init(lfs, 1 << egrp, OTX2_CPT_QUEUE_HI_PRIO, 1);
209
+
if (ret) {
210
+
dev_err(&cptpf->pdev->dev,
211
+
"LF configuration failed for RX inline ipsec.\n");
212
+
return ret;
213
+
}
214
+
215
+
/* Get msix offsets for attached LFs */
216
+
ret = otx2_cpt_msix_offset_msg(lfs);
217
+
if (ret)
218
+
goto cleanup_lf;
219
+
220
+
/* Register for CPT LF Misc interrupts */
221
+
ret = otx2_cptlf_register_misc_interrupts(lfs);
222
+
if (ret)
223
+
goto free_irq;
224
+
225
+
return 0;
226
+
free_irq:
227
+
otx2_cptlf_unregister_misc_interrupts(lfs);
228
+
cleanup_lf:
229
+
otx2_cptlf_shutdown(lfs);
230
+
return ret;
231
+
}
232
+
233
+
void
234
+
otx2_inline_cptlf_cleanup(struct otx2_cptlfs_info *lfs)
235
+
{
236
+
/* Unregister misc interrupt */
237
+
otx2_cptlf_unregister_misc_interrupts(lfs);
238
+
239
+
/* Cleanup LFs */
240
+
otx2_cptlf_shutdown(lfs);
241
+
}
242
+
202
243
static int handle_msg_rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf,
203
244
struct mbox_msghdr *req)
204
245
{
···
267
226
otx2_cptlf_set_dev_info(&cptpf->lfs, cptpf->pdev, cptpf->reg_base,
268
227
&cptpf->afpf_mbox, BLKADDR_CPT0);
269
228
cptpf->lfs.global_slot = 0;
270
-
ret = otx2_cptlf_init(&cptpf->lfs, 1 << egrp, OTX2_CPT_QUEUE_HI_PRIO,
271
-
num_lfs);
229
+
ret = otx2_inline_cptlf_setup(cptpf, &cptpf->lfs, egrp, num_lfs);
272
230
if (ret) {
273
-
dev_err(&cptpf->pdev->dev,
274
-
"LF configuration failed for RX inline ipsec.\n");
231
+
dev_err(&cptpf->pdev->dev, "Inline-Ipsec CPT0 LF setup failed.\n");
275
232
return ret;
276
233
}
277
234
···
279
240
cptpf->reg_base, &cptpf->afpf_mbox,
280
241
BLKADDR_CPT1);
281
242
cptpf->cpt1_lfs.global_slot = num_lfs;
282
-
ret = otx2_cptlf_init(&cptpf->cpt1_lfs, 1 << egrp,
283
-
OTX2_CPT_QUEUE_HI_PRIO, num_lfs);
243
+
ret = otx2_inline_cptlf_setup(cptpf, &cptpf->cpt1_lfs, egrp,
244
+
num_lfs);
284
245
if (ret) {
285
-
dev_err(&cptpf->pdev->dev,
286
-
"LF configuration failed for RX inline ipsec.\n");
246
+
dev_err(&cptpf->pdev->dev, "Inline CPT1 LF setup failed.\n");
287
247
goto lf_cleanup;
288
248
}
289
249
cptpf->rsrc_req_blkaddr = 0;
···
295
257
return 0;
296
258
297
259
lf1_cleanup:
298
-
otx2_cptlf_shutdown(&cptpf->cpt1_lfs);
260
+
otx2_inline_cptlf_cleanup(&cptpf->cpt1_lfs);
299
261
lf_cleanup:
300
-
otx2_cptlf_shutdown(&cptpf->lfs);
262
+
otx2_inline_cptlf_cleanup(&cptpf->lfs);
301
263
return ret;
302
264
}
303
265
···
452
414
struct otx2_cptlfs_info *lfs = &cptpf->lfs;
453
415
struct device *dev = &cptpf->pdev->dev;
454
416
struct cpt_rd_wr_reg_msg *rsp_rd_wr;
417
+
struct msix_offset_rsp *rsp_msix;
418
+
int i;
455
419
456
420
if (msg->id >= MBOX_MSG_MAX) {
457
421
dev_err(dev, "MBOX msg with unknown ID %d\n", msg->id);
···
471
431
case MBOX_MSG_READY:
472
432
cptpf->pf_id = (msg->pcifunc >> RVU_PFVF_PF_SHIFT) &
473
433
RVU_PFVF_PF_MASK;
434
+
break;
435
+
case MBOX_MSG_MSIX_OFFSET:
436
+
rsp_msix = (struct msix_offset_rsp *) msg;
437
+
for (i = 0; i < rsp_msix->cptlfs; i++)
438
+
lfs->lf[i].msix_offset = rsp_msix->cptlf_msixoff[i];
439
+
440
+
for (i = 0; i < rsp_msix->cpt1_lfs; i++)
441
+
lfs->lf[i].msix_offset = rsp_msix->cpt1_lf_msixoff[i];
474
442
break;
475
443
case MBOX_MSG_CPT_RD_WR_REGISTER:
476
444
rsp_rd_wr = (struct cpt_rd_wr_reg_msg *)msg;
+9
-3
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
+9
-3
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
···
246
246
/* Unregister crypto algorithms */
247
247
otx2_cpt_crypto_exit(lfs->pdev, THIS_MODULE);
248
248
/* Unregister LFs interrupts */
249
-
otx2_cptlf_unregister_interrupts(lfs);
249
+
otx2_cptlf_unregister_misc_interrupts(lfs);
250
+
otx2_cptlf_unregister_done_interrupts(lfs);
250
251
/* Cleanup LFs software side */
251
252
lf_sw_cleanup(lfs);
252
253
/* Free instruction queues */
···
301
300
goto cleanup_lf;
302
301
303
302
/* Register LFs interrupts */
304
-
ret = otx2_cptlf_register_interrupts(lfs);
303
+
ret = otx2_cptlf_register_misc_interrupts(lfs);
304
+
if (ret)
305
+
goto cleanup_lf_sw;
306
+
307
+
ret = otx2_cptlf_register_done_interrupts(lfs);
305
308
if (ret)
306
309
goto cleanup_lf_sw;
307
310
···
326
321
disable_irqs:
327
322
otx2_cptlf_free_irqs_affinity(lfs);
328
323
unregister_intr:
329
-
otx2_cptlf_unregister_interrupts(lfs);
324
+
otx2_cptlf_unregister_misc_interrupts(lfs);
325
+
otx2_cptlf_unregister_done_interrupts(lfs);
330
326
cleanup_lf_sw:
331
327
lf_sw_cleanup(lfs);
332
328
cleanup_lf: