Merge tag 'renesas-pinctrl-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

+13

Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml

··· 49 49 gpio-ranges: 50 50 maxItems: 1 51 51 52 + interrupt-controller: true 53 + 54 + '#interrupt-cells': 55 + const: 2 56 + description: 57 + The first cell contains the global GPIO port index, constructed using the 58 + RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> 59 + and the second cell is used to specify the flag. 60 + E.g. "interrupts = <RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>;" if P08_6 is 61 + being used as an interrupt. 62 + 52 63 clocks: 53 64 maxItems: 1 54 65 ··· 150 139 gpio-controller; 151 140 #gpio-cells = <2>; 152 141 gpio-ranges = <&pinctrl 0 0 288>; 142 + interrupt-controller; 143 + #interrupt-cells = <2>; 153 144 power-domains = <&cpg>; 154 145 155 146 serial0-pins {

+2

drivers/pinctrl/renesas/Kconfig

··· 308 308 bool "pin control support for RZ/N2H and RZ/T2H" if COMPILE_TEST 309 309 depends on 64BIT && OF 310 310 select GPIOLIB 311 + select GPIOLIB_IRQCHIP 311 312 select GENERIC_PINCTRL_GROUPS 312 313 select GENERIC_PINMUX_FUNCTIONS 313 314 select GENERIC_PINCONF 315 + select IRQ_DOMAIN_HIERARCHY 314 316 help 315 317 This selects GPIO and pinctrl driver for Renesas RZ/T2H 316 318 platforms.

+239 -9

drivers/pinctrl/renesas/pinctrl-rzt2h.c

··· 18 18 #include <linux/module.h> 19 19 #include <linux/mutex.h> 20 20 #include <linux/of_device.h> 21 + #include <linux/of_irq.h> 21 22 #include <linux/platform_device.h> 22 23 #include <linux/pm_runtime.h> 23 24 #include <linux/spinlock.h> ··· 52 51 53 52 #define PFC_MASK GENMASK_ULL(5, 0) 54 53 #define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8)) 54 + #define PFC_FUNC_INTERRUPT 0 55 55 56 56 /* 57 57 * Use 16 lower bits [15:0] for pin identifier ··· 65 63 #define RZT2H_PIN_ID_TO_PIN(id) ((id) % RZT2H_PINS_PER_PORT) 66 64 67 65 #define RZT2H_MAX_SAFETY_PORTS 12 66 + 67 + #define RZT2H_INTERRUPTS_START 16 68 + #define RZT2H_INTERRUPTS_NUM 17 68 69 69 70 struct rzt2h_pinctrl_data { 70 71 unsigned int n_port_pins; ··· 84 79 struct device *dev; 85 80 struct gpio_chip gpio_chip; 86 81 struct pinctrl_gpio_range gpio_range; 82 + DECLARE_BITMAP(used_irqs, RZT2H_INTERRUPTS_NUM); 87 83 spinlock_t lock; /* lock read/write registers */ 88 84 struct mutex mutex; /* serialize adding groups and functions */ 89 85 bool safety_port_enabled; 86 + atomic_t wakeup_path; 90 87 }; 91 88 92 89 #define RZT2H_GET_BASE(pctrl, port) \ ··· 126 119 return (pincfg & BIT(pin)) ? 0 : -EINVAL; 127 120 } 128 121 122 + static void rzt2h_pinctrl_set_gpio_en(struct rzt2h_pinctrl *pctrl, 123 + u8 port, u8 pin, bool en) 124 + { 125 + u8 reg = rzt2h_pinctrl_readb(pctrl, port, PMC(port)); 126 + 127 + if (en) 128 + reg &= ~BIT(pin); 129 + else 130 + reg |= BIT(pin); 131 + 132 + rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port)); 133 + } 134 + 129 135 static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl, 130 136 u8 port, u8 pin, u8 func) 131 137 { ··· 153 133 rzt2h_pinctrl_writew(pctrl, port, reg16, PM(port)); 154 134 155 135 /* Temporarily switch to GPIO mode with PMC register */ 156 - reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port)); 157 - rzt2h_pinctrl_writeb(pctrl, port, reg16 & ~BIT(pin), PMC(port)); 136 + rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true); 158 137 159 138 /* Select Pin function mode with PFC register */ 160 139 reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port)); ··· 161 142 rzt2h_pinctrl_writeq(pctrl, port, reg64 | ((u64)func << (pin * 8)), PFC(port)); 162 143 163 144 /* Switch to Peripheral pin function with PMC register */ 164 - reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port)); 165 - rzt2h_pinctrl_writeb(pctrl, port, reg16 | BIT(pin), PMC(port)); 145 + rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false); 166 146 } 167 147 168 148 static int rzt2h_pinctrl_set_mux(struct pinctrl_dev *pctldev, ··· 465 447 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 466 448 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 467 449 int ret; 468 - u8 reg; 469 450 470 451 ret = rzt2h_validate_pin(pctrl, offset); 471 452 if (ret) ··· 477 460 guard(spinlock_irqsave)(&pctrl->lock); 478 461 479 462 /* Select GPIO mode in PMC Register */ 480 - reg = rzt2h_pinctrl_readb(pctrl, port, PMC(port)); 481 - reg &= ~BIT(bit); 482 - rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port)); 463 + rzt2h_pinctrl_set_gpio_en(pctrl, port, bit, true); 483 464 484 465 return 0; 485 466 } ··· 501 486 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 502 487 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 503 488 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 489 + u64 reg64; 504 490 u16 reg; 505 491 int ret; 506 492 ··· 509 493 if (ret) 510 494 return ret; 511 495 512 - if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) 496 + guard(spinlock_irqsave)(&pctrl->lock); 497 + 498 + if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) { 499 + /* 500 + * When a GPIO is being requested as an IRQ, the pinctrl 501 + * framework expects to be able to read the GPIO's direction. 502 + * IRQ function is separate from GPIO, and enabling it takes the 503 + * pin out of GPIO mode. 504 + * At this point, .child_to_parent_hwirq() has already been 505 + * called to enable the IRQ function. 506 + * Default to input direction for IRQ function. 507 + */ 508 + reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port)); 509 + reg64 = (reg64 >> (bit * 8)) & PFC_MASK; 510 + if (reg64 == PFC_FUNC_INTERRUPT) 511 + return GPIO_LINE_DIRECTION_IN; 512 + 513 513 return -EINVAL; 514 + } 514 515 515 516 reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 516 517 reg = (reg >> (bit * 2)) & PM_MASK; ··· 650 617 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 651 618 }; 652 619 620 + /* 621 + * Interrupts 0-15 are for INTCPUn, which are not exposed externally. 622 + * Interrupts 16-31 are for IRQn. SEI is 32. 623 + * This table matches the information found in User Manual's Section 624 + * 17.5, Multiplexed Pin Configurations, Tables 17.5 to 17.40, on the 625 + * Interrupt rows. 626 + * RZ/N2H has the same GPIO to IRQ mapping, except for the pins which 627 + * are not present. 628 + */ 629 + static const u8 rzt2h_gpio_irq_map[] = { 630 + 32, 16, 17, 18, 19, 0, 20, 21, 631 + 22, 0, 0, 0, 0, 0, 0, 0, 632 + 23, 24, 25, 26, 27, 0, 0, 0, 633 + 0, 0, 28, 29, 30, 31, 0, 0, 634 + 0, 0, 0, 0, 0, 32, 16, 17, 635 + 18, 19, 20, 21, 22, 0, 0, 0, 636 + 0, 0, 24, 25, 26, 27, 0, 28, 637 + 29, 30, 31, 0, 0, 0, 0, 0, 638 + 0, 0, 0, 0, 0, 24, 32, 16, 639 + 0, 0, 0, 0, 0, 0, 0, 0, 640 + 20, 23, 17, 18, 19, 0, 16, 25, 641 + 29, 20, 21, 22, 23, 0, 0, 0, 642 + 0, 0, 0, 0, 17, 0, 0, 18, 643 + 0, 0, 19, 0, 0, 20, 0, 30, 644 + 21, 0, 0, 22, 0, 0, 24, 25, 645 + 0, 0, 0, 0, 0, 16, 17, 0, 646 + 18, 0, 0, 26, 27, 0, 0, 0, 647 + 28, 29, 30, 31, 0, 0, 0, 0, 648 + 23, 31, 32, 16, 17, 18, 19, 20, 649 + 0, 0, 0, 0, 0, 0, 0, 0, 650 + 0, 0, 0, 0, 0, 0, 0, 0, 651 + 0, 0, 0, 0, 0, 0, 0, 0, 652 + 27, 0, 0, 21, 22, 23, 24, 25, 653 + 26, 0, 0, 0, 0, 0, 0, 0, 654 + 27, 28, 29, 30, 31, 0, 0, 0, 655 + 0, 0, 0, 0, 0, 0, 0, 0, 656 + 0, 0, 0, 0, 0, 28, 32, 16, 657 + 17, 18, 19, 0, 0, 0, 0, 20, 658 + 21, 22, 23, 0, 0, 0, 0, 0, 659 + 0, 0, 0, 0, 24, 25, 0, 0, 660 + 0, 0, 26, 27, 0, 0, 0, 30, 661 + 0, 29, 0, 0, 0, 0, 0, 0, 662 + 0, 0, 0, 0, 0, 0, 0, 0, 663 + 0, 0, 0, 28, 29, 30, 31, 0, 664 + 0, 0, 0, 0, 0, 0, 0, 30, 665 + 0, 0, 0, 0, 0, 0, 0, 0, 666 + }; 667 + 668 + static void rzt2h_gpio_irq_disable(struct irq_data *d) 669 + { 670 + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 671 + unsigned int hwirq = irqd_to_hwirq(d); 672 + 673 + irq_chip_disable_parent(d); 674 + gpiochip_disable_irq(gc, hwirq); 675 + } 676 + 677 + static void rzt2h_gpio_irq_enable(struct irq_data *d) 678 + { 679 + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 680 + unsigned int hwirq = irqd_to_hwirq(d); 681 + 682 + gpiochip_enable_irq(gc, hwirq); 683 + irq_chip_enable_parent(d); 684 + } 685 + 686 + static int rzt2h_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 687 + { 688 + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 689 + struct rzt2h_pinctrl *pctrl = container_of(gc, struct rzt2h_pinctrl, gpio_chip); 690 + int ret; 691 + 692 + ret = irq_chip_set_wake_parent(d, on); 693 + if (ret) 694 + return ret; 695 + 696 + /* 697 + * If any of the IRQs are in use, put the entire pin controller on the 698 + * device wakeup path. 699 + */ 700 + if (on) 701 + atomic_inc(&pctrl->wakeup_path); 702 + else 703 + atomic_dec(&pctrl->wakeup_path); 704 + 705 + return 0; 706 + } 707 + 708 + static const struct irq_chip rzt2h_gpio_irqchip = { 709 + .name = "rzt2h-gpio", 710 + .irq_disable = rzt2h_gpio_irq_disable, 711 + .irq_enable = rzt2h_gpio_irq_enable, 712 + .irq_mask = irq_chip_mask_parent, 713 + .irq_unmask = irq_chip_unmask_parent, 714 + .irq_set_type = irq_chip_set_type_parent, 715 + .irq_set_wake = rzt2h_gpio_irq_set_wake, 716 + .irq_eoi = irq_chip_eoi_parent, 717 + .irq_set_affinity = irq_chip_set_affinity_parent, 718 + .flags = IRQCHIP_IMMUTABLE, 719 + GPIOCHIP_IRQ_RESOURCE_HELPERS, 720 + }; 721 + 722 + static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 723 + unsigned int child, 724 + unsigned int child_type, 725 + unsigned int *parent, 726 + unsigned int *parent_type) 727 + { 728 + struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc); 729 + u8 port = RZT2H_PIN_ID_TO_PORT(child); 730 + u8 pin = RZT2H_PIN_ID_TO_PIN(child); 731 + u8 parent_irq; 732 + 733 + parent_irq = rzt2h_gpio_irq_map[child]; 734 + if (parent_irq < RZT2H_INTERRUPTS_START) 735 + return -EINVAL; 736 + 737 + if (test_and_set_bit(parent_irq - RZT2H_INTERRUPTS_START, 738 + pctrl->used_irqs)) 739 + return -EBUSY; 740 + 741 + rzt2h_pinctrl_set_pfc_mode(pctrl, port, pin, PFC_FUNC_INTERRUPT); 742 + 743 + *parent = parent_irq; 744 + *parent_type = child_type; 745 + 746 + return 0; 747 + } 748 + 749 + static void rzt2h_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 750 + unsigned int nr_irqs) 751 + { 752 + struct irq_data *d = irq_domain_get_irq_data(domain, virq); 753 + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 754 + struct rzt2h_pinctrl *pctrl = container_of(gc, struct rzt2h_pinctrl, gpio_chip); 755 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 756 + u8 port = RZT2H_PIN_ID_TO_PORT(hwirq); 757 + u8 pin = RZT2H_PIN_ID_TO_PIN(hwirq); 758 + 759 + if (test_and_clear_bit(hwirq - RZT2H_INTERRUPTS_START, pctrl->used_irqs)) 760 + rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false); 761 + 762 + irq_domain_free_irqs_common(domain, virq, nr_irqs); 763 + } 764 + 765 + static void rzt2h_gpio_init_irq_valid_mask(struct gpio_chip *gc, 766 + unsigned long *valid_mask, 767 + unsigned int ngpios) 768 + { 769 + struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc); 770 + unsigned int offset; 771 + 772 + for (offset = 0; offset < ngpios; offset++) { 773 + if (!rzt2h_gpio_irq_map[offset] || rzt2h_validate_pin(pctrl, offset)) 774 + clear_bit(offset, valid_mask); 775 + } 776 + } 777 + 653 778 static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl) 654 779 { 655 780 struct pinctrl_gpio_range *range = &pctrl->gpio_range; 656 781 struct gpio_chip *chip = &pctrl->gpio_chip; 782 + struct device_node *np = pctrl->dev->of_node; 783 + struct irq_domain *parent_domain; 657 784 struct device *dev = pctrl->dev; 658 785 struct of_phandle_args of_args; 786 + struct device_node *parent_np; 787 + struct gpio_irq_chip *girq; 659 788 int ret; 789 + 790 + parent_np = of_irq_find_parent(np); 791 + if (!parent_np) 792 + return -ENXIO; 793 + 794 + parent_domain = irq_find_host(parent_np); 795 + of_node_put(parent_np); 796 + if (!parent_domain) 797 + return -EPROBE_DEFER; 660 798 661 799 ret = of_parse_phandle_with_fixed_args(dev->of_node, "gpio-ranges", 3, 0, &of_args); 662 800 if (ret) ··· 851 647 chip->get = rzt2h_gpio_get; 852 648 chip->set = rzt2h_gpio_set; 853 649 chip->label = dev_name(dev); 650 + 651 + if (of_property_present(np, "interrupt-controller")) { 652 + girq = &chip->irq; 653 + gpio_irq_chip_set_chip(girq, &rzt2h_gpio_irqchip); 654 + girq->fwnode = dev_fwnode(pctrl->dev); 655 + girq->parent_domain = parent_domain; 656 + girq->child_to_parent_hwirq = rzt2h_gpio_child_to_parent_hwirq; 657 + girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; 658 + girq->child_irq_domain_ops.free = rzt2h_gpio_irq_domain_free; 659 + girq->init_valid_mask = rzt2h_gpio_init_irq_valid_mask; 660 + } 854 661 855 662 range->id = 0; 856 663 range->pin_base = 0; ··· 1007 792 { /* sentinel */ } 1008 793 }; 1009 794 795 + static int rzt2h_pinctrl_suspend_noirq(struct device *dev) 796 + { 797 + struct rzt2h_pinctrl *pctrl = dev_get_drvdata(dev); 798 + 799 + if (atomic_read(&pctrl->wakeup_path)) 800 + device_set_wakeup_path(dev); 801 + 802 + return 0; 803 + } 804 + 805 + static const struct dev_pm_ops rzt2h_pinctrl_pm_ops = { 806 + NOIRQ_SYSTEM_SLEEP_PM_OPS(rzt2h_pinctrl_suspend_noirq, NULL) 807 + }; 808 + 1010 809 static struct platform_driver rzt2h_pinctrl_driver = { 1011 810 .driver = { 1012 811 .name = DRV_NAME, 1013 812 .of_match_table = of_match_ptr(rzt2h_pinctrl_of_table), 813 + .pm = pm_sleep_ptr(&rzt2h_pinctrl_pm_ops), 1014 814 .suppress_bind_attrs = true, 1015 815 }, 1016 816 .probe = rzt2h_pinctrl_probe,

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