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net/mlx5: Add IFC bits to support RSS for IPSec offload

This adds the capabilities, ipsec_next_header and inner/outer
l4_type_ext fields to support RSS for the decrypted packets.

These fields are specifically for firmware steering. HWS validation
logic is updated to correctly handle the changes, ensuring the
unsupported fields are not set.

Besides, reserved_at_c4 is fixed to reserved_at_d4 to reflect the
accurate offset within the structure.

Signed-off-by: Jianbo Liu <jianbol@nvidia.com>
Reviewed-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1752734895-257735-2-git-send-email-tariqt@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>

authored by

Jianbo Liu and committed by
Leon Romanovsky 438794e9 cd1746cb

+26 -12
+8 -5
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
··· 727 727 u32 *s_ipv6, *d_ipv6; 728 728 729 729 if (HWS_IS_FLD_SET_SZ(match_param, outer_headers.l4_type, 0x2) || 730 - HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_c2, 0xe) || 731 - HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_c4, 0x4)) { 730 + HWS_IS_FLD_SET_SZ(match_param, outer_headers.l4_type_ext, 0x4) || 731 + HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_c6, 0xa) || 732 + HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_d4, 0x4)) { 732 733 mlx5hws_err(cd->ctx, "Unsupported outer parameters set\n"); 733 734 return -EINVAL; 734 735 } ··· 904 903 u32 *s_ipv6, *d_ipv6; 905 904 906 905 if (HWS_IS_FLD_SET_SZ(match_param, inner_headers.l4_type, 0x2) || 907 - HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_c2, 0xe) || 908 - HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_c4, 0x4)) { 906 + HWS_IS_FLD_SET_SZ(match_param, inner_headers.l4_type_ext, 0x4) || 907 + HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_c6, 0xa) || 908 + HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_d4, 0x4)) { 909 909 mlx5hws_err(cd->ctx, "Unsupported inner parameters set\n"); 910 910 return -EINVAL; 911 911 } ··· 1281 1279 struct mlx5hws_definer_fc *curr_fc; 1282 1280 1283 1281 if (HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1a0, 0x8) || 1284 - HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1b8, 0x8) || 1282 + HWS_IS_FLD_SET_SZ(match_param, 1283 + misc_parameters_2.ipsec_next_header, 0x8) || 1285 1284 HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1c0, 0x40) || 1286 1285 HWS_IS_FLD_SET(match_param, misc_parameters_2.macsec_syndrome) || 1287 1286 HWS_IS_FLD_SET(match_param, misc_parameters_2.ipsec_syndrome)) {
+18 -7
include/linux/mlx5/mlx5_ifc.h
··· 420 420 421 421 /* Table 2170 - Flow Table Fields Supported 2 Format */ 422 422 struct mlx5_ifc_flow_table_fields_supported_2_bits { 423 - u8 reserved_at_0[0x2]; 423 + u8 inner_l4_type_ext[0x1]; 424 + u8 outer_l4_type_ext[0x1]; 424 425 u8 inner_l4_type[0x1]; 425 426 u8 outer_l4_type[0x1]; 426 427 u8 reserved_at_4[0xa]; ··· 430 429 u8 tunnel_header_0_1[0x1]; 431 430 u8 reserved_at_11[0xf]; 432 431 433 - u8 reserved_at_20[0x60]; 432 + u8 reserved_at_20[0xf]; 433 + u8 ipsec_next_header[0x1]; 434 + u8 reserved_at_30[0x10]; 435 + 436 + u8 reserved_at_40[0x40]; 434 437 }; 435 438 436 439 struct mlx5_ifc_flow_table_prop_layout_bits { ··· 557 552 MLX5_PACKET_L4_TYPE_UDP, 558 553 }; 559 554 555 + enum { 556 + MLX5_PACKET_L4_TYPE_EXT_NONE, 557 + MLX5_PACKET_L4_TYPE_EXT_TCP, 558 + MLX5_PACKET_L4_TYPE_EXT_UDP, 559 + MLX5_PACKET_L4_TYPE_EXT_ICMP, 560 + }; 561 + 560 562 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 561 563 u8 smac_47_16[0x20]; 562 564 ··· 590 578 u8 tcp_dport[0x10]; 591 579 592 580 u8 l4_type[0x2]; 593 - u8 reserved_at_c2[0xe]; 581 + u8 l4_type_ext[0x4]; 582 + u8 reserved_at_c6[0xa]; 594 583 u8 ipv4_ihl[0x4]; 595 - u8 reserved_at_c4[0x4]; 596 - 584 + u8 reserved_at_d4[0x4]; 597 585 u8 ttl_hoplimit[0x8]; 598 586 599 587 u8 udp_sport[0x10]; ··· 701 689 u8 metadata_reg_a[0x20]; 702 690 703 691 u8 reserved_at_1a0[0x8]; 704 - 705 692 u8 macsec_syndrome[0x8]; 706 693 u8 ipsec_syndrome[0x8]; 707 - u8 reserved_at_1b8[0x8]; 694 + u8 ipsec_next_header[0x8]; 708 695 709 696 u8 reserved_at_1c0[0x40]; 710 697 };