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Merge tag 'dt-vt8500-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt

VT8500 DTS ARM changes for v6.17

1. Several dtbs_check cleanups.
2. Add missing cache topology - L2 cache controller on WM8850/WM895.

* tag 'dt-vt8500-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
ARM: dts: vt8500: Add L2 cache controller on WM8850/WM8950
ARM: dts: vt8500: Fix the unit address of the VT8500 LCD controller
ARM: dts: vt8500: Use generic node name for the SD/MMC controller
ARM: dts: vt8500: Move memory nodes to board dts and fix addr/size
ARM: dts: vt8500: Add node address and reg in CPU nodes

Link: https://lore.kernel.org/r/20250709184800.168462-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 43af11e1 2ee49a61

+56 -38
+5
arch/arm/boot/dts/vt8500/vt8500-bv07.dts
··· 10 10 11 11 / { 12 12 model = "Benign BV07 Netbook"; 13 + 14 + memory@0 { 15 + device_type = "memory"; 16 + reg = <0x0 0x8000000>; 17 + }; 13 18 }; 14 19 15 20 &fb {
+4 -8
arch/arm/boot/dts/vt8500/vt8500.dtsi
··· 11 11 compatible = "via,vt8500"; 12 12 13 13 cpus { 14 - #address-cells = <0>; 14 + #address-cells = <1>; 15 15 #size-cells = <0>; 16 16 17 - cpu { 17 + cpu@0 { 18 18 device_type = "cpu"; 19 19 compatible = "arm,arm926ej-s"; 20 + reg = <0x0>; 20 21 }; 21 - }; 22 - 23 - memory { 24 - device_type = "memory"; 25 - reg = <0x0 0x0>; 26 22 }; 27 23 28 24 aliases { ··· 122 126 interrupts = <43>; 123 127 }; 124 128 125 - fb: fb@d8050800 { 129 + fb: lcd-controller@d800e400 { 126 130 compatible = "via,vt8500-fb"; 127 131 reg = <0xd800e400 0x400>; 128 132 interrupts = <12>;
+5
arch/arm/boot/dts/vt8500/wm8505-ref.dts
··· 10 10 11 11 / { 12 12 model = "Wondermedia WM8505 Netbook"; 13 + 14 + memory@0 { 15 + device_type = "memory"; 16 + reg = <0x0 0x8000000>; 17 + }; 13 18 }; 14 19 15 20 &fb {
+4 -8
arch/arm/boot/dts/vt8500/wm8505.dtsi
··· 11 11 compatible = "wm,wm8505"; 12 12 13 13 cpus { 14 - #address-cells = <0>; 14 + #address-cells = <1>; 15 15 #size-cells = <0>; 16 16 17 - cpu { 17 + cpu@0 { 18 18 device_type = "cpu"; 19 19 compatible = "arm,arm926ej-s"; 20 + reg = <0x0>; 20 21 }; 21 - }; 22 - 23 - memory { 24 - device_type = "memory"; 25 - reg = <0x0 0x0>; 26 22 }; 27 23 28 24 aliases { ··· 284 288 interrupts = <48>; 285 289 }; 286 290 287 - sdhc@d800a000 { 291 + mmc@d800a000 { 288 292 compatible = "wm,wm8505-sdhc"; 289 293 reg = <0xd800a000 0x400>; 290 294 interrupts = <20>, <21>;
+5
arch/arm/boot/dts/vt8500/wm8650-mid.dts
··· 10 10 11 11 / { 12 12 model = "Wondermedia WM8650-MID Tablet"; 13 + 14 + memory@0 { 15 + device_type = "memory"; 16 + reg = <0x0 0x10000000>; 17 + }; 13 18 }; 14 19 15 20 &fb {
+4 -8
arch/arm/boot/dts/vt8500/wm8650.dtsi
··· 11 11 compatible = "wm,wm8650"; 12 12 13 13 cpus { 14 - #address-cells = <0>; 14 + #address-cells = <1>; 15 15 #size-cells = <0>; 16 16 17 - cpu { 17 + cpu@0 { 18 18 device_type = "cpu"; 19 19 compatible = "arm,arm926ej-s"; 20 + reg = <0x0>; 20 21 }; 21 - }; 22 - 23 - memory { 24 - device_type = "memory"; 25 - reg = <0x0 0x0>; 26 22 }; 27 23 28 24 aliases { ··· 192 196 interrupts = <43>; 193 197 }; 194 198 195 - sdhc@d800a000 { 199 + mmc@d800a000 { 196 200 compatible = "wm,wm8505-sdhc"; 197 201 reg = <0xd800a000 0x400>; 198 202 interrupts = <20>, <21>;
+5
arch/arm/boot/dts/vt8500/wm8750-apc8750.dts
··· 11 11 12 12 / { 13 13 model = "VIA APC8750"; 14 + 15 + memory@0 { 16 + device_type = "memory"; 17 + reg = <0x0 0x20000000>; 18 + }; 14 19 }; 15 20 16 21 &pinctrl {
+4 -8
arch/arm/boot/dts/vt8500/wm8750.dtsi
··· 11 11 compatible = "wm,wm8750"; 12 12 13 13 cpus { 14 - #address-cells = <0>; 14 + #address-cells = <1>; 15 15 #size-cells = <0>; 16 16 17 - cpu { 17 + cpu@0 { 18 18 device_type = "cpu"; 19 19 compatible = "arm,arm1176jzf"; 20 + reg = <0x0>; 20 21 }; 21 - }; 22 - 23 - memory { 24 - device_type = "memory"; 25 - reg = <0x0 0x0>; 26 22 }; 27 23 28 24 aliases { ··· 324 328 interrupts = <48>; 325 329 }; 326 330 327 - sdhc@d800a000 { 331 + mmc@d800a000 { 328 332 compatible = "wm,wm8505-sdhc"; 329 333 reg = <0xd800a000 0x1000>; 330 334 interrupts = <20 21>;
+5
arch/arm/boot/dts/vt8500/wm8850-w70v2.dts
··· 22 22 brightness-levels = <0 40 60 80 100 130 190 255>; 23 23 default-brightness-level = <5>; 24 24 }; 25 + 26 + memory@0 { 27 + device_type = "memory"; 28 + reg = <0x0 0x20000000>; 29 + }; 25 30 }; 26 31 27 32 &fb {
+15 -6
arch/arm/boot/dts/vt8500/wm8850.dtsi
··· 18 18 device_type = "cpu"; 19 19 compatible = "arm,cortex-a9"; 20 20 reg = <0x0>; 21 + next-level-cache = <&l2_cache>; 21 22 }; 22 - }; 23 - 24 - memory { 25 - device_type = "memory"; 26 - reg = <0x0 0x0>; 27 23 }; 28 24 29 25 aliases { ··· 295 299 interrupts = <48>; 296 300 }; 297 301 298 - sdhc@d800a000 { 302 + mmc@d800a000 { 299 303 compatible = "wm,wm8505-sdhc"; 300 304 reg = <0xd800a000 0x1000>; 301 305 interrupts = <20 21>; ··· 309 313 reg = <0xd8004000 0x100>; 310 314 interrupts = <10>; 311 315 }; 316 + 317 + l2_cache: cache-controller@d9000000 { 318 + compatible = "arm,pl310-cache"; 319 + reg = <0xd9000000 0x1000>; 320 + arm,double-linefill = <1>; 321 + arm,dynamic-clock-gating = <1>; 322 + arm,shared-override; 323 + arm,standby-mode = <1>; 324 + cache-level = <2>; 325 + cache-unified; 326 + prefetch-data = <1>; 327 + prefetch-instr = <1>; 328 + }; 312 329 }; 313 330 };