Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers
Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg
clock and reset controllers. These provide the base clocks and resets
on the platform, enough to bring up all essential blocks including
PWRAP, MSDC and peripherals (UART, I2C, SPI).
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241017071708.38663-3-y.oudjana@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Yassine Oudjana
and committed by
Stephen Boyd
43c04ed7
ea1cca02
+777
+4
MAINTAINERS
+4
MAINTAINERS
···
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L: linux-clk@vger.kernel.org
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L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: drivers/clk/mediatek/clk-mt6735-apmixedsys.c
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F: drivers/clk/mediatek/clk-mt6735-infracfg.c
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F: drivers/clk/mediatek/clk-mt6735-pericfg.c
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F: drivers/clk/mediatek/clk-mt6735-topckgen.c
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F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
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F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h
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F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h
+9
drivers/clk/mediatek/Kconfig
+9
drivers/clk/mediatek/Kconfig
···
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help
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This driver supports MediaTek MT2712 vencsys clocks.
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config COMMON_CLK_MT6735
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tristate "Main clock drivers for MediaTek MT6735"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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help
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This enables drivers for clocks and resets provided
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by apmixedsys, topckgen, infracfg and pericfg on the
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MediaTek MT6735 SoC.
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config COMMON_CLK_MT6765
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bool "Clock driver for MediaTek MT6765"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+1
drivers/clk/mediatek/Makefile
+1
drivers/clk/mediatek/Makefile
···
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2
obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
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obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
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obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o
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obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
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obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
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obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
+138
drivers/clk/mediatek/clk-mt6735-apmixedsys.c
+138
drivers/clk/mediatek/clk-mt6735-apmixedsys.c
···
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+
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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+
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#include "clk-mtk.h"
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#include "clk-pll.h"
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+
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#include <dt-bindings/clock/mediatek,mt6735-apmixedsys.h>
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+
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#define AP_PLL_CON_5 0x014
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#define ARMPLL_CON0 0x200
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#define ARMPLL_CON1 0x204
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#define ARMPLL_PWR_CON0 0x20c
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#define MAINPLL_CON0 0x210
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#define MAINPLL_CON1 0x214
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#define MAINPLL_PWR_CON0 0x21c
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#define UNIVPLL_CON0 0x220
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#define UNIVPLL_CON1 0x224
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#define UNIVPLL_PWR_CON0 0x22c
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#define MMPLL_CON0 0x230
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#define MMPLL_CON1 0x234
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#define MMPLL_PWR_CON0 0x23c
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#define MSDCPLL_CON0 0x240
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#define MSDCPLL_CON1 0x244
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#define MSDCPLL_PWR_CON0 0x24c
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#define VENCPLL_CON0 0x250
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#define VENCPLL_CON1 0x254
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#define VENCPLL_PWR_CON0 0x25c
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#define TVDPLL_CON0 0x260
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#define TVDPLL_CON1 0x264
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#define TVDPLL_PWR_CON0 0x26c
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#define APLL1_CON0 0x270
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#define APLL1_CON1 0x274
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#define APLL1_CON2 0x278
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#define APLL1_PWR_CON0 0x280
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#define APLL2_CON0 0x284
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#define APLL2_CON1 0x288
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#define APLL2_CON2 0x28c
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#define APLL2_PWR_CON0 0x294
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+
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#define CON0_RST_BAR BIT(24)
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+
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _rst_bar_mask, \
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_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcwbits, _flags) { \
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.id = _id, \
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.name = _name, \
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.parent_name = "clk26m", \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.rst_bar_mask = _rst_bar_mask, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_chg_reg = _pcw_reg, \
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.pcwbits = _pcwbits, \
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.flags = _flags, \
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}
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+
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static const struct mtk_pll_data apmixedsys_plls[] = {
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PLL(CLK_APMIXED_ARMPLL, "armpll", ARMPLL_CON0, ARMPLL_PWR_CON0, 0x00000001, 0, ARMPLL_CON1, 24, 0, 0, 0, ARMPLL_CON1, 21, PLL_AO),
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PLL(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0, MAINPLL_PWR_CON0, 0xf0000101, CON0_RST_BAR, MAINPLL_CON1, 24, 0, 0, 0, MAINPLL_CON1, 21, HAVE_RST_BAR),
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PLL(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0, UNIVPLL_PWR_CON0, 0xfc000001, CON0_RST_BAR, UNIVPLL_CON1, 24, 0, 0, 0, UNIVPLL_CON1, 21, HAVE_RST_BAR),
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PLL(CLK_APMIXED_MMPLL, "mmpll", MMPLL_CON0, MMPLL_PWR_CON0, 0x00000001, 0, MMPLL_CON1, 24, 0, 0, 0, MMPLL_CON1, 21, 0),
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PLL(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0, MSDCPLL_PWR_CON0, 0x00000001, 0, MSDCPLL_CON1, 24, 0, 0, 0, MSDCPLL_CON1, 21, 0),
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PLL(CLK_APMIXED_VENCPLL, "vencpll", VENCPLL_CON0, VENCPLL_PWR_CON0, 0x00000001, CON0_RST_BAR, VENCPLL_CON1, 24, 0, 0, 0, VENCPLL_CON1, 21, HAVE_RST_BAR),
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PLL(CLK_APMIXED_TVDPLL, "tvdpll", TVDPLL_CON0, TVDPLL_PWR_CON0, 0x00000001, 0, TVDPLL_CON1, 24, 0, 0, 0, TVDPLL_CON1, 21, 0),
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PLL(CLK_APMIXED_APLL1, "apll1", APLL1_CON0, APLL1_PWR_CON0, 0x00000001, 0, APLL1_CON0, 4, APLL1_CON2, AP_PLL_CON_5, 0, APLL1_CON1, 31, 0),
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PLL(CLK_APMIXED_APLL2, "apll2", APLL2_CON0, APLL2_PWR_CON0, 0x00000001, 0, APLL2_CON0, 4, APLL2_CON2, AP_PLL_CON_5, 1, APLL2_CON1, 31, 0)
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};
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+
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static int clk_mt6735_apmixed_probe(struct platform_device *pdev)
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{
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void __iomem *base;
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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struct clk_hw_onecell_data *clk_data;
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int ret;
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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+
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clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixedsys_plls));
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if (!clk_data)
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return -ENOMEM;
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platform_set_drvdata(pdev, clk_data);
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ret = mtk_clk_register_plls(pdev->dev.of_node, apmixedsys_plls,
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ARRAY_SIZE(apmixedsys_plls), clk_data);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret);
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return ret;
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}
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ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
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clk_data);
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if (ret)
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dev_err(&pdev->dev,
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"Failed to register clock provider: %d\n", ret);
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return ret;
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}
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static void clk_mt6735_apmixed_remove(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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mtk_clk_unregister_plls(apmixedsys_plls, ARRAY_SIZE(apmixedsys_plls), clk_data);
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mtk_free_clk_data(clk_data);
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}
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static const struct of_device_id of_match_mt6735_apmixedsys[] = {
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{ .compatible = "mediatek,mt6735-apmixedsys" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_mt6735_apmixedsys);
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static struct platform_driver clk_mt6735_apmixedsys = {
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.probe = clk_mt6735_apmixed_probe,
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.remove = clk_mt6735_apmixed_remove,
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.driver = {
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.name = "clk-mt6735-apmixedsys",
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.of_match_table = of_match_mt6735_apmixedsys,
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},
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};
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module_platform_driver(clk_mt6735_apmixedsys);
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MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
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MODULE_DESCRIPTION("MediaTek MT6735 apmixedsys clock driver");
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MODULE_LICENSE("GPL");
+107
drivers/clk/mediatek/clk-mt6735-infracfg.c
+107
drivers/clk/mediatek/clk-mt6735-infracfg.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mediatek,mt6735-infracfg.h>
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#include <dt-bindings/reset/mediatek,mt6735-infracfg.h>
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#define INFRA_RST0 0x30
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#define INFRA_GLOBALCON_PDN0 0x40
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#define INFRA_PDN1 0x44
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#define INFRA_PDN_STA 0x48
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#define RST_NR_PER_BANK 32
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static struct mtk_gate_regs infra_cg_regs = {
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.set_ofs = INFRA_GLOBALCON_PDN0,
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.clr_ofs = INFRA_PDN1,
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.sta_ofs = INFRA_PDN_STA,
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};
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static const struct mtk_gate infracfg_gates[] = {
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GATE_MTK(CLK_INFRA_DBG, "dbg", "axi_sel", &infra_cg_regs, 0, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_GCE, "gce", "axi_sel", &infra_cg_regs, 1, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_TRBG, "trbg", "axi_sel", &infra_cg_regs, 2, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CPUM, "cpum", "axi_sel", &infra_cg_regs, 3, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_DEVAPC, "devapc", "axi_sel", &infra_cg_regs, 4, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_AUDIO, "audio", "aud_intbus_sel", &infra_cg_regs, 5, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_GCPU, "gcpu", "axi_sel", &infra_cg_regs, 6, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_L2C_SRAM, "l2csram", "axi_sel", &infra_cg_regs, 7, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_M4U, "m4u", "axi_sel", &infra_cg_regs, 8, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CLDMA, "cldma", "axi_sel", &infra_cg_regs, 12, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CONNMCU_BUS, "connmcu_bus", "axi_sel", &infra_cg_regs, 15, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_KP, "kp", "axi_sel", &infra_cg_regs, 16, &mtk_clk_gate_ops_setclr),
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GATE_MTK_FLAGS(CLK_INFRA_APXGPT, "apxgpt", "axi_sel", &infra_cg_regs, 18, &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL),
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GATE_MTK(CLK_INFRA_SEJ, "sej", "axi_sel", &infra_cg_regs, 19, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CCIF0_AP, "ccif0ap", "axi_sel", &infra_cg_regs, 20, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CCIF1_AP, "ccif1ap", "axi_sel", &infra_cg_regs, 21, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_PMIC_SPI, "pmicspi", "pmicspi_sel", &infra_cg_regs, 22, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_PMIC_WRAP, "pmicwrap", "axi_sel", &infra_cg_regs, 23, &mtk_clk_gate_ops_setclr)
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};
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static u16 infracfg_rst_bank_ofs[] = { INFRA_RST0 };
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static u16 infracfg_rst_idx_map[] = {
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[MT6735_INFRA_RST0_EMI_REG] = 0 * RST_NR_PER_BANK + 0,
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[MT6735_INFRA_RST0_DRAMC0_AO] = 0 * RST_NR_PER_BANK + 1,
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[MT6735_INFRA_RST0_AP_CIRQ_EINT] = 0 * RST_NR_PER_BANK + 3,
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[MT6735_INFRA_RST0_APXGPT] = 0 * RST_NR_PER_BANK + 4,
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[MT6735_INFRA_RST0_SCPSYS] = 0 * RST_NR_PER_BANK + 5,
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[MT6735_INFRA_RST0_KP] = 0 * RST_NR_PER_BANK + 6,
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[MT6735_INFRA_RST0_PMIC_WRAP] = 0 * RST_NR_PER_BANK + 7,
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[MT6735_INFRA_RST0_CLDMA_AO_TOP] = 0 * RST_NR_PER_BANK + 8,
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[MT6735_INFRA_RST0_USBSIF_TOP] = 0 * RST_NR_PER_BANK + 9,
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[MT6735_INFRA_RST0_EMI] = 0 * RST_NR_PER_BANK + 16,
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[MT6735_INFRA_RST0_CCIF] = 0 * RST_NR_PER_BANK + 17,
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[MT6735_INFRA_RST0_DRAMC0] = 0 * RST_NR_PER_BANK + 18,
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[MT6735_INFRA_RST0_EMI_AO_REG] = 0 * RST_NR_PER_BANK + 19,
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[MT6735_INFRA_RST0_CCIF_AO] = 0 * RST_NR_PER_BANK + 20,
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[MT6735_INFRA_RST0_TRNG] = 0 * RST_NR_PER_BANK + 21,
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[MT6735_INFRA_RST0_SYS_CIRQ] = 0 * RST_NR_PER_BANK + 22,
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[MT6735_INFRA_RST0_GCE] = 0 * RST_NR_PER_BANK + 23,
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[MT6735_INFRA_RST0_M4U] = 0 * RST_NR_PER_BANK + 24,
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[MT6735_INFRA_RST0_CCIF1] = 0 * RST_NR_PER_BANK + 25,
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[MT6735_INFRA_RST0_CLDMA_TOP_PD] = 0 * RST_NR_PER_BANK + 26
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};
73
+
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static const struct mtk_clk_rst_desc infracfg_resets = {
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = infracfg_rst_bank_ofs,
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.rst_bank_nr = ARRAY_SIZE(infracfg_rst_bank_ofs),
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.rst_idx_map = infracfg_rst_idx_map,
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.rst_idx_map_nr = ARRAY_SIZE(infracfg_rst_idx_map)
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};
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+
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static const struct mtk_clk_desc infracfg_clks = {
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.clks = infracfg_gates,
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.num_clks = ARRAY_SIZE(infracfg_gates),
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+
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.rst_desc = &infracfg_resets
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};
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+
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static const struct of_device_id of_match_mt6735_infracfg[] = {
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{ .compatible = "mediatek,mt6735-infracfg", .data = &infracfg_clks },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_mt6735_infracfg);
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+
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static struct platform_driver clk_mt6735_infracfg = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt6735-infracfg",
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.of_match_table = of_match_mt6735_infracfg,
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},
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};
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module_platform_driver(clk_mt6735_infracfg);
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MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
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MODULE_DESCRIPTION("MediaTek MT6735 infracfg clock and reset driver");
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MODULE_LICENSE("GPL");
+124
drivers/clk/mediatek/clk-mt6735-pericfg.c
+124
drivers/clk/mediatek/clk-mt6735-pericfg.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
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+
* Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
4
+
*/
5
+
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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+
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#include "clk-gate.h"
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#include "clk-mtk.h"
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+
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#include <dt-bindings/clock/mediatek,mt6735-pericfg.h>
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#include <dt-bindings/reset/mediatek,mt6735-pericfg.h>
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+
15
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#define PERI_GLOBALCON_RST0 0x00
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#define PERI_GLOBALCON_RST1 0x04
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#define PERI_GLOBALCON_PDN0_SET 0x08
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#define PERI_GLOBALCON_PDN0_CLR 0x10
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#define PERI_GLOBALCON_PDN0_STA 0x18
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#define RST_NR_PER_BANK 32
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+
23
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static struct mtk_gate_regs peri_cg_regs = {
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.set_ofs = PERI_GLOBALCON_PDN0_SET,
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.clr_ofs = PERI_GLOBALCON_PDN0_CLR,
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.sta_ofs = PERI_GLOBALCON_PDN0_STA,
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};
28
+
29
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static const struct mtk_gate pericfg_gates[] = {
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GATE_MTK(CLK_PERI_DISP_PWM, "disp_pwm", "disppwm_sel", &peri_cg_regs, 0, &mtk_clk_gate_ops_setclr),
31
+
GATE_MTK(CLK_PERI_THERM, "therm", "axi_sel", &peri_cg_regs, 1, &mtk_clk_gate_ops_setclr),
32
+
GATE_MTK(CLK_PERI_PWM1, "pwm1", "axi_sel", &peri_cg_regs, 2, &mtk_clk_gate_ops_setclr),
33
+
GATE_MTK(CLK_PERI_PWM2, "pwm2", "axi_sel", &peri_cg_regs, 3, &mtk_clk_gate_ops_setclr),
34
+
GATE_MTK(CLK_PERI_PWM3, "pwm3", "axi_sel", &peri_cg_regs, 4, &mtk_clk_gate_ops_setclr),
35
+
GATE_MTK(CLK_PERI_PWM4, "pwm4", "axi_sel", &peri_cg_regs, 5, &mtk_clk_gate_ops_setclr),
36
+
GATE_MTK(CLK_PERI_PWM5, "pwm5", "axi_sel", &peri_cg_regs, 6, &mtk_clk_gate_ops_setclr),
37
+
GATE_MTK(CLK_PERI_PWM6, "pwm6", "axi_sel", &peri_cg_regs, 7, &mtk_clk_gate_ops_setclr),
38
+
GATE_MTK(CLK_PERI_PWM7, "pwm7", "axi_sel", &peri_cg_regs, 8, &mtk_clk_gate_ops_setclr),
39
+
GATE_MTK(CLK_PERI_PWM, "pwm", "axi_sel", &peri_cg_regs, 9, &mtk_clk_gate_ops_setclr),
40
+
GATE_MTK(CLK_PERI_USB0, "usb0", "usb20_sel", &peri_cg_regs, 10, &mtk_clk_gate_ops_setclr),
41
+
GATE_MTK(CLK_PERI_IRDA, "irda", "irda_sel", &peri_cg_regs, 11, &mtk_clk_gate_ops_setclr),
42
+
GATE_MTK(CLK_PERI_APDMA, "apdma", "axi_sel", &peri_cg_regs, 12, &mtk_clk_gate_ops_setclr),
43
+
GATE_MTK(CLK_PERI_MSDC30_0, "msdc30_0", "msdc30_0_sel", &peri_cg_regs, 13, &mtk_clk_gate_ops_setclr),
44
+
GATE_MTK(CLK_PERI_MSDC30_1, "msdc30_1", "msdc30_1_sel", &peri_cg_regs, 14, &mtk_clk_gate_ops_setclr),
45
+
GATE_MTK(CLK_PERI_MSDC30_2, "msdc30_2", "msdc30_2_sel", &peri_cg_regs, 15, &mtk_clk_gate_ops_setclr),
46
+
GATE_MTK(CLK_PERI_MSDC30_3, "msdc30_3", "msdc30_3_sel", &peri_cg_regs, 16, &mtk_clk_gate_ops_setclr),
47
+
GATE_MTK(CLK_PERI_UART0, "uart0", "uart_sel", &peri_cg_regs, 17, &mtk_clk_gate_ops_setclr),
48
+
GATE_MTK(CLK_PERI_UART1, "uart1", "uart_sel", &peri_cg_regs, 18, &mtk_clk_gate_ops_setclr),
49
+
GATE_MTK(CLK_PERI_UART2, "uart2", "uart_sel", &peri_cg_regs, 19, &mtk_clk_gate_ops_setclr),
50
+
GATE_MTK(CLK_PERI_UART3, "uart3", "uart_sel", &peri_cg_regs, 20, &mtk_clk_gate_ops_setclr),
51
+
GATE_MTK(CLK_PERI_UART4, "uart4", "uart_sel", &peri_cg_regs, 21, &mtk_clk_gate_ops_setclr),
52
+
GATE_MTK(CLK_PERI_BTIF, "btif", "axi_sel", &peri_cg_regs, 22, &mtk_clk_gate_ops_setclr),
53
+
GATE_MTK(CLK_PERI_I2C0, "i2c0", "axi_sel", &peri_cg_regs, 23, &mtk_clk_gate_ops_setclr),
54
+
GATE_MTK(CLK_PERI_I2C1, "i2c1", "axi_sel", &peri_cg_regs, 24, &mtk_clk_gate_ops_setclr),
55
+
GATE_MTK(CLK_PERI_I2C2, "i2c2", "axi_sel", &peri_cg_regs, 25, &mtk_clk_gate_ops_setclr),
56
+
GATE_MTK(CLK_PERI_I2C3, "i2c3", "axi_sel", &peri_cg_regs, 26, &mtk_clk_gate_ops_setclr),
57
+
GATE_MTK(CLK_PERI_AUXADC, "auxadc", "axi_sel", &peri_cg_regs, 27, &mtk_clk_gate_ops_setclr),
58
+
GATE_MTK(CLK_PERI_SPI0, "spi0", "spi_sel", &peri_cg_regs, 28, &mtk_clk_gate_ops_setclr),
59
+
GATE_MTK(CLK_PERI_IRTX, "irtx", "irtx_sel", &peri_cg_regs, 29, &mtk_clk_gate_ops_setclr)
60
+
};
61
+
62
+
static u16 pericfg_rst_bank_ofs[] = { PERI_GLOBALCON_RST0, PERI_GLOBALCON_RST1 };
63
+
64
+
static u16 pericfg_rst_idx_map[] = {
65
+
[MT6735_PERI_RST0_UART0] = 0 * RST_NR_PER_BANK + 0,
66
+
[MT6735_PERI_RST0_UART1] = 0 * RST_NR_PER_BANK + 1,
67
+
[MT6735_PERI_RST0_UART2] = 0 * RST_NR_PER_BANK + 2,
68
+
[MT6735_PERI_RST0_UART3] = 0 * RST_NR_PER_BANK + 3,
69
+
[MT6735_PERI_RST0_UART4] = 0 * RST_NR_PER_BANK + 4,
70
+
[MT6735_PERI_RST0_BTIF] = 0 * RST_NR_PER_BANK + 6,
71
+
[MT6735_PERI_RST0_DISP_PWM_PERI] = 0 * RST_NR_PER_BANK + 7,
72
+
[MT6735_PERI_RST0_PWM] = 0 * RST_NR_PER_BANK + 8,
73
+
[MT6735_PERI_RST0_AUXADC] = 0 * RST_NR_PER_BANK + 10,
74
+
[MT6735_PERI_RST0_DMA] = 0 * RST_NR_PER_BANK + 11,
75
+
[MT6735_PERI_RST0_IRDA] = 0 * RST_NR_PER_BANK + 12,
76
+
[MT6735_PERI_RST0_IRTX] = 0 * RST_NR_PER_BANK + 13,
77
+
[MT6735_PERI_RST0_THERM] = 0 * RST_NR_PER_BANK + 16,
78
+
[MT6735_PERI_RST0_MSDC2] = 0 * RST_NR_PER_BANK + 17,
79
+
[MT6735_PERI_RST0_MSDC3] = 0 * RST_NR_PER_BANK + 18,
80
+
[MT6735_PERI_RST0_MSDC0] = 0 * RST_NR_PER_BANK + 19,
81
+
[MT6735_PERI_RST0_MSDC1] = 0 * RST_NR_PER_BANK + 20,
82
+
[MT6735_PERI_RST0_I2C0] = 0 * RST_NR_PER_BANK + 22,
83
+
[MT6735_PERI_RST0_I2C1] = 0 * RST_NR_PER_BANK + 23,
84
+
[MT6735_PERI_RST0_I2C2] = 0 * RST_NR_PER_BANK + 24,
85
+
[MT6735_PERI_RST0_I2C3] = 0 * RST_NR_PER_BANK + 25,
86
+
[MT6735_PERI_RST0_USB] = 0 * RST_NR_PER_BANK + 28,
87
+
88
+
[MT6735_PERI_RST1_SPI0] = 1 * RST_NR_PER_BANK + 1,
89
+
};
90
+
91
+
static const struct mtk_clk_rst_desc pericfg_resets = {
92
+
.version = MTK_RST_SIMPLE,
93
+
.rst_bank_ofs = pericfg_rst_bank_ofs,
94
+
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_bank_ofs),
95
+
.rst_idx_map = pericfg_rst_idx_map,
96
+
.rst_idx_map_nr = ARRAY_SIZE(pericfg_rst_idx_map)
97
+
};
98
+
99
+
static const struct mtk_clk_desc pericfg_clks = {
100
+
.clks = pericfg_gates,
101
+
.num_clks = ARRAY_SIZE(pericfg_gates),
102
+
103
+
.rst_desc = &pericfg_resets
104
+
};
105
+
106
+
static const struct of_device_id of_match_mt6735_pericfg[] = {
107
+
{ .compatible = "mediatek,mt6735-pericfg", .data = &pericfg_clks },
108
+
{ /* sentinel */ }
109
+
};
110
+
MODULE_DEVICE_TABLE(of, of_match_mt6735_pericfg);
111
+
112
+
static struct platform_driver clk_mt6735_pericfg = {
113
+
.probe = mtk_clk_simple_probe,
114
+
.remove = mtk_clk_simple_remove,
115
+
.driver = {
116
+
.name = "clk-mt6735-pericfg",
117
+
.of_match_table = of_match_mt6735_pericfg,
118
+
},
119
+
};
120
+
module_platform_driver(clk_mt6735_pericfg);
121
+
122
+
MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
123
+
MODULE_DESCRIPTION("MediaTek MT6735 pericfg clock driver");
124
+
MODULE_LICENSE("GPL");
+394
drivers/clk/mediatek/clk-mt6735-topckgen.c
+394
drivers/clk/mediatek/clk-mt6735-topckgen.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/platform_device.h>
8
+
9
+
#include "clk-mtk.h"
10
+
#include "clk-mux.h"
11
+
12
+
#include <dt-bindings/clock/mediatek,mt6735-topckgen.h>
13
+
14
+
#define CLK_CFG_0 0x40
15
+
#define CLK_CFG_0_SET 0x44
16
+
#define CLK_CFG_0_CLR 0x48
17
+
#define CLK_CFG_1 0x50
18
+
#define CLK_CFG_1_SET 0x54
19
+
#define CLK_CFG_1_CLR 0x58
20
+
#define CLK_CFG_2 0x60
21
+
#define CLK_CFG_2_SET 0x64
22
+
#define CLK_CFG_2_CLR 0x68
23
+
#define CLK_CFG_3 0x70
24
+
#define CLK_CFG_3_SET 0x74
25
+
#define CLK_CFG_3_CLR 0x78
26
+
#define CLK_CFG_4 0x80
27
+
#define CLK_CFG_4_SET 0x84
28
+
#define CLK_CFG_4_CLR 0x88
29
+
#define CLK_CFG_5 0x90
30
+
#define CLK_CFG_5_SET 0x94
31
+
#define CLK_CFG_5_CLR 0x98
32
+
#define CLK_CFG_6 0xa0
33
+
#define CLK_CFG_6_SET 0xa4
34
+
#define CLK_CFG_6_CLR 0xa8
35
+
#define CLK_CFG_7 0xb0
36
+
#define CLK_CFG_7_SET 0xb4
37
+
#define CLK_CFG_7_CLR 0xb8
38
+
39
+
static DEFINE_SPINLOCK(mt6735_topckgen_lock);
40
+
41
+
/* Some clocks with unknown details are modeled as fixed clocks */
42
+
static const struct mtk_fixed_clk topckgen_fixed_clks[] = {
43
+
/*
44
+
* This clock is available as a parent option for multiple
45
+
* muxes and seems like an alternative name for clk26m at first,
46
+
* but it appears alongside it in several muxes which should
47
+
* mean it is a separate clock.
48
+
*/
49
+
FIXED_CLK(CLK_TOP_AD_SYS_26M_CK, "ad_sys_26m_ck", "clk26m", 26 * MHZ),
50
+
/*
51
+
* This clock is the parent of DMPLL divisors. It might be MEMPLL
52
+
* or its parent, as DMPLL appears to be an alternative name for
53
+
* MEMPLL.
54
+
*/
55
+
FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", NULL, 0),
56
+
/*
57
+
* DMPLL clock (dmpll_ck), controlled by DDRPHY.
58
+
*/
59
+
FIXED_CLK(CLK_TOP_DMPLL, "dmpll", "clkph_mck_o", 0),
60
+
/*
61
+
* MIPI DPI clock. Parent option for dpi0_sel. Unknown parent.
62
+
*/
63
+
FIXED_CLK(CLK_TOP_DPI_CK, "dpi_ck", NULL, 0),
64
+
/*
65
+
* This clock is a child of WHPLL which is controlled by
66
+
* the modem.
67
+
*/
68
+
FIXED_CLK(CLK_TOP_WHPLL_AUDIO_CK, "whpll_audio_ck", NULL, 0)
69
+
};
70
+
71
+
static const struct mtk_fixed_factor topckgen_factors[] = {
72
+
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
73
+
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
74
+
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
75
+
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 2),
76
+
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 4),
77
+
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 8),
78
+
FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 16),
79
+
FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 2),
80
+
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 4),
81
+
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 2),
82
+
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 4),
83
+
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 2),
84
+
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 4),
85
+
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
86
+
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
87
+
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
88
+
FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
89
+
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 2),
90
+
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 4),
91
+
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 8),
92
+
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2),
93
+
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
94
+
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
95
+
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 2),
96
+
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 4),
97
+
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
98
+
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
99
+
FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
100
+
FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
101
+
FACTOR(CLK_TOP_VENCPLL_D3, "vencpll_d3", "vencpll", 1, 3),
102
+
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
103
+
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
104
+
FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
105
+
FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
106
+
FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
107
+
FACTOR(CLK_TOP_AD_SYS_26M_D2, "ad_sys_26m_d2", "clk26m", 1, 2)
108
+
};
109
+
110
+
static const char * const axi_sel_parents[] = {
111
+
"clk26m",
112
+
"syspll1_d2",
113
+
"syspll_d5",
114
+
"syspll1_d4",
115
+
"univpll_d5",
116
+
"univpll2_d2",
117
+
"dmpll",
118
+
"dmpll_d2"
119
+
};
120
+
121
+
static const char * const mem_sel_parents[] = {
122
+
"clk26m",
123
+
"dmpll"
124
+
};
125
+
126
+
static const char * const ddrphycfg_parents[] = {
127
+
"clk26m",
128
+
"syspll1_d8"
129
+
};
130
+
131
+
static const char * const mm_sel_parents[] = {
132
+
"clk26m",
133
+
"vencpll",
134
+
"syspll1_d2",
135
+
"syspll_d5",
136
+
"syspll1_d4",
137
+
"univpll_d5",
138
+
"univpll2_d2",
139
+
"dmpll"
140
+
};
141
+
142
+
static const char * const pwm_sel_parents[] = {
143
+
"clk26m",
144
+
"univpll2_d4",
145
+
"univpll3_d2",
146
+
"univpll1_d4"
147
+
};
148
+
149
+
static const char * const vdec_sel_parents[] = {
150
+
"clk26m",
151
+
"syspll1_d2",
152
+
"syspll_d5",
153
+
"syspll1_d4",
154
+
"univpll_d5",
155
+
"syspll_d2",
156
+
"syspll2_d2",
157
+
"msdcpll_d2"
158
+
};
159
+
160
+
static const char * const mfg_sel_parents[] = {
161
+
"clk26m",
162
+
"mmpll",
163
+
"clk26m",
164
+
"clk26m",
165
+
"clk26m",
166
+
"clk26m",
167
+
"clk26m",
168
+
"clk26m",
169
+
"clk26m",
170
+
"syspll_d3",
171
+
"syspll1_d2",
172
+
"syspll_d5",
173
+
"univpll_d3",
174
+
"univpll1_d2"
175
+
};
176
+
177
+
static const char * const camtg_sel_parents[] = {
178
+
"clk26m",
179
+
"univpll_d26",
180
+
"univpll2_d2",
181
+
"syspll3_d2",
182
+
"syspll3_d4",
183
+
"msdcpll_d4"
184
+
};
185
+
186
+
static const char * const uart_sel_parents[] = {
187
+
"clk26m",
188
+
"univpll2_d8"
189
+
};
190
+
191
+
static const char * const spi_sel_parents[] = {
192
+
"clk26m",
193
+
"syspll3_d2",
194
+
"msdcpll_d8",
195
+
"syspll2_d4",
196
+
"syspll4_d2",
197
+
"univpll2_d4",
198
+
"univpll1_d8"
199
+
};
200
+
201
+
static const char * const usb20_sel_parents[] = {
202
+
"clk26m",
203
+
"univpll1_d8",
204
+
"univpll3_d4"
205
+
};
206
+
207
+
static const char * const msdc50_0_sel_parents[] = {
208
+
"clk26m",
209
+
"syspll1_d2",
210
+
"syspll2_d2",
211
+
"syspll4_d2",
212
+
"univpll_d5",
213
+
"univpll1_d4"
214
+
};
215
+
216
+
static const char * const msdc30_0_sel_parents[] = {
217
+
"clk26m",
218
+
"msdcpll",
219
+
"msdcpll_d2",
220
+
"msdcpll_d4",
221
+
"syspll2_d2",
222
+
"syspll1_d4",
223
+
"univpll1_d4",
224
+
"univpll_d3",
225
+
"univpll_d26",
226
+
"syspll2_d4",
227
+
"univpll_d2"
228
+
};
229
+
230
+
static const char * const msdc30_1_2_sel_parents[] = {
231
+
"clk26m",
232
+
"univpll2_d2",
233
+
"msdcpll_d4",
234
+
"syspll2_d2",
235
+
"syspll1_d4",
236
+
"univpll1_d4",
237
+
"univpll_d26",
238
+
"syspll2_d4"
239
+
};
240
+
241
+
static const char * const msdc30_3_sel_parents[] = {
242
+
"clk26m",
243
+
"univpll2_d2",
244
+
"msdcpll_d4",
245
+
"syspll2_d2",
246
+
"syspll1_d4",
247
+
"univpll1_d4",
248
+
"univpll_d26",
249
+
"msdcpll_d16",
250
+
"syspll2_d4"
251
+
};
252
+
253
+
static const char * const audio_sel_parents[] = {
254
+
"clk26m",
255
+
"syspll3_d4",
256
+
"syspll4_d4",
257
+
"syspll1_d16"
258
+
};
259
+
260
+
static const char * const aud_intbus_sel_parents[] = {
261
+
"clk26m",
262
+
"syspll1_d4",
263
+
"syspll4_d2",
264
+
"dmpll_d4"
265
+
};
266
+
267
+
static const char * const pmicspi_sel_parents[] = {
268
+
"clk26m",
269
+
"syspll1_d8",
270
+
"syspll3_d4",
271
+
"syspll1_d16",
272
+
"univpll3_d4",
273
+
"univpll_d26",
274
+
"dmpll_d4",
275
+
"dmpll_d8"
276
+
};
277
+
278
+
static const char * const scp_sel_parents[] = {
279
+
"clk26m",
280
+
"syspll1_d8",
281
+
"dmpll_d2",
282
+
"dmpll_d4"
283
+
};
284
+
285
+
static const char * const atb_sel_parents[] = {
286
+
"clk26m",
287
+
"syspll1_d2",
288
+
"syspll_d5",
289
+
"dmpll"
290
+
};
291
+
292
+
static const char * const dpi0_sel_parents[] = {
293
+
"clk26m",
294
+
"tvdpll",
295
+
"tvdpll_d2",
296
+
"tvdpll_d4",
297
+
"dpi_ck"
298
+
};
299
+
300
+
static const char * const scam_sel_parents[] = {
301
+
"clk26m",
302
+
"syspll3_d2",
303
+
"univpll2_d4",
304
+
"vencpll_d3"
305
+
};
306
+
307
+
static const char * const mfg13m_sel_parents[] = {
308
+
"clk26m",
309
+
"ad_sys_26m_d2"
310
+
};
311
+
312
+
static const char * const aud_1_2_sel_parents[] = {
313
+
"clk26m",
314
+
"apll1"
315
+
};
316
+
317
+
static const char * const irda_sel_parents[] = {
318
+
"clk26m",
319
+
"univpll2_d4"
320
+
};
321
+
322
+
static const char * const irtx_sel_parents[] = {
323
+
"clk26m",
324
+
"ad_sys_26m_ck"
325
+
};
326
+
327
+
static const char * const disppwm_sel_parents[] = {
328
+
"clk26m",
329
+
"univpll2_d4",
330
+
"syspll4_d2_d8",
331
+
"ad_sys_26m_ck"
332
+
};
333
+
334
+
static const struct mtk_mux topckgen_muxes[] = {
335
+
MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, "axi_sel", axi_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 0, 3, 0, 0),
336
+
MUX_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 1, 0, 0),
337
+
MUX_CLR_SET_UPD(CLK_TOP_DDRPHY_SEL, "ddrphycfg_sel", ddrphycfg_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 1, 0, 0),
338
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31, 0, 0),
339
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7, 0, 0),
340
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 3, 15, 0, 0),
341
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 16, 4, 23, 0, 0),
342
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 24, 3, 31, 0, 0),
343
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 0, 1, 7, 0, 0),
344
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 8, 3, 15, 0, 0),
345
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB20_SEL, "usb20_sel", usb20_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 2, 23, 0, 0),
346
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 3, 31, 0, 0),
347
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 0, 4, 7, 0, 0),
348
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_2_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 8, 3, 15, 0, 0),
349
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_1_2_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 16, 3, 23, 0, 0),
350
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 24, 4, 31, 0, 0),
351
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 0, 2, 7, 0, 0),
352
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 8, 2, 15, 0, 0),
353
+
MUX_CLR_SET_UPD(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 16, 3, 0, 0),
354
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 24, 2, 31, 0, 0),
355
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7, 0, 0),
356
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 3, 15, 0, 0),
357
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel", scam_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 16, 2, 23, 0, 0),
358
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG13M_SEL, "mfg13m_sel", mfg13m_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 1, 31, 0, 0),
359
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD1_SEL, "aud_1_sel", aud_1_2_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 0, 1, 7, 0, 0),
360
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD2_SEL, "aud_2_sel", aud_1_2_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 1, 15, 0, 0),
361
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_IRDA_SEL, "irda_sel", irda_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 1, 23, 0, 0),
362
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_IRTX_SEL, "irtx_sel", irtx_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 24, 1, 31, 0, 0),
363
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISPPWM_SEL, "disppwm_sel", disppwm_sel_parents, CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 0, 2, 7, 0, 0),
364
+
};
365
+
366
+
static const struct mtk_clk_desc topckgen_desc = {
367
+
.fixed_clks = topckgen_fixed_clks,
368
+
.num_fixed_clks = ARRAY_SIZE(topckgen_fixed_clks),
369
+
.factor_clks = topckgen_factors,
370
+
.num_factor_clks = ARRAY_SIZE(topckgen_factors),
371
+
.mux_clks = topckgen_muxes,
372
+
.num_mux_clks = ARRAY_SIZE(topckgen_muxes),
373
+
.clk_lock = &mt6735_topckgen_lock,
374
+
};
375
+
376
+
static const struct of_device_id of_match_mt6735_topckgen[] = {
377
+
{ .compatible = "mediatek,mt6735-topckgen", .data = &topckgen_desc},
378
+
{ /* sentinel */ }
379
+
};
380
+
MODULE_DEVICE_TABLE(of, of_match_mt6735_topckgen);
381
+
382
+
static struct platform_driver clk_mt6735_topckgen = {
383
+
.probe = mtk_clk_simple_probe,
384
+
.remove = mtk_clk_simple_remove,
385
+
.driver = {
386
+
.name = "clk-mt6735-topckgen",
387
+
.of_match_table = of_match_mt6735_topckgen,
388
+
},
389
+
};
390
+
module_platform_driver(clk_mt6735_topckgen);
391
+
392
+
MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
393
+
MODULE_DESCRIPTION("MediaTek MT6735 topckgen clock driver");
394
+
MODULE_LICENSE("GPL");