Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pci-v6.19-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull PCI updates from Bjorn Helgaas:
"Enumeration:
- Enable host bridge emulation for PCI_DOMAINS_GENERIC platforms (Dan
Williams)
- Switch vmd from custom domain number allocator to the common
allocator to prevent a potential race with new non-VMD buses (Dan
Williams)
- Enable Precision Time Measurement (PTM) only if device advertises
support for a relevant role, to prevent invalid PTM Requests that
cause ACS violations that are reported as AER Uncorrectable
Non-Fatal errors (Mika Westerberg)
Resource management:
- Prevent resource tree corruption when BAR resize fails (Ilpo
Järvinen)
- Restore BARs to the original size if a BAR resize fails (Ilpo
Järvinen)
- Remove BAR release from BAR resize attempts by the xe, i915, and
amdgpu drivers so the PCI core can restore BARs if the resize fails
(Ilpo Järvinen)
- Move Resizable BAR code to rebar.c (Ilpo Järvinen)
- Add pci_rebar_size_supported() and use it in i915 and xe (Ilpo
Järvinen)
- Add pci_rebar_get_max_size() and use it in xe and amdgpu (Ilpo
Järvinen)
Power management and error handling:
- For drivers using PCI legacy suspend, save config state at suspend
so that state (not any earlier state from enumeration, probe, or
error recovery) will be restored when resuming (Lukas Wunner)
- For devices with no driver or a driver that lacks power management,
save config state at hibernate so that state (not any earlier state
from enumeration, probe, or error recovery) will be restored when
resuming (Lukas Wunner)
- Save device config space on device addition, before driver binding,
so error recovery works more reliably (Lukas Wunner)
- Drop pci_save_state() from several drivers that no longer need it
since the PCI core always does it and pci_restore_state() no longer
invalidates the saved state (Lukas Wunner)
- Document use of pci_save_state() by drivers to capture the state
they want restored during error recovery (Lukas Wunner)
Power control:
- Add a struct pci_ops.assert_perst() function pointer to
assert/deassert PCIe PERST# and implement it for the qcom driver
(Krishna Chaitanya Chundru)
- Add DT binding and pwrctrl driver for the Toshiba TC9563 PCIe
switch, which must be held in reset after poweron so the pwrctrl
driver can configure the switch via I2C before bringing up the
links (Krishna Chaitanya Chundru)
Endpoint framework:
- Convert the endpoint doorbell test to use a threaded IRQ to fix a
'sleeping while atomic' issue (Bhanu Seshu Kumar Valluri)
- Add endpoint VNTB MSI doorbell support to reduce latency between
host and endpoint (Frank Li)
New native PCIe controller drivers:
- Add CIX Sky1 host controller DT binding and driver (Hans Zhang)
- Add NXP S32G host controller DT binding and driver (Vincent
Guittot)
- Add Renesas RZ/G3S host controller DT binding and driver (Claudiu
Beznea)
- Add SpacemiT K1 host controller DT binding and driver (Alex Elder)
Amlogic Meson PCIe controller driver:
- Update DT binding to name DBI region 'dbi', not 'elbi', and update
driver to support both (Manivannan Sadhasivam)
Apple PCIe controller driver:
- Move struct pci_host_bridge allocation from pci_host_common_init()
to callers, which significantly simplifies pcie-apple (Marc
Zyngier)
Broadcom STB PCIe controller driver:
- Disable advertising ASPM L0s support correctly (Jim Quinlan)
- Add a panic/die handler to print diagnostic info in case PCIe
caused an unrecoverable abort (Jim Quinlan)
Cadence PCIe controller driver:
- Add module support for Cadence platform host and endpoint
controller driver (Manikandan K Pillai)
- Split headers into 'legacy' (LGA) and 'high perf' (HPA) to prepare
for new CIX Sky1 driver (Manikandan K Pillai)
MediaTek PCIe controller driver:
- Convert DT binding to YAML schema (Christian Marangi)
- Add Airoha AN7583 DT compatible and driver support (Christian
Marangi)
Qualcomm PCIe controller driver:
- Add Qualcomm Kaanapali to SM8550 DT binding (Qiang Yu)
- Add required 'power-domains' and 'resets' to qcom sa8775p, sc7280,
sc8280xp, sm8150, sm8250, sm8350, sm8450, sm8550, x1e80100 DT
schemas (Krzysztof Kozlowski)
- Look up OPP using both frequency and data rate (not just frequency)
so RPMh votes can account for both (Krishna Chaitanya Chundru)
Rockchip DesignWare PCIe controller driver:
- Add Rockchip RK3528 compatible strings in DT binding (Yao Zi)
STMicroelectronics STM32MP25 PCIe controller driver:
- Fix a race between link training and endpoint register
initialization (Christian Bruel)
- Align endpoint allocations to match the ATU requirements (Christian
Bruel)
Synopsys DesignWare PCIe controller driver:
- Clear L1 PM Substate Capability 'Supported' bits unless glue driver
says it's supported, which prevents users from enabling non-working
L1SS. Currently only qcom and tegra194 support L1SS (Bjorn Helgaas)
- Remove now-superfluous L1SS disable code from tegra194 (Bjorn
Helgaas)
- Configure L1SS support in dw-rockchip when DT says
'supports-clkreq' (Shawn Lin)
TI Keystone PCIe controller driver:
- Fail the probe instead of silently succeeding if ks_pcie_of_data
didn't specify Root Complex or Endpoint mode (Siddharth Vadapalli)
- Make keystone buildable as a loadable module, except on ARM32 where
hook_fault_code() is __init (Siddharth Vadapalli)"
* tag 'pci-v6.19-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (100 commits)
MAINTAINERS: Add Manivannan Sadhasivam as PCI/pwrctrl maintainer
MAINTAINERS: Add CIX Sky1 PCIe controller driver maintainer
PCI: sky1: Add PCIe host support for CIX Sky1
dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings
PCI: cadence: Add support for High Perf Architecture (HPA) controller
MAINTAINERS: Add NXP S32G PCIe controller driver maintainer
PCI: s32g: Add NXP S32G PCIe controller driver (RC)
PCI: dwc: Add register and bitfield definitions
dt-bindings: PCI: s32g: Add NXP S32G PCIe controller
PCI: Add Renesas RZ/G3S host controller driver
PCI: host-generic: Move bridge allocation outside of pci_host_common_init()
dt-bindings: PCI: Add Renesas RZ/G3S PCIe controller binding
PCI: Validate pci_rebar_size_supported() input
Documentation: PCI: Amend error recovery doc with pci_save_state() rules
treewide: Drop pci_save_state() after pci_restore_state()
PCI/ERR: Ensure error recoverability at all times
PCI/PM: Stop needlessly clearing state_saved on enumeration and thaw
PCI/PM: Reinstate clearing state_saved in legacy and !PM codepaths
PCI: dw-rockchip: Configure L1SS support
PCI: tegra194: Remove unnecessary L1SS disable code
...
+7905
-1672
+15
Documentation/PCI/pci-error-recovery.rst
+15
Documentation/PCI/pci-error-recovery.rst
···
326
326
will typically report a "permanent failure" in such a case. The
327
327
device will be considered "dead" in this case.
328
328
329
+
Drivers typically need to call pci_restore_state() after reset to
330
+
re-initialize the device's config space registers and thereby
331
+
bring it from D0\ :sub:`uninitialized` into D0\ :sub:`active` state
332
+
(PCIe r7.0 sec 5.3.1.1). The PCI core invokes pci_save_state()
333
+
on enumeration after initializing config space to ensure that a
334
+
saved state is available for subsequent error recovery.
335
+
Drivers which modify config space on probe may need to invoke
336
+
pci_save_state() afterwards to record those changes for later
337
+
error recovery. When going into system suspend, pci_save_state()
338
+
is called for every PCI device and that state will be restored
339
+
not only on resume, but also on any subsequent error recovery.
340
+
In the unlikely event that the saved state recorded on suspend
341
+
is unsuitable for error recovery, drivers should call
342
+
pci_save_state() on resume.
343
+
329
344
Drivers for multi-function cards will need to coordinate among
330
345
themselves as to which driver instance will perform any "one-shot"
331
346
or global device initialization. For example, the Symbios sym53cxx2
+12
-11
Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml
+12
-11
Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml
···
20
20
select:
21
21
properties:
22
22
compatible:
23
-
enum:
24
-
- amlogic,axg-pcie
25
-
- amlogic,g12a-pcie
23
+
contains:
24
+
enum:
25
+
- amlogic,axg-pcie
26
+
- amlogic,g12a-pcie
26
27
required:
27
28
- compatible
28
29
···
37
36
38
37
reg:
39
38
items:
40
-
- description: External local bus interface registers
39
+
- description: Data Bus Interface registers
41
40
- description: Meson designed configuration registers
42
41
- description: PCIe configuration space
43
42
44
43
reg-names:
45
44
items:
46
-
- const: elbi
45
+
- const: dbi
47
46
- const: cfg
48
47
- const: config
49
48
···
52
51
53
52
clocks:
54
53
items:
54
+
- description: PCIe PHY clock
55
55
- description: PCIe GEN 100M PLL clock
56
56
- description: PCIe RC clock gate
57
-
- description: PCIe PHY clock
58
57
59
58
clock-names:
60
59
items:
60
+
- const: general
61
61
- const: pclk
62
62
- const: port
63
-
- const: general
64
63
65
64
phys:
66
65
maxItems: 1
···
89
88
- reg
90
89
- reg-names
91
90
- interrupts
92
-
- clock
91
+
- clocks
93
92
- clock-names
94
93
- "#address-cells"
95
94
- "#size-cells"
···
114
113
pcie: pcie@f9800000 {
115
114
compatible = "amlogic,axg-pcie", "snps,dw-pcie";
116
115
reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>;
117
-
reg-names = "elbi", "cfg", "config";
116
+
reg-names = "dbi", "cfg", "config";
118
117
interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
119
-
clocks = <&pclk>, <&clk_port>, <&clk_phy>;
120
-
clock-names = "pclk", "port", "general";
118
+
clocks = <&clk_phy>, <&pclk>, <&clk_port>;
119
+
clock-names = "general", "pclk", "port";
121
120
resets = <&reset_pcie_port>, <&reset_pcie_apb>;
122
121
reset-names = "port", "apb";
123
122
phys = <&pcie_phy>;
+83
Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml
+83
Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/cix,sky1-pcie-host.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: CIX Sky1 PCIe Root Complex
8
+
9
+
maintainers:
10
+
- Hans Zhang <hans.zhang@cixtech.com>
11
+
12
+
description:
13
+
PCIe root complex controller based on the Cadence PCIe core.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pci/pci-host-bridge.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: cix,sky1-pcie-host
21
+
22
+
reg:
23
+
items:
24
+
- description: PCIe controller registers.
25
+
- description: ECAM registers.
26
+
- description: Remote CIX System Unit strap registers.
27
+
- description: Remote CIX System Unit status registers.
28
+
- description: Region for sending messages registers.
29
+
30
+
reg-names:
31
+
items:
32
+
- const: reg
33
+
- const: cfg
34
+
- const: rcsu_strap
35
+
- const: rcsu_status
36
+
- const: msg
37
+
38
+
ranges:
39
+
maxItems: 3
40
+
41
+
required:
42
+
- compatible
43
+
- ranges
44
+
- bus-range
45
+
- device_type
46
+
- interrupt-map
47
+
- interrupt-map-mask
48
+
- msi-map
49
+
50
+
unevaluatedProperties: false
51
+
52
+
examples:
53
+
- |
54
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
55
+
56
+
soc {
57
+
#address-cells = <2>;
58
+
#size-cells = <2>;
59
+
60
+
pcie@a010000 {
61
+
compatible = "cix,sky1-pcie-host";
62
+
reg = <0x00 0x0a010000 0x00 0x10000>,
63
+
<0x00 0x2c000000 0x00 0x4000000>,
64
+
<0x00 0x0a000300 0x00 0x100>,
65
+
<0x00 0x0a000400 0x00 0x100>,
66
+
<0x00 0x60000000 0x00 0x00100000>;
67
+
reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
68
+
ranges = <0x01000000 0x00 0x60100000 0x00 0x60100000 0x00 0x00100000>,
69
+
<0x02000000 0x00 0x60200000 0x00 0x60200000 0x00 0x1fe00000>,
70
+
<0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>;
71
+
#address-cells = <3>;
72
+
#size-cells = <2>;
73
+
bus-range = <0xc0 0xff>;
74
+
device_type = "pci";
75
+
#interrupt-cells = <1>;
76
+
interrupt-map-mask = <0 0 0 0x7>;
77
+
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
78
+
<0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
79
+
<0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
80
+
<0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>;
81
+
msi-map = <0xc000 &gic_its 0xc000 0x4000>;
82
+
};
83
+
};
+164
Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml
+164
Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/mediatek-pcie-mt7623.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: PCIe controller on MediaTek SoCs
8
+
9
+
maintainers:
10
+
- Christian Marangi <ansuelsmth@gmail.com>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- mediatek,mt2701-pcie
16
+
- mediatek,mt7623-pcie
17
+
18
+
reg:
19
+
minItems: 4
20
+
maxItems: 4
21
+
22
+
reg-names:
23
+
items:
24
+
- const: subsys
25
+
- const: port0
26
+
- const: port1
27
+
- const: port2
28
+
29
+
clocks:
30
+
minItems: 4
31
+
maxItems: 4
32
+
33
+
clock-names:
34
+
items:
35
+
- const: free_ck
36
+
- const: sys_ck0
37
+
- const: sys_ck1
38
+
- const: sys_ck2
39
+
40
+
resets:
41
+
minItems: 3
42
+
maxItems: 3
43
+
44
+
reset-names:
45
+
items:
46
+
- const: pcie-rst0
47
+
- const: pcie-rst1
48
+
- const: pcie-rst2
49
+
50
+
phys:
51
+
minItems: 3
52
+
maxItems: 3
53
+
54
+
phy-names:
55
+
items:
56
+
- const: pcie-phy0
57
+
- const: pcie-phy1
58
+
- const: pcie-phy2
59
+
60
+
power-domains:
61
+
maxItems: 1
62
+
63
+
required:
64
+
- compatible
65
+
- reg
66
+
- reg-names
67
+
- ranges
68
+
- clocks
69
+
- clock-names
70
+
- '#interrupt-cells'
71
+
- resets
72
+
- reset-names
73
+
- phys
74
+
- phy-names
75
+
- power-domains
76
+
- pcie@0,0
77
+
- pcie@1,0
78
+
- pcie@2,0
79
+
80
+
allOf:
81
+
- $ref: /schemas/pci/pci-host-bridge.yaml#
82
+
83
+
unevaluatedProperties: false
84
+
85
+
examples:
86
+
# MT7623
87
+
- |
88
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
89
+
#include <dt-bindings/interrupt-controller/irq.h>
90
+
#include <dt-bindings/clock/mt2701-clk.h>
91
+
#include <dt-bindings/reset/mt2701-resets.h>
92
+
#include <dt-bindings/phy/phy.h>
93
+
#include <dt-bindings/power/mt2701-power.h>
94
+
95
+
soc {
96
+
#address-cells = <2>;
97
+
#size-cells = <2>;
98
+
99
+
pcie@1a140000 {
100
+
compatible = "mediatek,mt7623-pcie";
101
+
device_type = "pci";
102
+
reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
103
+
<0 0x1a142000 0 0x1000>, /* Port0 registers */
104
+
<0 0x1a143000 0 0x1000>, /* Port1 registers */
105
+
<0 0x1a144000 0 0x1000>; /* Port2 registers */
106
+
reg-names = "subsys", "port0", "port1", "port2";
107
+
#address-cells = <3>;
108
+
#size-cells = <2>;
109
+
#interrupt-cells = <1>;
110
+
interrupt-map-mask = <0xf800 0 0 0>;
111
+
interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
112
+
<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
113
+
<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
114
+
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
115
+
<&hifsys CLK_HIFSYS_PCIE0>,
116
+
<&hifsys CLK_HIFSYS_PCIE1>,
117
+
<&hifsys CLK_HIFSYS_PCIE2>;
118
+
clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
119
+
resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
120
+
<&hifsys MT2701_HIFSYS_PCIE1_RST>,
121
+
<&hifsys MT2701_HIFSYS_PCIE2_RST>;
122
+
reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
123
+
phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
124
+
<&pcie2_phy PHY_TYPE_PCIE>;
125
+
phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
126
+
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
127
+
bus-range = <0x00 0xff>;
128
+
ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000>, /* I/O space */
129
+
<0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
130
+
131
+
pcie@0,0 {
132
+
device_type = "pci";
133
+
reg = <0x0000 0 0 0 0>;
134
+
#address-cells = <3>;
135
+
#size-cells = <2>;
136
+
#interrupt-cells = <1>;
137
+
interrupt-map-mask = <0 0 0 0>;
138
+
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
139
+
ranges;
140
+
};
141
+
142
+
pcie@1,0 {
143
+
device_type = "pci";
144
+
reg = <0x0800 0 0 0 0>;
145
+
#address-cells = <3>;
146
+
#size-cells = <2>;
147
+
#interrupt-cells = <1>;
148
+
interrupt-map-mask = <0 0 0 0>;
149
+
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
150
+
ranges;
151
+
};
152
+
153
+
pcie@2,0 {
154
+
device_type = "pci";
155
+
reg = <0x1000 0 0 0 0>;
156
+
#address-cells = <3>;
157
+
#size-cells = <2>;
158
+
#interrupt-cells = <1>;
159
+
interrupt-map-mask = <0 0 0 0>;
160
+
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
161
+
ranges;
162
+
};
163
+
};
164
+
};
-289
Documentation/devicetree/bindings/pci/mediatek-pcie.txt
-289
Documentation/devicetree/bindings/pci/mediatek-pcie.txt
···
1
-
MediaTek Gen2 PCIe controller
2
-
3
-
Required properties:
4
-
- compatible: Should contain one of the following strings:
5
-
"mediatek,mt2701-pcie"
6
-
"mediatek,mt2712-pcie"
7
-
"mediatek,mt7622-pcie"
8
-
"mediatek,mt7623-pcie"
9
-
"mediatek,mt7629-pcie"
10
-
"airoha,en7523-pcie"
11
-
- device_type: Must be "pci"
12
-
- reg: Base addresses and lengths of the root ports.
13
-
- reg-names: Names of the above areas to use during resource lookup.
14
-
- #address-cells: Address representation for root ports (must be 3)
15
-
- #size-cells: Size representation for root ports (must be 2)
16
-
- clocks: Must contain an entry for each entry in clock-names.
17
-
See ../clocks/clock-bindings.txt for details.
18
-
- clock-names:
19
-
Mandatory entries:
20
-
- sys_ckN :transaction layer and data link layer clock
21
-
Required entries for MT2701/MT7623:
22
-
- free_ck :for reference clock of PCIe subsys
23
-
Required entries for MT2712/MT7622:
24
-
- ahb_ckN :AHB slave interface operating clock for CSR access and RC
25
-
initiated MMIO access
26
-
Required entries for MT7622:
27
-
- axi_ckN :application layer MMIO channel operating clock
28
-
- aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
29
-
pcie_mac_ck/pcie_pipe_ck is turned off
30
-
- obff_ckN :OBFF functional block operating clock
31
-
- pipe_ckN :LTSSM and PHY/MAC layer operating clock
32
-
where N starting from 0 to one less than the number of root ports.
33
-
- phys: List of PHY specifiers (used by generic PHY framework).
34
-
- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
35
-
number of PHYs as specified in *phys* property.
36
-
- power-domains: A phandle and power domain specifier pair to the power domain
37
-
which is responsible for collapsing and restoring power to the peripheral.
38
-
- bus-range: Range of bus numbers associated with this controller.
39
-
- ranges: Ranges for the PCI memory and I/O regions.
40
-
41
-
Required properties for MT7623/MT2701:
42
-
- #interrupt-cells: Size representation for interrupts (must be 1)
43
-
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
44
-
Please refer to the standard PCI bus binding document for a more detailed
45
-
explanation.
46
-
- resets: Must contain an entry for each entry in reset-names.
47
-
See ../reset/reset.txt for details.
48
-
- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
49
-
number of root ports.
50
-
51
-
Required properties for MT2712/MT7622/MT7629:
52
-
-interrupts: A list of interrupt outputs of the controller, must have one
53
-
entry for each PCIe port
54
-
- interrupt-names: Must include the following entries:
55
-
- "pcie_irq": The interrupt that is asserted when an MSI/INTX is received
56
-
- linux,pci-domain: PCI domain ID. Should be unique for each host controller
57
-
58
-
In addition, the device tree node must have sub-nodes describing each
59
-
PCIe port interface, having the following mandatory properties:
60
-
61
-
Required properties:
62
-
- device_type: Must be "pci"
63
-
- reg: Only the first four bytes are used to refer to the correct bus number
64
-
and device number.
65
-
- #address-cells: Must be 3
66
-
- #size-cells: Must be 2
67
-
- #interrupt-cells: Must be 1
68
-
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
69
-
Please refer to the standard PCI bus binding document for a more detailed
70
-
explanation.
71
-
- ranges: Sub-ranges distributed from the PCIe controller node. An empty
72
-
property is sufficient.
73
-
74
-
Examples for MT7623:
75
-
76
-
hifsys: syscon@1a000000 {
77
-
compatible = "mediatek,mt7623-hifsys",
78
-
"mediatek,mt2701-hifsys",
79
-
"syscon";
80
-
reg = <0 0x1a000000 0 0x1000>;
81
-
#clock-cells = <1>;
82
-
#reset-cells = <1>;
83
-
};
84
-
85
-
pcie: pcie@1a140000 {
86
-
compatible = "mediatek,mt7623-pcie";
87
-
device_type = "pci";
88
-
reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
89
-
<0 0x1a142000 0 0x1000>, /* Port0 registers */
90
-
<0 0x1a143000 0 0x1000>, /* Port1 registers */
91
-
<0 0x1a144000 0 0x1000>; /* Port2 registers */
92
-
reg-names = "subsys", "port0", "port1", "port2";
93
-
#address-cells = <3>;
94
-
#size-cells = <2>;
95
-
#interrupt-cells = <1>;
96
-
interrupt-map-mask = <0xf800 0 0 0>;
97
-
interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
98
-
<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
99
-
<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
100
-
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
101
-
<&hifsys CLK_HIFSYS_PCIE0>,
102
-
<&hifsys CLK_HIFSYS_PCIE1>,
103
-
<&hifsys CLK_HIFSYS_PCIE2>;
104
-
clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
105
-
resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
106
-
<&hifsys MT2701_HIFSYS_PCIE1_RST>,
107
-
<&hifsys MT2701_HIFSYS_PCIE2_RST>;
108
-
reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
109
-
phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
110
-
<&pcie2_phy PHY_TYPE_PCIE>;
111
-
phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
112
-
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
113
-
bus-range = <0x00 0xff>;
114
-
ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
115
-
0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
116
-
117
-
pcie@0,0 {
118
-
reg = <0x0000 0 0 0 0>;
119
-
#address-cells = <3>;
120
-
#size-cells = <2>;
121
-
#interrupt-cells = <1>;
122
-
interrupt-map-mask = <0 0 0 0>;
123
-
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
124
-
ranges;
125
-
};
126
-
127
-
pcie@1,0 {
128
-
reg = <0x0800 0 0 0 0>;
129
-
#address-cells = <3>;
130
-
#size-cells = <2>;
131
-
#interrupt-cells = <1>;
132
-
interrupt-map-mask = <0 0 0 0>;
133
-
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
134
-
ranges;
135
-
};
136
-
137
-
pcie@2,0 {
138
-
reg = <0x1000 0 0 0 0>;
139
-
#address-cells = <3>;
140
-
#size-cells = <2>;
141
-
#interrupt-cells = <1>;
142
-
interrupt-map-mask = <0 0 0 0>;
143
-
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
144
-
ranges;
145
-
};
146
-
};
147
-
148
-
Examples for MT2712:
149
-
150
-
pcie1: pcie@112ff000 {
151
-
compatible = "mediatek,mt2712-pcie";
152
-
device_type = "pci";
153
-
reg = <0 0x112ff000 0 0x1000>;
154
-
reg-names = "port1";
155
-
linux,pci-domain = <1>;
156
-
#address-cells = <3>;
157
-
#size-cells = <2>;
158
-
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
159
-
interrupt-names = "pcie_irq";
160
-
clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
161
-
<&pericfg CLK_PERI_PCIE1>;
162
-
clock-names = "sys_ck1", "ahb_ck1";
163
-
phys = <&u3port1 PHY_TYPE_PCIE>;
164
-
phy-names = "pcie-phy1";
165
-
bus-range = <0x00 0xff>;
166
-
ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
167
-
status = "disabled";
168
-
169
-
#interrupt-cells = <1>;
170
-
interrupt-map-mask = <0 0 0 7>;
171
-
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
172
-
<0 0 0 2 &pcie_intc1 1>,
173
-
<0 0 0 3 &pcie_intc1 2>,
174
-
<0 0 0 4 &pcie_intc1 3>;
175
-
pcie_intc1: interrupt-controller {
176
-
interrupt-controller;
177
-
#address-cells = <0>;
178
-
#interrupt-cells = <1>;
179
-
};
180
-
};
181
-
182
-
pcie0: pcie@11700000 {
183
-
compatible = "mediatek,mt2712-pcie";
184
-
device_type = "pci";
185
-
reg = <0 0x11700000 0 0x1000>;
186
-
reg-names = "port0";
187
-
linux,pci-domain = <0>;
188
-
#address-cells = <3>;
189
-
#size-cells = <2>;
190
-
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
191
-
interrupt-names = "pcie_irq";
192
-
clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
193
-
<&pericfg CLK_PERI_PCIE0>;
194
-
clock-names = "sys_ck0", "ahb_ck0";
195
-
phys = <&u3port0 PHY_TYPE_PCIE>;
196
-
phy-names = "pcie-phy0";
197
-
bus-range = <0x00 0xff>;
198
-
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
199
-
status = "disabled";
200
-
201
-
#interrupt-cells = <1>;
202
-
interrupt-map-mask = <0 0 0 7>;
203
-
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
204
-
<0 0 0 2 &pcie_intc0 1>,
205
-
<0 0 0 3 &pcie_intc0 2>,
206
-
<0 0 0 4 &pcie_intc0 3>;
207
-
pcie_intc0: interrupt-controller {
208
-
interrupt-controller;
209
-
#address-cells = <0>;
210
-
#interrupt-cells = <1>;
211
-
};
212
-
};
213
-
214
-
Examples for MT7622:
215
-
216
-
pcie0: pcie@1a143000 {
217
-
compatible = "mediatek,mt7622-pcie";
218
-
device_type = "pci";
219
-
reg = <0 0x1a143000 0 0x1000>;
220
-
reg-names = "port0";
221
-
linux,pci-domain = <0>;
222
-
#address-cells = <3>;
223
-
#size-cells = <2>;
224
-
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
225
-
interrupt-names = "pcie_irq";
226
-
clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
227
-
<&pciesys CLK_PCIE_P0_AHB_EN>,
228
-
<&pciesys CLK_PCIE_P0_AUX_EN>,
229
-
<&pciesys CLK_PCIE_P0_AXI_EN>,
230
-
<&pciesys CLK_PCIE_P0_OBFF_EN>,
231
-
<&pciesys CLK_PCIE_P0_PIPE_EN>;
232
-
clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
233
-
"axi_ck0", "obff_ck0", "pipe_ck0";
234
-
235
-
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
236
-
bus-range = <0x00 0xff>;
237
-
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
238
-
status = "disabled";
239
-
240
-
#interrupt-cells = <1>;
241
-
interrupt-map-mask = <0 0 0 7>;
242
-
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
243
-
<0 0 0 2 &pcie_intc0 1>,
244
-
<0 0 0 3 &pcie_intc0 2>,
245
-
<0 0 0 4 &pcie_intc0 3>;
246
-
pcie_intc0: interrupt-controller {
247
-
interrupt-controller;
248
-
#address-cells = <0>;
249
-
#interrupt-cells = <1>;
250
-
};
251
-
};
252
-
253
-
pcie1: pcie@1a145000 {
254
-
compatible = "mediatek,mt7622-pcie";
255
-
device_type = "pci";
256
-
reg = <0 0x1a145000 0 0x1000>;
257
-
reg-names = "port1";
258
-
linux,pci-domain = <1>;
259
-
#address-cells = <3>;
260
-
#size-cells = <2>;
261
-
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
262
-
interrupt-names = "pcie_irq";
263
-
clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
264
-
/* designer has connect RC1 with p0_ahb clock */
265
-
<&pciesys CLK_PCIE_P0_AHB_EN>,
266
-
<&pciesys CLK_PCIE_P1_AUX_EN>,
267
-
<&pciesys CLK_PCIE_P1_AXI_EN>,
268
-
<&pciesys CLK_PCIE_P1_OBFF_EN>,
269
-
<&pciesys CLK_PCIE_P1_PIPE_EN>;
270
-
clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
271
-
"axi_ck1", "obff_ck1", "pipe_ck1";
272
-
273
-
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
274
-
bus-range = <0x00 0xff>;
275
-
ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
276
-
status = "disabled";
277
-
278
-
#interrupt-cells = <1>;
279
-
interrupt-map-mask = <0 0 0 7>;
280
-
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
281
-
<0 0 0 2 &pcie_intc1 1>,
282
-
<0 0 0 3 &pcie_intc1 2>,
283
-
<0 0 0 4 &pcie_intc1 3>;
284
-
pcie_intc1: interrupt-controller {
285
-
interrupt-controller;
286
-
#address-cells = <0>;
287
-
#interrupt-cells = <1>;
288
-
};
289
-
};
+438
Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
+438
Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/mediatek-pcie.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: PCIe controller on MediaTek SoCs
8
+
9
+
maintainers:
10
+
- Christian Marangi <ansuelsmth@gmail.com>
11
+
12
+
properties:
13
+
compatible:
14
+
oneOf:
15
+
- enum:
16
+
- airoha,an7583-pcie
17
+
- mediatek,mt2712-pcie
18
+
- mediatek,mt7622-pcie
19
+
- mediatek,mt7629-pcie
20
+
- items:
21
+
- const: airoha,en7523-pcie
22
+
- const: mediatek,mt7622-pcie
23
+
24
+
reg:
25
+
maxItems: 1
26
+
27
+
reg-names:
28
+
enum: [ port0, port1 ]
29
+
30
+
clocks:
31
+
minItems: 1
32
+
maxItems: 6
33
+
34
+
clock-names:
35
+
minItems: 1
36
+
items:
37
+
- enum: [ sys_ck0, sys_ck1 ]
38
+
- enum: [ ahb_ck0, ahb_ck1 ]
39
+
- enum: [ aux_ck0, aux_ck1 ]
40
+
- enum: [ axi_ck0, axi_ck1 ]
41
+
- enum: [ obff_ck0, obff_ck1 ]
42
+
- enum: [ pipe_ck0, pipe_ck1 ]
43
+
44
+
resets:
45
+
maxItems: 1
46
+
47
+
reset-names:
48
+
const: pcie-rst1
49
+
50
+
interrupts:
51
+
maxItems: 1
52
+
53
+
interrupt-names:
54
+
const: pcie_irq
55
+
56
+
phys:
57
+
maxItems: 1
58
+
59
+
phy-names:
60
+
enum: [ pcie-phy0, pcie-phy1 ]
61
+
62
+
power-domains:
63
+
maxItems: 1
64
+
65
+
mediatek,pbus-csr:
66
+
$ref: /schemas/types.yaml#/definitions/phandle-array
67
+
items:
68
+
- items:
69
+
- description: phandle to pbus-csr syscon
70
+
- description: offset of pbus-csr base address register
71
+
- description: offset of pbus-csr base address mask register
72
+
description:
73
+
Phandle with two arguments to the syscon node used to detect if
74
+
a given address is accessible on PCIe controller.
75
+
76
+
'#interrupt-cells':
77
+
const: 1
78
+
79
+
interrupt-controller:
80
+
description: Interrupt controller node for handling legacy PCI interrupts.
81
+
type: object
82
+
properties:
83
+
'#address-cells':
84
+
const: 0
85
+
'#interrupt-cells':
86
+
const: 1
87
+
interrupt-controller: true
88
+
89
+
required:
90
+
- '#address-cells'
91
+
- '#interrupt-cells'
92
+
- interrupt-controller
93
+
94
+
additionalProperties: false
95
+
96
+
required:
97
+
- compatible
98
+
- reg
99
+
- reg-names
100
+
- ranges
101
+
- clocks
102
+
- clock-names
103
+
- '#interrupt-cells'
104
+
- interrupts
105
+
- interrupt-names
106
+
- interrupt-controller
107
+
108
+
allOf:
109
+
- $ref: /schemas/pci/pci-host-bridge.yaml#
110
+
111
+
- if:
112
+
properties:
113
+
compatible:
114
+
const: airoha,an7583-pcie
115
+
then:
116
+
properties:
117
+
reg-names:
118
+
const: port1
119
+
120
+
clocks:
121
+
maxItems: 1
122
+
123
+
clock-names:
124
+
const: sys_ck1
125
+
126
+
phy-names:
127
+
const: pcie-phy1
128
+
129
+
power-domain: false
130
+
131
+
required:
132
+
- resets
133
+
- reset-names
134
+
- phys
135
+
- phy-names
136
+
- mediatek,pbus-csr
137
+
138
+
- if:
139
+
properties:
140
+
compatible:
141
+
const: mediatek,mt2712-pcie
142
+
then:
143
+
properties:
144
+
clocks:
145
+
minItems: 2
146
+
maxItems: 2
147
+
148
+
clock-names:
149
+
minItems: 2
150
+
maxItems: 2
151
+
152
+
reset: false
153
+
154
+
reset-names: false
155
+
156
+
power-domains: false
157
+
158
+
mediatek,pbus-csr: false
159
+
160
+
required:
161
+
- phys
162
+
- phy-names
163
+
164
+
- if:
165
+
properties:
166
+
compatible:
167
+
const: mediatek,mt7622-pcie
168
+
then:
169
+
properties:
170
+
clocks:
171
+
minItems: 6
172
+
173
+
reset: false
174
+
175
+
reset-names: false
176
+
177
+
phys: false
178
+
179
+
phy-names: false
180
+
181
+
mediatek,pbus-csr: false
182
+
183
+
required:
184
+
- power-domains
185
+
186
+
- if:
187
+
properties:
188
+
compatible:
189
+
const: mediatek,mt7629-pcie
190
+
then:
191
+
properties:
192
+
clocks:
193
+
minItems: 6
194
+
195
+
reset: false
196
+
197
+
reset-names: false
198
+
199
+
mediatek,pbus-csr: false
200
+
201
+
required:
202
+
- power-domains
203
+
204
+
- if:
205
+
properties:
206
+
compatible:
207
+
contains:
208
+
const: airoha,en7523-pcie
209
+
then:
210
+
properties:
211
+
clocks:
212
+
maxItems: 1
213
+
214
+
clock-names:
215
+
maxItems: 1
216
+
217
+
reset: false
218
+
219
+
reset-names: false
220
+
221
+
phys: false
222
+
223
+
phy-names: false
224
+
225
+
power-domain: false
226
+
227
+
mediatek,pbus-csr: false
228
+
229
+
unevaluatedProperties: false
230
+
231
+
examples:
232
+
# MT2712
233
+
- |
234
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
235
+
#include <dt-bindings/interrupt-controller/irq.h>
236
+
#include <dt-bindings/phy/phy.h>
237
+
238
+
soc_1 {
239
+
#address-cells = <2>;
240
+
#size-cells = <2>;
241
+
242
+
pcie@112ff000 {
243
+
compatible = "mediatek,mt2712-pcie";
244
+
device_type = "pci";
245
+
reg = <0 0x112ff000 0 0x1000>;
246
+
reg-names = "port1";
247
+
linux,pci-domain = <1>;
248
+
#address-cells = <3>;
249
+
#size-cells = <2>;
250
+
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
251
+
interrupt-names = "pcie_irq";
252
+
clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P1_SEL */
253
+
<&pericfg>; /* CLK_PERI_PCIE1 */
254
+
clock-names = "sys_ck1", "ahb_ck1";
255
+
phys = <&u3port1 PHY_TYPE_PCIE>;
256
+
phy-names = "pcie-phy1";
257
+
bus-range = <0x00 0xff>;
258
+
ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
259
+
260
+
#interrupt-cells = <1>;
261
+
interrupt-map-mask = <0 0 0 7>;
262
+
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
263
+
<0 0 0 2 &pcie_intc1 1>,
264
+
<0 0 0 3 &pcie_intc1 2>,
265
+
<0 0 0 4 &pcie_intc1 3>;
266
+
pcie_intc1: interrupt-controller {
267
+
interrupt-controller;
268
+
#address-cells = <0>;
269
+
#interrupt-cells = <1>;
270
+
};
271
+
};
272
+
273
+
pcie@11700000 {
274
+
compatible = "mediatek,mt2712-pcie";
275
+
device_type = "pci";
276
+
reg = <0 0x11700000 0 0x1000>;
277
+
reg-names = "port0";
278
+
linux,pci-domain = <0>;
279
+
#address-cells = <3>;
280
+
#size-cells = <2>;
281
+
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
282
+
interrupt-names = "pcie_irq";
283
+
clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P0_SEL */
284
+
<&pericfg>; /* CLK_PERI_PCIE0 */
285
+
clock-names = "sys_ck0", "ahb_ck0";
286
+
phys = <&u3port0 PHY_TYPE_PCIE>;
287
+
phy-names = "pcie-phy0";
288
+
bus-range = <0x00 0xff>;
289
+
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
290
+
291
+
#interrupt-cells = <1>;
292
+
interrupt-map-mask = <0 0 0 7>;
293
+
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
294
+
<0 0 0 2 &pcie_intc0 1>,
295
+
<0 0 0 3 &pcie_intc0 2>,
296
+
<0 0 0 4 &pcie_intc0 3>;
297
+
pcie_intc0: interrupt-controller {
298
+
interrupt-controller;
299
+
#address-cells = <0>;
300
+
#interrupt-cells = <1>;
301
+
};
302
+
};
303
+
};
304
+
305
+
# MT7622
306
+
- |
307
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
308
+
#include <dt-bindings/interrupt-controller/irq.h>
309
+
#include <dt-bindings/power/mt7622-power.h>
310
+
311
+
soc_2 {
312
+
#address-cells = <2>;
313
+
#size-cells = <2>;
314
+
315
+
pcie@1a143000 {
316
+
compatible = "mediatek,mt7622-pcie";
317
+
device_type = "pci";
318
+
reg = <0 0x1a143000 0 0x1000>;
319
+
reg-names = "port0";
320
+
linux,pci-domain = <0>;
321
+
#address-cells = <3>;
322
+
#size-cells = <2>;
323
+
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
324
+
interrupt-names = "pcie_irq";
325
+
clocks = <&pciesys>, /* CLK_PCIE_P0_MAC_EN */
326
+
<&pciesys>, /* CLK_PCIE_P0_AHB_EN */
327
+
<&pciesys>, /* CLK_PCIE_P0_AUX_EN */
328
+
<&pciesys>, /* CLK_PCIE_P0_AXI_EN */
329
+
<&pciesys>, /* CLK_PCIE_P0_OBFF_EN */
330
+
<&pciesys>; /* CLK_PCIE_P0_PIPE_EN */
331
+
clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
332
+
"axi_ck0", "obff_ck0", "pipe_ck0";
333
+
334
+
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
335
+
bus-range = <0x00 0xff>;
336
+
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
337
+
338
+
#interrupt-cells = <1>;
339
+
interrupt-map-mask = <0 0 0 7>;
340
+
interrupt-map = <0 0 0 1 &pcie_intc0_1 0>,
341
+
<0 0 0 2 &pcie_intc0_1 1>,
342
+
<0 0 0 3 &pcie_intc0_1 2>,
343
+
<0 0 0 4 &pcie_intc0_1 3>;
344
+
pcie_intc0_1: interrupt-controller {
345
+
interrupt-controller;
346
+
#address-cells = <0>;
347
+
#interrupt-cells = <1>;
348
+
};
349
+
};
350
+
351
+
pcie@1a145000 {
352
+
compatible = "mediatek,mt7622-pcie";
353
+
device_type = "pci";
354
+
reg = <0 0x1a145000 0 0x1000>;
355
+
reg-names = "port1";
356
+
linux,pci-domain = <1>;
357
+
#address-cells = <3>;
358
+
#size-cells = <2>;
359
+
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
360
+
interrupt-names = "pcie_irq";
361
+
clocks = <&pciesys>, /* CLK_PCIE_P1_MAC_EN */
362
+
/* designer has connect RC1 with p0_ahb clock */
363
+
<&pciesys>, /* CLK_PCIE_P0_AHB_EN */
364
+
<&pciesys>, /* CLK_PCIE_P1_AUX_EN */
365
+
<&pciesys>, /* CLK_PCIE_P1_AXI_EN */
366
+
<&pciesys>, /* CLK_PCIE_P1_OBFF_EN */
367
+
<&pciesys>; /* CLK_PCIE_P1_PIPE_EN */
368
+
clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
369
+
"axi_ck1", "obff_ck1", "pipe_ck1";
370
+
371
+
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
372
+
bus-range = <0x00 0xff>;
373
+
ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
374
+
375
+
#interrupt-cells = <1>;
376
+
interrupt-map-mask = <0 0 0 7>;
377
+
interrupt-map = <0 0 0 1 &pcie_intc1_1 0>,
378
+
<0 0 0 2 &pcie_intc1_1 1>,
379
+
<0 0 0 3 &pcie_intc1_1 2>,
380
+
<0 0 0 4 &pcie_intc1_1 3>;
381
+
pcie_intc1_1: interrupt-controller {
382
+
interrupt-controller;
383
+
#address-cells = <0>;
384
+
#interrupt-cells = <1>;
385
+
};
386
+
};
387
+
};
388
+
389
+
# AN7583
390
+
- |
391
+
#include <dt-bindings/interrupt-controller/irq.h>
392
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
393
+
#include <dt-bindings/clock/en7523-clk.h>
394
+
395
+
soc_3 {
396
+
#address-cells = <2>;
397
+
#size-cells = <2>;
398
+
399
+
pcie@1fa92000 {
400
+
compatible = "airoha,an7583-pcie";
401
+
device_type = "pci";
402
+
linux,pci-domain = <1>;
403
+
#address-cells = <3>;
404
+
#size-cells = <2>;
405
+
406
+
reg = <0x0 0x1fa92000 0x0 0x1670>;
407
+
reg-names = "port1";
408
+
409
+
clocks = <&scuclk EN7523_CLK_PCIE>;
410
+
clock-names = "sys_ck1";
411
+
412
+
phys = <&pciephy>;
413
+
phy-names = "pcie-phy1";
414
+
415
+
ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>;
416
+
417
+
resets = <&scuclk>; /* AN7583_PCIE1_RST */
418
+
reset-names = "pcie-rst1";
419
+
420
+
mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
421
+
422
+
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
423
+
interrupt-names = "pcie_irq";
424
+
bus-range = <0x00 0xff>;
425
+
#interrupt-cells = <1>;
426
+
interrupt-map-mask = <0 0 0 7>;
427
+
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
428
+
<0 0 0 2 &pcie_intc1 1>,
429
+
<0 0 0 3 &pcie_intc1 2>,
430
+
<0 0 0 4 &pcie_intc1 3>;
431
+
432
+
pcie_intc1_4: interrupt-controller {
433
+
interrupt-controller;
434
+
#address-cells = <0>;
435
+
#interrupt-cells = <1>;
436
+
};
437
+
};
438
+
};
+130
Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
+130
Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/nxp,s32g-pcie.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP S32G2xxx/S32G3xxx PCIe Root Complex controller
8
+
9
+
maintainers:
10
+
- Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
11
+
- Ionut Vicovan <ionut.vicovan@nxp.com>
12
+
13
+
description:
14
+
This PCIe controller is based on the Synopsys DesignWare PCIe IP.
15
+
The S32G SoC family has two PCIe controllers, which can be configured as
16
+
either Root Complex or Endpoint.
17
+
18
+
properties:
19
+
compatible:
20
+
oneOf:
21
+
- enum:
22
+
- nxp,s32g2-pcie
23
+
- items:
24
+
- const: nxp,s32g3-pcie
25
+
- const: nxp,s32g2-pcie
26
+
27
+
reg:
28
+
maxItems: 6
29
+
30
+
reg-names:
31
+
items:
32
+
- const: dbi
33
+
- const: dbi2
34
+
- const: atu
35
+
- const: dma
36
+
- const: ctrl
37
+
- const: config
38
+
39
+
interrupts:
40
+
minItems: 1
41
+
maxItems: 2
42
+
43
+
interrupt-names:
44
+
items:
45
+
- const: msi
46
+
- const: dma
47
+
minItems: 1
48
+
49
+
pcie@0:
50
+
description:
51
+
Describe the S32G Root Port.
52
+
type: object
53
+
$ref: /schemas/pci/pci-pci-bridge.yaml#
54
+
55
+
properties:
56
+
reg:
57
+
maxItems: 1
58
+
59
+
phys:
60
+
maxItems: 1
61
+
62
+
required:
63
+
- reg
64
+
- phys
65
+
66
+
unevaluatedProperties: false
67
+
68
+
required:
69
+
- compatible
70
+
- reg
71
+
- reg-names
72
+
- interrupts
73
+
- interrupt-names
74
+
- ranges
75
+
- pcie@0
76
+
77
+
allOf:
78
+
- $ref: /schemas/pci/snps,dw-pcie.yaml#
79
+
80
+
unevaluatedProperties: false
81
+
82
+
examples:
83
+
- |
84
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
85
+
#include <dt-bindings/phy/phy.h>
86
+
87
+
bus {
88
+
#address-cells = <2>;
89
+
#size-cells = <2>;
90
+
91
+
pcie@40400000 {
92
+
compatible = "nxp,s32g3-pcie", "nxp,s32g2-pcie";
93
+
reg = <0x00 0x40400000 0x0 0x00001000>, /* dbi registers */
94
+
<0x00 0x40420000 0x0 0x00001000>, /* dbi2 registers */
95
+
<0x00 0x40460000 0x0 0x00001000>, /* atu registers */
96
+
<0x00 0x40470000 0x0 0x00001000>, /* dma registers */
97
+
<0x00 0x40481000 0x0 0x000000f8>, /* ctrl registers */
98
+
<0x5f 0xffffe000 0x0 0x00002000>; /* config space */
99
+
reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", "config";
100
+
dma-coherent;
101
+
#address-cells = <3>;
102
+
#size-cells = <2>;
103
+
device_type = "pci";
104
+
ranges =
105
+
<0x01000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>,
106
+
<0x02000000 0x0 0x00000000 0x58 0x00000000 0x0 0x80000000>,
107
+
<0x02000000 0x1 0x00000000 0x59 0x00000000 0x6 0xfffe0000>;
108
+
109
+
bus-range = <0x0 0xff>;
110
+
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
111
+
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
112
+
interrupt-names = "msi", "dma";
113
+
#interrupt-cells = <1>;
114
+
interrupt-map-mask = <0 0 0 0x7>;
115
+
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
116
+
<0 0 0 2 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
117
+
<0 0 0 3 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
118
+
<0 0 0 4 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
119
+
120
+
pcie@0 {
121
+
reg = <0x0 0x0 0x0 0x0 0x0>;
122
+
#address-cells = <3>;
123
+
#size-cells = <2>;
124
+
ranges;
125
+
126
+
device_type = "pci";
127
+
phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
128
+
};
129
+
};
130
+
};
+1
-1
Documentation/devicetree/bindings/pci/pci-ep.yaml
+1
-1
Documentation/devicetree/bindings/pci/pci-ep.yaml
+1
-1
Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
+1
-1
Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
+1
-1
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+1
-1
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+1
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
+1
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
+4
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
+4
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
···
8
8
9
9
maintainers:
10
10
- Bjorn Andersson <andersson@kernel.org>
11
-
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
12
13
13
description:
14
14
Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
···
78
78
required:
79
79
- interconnects
80
80
- interconnect-names
81
+
- power-domains
82
+
- resets
83
+
- reset-names
81
84
82
85
allOf:
83
86
- $ref: qcom,pcie-common.yaml#
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml
···
8
8
9
9
maintainers:
10
10
- Bjorn Andersson <andersson@kernel.org>
11
-
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
12
13
13
description:
14
14
Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys
···
75
75
reset-names:
76
76
items:
77
77
- const: pci
78
+
79
+
required:
80
+
- power-domains
81
+
- resets
82
+
- reset-names
78
83
79
84
allOf:
80
85
- $ref: qcom,pcie-common.yaml#
+1
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml
+1
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml
+4
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml
+4
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml
···
8
8
9
9
maintainers:
10
10
- Bjorn Andersson <andersson@kernel.org>
11
-
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
12
13
13
description:
14
14
Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys
···
61
61
required:
62
62
- interconnects
63
63
- interconnect-names
64
+
- power-domains
65
+
- resets
66
+
- reset-names
64
67
65
68
allOf:
66
69
- $ref: qcom,pcie-common.yaml#
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml
···
8
8
9
9
maintainers:
10
10
- Bjorn Andersson <andersson@kernel.org>
11
-
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
12
13
13
description:
14
14
Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys
···
73
73
reset-names:
74
74
items:
75
75
- const: pci
76
+
77
+
required:
78
+
- power-domains
79
+
- resets
80
+
- reset-names
76
81
77
82
allOf:
78
83
- $ref: qcom,pcie-common.yaml#
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml
···
8
8
9
9
maintainers:
10
10
- Bjorn Andersson <andersson@kernel.org>
11
-
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
12
13
13
description:
14
14
Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys
···
82
82
reset-names:
83
83
items:
84
84
- const: pci
85
+
86
+
required:
87
+
- power-domains
88
+
- resets
89
+
- reset-names
85
90
86
91
allOf:
87
92
- $ref: qcom,pcie-common.yaml#
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml
···
8
8
9
9
maintainers:
10
10
- Bjorn Andersson <andersson@kernel.org>
11
-
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
12
13
13
description:
14
14
Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys
···
72
72
reset-names:
73
73
items:
74
74
- const: pci
75
+
76
+
required:
77
+
- power-domains
78
+
- resets
79
+
- reset-names
75
80
76
81
allOf:
77
82
- $ref: qcom,pcie-common.yaml#
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
···
8
8
9
9
maintainers:
10
10
- Bjorn Andersson <andersson@kernel.org>
11
-
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
12
13
13
description:
14
14
Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
···
76
76
reset-names:
77
77
items:
78
78
- const: pci
79
+
80
+
required:
81
+
- power-domains
82
+
- resets
83
+
- reset-names
79
84
80
85
allOf:
81
86
- $ref: qcom,pcie-common.yaml#
+7
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
+7
-1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
···
8
8
9
9
maintainers:
10
10
- Bjorn Andersson <andersson@kernel.org>
11
-
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
12
13
13
description:
14
14
Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
···
20
20
- const: qcom,pcie-sm8550
21
21
- items:
22
22
- enum:
23
+
- qcom,kaanapali-pcie
23
24
- qcom,sar2130p-pcie
24
25
- qcom,pcie-sm8650
25
26
- qcom,pcie-sm8750
···
83
82
items:
84
83
- const: pci # PCIe core reset
85
84
- const: link_down # PCIe link down reset
85
+
86
+
required:
87
+
- power-domains
88
+
- resets
89
+
- reset-names
86
90
87
91
allOf:
88
92
- $ref: qcom,pcie-common.yaml#
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
···
8
8
9
9
maintainers:
10
10
- Bjorn Andersson <andersson@kernel.org>
11
-
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
12
13
13
description:
14
14
Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
···
72
72
items:
73
73
- const: pci # PCIe core reset
74
74
- const: link_down # PCIe link down reset
75
+
76
+
required:
77
+
- power-domains
78
+
- resets
79
+
- reset-names
75
80
76
81
allOf:
77
82
- $ref: qcom,pcie-common.yaml#
+1
-1
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+1
-1
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+249
Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
+249
Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/renesas,r9a08g045-pcie.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Renesas RZ/G3S PCIe host controller
8
+
9
+
maintainers:
10
+
- Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
11
+
12
+
description:
13
+
Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification
14
+
4.0 and supports up to 5 GT/s (Gen2).
15
+
16
+
properties:
17
+
compatible:
18
+
const: renesas,r9a08g045-pcie # RZ/G3S
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts:
24
+
items:
25
+
- description: System error interrupt
26
+
- description: System error on correctable error interrupt
27
+
- description: System error on non-fatal error interrupt
28
+
- description: System error on fatal error interrupt
29
+
- description: AXI error interrupt
30
+
- description: INTA interrupt
31
+
- description: INTB interrupt
32
+
- description: INTC interrupt
33
+
- description: INTD interrupt
34
+
- description: MSI interrupt
35
+
- description: Link bandwidth interrupt
36
+
- description: PME interrupt
37
+
- description: DMA interrupt
38
+
- description: PCIe event interrupt
39
+
- description: Message interrupt
40
+
- description: All interrupts
41
+
42
+
interrupt-names:
43
+
items:
44
+
- description: serr
45
+
- description: ser_cor
46
+
- description: serr_nonfatal
47
+
- description: serr_fatal
48
+
- description: axi_err
49
+
- description: inta
50
+
- description: intb
51
+
- description: intc
52
+
- description: intd
53
+
- description: msi
54
+
- description: link_bandwidth
55
+
- description: pm_pme
56
+
- description: dma
57
+
- description: pcie_evt
58
+
- description: msg
59
+
- description: all
60
+
61
+
interrupt-controller: true
62
+
63
+
clocks:
64
+
items:
65
+
- description: System clock
66
+
- description: PM control clock
67
+
68
+
clock-names:
69
+
items:
70
+
- description: aclk
71
+
- description: pm
72
+
73
+
resets:
74
+
items:
75
+
- description: AXI2PCIe Bridge reset
76
+
- description: Data link layer/transaction layer reset
77
+
- description: Transaction layer (ACLK domain) reset
78
+
- description: Transaction layer (PCLK domain) reset
79
+
- description: Physical layer reset
80
+
- description: Configuration register reset
81
+
- description: Configuration register reset
82
+
83
+
reset-names:
84
+
items:
85
+
- description: aresetn
86
+
- description: rst_b
87
+
- description: rst_gp_b
88
+
- description: rst_ps_b
89
+
- description: rst_rsm_b
90
+
- description: rst_cfg_b
91
+
- description: rst_load_b
92
+
93
+
power-domains:
94
+
maxItems: 1
95
+
96
+
dma-ranges:
97
+
description:
98
+
A single range for the inbound memory region.
99
+
maxItems: 1
100
+
101
+
renesas,sysc:
102
+
description: |
103
+
System controller registers control and monitor various PCIe
104
+
functionalities.
105
+
106
+
Control:
107
+
- transition to L1 state
108
+
- receiver termination settings
109
+
- RST_RSM_B signal
110
+
111
+
Monitor:
112
+
- clkl1pm clock request state
113
+
- power off information in L2 state
114
+
- errors (fatal, non-fatal, correctable)
115
+
$ref: /schemas/types.yaml#/definitions/phandle
116
+
117
+
patternProperties:
118
+
"^pcie@0,[0-0]$":
119
+
type: object
120
+
allOf:
121
+
- $ref: /schemas/pci/pci-pci-bridge.yaml#
122
+
123
+
properties:
124
+
reg:
125
+
maxItems: 1
126
+
127
+
vendor-id:
128
+
const: 0x1912
129
+
130
+
device-id:
131
+
const: 0x0033
132
+
133
+
clocks:
134
+
items:
135
+
- description: Reference clock
136
+
137
+
clock-names:
138
+
items:
139
+
- const: ref
140
+
141
+
required:
142
+
- device_type
143
+
- vendor-id
144
+
- device-id
145
+
- clocks
146
+
- clock-names
147
+
148
+
unevaluatedProperties: false
149
+
150
+
required:
151
+
- compatible
152
+
- reg
153
+
- clocks
154
+
- clock-names
155
+
- resets
156
+
- reset-names
157
+
- interrupts
158
+
- interrupt-names
159
+
- interrupt-map
160
+
- interrupt-map-mask
161
+
- interrupt-controller
162
+
- power-domains
163
+
- "#address-cells"
164
+
- "#size-cells"
165
+
- "#interrupt-cells"
166
+
- renesas,sysc
167
+
168
+
allOf:
169
+
- $ref: /schemas/pci/pci-host-bridge.yaml#
170
+
171
+
unevaluatedProperties: false
172
+
173
+
examples:
174
+
- |
175
+
#include <dt-bindings/clock/r9a08g045-cpg.h>
176
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
177
+
178
+
bus {
179
+
#address-cells = <2>;
180
+
#size-cells = <2>;
181
+
182
+
pcie@11e40000 {
183
+
compatible = "renesas,r9a08g045-pcie";
184
+
reg = <0 0x11e40000 0 0x10000>;
185
+
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
186
+
/* Map all possible DRAM ranges (4 GB). */
187
+
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;
188
+
bus-range = <0x0 0xff>;
189
+
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
190
+
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
191
+
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
192
+
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
193
+
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
194
+
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
195
+
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
196
+
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
197
+
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
198
+
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
199
+
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
200
+
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
201
+
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
202
+
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
203
+
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
204
+
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
205
+
interrupt-names = "serr", "serr_cor", "serr_nonfatal",
206
+
"serr_fatal", "axi_err", "inta",
207
+
"intb", "intc", "intd", "msi",
208
+
"link_bandwidth", "pm_pme", "dma",
209
+
"pcie_evt", "msg", "all";
210
+
#interrupt-cells = <1>;
211
+
interrupt-controller;
212
+
interrupt-map-mask = <0 0 0 7>;
213
+
interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */
214
+
<0 0 0 2 &pcie 0 0 0 1>, /* INTB */
215
+
<0 0 0 3 &pcie 0 0 0 2>, /* INTC */
216
+
<0 0 0 4 &pcie 0 0 0 3>; /* INTD */
217
+
clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>,
218
+
<&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>;
219
+
clock-names = "aclk", "pm";
220
+
resets = <&cpg R9A08G045_PCI_ARESETN>,
221
+
<&cpg R9A08G045_PCI_RST_B>,
222
+
<&cpg R9A08G045_PCI_RST_GP_B>,
223
+
<&cpg R9A08G045_PCI_RST_PS_B>,
224
+
<&cpg R9A08G045_PCI_RST_RSM_B>,
225
+
<&cpg R9A08G045_PCI_RST_CFG_B>,
226
+
<&cpg R9A08G045_PCI_RST_LOAD_B>;
227
+
reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b",
228
+
"rst_rsm_b", "rst_cfg_b", "rst_load_b";
229
+
power-domains = <&cpg>;
230
+
device_type = "pci";
231
+
#address-cells = <3>;
232
+
#size-cells = <2>;
233
+
renesas,sysc = <&sysc>;
234
+
235
+
pcie@0,0 {
236
+
reg = <0x0 0x0 0x0 0x0 0x0>;
237
+
ranges;
238
+
clocks = <&versa3 5>;
239
+
clock-names = "ref";
240
+
device_type = "pci";
241
+
vendor-id = <0x1912>;
242
+
device-id = <0x0033>;
243
+
#address-cells = <3>;
244
+
#size-cells = <2>;
245
+
};
246
+
};
247
+
};
248
+
249
+
...
+3
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+3
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
···
22
22
- const: rockchip,rk3568-pcie
23
23
- items:
24
24
- enum:
25
+
- rockchip,rk3528-pcie
25
26
- rockchip,rk3562-pcie
26
27
- rockchip,rk3576-pcie
27
28
- rockchip,rk3588-pcie
···
79
78
compatible:
80
79
contains:
81
80
enum:
81
+
- rockchip,rk3528-pcie
82
82
- rockchip,rk3562-pcie
83
83
- rockchip,rk3576-pcie
84
84
then:
···
91
89
compatible:
92
90
contains:
93
91
enum:
92
+
- rockchip,rk3528-pcie
94
93
- rockchip,rk3562-pcie
95
94
- rockchip,rk3576-pcie
96
95
then:
+3
-3
Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
+3
-3
Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
···
115
115
above for new bindings.
116
116
oneOf:
117
117
- description: See native 'dbi' clock for details
118
-
enum: [ pcie, pcie_apb_sys, aclk_dbi, reg ]
118
+
enum: [ pcie, pcie_apb_sys, aclk_dbi, reg, port ]
119
119
- description: See native 'mstr/slv' clock for details
120
120
enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ]
121
121
- description: See native 'pipe' clock for details
122
-
enum: [ pcie_phy, pcie_phy_ref, link ]
122
+
enum: [ pcie_phy, pcie_phy_ref, link, general ]
123
123
- description: See native 'aux' clock for details
124
124
enum: [ pcie_aux ]
125
125
- description: See native 'ref' clock for details.
···
176
176
- description: See native 'phy' reset for details
177
177
enum: [ pciephy, link ]
178
178
- description: See native 'pwr' reset for details
179
-
enum: [ turnoff ]
179
+
enum: [ turnoff, port ]
180
180
181
181
phys:
182
182
description:
+157
Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
+157
Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: SpacemiT K1 PCI Express Host Controller
8
+
9
+
maintainers:
10
+
- Alex Elder <elder@riscstar.com>
11
+
12
+
description: >
13
+
The SpacemiT K1 SoC PCIe host controller is based on the Synopsys DesignWare
14
+
PCIe IP. The controller uses the DesignWare built-in MSI interrupt
15
+
controller, and supports 256 MSIs.
16
+
17
+
allOf:
18
+
- $ref: /schemas/pci/snps,dw-pcie.yaml#
19
+
20
+
properties:
21
+
compatible:
22
+
const: spacemit,k1-pcie
23
+
24
+
reg:
25
+
items:
26
+
- description: DesignWare PCIe registers
27
+
- description: ATU address space
28
+
- description: PCIe configuration space
29
+
- description: Link control registers
30
+
31
+
reg-names:
32
+
items:
33
+
- const: dbi
34
+
- const: atu
35
+
- const: config
36
+
- const: link
37
+
38
+
clocks:
39
+
items:
40
+
- description: DWC PCIe Data Bus Interface (DBI) clock
41
+
- description: DWC PCIe application AXI-bus master interface clock
42
+
- description: DWC PCIe application AXI-bus slave interface clock
43
+
44
+
clock-names:
45
+
items:
46
+
- const: dbi
47
+
- const: mstr
48
+
- const: slv
49
+
50
+
resets:
51
+
items:
52
+
- description: DWC PCIe Data Bus Interface (DBI) reset
53
+
- description: DWC PCIe application AXI-bus master interface reset
54
+
- description: DWC PCIe application AXI-bus slave interface reset
55
+
56
+
reset-names:
57
+
items:
58
+
- const: dbi
59
+
- const: mstr
60
+
- const: slv
61
+
62
+
interrupts:
63
+
items:
64
+
- description: Interrupt used for MSIs
65
+
66
+
interrupt-names:
67
+
const: msi
68
+
69
+
spacemit,apmu:
70
+
$ref: /schemas/types.yaml#/definitions/phandle-array
71
+
description:
72
+
A phandle that refers to the APMU system controller, whose regmap is
73
+
used in managing resets and link state, along with and offset of its
74
+
reset control register.
75
+
items:
76
+
- items:
77
+
- description: phandle to APMU system controller
78
+
- description: register offset
79
+
80
+
patternProperties:
81
+
'^pcie@':
82
+
type: object
83
+
$ref: /schemas/pci/pci-pci-bridge.yaml#
84
+
85
+
properties:
86
+
phys:
87
+
maxItems: 1
88
+
89
+
vpcie3v3-supply:
90
+
description:
91
+
A phandle for 3.3v regulator to use for PCIe
92
+
93
+
required:
94
+
- phys
95
+
- vpcie3v3-supply
96
+
97
+
unevaluatedProperties: false
98
+
99
+
required:
100
+
- clocks
101
+
- clock-names
102
+
- resets
103
+
- reset-names
104
+
- interrupts
105
+
- interrupt-names
106
+
- spacemit,apmu
107
+
108
+
unevaluatedProperties: false
109
+
110
+
examples:
111
+
- |
112
+
#include <dt-bindings/clock/spacemit,k1-syscon.h>
113
+
pcie@ca400000 {
114
+
device_type = "pci";
115
+
compatible = "spacemit,k1-pcie";
116
+
reg = <0xca400000 0x00001000>,
117
+
<0xca700000 0x0001ff24>,
118
+
<0x9f000000 0x00002000>,
119
+
<0xc0c20000 0x00001000>;
120
+
reg-names = "dbi",
121
+
"atu",
122
+
"config",
123
+
"link";
124
+
#address-cells = <3>;
125
+
#size-cells = <2>;
126
+
ranges = <0x01000000 0x0 0x00000000 0x9f002000 0x0 0x00100000>,
127
+
<0x02000000 0x0 0x90000000 0x90000000 0x0 0x0f000000>;
128
+
interrupts = <142>;
129
+
interrupt-names = "msi";
130
+
clocks = <&syscon_apmu CLK_PCIE1_DBI>,
131
+
<&syscon_apmu CLK_PCIE1_MASTER>,
132
+
<&syscon_apmu CLK_PCIE1_SLAVE>;
133
+
clock-names = "dbi",
134
+
"mstr",
135
+
"slv";
136
+
resets = <&syscon_apmu RESET_PCIE1_DBI>,
137
+
<&syscon_apmu RESET_PCIE1_MASTER>,
138
+
<&syscon_apmu RESET_PCIE1_SLAVE>;
139
+
reset-names = "dbi",
140
+
"mstr",
141
+
"slv";
142
+
pinctrl-names = "default";
143
+
pinctrl-0 = <&pcie1_3_cfg>;
144
+
spacemit,apmu = <&syscon_apmu 0x3d4>;
145
+
146
+
pcie@0 {
147
+
device_type = "pci";
148
+
compatible = "pciclass,0604";
149
+
reg = <0x0 0x0 0x0 0x0 0x0>;
150
+
bus-range = <0x01 0xff>;
151
+
#address-cells = <3>;
152
+
#size-cells = <2>;
153
+
ranges;
154
+
phys = <&pcie1_phy>;
155
+
vpcie3v3-supply = <&pcie_vcc_3v3>;
156
+
};
157
+
};
+179
Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml
+179
Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Toshiba TC9563 PCIe switch
8
+
9
+
maintainers:
10
+
- Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
11
+
12
+
description: |
13
+
Toshiba TC9563 PCIe switch has one upstream and three downstream ports.
14
+
The 3rd downstream port has integrated endpoint device of Ethernet MAC.
15
+
Other two downstream ports are supposed to connect to external device.
16
+
17
+
The TC9563 PCIe switch can be configured through I2C interface before
18
+
PCIe link is established to change FTS, ASPM related entry delays,
19
+
tx amplitude etc for better power efficiency and functionality.
20
+
21
+
properties:
22
+
compatible:
23
+
enum:
24
+
- pci1179,0623
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
resx-gpios:
30
+
maxItems: 1
31
+
description:
32
+
GPIO controlling the RESX# pin.
33
+
34
+
vdd18-supply: true
35
+
36
+
vdd09-supply: true
37
+
38
+
vddc-supply: true
39
+
40
+
vddio1-supply: true
41
+
42
+
vddio2-supply: true
43
+
44
+
vddio18-supply: true
45
+
46
+
i2c-parent:
47
+
$ref: /schemas/types.yaml#/definitions/phandle-array
48
+
description:
49
+
A phandle to the parent I2C node and the slave address of the device
50
+
used to configure tc9563 to change FTS, tx amplitude etc.
51
+
items:
52
+
- description: Phandle to the I2C controller node
53
+
- description: I2C slave address
54
+
55
+
patternProperties:
56
+
"^pcie@[1-3],0$":
57
+
description:
58
+
child nodes describing the internal downstream ports of
59
+
the tc9563 switch.
60
+
type: object
61
+
allOf:
62
+
- $ref: "#/$defs/tc9563-node"
63
+
- $ref: /schemas/pci/pci-pci-bridge.yaml#
64
+
unevaluatedProperties: false
65
+
66
+
$defs:
67
+
tc9563-node:
68
+
type: object
69
+
70
+
properties:
71
+
toshiba,tx-amplitude-microvolt:
72
+
description:
73
+
Change Tx Margin setting for low power consumption.
74
+
75
+
toshiba,no-dfe-support:
76
+
type: boolean
77
+
description:
78
+
Disable DFE (Decision Feedback Equalizer), which mitigates
79
+
intersymbol interference and some reflections caused by
80
+
impedance mismatches.
81
+
82
+
required:
83
+
- resx-gpios
84
+
- vdd18-supply
85
+
- vdd09-supply
86
+
- vddc-supply
87
+
- vddio1-supply
88
+
- vddio2-supply
89
+
- vddio18-supply
90
+
- i2c-parent
91
+
92
+
allOf:
93
+
- $ref: "#/$defs/tc9563-node"
94
+
- $ref: /schemas/pci/pci-bus-common.yaml#
95
+
96
+
unevaluatedProperties: false
97
+
98
+
examples:
99
+
- |
100
+
#include <dt-bindings/gpio/gpio.h>
101
+
102
+
pcie {
103
+
#address-cells = <3>;
104
+
#size-cells = <2>;
105
+
106
+
pcie@0 {
107
+
device_type = "pci";
108
+
reg = <0x0 0x0 0x0 0x0 0x0>;
109
+
110
+
#address-cells = <3>;
111
+
#size-cells = <2>;
112
+
ranges;
113
+
bus-range = <0x01 0xff>;
114
+
115
+
pcie@0,0 {
116
+
compatible = "pci1179,0623";
117
+
118
+
reg = <0x10000 0x0 0x0 0x0 0x0>;
119
+
device_type = "pci";
120
+
#address-cells = <3>;
121
+
#size-cells = <2>;
122
+
ranges;
123
+
bus-range = <0x02 0xff>;
124
+
125
+
i2c-parent = <&qup_i2c 0x77>;
126
+
127
+
vdd18-supply = <&vdd>;
128
+
vdd09-supply = <&vdd>;
129
+
vddc-supply = <&vdd>;
130
+
vddio1-supply = <&vdd>;
131
+
vddio2-supply = <&vdd>;
132
+
vddio18-supply = <&vdd>;
133
+
134
+
resx-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
135
+
136
+
pcie@1,0 {
137
+
compatible = "pciclass,0604";
138
+
reg = <0x20800 0x0 0x0 0x0 0x0>;
139
+
#address-cells = <3>;
140
+
#size-cells = <2>;
141
+
device_type = "pci";
142
+
ranges;
143
+
bus-range = <0x03 0xff>;
144
+
145
+
toshiba,no-dfe-support;
146
+
};
147
+
148
+
pcie@2,0 {
149
+
compatible = "pciclass,0604";
150
+
reg = <0x21000 0x0 0x0 0x0 0x0>;
151
+
#address-cells = <3>;
152
+
#size-cells = <2>;
153
+
device_type = "pci";
154
+
ranges;
155
+
bus-range = <0x04 0xff>;
156
+
};
157
+
158
+
pcie@3,0 {
159
+
compatible = "pciclass,0604";
160
+
reg = <0x21800 0x0 0x0 0x0 0x0>;
161
+
#address-cells = <3>;
162
+
#size-cells = <2>;
163
+
device_type = "pci";
164
+
ranges;
165
+
bus-range = <0x05 0xff>;
166
+
167
+
toshiba,tx-amplitude-microvolt = <10>;
168
+
169
+
ethernet@0,0 {
170
+
reg = <0x50000 0x0 0x0 0x0 0x0>;
171
+
};
172
+
173
+
ethernet@0,1 {
174
+
reg = <0x50100 0x0 0x0 0x0 0x0>;
175
+
};
176
+
};
177
+
};
178
+
};
179
+
};
+3
Documentation/driver-api/pci/pci.rst
+3
Documentation/driver-api/pci/pci.rst
+25
MAINTAINERS
+25
MAINTAINERS
···
3164
3164
F: drivers/pinctrl/nxp/
3165
3165
F: drivers/rtc/rtc-s32g.c
3166
3166
3167
+
ARM/NXP S32G PCIE CONTROLLER DRIVER
3168
+
M: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
3169
+
R: NXP S32 Linux Team <s32@nxp.com>
3170
+
L: imx@lists.linux.dev
3171
+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
3172
+
S: Maintained
3173
+
F: Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
3174
+
F: drivers/pci/controller/dwc/pcie-nxp-s32g*
3175
+
3167
3176
ARM/NXP S32G/S32R DWMAC ETHERNET DRIVER
3168
3177
M: Jan Petrous <jan.petrous@oss.nxp.com>
3169
3178
R: s32@nxp.com
···
19784
19775
F: Documentation/devicetree/bindings/pci/cdns,*
19785
19776
F: drivers/pci/controller/cadence/*cadence*
19786
19777
19778
+
PCI DRIVER FOR CIX Sky1
19779
+
M: Hans Zhang <hans.zhang@cixtech.com>
19780
+
L: linux-pci@vger.kernel.org
19781
+
S: Maintained
19782
+
F: Documentation/devicetree/bindings/pci/cix,sky1-pcie-*.yaml
19783
+
F: drivers/pci/controller/cadence/*sky1*
19784
+
19787
19785
PCI DRIVER FOR FREESCALE LAYERSCAPE
19788
19786
M: Minghuan Lian <minghuan.Lian@nxp.com>
19789
19787
M: Mingkai Hu <mingkai.hu@nxp.com>
···
20041
20025
20042
20026
PCI POWER CONTROL
20043
20027
M: Bartosz Golaszewski <brgl@kernel.org>
20028
+
M: Manivannan Sadhasivam <mani@kernel.org>
20044
20029
L: linux-pci@vger.kernel.org
20045
20030
S: Maintained
20046
20031
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
···
20177
20160
S: Maintained
20178
20161
F: drivers/pci/controller/dwc/pcie-qcom-common.c
20179
20162
F: drivers/pci/controller/dwc/pcie-qcom.c
20163
+
20164
+
PCIE DRIVER FOR RENESAS RZ/G3S SERIES
20165
+
M: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
20166
+
L: linux-pci@vger.kernel.org
20167
+
L: linux-renesas-soc@vger.kernel.org
20168
+
S: Supported
20169
+
F: Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
20170
+
F: drivers/pci/controller/pcie-rzg3s-host.c
20180
20171
20181
20172
PCIE DRIVER FOR ROCKCHIP
20182
20173
M: Shawn Lin <shawn.lin@rock-chips.com>
-2
drivers/crypto/intel/qat/qat_common/adf_aer.c
-2
drivers/crypto/intel/qat/qat_common/adf_aer.c
···
105
105
accel_dev->accel_id);
106
106
hw_device->reset_device(accel_dev);
107
107
pci_restore_state(pdev);
108
-
pci_save_state(pdev);
109
108
}
110
109
}
111
110
···
203
204
if (!pdev->is_busmaster)
204
205
pci_set_master(pdev);
205
206
pci_restore_state(pdev);
206
-
pci_save_state(pdev);
207
207
res = adf_dev_up(accel_dev, false);
208
208
if (res && res != -EALREADY)
209
209
return PCI_ERS_RESULT_DISCONNECT;
-1
drivers/dma/ioat/init.c
-1
drivers/dma/ioat/init.c
+9
-11
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+9
-11
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
1678
1678
int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1679
1679
struct pci_bus *root;
1680
1680
struct resource *res;
1681
+
int max_size, r;
1681
1682
unsigned int i;
1682
1683
u16 cmd;
1683
-
int r;
1684
1684
1685
1685
if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
1686
1686
return 0;
···
1726
1726
return 0;
1727
1727
1728
1728
/* Limit the BAR size to what is available */
1729
-
rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1730
-
rbar_size);
1729
+
max_size = pci_rebar_get_max_size(adev->pdev, 0);
1730
+
if (max_size < 0)
1731
+
return 0;
1732
+
rbar_size = min(max_size, rbar_size);
1731
1733
1732
1734
/* Disable memory decoding while we change the BAR addresses and size */
1733
1735
pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1734
1736
pci_write_config_word(adev->pdev, PCI_COMMAND,
1735
1737
cmd & ~PCI_COMMAND_MEMORY);
1736
1738
1737
-
/* Free the VRAM and doorbell BAR, we most likely need to move both. */
1739
+
/* Tear down doorbell as resizing will release BARs */
1738
1740
amdgpu_doorbell_fini(adev);
1739
-
if (adev->asic_type >= CHIP_BONAIRE)
1740
-
pci_release_resource(adev->pdev, 2);
1741
1741
1742
-
pci_release_resource(adev->pdev, 0);
1743
-
1744
-
r = pci_resize_resource(adev->pdev, 0, rbar_size);
1742
+
r = pci_resize_resource(adev->pdev, 0, rbar_size,
1743
+
(adev->asic_type >= CHIP_BONAIRE) ? 1 << 5
1744
+
: 1 << 2);
1745
1745
if (r == -ENOSPC)
1746
1746
dev_info(adev->dev,
1747
1747
"Not enough PCI address space for a large BAR.");
1748
1748
else if (r && r != -ENOTSUPP)
1749
1749
dev_err(adev->dev, "Problem resizing BAR0 (%d).", r);
1750
-
1751
-
pci_assign_unassigned_bus_resources(adev->pdev->bus);
1752
1750
1753
1751
/* When the doorbell or fb BAR isn't available we have no chance of
1754
1752
* using the device.
+4
-20
drivers/gpu/drm/i915/gt/intel_region_lmem.c
+4
-20
drivers/gpu/drm/i915/gt/intel_region_lmem.c
···
20
20
#include "gt/intel_gt_regs.h"
21
21
22
22
#ifdef CONFIG_64BIT
23
-
static void _release_bars(struct pci_dev *pdev)
24
-
{
25
-
int resno;
26
-
27
-
for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
28
-
if (pci_resource_len(pdev, resno))
29
-
pci_release_resource(pdev, resno);
30
-
}
31
-
}
32
-
33
23
static void
34
24
_resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
35
25
{
···
27
37
int bar_size = pci_rebar_bytes_to_size(size);
28
38
int ret;
29
39
30
-
_release_bars(pdev);
31
-
32
-
ret = pci_resize_resource(pdev, resno, bar_size);
40
+
ret = pci_resize_resource(pdev, resno, bar_size, 0);
33
41
if (ret) {
34
42
drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
35
43
resno, 1 << bar_size, ERR_PTR(ret));
···
51
63
current_size = roundup_pow_of_two(pci_resource_len(pdev, GEN12_LMEM_BAR));
52
64
53
65
if (i915->params.lmem_bar_size) {
54
-
u32 bar_sizes;
55
-
56
-
rebar_size = i915->params.lmem_bar_size *
57
-
(resource_size_t)SZ_1M;
58
-
bar_sizes = pci_rebar_get_possible_sizes(pdev, GEN12_LMEM_BAR);
59
-
66
+
rebar_size = i915->params.lmem_bar_size * (resource_size_t)SZ_1M;
60
67
if (rebar_size == current_size)
61
68
return;
62
69
63
-
if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) ||
70
+
if (!pci_rebar_size_supported(pdev, GEN12_LMEM_BAR,
71
+
pci_rebar_bytes_to_size(rebar_size)) ||
64
72
rebar_size >= roundup_pow_of_two(lmem_size)) {
65
73
rebar_size = lmem_size;
66
74
+14
-44
drivers/gpu/drm/xe/xe_vram.c
+14
-44
drivers/gpu/drm/xe/xe_vram.c
···
25
25
#include "xe_vram.h"
26
26
#include "xe_vram_types.h"
27
27
28
-
#define BAR_SIZE_SHIFT 20
29
-
30
-
/*
31
-
* Release all the BARs that could influence/block LMEMBAR resizing, i.e.
32
-
* assigned IORESOURCE_MEM_64 BARs
33
-
*/
34
-
static void release_bars(struct pci_dev *pdev)
35
-
{
36
-
struct resource *res;
37
-
int i;
38
-
39
-
pci_dev_for_each_resource(pdev, res, i) {
40
-
/* Resource already un-assigned, do not reset it */
41
-
if (!res->parent)
42
-
continue;
43
-
44
-
/* No need to release unrelated BARs */
45
-
if (!(res->flags & IORESOURCE_MEM_64))
46
-
continue;
47
-
48
-
pci_release_resource(pdev, i);
49
-
}
50
-
}
51
-
52
28
static void resize_bar(struct xe_device *xe, int resno, resource_size_t size)
53
29
{
54
30
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
55
31
int bar_size = pci_rebar_bytes_to_size(size);
56
32
int ret;
57
33
58
-
release_bars(pdev);
59
-
60
-
ret = pci_resize_resource(pdev, resno, bar_size);
34
+
ret = pci_resize_resource(pdev, resno, bar_size, 0);
61
35
if (ret) {
62
36
drm_info(&xe->drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support in your BIOS\n",
63
37
resno, 1 << bar_size, ERR_PTR(ret));
···
53
79
resource_size_t current_size;
54
80
resource_size_t rebar_size;
55
81
struct resource *root_res;
56
-
u32 bar_size_mask;
82
+
int max_size, i;
57
83
u32 pci_cmd;
58
-
int i;
59
84
60
85
/* gather some relevant info */
61
86
current_size = pci_resource_len(pdev, LMEM_BAR);
62
-
bar_size_mask = pci_rebar_get_possible_sizes(pdev, LMEM_BAR);
63
-
64
-
if (!bar_size_mask)
65
-
return;
66
87
67
88
if (force_vram_bar_size < 0)
68
89
return;
69
90
70
91
/* set to a specific size? */
71
92
if (force_vram_bar_size) {
72
-
u32 bar_size_bit;
93
+
rebar_size = pci_rebar_bytes_to_size(force_vram_bar_size *
94
+
(resource_size_t)SZ_1M);
73
95
74
-
rebar_size = force_vram_bar_size * (resource_size_t)SZ_1M;
75
-
76
-
bar_size_bit = bar_size_mask & BIT(pci_rebar_bytes_to_size(rebar_size));
77
-
78
-
if (!bar_size_bit) {
96
+
if (!pci_rebar_size_supported(pdev, LMEM_BAR, rebar_size)) {
79
97
drm_info(&xe->drm,
80
-
"Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leaving default: %lluMiB\n",
81
-
(u64)rebar_size >> 20, bar_size_mask, (u64)current_size >> 20);
98
+
"Requested size: %lluMiB is not supported by rebar sizes: 0x%llx. Leaving default: %lluMiB\n",
99
+
(u64)pci_rebar_size_to_bytes(rebar_size) >> 20,
100
+
pci_rebar_get_possible_sizes(pdev, LMEM_BAR),
101
+
(u64)current_size >> 20);
82
102
return;
83
103
}
84
104
85
-
rebar_size = 1ULL << (__fls(bar_size_bit) + BAR_SIZE_SHIFT);
86
-
105
+
rebar_size = pci_rebar_size_to_bytes(rebar_size);
87
106
if (rebar_size == current_size)
88
107
return;
89
108
} else {
90
-
rebar_size = 1ULL << (__fls(bar_size_mask) + BAR_SIZE_SHIFT);
109
+
max_size = pci_rebar_get_max_size(pdev, LMEM_BAR);
110
+
if (max_size < 0)
111
+
return;
112
+
rebar_size = pci_rebar_size_to_bytes(max_size);
91
113
92
114
/* only resize if larger than current */
93
115
if (rebar_size <= current_size)
-2
drivers/net/ethernet/broadcom/bnx2.c
-2
drivers/net/ethernet/broadcom/bnx2.c
···
6444
6444
if (!(pcicmd & PCI_COMMAND_MEMORY)) {
6445
6445
/* in case PCI block has reset */
6446
6446
pci_restore_state(bp->pdev);
6447
-
pci_save_state(bp->pdev);
6448
6447
}
6449
6448
rc = bnx2_init_nic(bp, 1);
6450
6449
if (rc) {
···
8717
8718
} else {
8718
8719
pci_set_master(pdev);
8719
8720
pci_restore_state(pdev);
8720
-
pci_save_state(pdev);
8721
8721
8722
8722
if (netif_running(dev))
8723
8723
err = bnx2_init_nic(bp, 1);
-1
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
-1
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
-1
drivers/net/ethernet/broadcom/tg3.c
-1
drivers/net/ethernet/broadcom/tg3.c
-1
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
-1
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
-2
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
-2
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
···
5458
5458
5459
5459
if (!adap) {
5460
5460
pci_restore_state(pdev);
5461
-
pci_save_state(pdev);
5462
5461
return PCI_ERS_RESULT_RECOVERED;
5463
5462
}
5464
5463
···
5472
5473
5473
5474
pci_set_master(pdev);
5474
5475
pci_restore_state(pdev);
5475
-
pci_save_state(pdev);
5476
5476
5477
5477
if (t4_wait_dev_ready(adap->regs) < 0)
5478
5478
return PCI_ERS_RESULT_DISCONNECT;
-1
drivers/net/ethernet/hisilicon/hibmcge/hbg_err.c
-1
drivers/net/ethernet/hisilicon/hibmcge/hbg_err.c
-1
drivers/net/ethernet/intel/e1000e/netdev.c
-1
drivers/net/ethernet/intel/e1000e/netdev.c
-6
drivers/net/ethernet/intel/fm10k/fm10k_pci.c
-6
drivers/net/ethernet/intel/fm10k/fm10k_pci.c
···
2423
2423
} else {
2424
2424
pci_set_master(pdev);
2425
2425
pci_restore_state(pdev);
2426
-
2427
-
/* After second error pci->state_saved is false, this
2428
-
* resets it so EEH doesn't break.
2429
-
*/
2430
-
pci_save_state(pdev);
2431
-
2432
2426
pci_wake_from_d3(pdev, false);
2433
2427
2434
2428
result = PCI_ERS_RESULT_RECOVERED;
-1
drivers/net/ethernet/intel/i40e/i40e_main.c
-1
drivers/net/ethernet/intel/i40e/i40e_main.c
-2
drivers/net/ethernet/intel/ice/ice_main.c
-2
drivers/net/ethernet/intel/ice/ice_main.c
···
5653
5653
5654
5654
pci_set_power_state(pdev, PCI_D0);
5655
5655
pci_restore_state(pdev);
5656
-
pci_save_state(pdev);
5657
5656
5658
5657
if (!pci_device_is_present(pdev))
5659
5658
return -ENODEV;
···
5752
5753
} else {
5753
5754
pci_set_master(pdev);
5754
5755
pci_restore_state(pdev);
5755
-
pci_save_state(pdev);
5756
5756
pci_wake_from_d3(pdev, false);
5757
5757
5758
5758
/* Check for life */
-2
drivers/net/ethernet/intel/igb/igb_main.c
-2
drivers/net/ethernet/intel/igb/igb_main.c
···
9599
9599
9600
9600
pci_set_power_state(pdev, PCI_D0);
9601
9601
pci_restore_state(pdev);
9602
-
pci_save_state(pdev);
9603
9602
9604
9603
if (!pci_device_is_present(pdev))
9605
9604
return -ENODEV;
···
9753
9754
} else {
9754
9755
pci_set_master(pdev);
9755
9756
pci_restore_state(pdev);
9756
-
pci_save_state(pdev);
9757
9757
9758
9758
pci_enable_wake(pdev, PCI_D3hot, 0);
9759
9759
pci_enable_wake(pdev, PCI_D3cold, 0);
-2
drivers/net/ethernet/intel/igc/igc_main.c
-2
drivers/net/ethernet/intel/igc/igc_main.c
···
7530
7530
7531
7531
pci_set_power_state(pdev, PCI_D0);
7532
7532
pci_restore_state(pdev);
7533
-
pci_save_state(pdev);
7534
7533
7535
7534
if (!pci_device_is_present(pdev))
7536
7535
return -ENODEV;
···
7666
7667
} else {
7667
7668
pci_set_master(pdev);
7668
7669
pci_restore_state(pdev);
7669
-
pci_save_state(pdev);
7670
7670
7671
7671
pci_enable_wake(pdev, PCI_D3hot, 0);
7672
7672
pci_enable_wake(pdev, PCI_D3cold, 0);
-1
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
-1
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
-1
drivers/net/ethernet/mellanox/mlx4/main.c
-1
drivers/net/ethernet/mellanox/mlx4/main.c
-1
drivers/net/ethernet/mellanox/mlx5/core/main.c
-1
drivers/net/ethernet/mellanox/mlx5/core/main.c
-1
drivers/net/ethernet/meta/fbnic/fbnic_pci.c
-1
drivers/net/ethernet/meta/fbnic/fbnic_pci.c
-1
drivers/net/ethernet/microchip/lan743x_main.c
-1
drivers/net/ethernet/microchip/lan743x_main.c
-4
drivers/net/ethernet/myricom/myri10ge/myri10ge.c
-4
drivers/net/ethernet/myricom/myri10ge/myri10ge.c
···
3416
3416
* nic was resumed from power saving mode.
3417
3417
*/
3418
3418
pci_restore_state(mgp->pdev);
3419
-
3420
-
/* save state again for accounting reasons */
3421
-
pci_save_state(mgp->pdev);
3422
-
3423
3419
} else {
3424
3420
/* if we get back -1's from our slot, perhaps somebody
3425
3421
* powered off our card. Don't try to reset it in
-1
drivers/net/ethernet/neterion/s2io.c
-1
drivers/net/ethernet/neterion/s2io.c
+1
-1
drivers/pci/Makefile
+1
-1
drivers/pci/Makefile
+3
drivers/pci/bus.c
+3
drivers/pci/bus.c
···
357
357
pci_proc_attach_device(dev);
358
358
pci_bridge_d3_update(dev);
359
359
360
+
/* Save config space for error recoverability */
361
+
pci_save_state(dev);
362
+
360
363
/*
361
364
* If the PCI device is associated with a pwrctrl device with a
362
365
* power supply, create a device link between the PCI device and
+13
-5
drivers/pci/controller/Kconfig
+13
-5
drivers/pci/controller/Kconfig
···
146
146
147
147
config PCI_IXP4XX
148
148
bool "Intel IXP4xx PCI controller"
149
-
depends on ARM && OF
149
+
depends on OF
150
150
depends on ARCH_IXP4XX || COMPILE_TEST
151
151
default ARCH_IXP4XX
152
152
help
···
259
259
260
260
config PCI_RCAR_GEN2
261
261
bool "Renesas R-Car Gen2 Internal PCI controller"
262
-
depends on ARCH_RENESAS || COMPILE_TEST
263
-
depends on ARM
262
+
depends on (ARCH_RENESAS && ARM) || COMPILE_TEST
264
263
help
265
264
Say Y here if you want internal PCI support on R-Car Gen2 SoC.
266
-
There are 3 internal PCI controllers available with a single
267
-
built-in EHCI/OHCI host controller present on each one.
265
+
Each internal PCI controller contains a single built-in EHCI/OHCI
266
+
host controller.
267
+
268
+
config PCIE_RENESAS_RZG3S_HOST
269
+
bool "Renesas RZ/G3S PCIe host controller"
270
+
depends on ARCH_RENESAS || COMPILE_TEST
271
+
select MFD_SYSCON
272
+
select IRQ_MSI_LIB
273
+
help
274
+
Say Y here if you want PCIe host controller support on Renesas RZ/G3S
275
+
SoC.
268
276
269
277
config PCIE_ROCKCHIP
270
278
bool
+1
drivers/pci/controller/Makefile
+1
drivers/pci/controller/Makefile
···
10
10
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
11
11
obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o
12
12
obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o
13
+
obj-$(CONFIG_PCIE_RENESAS_RZG3S_HOST) += pcie-rzg3s-host.o
13
14
obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o
14
15
obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
15
16
obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
+18
-3
drivers/pci/controller/cadence/Kconfig
+18
-3
drivers/pci/controller/cadence/Kconfig
···
19
19
select PCIE_CADENCE
20
20
21
21
config PCIE_CADENCE_PLAT
22
-
bool
22
+
tristate
23
23
24
24
config PCIE_CADENCE_PLAT_HOST
25
-
bool "Cadence platform PCIe controller (host mode)"
25
+
tristate "Cadence platform PCIe controller (host mode)"
26
26
depends on OF
27
27
select PCIE_CADENCE_HOST
28
28
select PCIE_CADENCE_PLAT
···
32
32
vendors SoCs.
33
33
34
34
config PCIE_CADENCE_PLAT_EP
35
-
bool "Cadence platform PCIe controller (endpoint mode)"
35
+
tristate "Cadence platform PCIe controller (endpoint mode)"
36
36
depends on OF
37
37
depends on PCI_ENDPOINT
38
38
select PCIE_CADENCE_EP
···
41
41
Say Y here if you want to support the Cadence PCIe platform controller in
42
42
endpoint mode. This PCIe controller may be embedded into many
43
43
different vendors SoCs.
44
+
45
+
config PCI_SKY1_HOST
46
+
tristate "CIX SKY1 PCIe controller (host mode)"
47
+
depends on OF && (ARCH_CIX || COMPILE_TEST)
48
+
select PCIE_CADENCE_HOST
49
+
select PCI_ECAM
50
+
help
51
+
Say Y here if you want to support the CIX SKY1 PCIe platform
52
+
controller in host mode. CIX SKY1 PCIe controller uses Cadence
53
+
HPA (High Performance Architecture IP [Second generation of
54
+
Cadence PCIe IP])
55
+
56
+
This driver requires Cadence PCIe core infrastructure
57
+
(PCIE_CADENCE_HOST) and hardware platform adaptation layer
58
+
to function.
44
59
45
60
config PCIE_SG2042_HOST
46
61
tristate "Sophgo SG2042 PCIe controller (host mode)"
+8
-3
drivers/pci/controller/cadence/Makefile
+8
-3
drivers/pci/controller/cadence/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
-
obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o
3
-
obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
4
-
obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
2
+
pcie-cadence-mod-y := pcie-cadence-hpa.o pcie-cadence.o
3
+
pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o pcie-cadence-host-hpa.o
4
+
pcie-cadence-ep-mod-y := pcie-cadence-ep.o
5
+
6
+
obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o
7
+
obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o
8
+
obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o
5
9
obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
6
10
obj-$(CONFIG_PCI_J721E) += pci-j721e.o
7
11
obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o
12
+
obj-$(CONFIG_PCI_SKY1_HOST) += pci-sky1.o
+11
-22
drivers/pci/controller/cadence/pci-j721e.c
+11
-22
drivers/pci/controller/cadence/pci-j721e.c
···
477
477
struct j721e_pcie *pcie;
478
478
struct cdns_pcie_rc *rc = NULL;
479
479
struct cdns_pcie_ep *ep = NULL;
480
-
struct gpio_desc *gpiod;
481
480
void __iomem *base;
482
-
struct clk *clk;
483
481
u32 num_lanes;
484
482
u32 mode;
485
483
int ret;
···
588
590
589
591
switch (mode) {
590
592
case PCI_MODE_RC:
591
-
gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
592
-
if (IS_ERR(gpiod)) {
593
-
ret = dev_err_probe(dev, PTR_ERR(gpiod), "Failed to get reset GPIO\n");
593
+
pcie->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
594
+
if (IS_ERR(pcie->reset_gpio)) {
595
+
ret = dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
596
+
"Failed to get reset GPIO\n");
594
597
goto err_get_sync;
595
598
}
596
-
pcie->reset_gpio = gpiod;
597
599
598
600
ret = cdns_pcie_init_phy(dev, cdns_pcie);
599
601
if (ret) {
···
601
603
goto err_get_sync;
602
604
}
603
605
604
-
clk = devm_clk_get_optional(dev, "pcie_refclk");
605
-
if (IS_ERR(clk)) {
606
-
ret = dev_err_probe(dev, PTR_ERR(clk), "failed to get pcie_refclk\n");
606
+
pcie->refclk = devm_clk_get_optional_enabled(dev, "pcie_refclk");
607
+
if (IS_ERR(pcie->refclk)) {
608
+
ret = dev_err_probe(dev, PTR_ERR(pcie->refclk),
609
+
"failed to enable pcie_refclk\n");
607
610
goto err_pcie_setup;
608
611
}
609
-
610
-
ret = clk_prepare_enable(clk);
611
-
if (ret) {
612
-
dev_err_probe(dev, ret, "failed to enable pcie_refclk\n");
613
-
goto err_pcie_setup;
614
-
}
615
-
pcie->refclk = clk;
616
612
617
613
/*
618
614
* Section 2.2 of the PCI Express Card Electromechanical
···
615
623
* This shall ensure that the power and the reference clock
616
624
* are stable.
617
625
*/
618
-
if (gpiod) {
626
+
if (pcie->reset_gpio) {
619
627
msleep(PCIE_T_PVPERL_MS);
620
-
gpiod_set_value_cansleep(gpiod, 1);
628
+
gpiod_set_value_cansleep(pcie->reset_gpio, 1);
621
629
}
622
630
623
631
ret = cdns_pcie_host_setup(rc);
624
-
if (ret < 0) {
625
-
clk_disable_unprepare(pcie->refclk);
632
+
if (ret < 0)
626
633
goto err_pcie_setup;
627
-
}
628
634
629
635
break;
630
636
case PCI_MODE_EP:
···
669
679
670
680
gpiod_set_value_cansleep(pcie->reset_gpio, 0);
671
681
672
-
clk_disable_unprepare(pcie->refclk);
673
682
cdns_pcie_disable_phy(cdns_pcie);
674
683
j721e_pcie_disable_link_irq(pcie);
675
684
pm_runtime_put(dev);
+238
drivers/pci/controller/cadence/pci-sky1.c
+238
drivers/pci/controller/cadence/pci-sky1.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* PCIe controller driver for CIX's sky1 SoCs
4
+
*
5
+
* Copyright 2025 Cix Technology Group Co., Ltd.
6
+
* Author: Hans Zhang <hans.zhang@cixtech.com>
7
+
*/
8
+
9
+
#include <linux/kernel.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/pci.h>
14
+
#include <linux/pci-ecam.h>
15
+
#include <linux/pci_ids.h>
16
+
17
+
#include "pcie-cadence.h"
18
+
#include "pcie-cadence-host-common.h"
19
+
20
+
#define PCI_VENDOR_ID_CIX 0x1f6c
21
+
#define PCI_DEVICE_ID_CIX_SKY1 0x0001
22
+
23
+
#define STRAP_REG(n) ((n) * 0x04)
24
+
#define STATUS_REG(n) ((n) * 0x04)
25
+
#define LINK_TRAINING_ENABLE BIT(0)
26
+
#define LINK_COMPLETE BIT(0)
27
+
28
+
#define SKY1_IP_REG_BANK 0x1000
29
+
#define SKY1_IP_CFG_CTRL_REG_BANK 0x4c00
30
+
#define SKY1_IP_AXI_MASTER_COMMON 0xf000
31
+
#define SKY1_AXI_SLAVE 0x9000
32
+
#define SKY1_AXI_MASTER 0xb000
33
+
#define SKY1_AXI_HLS_REGISTERS 0xc000
34
+
#define SKY1_AXI_RAS_REGISTERS 0xe000
35
+
#define SKY1_DTI_REGISTERS 0xd000
36
+
37
+
#define IP_REG_I_DBG_STS_0 0x420
38
+
39
+
struct sky1_pcie {
40
+
struct cdns_pcie *cdns_pcie;
41
+
struct cdns_pcie_rc *cdns_pcie_rc;
42
+
43
+
struct resource *cfg_res;
44
+
struct resource *msg_res;
45
+
struct pci_config_window *cfg;
46
+
void __iomem *strap_base;
47
+
void __iomem *status_base;
48
+
void __iomem *reg_base;
49
+
void __iomem *cfg_base;
50
+
void __iomem *msg_base;
51
+
};
52
+
53
+
static int sky1_pcie_resource_get(struct platform_device *pdev,
54
+
struct sky1_pcie *pcie)
55
+
{
56
+
struct device *dev = &pdev->dev;
57
+
struct resource *res;
58
+
void __iomem *base;
59
+
60
+
base = devm_platform_ioremap_resource_byname(pdev, "reg");
61
+
if (IS_ERR(base))
62
+
return dev_err_probe(dev, PTR_ERR(base),
63
+
"unable to find \"reg\" registers\n");
64
+
pcie->reg_base = base;
65
+
66
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
67
+
if (!res)
68
+
return dev_err_probe(dev, -ENODEV, "unable to get \"cfg\" resource\n");
69
+
pcie->cfg_res = res;
70
+
71
+
base = devm_platform_ioremap_resource_byname(pdev, "rcsu_strap");
72
+
if (IS_ERR(base))
73
+
return dev_err_probe(dev, PTR_ERR(base),
74
+
"unable to find \"rcsu_strap\" registers\n");
75
+
pcie->strap_base = base;
76
+
77
+
base = devm_platform_ioremap_resource_byname(pdev, "rcsu_status");
78
+
if (IS_ERR(base))
79
+
return dev_err_probe(dev, PTR_ERR(base),
80
+
"unable to find \"rcsu_status\" registers\n");
81
+
pcie->status_base = base;
82
+
83
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "msg");
84
+
if (!res)
85
+
return dev_err_probe(dev, -ENODEV, "unable to get \"msg\" resource\n");
86
+
pcie->msg_res = res;
87
+
pcie->msg_base = devm_ioremap_resource(dev, res);
88
+
if (IS_ERR(pcie->msg_base)) {
89
+
return dev_err_probe(dev, PTR_ERR(pcie->msg_base),
90
+
"unable to ioremap msg resource\n");
91
+
}
92
+
93
+
return 0;
94
+
}
95
+
96
+
static int sky1_pcie_start_link(struct cdns_pcie *cdns_pcie)
97
+
{
98
+
struct sky1_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
99
+
u32 val;
100
+
101
+
val = readl(pcie->strap_base + STRAP_REG(1));
102
+
val |= LINK_TRAINING_ENABLE;
103
+
writel(val, pcie->strap_base + STRAP_REG(1));
104
+
105
+
return 0;
106
+
}
107
+
108
+
static void sky1_pcie_stop_link(struct cdns_pcie *cdns_pcie)
109
+
{
110
+
struct sky1_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
111
+
u32 val;
112
+
113
+
val = readl(pcie->strap_base + STRAP_REG(1));
114
+
val &= ~LINK_TRAINING_ENABLE;
115
+
writel(val, pcie->strap_base + STRAP_REG(1));
116
+
}
117
+
118
+
static bool sky1_pcie_link_up(struct cdns_pcie *cdns_pcie)
119
+
{
120
+
u32 val;
121
+
122
+
val = cdns_pcie_hpa_readl(cdns_pcie, REG_BANK_IP_REG,
123
+
IP_REG_I_DBG_STS_0);
124
+
return val & LINK_COMPLETE;
125
+
}
126
+
127
+
static const struct cdns_pcie_ops sky1_pcie_ops = {
128
+
.start_link = sky1_pcie_start_link,
129
+
.stop_link = sky1_pcie_stop_link,
130
+
.link_up = sky1_pcie_link_up,
131
+
};
132
+
133
+
static int sky1_pcie_probe(struct platform_device *pdev)
134
+
{
135
+
struct cdns_plat_pcie_of_data *reg_off;
136
+
struct device *dev = &pdev->dev;
137
+
struct pci_host_bridge *bridge;
138
+
struct cdns_pcie *cdns_pcie;
139
+
struct resource_entry *bus;
140
+
struct cdns_pcie_rc *rc;
141
+
struct sky1_pcie *pcie;
142
+
int ret;
143
+
144
+
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
145
+
if (!pcie)
146
+
return -ENOMEM;
147
+
148
+
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
149
+
if (!bridge)
150
+
return -ENOMEM;
151
+
152
+
ret = sky1_pcie_resource_get(pdev, pcie);
153
+
if (ret < 0)
154
+
return ret;
155
+
156
+
bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
157
+
if (!bus)
158
+
return -ENODEV;
159
+
160
+
pcie->cfg = pci_ecam_create(dev, pcie->cfg_res, bus->res,
161
+
&pci_generic_ecam_ops);
162
+
if (IS_ERR(pcie->cfg))
163
+
return PTR_ERR(pcie->cfg);
164
+
165
+
bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops;
166
+
rc = pci_host_bridge_priv(bridge);
167
+
rc->ecam_supported = 1;
168
+
rc->cfg_base = pcie->cfg->win;
169
+
rc->cfg_res = &pcie->cfg->res;
170
+
171
+
cdns_pcie = &rc->pcie;
172
+
cdns_pcie->dev = dev;
173
+
cdns_pcie->ops = &sky1_pcie_ops;
174
+
cdns_pcie->reg_base = pcie->reg_base;
175
+
cdns_pcie->msg_res = pcie->msg_res;
176
+
cdns_pcie->is_rc = 1;
177
+
178
+
reg_off = devm_kzalloc(dev, sizeof(*reg_off), GFP_KERNEL);
179
+
if (!reg_off)
180
+
return -ENOMEM;
181
+
182
+
reg_off->ip_reg_bank_offset = SKY1_IP_REG_BANK;
183
+
reg_off->ip_cfg_ctrl_reg_offset = SKY1_IP_CFG_CTRL_REG_BANK;
184
+
reg_off->axi_mstr_common_offset = SKY1_IP_AXI_MASTER_COMMON;
185
+
reg_off->axi_slave_offset = SKY1_AXI_SLAVE;
186
+
reg_off->axi_master_offset = SKY1_AXI_MASTER;
187
+
reg_off->axi_hls_offset = SKY1_AXI_HLS_REGISTERS;
188
+
reg_off->axi_ras_offset = SKY1_AXI_RAS_REGISTERS;
189
+
reg_off->axi_dti_offset = SKY1_DTI_REGISTERS;
190
+
cdns_pcie->cdns_pcie_reg_offsets = reg_off;
191
+
192
+
pcie->cdns_pcie = cdns_pcie;
193
+
pcie->cdns_pcie_rc = rc;
194
+
pcie->cfg_base = rc->cfg_base;
195
+
bridge->sysdata = pcie->cfg;
196
+
197
+
rc->vendor_id = PCI_VENDOR_ID_CIX;
198
+
rc->device_id = PCI_DEVICE_ID_CIX_SKY1;
199
+
rc->no_inbound_map = 1;
200
+
201
+
dev_set_drvdata(dev, pcie);
202
+
203
+
ret = cdns_pcie_hpa_host_setup(rc);
204
+
if (ret < 0) {
205
+
pci_ecam_free(pcie->cfg);
206
+
return ret;
207
+
}
208
+
209
+
return 0;
210
+
}
211
+
212
+
static const struct of_device_id of_sky1_pcie_match[] = {
213
+
{ .compatible = "cix,sky1-pcie-host", },
214
+
{},
215
+
};
216
+
MODULE_DEVICE_TABLE(of, of_sky1_pcie_match);
217
+
218
+
static void sky1_pcie_remove(struct platform_device *pdev)
219
+
{
220
+
struct sky1_pcie *pcie = platform_get_drvdata(pdev);
221
+
222
+
pci_ecam_free(pcie->cfg);
223
+
}
224
+
225
+
static struct platform_driver sky1_pcie_driver = {
226
+
.probe = sky1_pcie_probe,
227
+
.remove = sky1_pcie_remove,
228
+
.driver = {
229
+
.name = "sky1-pcie",
230
+
.of_match_table = of_sky1_pcie_match,
231
+
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
232
+
},
233
+
};
234
+
module_platform_driver(sky1_pcie_driver);
235
+
236
+
MODULE_LICENSE("GPL");
237
+
MODULE_DESCRIPTION("PCIe controller driver for CIX's sky1 SoCs");
238
+
MODULE_AUTHOR("Hans Zhang <hans.zhang@cixtech.com>");
+288
drivers/pci/controller/cadence/pcie-cadence-host-common.c
+288
drivers/pci/controller/cadence/pcie-cadence-host-common.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Cadence PCIe host controller library.
4
+
*
5
+
* Copyright (c) 2017 Cadence
6
+
* Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
7
+
*/
8
+
#include <linux/delay.h>
9
+
#include <linux/kernel.h>
10
+
#include <linux/list_sort.h>
11
+
#include <linux/of_address.h>
12
+
#include <linux/of_pci.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include "pcie-cadence.h"
16
+
#include "pcie-cadence-host-common.h"
17
+
18
+
#define LINK_RETRAIN_TIMEOUT HZ
19
+
20
+
u64 bar_max_size[] = {
21
+
[RP_BAR0] = _ULL(128 * SZ_2G),
22
+
[RP_BAR1] = SZ_2G,
23
+
[RP_NO_BAR] = _BITULL(63),
24
+
};
25
+
EXPORT_SYMBOL_GPL(bar_max_size);
26
+
27
+
int cdns_pcie_host_training_complete(struct cdns_pcie *pcie)
28
+
{
29
+
u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
30
+
unsigned long end_jiffies;
31
+
u16 lnk_stat;
32
+
33
+
/* Wait for link training to complete. Exit after timeout. */
34
+
end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
35
+
do {
36
+
lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
37
+
if (!(lnk_stat & PCI_EXP_LNKSTA_LT))
38
+
break;
39
+
usleep_range(0, 1000);
40
+
} while (time_before(jiffies, end_jiffies));
41
+
42
+
if (!(lnk_stat & PCI_EXP_LNKSTA_LT))
43
+
return 0;
44
+
45
+
return -ETIMEDOUT;
46
+
}
47
+
EXPORT_SYMBOL_GPL(cdns_pcie_host_training_complete);
48
+
49
+
int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie,
50
+
cdns_pcie_linkup_func pcie_link_up)
51
+
{
52
+
struct device *dev = pcie->dev;
53
+
int retries;
54
+
55
+
/* Check if the link is up or not */
56
+
for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
57
+
if (pcie_link_up(pcie)) {
58
+
dev_info(dev, "Link up\n");
59
+
return 0;
60
+
}
61
+
usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
62
+
}
63
+
64
+
return -ETIMEDOUT;
65
+
}
66
+
EXPORT_SYMBOL_GPL(cdns_pcie_host_wait_for_link);
67
+
68
+
int cdns_pcie_retrain(struct cdns_pcie *pcie,
69
+
cdns_pcie_linkup_func pcie_link_up)
70
+
{
71
+
u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
72
+
u16 lnk_stat, lnk_ctl;
73
+
int ret = 0;
74
+
75
+
/*
76
+
* Set retrain bit if current speed is 2.5 GB/s,
77
+
* but the PCIe root port support is > 2.5 GB/s.
78
+
*/
79
+
80
+
lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off +
81
+
PCI_EXP_LNKCAP));
82
+
if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
83
+
return ret;
84
+
85
+
lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
86
+
if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
87
+
lnk_ctl = cdns_pcie_rp_readw(pcie,
88
+
pcie_cap_off + PCI_EXP_LNKCTL);
89
+
lnk_ctl |= PCI_EXP_LNKCTL_RL;
90
+
cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
91
+
lnk_ctl);
92
+
93
+
ret = cdns_pcie_host_training_complete(pcie);
94
+
if (ret)
95
+
return ret;
96
+
97
+
ret = cdns_pcie_host_wait_for_link(pcie, pcie_link_up);
98
+
}
99
+
return ret;
100
+
}
101
+
EXPORT_SYMBOL_GPL(cdns_pcie_retrain);
102
+
103
+
int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc,
104
+
cdns_pcie_linkup_func pcie_link_up)
105
+
{
106
+
struct cdns_pcie *pcie = &rc->pcie;
107
+
int ret;
108
+
109
+
ret = cdns_pcie_host_wait_for_link(pcie, pcie_link_up);
110
+
111
+
/*
112
+
* Retrain link for Gen2 training defect
113
+
* if quirk flag is set.
114
+
*/
115
+
if (!ret && rc->quirk_retrain_flag)
116
+
ret = cdns_pcie_retrain(pcie, pcie_link_up);
117
+
118
+
return ret;
119
+
}
120
+
EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link);
121
+
122
+
enum cdns_pcie_rp_bar
123
+
cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size)
124
+
{
125
+
enum cdns_pcie_rp_bar bar, sel_bar;
126
+
127
+
sel_bar = RP_BAR_UNDEFINED;
128
+
for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) {
129
+
if (!rc->avail_ib_bar[bar])
130
+
continue;
131
+
132
+
if (size <= bar_max_size[bar]) {
133
+
if (sel_bar == RP_BAR_UNDEFINED) {
134
+
sel_bar = bar;
135
+
continue;
136
+
}
137
+
138
+
if (bar_max_size[bar] < bar_max_size[sel_bar])
139
+
sel_bar = bar;
140
+
}
141
+
}
142
+
143
+
return sel_bar;
144
+
}
145
+
EXPORT_SYMBOL_GPL(cdns_pcie_host_find_min_bar);
146
+
147
+
enum cdns_pcie_rp_bar
148
+
cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size)
149
+
{
150
+
enum cdns_pcie_rp_bar bar, sel_bar;
151
+
152
+
sel_bar = RP_BAR_UNDEFINED;
153
+
for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) {
154
+
if (!rc->avail_ib_bar[bar])
155
+
continue;
156
+
157
+
if (size >= bar_max_size[bar]) {
158
+
if (sel_bar == RP_BAR_UNDEFINED) {
159
+
sel_bar = bar;
160
+
continue;
161
+
}
162
+
163
+
if (bar_max_size[bar] > bar_max_size[sel_bar])
164
+
sel_bar = bar;
165
+
}
166
+
}
167
+
168
+
return sel_bar;
169
+
}
170
+
EXPORT_SYMBOL_GPL(cdns_pcie_host_find_max_bar);
171
+
172
+
int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a,
173
+
const struct list_head *b)
174
+
{
175
+
struct resource_entry *entry1, *entry2;
176
+
177
+
entry1 = container_of(a, struct resource_entry, node);
178
+
entry2 = container_of(b, struct resource_entry, node);
179
+
180
+
return resource_size(entry2->res) - resource_size(entry1->res);
181
+
}
182
+
EXPORT_SYMBOL_GPL(cdns_pcie_host_dma_ranges_cmp);
183
+
184
+
int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc,
185
+
struct resource_entry *entry,
186
+
cdns_pcie_host_bar_ib_cfg pci_host_ib_config)
187
+
{
188
+
struct cdns_pcie *pcie = &rc->pcie;
189
+
struct device *dev = pcie->dev;
190
+
u64 cpu_addr, size, winsize;
191
+
enum cdns_pcie_rp_bar bar;
192
+
unsigned long flags;
193
+
int ret;
194
+
195
+
cpu_addr = entry->res->start;
196
+
flags = entry->res->flags;
197
+
size = resource_size(entry->res);
198
+
199
+
while (size > 0) {
200
+
/*
201
+
* Try to find a minimum BAR whose size is greater than
202
+
* or equal to the remaining resource_entry size. This will
203
+
* fail if the size of each of the available BARs is less than
204
+
* the remaining resource_entry size.
205
+
*
206
+
* If a minimum BAR is found, IB ATU will be configured and
207
+
* exited.
208
+
*/
209
+
bar = cdns_pcie_host_find_min_bar(rc, size);
210
+
if (bar != RP_BAR_UNDEFINED) {
211
+
ret = pci_host_ib_config(rc, bar, cpu_addr, size, flags);
212
+
if (ret)
213
+
dev_err(dev, "IB BAR: %d config failed\n", bar);
214
+
return ret;
215
+
}
216
+
217
+
/*
218
+
* If the control reaches here, it would mean the remaining
219
+
* resource_entry size cannot be fitted in a single BAR. So we
220
+
* find a maximum BAR whose size is less than or equal to the
221
+
* remaining resource_entry size and split the resource entry
222
+
* so that part of resource entry is fitted inside the maximum
223
+
* BAR. The remaining size would be fitted during the next
224
+
* iteration of the loop.
225
+
*
226
+
* If a maximum BAR is not found, there is no way we can fit
227
+
* this resource_entry, so we error out.
228
+
*/
229
+
bar = cdns_pcie_host_find_max_bar(rc, size);
230
+
if (bar == RP_BAR_UNDEFINED) {
231
+
dev_err(dev, "No free BAR to map cpu_addr %llx\n",
232
+
cpu_addr);
233
+
return -EINVAL;
234
+
}
235
+
236
+
winsize = bar_max_size[bar];
237
+
ret = pci_host_ib_config(rc, bar, cpu_addr, winsize, flags);
238
+
if (ret) {
239
+
dev_err(dev, "IB BAR: %d config failed\n", bar);
240
+
return ret;
241
+
}
242
+
243
+
size -= winsize;
244
+
cpu_addr += winsize;
245
+
}
246
+
247
+
return 0;
248
+
}
249
+
250
+
int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc,
251
+
cdns_pcie_host_bar_ib_cfg pci_host_ib_config)
252
+
{
253
+
struct cdns_pcie *pcie = &rc->pcie;
254
+
struct device *dev = pcie->dev;
255
+
struct device_node *np = dev->of_node;
256
+
struct pci_host_bridge *bridge;
257
+
struct resource_entry *entry;
258
+
u32 no_bar_nbits = 32;
259
+
int err;
260
+
261
+
bridge = pci_host_bridge_from_priv(rc);
262
+
if (!bridge)
263
+
return -ENOMEM;
264
+
265
+
if (list_empty(&bridge->dma_ranges)) {
266
+
of_property_read_u32(np, "cdns,no-bar-match-nbits",
267
+
&no_bar_nbits);
268
+
err = pci_host_ib_config(rc, RP_NO_BAR, 0x0, (u64)1 << no_bar_nbits, 0);
269
+
if (err)
270
+
dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR);
271
+
return err;
272
+
}
273
+
274
+
list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp);
275
+
276
+
resource_list_for_each_entry(entry, &bridge->dma_ranges) {
277
+
err = cdns_pcie_host_bar_config(rc, entry, pci_host_ib_config);
278
+
if (err) {
279
+
dev_err(dev, "Fail to configure IB using dma-ranges\n");
280
+
return err;
281
+
}
282
+
}
283
+
284
+
return 0;
285
+
}
286
+
287
+
MODULE_LICENSE("GPL");
288
+
MODULE_DESCRIPTION("Cadence PCIe host controller driver");
+46
drivers/pci/controller/cadence/pcie-cadence-host-common.h
+46
drivers/pci/controller/cadence/pcie-cadence-host-common.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Cadence PCIe Host controller driver.
4
+
*
5
+
* Copyright (c) 2017 Cadence
6
+
* Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
7
+
*/
8
+
#ifndef _PCIE_CADENCE_HOST_COMMON_H
9
+
#define _PCIE_CADENCE_HOST_COMMON_H
10
+
11
+
#include <linux/kernel.h>
12
+
#include <linux/pci.h>
13
+
14
+
extern u64 bar_max_size[];
15
+
16
+
typedef int (*cdns_pcie_host_bar_ib_cfg)(struct cdns_pcie_rc *,
17
+
enum cdns_pcie_rp_bar,
18
+
u64,
19
+
u64,
20
+
unsigned long);
21
+
typedef bool (*cdns_pcie_linkup_func)(struct cdns_pcie *);
22
+
23
+
int cdns_pcie_host_training_complete(struct cdns_pcie *pcie);
24
+
int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie,
25
+
cdns_pcie_linkup_func pcie_link_up);
26
+
int cdns_pcie_retrain(struct cdns_pcie *pcie, cdns_pcie_linkup_func pcie_linkup_func);
27
+
int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc,
28
+
cdns_pcie_linkup_func pcie_link_up);
29
+
enum cdns_pcie_rp_bar
30
+
cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size);
31
+
enum cdns_pcie_rp_bar
32
+
cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size);
33
+
int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a,
34
+
const struct list_head *b);
35
+
int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc,
36
+
enum cdns_pcie_rp_bar bar,
37
+
u64 cpu_addr,
38
+
u64 size,
39
+
unsigned long flags);
40
+
int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc,
41
+
struct resource_entry *entry,
42
+
cdns_pcie_host_bar_ib_cfg pci_host_ib_config);
43
+
int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc,
44
+
cdns_pcie_host_bar_ib_cfg pci_host_ib_config);
45
+
46
+
#endif /* _PCIE_CADENCE_HOST_COMMON_H */
+368
drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
+368
drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Cadence PCIe host controller driver.
4
+
*
5
+
* Copyright (c) 2024, Cadence Design Systems
6
+
* Author: Manikandan K Pillai <mpillai@cadence.com>
7
+
*/
8
+
#include <linux/delay.h>
9
+
#include <linux/kernel.h>
10
+
#include <linux/list_sort.h>
11
+
#include <linux/of_address.h>
12
+
#include <linux/of_pci.h>
13
+
#include <linux/of_irq.h>
14
+
#include <linux/platform_device.h>
15
+
16
+
#include "pcie-cadence.h"
17
+
#include "pcie-cadence-host-common.h"
18
+
19
+
static u8 bar_aperture_mask[] = {
20
+
[RP_BAR0] = 0x3F,
21
+
[RP_BAR1] = 0x3F,
22
+
};
23
+
24
+
void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn,
25
+
int where)
26
+
{
27
+
struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
28
+
struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
29
+
struct cdns_pcie *pcie = &rc->pcie;
30
+
unsigned int busn = bus->number;
31
+
u32 addr0, desc0, desc1, ctrl0;
32
+
u32 regval;
33
+
34
+
if (pci_is_root_bus(bus)) {
35
+
/*
36
+
* Only the root port (devfn == 0) is connected to this bus.
37
+
* All other PCI devices are behind some bridge hence on another
38
+
* bus.
39
+
*/
40
+
if (devfn)
41
+
return NULL;
42
+
43
+
return pcie->reg_base + (where & 0xfff);
44
+
}
45
+
46
+
/* Clear AXI link-down status */
47
+
regval = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN);
48
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN,
49
+
(regval & ~GENMASK(0, 0)));
50
+
51
+
/* Update Output registers for AXI region 0 */
52
+
addr0 = CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
53
+
CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) |
54
+
CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(busn);
55
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
56
+
CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), addr0);
57
+
58
+
desc1 = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE,
59
+
CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0));
60
+
desc1 &= ~CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK;
61
+
desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0);
62
+
ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS |
63
+
CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN;
64
+
65
+
if (busn == bridge->busnr + 1)
66
+
desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0;
67
+
else
68
+
desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1;
69
+
70
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
71
+
CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), desc0);
72
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
73
+
CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1);
74
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
75
+
CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), ctrl0);
76
+
77
+
return rc->cfg_base + (where & 0xfff);
78
+
}
79
+
80
+
static struct pci_ops cdns_pcie_hpa_host_ops = {
81
+
.map_bus = cdns_pci_hpa_map_bus,
82
+
.read = pci_generic_config_read,
83
+
.write = pci_generic_config_write,
84
+
};
85
+
86
+
static void cdns_pcie_hpa_host_enable_ptm_response(struct cdns_pcie *pcie)
87
+
{
88
+
u32 val;
89
+
90
+
val = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL);
91
+
cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL,
92
+
val | CDNS_PCIE_HPA_LM_PTM_CTRL_PTMRSEN);
93
+
}
94
+
95
+
static int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc,
96
+
enum cdns_pcie_rp_bar bar,
97
+
u64 cpu_addr, u64 size,
98
+
unsigned long flags)
99
+
{
100
+
struct cdns_pcie *pcie = &rc->pcie;
101
+
u32 addr0, addr1, aperture, value;
102
+
103
+
if (!rc->avail_ib_bar[bar])
104
+
return -ENODEV;
105
+
106
+
rc->avail_ib_bar[bar] = false;
107
+
108
+
aperture = ilog2(size);
109
+
if (bar == RP_NO_BAR) {
110
+
addr0 = CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(aperture) |
111
+
(lower_32_bits(cpu_addr) & GENMASK(31, 8));
112
+
addr1 = upper_32_bits(cpu_addr);
113
+
} else {
114
+
addr0 = lower_32_bits(cpu_addr);
115
+
addr1 = upper_32_bits(cpu_addr);
116
+
}
117
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER,
118
+
CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar), addr0);
119
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER,
120
+
CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar), addr1);
121
+
122
+
if (bar == RP_NO_BAR)
123
+
bar = (enum cdns_pcie_rp_bar)BAR_0;
124
+
125
+
value = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_BAR_CFG);
126
+
value &= ~(HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) |
127
+
HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) |
128
+
HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) |
129
+
HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) |
130
+
HPA_LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 7));
131
+
if (size + cpu_addr >= SZ_4G) {
132
+
value |= HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar);
133
+
if ((flags & IORESOURCE_PREFETCH))
134
+
value |= HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar);
135
+
} else {
136
+
value |= HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar);
137
+
if ((flags & IORESOURCE_PREFETCH))
138
+
value |= HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar);
139
+
}
140
+
141
+
value |= HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture);
142
+
cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_BAR_CFG, value);
143
+
144
+
return 0;
145
+
}
146
+
147
+
static int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc)
148
+
{
149
+
struct cdns_pcie *pcie = &rc->pcie;
150
+
u32 value, ctrl;
151
+
152
+
/*
153
+
* Set the root port BAR configuration register:
154
+
* - disable both BAR0 and BAR1
155
+
* - enable Prefetchable Memory Base and Limit registers in type 1
156
+
* config space (64 bits)
157
+
* - enable IO Base and Limit registers in type 1 config
158
+
* space (32 bits)
159
+
*/
160
+
161
+
ctrl = CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED;
162
+
value = CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) |
163
+
CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) |
164
+
CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE |
165
+
CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS |
166
+
CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE |
167
+
CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS;
168
+
cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG,
169
+
CDNS_PCIE_HPA_LM_RC_BAR_CFG, value);
170
+
171
+
if (rc->vendor_id != 0xffff)
172
+
cdns_pcie_hpa_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id);
173
+
174
+
if (rc->device_id != 0xffff)
175
+
cdns_pcie_hpa_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id);
176
+
177
+
cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_REVISION, 0);
178
+
cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_PROG, 0);
179
+
cdns_pcie_hpa_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
180
+
181
+
/* Enable bus mastering */
182
+
value = cdns_pcie_hpa_readl(pcie, REG_BANK_RP, PCI_COMMAND);
183
+
value |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
184
+
cdns_pcie_hpa_writel(pcie, REG_BANK_RP, PCI_COMMAND, value);
185
+
return 0;
186
+
}
187
+
188
+
static void cdns_pcie_hpa_create_region_for_cfg(struct cdns_pcie_rc *rc)
189
+
{
190
+
struct cdns_pcie *pcie = &rc->pcie;
191
+
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc);
192
+
struct resource *cfg_res = rc->cfg_res;
193
+
struct resource_entry *entry;
194
+
u64 cpu_addr = cfg_res->start;
195
+
u32 addr0, addr1, desc1;
196
+
int busnr = 0;
197
+
198
+
entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
199
+
if (entry)
200
+
busnr = entry->res->start;
201
+
202
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
203
+
CDNS_PCIE_HPA_TAG_MANAGEMENT, 0x01000000);
204
+
/*
205
+
* Reserve region 0 for PCI configure space accesses:
206
+
* OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by
207
+
* cdns_pci_map_bus(), other region registers are set here once for all
208
+
*/
209
+
desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr);
210
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
211
+
CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), 0x0);
212
+
/* Type-1 CFG */
213
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
214
+
CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), 0x05000000);
215
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
216
+
CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1);
217
+
218
+
addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(12) |
219
+
(lower_32_bits(cpu_addr) & GENMASK(31, 8));
220
+
addr1 = upper_32_bits(cpu_addr);
221
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
222
+
CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), addr0);
223
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
224
+
CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), addr1);
225
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
226
+
CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), 0x06000000);
227
+
}
228
+
229
+
static int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc *rc)
230
+
{
231
+
struct cdns_pcie *pcie = &rc->pcie;
232
+
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc);
233
+
struct resource_entry *entry;
234
+
int r = 0, busnr = 0;
235
+
236
+
if (!rc->ecam_supported)
237
+
cdns_pcie_hpa_create_region_for_cfg(rc);
238
+
239
+
entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
240
+
if (entry)
241
+
busnr = entry->res->start;
242
+
243
+
r++;
244
+
if (pcie->msg_res) {
245
+
cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, busnr, 0, r,
246
+
pcie->msg_res->start);
247
+
248
+
r++;
249
+
}
250
+
resource_list_for_each_entry(entry, &bridge->windows) {
251
+
struct resource *res = entry->res;
252
+
u64 pci_addr = res->start - entry->offset;
253
+
254
+
if (resource_type(res) == IORESOURCE_IO)
255
+
cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r,
256
+
true,
257
+
pci_pio_to_address(res->start),
258
+
pci_addr,
259
+
resource_size(res));
260
+
else
261
+
cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r,
262
+
false,
263
+
res->start,
264
+
pci_addr,
265
+
resource_size(res));
266
+
267
+
r++;
268
+
}
269
+
270
+
if (rc->no_inbound_map)
271
+
return 0;
272
+
else
273
+
return cdns_pcie_host_map_dma_ranges(rc, cdns_pcie_hpa_host_bar_ib_config);
274
+
}
275
+
276
+
static int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc)
277
+
{
278
+
int err;
279
+
280
+
err = cdns_pcie_hpa_host_init_root_port(rc);
281
+
if (err)
282
+
return err;
283
+
284
+
return cdns_pcie_hpa_host_init_address_translation(rc);
285
+
}
286
+
287
+
int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc)
288
+
{
289
+
struct cdns_pcie *pcie = &rc->pcie;
290
+
struct device *dev = rc->pcie.dev;
291
+
int ret;
292
+
293
+
if (rc->quirk_detect_quiet_flag)
294
+
cdns_pcie_hpa_detect_quiet_min_delay_set(&rc->pcie);
295
+
296
+
cdns_pcie_hpa_host_enable_ptm_response(pcie);
297
+
298
+
ret = cdns_pcie_start_link(pcie);
299
+
if (ret) {
300
+
dev_err(dev, "Failed to start link\n");
301
+
return ret;
302
+
}
303
+
304
+
ret = cdns_pcie_host_wait_for_link(pcie, cdns_pcie_hpa_link_up);
305
+
if (ret)
306
+
dev_dbg(dev, "PCIe link never came up\n");
307
+
308
+
return ret;
309
+
}
310
+
EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup);
311
+
312
+
int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc)
313
+
{
314
+
struct device *dev = rc->pcie.dev;
315
+
struct platform_device *pdev = to_platform_device(dev);
316
+
struct pci_host_bridge *bridge;
317
+
enum cdns_pcie_rp_bar bar;
318
+
struct cdns_pcie *pcie;
319
+
struct resource *res;
320
+
int ret;
321
+
322
+
bridge = pci_host_bridge_from_priv(rc);
323
+
if (!bridge)
324
+
return -ENOMEM;
325
+
326
+
pcie = &rc->pcie;
327
+
pcie->is_rc = true;
328
+
329
+
if (!pcie->reg_base) {
330
+
pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
331
+
if (IS_ERR(pcie->reg_base)) {
332
+
dev_err(dev, "missing \"reg\"\n");
333
+
return PTR_ERR(pcie->reg_base);
334
+
}
335
+
}
336
+
337
+
/* ECAM config space is remapped at glue layer */
338
+
if (!rc->cfg_base) {
339
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
340
+
rc->cfg_base = devm_pci_remap_cfg_resource(dev, res);
341
+
if (IS_ERR(rc->cfg_base))
342
+
return PTR_ERR(rc->cfg_base);
343
+
rc->cfg_res = res;
344
+
}
345
+
346
+
/* Put EROM Bar aperture to 0 */
347
+
cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_EROM, 0x0);
348
+
349
+
ret = cdns_pcie_hpa_host_link_setup(rc);
350
+
if (ret)
351
+
return ret;
352
+
353
+
for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
354
+
rc->avail_ib_bar[bar] = true;
355
+
356
+
ret = cdns_pcie_hpa_host_init(rc);
357
+
if (ret)
358
+
return ret;
359
+
360
+
if (!bridge->ops)
361
+
bridge->ops = &cdns_pcie_hpa_host_ops;
362
+
363
+
return pci_host_probe(bridge);
364
+
}
365
+
EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_setup);
366
+
367
+
MODULE_LICENSE("GPL");
368
+
MODULE_DESCRIPTION("Cadence PCIe host controller driver");
+8
-270
drivers/pci/controller/cadence/pcie-cadence-host.c
+8
-270
drivers/pci/controller/cadence/pcie-cadence-host.c
···
12
12
#include <linux/platform_device.h>
13
13
14
14
#include "pcie-cadence.h"
15
-
16
-
#define LINK_RETRAIN_TIMEOUT HZ
17
-
18
-
static u64 bar_max_size[] = {
19
-
[RP_BAR0] = _ULL(128 * SZ_2G),
20
-
[RP_BAR1] = SZ_2G,
21
-
[RP_NO_BAR] = _BITULL(63),
22
-
};
15
+
#include "pcie-cadence-host-common.h"
23
16
24
17
static u8 bar_aperture_mask[] = {
25
18
[RP_BAR0] = 0x1F,
···
74
81
.write = pci_generic_config_write,
75
82
};
76
83
77
-
static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie)
78
-
{
79
-
u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
80
-
unsigned long end_jiffies;
81
-
u16 lnk_stat;
82
-
83
-
/* Wait for link training to complete. Exit after timeout. */
84
-
end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
85
-
do {
86
-
lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
87
-
if (!(lnk_stat & PCI_EXP_LNKSTA_LT))
88
-
break;
89
-
usleep_range(0, 1000);
90
-
} while (time_before(jiffies, end_jiffies));
91
-
92
-
if (!(lnk_stat & PCI_EXP_LNKSTA_LT))
93
-
return 0;
94
-
95
-
return -ETIMEDOUT;
96
-
}
97
-
98
-
static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie)
99
-
{
100
-
struct device *dev = pcie->dev;
101
-
int retries;
102
-
103
-
/* Check if the link is up or not */
104
-
for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
105
-
if (cdns_pcie_link_up(pcie)) {
106
-
dev_info(dev, "Link up\n");
107
-
return 0;
108
-
}
109
-
usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
110
-
}
111
-
112
-
return -ETIMEDOUT;
113
-
}
114
-
115
-
static int cdns_pcie_retrain(struct cdns_pcie *pcie)
116
-
{
117
-
u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
118
-
u16 lnk_stat, lnk_ctl;
119
-
int ret = 0;
120
-
121
-
/*
122
-
* Set retrain bit if current speed is 2.5 GB/s,
123
-
* but the PCIe root port support is > 2.5 GB/s.
124
-
*/
125
-
126
-
lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off +
127
-
PCI_EXP_LNKCAP));
128
-
if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
129
-
return ret;
130
-
131
-
lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
132
-
if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
133
-
lnk_ctl = cdns_pcie_rp_readw(pcie,
134
-
pcie_cap_off + PCI_EXP_LNKCTL);
135
-
lnk_ctl |= PCI_EXP_LNKCTL_RL;
136
-
cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
137
-
lnk_ctl);
138
-
139
-
ret = cdns_pcie_host_training_complete(pcie);
140
-
if (ret)
141
-
return ret;
142
-
143
-
ret = cdns_pcie_host_wait_for_link(pcie);
144
-
}
145
-
return ret;
146
-
}
147
-
148
84
static void cdns_pcie_host_disable_ptm_response(struct cdns_pcie *pcie)
149
85
{
150
86
u32 val;
···
88
166
89
167
val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);
90
168
cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);
91
-
}
92
-
93
-
static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
94
-
{
95
-
struct cdns_pcie *pcie = &rc->pcie;
96
-
int ret;
97
-
98
-
ret = cdns_pcie_host_wait_for_link(pcie);
99
-
100
-
/*
101
-
* Retrain link for Gen2 training defect
102
-
* if quirk flag is set.
103
-
*/
104
-
if (!ret && rc->quirk_retrain_flag)
105
-
ret = cdns_pcie_retrain(pcie);
106
-
107
-
return ret;
108
169
}
109
170
110
171
static void cdns_pcie_host_deinit_root_port(struct cdns_pcie_rc *rc)
···
150
245
return 0;
151
246
}
152
247
153
-
static int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc,
154
-
enum cdns_pcie_rp_bar bar,
155
-
u64 cpu_addr, u64 size,
156
-
unsigned long flags)
248
+
int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc,
249
+
enum cdns_pcie_rp_bar bar,
250
+
u64 cpu_addr,
251
+
u64 size,
252
+
unsigned long flags)
157
253
{
158
254
struct cdns_pcie *pcie = &rc->pcie;
159
255
u32 addr0, addr1, aperture, value;
···
196
290
return 0;
197
291
}
198
292
199
-
static enum cdns_pcie_rp_bar
200
-
cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size)
201
-
{
202
-
enum cdns_pcie_rp_bar bar, sel_bar;
203
-
204
-
sel_bar = RP_BAR_UNDEFINED;
205
-
for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) {
206
-
if (!rc->avail_ib_bar[bar])
207
-
continue;
208
-
209
-
if (size <= bar_max_size[bar]) {
210
-
if (sel_bar == RP_BAR_UNDEFINED) {
211
-
sel_bar = bar;
212
-
continue;
213
-
}
214
-
215
-
if (bar_max_size[bar] < bar_max_size[sel_bar])
216
-
sel_bar = bar;
217
-
}
218
-
}
219
-
220
-
return sel_bar;
221
-
}
222
-
223
-
static enum cdns_pcie_rp_bar
224
-
cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size)
225
-
{
226
-
enum cdns_pcie_rp_bar bar, sel_bar;
227
-
228
-
sel_bar = RP_BAR_UNDEFINED;
229
-
for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) {
230
-
if (!rc->avail_ib_bar[bar])
231
-
continue;
232
-
233
-
if (size >= bar_max_size[bar]) {
234
-
if (sel_bar == RP_BAR_UNDEFINED) {
235
-
sel_bar = bar;
236
-
continue;
237
-
}
238
-
239
-
if (bar_max_size[bar] > bar_max_size[sel_bar])
240
-
sel_bar = bar;
241
-
}
242
-
}
243
-
244
-
return sel_bar;
245
-
}
246
-
247
-
static int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc,
248
-
struct resource_entry *entry)
249
-
{
250
-
u64 cpu_addr, pci_addr, size, winsize;
251
-
struct cdns_pcie *pcie = &rc->pcie;
252
-
struct device *dev = pcie->dev;
253
-
enum cdns_pcie_rp_bar bar;
254
-
unsigned long flags;
255
-
int ret;
256
-
257
-
cpu_addr = entry->res->start;
258
-
pci_addr = entry->res->start - entry->offset;
259
-
flags = entry->res->flags;
260
-
size = resource_size(entry->res);
261
-
262
-
if (entry->offset) {
263
-
dev_err(dev, "PCI addr: %llx must be equal to CPU addr: %llx\n",
264
-
pci_addr, cpu_addr);
265
-
return -EINVAL;
266
-
}
267
-
268
-
while (size > 0) {
269
-
/*
270
-
* Try to find a minimum BAR whose size is greater than
271
-
* or equal to the remaining resource_entry size. This will
272
-
* fail if the size of each of the available BARs is less than
273
-
* the remaining resource_entry size.
274
-
* If a minimum BAR is found, IB ATU will be configured and
275
-
* exited.
276
-
*/
277
-
bar = cdns_pcie_host_find_min_bar(rc, size);
278
-
if (bar != RP_BAR_UNDEFINED) {
279
-
ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr,
280
-
size, flags);
281
-
if (ret)
282
-
dev_err(dev, "IB BAR: %d config failed\n", bar);
283
-
return ret;
284
-
}
285
-
286
-
/*
287
-
* If the control reaches here, it would mean the remaining
288
-
* resource_entry size cannot be fitted in a single BAR. So we
289
-
* find a maximum BAR whose size is less than or equal to the
290
-
* remaining resource_entry size and split the resource entry
291
-
* so that part of resource entry is fitted inside the maximum
292
-
* BAR. The remaining size would be fitted during the next
293
-
* iteration of the loop.
294
-
* If a maximum BAR is not found, there is no way we can fit
295
-
* this resource_entry, so we error out.
296
-
*/
297
-
bar = cdns_pcie_host_find_max_bar(rc, size);
298
-
if (bar == RP_BAR_UNDEFINED) {
299
-
dev_err(dev, "No free BAR to map cpu_addr %llx\n",
300
-
cpu_addr);
301
-
return -EINVAL;
302
-
}
303
-
304
-
winsize = bar_max_size[bar];
305
-
ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, winsize,
306
-
flags);
307
-
if (ret) {
308
-
dev_err(dev, "IB BAR: %d config failed\n", bar);
309
-
return ret;
310
-
}
311
-
312
-
size -= winsize;
313
-
cpu_addr += winsize;
314
-
}
315
-
316
-
return 0;
317
-
}
318
-
319
-
static int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a,
320
-
const struct list_head *b)
321
-
{
322
-
struct resource_entry *entry1, *entry2;
323
-
324
-
entry1 = container_of(a, struct resource_entry, node);
325
-
entry2 = container_of(b, struct resource_entry, node);
326
-
327
-
return resource_size(entry2->res) - resource_size(entry1->res);
328
-
}
329
-
330
293
static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc)
331
294
{
332
295
struct cdns_pcie *pcie = &rc->pcie;
···
220
445
LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2));
221
446
cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);
222
447
}
223
-
}
224
-
225
-
static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc)
226
-
{
227
-
struct cdns_pcie *pcie = &rc->pcie;
228
-
struct device *dev = pcie->dev;
229
-
struct device_node *np = dev->of_node;
230
-
struct pci_host_bridge *bridge;
231
-
struct resource_entry *entry;
232
-
u32 no_bar_nbits = 32;
233
-
int err;
234
-
235
-
bridge = pci_host_bridge_from_priv(rc);
236
-
if (!bridge)
237
-
return -ENOMEM;
238
-
239
-
if (list_empty(&bridge->dma_ranges)) {
240
-
of_property_read_u32(np, "cdns,no-bar-match-nbits",
241
-
&no_bar_nbits);
242
-
err = cdns_pcie_host_bar_ib_config(rc, RP_NO_BAR, 0x0,
243
-
(u64)1 << no_bar_nbits, 0);
244
-
if (err)
245
-
dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR);
246
-
return err;
247
-
}
248
-
249
-
list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp);
250
-
251
-
resource_list_for_each_entry(entry, &bridge->dma_ranges) {
252
-
err = cdns_pcie_host_bar_config(rc, entry);
253
-
if (err) {
254
-
dev_err(dev, "Fail to configure IB using dma-ranges\n");
255
-
return err;
256
-
}
257
-
}
258
-
259
-
return 0;
260
448
}
261
449
262
450
static void cdns_pcie_host_deinit_address_translation(struct cdns_pcie_rc *rc)
···
299
561
r++;
300
562
}
301
563
302
-
return cdns_pcie_host_map_dma_ranges(rc);
564
+
return cdns_pcie_host_map_dma_ranges(rc, cdns_pcie_host_bar_ib_config);
303
565
}
304
566
305
567
static void cdns_pcie_host_deinit(struct cdns_pcie_rc *rc)
···
345
607
return ret;
346
608
}
347
609
348
-
ret = cdns_pcie_host_start_link(rc);
610
+
ret = cdns_pcie_host_start_link(rc, cdns_pcie_link_up);
349
611
if (ret)
350
612
dev_dbg(dev, "PCIe link never came up\n");
351
613
+193
drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h
+193
drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Cadence PCIe controller driver.
4
+
*
5
+
* Copyright (c) 2024, Cadence Design Systems
6
+
* Author: Manikandan K Pillai <mpillai@cadence.com>
7
+
*/
8
+
#ifndef _PCIE_CADENCE_HPA_REGS_H
9
+
#define _PCIE_CADENCE_HPA_REGS_H
10
+
11
+
#include <linux/kernel.h>
12
+
#include <linux/pci.h>
13
+
#include <linux/pci-epf.h>
14
+
#include <linux/phy/phy.h>
15
+
#include <linux/bitfield.h>
16
+
17
+
/* High Performance Architecture (HPA) PCIe controller registers */
18
+
#define CDNS_PCIE_HPA_IP_REG_BANK 0x01000000
19
+
#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x01003C00
20
+
#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0x02020000
21
+
22
+
/* Address Translation Registers */
23
+
#define CDNS_PCIE_HPA_AXI_SLAVE 0x03000000
24
+
#define CDNS_PCIE_HPA_AXI_MASTER 0x03002000
25
+
26
+
/* Root Port register base address */
27
+
#define CDNS_PCIE_HPA_RP_BASE 0x0
28
+
29
+
#define CDNS_PCIE_HPA_LM_ID 0x1420
30
+
31
+
/* Endpoint Function BARs */
32
+
#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \
33
+
(((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \
34
+
CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn))
35
+
#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) (0x4000 * (pfn))
36
+
#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) ((0x4000 * (pfn)) + 0x04)
37
+
#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \
38
+
(((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \
39
+
CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn))
40
+
#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) ((0x4000 * (vfn)) + 0x08)
41
+
#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) ((0x4000 * (vfn)) + 0x0C)
42
+
#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \
43
+
(GENMASK(5, 0) << (0x4 + (f) * 10))
44
+
#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
45
+
(((a) << (4 + ((b) * 10))) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)))
46
+
#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \
47
+
(GENMASK(3, 0) << ((f) * 10))
48
+
#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
49
+
(((c) << ((b) * 10)) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)))
50
+
51
+
/* Endpoint Function Configuration Register */
52
+
#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG 0x02C0
53
+
54
+
/* Root Complex BAR Configuration Register */
55
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG 0x14
56
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(9, 4)
57
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
58
+
FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK, a)
59
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(3, 0)
60
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \
61
+
FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c)
62
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(19, 14)
63
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
64
+
FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK, a)
65
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(13, 10)
66
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \
67
+
FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c)
68
+
69
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(20)
70
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(21)
71
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE BIT(22)
72
+
#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS BIT(23)
73
+
74
+
/* BAR control values applicable to both Endpoint Function and Root Complex */
75
+
#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED 0x0
76
+
#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS 0x3
77
+
#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS 0x1
78
+
#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x9
79
+
#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS 0x5
80
+
#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0xD
81
+
82
+
#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \
83
+
(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10))
84
+
#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \
85
+
(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10))
86
+
#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \
87
+
(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10))
88
+
#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \
89
+
(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10))
90
+
#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \
91
+
(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10))
92
+
#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \
93
+
(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10))
94
+
#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture) \
95
+
(((aperture) - 7) << (((bar) * 10) + 4))
96
+
97
+
#define CDNS_PCIE_HPA_LM_PTM_CTRL 0x0520
98
+
#define CDNS_PCIE_HPA_LM_PTM_CTRL_PTMRSEN BIT(17)
99
+
100
+
/* Root Port Registers PCI config space for root port function */
101
+
#define CDNS_PCIE_HPA_RP_CAP_OFFSET 0xC0
102
+
103
+
/* Region r Outbound AXI to PCIe Address Translation Register 0 */
104
+
#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) (0x1010 + ((r) & 0x1F) * 0x0080)
105
+
#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
106
+
#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
107
+
(((nbits) - 1) & CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
108
+
#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(23, 16)
109
+
#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
110
+
FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK, devfn)
111
+
#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(31, 24)
112
+
#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
113
+
FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK, bus)
114
+
115
+
/* Region r Outbound AXI to PCIe Address Translation Register 1 */
116
+
#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) (0x1014 + ((r) & 0x1F) * 0x0080)
117
+
118
+
/* Region r Outbound PCIe Descriptor Register */
119
+
#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) (0x1008 + ((r) & 0x1F) * 0x0080)
120
+
#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(28, 24)
121
+
#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM \
122
+
FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0)
123
+
#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO \
124
+
FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2)
125
+
#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 \
126
+
FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4)
127
+
#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 \
128
+
FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5)
129
+
#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG \
130
+
FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10)
131
+
132
+
/* Region r Outbound PCIe Descriptor Register */
133
+
#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) (0x100C + ((r) & 0x1F) * 0x0080)
134
+
#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK GENMASK(31, 24)
135
+
#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \
136
+
FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK, bus)
137
+
#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK GENMASK(23, 16)
138
+
#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \
139
+
FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK, devfn)
140
+
141
+
#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) (0x1018 + ((r) & 0x1F) * 0x0080)
142
+
#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26)
143
+
#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25)
144
+
145
+
/* Region r AXI Region Base Address Register 0 */
146
+
#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) (0x1000 + ((r) & 0x1F) * 0x0080)
147
+
#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
148
+
#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
149
+
(((nbits) - 1) & CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
150
+
151
+
/* Region r AXI Region Base Address Register 1 */
152
+
#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) (0x1004 + ((r) & 0x1F) * 0x0080)
153
+
154
+
/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
155
+
#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) (((bar) * 0x0008))
156
+
#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
157
+
#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
158
+
(((nbits) - 1) & CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
159
+
#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) (0x04 + ((bar) * 0x0008))
160
+
161
+
/* AXI link down register */
162
+
#define CDNS_PCIE_HPA_AT_LINKDOWN 0x04
163
+
164
+
/*
165
+
* Physical Layer Configuration Register 0
166
+
* This register contains the parameters required for functional setup
167
+
* of Physical Layer.
168
+
*/
169
+
#define CDNS_PCIE_HPA_PHY_LAYER_CFG0 0x0400
170
+
#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK GENMASK(26, 24)
171
+
#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \
172
+
FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK, delay)
173
+
#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK GENMASK(27, 27)
174
+
175
+
#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0 0x0420
176
+
177
+
#define CDNS_PCIE_HPA_RP_MAX_IB 0x3
178
+
#define CDNS_PCIE_HPA_MAX_OB 15
179
+
180
+
/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
181
+
#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) (((fn) * 0x0080) + ((bar) * 0x0008))
182
+
#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) (0x4 + ((fn) * 0x0080) + ((bar) * 0x0008))
183
+
184
+
/* Miscellaneous offsets definitions */
185
+
#define CDNS_PCIE_HPA_TAG_MANAGEMENT 0x0
186
+
#define CDNS_PCIE_HPA_SLAVE_RESP 0x100
187
+
188
+
#define I_ROOT_PORT_REQ_ID_REG 0x141c
189
+
#define LM_HAL_SBSA_CTRL 0x1170
190
+
191
+
#define I_PCIE_BUS_NUMBERS (CDNS_PCIE_HPA_RP_BASE + 0x18)
192
+
#define CDNS_PCIE_EROM 0x18
193
+
#endif /* _PCIE_CADENCE_HPA_REGS_H */
+167
drivers/pci/controller/cadence/pcie-cadence-hpa.c
+167
drivers/pci/controller/cadence/pcie-cadence-hpa.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Cadence PCIe controller driver.
4
+
*
5
+
* Copyright (c) 2024, Cadence Design Systems
6
+
* Author: Manikandan K Pillai <mpillai@cadence.com>
7
+
*/
8
+
#include <linux/kernel.h>
9
+
#include <linux/of.h>
10
+
11
+
#include "pcie-cadence.h"
12
+
13
+
bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie)
14
+
{
15
+
u32 pl_reg_val;
16
+
17
+
pl_reg_val = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_DBG_STS_REG0);
18
+
if (pl_reg_val & GENMASK(0, 0))
19
+
return true;
20
+
return false;
21
+
}
22
+
EXPORT_SYMBOL_GPL(cdns_pcie_hpa_link_up);
23
+
24
+
void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie)
25
+
{
26
+
u32 delay = 0x3;
27
+
u32 ltssm_control_cap;
28
+
29
+
/* Set the LTSSM Detect Quiet state min. delay to 2ms */
30
+
ltssm_control_cap = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG,
31
+
CDNS_PCIE_HPA_PHY_LAYER_CFG0);
32
+
ltssm_control_cap = ((ltssm_control_cap &
33
+
~CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK) |
34
+
CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay));
35
+
36
+
cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG,
37
+
CDNS_PCIE_HPA_PHY_LAYER_CFG0, ltssm_control_cap);
38
+
}
39
+
EXPORT_SYMBOL_GPL(cdns_pcie_hpa_detect_quiet_min_delay_set);
40
+
41
+
void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
42
+
u32 r, bool is_io,
43
+
u64 cpu_addr, u64 pci_addr, size_t size)
44
+
{
45
+
/*
46
+
* roundup_pow_of_two() returns an unsigned long, which is not suited
47
+
* for 64bit values
48
+
*/
49
+
u64 sz = 1ULL << fls64(size - 1);
50
+
int nbits = ilog2(sz);
51
+
u32 addr0, addr1, desc0, desc1, ctrl0;
52
+
53
+
if (nbits < 8)
54
+
nbits = 8;
55
+
56
+
/* Set the PCI address */
57
+
addr0 = CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) |
58
+
(lower_32_bits(pci_addr) & GENMASK(31, 8));
59
+
addr1 = upper_32_bits(pci_addr);
60
+
61
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
62
+
CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), addr0);
63
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
64
+
CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), addr1);
65
+
66
+
/* Set the PCIe header descriptor */
67
+
if (is_io)
68
+
desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO;
69
+
else
70
+
desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM;
71
+
desc1 = 0;
72
+
ctrl0 = 0;
73
+
74
+
/*
75
+
* Whether Bit [26] is set or not inside DESC0 register of the outbound
76
+
* PCIe descriptor, the PCI function number must be set into
77
+
* Bits [31:24] of DESC1 anyway.
78
+
*
79
+
* In Root Complex mode, the function number is always 0 but in Endpoint
80
+
* mode, the PCIe controller may support more than one function. This
81
+
* function number needs to be set properly into the outbound PCIe
82
+
* descriptor.
83
+
*
84
+
* Besides, setting Bit [26] is mandatory when in Root Complex mode:
85
+
* then the driver must provide the bus, resp. device, number in
86
+
* Bits [31:24] of DESC1, resp. Bits[23:16] of DESC0. Like the function
87
+
* number, the device number is always 0 in Root Complex mode.
88
+
*
89
+
* However when in Endpoint mode, we can clear Bit [26] of DESC0, hence
90
+
* the PCIe controller will use the captured values for the bus and
91
+
* device numbers.
92
+
*/
93
+
if (pcie->is_rc) {
94
+
/* The device and function numbers are always 0 */
95
+
desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) |
96
+
CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0);
97
+
ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS |
98
+
CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN;
99
+
} else {
100
+
/*
101
+
* Use captured values for bus and device numbers but still
102
+
* need to set the function number
103
+
*/
104
+
desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn);
105
+
}
106
+
107
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
108
+
CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0);
109
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
110
+
CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1);
111
+
112
+
addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
113
+
(lower_32_bits(cpu_addr) & GENMASK(31, 8));
114
+
addr1 = upper_32_bits(cpu_addr);
115
+
116
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
117
+
CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0);
118
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
119
+
CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1);
120
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
121
+
CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0);
122
+
}
123
+
EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region);
124
+
125
+
void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
126
+
u8 busnr, u8 fn,
127
+
u32 r, u64 cpu_addr)
128
+
{
129
+
u32 addr0, addr1, desc0, desc1, ctrl0;
130
+
131
+
desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG;
132
+
desc1 = 0;
133
+
ctrl0 = 0;
134
+
135
+
/* See cdns_pcie_set_outbound_region() comments above */
136
+
if (pcie->is_rc) {
137
+
desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) |
138
+
CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0);
139
+
ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS |
140
+
CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN;
141
+
} else {
142
+
desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn);
143
+
}
144
+
145
+
addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(17) |
146
+
(lower_32_bits(cpu_addr) & GENMASK(31, 8));
147
+
addr1 = upper_32_bits(cpu_addr);
148
+
149
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
150
+
CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0);
151
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
152
+
CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0);
153
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
154
+
CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0);
155
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
156
+
CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1);
157
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
158
+
CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0);
159
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
160
+
CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1);
161
+
cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
162
+
CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0);
163
+
}
164
+
EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region_for_normal_msg);
165
+
166
+
MODULE_LICENSE("GPL");
167
+
MODULE_DESCRIPTION("Cadence PCIe controller driver");
+230
drivers/pci/controller/cadence/pcie-cadence-lga-regs.h
+230
drivers/pci/controller/cadence/pcie-cadence-lga-regs.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Cadence PCIe controller driver.
4
+
*
5
+
* Copyright (c) 2017 Cadence
6
+
* Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
7
+
*/
8
+
#ifndef _PCIE_CADENCE_LGA_REGS_H
9
+
#define _PCIE_CADENCE_LGA_REGS_H
10
+
11
+
#include <linux/bitfield.h>
12
+
13
+
/* Parameters for the waiting for link up routine */
14
+
#define LINK_WAIT_MAX_RETRIES 10
15
+
#define LINK_WAIT_USLEEP_MIN 90000
16
+
#define LINK_WAIT_USLEEP_MAX 100000
17
+
18
+
/* Local Management Registers */
19
+
#define CDNS_PCIE_LM_BASE 0x00100000
20
+
21
+
/* Vendor ID Register */
22
+
#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044)
23
+
#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)
24
+
#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0
25
+
#define CDNS_PCIE_LM_ID_VENDOR(vid) \
26
+
(((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)
27
+
#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)
28
+
#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16
29
+
#define CDNS_PCIE_LM_ID_SUBSYS(sub) \
30
+
(((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
31
+
32
+
/* Root Port Requester ID Register */
33
+
#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
34
+
#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
35
+
#define CDNS_PCIE_LM_RP_RID_SHIFT 0
36
+
#define CDNS_PCIE_LM_RP_RID_(rid) \
37
+
(((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK)
38
+
39
+
/* Endpoint Bus and Device Number Register */
40
+
#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022C)
41
+
#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0)
42
+
#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0
43
+
#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8)
44
+
#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8
45
+
46
+
/* Endpoint Function f BAR b Configuration Registers */
47
+
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \
48
+
(((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn))
49
+
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \
50
+
(CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)
51
+
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \
52
+
(CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)
53
+
#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \
54
+
(((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn))
55
+
#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \
56
+
(CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008)
57
+
#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \
58
+
(CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008)
59
+
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \
60
+
(GENMASK(4, 0) << ((b) * 8))
61
+
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
62
+
(((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))
63
+
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \
64
+
(GENMASK(7, 5) << ((b) * 8))
65
+
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
66
+
(((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
67
+
68
+
/* Endpoint Function Configuration Register */
69
+
#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02C0)
70
+
71
+
/* Root Complex BAR Configuration Register */
72
+
#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)
73
+
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
74
+
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
75
+
(((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK)
76
+
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
77
+
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \
78
+
(((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
79
+
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9)
80
+
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
81
+
(((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK)
82
+
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14)
83
+
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \
84
+
(((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)
85
+
#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17)
86
+
#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0
87
+
#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18)
88
+
#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19)
89
+
#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0
90
+
#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20)
91
+
#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31)
92
+
93
+
/* BAR control values applicable to both Endpoint Function and Root Complex */
94
+
#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0
95
+
#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1
96
+
#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4
97
+
#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5
98
+
#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6
99
+
#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7
100
+
101
+
#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \
102
+
(CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6))
103
+
#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \
104
+
(CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6))
105
+
#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \
106
+
(CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6))
107
+
#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \
108
+
(CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6))
109
+
#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \
110
+
(CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6))
111
+
#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \
112
+
(CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6))
113
+
#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \
114
+
(((aperture) - 2) << ((bar) * 8))
115
+
116
+
/* PTM Control Register */
117
+
#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0DA8)
118
+
#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17)
119
+
120
+
/*
121
+
* Endpoint Function Registers (PCI configuration space for endpoint functions)
122
+
*/
123
+
#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
124
+
125
+
#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90
126
+
#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xB0
127
+
#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xC0
128
+
#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200
129
+
130
+
/* Endpoint PF Registers */
131
+
#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000)
132
+
#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8)
133
+
134
+
/* Root Port Registers (PCI configuration space for the root port function) */
135
+
#define CDNS_PCIE_RP_BASE 0x00200000
136
+
#define CDNS_PCIE_RP_CAP_OFFSET 0xC0
137
+
138
+
/* Address Translation Registers */
139
+
#define CDNS_PCIE_AT_BASE 0x00400000
140
+
141
+
/* Region r Outbound AXI to PCIe Address Translation Register 0 */
142
+
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
143
+
(CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1F) * 0x0020)
144
+
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
145
+
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
146
+
(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
147
+
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)
148
+
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
149
+
(((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
150
+
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)
151
+
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
152
+
(((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
153
+
154
+
/* Region r Outbound AXI to PCIe Address Translation Register 1 */
155
+
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
156
+
(CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1F) * 0x0020)
157
+
158
+
/* Region r Outbound PCIe Descriptor Register 0 */
159
+
#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \
160
+
(CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1F) * 0x0020)
161
+
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0)
162
+
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2
163
+
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6
164
+
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xA
165
+
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xB
166
+
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xC
167
+
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xD
168
+
/* Bit 23 MUST be set in RC mode. */
169
+
#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)
170
+
#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)
171
+
#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
172
+
(((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
173
+
174
+
/* Region r Outbound PCIe Descriptor Register 1 */
175
+
#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \
176
+
(CDNS_PCIE_AT_BASE + 0x000C + ((r) & 0x1F) * 0x0020)
177
+
#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0)
178
+
#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \
179
+
((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
180
+
181
+
/* Region r AXI Region Base Address Register 0 */
182
+
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
183
+
(CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1F) * 0x0020)
184
+
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
185
+
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
186
+
(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
187
+
188
+
/* Region r AXI Region Base Address Register 1 */
189
+
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
190
+
(CDNS_PCIE_AT_BASE + 0x001C + ((r) & 0x1F) * 0x0020)
191
+
192
+
/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
193
+
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
194
+
(CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
195
+
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
196
+
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
197
+
(((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
198
+
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
199
+
(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
200
+
201
+
/* AXI link down register */
202
+
#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
203
+
204
+
/* LTSSM Capabilities register */
205
+
#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054)
206
+
#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1)
207
+
#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1
208
+
#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \
209
+
(((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \
210
+
CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK)
211
+
212
+
#define CDNS_PCIE_RP_MAX_IB 0x3
213
+
#define CDNS_PCIE_MAX_OB 32
214
+
215
+
/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
216
+
#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
217
+
(CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
218
+
#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
219
+
(CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
220
+
221
+
/* Normal/Vendor specific message access: offset inside some outbound region */
222
+
#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5)
223
+
#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \
224
+
(((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
225
+
#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8)
226
+
#define CDNS_PCIE_NORMAL_MSG_CODE(code) \
227
+
(((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK)
228
+
#define CDNS_PCIE_MSG_NO_DATA BIT(16)
229
+
230
+
#endif /* _PCIE_CADENCE_LGA_REGS_H */
+4
-5
drivers/pci/controller/cadence/pcie-cadence-plat.c
+4
-5
drivers/pci/controller/cadence/pcie-cadence-plat.c
···
22
22
struct cdns_pcie *pcie;
23
23
};
24
24
25
-
struct cdns_plat_pcie_of_data {
26
-
bool is_rc;
27
-
};
28
-
29
25
static const struct of_device_id cdns_plat_pcie_of_match[];
30
26
31
27
static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr)
···
173
177
.probe = cdns_plat_pcie_probe,
174
178
.shutdown = cdns_plat_pcie_shutdown,
175
179
};
176
-
builtin_platform_driver(cdns_plat_pcie_driver);
180
+
module_platform_driver(cdns_plat_pcie_driver);
181
+
182
+
MODULE_LICENSE("GPL");
183
+
MODULE_DESCRIPTION("Cadence PCIe controller platform driver");
+12
drivers/pci/controller/cadence/pcie-cadence.c
+12
drivers/pci/controller/cadence/pcie-cadence.c
···
23
23
}
24
24
EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability);
25
25
26
+
bool cdns_pcie_linkup(struct cdns_pcie *pcie)
27
+
{
28
+
u32 pl_reg_val;
29
+
30
+
pl_reg_val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE);
31
+
if (pl_reg_val & GENMASK(0, 0))
32
+
return true;
33
+
return false;
34
+
}
35
+
EXPORT_SYMBOL_GPL(cdns_pcie_linkup);
36
+
26
37
void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie)
27
38
{
28
39
u32 delay = 0x3;
···
304
293
NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
305
294
cdns_pcie_resume_noirq)
306
295
};
296
+
EXPORT_SYMBOL_GPL(cdns_pcie_pm_ops);
307
297
308
298
MODULE_LICENSE("GPL");
309
299
MODULE_DESCRIPTION("Cadence PCIe controller driver");
+174
-235
drivers/pci/controller/cadence/pcie-cadence.h
+174
-235
drivers/pci/controller/cadence/pcie-cadence.h
···
7
7
#define _PCIE_CADENCE_H
8
8
9
9
#include <linux/kernel.h>
10
+
#include <linux/module.h>
10
11
#include <linux/pci.h>
11
12
#include <linux/pci-epf.h>
12
13
#include <linux/phy/phy.h>
13
-
14
-
/* Parameters for the waiting for link up routine */
15
-
#define LINK_WAIT_MAX_RETRIES 10
16
-
#define LINK_WAIT_USLEEP_MIN 90000
17
-
#define LINK_WAIT_USLEEP_MAX 100000
18
-
19
-
/*
20
-
* Local Management Registers
21
-
*/
22
-
#define CDNS_PCIE_LM_BASE 0x00100000
23
-
24
-
/* Vendor ID Register */
25
-
#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044)
26
-
#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)
27
-
#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0
28
-
#define CDNS_PCIE_LM_ID_VENDOR(vid) \
29
-
(((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)
30
-
#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)
31
-
#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16
32
-
#define CDNS_PCIE_LM_ID_SUBSYS(sub) \
33
-
(((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
34
-
35
-
/* Root Port Requester ID Register */
36
-
#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
37
-
#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
38
-
#define CDNS_PCIE_LM_RP_RID_SHIFT 0
39
-
#define CDNS_PCIE_LM_RP_RID_(rid) \
40
-
(((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK)
41
-
42
-
/* Endpoint Bus and Device Number Register */
43
-
#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c)
44
-
#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0)
45
-
#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0
46
-
#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8)
47
-
#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8
48
-
49
-
/* Endpoint Function f BAR b Configuration Registers */
50
-
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \
51
-
(((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn))
52
-
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \
53
-
(CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)
54
-
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \
55
-
(CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)
56
-
#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \
57
-
(((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn))
58
-
#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \
59
-
(CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008)
60
-
#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \
61
-
(CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008)
62
-
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \
63
-
(GENMASK(4, 0) << ((b) * 8))
64
-
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
65
-
(((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))
66
-
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \
67
-
(GENMASK(7, 5) << ((b) * 8))
68
-
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
69
-
(((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
70
-
71
-
/* Endpoint Function Configuration Register */
72
-
#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0)
73
-
74
-
/* Root Complex BAR Configuration Register */
75
-
#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)
76
-
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
77
-
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
78
-
(((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK)
79
-
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
80
-
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \
81
-
(((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
82
-
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9)
83
-
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
84
-
(((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK)
85
-
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14)
86
-
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \
87
-
(((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)
88
-
#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17)
89
-
#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0
90
-
#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18)
91
-
#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19)
92
-
#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0
93
-
#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20)
94
-
#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31)
95
-
96
-
/* BAR control values applicable to both Endpoint Function and Root Complex */
97
-
#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0
98
-
#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1
99
-
#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4
100
-
#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5
101
-
#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6
102
-
#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7
103
-
104
-
#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \
105
-
(CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6))
106
-
#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \
107
-
(CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6))
108
-
#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \
109
-
(CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6))
110
-
#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \
111
-
(CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6))
112
-
#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \
113
-
(CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6))
114
-
#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \
115
-
(CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6))
116
-
#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \
117
-
(((aperture) - 2) << ((bar) * 8))
118
-
119
-
/* PTM Control Register */
120
-
#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8)
121
-
#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17)
122
-
123
-
/*
124
-
* Endpoint Function Registers (PCI configuration space for endpoint functions)
125
-
*/
126
-
#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
127
-
128
-
/*
129
-
* Endpoint PF Registers
130
-
*/
131
-
#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000)
132
-
#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8)
133
-
134
-
/*
135
-
* Root Port Registers (PCI configuration space for the root port function)
136
-
*/
137
-
#define CDNS_PCIE_RP_BASE 0x00200000
138
-
#define CDNS_PCIE_RP_CAP_OFFSET 0xc0
139
-
140
-
/*
141
-
* Address Translation Registers
142
-
*/
143
-
#define CDNS_PCIE_AT_BASE 0x00400000
144
-
145
-
/* Region r Outbound AXI to PCIe Address Translation Register 0 */
146
-
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
147
-
(CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
148
-
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
149
-
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
150
-
(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
151
-
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)
152
-
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
153
-
(((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
154
-
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)
155
-
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
156
-
(((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
157
-
158
-
/* Region r Outbound AXI to PCIe Address Translation Register 1 */
159
-
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
160
-
(CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
161
-
162
-
/* Region r Outbound PCIe Descriptor Register 0 */
163
-
#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \
164
-
(CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
165
-
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0)
166
-
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2
167
-
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6
168
-
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa
169
-
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb
170
-
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc
171
-
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd
172
-
/* Bit 23 MUST be set in RC mode. */
173
-
#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)
174
-
#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)
175
-
#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
176
-
(((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
177
-
178
-
/* Region r Outbound PCIe Descriptor Register 1 */
179
-
#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \
180
-
(CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
181
-
#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0)
182
-
#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \
183
-
((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
184
-
185
-
/* Region r AXI Region Base Address Register 0 */
186
-
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
187
-
(CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
188
-
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
189
-
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
190
-
(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
191
-
192
-
/* Region r AXI Region Base Address Register 1 */
193
-
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
194
-
(CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
195
-
196
-
/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
197
-
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
198
-
(CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
199
-
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
200
-
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
201
-
(((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
202
-
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
203
-
(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
204
-
205
-
/* AXI link down register */
206
-
#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
207
-
208
-
/* LTSSM Capabilities register */
209
-
#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054)
210
-
#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1)
211
-
#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1
212
-
#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \
213
-
(((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \
214
-
CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK)
14
+
#include "pcie-cadence-lga-regs.h"
15
+
#include "pcie-cadence-hpa-regs.h"
215
16
216
17
enum cdns_pcie_rp_bar {
217
18
RP_BAR_UNDEFINED = -1,
···
21
220
RP_NO_BAR
22
221
};
23
222
24
-
#define CDNS_PCIE_RP_MAX_IB 0x3
25
-
#define CDNS_PCIE_MAX_OB 32
26
-
27
223
struct cdns_pcie_rp_ib_bar {
28
224
u64 size;
29
225
bool free;
30
226
};
31
227
32
-
/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
33
-
#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
34
-
(CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
35
-
#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
36
-
(CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
37
-
38
-
/* Normal/Vendor specific message access: offset inside some outbound region */
39
-
#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5)
40
-
#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \
41
-
(((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
42
-
#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8)
43
-
#define CDNS_PCIE_NORMAL_MSG_CODE(code) \
44
-
(((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK)
45
-
#define CDNS_PCIE_MSG_DATA BIT(16)
46
-
47
228
struct cdns_pcie;
229
+
struct cdns_pcie_rc;
230
+
231
+
enum cdns_pcie_reg_bank {
232
+
REG_BANK_RP,
233
+
REG_BANK_IP_REG,
234
+
REG_BANK_IP_CFG_CTRL_REG,
235
+
REG_BANK_AXI_MASTER_COMMON,
236
+
REG_BANK_AXI_MASTER,
237
+
REG_BANK_AXI_SLAVE,
238
+
REG_BANK_AXI_HLS,
239
+
REG_BANK_AXI_RAS,
240
+
REG_BANK_AXI_DTI,
241
+
REG_BANKS_MAX,
242
+
};
48
243
49
244
struct cdns_pcie_ops {
50
-
int (*start_link)(struct cdns_pcie *pcie);
51
-
void (*stop_link)(struct cdns_pcie *pcie);
52
-
bool (*link_up)(struct cdns_pcie *pcie);
245
+
int (*start_link)(struct cdns_pcie *pcie);
246
+
void (*stop_link)(struct cdns_pcie *pcie);
247
+
bool (*link_up)(struct cdns_pcie *pcie);
53
248
u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr);
249
+
};
250
+
251
+
/**
252
+
* struct cdns_plat_pcie_of_data - Register bank offset for a platform
253
+
* @is_rc: controller is a RC
254
+
* @ip_reg_bank_offset: ip register bank start offset
255
+
* @ip_cfg_ctrl_reg_offset: ip config control register start offset
256
+
* @axi_mstr_common_offset: AXI master common register start offset
257
+
* @axi_slave_offset: AXI slave start offset
258
+
* @axi_master_offset: AXI master start offset
259
+
* @axi_hls_offset: AXI HLS offset start
260
+
* @axi_ras_offset: AXI RAS offset
261
+
* @axi_dti_offset: AXI DTI offset
262
+
*/
263
+
struct cdns_plat_pcie_of_data {
264
+
u32 is_rc:1;
265
+
u32 ip_reg_bank_offset;
266
+
u32 ip_cfg_ctrl_reg_offset;
267
+
u32 axi_mstr_common_offset;
268
+
u32 axi_slave_offset;
269
+
u32 axi_master_offset;
270
+
u32 axi_hls_offset;
271
+
u32 axi_ras_offset;
272
+
u32 axi_dti_offset;
54
273
};
55
274
56
275
/**
57
276
* struct cdns_pcie - private data for Cadence PCIe controller drivers
58
277
* @reg_base: IO mapped register base
59
278
* @mem_res: start/end offsets in the physical system memory to map PCI accesses
279
+
* @msg_res: Region for send message to map PCI accesses
60
280
* @dev: PCIe controller
61
281
* @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
62
282
* @phy_count: number of supported PHY devices
···
85
263
* @link: list of pointers to corresponding device link representations
86
264
* @ops: Platform-specific ops to control various inputs from Cadence PCIe
87
265
* wrapper
266
+
* @cdns_pcie_reg_offsets: Register bank offsets for different SoC
88
267
*/
89
268
struct cdns_pcie {
90
-
void __iomem *reg_base;
91
-
struct resource *mem_res;
92
-
struct device *dev;
93
-
bool is_rc;
94
-
int phy_count;
95
-
struct phy **phy;
96
-
struct device_link **link;
97
-
const struct cdns_pcie_ops *ops;
269
+
void __iomem *reg_base;
270
+
struct resource *mem_res;
271
+
struct resource *msg_res;
272
+
struct device *dev;
273
+
bool is_rc;
274
+
int phy_count;
275
+
struct phy **phy;
276
+
struct device_link **link;
277
+
const struct cdns_pcie_ops *ops;
278
+
const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
98
279
};
99
280
100
281
/**
···
113
288
* available
114
289
* @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2
115
290
* @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
291
+
* @ecam_supported: Whether the ECAM is supported
292
+
* @no_inbound_map: Whether inbound mapping is supported
116
293
*/
117
294
struct cdns_pcie_rc {
118
295
struct cdns_pcie pcie;
···
125
298
bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB];
126
299
unsigned int quirk_retrain_flag:1;
127
300
unsigned int quirk_detect_quiet_flag:1;
301
+
unsigned int ecam_supported:1;
302
+
unsigned int no_inbound_map:1;
128
303
};
129
304
130
305
/**
···
179
350
unsigned int quirk_disable_flr:1;
180
351
};
181
352
353
+
static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_pcie_reg_bank bank)
354
+
{
355
+
u32 offset = 0x0;
356
+
357
+
switch (bank) {
358
+
case REG_BANK_RP:
359
+
offset = 0;
360
+
break;
361
+
case REG_BANK_IP_REG:
362
+
offset = pcie->cdns_pcie_reg_offsets->ip_reg_bank_offset;
363
+
break;
364
+
case REG_BANK_IP_CFG_CTRL_REG:
365
+
offset = pcie->cdns_pcie_reg_offsets->ip_cfg_ctrl_reg_offset;
366
+
break;
367
+
case REG_BANK_AXI_MASTER_COMMON:
368
+
offset = pcie->cdns_pcie_reg_offsets->axi_mstr_common_offset;
369
+
break;
370
+
case REG_BANK_AXI_MASTER:
371
+
offset = pcie->cdns_pcie_reg_offsets->axi_master_offset;
372
+
break;
373
+
case REG_BANK_AXI_SLAVE:
374
+
offset = pcie->cdns_pcie_reg_offsets->axi_slave_offset;
375
+
break;
376
+
case REG_BANK_AXI_HLS:
377
+
offset = pcie->cdns_pcie_reg_offsets->axi_hls_offset;
378
+
break;
379
+
case REG_BANK_AXI_RAS:
380
+
offset = pcie->cdns_pcie_reg_offsets->axi_ras_offset;
381
+
break;
382
+
case REG_BANK_AXI_DTI:
383
+
offset = pcie->cdns_pcie_reg_offsets->axi_dti_offset;
384
+
break;
385
+
default:
386
+
break;
387
+
}
388
+
return offset;
389
+
}
182
390
183
391
/* Register access */
184
392
static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value)
···
225
359
226
360
static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
227
361
{
362
+
return readl(pcie->reg_base + reg);
363
+
}
364
+
365
+
static inline void cdns_pcie_hpa_writel(struct cdns_pcie *pcie,
366
+
enum cdns_pcie_reg_bank bank,
367
+
u32 reg,
368
+
u32 value)
369
+
{
370
+
u32 offset = cdns_reg_bank_to_off(pcie, bank);
371
+
372
+
reg += offset;
373
+
writel(value, pcie->reg_base + reg);
374
+
}
375
+
376
+
static inline u32 cdns_pcie_hpa_readl(struct cdns_pcie *pcie,
377
+
enum cdns_pcie_reg_bank bank,
378
+
u32 reg)
379
+
{
380
+
u32 offset = cdns_reg_bank_to_off(pcie, bank);
381
+
382
+
reg += offset;
228
383
return readl(pcie->reg_base + reg);
229
384
}
230
385
···
344
457
return cdns_pcie_read_sz(addr, 0x2);
345
458
}
346
459
460
+
static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie,
461
+
u32 reg, u8 value)
462
+
{
463
+
void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg;
464
+
465
+
cdns_pcie_write_sz(addr, 0x1, value);
466
+
}
467
+
468
+
static inline void cdns_pcie_hpa_rp_writew(struct cdns_pcie *pcie,
469
+
u32 reg, u16 value)
470
+
{
471
+
void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg;
472
+
473
+
cdns_pcie_write_sz(addr, 0x2, value);
474
+
}
475
+
476
+
static inline u16 cdns_pcie_hpa_rp_readw(struct cdns_pcie *pcie, u32 reg)
477
+
{
478
+
void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg;
479
+
480
+
return cdns_pcie_read_sz(addr, 0x2);
481
+
}
482
+
347
483
/* Endpoint Function register access */
348
484
static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
349
485
u32 reg, u8 value)
···
431
521
void cdns_pcie_host_disable(struct cdns_pcie_rc *rc);
432
522
void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
433
523
int where);
524
+
int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc);
434
525
#else
435
526
static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)
436
527
{
···
444
533
}
445
534
446
535
static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
536
+
{
537
+
return 0;
538
+
}
539
+
540
+
static inline int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc)
447
541
{
448
542
return 0;
449
543
}
···
467
551
#if IS_ENABLED(CONFIG_PCIE_CADENCE_EP)
468
552
int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep);
469
553
void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep);
554
+
int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep);
470
555
#else
471
556
static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
472
557
{
···
477
560
static inline void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep)
478
561
{
479
562
}
563
+
564
+
static inline int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep)
565
+
{
566
+
return 0;
567
+
}
568
+
480
569
#endif
481
570
482
-
u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap);
483
-
u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap);
571
+
u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap);
572
+
u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap);
573
+
bool cdns_pcie_linkup(struct cdns_pcie *pcie);
484
574
485
575
void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
486
576
···
501
577
502
578
void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
503
579
void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
504
-
int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
505
-
int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
580
+
int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
581
+
int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
582
+
void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
583
+
void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
584
+
u32 r, bool is_io,
585
+
u64 cpu_addr, u64 pci_addr, size_t size);
586
+
void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
587
+
u8 busnr, u8 fn,
588
+
u32 r, u64 cpu_addr);
589
+
int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc);
590
+
void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn,
591
+
int where);
592
+
int cdns_pcie_hpa_host_start_link(struct cdns_pcie_rc *rc);
593
+
int cdns_pcie_hpa_start_link(struct cdns_pcie *pcie);
594
+
void cdns_pcie_hpa_stop_link(struct cdns_pcie *pcie);
595
+
bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie);
596
+
506
597
extern const struct dev_pm_ops cdns_pcie_pm_ops;
507
598
508
599
#endif /* _PCIE_CADENCE_H */
-3
drivers/pci/controller/cadence/pcie-sg2042.c
-3
drivers/pci/controller/cadence/pcie-sg2042.c
···
74
74
static void sg2042_pcie_remove(struct platform_device *pdev)
75
75
{
76
76
struct cdns_pcie *pcie = platform_get_drvdata(pdev);
77
-
struct device *dev = &pdev->dev;
78
77
struct cdns_pcie_rc *rc;
79
78
80
79
rc = container_of(pcie, struct cdns_pcie_rc, pcie);
81
80
cdns_pcie_host_disable(rc);
82
81
83
82
cdns_pcie_disable_phy(pcie);
84
-
85
-
pm_runtime_disable(dev);
86
83
}
87
84
88
85
static int sg2042_pcie_suspend_noirq(struct device *dev)
+34
-4
drivers/pci/controller/dwc/Kconfig
+34
-4
drivers/pci/controller/dwc/Kconfig
···
256
256
in order to enable device-specific features PCIE_TEGRA194_EP must be
257
257
selected. This uses the DesignWare core.
258
258
259
+
config PCIE_NXP_S32G
260
+
bool "NXP S32G PCIe controller (host mode)"
261
+
depends on ARCH_S32 || COMPILE_TEST
262
+
select PCIE_DW_HOST
263
+
help
264
+
Enable support for the PCIe controller in NXP S32G based boards to
265
+
work in Host mode. The controller is based on DesignWare IP and
266
+
can work either as RC or EP. In order to enable host-specific
267
+
features PCIE_NXP_S32G must be selected.
268
+
259
269
config PCIE_DW_PLAT
260
270
bool
261
271
···
426
416
Say Y here if you want PCIe host controller support on
427
417
Sophgo SoCs.
428
418
419
+
config PCIE_SPACEMIT_K1
420
+
tristate "SpacemiT K1 PCIe controller (host mode)"
421
+
depends on ARCH_SPACEMIT || COMPILE_TEST
422
+
depends on HAS_IOMEM
423
+
select PCIE_DW_HOST
424
+
select PCI_PWRCTRL_SLOT
425
+
default ARCH_SPACEMIT
426
+
help
427
+
Enables support for the DesignWare based PCIe controller in
428
+
the SpacemiT K1 SoC operating in host mode. Three controllers
429
+
are available on the K1 SoC; the first of these shares a PHY
430
+
with a USB 3.0 host controller (one or the other can be used).
431
+
429
432
config PCIE_SPEAR13XX
430
433
bool "STMicroelectronics SPEAr PCIe controller"
431
434
depends on ARCH_SPEAR13XX || COMPILE_TEST
···
505
482
to enable device-specific features PCI_DRA7XX_EP must be selected.
506
483
This uses the DesignWare core.
507
484
485
+
# ARM32 platforms use hook_fault_code() and cannot support loadable module.
508
486
config PCI_KEYSTONE
509
487
bool
510
488
489
+
# On non-ARM32 platforms, loadable module can be supported.
490
+
config PCI_KEYSTONE_TRISTATE
491
+
tristate
492
+
511
493
config PCI_KEYSTONE_HOST
512
-
bool "TI Keystone PCIe controller (host mode)"
494
+
tristate "TI Keystone PCIe controller (host mode)"
513
495
depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
514
496
depends on PCI_MSI
515
497
select PCIE_DW_HOST
516
-
select PCI_KEYSTONE
498
+
select PCI_KEYSTONE if ARM
499
+
select PCI_KEYSTONE_TRISTATE if !ARM
517
500
help
518
501
Enables support for the PCIe controller in the Keystone SoC to
519
502
work in host mode. The PCI controller on Keystone is based on
···
527
498
DesignWare core functions to implement the driver.
528
499
529
500
config PCI_KEYSTONE_EP
530
-
bool "TI Keystone PCIe controller (endpoint mode)"
501
+
tristate "TI Keystone PCIe controller (endpoint mode)"
531
502
depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
532
503
depends on PCI_ENDPOINT
533
504
select PCIE_DW_EP
534
-
select PCI_KEYSTONE
505
+
select PCI_KEYSTONE if ARM
506
+
select PCI_KEYSTONE_TRISTATE if !ARM
535
507
help
536
508
Enables support for the PCIe controller in the Keystone SoC to
537
509
work in endpoint mode. The PCI controller on Keystone is based
+5
drivers/pci/controller/dwc/Makefile
+5
drivers/pci/controller/dwc/Makefile
···
10
10
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
11
11
obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
12
12
obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
13
+
obj-$(CONFIG_PCIE_NXP_S32G) += pcie-nxp-s32g.o
13
14
obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
15
+
# ARM32 platforms use hook_fault_code() and cannot support loadable module.
14
16
obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
17
+
# On non-ARM32 platforms, loadable module can be supported.
18
+
obj-$(CONFIG_PCI_KEYSTONE_TRISTATE) += pci-keystone.o
15
19
obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
16
20
obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o
17
21
obj-$(CONFIG_PCIE_QCOM_COMMON) += pcie-qcom-common.o
···
35
31
obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
36
32
obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
37
33
obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
34
+
obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o
38
35
obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
39
36
obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
40
37
+47
-33
drivers/pci/controller/dwc/pci-keystone.c
+47
-33
drivers/pci/controller/dwc/pci-keystone.c
···
17
17
#include <linux/irqchip/chained_irq.h>
18
18
#include <linux/irqdomain.h>
19
19
#include <linux/mfd/syscon.h>
20
+
#include <linux/module.h>
20
21
#include <linux/msi.h>
21
22
#include <linux/of.h>
22
23
#include <linux/of_irq.h>
···
778
777
return ret;
779
778
}
780
779
781
-
#ifdef CONFIG_ARM
782
-
/*
783
-
* When a PCI device does not exist during config cycles, keystone host
784
-
* gets a bus error instead of returning 0xffffffff (PCI_ERROR_RESPONSE).
785
-
* This handler always returns 0 for this kind of fault.
786
-
*/
787
-
static int ks_pcie_fault(unsigned long addr, unsigned int fsr,
788
-
struct pt_regs *regs)
789
-
{
790
-
unsigned long instr = *(unsigned long *) instruction_pointer(regs);
791
-
792
-
if ((instr & 0x0e100090) == 0x00100090) {
793
-
int reg = (instr >> 12) & 15;
794
-
795
-
regs->uregs[reg] = -1;
796
-
regs->ARM_pc += 4;
797
-
}
798
-
799
-
return 0;
800
-
}
801
-
#endif
802
-
803
-
static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie)
780
+
static int ks_pcie_init_id(struct keystone_pcie *ks_pcie)
804
781
{
805
782
int ret;
806
783
unsigned int id;
···
810
831
return 0;
811
832
}
812
833
813
-
static int __init ks_pcie_host_init(struct dw_pcie_rp *pp)
834
+
static int ks_pcie_host_init(struct dw_pcie_rp *pp)
814
835
{
815
836
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
816
837
struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
···
839
860
ret = ks_pcie_init_id(ks_pcie);
840
861
if (ret < 0)
841
862
return ret;
842
-
843
-
#ifdef CONFIG_ARM
844
-
/*
845
-
* PCIe access errors that result into OCP errors are caught by ARM as
846
-
* "External aborts"
847
-
*/
848
-
hook_fault_code(17, ks_pcie_fault, SIGBUS, 0,
849
-
"Asynchronous external abort");
850
-
#endif
851
863
852
864
return 0;
853
865
}
···
1104
1134
},
1105
1135
{ },
1106
1136
};
1137
+
MODULE_DEVICE_TABLE(of, ks_pcie_of_match);
1107
1138
1108
1139
static int ks_pcie_probe(struct platform_device *pdev)
1109
1140
{
···
1308
1337
break;
1309
1338
default:
1310
1339
dev_err(dev, "INVALID device type %d\n", mode);
1340
+
ret = -EINVAL;
1341
+
goto err_get_sync;
1311
1342
}
1312
1343
1313
1344
ks_pcie_enable_error_irq(ks_pcie);
···
1352
1379
.of_match_table = ks_pcie_of_match,
1353
1380
},
1354
1381
};
1382
+
1383
+
#ifdef CONFIG_ARM
1384
+
/*
1385
+
* When a PCI device does not exist during config cycles, keystone host
1386
+
* gets a bus error instead of returning 0xffffffff (PCI_ERROR_RESPONSE).
1387
+
* This handler always returns 0 for this kind of fault.
1388
+
*/
1389
+
static int ks_pcie_fault(unsigned long addr, unsigned int fsr,
1390
+
struct pt_regs *regs)
1391
+
{
1392
+
unsigned long instr = *(unsigned long *)instruction_pointer(regs);
1393
+
1394
+
if ((instr & 0x0e100090) == 0x00100090) {
1395
+
int reg = (instr >> 12) & 15;
1396
+
1397
+
regs->uregs[reg] = -1;
1398
+
regs->ARM_pc += 4;
1399
+
}
1400
+
1401
+
return 0;
1402
+
}
1403
+
1404
+
static int __init ks_pcie_init(void)
1405
+
{
1406
+
/*
1407
+
* PCIe access errors that result into OCP errors are caught by ARM as
1408
+
* "External aborts"
1409
+
*/
1410
+
if (of_find_matching_node(NULL, ks_pcie_of_match))
1411
+
hook_fault_code(17, ks_pcie_fault, SIGBUS, 0,
1412
+
"Asynchronous external abort");
1413
+
1414
+
return platform_driver_register(&ks_pcie_driver);
1415
+
}
1416
+
device_initcall(ks_pcie_init);
1417
+
#else
1355
1418
builtin_platform_driver(ks_pcie_driver);
1419
+
#endif
1420
+
1421
+
MODULE_LICENSE("GPL");
1422
+
MODULE_DESCRIPTION("PCIe controller driver for Texas Instruments Keystone SoCs");
1423
+
MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
+15
-3
drivers/pci/controller/dwc/pci-meson.c
+15
-3
drivers/pci/controller/dwc/pci-meson.c
···
108
108
struct meson_pcie *mp)
109
109
{
110
110
struct dw_pcie *pci = &mp->pci;
111
+
struct resource *res;
111
112
112
-
pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
113
-
if (IS_ERR(pci->dbi_base))
114
-
return PTR_ERR(pci->dbi_base);
113
+
/*
114
+
* For the broken DTs that supply 'dbi' as 'elbi', parse the 'elbi'
115
+
* region and assign it to both 'pci->elbi_base' and 'pci->dbi_space' so
116
+
* that the DWC core can skip parsing both regions.
117
+
*/
118
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
119
+
if (res) {
120
+
pci->elbi_base = devm_pci_remap_cfg_resource(pci->dev, res);
121
+
if (IS_ERR(pci->elbi_base))
122
+
return PTR_ERR(pci->elbi_base);
123
+
124
+
pci->dbi_base = pci->elbi_base;
125
+
pci->dbi_phys_addr = res->start;
126
+
}
115
127
116
128
mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
117
129
if (IS_ERR(mp->cfg_base))
+1
drivers/pci/controller/dwc/pcie-designware-ep.c
+1
drivers/pci/controller/dwc/pcie-designware-ep.c
+12
drivers/pci/controller/dwc/pcie-designware-host.c
+12
drivers/pci/controller/dwc/pcie-designware-host.c
···
233
233
234
234
return 0;
235
235
}
236
+
EXPORT_SYMBOL_GPL(dw_pcie_allocate_domains);
236
237
237
238
void dw_pcie_free_msi(struct dw_pcie_rp *pp)
238
239
{
···
857
856
return pci->dbi_base + where;
858
857
}
859
858
859
+
static int dw_pcie_op_assert_perst(struct pci_bus *bus, bool assert)
860
+
{
861
+
struct dw_pcie_rp *pp = bus->sysdata;
862
+
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
863
+
864
+
return dw_pcie_assert_perst(pci, assert);
865
+
}
866
+
860
867
static struct pci_ops dw_pcie_ops = {
861
868
.map_bus = dw_pcie_own_conf_map_bus,
862
869
.read = pci_generic_config_read,
863
870
.write = pci_generic_config_write,
871
+
.assert_perst = dw_pcie_op_assert_perst,
864
872
};
865
873
866
874
static struct pci_ops dw_pcie_ecam_ops = {
···
1089
1079
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
1090
1080
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
1091
1081
dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
1082
+
1083
+
dw_pcie_hide_unsupported_l1ss(pci);
1092
1084
1093
1085
dw_pcie_config_presets(pp);
1094
1086
/*
+31
-5
drivers/pci/controller/dwc/pcie-designware.c
+31
-5
drivers/pci/controller/dwc/pcie-designware.c
···
168
168
}
169
169
170
170
/* ELBI is an optional resource */
171
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
172
-
if (res) {
173
-
pci->elbi_base = devm_ioremap_resource(pci->dev, res);
174
-
if (IS_ERR(pci->elbi_base))
175
-
return PTR_ERR(pci->elbi_base);
171
+
if (!pci->elbi_base) {
172
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
173
+
if (res) {
174
+
pci->elbi_base = devm_ioremap_resource(pci->dev, res);
175
+
if (IS_ERR(pci->elbi_base))
176
+
return PTR_ERR(pci->elbi_base);
177
+
}
176
178
}
177
179
178
180
/* LLDD is supposed to manually switch the clocks and resets state */
···
1081
1079
void dw_pcie_edma_remove(struct dw_pcie *pci)
1082
1080
{
1083
1081
dw_edma_remove(&pci->edma);
1082
+
}
1083
+
1084
+
void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci)
1085
+
{
1086
+
u16 l1ss;
1087
+
u32 l1ss_cap;
1088
+
1089
+
if (pci->l1ss_support)
1090
+
return;
1091
+
1092
+
l1ss = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);
1093
+
if (!l1ss)
1094
+
return;
1095
+
1096
+
/*
1097
+
* Unless the driver claims "l1ss_support", don't advertise L1 PM
1098
+
* Substates because they require CLKREQ# and possibly other
1099
+
* device-specific configuration.
1100
+
*/
1101
+
l1ss_cap = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP);
1102
+
l1ss_cap &= ~(PCI_L1SS_CAP_PCIPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_1 |
1103
+
PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2 |
1104
+
PCI_L1SS_CAP_L1_PM_SS);
1105
+
dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap);
1084
1106
}
1085
1107
1086
1108
void dw_pcie_setup(struct dw_pcie *pci)
+20
-1
drivers/pci/controller/dwc/pcie-designware.h
+20
-1
drivers/pci/controller/dwc/pcie-designware.h
···
97
97
#define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0)
98
98
99
99
#define PCIE_PORT_DEBUG0 0x728
100
-
#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
100
+
#define PORT_LOGIC_LTSSM_STATE_MASK 0x3f
101
101
#define PORT_LOGIC_LTSSM_STATE_L0 0x11
102
102
#define PCIE_PORT_DEBUG1 0x72C
103
103
#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
···
121
121
122
122
#define GEN3_RELATED_OFF 0x890
123
123
#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
124
+
#define GEN3_RELATED_OFF_EQ_PHASE_2_3 BIT(9)
124
125
#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)
125
126
#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
126
127
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
···
138
137
#define GEN3_EQ_FMDC_N_EVALS GENMASK(9, 5)
139
138
#define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA GENMASK(13, 10)
140
139
#define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA GENMASK(17, 14)
140
+
141
+
#define COHERENCY_CONTROL_1_OFF 0x8E0
142
+
#define CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK GENMASK(31, 2)
143
+
#define CFG_MEMTYPE_VALUE BIT(0)
144
+
145
+
#define COHERENCY_CONTROL_2_OFF 0x8E4
146
+
#define COHERENCY_CONTROL_3_OFF 0x8E8
141
147
142
148
#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
143
149
#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
···
493
485
enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie);
494
486
int (*start_link)(struct dw_pcie *pcie);
495
487
void (*stop_link)(struct dw_pcie *pcie);
488
+
int (*assert_perst)(struct dw_pcie *pcie, bool assert);
496
489
};
497
490
498
491
struct debugfs_info {
···
525
516
int max_link_speed;
526
517
u8 n_fts[2];
527
518
struct dw_edma_chip edma;
519
+
bool l1ss_support; /* L1 PM Substates support */
528
520
struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS];
529
521
struct clk_bulk_data core_clks[DW_PCIE_NUM_CORE_CLKS];
530
522
struct reset_control_bulk_data app_rsts[DW_PCIE_NUM_APP_RSTS];
···
583
573
int type, u64 parent_bus_addr,
584
574
u8 bar, size_t size);
585
575
void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index);
576
+
void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci);
586
577
void dw_pcie_setup(struct dw_pcie *pci);
587
578
void dw_pcie_iatu_detect(struct dw_pcie *pci);
588
579
int dw_pcie_edma_detect(struct dw_pcie *pci);
···
796
785
{
797
786
if (pci->ops && pci->ops->stop_link)
798
787
pci->ops->stop_link(pci);
788
+
}
789
+
790
+
static inline int dw_pcie_assert_perst(struct dw_pcie *pci, bool assert)
791
+
{
792
+
if (pci->ops && pci->ops->assert_perst)
793
+
return pci->ops->assert_perst(pci, assert);
794
+
795
+
return 0;
799
796
}
800
797
801
798
static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)
+46
-17
drivers/pci/controller/dwc/pcie-dw-rockchip.c
+46
-17
drivers/pci/controller/dwc/pcie-dw-rockchip.c
···
62
62
/* Interrupt Mask Register Related to Miscellaneous Operation */
63
63
#define PCIE_CLIENT_INTR_MASK_MISC 0x24
64
64
65
+
/* Power Management Control Register */
66
+
#define PCIE_CLIENT_POWER_CON 0x2c
67
+
#define PCIE_CLKREQ_READY FIELD_PREP_WM16(BIT(0), 1)
68
+
#define PCIE_CLKREQ_NOT_READY FIELD_PREP_WM16(BIT(0), 0)
69
+
#define PCIE_CLKREQ_PULL_DOWN FIELD_PREP_WM16(GENMASK(13, 12), 1)
70
+
65
71
/* Hot Reset Control Register */
66
72
#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
67
73
#define PCIE_LTSSM_APP_DLY2_EN BIT(1)
···
88
82
unsigned int clk_cnt;
89
83
struct reset_control *rst;
90
84
struct gpio_desc *rst_gpio;
91
-
struct regulator *vpcie3v3;
92
85
struct irq_domain *irq_domain;
93
86
const struct rockchip_pcie_of_data *data;
87
+
bool supports_clkreq;
94
88
};
95
89
96
90
struct rockchip_pcie_of_data {
···
206
200
return FIELD_GET(PCIE_LINKUP_MASK, val) == PCIE_LINKUP;
207
201
}
208
202
203
+
/*
204
+
* See e.g. section '11.6.6.4 L1 Substate' in the RK3588 TRM V1.0 for the steps
205
+
* needed to support L1 substates. Currently, just enable L1 substates for RC
206
+
* mode if CLKREQ# is properly connected and supports-clkreq is present in DT.
207
+
* For EP mode, there are more things should be done to actually save power in
208
+
* L1 substates, so disable L1 substates until there is proper support.
209
+
*/
210
+
static void rockchip_pcie_configure_l1ss(struct dw_pcie *pci)
211
+
{
212
+
struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
213
+
214
+
/* Enable L1 substates if CLKREQ# is properly connected */
215
+
if (rockchip->supports_clkreq) {
216
+
rockchip_pcie_writel_apb(rockchip, PCIE_CLKREQ_READY,
217
+
PCIE_CLIENT_POWER_CON);
218
+
pci->l1ss_support = true;
219
+
return;
220
+
}
221
+
222
+
/*
223
+
* Otherwise, assert CLKREQ# unconditionally. Since
224
+
* pci->l1ss_support is not set, the DWC core will prevent L1
225
+
* Substates support from being advertised.
226
+
*/
227
+
rockchip_pcie_writel_apb(rockchip,
228
+
PCIE_CLKREQ_PULL_DOWN | PCIE_CLKREQ_NOT_READY,
229
+
PCIE_CLIENT_POWER_CON);
230
+
}
231
+
209
232
static void rockchip_pcie_enable_l0s(struct dw_pcie *pci)
210
233
{
211
234
u32 cap, lnkcap;
···
299
264
irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler,
300
265
rockchip);
301
266
267
+
rockchip_pcie_configure_l1ss(pci);
302
268
rockchip_pcie_enable_l0s(pci);
303
269
304
270
return 0;
···
447
411
if (IS_ERR(rockchip->rst))
448
412
return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
449
413
"failed to get reset lines\n");
414
+
415
+
rockchip->supports_clkreq = of_property_read_bool(pdev->dev.of_node,
416
+
"supports-clkreq");
450
417
451
418
return 0;
452
419
}
···
691
652
return ret;
692
653
693
654
/* DON'T MOVE ME: must be enable before PHY init */
694
-
rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
695
-
if (IS_ERR(rockchip->vpcie3v3)) {
696
-
if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
697
-
return dev_err_probe(dev, PTR_ERR(rockchip->vpcie3v3),
698
-
"failed to get vpcie3v3 regulator\n");
699
-
rockchip->vpcie3v3 = NULL;
700
-
} else {
701
-
ret = regulator_enable(rockchip->vpcie3v3);
702
-
if (ret)
703
-
return dev_err_probe(dev, ret,
704
-
"failed to enable vpcie3v3 regulator\n");
705
-
}
655
+
ret = devm_regulator_get_enable_optional(dev, "vpcie3v3");
656
+
if (ret < 0 && ret != -ENODEV)
657
+
return dev_err_probe(dev, ret,
658
+
"failed to enable vpcie3v3 regulator\n");
706
659
707
660
ret = rockchip_pcie_phy_init(rockchip);
708
661
if (ret)
709
-
goto disable_regulator;
662
+
return dev_err_probe(dev, ret,
663
+
"failed to initialize the phy\n");
710
664
711
665
ret = reset_control_deassert(rockchip->rst);
712
666
if (ret)
···
732
700
clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
733
701
deinit_phy:
734
702
rockchip_pcie_phy_deinit(rockchip);
735
-
disable_regulator:
736
-
if (rockchip->vpcie3v3)
737
-
regulator_disable(rockchip->vpcie3v3);
738
703
739
704
return ret;
740
705
}
+406
drivers/pci/controller/dwc/pcie-nxp-s32g.c
+406
drivers/pci/controller/dwc/pcie-nxp-s32g.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* PCIe host controller driver for NXP S32G SoCs
4
+
*
5
+
* Copyright 2019-2025 NXP
6
+
*/
7
+
8
+
#include <linux/interrupt.h>
9
+
#include <linux/io.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of_device.h>
12
+
#include <linux/of_address.h>
13
+
#include <linux/pci.h>
14
+
#include <linux/phy/phy.h>
15
+
#include <linux/platform_device.h>
16
+
#include <linux/pm_runtime.h>
17
+
#include <linux/sizes.h>
18
+
#include <linux/types.h>
19
+
20
+
#include "pcie-designware.h"
21
+
22
+
/* PCIe controller Sub-System */
23
+
24
+
/* PCIe controller 0 General Control 1 */
25
+
#define PCIE_S32G_PE0_GEN_CTRL_1 0x50
26
+
#define DEVICE_TYPE_MASK GENMASK(3, 0)
27
+
#define SRIS_MODE BIT(8)
28
+
29
+
/* PCIe controller 0 General Control 3 */
30
+
#define PCIE_S32G_PE0_GEN_CTRL_3 0x58
31
+
#define LTSSM_EN BIT(0)
32
+
33
+
/* PCIe Controller 0 Interrupt Status */
34
+
#define PCIE_S32G_PE0_INT_STS 0xE8
35
+
#define HP_INT_STS BIT(6)
36
+
37
+
/* Boundary between peripheral space and physical memory space */
38
+
#define S32G_MEMORY_BOUNDARY_ADDR 0x80000000
39
+
40
+
struct s32g_pcie_port {
41
+
struct list_head list;
42
+
struct phy *phy;
43
+
};
44
+
45
+
struct s32g_pcie {
46
+
struct dw_pcie pci;
47
+
void __iomem *ctrl_base;
48
+
struct list_head ports;
49
+
};
50
+
51
+
#define to_s32g_from_dw_pcie(x) \
52
+
container_of(x, struct s32g_pcie, pci)
53
+
54
+
static void s32g_pcie_writel_ctrl(struct s32g_pcie *s32g_pp, u32 reg, u32 val)
55
+
{
56
+
writel(val, s32g_pp->ctrl_base + reg);
57
+
}
58
+
59
+
static u32 s32g_pcie_readl_ctrl(struct s32g_pcie *s32g_pp, u32 reg)
60
+
{
61
+
return readl(s32g_pp->ctrl_base + reg);
62
+
}
63
+
64
+
static void s32g_pcie_enable_ltssm(struct s32g_pcie *s32g_pp)
65
+
{
66
+
u32 reg;
67
+
68
+
reg = s32g_pcie_readl_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_3);
69
+
reg |= LTSSM_EN;
70
+
s32g_pcie_writel_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_3, reg);
71
+
}
72
+
73
+
static void s32g_pcie_disable_ltssm(struct s32g_pcie *s32g_pp)
74
+
{
75
+
u32 reg;
76
+
77
+
reg = s32g_pcie_readl_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_3);
78
+
reg &= ~LTSSM_EN;
79
+
s32g_pcie_writel_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_3, reg);
80
+
}
81
+
82
+
static int s32g_pcie_start_link(struct dw_pcie *pci)
83
+
{
84
+
struct s32g_pcie *s32g_pp = to_s32g_from_dw_pcie(pci);
85
+
86
+
s32g_pcie_enable_ltssm(s32g_pp);
87
+
88
+
return 0;
89
+
}
90
+
91
+
static void s32g_pcie_stop_link(struct dw_pcie *pci)
92
+
{
93
+
struct s32g_pcie *s32g_pp = to_s32g_from_dw_pcie(pci);
94
+
95
+
s32g_pcie_disable_ltssm(s32g_pp);
96
+
}
97
+
98
+
static struct dw_pcie_ops s32g_pcie_ops = {
99
+
.start_link = s32g_pcie_start_link,
100
+
.stop_link = s32g_pcie_stop_link,
101
+
};
102
+
103
+
/* Configure the AMBA AXI Coherency Extensions (ACE) interface */
104
+
static void s32g_pcie_reset_mstr_ace(struct dw_pcie *pci)
105
+
{
106
+
u32 ddr_base_low = lower_32_bits(S32G_MEMORY_BOUNDARY_ADDR);
107
+
u32 ddr_base_high = upper_32_bits(S32G_MEMORY_BOUNDARY_ADDR);
108
+
109
+
dw_pcie_dbi_ro_wr_en(pci);
110
+
dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_3_OFF, 0x0);
111
+
112
+
/*
113
+
* Ncore is a cache-coherent interconnect module that enables the
114
+
* integration of heterogeneous coherent and non-coherent agents in
115
+
* the chip. Ncore transactions to peripheral should be non-coherent
116
+
* or it might drop them.
117
+
*
118
+
* One example where this is needed are PCIe MSIs, which use NoSnoop=0
119
+
* and might end up routed to Ncore. PCIe coherent traffic (e.g. MSIs)
120
+
* that targets peripheral space will be dropped by Ncore because
121
+
* peripherals on S32G are not coherent as slaves. We add a hard
122
+
* boundary in the PCIe controller coherency control registers to
123
+
* separate physical memory space from peripheral space.
124
+
*
125
+
* Define the start of DDR as seen by Linux as this boundary between
126
+
* "memory" and "peripherals", with peripherals being below.
127
+
*/
128
+
dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_1_OFF,
129
+
(ddr_base_low & CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK));
130
+
dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_2_OFF, ddr_base_high);
131
+
dw_pcie_dbi_ro_wr_dis(pci);
132
+
}
133
+
134
+
static int s32g_init_pcie_controller(struct dw_pcie_rp *pp)
135
+
{
136
+
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
137
+
struct s32g_pcie *s32g_pp = to_s32g_from_dw_pcie(pci);
138
+
u32 val;
139
+
140
+
/* Set RP mode */
141
+
val = s32g_pcie_readl_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_1);
142
+
val &= ~DEVICE_TYPE_MASK;
143
+
val |= FIELD_PREP(DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
144
+
145
+
/* Use default CRNS */
146
+
val &= ~SRIS_MODE;
147
+
148
+
s32g_pcie_writel_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_1, val);
149
+
150
+
/*
151
+
* Make sure we use the coherency defaults (just in case the settings
152
+
* have been changed from their reset values)
153
+
*/
154
+
s32g_pcie_reset_mstr_ace(pci);
155
+
156
+
dw_pcie_dbi_ro_wr_en(pci);
157
+
158
+
val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
159
+
val |= PORT_FORCE_DO_DESKEW_FOR_SRIS;
160
+
dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
161
+
162
+
val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
163
+
val |= GEN3_RELATED_OFF_EQ_PHASE_2_3;
164
+
dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
165
+
166
+
dw_pcie_dbi_ro_wr_dis(pci);
167
+
168
+
return 0;
169
+
}
170
+
171
+
static const struct dw_pcie_host_ops s32g_pcie_host_ops = {
172
+
.init = s32g_init_pcie_controller,
173
+
};
174
+
175
+
static int s32g_init_pcie_phy(struct s32g_pcie *s32g_pp)
176
+
{
177
+
struct dw_pcie *pci = &s32g_pp->pci;
178
+
struct device *dev = pci->dev;
179
+
struct s32g_pcie_port *port, *tmp;
180
+
int ret;
181
+
182
+
list_for_each_entry(port, &s32g_pp->ports, list) {
183
+
ret = phy_init(port->phy);
184
+
if (ret) {
185
+
dev_err(dev, "Failed to init serdes PHY\n");
186
+
goto err_phy_revert;
187
+
}
188
+
189
+
ret = phy_set_mode_ext(port->phy, PHY_MODE_PCIE, 0);
190
+
if (ret) {
191
+
dev_err(dev, "Failed to set mode on serdes PHY\n");
192
+
goto err_phy_exit;
193
+
}
194
+
195
+
ret = phy_power_on(port->phy);
196
+
if (ret) {
197
+
dev_err(dev, "Failed to power on serdes PHY\n");
198
+
goto err_phy_exit;
199
+
}
200
+
}
201
+
202
+
return 0;
203
+
204
+
err_phy_exit:
205
+
phy_exit(port->phy);
206
+
207
+
err_phy_revert:
208
+
list_for_each_entry_continue_reverse(port, &s32g_pp->ports, list) {
209
+
phy_power_off(port->phy);
210
+
phy_exit(port->phy);
211
+
}
212
+
213
+
list_for_each_entry_safe(port, tmp, &s32g_pp->ports, list)
214
+
list_del(&port->list);
215
+
216
+
return ret;
217
+
}
218
+
219
+
static void s32g_deinit_pcie_phy(struct s32g_pcie *s32g_pp)
220
+
{
221
+
struct s32g_pcie_port *port, *tmp;
222
+
223
+
list_for_each_entry_safe(port, tmp, &s32g_pp->ports, list) {
224
+
phy_power_off(port->phy);
225
+
phy_exit(port->phy);
226
+
list_del(&port->list);
227
+
}
228
+
}
229
+
230
+
static int s32g_pcie_init(struct device *dev, struct s32g_pcie *s32g_pp)
231
+
{
232
+
s32g_pcie_disable_ltssm(s32g_pp);
233
+
234
+
return s32g_init_pcie_phy(s32g_pp);
235
+
}
236
+
237
+
static void s32g_pcie_deinit(struct s32g_pcie *s32g_pp)
238
+
{
239
+
s32g_pcie_disable_ltssm(s32g_pp);
240
+
241
+
s32g_deinit_pcie_phy(s32g_pp);
242
+
}
243
+
244
+
static int s32g_pcie_parse_port(struct s32g_pcie *s32g_pp, struct device_node *node)
245
+
{
246
+
struct device *dev = s32g_pp->pci.dev;
247
+
struct s32g_pcie_port *port;
248
+
int num_lanes;
249
+
250
+
port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
251
+
if (!port)
252
+
return -ENOMEM;
253
+
254
+
port->phy = devm_of_phy_get(dev, node, NULL);
255
+
if (IS_ERR(port->phy))
256
+
return dev_err_probe(dev, PTR_ERR(port->phy),
257
+
"Failed to get serdes PHY\n");
258
+
259
+
INIT_LIST_HEAD(&port->list);
260
+
list_add_tail(&port->list, &s32g_pp->ports);
261
+
262
+
/*
263
+
* The DWC core initialization code cannot yet parse the num-lanes
264
+
* attribute in the Root Port node. The S32G only supports one Root
265
+
* Port for now so its driver can parse the node and set the num_lanes
266
+
* field of struct dwc_pcie before calling dw_pcie_host_init().
267
+
*/
268
+
if (!of_property_read_u32(node, "num-lanes", &num_lanes))
269
+
s32g_pp->pci.num_lanes = num_lanes;
270
+
271
+
return 0;
272
+
}
273
+
274
+
static int s32g_pcie_parse_ports(struct device *dev, struct s32g_pcie *s32g_pp)
275
+
{
276
+
struct s32g_pcie_port *port, *tmp;
277
+
int ret = -ENOENT;
278
+
279
+
for_each_available_child_of_node_scoped(dev->of_node, of_port) {
280
+
if (!of_node_is_type(of_port, "pci"))
281
+
continue;
282
+
283
+
ret = s32g_pcie_parse_port(s32g_pp, of_port);
284
+
if (ret)
285
+
goto err_port;
286
+
}
287
+
288
+
err_port:
289
+
list_for_each_entry_safe(port, tmp, &s32g_pp->ports, list)
290
+
list_del(&port->list);
291
+
292
+
return ret;
293
+
}
294
+
295
+
static int s32g_pcie_get_resources(struct platform_device *pdev,
296
+
struct s32g_pcie *s32g_pp)
297
+
{
298
+
struct dw_pcie *pci = &s32g_pp->pci;
299
+
struct device *dev = &pdev->dev;
300
+
int ret;
301
+
302
+
pci->dev = dev;
303
+
pci->ops = &s32g_pcie_ops;
304
+
305
+
s32g_pp->ctrl_base = devm_platform_ioremap_resource_byname(pdev, "ctrl");
306
+
if (IS_ERR(s32g_pp->ctrl_base))
307
+
return PTR_ERR(s32g_pp->ctrl_base);
308
+
309
+
INIT_LIST_HEAD(&s32g_pp->ports);
310
+
311
+
ret = s32g_pcie_parse_ports(dev, s32g_pp);
312
+
if (ret)
313
+
return dev_err_probe(dev, ret,
314
+
"Failed to parse Root Port: %d\n", ret);
315
+
316
+
platform_set_drvdata(pdev, s32g_pp);
317
+
318
+
return 0;
319
+
}
320
+
321
+
static int s32g_pcie_probe(struct platform_device *pdev)
322
+
{
323
+
struct device *dev = &pdev->dev;
324
+
struct s32g_pcie *s32g_pp;
325
+
struct dw_pcie_rp *pp;
326
+
int ret;
327
+
328
+
s32g_pp = devm_kzalloc(dev, sizeof(*s32g_pp), GFP_KERNEL);
329
+
if (!s32g_pp)
330
+
return -ENOMEM;
331
+
332
+
ret = s32g_pcie_get_resources(pdev, s32g_pp);
333
+
if (ret)
334
+
return ret;
335
+
336
+
pm_runtime_no_callbacks(dev);
337
+
devm_pm_runtime_enable(dev);
338
+
ret = pm_runtime_get_sync(dev);
339
+
if (ret < 0)
340
+
goto err_pm_runtime_put;
341
+
342
+
ret = s32g_pcie_init(dev, s32g_pp);
343
+
if (ret)
344
+
goto err_pm_runtime_put;
345
+
346
+
pp = &s32g_pp->pci.pp;
347
+
pp->ops = &s32g_pcie_host_ops;
348
+
pp->use_atu_msg = true;
349
+
350
+
ret = dw_pcie_host_init(pp);
351
+
if (ret)
352
+
goto err_pcie_deinit;
353
+
354
+
return 0;
355
+
356
+
err_pcie_deinit:
357
+
s32g_pcie_deinit(s32g_pp);
358
+
err_pm_runtime_put:
359
+
pm_runtime_put(dev);
360
+
361
+
return ret;
362
+
}
363
+
364
+
static int s32g_pcie_suspend_noirq(struct device *dev)
365
+
{
366
+
struct s32g_pcie *s32g_pp = dev_get_drvdata(dev);
367
+
struct dw_pcie *pci = &s32g_pp->pci;
368
+
369
+
return dw_pcie_suspend_noirq(pci);
370
+
}
371
+
372
+
static int s32g_pcie_resume_noirq(struct device *dev)
373
+
{
374
+
struct s32g_pcie *s32g_pp = dev_get_drvdata(dev);
375
+
struct dw_pcie *pci = &s32g_pp->pci;
376
+
377
+
return dw_pcie_resume_noirq(pci);
378
+
}
379
+
380
+
static const struct dev_pm_ops s32g_pcie_pm_ops = {
381
+
NOIRQ_SYSTEM_SLEEP_PM_OPS(s32g_pcie_suspend_noirq,
382
+
s32g_pcie_resume_noirq)
383
+
};
384
+
385
+
static const struct of_device_id s32g_pcie_of_match[] = {
386
+
{ .compatible = "nxp,s32g2-pcie" },
387
+
{ /* sentinel */ },
388
+
};
389
+
MODULE_DEVICE_TABLE(of, s32g_pcie_of_match);
390
+
391
+
static struct platform_driver s32g_pcie_driver = {
392
+
.driver = {
393
+
.name = "s32g-pcie",
394
+
.of_match_table = s32g_pcie_of_match,
395
+
.suppress_bind_attrs = true,
396
+
.pm = pm_sleep_ptr(&s32g_pcie_pm_ops),
397
+
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
398
+
},
399
+
.probe = s32g_pcie_probe,
400
+
};
401
+
402
+
builtin_platform_driver(s32g_pcie_driver);
403
+
404
+
MODULE_AUTHOR("Ionut Vicovan <Ionut.Vicovan@nxp.com>");
405
+
MODULE_DESCRIPTION("NXP S32G PCIe Host controller driver");
406
+
MODULE_LICENSE("GPL");
+30
-2
drivers/pci/controller/dwc/pcie-qcom.c
+30
-2
drivers/pci/controller/dwc/pcie-qcom.c
···
641
641
return 0;
642
642
}
643
643
644
+
static int qcom_pcie_assert_perst(struct dw_pcie *pci, bool assert)
645
+
{
646
+
struct qcom_pcie *pcie = to_qcom_pcie(pci);
647
+
648
+
if (assert)
649
+
qcom_ep_reset_assert(pcie);
650
+
else
651
+
qcom_ep_reset_deassert(pcie);
652
+
653
+
return 0;
654
+
}
655
+
644
656
static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
645
657
{
646
658
u32 val;
···
1023
1011
val = readl(pcie->parf + PARF_PM_CTRL);
1024
1012
val &= ~REQ_NOT_ENTR_L1;
1025
1013
writel(val, pcie->parf + PARF_PM_CTRL);
1014
+
1015
+
pci->l1ss_support = true;
1026
1016
1027
1017
val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
1028
1018
val |= EN;
···
1494
1480
static const struct dw_pcie_ops dw_pcie_ops = {
1495
1481
.link_up = qcom_pcie_link_up,
1496
1482
.start_link = qcom_pcie_start_link,
1483
+
.assert_perst = qcom_pcie_assert_perst,
1497
1484
};
1498
1485
1499
1486
static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
···
1544
1529
{
1545
1530
u32 offset, status, width, speed;
1546
1531
struct dw_pcie *pci = pcie->pci;
1532
+
struct dev_pm_opp_key key = {};
1547
1533
unsigned long freq_kbps;
1548
1534
struct dev_pm_opp *opp;
1549
1535
int ret, freq_mbps;
···
1572
1556
return;
1573
1557
1574
1558
freq_kbps = freq_mbps * KILO;
1575
-
opp = dev_pm_opp_find_freq_exact(pci->dev, freq_kbps * width,
1576
-
true);
1559
+
opp = dev_pm_opp_find_level_exact(pci->dev, speed);
1560
+
if (IS_ERR(opp)) {
1561
+
/* opp-level is not defined use only frequency */
1562
+
opp = dev_pm_opp_find_freq_exact(pci->dev, freq_kbps * width,
1563
+
true);
1564
+
} else {
1565
+
/* put opp-level OPP */
1566
+
dev_pm_opp_put(opp);
1567
+
1568
+
key.freq = freq_kbps * width;
1569
+
key.level = speed;
1570
+
key.bw = 0;
1571
+
opp = dev_pm_opp_find_key_exact(pci->dev, &key, true);
1572
+
}
1577
1573
if (!IS_ERR(opp)) {
1578
1574
ret = dev_pm_opp_set_opp(pci->dev, opp);
1579
1575
if (ret)
+357
drivers/pci/controller/dwc/pcie-spacemit-k1.c
+357
drivers/pci/controller/dwc/pcie-spacemit-k1.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* SpacemiT K1 PCIe host driver
4
+
*
5
+
* Copyright (C) 2025 by RISCstar Solutions Corporation. All rights reserved.
6
+
* Copyright (c) 2023, spacemit Corporation.
7
+
*/
8
+
9
+
#include <linux/clk.h>
10
+
#include <linux/delay.h>
11
+
#include <linux/device.h>
12
+
#include <linux/err.h>
13
+
#include <linux/gfp.h>
14
+
#include <linux/mfd/syscon.h>
15
+
#include <linux/mod_devicetable.h>
16
+
#include <linux/phy/phy.h>
17
+
#include <linux/platform_device.h>
18
+
#include <linux/regmap.h>
19
+
#include <linux/reset.h>
20
+
#include <linux/types.h>
21
+
22
+
#include "pcie-designware.h"
23
+
24
+
#define PCI_VENDOR_ID_SPACEMIT 0x201f
25
+
#define PCI_DEVICE_ID_SPACEMIT_K1 0x0001
26
+
27
+
/* Offsets and field definitions for link management registers */
28
+
#define K1_PHY_AHB_IRQ_EN 0x0000
29
+
#define PCIE_INTERRUPT_EN BIT(0)
30
+
31
+
#define K1_PHY_AHB_LINK_STS 0x0004
32
+
#define SMLH_LINK_UP BIT(1)
33
+
#define RDLH_LINK_UP BIT(12)
34
+
35
+
#define INTR_ENABLE 0x0014
36
+
#define MSI_CTRL_INT BIT(11)
37
+
38
+
/* Some controls require APMU regmap access */
39
+
#define SYSCON_APMU "spacemit,apmu"
40
+
41
+
/* Offsets and field definitions for APMU registers */
42
+
#define PCIE_CLK_RESET_CONTROL 0x0000
43
+
#define LTSSM_EN BIT(6)
44
+
#define PCIE_AUX_PWR_DET BIT(9)
45
+
#define PCIE_RC_PERST BIT(12) /* 1: assert PERST# */
46
+
#define APP_HOLD_PHY_RST BIT(30)
47
+
#define DEVICE_TYPE_RC BIT(31) /* 0: endpoint; 1: RC */
48
+
49
+
#define PCIE_CONTROL_LOGIC 0x0004
50
+
#define PCIE_SOFT_RESET BIT(0)
51
+
52
+
struct k1_pcie {
53
+
struct dw_pcie pci;
54
+
struct phy *phy;
55
+
void __iomem *link;
56
+
struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */
57
+
u32 pmu_off;
58
+
};
59
+
60
+
#define to_k1_pcie(dw_pcie) \
61
+
platform_get_drvdata(to_platform_device((dw_pcie)->dev))
62
+
63
+
static void k1_pcie_toggle_soft_reset(struct k1_pcie *k1)
64
+
{
65
+
u32 offset;
66
+
u32 val;
67
+
68
+
/*
69
+
* Write, then read back to guarantee it has reached the device
70
+
* before we start the delay.
71
+
*/
72
+
offset = k1->pmu_off + PCIE_CONTROL_LOGIC;
73
+
regmap_set_bits(k1->pmu, offset, PCIE_SOFT_RESET);
74
+
regmap_read(k1->pmu, offset, &val);
75
+
76
+
mdelay(2);
77
+
78
+
regmap_clear_bits(k1->pmu, offset, PCIE_SOFT_RESET);
79
+
}
80
+
81
+
/* Enable app clocks, deassert resets */
82
+
static int k1_pcie_enable_resources(struct k1_pcie *k1)
83
+
{
84
+
struct dw_pcie *pci = &k1->pci;
85
+
int ret;
86
+
87
+
ret = clk_bulk_prepare_enable(ARRAY_SIZE(pci->app_clks), pci->app_clks);
88
+
if (ret)
89
+
return ret;
90
+
91
+
ret = reset_control_bulk_deassert(ARRAY_SIZE(pci->app_rsts),
92
+
pci->app_rsts);
93
+
if (ret)
94
+
goto err_disable_clks;
95
+
96
+
return 0;
97
+
98
+
err_disable_clks:
99
+
clk_bulk_disable_unprepare(ARRAY_SIZE(pci->app_clks), pci->app_clks);
100
+
101
+
return ret;
102
+
}
103
+
104
+
/* Assert resets, disable app clocks */
105
+
static void k1_pcie_disable_resources(struct k1_pcie *k1)
106
+
{
107
+
struct dw_pcie *pci = &k1->pci;
108
+
109
+
reset_control_bulk_assert(ARRAY_SIZE(pci->app_rsts), pci->app_rsts);
110
+
clk_bulk_disable_unprepare(ARRAY_SIZE(pci->app_clks), pci->app_clks);
111
+
}
112
+
113
+
/* FIXME: Disable ASPM L1 to avoid errors reported on some NVMe drives */
114
+
static void k1_pcie_disable_aspm_l1(struct k1_pcie *k1)
115
+
{
116
+
struct dw_pcie *pci = &k1->pci;
117
+
u8 offset;
118
+
u32 val;
119
+
120
+
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
121
+
offset += PCI_EXP_LNKCAP;
122
+
123
+
dw_pcie_dbi_ro_wr_en(pci);
124
+
val = dw_pcie_readl_dbi(pci, offset);
125
+
val &= ~PCI_EXP_LNKCAP_ASPM_L1;
126
+
dw_pcie_writel_dbi(pci, offset, val);
127
+
dw_pcie_dbi_ro_wr_dis(pci);
128
+
}
129
+
130
+
static int k1_pcie_init(struct dw_pcie_rp *pp)
131
+
{
132
+
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
133
+
struct k1_pcie *k1 = to_k1_pcie(pci);
134
+
u32 reset_ctrl;
135
+
u32 val;
136
+
int ret;
137
+
138
+
k1_pcie_toggle_soft_reset(k1);
139
+
140
+
ret = k1_pcie_enable_resources(k1);
141
+
if (ret)
142
+
return ret;
143
+
144
+
/* Set the PCI vendor and device ID */
145
+
dw_pcie_dbi_ro_wr_en(pci);
146
+
dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT);
147
+
dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_SPACEMIT_K1);
148
+
dw_pcie_dbi_ro_wr_dis(pci);
149
+
150
+
/*
151
+
* Start by asserting fundamental reset (drive PERST# low). The
152
+
* PCI CEM spec says that PERST# should be deasserted at least
153
+
* 100ms after the power becomes stable, so we'll insert that
154
+
* delay first. Write, then read it back to guarantee the write
155
+
* reaches the device before we start the delay.
156
+
*/
157
+
reset_ctrl = k1->pmu_off + PCIE_CLK_RESET_CONTROL;
158
+
regmap_set_bits(k1->pmu, reset_ctrl, PCIE_RC_PERST);
159
+
regmap_read(k1->pmu, reset_ctrl, &val);
160
+
mdelay(PCIE_T_PVPERL_MS);
161
+
162
+
/*
163
+
* Put the controller in root complex mode, and indicate that
164
+
* Vaux (3.3v) is present.
165
+
*/
166
+
regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET);
167
+
168
+
ret = phy_init(k1->phy);
169
+
if (ret) {
170
+
k1_pcie_disable_resources(k1);
171
+
172
+
return ret;
173
+
}
174
+
175
+
/* Deassert fundamental reset (drive PERST# high) */
176
+
regmap_clear_bits(k1->pmu, reset_ctrl, PCIE_RC_PERST);
177
+
178
+
/* Finally, as a workaround, disable ASPM L1 */
179
+
k1_pcie_disable_aspm_l1(k1);
180
+
181
+
return 0;
182
+
}
183
+
184
+
static void k1_pcie_deinit(struct dw_pcie_rp *pp)
185
+
{
186
+
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
187
+
struct k1_pcie *k1 = to_k1_pcie(pci);
188
+
189
+
/* Assert fundamental reset (drive PERST# low) */
190
+
regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL,
191
+
PCIE_RC_PERST);
192
+
193
+
phy_exit(k1->phy);
194
+
195
+
k1_pcie_disable_resources(k1);
196
+
}
197
+
198
+
static const struct dw_pcie_host_ops k1_pcie_host_ops = {
199
+
.init = k1_pcie_init,
200
+
.deinit = k1_pcie_deinit,
201
+
};
202
+
203
+
static bool k1_pcie_link_up(struct dw_pcie *pci)
204
+
{
205
+
struct k1_pcie *k1 = to_k1_pcie(pci);
206
+
u32 val;
207
+
208
+
val = readl_relaxed(k1->link + K1_PHY_AHB_LINK_STS);
209
+
210
+
return (val & RDLH_LINK_UP) && (val & SMLH_LINK_UP);
211
+
}
212
+
213
+
static int k1_pcie_start_link(struct dw_pcie *pci)
214
+
{
215
+
struct k1_pcie *k1 = to_k1_pcie(pci);
216
+
u32 val;
217
+
218
+
/* Stop holding the PHY in reset, and enable link training */
219
+
regmap_update_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL,
220
+
APP_HOLD_PHY_RST | LTSSM_EN, LTSSM_EN);
221
+
222
+
/* Enable the MSI interrupt */
223
+
writel_relaxed(MSI_CTRL_INT, k1->link + INTR_ENABLE);
224
+
225
+
/* Top-level interrupt enable */
226
+
val = readl_relaxed(k1->link + K1_PHY_AHB_IRQ_EN);
227
+
val |= PCIE_INTERRUPT_EN;
228
+
writel_relaxed(val, k1->link + K1_PHY_AHB_IRQ_EN);
229
+
230
+
return 0;
231
+
}
232
+
233
+
static void k1_pcie_stop_link(struct dw_pcie *pci)
234
+
{
235
+
struct k1_pcie *k1 = to_k1_pcie(pci);
236
+
u32 val;
237
+
238
+
/* Disable interrupts */
239
+
val = readl_relaxed(k1->link + K1_PHY_AHB_IRQ_EN);
240
+
val &= ~PCIE_INTERRUPT_EN;
241
+
writel_relaxed(val, k1->link + K1_PHY_AHB_IRQ_EN);
242
+
243
+
writel_relaxed(0, k1->link + INTR_ENABLE);
244
+
245
+
/* Disable the link and hold the PHY in reset */
246
+
regmap_update_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL,
247
+
APP_HOLD_PHY_RST | LTSSM_EN, APP_HOLD_PHY_RST);
248
+
}
249
+
250
+
static const struct dw_pcie_ops k1_pcie_ops = {
251
+
.link_up = k1_pcie_link_up,
252
+
.start_link = k1_pcie_start_link,
253
+
.stop_link = k1_pcie_stop_link,
254
+
};
255
+
256
+
static int k1_pcie_parse_port(struct k1_pcie *k1)
257
+
{
258
+
struct device *dev = k1->pci.dev;
259
+
struct device_node *root_port;
260
+
struct phy *phy;
261
+
262
+
/* We assume only one root port */
263
+
root_port = of_get_next_available_child(dev_of_node(dev), NULL);
264
+
if (!root_port)
265
+
return -EINVAL;
266
+
267
+
phy = devm_of_phy_get(dev, root_port, NULL);
268
+
269
+
of_node_put(root_port);
270
+
271
+
if (IS_ERR(phy))
272
+
return PTR_ERR(phy);
273
+
274
+
k1->phy = phy;
275
+
276
+
return 0;
277
+
}
278
+
279
+
static int k1_pcie_probe(struct platform_device *pdev)
280
+
{
281
+
struct device *dev = &pdev->dev;
282
+
struct k1_pcie *k1;
283
+
int ret;
284
+
285
+
k1 = devm_kzalloc(dev, sizeof(*k1), GFP_KERNEL);
286
+
if (!k1)
287
+
return -ENOMEM;
288
+
289
+
k1->pmu = syscon_regmap_lookup_by_phandle_args(dev_of_node(dev),
290
+
SYSCON_APMU, 1,
291
+
&k1->pmu_off);
292
+
if (IS_ERR(k1->pmu))
293
+
return dev_err_probe(dev, PTR_ERR(k1->pmu),
294
+
"failed to lookup PMU registers\n");
295
+
296
+
k1->link = devm_platform_ioremap_resource_byname(pdev, "link");
297
+
if (IS_ERR(k1->link))
298
+
return dev_err_probe(dev, PTR_ERR(k1->link),
299
+
"failed to map \"link\" registers\n");
300
+
301
+
k1->pci.dev = dev;
302
+
k1->pci.ops = &k1_pcie_ops;
303
+
k1->pci.pp.num_vectors = MAX_MSI_IRQS;
304
+
dw_pcie_cap_set(&k1->pci, REQ_RES);
305
+
306
+
k1->pci.pp.ops = &k1_pcie_host_ops;
307
+
308
+
/* Hold the PHY in reset until we start the link */
309
+
regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL,
310
+
APP_HOLD_PHY_RST);
311
+
312
+
ret = devm_regulator_get_enable(dev, "vpcie3v3");
313
+
if (ret)
314
+
return dev_err_probe(dev, ret,
315
+
"failed to get \"vpcie3v3\" supply\n");
316
+
317
+
pm_runtime_set_active(dev);
318
+
pm_runtime_no_callbacks(dev);
319
+
devm_pm_runtime_enable(dev);
320
+
321
+
platform_set_drvdata(pdev, k1);
322
+
323
+
ret = k1_pcie_parse_port(k1);
324
+
if (ret)
325
+
return dev_err_probe(dev, ret, "failed to parse root port\n");
326
+
327
+
ret = dw_pcie_host_init(&k1->pci.pp);
328
+
if (ret)
329
+
return dev_err_probe(dev, ret, "failed to initialize host\n");
330
+
331
+
return 0;
332
+
}
333
+
334
+
static void k1_pcie_remove(struct platform_device *pdev)
335
+
{
336
+
struct k1_pcie *k1 = platform_get_drvdata(pdev);
337
+
338
+
dw_pcie_host_deinit(&k1->pci.pp);
339
+
}
340
+
341
+
static const struct of_device_id k1_pcie_of_match_table[] = {
342
+
{ .compatible = "spacemit,k1-pcie", },
343
+
{ }
344
+
};
345
+
346
+
static struct platform_driver k1_pcie_driver = {
347
+
.probe = k1_pcie_probe,
348
+
.remove = k1_pcie_remove,
349
+
.driver = {
350
+
.name = "spacemit-k1-pcie",
351
+
.of_match_table = k1_pcie_of_match_table,
352
+
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
353
+
},
354
+
};
355
+
module_platform_driver(k1_pcie_driver);
356
+
MODULE_LICENSE("GPL");
357
+
MODULE_DESCRIPTION("SpacemiT K1 PCIe host driver");
+11
-32
drivers/pci/controller/dwc/pcie-stm32-ep.c
+11
-32
drivers/pci/controller/dwc/pcie-stm32-ep.c
···
7
7
*/
8
8
9
9
#include <linux/clk.h>
10
+
#include <linux/gpio/consumer.h>
10
11
#include <linux/mfd/syscon.h>
11
12
#include <linux/of_platform.h>
12
-
#include <linux/of_gpio.h>
13
13
#include <linux/phy/phy.h>
14
14
#include <linux/platform_device.h>
15
15
#include <linux/pm_runtime.h>
···
37
37
dw_pcie_ep_reset_bar(pci, bar);
38
38
}
39
39
40
-
static int stm32_pcie_enable_link(struct dw_pcie *pci)
41
-
{
42
-
struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci);
43
-
44
-
regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR,
45
-
STM32MP25_PCIECR_LTSSM_EN,
46
-
STM32MP25_PCIECR_LTSSM_EN);
47
-
48
-
return dw_pcie_wait_for_link(pci);
49
-
}
50
-
51
-
static void stm32_pcie_disable_link(struct dw_pcie *pci)
52
-
{
53
-
struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci);
54
-
55
-
regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, STM32MP25_PCIECR_LTSSM_EN, 0);
56
-
}
57
-
58
40
static int stm32_pcie_start_link(struct dw_pcie *pci)
59
41
{
60
42
struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci);
61
-
int ret;
62
-
63
-
dev_dbg(pci->dev, "Enable link\n");
64
-
65
-
ret = stm32_pcie_enable_link(pci);
66
-
if (ret) {
67
-
dev_err(pci->dev, "PCIe cannot establish link: %d\n", ret);
68
-
return ret;
69
-
}
70
43
71
44
enable_irq(stm32_pcie->perst_irq);
72
45
···
50
77
{
51
78
struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci);
52
79
53
-
dev_dbg(pci->dev, "Disable link\n");
54
-
55
80
disable_irq(stm32_pcie->perst_irq);
56
-
57
-
stm32_pcie_disable_link(pci);
58
81
}
59
82
60
83
static int stm32_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
···
121
152
122
153
dev_dbg(dev, "PERST asserted by host\n");
123
154
155
+
regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR,
156
+
STM32MP25_PCIECR_LTSSM_EN, 0);
157
+
124
158
pci_epc_deinit_notify(ep->epc);
125
159
126
160
stm32_pcie_disable_resources(stm32_pcie);
···
163
191
}
164
192
165
193
pci_epc_init_notify(ep->epc);
194
+
195
+
/* Enable link training */
196
+
regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR,
197
+
STM32MP25_PCIECR_LTSSM_EN,
198
+
STM32MP25_PCIECR_LTSSM_EN);
166
199
167
200
return;
168
201
···
213
236
reset_control_deassert(stm32_pcie->rst);
214
237
215
238
ep->ops = &stm32_pcie_ep_ops;
239
+
240
+
ep->page_size = stm32_pcie_epc_features.align;
216
241
217
242
ret = dw_pcie_ep_init(ep);
218
243
if (ret) {
+13
-1
drivers/pci/controller/dwc/pcie-stm32.c
+13
-1
drivers/pci/controller/dwc/pcie-stm32.c
···
7
7
*/
8
8
9
9
#include <linux/clk.h>
10
+
#include <linux/delay.h>
11
+
#include <linux/device.h>
12
+
#include <linux/err.h>
13
+
#include <linux/gpio/consumer.h>
14
+
#include <linux/irq.h>
10
15
#include <linux/mfd/syscon.h>
16
+
#include <linux/mod_devicetable.h>
17
+
#include <linux/module.h>
18
+
#include <linux/of.h>
11
19
#include <linux/of_platform.h>
12
20
#include <linux/phy/phy.h>
13
21
#include <linux/pinctrl/consumer.h>
14
22
#include <linux/platform_device.h>
23
+
#include <linux/pm.h>
15
24
#include <linux/pm_runtime.h>
16
25
#include <linux/pm_wakeirq.h>
17
26
#include <linux/regmap.h>
18
27
#include <linux/reset.h>
28
+
#include <linux/stddef.h>
29
+
30
+
#include "../../pci.h"
31
+
19
32
#include "pcie-designware.h"
20
33
#include "pcie-stm32.h"
21
-
#include "../../pci.h"
22
34
23
35
struct stm32_pcie {
24
36
struct dw_pcie pci;
+3
drivers/pci/controller/dwc/pcie-stm32.h
+3
drivers/pci/controller/dwc/pcie-stm32.h
+8
-40
drivers/pci/controller/dwc/pcie-tegra194.c
+8
-40
drivers/pci/controller/dwc/pcie-tegra194.c
···
260
260
u32 msi_ctrl_int;
261
261
u32 num_lanes;
262
262
u32 cid;
263
-
u32 cfg_link_cap_l1sub;
264
263
u32 ras_des_cap;
265
264
u32 pcie_cap_base;
266
265
u32 aspm_cmrt;
···
474
475
return IRQ_HANDLED;
475
476
476
477
/* If EP doesn't advertise L1SS, just return */
477
-
val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
478
-
if (!(val & (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2)))
478
+
if (!pci->l1ss_support)
479
479
return IRQ_HANDLED;
480
480
481
481
/* Check if BME is set to '1' */
···
606
608
};
607
609
608
610
#if defined(CONFIG_PCIEASPM)
609
-
static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
610
-
{
611
-
u32 val;
612
-
613
-
val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
614
-
val &= ~PCI_L1SS_CAP_ASPM_L1_1;
615
-
dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
616
-
}
617
-
618
-
static void disable_aspm_l12(struct tegra_pcie_dw *pcie)
619
-
{
620
-
u32 val;
621
-
622
-
val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
623
-
val &= ~PCI_L1SS_CAP_ASPM_L1_2;
624
-
dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
625
-
}
626
-
627
611
static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
628
612
{
629
613
u32 val;
···
662
682
static void init_host_aspm(struct tegra_pcie_dw *pcie)
663
683
{
664
684
struct dw_pcie *pci = &pcie->pci;
665
-
u32 val;
685
+
u32 l1ss, val;
666
686
667
-
val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);
668
-
pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP;
687
+
l1ss = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);
669
688
670
689
pcie->ras_des_cap = dw_pcie_find_ext_capability(&pcie->pci,
671
690
PCI_EXT_CAP_ID_VNDR);
···
676
697
PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
677
698
678
699
/* Program T_cmrt and T_pwr_on values */
679
-
val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
700
+
val = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP);
680
701
val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE);
681
702
val |= (pcie->aspm_cmrt << 8);
682
703
val |= (pcie->aspm_pwr_on_t << 19);
683
-
dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
704
+
dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, val);
705
+
706
+
if (pcie->supports_clkreq)
707
+
pci->l1ss_support = true;
684
708
685
709
/* Program L0s and L1 entrance latencies */
686
710
val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
···
708
726
aspm_state_cnt);
709
727
}
710
728
#else
711
-
static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; }
712
-
static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; }
713
729
static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; }
714
730
static inline void init_debugfs(struct tegra_pcie_dw *pcie) { return; }
715
731
#endif
···
910
930
config_gen3_gen4_eq_presets(pcie);
911
931
912
932
init_host_aspm(pcie);
913
-
914
-
/* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */
915
-
if (!pcie->supports_clkreq) {
916
-
disable_aspm_l11(pcie);
917
-
disable_aspm_l12(pcie);
918
-
}
919
933
920
934
if (!pcie->of_data->has_l1ss_exit_fix) {
921
935
val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
···
1844
1870
config_gen3_gen4_eq_presets(pcie);
1845
1871
1846
1872
init_host_aspm(pcie);
1847
-
1848
-
/* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */
1849
-
if (!pcie->supports_clkreq) {
1850
-
disable_aspm_l11(pcie);
1851
-
disable_aspm_l12(pcie);
1852
-
}
1853
1873
1854
1874
if (!pcie->of_data->has_l1ss_exit_fix) {
1855
1875
val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
+7
-6
drivers/pci/controller/pci-host-common.c
+7
-6
drivers/pci/controller/pci-host-common.c
···
53
53
EXPORT_SYMBOL_GPL(pci_host_common_ecam_create);
54
54
55
55
int pci_host_common_init(struct platform_device *pdev,
56
+
struct pci_host_bridge *bridge,
56
57
const struct pci_ecam_ops *ops)
57
58
{
58
59
struct device *dev = &pdev->dev;
59
-
struct pci_host_bridge *bridge;
60
60
struct pci_config_window *cfg;
61
-
62
-
bridge = devm_pci_alloc_host_bridge(dev, 0);
63
-
if (!bridge)
64
-
return -ENOMEM;
65
61
66
62
of_pci_check_probe_only();
67
63
···
81
85
int pci_host_common_probe(struct platform_device *pdev)
82
86
{
83
87
const struct pci_ecam_ops *ops;
88
+
struct pci_host_bridge *bridge;
84
89
85
90
ops = of_device_get_match_data(&pdev->dev);
86
91
if (!ops)
87
92
return -ENODEV;
88
93
89
-
return pci_host_common_init(pdev, ops);
94
+
bridge = devm_pci_alloc_host_bridge(&pdev->dev, 0);
95
+
if (!bridge)
96
+
return -ENOMEM;
97
+
98
+
return pci_host_common_init(pdev, bridge, ops);
90
99
}
91
100
EXPORT_SYMBOL_GPL(pci_host_common_probe);
92
101
+1
drivers/pci/controller/pci-host-common.h
+1
drivers/pci/controller/pci-host-common.h
+9
-53
drivers/pci/controller/pci-hyperv.c
+9
-53
drivers/pci/controller/pci-hyperv.c
···
3696
3696
return 0;
3697
3697
}
3698
3698
3699
-
#define HVPCI_DOM_MAP_SIZE (64 * 1024)
3700
-
static DECLARE_BITMAP(hvpci_dom_map, HVPCI_DOM_MAP_SIZE);
3701
-
3702
-
/*
3703
-
* PCI domain number 0 is used by emulated devices on Gen1 VMs, so define 0
3704
-
* as invalid for passthrough PCI devices of this driver.
3705
-
*/
3706
-
#define HVPCI_DOM_INVALID 0
3707
-
3708
-
/**
3709
-
* hv_get_dom_num() - Get a valid PCI domain number
3710
-
* Check if the PCI domain number is in use, and return another number if
3711
-
* it is in use.
3712
-
*
3713
-
* @dom: Requested domain number
3714
-
*
3715
-
* return: domain number on success, HVPCI_DOM_INVALID on failure
3716
-
*/
3717
-
static u16 hv_get_dom_num(u16 dom)
3718
-
{
3719
-
unsigned int i;
3720
-
3721
-
if (test_and_set_bit(dom, hvpci_dom_map) == 0)
3722
-
return dom;
3723
-
3724
-
for_each_clear_bit(i, hvpci_dom_map, HVPCI_DOM_MAP_SIZE) {
3725
-
if (test_and_set_bit(i, hvpci_dom_map) == 0)
3726
-
return i;
3727
-
}
3728
-
3729
-
return HVPCI_DOM_INVALID;
3730
-
}
3731
-
3732
-
/**
3733
-
* hv_put_dom_num() - Mark the PCI domain number as free
3734
-
* @dom: Domain number to be freed
3735
-
*/
3736
-
static void hv_put_dom_num(u16 dom)
3737
-
{
3738
-
clear_bit(dom, hvpci_dom_map);
3739
-
}
3740
-
3741
3699
/**
3742
3700
* hv_pci_probe() - New VMBus channel probe, for a root PCI bus
3743
3701
* @hdev: VMBus's tracking struct for this root PCI bus
···
3708
3750
{
3709
3751
struct pci_host_bridge *bridge;
3710
3752
struct hv_pcibus_device *hbus;
3711
-
u16 dom_req, dom;
3753
+
int ret, dom;
3754
+
u16 dom_req;
3712
3755
char *name;
3713
-
int ret;
3714
3756
3715
3757
bridge = devm_pci_alloc_host_bridge(&hdev->device, 0);
3716
3758
if (!bridge)
···
3737
3779
* PCI bus (which is actually emulated by the hypervisor) is domain 0.
3738
3780
* (2) There will be no overlap between domains (after fixing possible
3739
3781
* collisions) in the same VM.
3782
+
*
3783
+
* Because Gen1 VMs use domain 0, don't allow picking domain 0 here,
3784
+
* even if bytes 4 and 5 of the instance GUID are both zero. For wider
3785
+
* userspace compatibility, limit the domain ID to a 16-bit value.
3740
3786
*/
3741
3787
dom_req = hdev->dev_instance.b[5] << 8 | hdev->dev_instance.b[4];
3742
-
dom = hv_get_dom_num(dom_req);
3743
-
3744
-
if (dom == HVPCI_DOM_INVALID) {
3788
+
dom = pci_bus_find_emul_domain_nr(dom_req, 1, U16_MAX);
3789
+
if (dom < 0) {
3745
3790
dev_err(&hdev->device,
3746
3791
"Unable to use dom# 0x%x or other numbers", dom_req);
3747
3792
ret = -EINVAL;
···
3878
3917
destroy_wq:
3879
3918
destroy_workqueue(hbus->wq);
3880
3919
free_dom:
3881
-
hv_put_dom_num(hbus->bridge->domain_nr);
3920
+
pci_bus_release_emul_domain_nr(hbus->bridge->domain_nr);
3882
3921
free_bus:
3883
3922
kfree(hbus);
3884
3923
return ret;
···
4002
4041
hv_pci_free_bridge_windows(hbus);
4003
4042
irq_domain_remove(hbus->irq_domain);
4004
4043
irq_domain_free_fwnode(hbus->fwnode);
4005
-
4006
-
hv_put_dom_num(hbus->bridge->domain_nr);
4007
4044
4008
4045
kfree(hbus);
4009
4046
}
···
4175
4216
ret = hv_pci_irqchip_init();
4176
4217
if (ret)
4177
4218
return ret;
4178
-
4179
-
/* Set the invalid domain number's bit, so it will not be used */
4180
-
set_bit(HVPCI_DOM_INVALID, hvpci_dom_map);
4181
4219
4182
4220
/* Initialize PCI block r/w interface */
4183
4221
hvpci_block_ops.read_block = hv_read_config_block;
+6
drivers/pci/controller/pci-ixp4xx.c
+6
drivers/pci/controller/pci-ixp4xx.c
···
214
214
return 0xffffffff;
215
215
}
216
216
217
+
#ifdef CONFIG_ARM
217
218
static int ixp4xx_crp_read_config(struct ixp4xx_pci *p, int where, int size,
218
219
u32 *value)
219
220
{
···
252
251
253
252
return PCIBIOS_SUCCESSFUL;
254
253
}
254
+
#endif
255
255
256
256
static int ixp4xx_crp_write_config(struct ixp4xx_pci *p, int where, int size,
257
257
u32 value)
···
472
470
return 0;
473
471
}
474
472
473
+
#ifdef CONFIG_ARM
475
474
/* Only used to get context for abort handling */
476
475
static struct ixp4xx_pci *ixp4xx_pci_abort_singleton;
477
476
···
512
509
513
510
return 0;
514
511
}
512
+
#endif
515
513
516
514
static int __init ixp4xx_pci_probe(struct platform_device *pdev)
517
515
{
···
559
555
dev_info(dev, "controller is in %s mode\n",
560
556
p->host_mode ? "host" : "option");
561
557
558
+
#ifdef CONFIG_ARM
562
559
/* Hook in our fault handler for PCI errors */
563
560
ixp4xx_pci_abort_singleton = p;
564
561
hook_fault_code(16+6, ixp4xx_pci_abort_handler, SIGBUS, 0,
565
562
"imprecise external abort");
563
+
#endif
566
564
567
565
ret = ixp4xx_pci_parse_map_ranges(p);
568
566
if (ret)
+6
-37
drivers/pci/controller/pcie-apple.c
+6
-37
drivers/pci/controller/pcie-apple.c
···
187
187
const struct hw_info *hw;
188
188
unsigned long *bitmap;
189
189
struct list_head ports;
190
-
struct list_head entry;
191
190
struct completion event;
192
191
struct irq_fwspec fwspec;
193
192
u32 nvecs;
···
204
205
int sid_map_sz;
205
206
int idx;
206
207
};
207
-
208
-
static LIST_HEAD(pcie_list);
209
-
static DEFINE_MUTEX(pcie_list_lock);
210
208
211
209
static void rmw_set(u32 set, void __iomem *addr)
212
210
{
···
720
724
return 0;
721
725
}
722
726
723
-
static void apple_pcie_register(struct apple_pcie *pcie)
724
-
{
725
-
guard(mutex)(&pcie_list_lock);
726
-
727
-
list_add_tail(&pcie->entry, &pcie_list);
728
-
}
729
-
730
-
static void apple_pcie_unregister(struct apple_pcie *pcie)
731
-
{
732
-
guard(mutex)(&pcie_list_lock);
733
-
734
-
list_del(&pcie->entry);
735
-
}
736
-
737
727
static struct apple_pcie *apple_pcie_lookup(struct device *dev)
738
728
{
739
-
struct apple_pcie *pcie;
740
-
741
-
guard(mutex)(&pcie_list_lock);
742
-
743
-
list_for_each_entry(pcie, &pcie_list, entry) {
744
-
if (pcie->dev == dev)
745
-
return pcie;
746
-
}
747
-
748
-
return NULL;
729
+
return pci_host_bridge_priv(dev_get_drvdata(dev));
749
730
}
750
731
751
732
static struct apple_pcie_port *apple_pcie_get_port(struct pci_dev *pdev)
···
848
875
static int apple_pcie_probe(struct platform_device *pdev)
849
876
{
850
877
struct device *dev = &pdev->dev;
878
+
struct pci_host_bridge *bridge;
851
879
struct apple_pcie *pcie;
852
880
int ret;
853
881
854
-
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
855
-
if (!pcie)
882
+
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
883
+
if (!bridge)
856
884
return -ENOMEM;
857
885
886
+
pcie = pci_host_bridge_priv(bridge);
858
887
pcie->dev = dev;
859
888
pcie->hw = of_device_get_match_data(dev);
860
889
if (!pcie->hw)
···
872
897
if (ret)
873
898
return ret;
874
899
875
-
apple_pcie_register(pcie);
876
-
877
-
ret = pci_host_common_init(pdev, &apple_pcie_cfg_ecam_ops);
878
-
if (ret)
879
-
apple_pcie_unregister(pcie);
880
-
881
-
return ret;
900
+
return pci_host_common_init(pdev, bridge, &apple_pcie_cfg_ecam_ops);
882
901
}
883
902
884
903
static const struct of_device_id apple_pcie_of_match[] = {
+196
-13
drivers/pci/controller/pcie-brcmstb.c
+196
-13
drivers/pci/controller/pcie-brcmstb.c
···
14
14
#include <linux/irqchip/chained_irq.h>
15
15
#include <linux/irqchip/irq-msi-lib.h>
16
16
#include <linux/irqdomain.h>
17
+
#include <linux/kdebug.h>
17
18
#include <linux/kernel.h>
18
19
#include <linux/list.h>
19
20
#include <linux/log2.h>
20
21
#include <linux/module.h>
21
22
#include <linux/msi.h>
23
+
#include <linux/notifier.h>
22
24
#include <linux/of_address.h>
23
25
#include <linux/of_irq.h>
24
26
#include <linux/of_pci.h>
25
27
#include <linux/of_platform.h>
28
+
#include <linux/panic_notifier.h>
26
29
#include <linux/pci.h>
27
30
#include <linux/pci-ecam.h>
28
31
#include <linux/printk.h>
···
33
30
#include <linux/reset.h>
34
31
#include <linux/sizes.h>
35
32
#include <linux/slab.h>
33
+
#include <linux/spinlock.h>
36
34
#include <linux/string.h>
35
+
#include <linux/string_choices.h>
37
36
#include <linux/types.h>
38
37
39
38
#include "../pci.h"
···
53
48
54
49
#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
55
50
#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK 0x1f0
56
-
#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
57
51
58
52
#define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8
59
53
#define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8
···
159
155
#define MSI_INT_MASK_SET 0x10
160
156
#define MSI_INT_MASK_CLR 0x14
161
157
158
+
/* Error report registers */
159
+
#define PCIE_OUTB_ERR_TREAT 0x6000
160
+
#define PCIE_OUTB_ERR_TREAT_CONFIG 0x1
161
+
#define PCIE_OUTB_ERR_TREAT_MEM 0x2
162
+
#define PCIE_OUTB_ERR_VALID 0x6004
163
+
#define PCIE_OUTB_ERR_CLEAR 0x6008
164
+
#define PCIE_OUTB_ERR_ACC_INFO 0x600c
165
+
#define PCIE_OUTB_ERR_ACC_INFO_CFG_ERR BIT(0)
166
+
#define PCIE_OUTB_ERR_ACC_INFO_MEM_ERR BIT(1)
167
+
#define PCIE_OUTB_ERR_ACC_INFO_TYPE_64 BIT(2)
168
+
#define PCIE_OUTB_ERR_ACC_INFO_DIR_WRITE BIT(4)
169
+
#define PCIE_OUTB_ERR_ACC_INFO_BYTE_LANES 0xff00
170
+
#define PCIE_OUTB_ERR_ACC_ADDR 0x6010
171
+
#define PCIE_OUTB_ERR_ACC_ADDR_BUS 0xff00000
172
+
#define PCIE_OUTB_ERR_ACC_ADDR_DEV 0xf8000
173
+
#define PCIE_OUTB_ERR_ACC_ADDR_FUNC 0x7000
174
+
#define PCIE_OUTB_ERR_ACC_ADDR_REG 0xfff
175
+
#define PCIE_OUTB_ERR_CFG_CAUSE 0x6014
176
+
#define PCIE_OUTB_ERR_CFG_CAUSE_TIMEOUT BIT(6)
177
+
#define PCIE_OUTB_ERR_CFG_CAUSE_ABORT BIT(5)
178
+
#define PCIE_OUTB_ERR_CFG_CAUSE_UNSUPP_REQ BIT(4)
179
+
#define PCIE_OUTB_ERR_CFG_CAUSE_ACC_TIMEOUT BIT(2)
180
+
#define PCIE_OUTB_ERR_CFG_CAUSE_ACC_DISABLED BIT(1)
181
+
#define PCIE_OUTB_ERR_CFG_CAUSE_ACC_64BIT BIT(0)
182
+
#define PCIE_OUTB_ERR_MEM_ADDR_LO 0x6018
183
+
#define PCIE_OUTB_ERR_MEM_ADDR_HI 0x601c
184
+
#define PCIE_OUTB_ERR_MEM_CAUSE 0x6020
185
+
#define PCIE_OUTB_ERR_MEM_CAUSE_TIMEOUT BIT(6)
186
+
#define PCIE_OUTB_ERR_MEM_CAUSE_ABORT BIT(5)
187
+
#define PCIE_OUTB_ERR_MEM_CAUSE_UNSUPP_REQ BIT(4)
188
+
#define PCIE_OUTB_ERR_MEM_CAUSE_ACC_DISABLED BIT(1)
189
+
#define PCIE_OUTB_ERR_MEM_CAUSE_BAD_ADDR BIT(0)
190
+
162
191
#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
163
-
#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
164
192
165
193
#define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
166
194
#define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
···
295
259
int (*perst_set)(struct brcm_pcie *pcie, u32 val);
296
260
int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
297
261
int (*post_setup)(struct brcm_pcie *pcie);
262
+
bool has_err_report;
298
263
};
299
264
300
265
struct subdev_regulators {
···
340
303
struct subdev_regulators *sr;
341
304
bool ep_wakeup_capable;
342
305
const struct pcie_cfg_data *cfg;
306
+
bool bridge_in_reset;
307
+
struct notifier_block die_notifier;
308
+
struct notifier_block panic_notifier;
309
+
spinlock_t bridge_lock;
343
310
};
344
311
345
312
static inline bool is_bmips(const struct brcm_pcie *pcie)
346
313
{
347
314
return pcie->cfg->soc_base == BCM7435 || pcie->cfg->soc_base == BCM7425;
315
+
}
316
+
317
+
static int brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val)
318
+
{
319
+
unsigned long flags;
320
+
int ret;
321
+
322
+
if (pcie->cfg->has_err_report)
323
+
spin_lock_irqsave(&pcie->bridge_lock, flags);
324
+
325
+
ret = pcie->cfg->bridge_sw_init_set(pcie, val);
326
+
/* If we fail, assume the bridge is in reset (off) */
327
+
pcie->bridge_in_reset = ret ? true : val;
328
+
329
+
if (pcie->cfg->has_err_report)
330
+
spin_unlock_irqrestore(&pcie->bridge_lock, flags);
331
+
332
+
return ret;
348
333
}
349
334
350
335
/*
···
1134
1075
void __iomem *base = pcie->base;
1135
1076
struct pci_host_bridge *bridge;
1136
1077
struct resource_entry *entry;
1137
-
u32 tmp, burst, aspm_support, num_lanes, num_lanes_cap;
1078
+
u32 tmp, burst, num_lanes, num_lanes_cap;
1138
1079
u8 num_out_wins = 0;
1139
1080
int num_inbound_wins = 0;
1140
1081
int memc, ret;
1141
1082
1142
1083
/* Reset the bridge */
1143
-
ret = pcie->cfg->bridge_sw_init_set(pcie, 1);
1084
+
ret = brcm_pcie_bridge_sw_init_set(pcie, 1);
1144
1085
if (ret)
1145
1086
return ret;
1146
1087
···
1156
1097
usleep_range(100, 200);
1157
1098
1158
1099
/* Take the bridge out of reset */
1159
-
ret = pcie->cfg->bridge_sw_init_set(pcie, 0);
1100
+
ret = brcm_pcie_bridge_sw_init_set(pcie, 0);
1160
1101
if (ret)
1161
1102
return ret;
1162
1103
···
1234
1175
1235
1176
1236
1177
/* Don't advertise L0s capability if 'aspm-no-l0s' */
1237
-
aspm_support = PCIE_LINK_STATE_L1;
1238
-
if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
1239
-
aspm_support |= PCIE_LINK_STATE_L0S;
1240
1178
tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
1241
-
u32p_replace_bits(&tmp, aspm_support,
1242
-
PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
1179
+
if (of_property_read_bool(pcie->np, "aspm-no-l0s"))
1180
+
tmp &= ~PCI_EXP_LNKCAP_ASPM_L0S;
1243
1181
writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
1244
1182
1245
1183
/* 'tmp' still holds the contents of PRIV1_LINK_CAPABILITY */
···
1621
1565
1622
1566
if (!(pcie->cfg->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN))
1623
1567
/* Shutdown PCIe bridge */
1624
-
ret = pcie->cfg->bridge_sw_init_set(pcie, 1);
1568
+
ret = brcm_pcie_bridge_sw_init_set(pcie, 1);
1625
1569
1626
1570
return ret;
1627
1571
}
···
1709
1653
goto err_reset;
1710
1654
1711
1655
/* Take bridge out of reset so we can access the SERDES reg */
1712
-
pcie->cfg->bridge_sw_init_set(pcie, 0);
1656
+
ret = brcm_pcie_bridge_sw_init_set(pcie, 0);
1657
+
if (ret)
1658
+
goto err_reset;
1713
1659
1714
1660
/* SERDES_IDDQ = 0 */
1715
1661
tmp = readl(base + HARD_DEBUG(pcie));
···
1765
1707
return ret;
1766
1708
}
1767
1709
1710
+
/* Dump out PCIe errors on die or panic */
1711
+
static int brcm_pcie_dump_err(struct brcm_pcie *pcie,
1712
+
const char *type)
1713
+
{
1714
+
void __iomem *base = pcie->base;
1715
+
int i, is_cfg_err, is_mem_err, lanes;
1716
+
const char *width_str, *direction_str;
1717
+
u32 info, cfg_addr, cfg_cause, mem_cause, lo, hi;
1718
+
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1719
+
unsigned long flags;
1720
+
char lanes_str[9];
1721
+
1722
+
spin_lock_irqsave(&pcie->bridge_lock, flags);
1723
+
/* Don't access registers when the bridge is off */
1724
+
if (pcie->bridge_in_reset || readl(base + PCIE_OUTB_ERR_VALID) == 0) {
1725
+
spin_unlock_irqrestore(&pcie->bridge_lock, flags);
1726
+
return NOTIFY_DONE;
1727
+
}
1728
+
1729
+
/* Read all necessary registers so we can release the spinlock ASAP */
1730
+
info = readl(base + PCIE_OUTB_ERR_ACC_INFO);
1731
+
is_cfg_err = !!(info & PCIE_OUTB_ERR_ACC_INFO_CFG_ERR);
1732
+
is_mem_err = !!(info & PCIE_OUTB_ERR_ACC_INFO_MEM_ERR);
1733
+
if (is_cfg_err) {
1734
+
cfg_addr = readl(base + PCIE_OUTB_ERR_ACC_ADDR);
1735
+
cfg_cause = readl(base + PCIE_OUTB_ERR_CFG_CAUSE);
1736
+
}
1737
+
if (is_mem_err) {
1738
+
mem_cause = readl(base + PCIE_OUTB_ERR_MEM_CAUSE);
1739
+
lo = readl(base + PCIE_OUTB_ERR_MEM_ADDR_LO);
1740
+
hi = readl(base + PCIE_OUTB_ERR_MEM_ADDR_HI);
1741
+
}
1742
+
/* We've got all of the info, clear the error */
1743
+
writel(1, base + PCIE_OUTB_ERR_CLEAR);
1744
+
spin_unlock_irqrestore(&pcie->bridge_lock, flags);
1745
+
1746
+
dev_err(pcie->dev, "reporting PCIe info which may be related to %s error\n",
1747
+
type);
1748
+
width_str = (info & PCIE_OUTB_ERR_ACC_INFO_TYPE_64) ? "64bit" : "32bit";
1749
+
direction_str = str_read_write(!(info & PCIE_OUTB_ERR_ACC_INFO_DIR_WRITE));
1750
+
lanes = FIELD_GET(PCIE_OUTB_ERR_ACC_INFO_BYTE_LANES, info);
1751
+
for (i = 0, lanes_str[8] = 0; i < 8; i++)
1752
+
lanes_str[i] = (lanes & (1 << i)) ? '1' : '0';
1753
+
1754
+
if (is_cfg_err) {
1755
+
int bus = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_BUS, cfg_addr);
1756
+
int dev = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_DEV, cfg_addr);
1757
+
int func = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_FUNC, cfg_addr);
1758
+
int reg = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_REG, cfg_addr);
1759
+
1760
+
dev_err(pcie->dev, "Error: CFG Acc, %s, %s (%04x:%02x:%02x.%d) reg=0x%x, lanes=%s\n",
1761
+
width_str, direction_str, bridge->domain_nr, bus, dev,
1762
+
func, reg, lanes_str);
1763
+
dev_err(pcie->dev, " Type: TO=%d Abt=%d UnsupReq=%d AccTO=%d AccDsbld=%d Acc64bit=%d\n",
1764
+
!!(cfg_cause & PCIE_OUTB_ERR_CFG_CAUSE_TIMEOUT),
1765
+
!!(cfg_cause & PCIE_OUTB_ERR_CFG_CAUSE_ABORT),
1766
+
!!(cfg_cause & PCIE_OUTB_ERR_CFG_CAUSE_UNSUPP_REQ),
1767
+
!!(cfg_cause & PCIE_OUTB_ERR_CFG_CAUSE_ACC_TIMEOUT),
1768
+
!!(cfg_cause & PCIE_OUTB_ERR_CFG_CAUSE_ACC_DISABLED),
1769
+
!!(cfg_cause & PCIE_OUTB_ERR_CFG_CAUSE_ACC_64BIT));
1770
+
}
1771
+
1772
+
if (is_mem_err) {
1773
+
u64 addr = ((u64)hi << 32) | (u64)lo;
1774
+
1775
+
dev_err(pcie->dev, "Error: Mem Acc, %s, %s, @0x%llx, lanes=%s\n",
1776
+
width_str, direction_str, addr, lanes_str);
1777
+
dev_err(pcie->dev, " Type: TO=%d Abt=%d UnsupReq=%d AccDsble=%d BadAddr=%d\n",
1778
+
!!(mem_cause & PCIE_OUTB_ERR_MEM_CAUSE_TIMEOUT),
1779
+
!!(mem_cause & PCIE_OUTB_ERR_MEM_CAUSE_ABORT),
1780
+
!!(mem_cause & PCIE_OUTB_ERR_MEM_CAUSE_UNSUPP_REQ),
1781
+
!!(mem_cause & PCIE_OUTB_ERR_MEM_CAUSE_ACC_DISABLED),
1782
+
!!(mem_cause & PCIE_OUTB_ERR_MEM_CAUSE_BAD_ADDR));
1783
+
}
1784
+
1785
+
return NOTIFY_DONE;
1786
+
}
1787
+
1788
+
static int brcm_pcie_die_notify_cb(struct notifier_block *self,
1789
+
unsigned long v, void *p)
1790
+
{
1791
+
struct brcm_pcie *pcie =
1792
+
container_of(self, struct brcm_pcie, die_notifier);
1793
+
1794
+
return brcm_pcie_dump_err(pcie, "Die");
1795
+
}
1796
+
1797
+
static int brcm_pcie_panic_notify_cb(struct notifier_block *self,
1798
+
unsigned long v, void *p)
1799
+
{
1800
+
struct brcm_pcie *pcie =
1801
+
container_of(self, struct brcm_pcie, panic_notifier);
1802
+
1803
+
return brcm_pcie_dump_err(pcie, "Panic");
1804
+
}
1805
+
1806
+
static void brcm_register_die_notifiers(struct brcm_pcie *pcie)
1807
+
{
1808
+
pcie->panic_notifier.notifier_call = brcm_pcie_panic_notify_cb;
1809
+
atomic_notifier_chain_register(&panic_notifier_list,
1810
+
&pcie->panic_notifier);
1811
+
1812
+
pcie->die_notifier.notifier_call = brcm_pcie_die_notify_cb;
1813
+
register_die_notifier(&pcie->die_notifier);
1814
+
}
1815
+
1816
+
static void brcm_unregister_die_notifiers(struct brcm_pcie *pcie)
1817
+
{
1818
+
unregister_die_notifier(&pcie->die_notifier);
1819
+
atomic_notifier_chain_unregister(&panic_notifier_list,
1820
+
&pcie->panic_notifier);
1821
+
}
1822
+
1768
1823
static void __brcm_pcie_remove(struct brcm_pcie *pcie)
1769
1824
{
1770
1825
brcm_msi_remove(pcie);
···
1896
1725
1897
1726
pci_stop_root_bus(bridge->bus);
1898
1727
pci_remove_root_bus(bridge->bus);
1728
+
if (pcie->cfg->has_err_report)
1729
+
brcm_unregister_die_notifiers(pcie);
1730
+
1899
1731
__brcm_pcie_remove(pcie);
1900
1732
}
1901
1733
···
1999
1825
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
2000
1826
.has_phy = true,
2001
1827
.num_inbound_wins = 3,
1828
+
.has_err_report = true,
2002
1829
};
2003
1830
2004
1831
static const struct pcie_cfg_data bcm7712_cfg = {
···
2096
1921
if (ret)
2097
1922
return dev_err_probe(&pdev->dev, ret, "could not enable clock\n");
2098
1923
2099
-
pcie->cfg->bridge_sw_init_set(pcie, 0);
1924
+
ret = brcm_pcie_bridge_sw_init_set(pcie, 0);
1925
+
if (ret)
1926
+
return dev_err_probe(&pdev->dev, ret,
1927
+
"could not de-assert bridge reset\n");
2100
1928
2101
1929
if (pcie->swinit_reset) {
2102
1930
ret = reset_control_assert(pcie->swinit_reset);
···
2172
1994
if (ret) {
2173
1995
brcm_pcie_remove(pdev);
2174
1996
return ret;
1997
+
}
1998
+
1999
+
if (pcie->cfg->has_err_report) {
2000
+
spin_lock_init(&pcie->bridge_lock);
2001
+
brcm_register_die_notifiers(pcie);
2175
2002
}
2176
2003
2177
2004
return 0;
+81
-32
drivers/pci/controller/pcie-mediatek.c
+81
-32
drivers/pci/controller/pcie-mediatek.c
···
143
143
struct mtk_pcie_port;
144
144
145
145
/**
146
+
* enum mtk_pcie_quirks - MTK PCIe quirks
147
+
* @MTK_PCIE_FIX_CLASS_ID: host's class ID needed to be fixed
148
+
* @MTK_PCIE_FIX_DEVICE_ID: host's device ID needed to be fixed
149
+
* @MTK_PCIE_NO_MSI: Bridge has no MSI support, and relies on an external block
150
+
* @MTK_PCIE_SKIP_RSTB: Skip calling RSTB bits on PCIe probe
151
+
*/
152
+
enum mtk_pcie_quirks {
153
+
MTK_PCIE_FIX_CLASS_ID = BIT(0),
154
+
MTK_PCIE_FIX_DEVICE_ID = BIT(1),
155
+
MTK_PCIE_NO_MSI = BIT(2),
156
+
MTK_PCIE_SKIP_RSTB = BIT(3),
157
+
};
158
+
159
+
/**
146
160
* struct mtk_pcie_soc - differentiate between host generations
147
-
* @need_fix_class_id: whether this host's class ID needed to be fixed or not
148
-
* @need_fix_device_id: whether this host's device ID needed to be fixed or not
149
-
* @no_msi: Bridge has no MSI support, and relies on an external block
150
161
* @device_id: device ID which this host need to be fixed
151
162
* @ops: pointer to configuration access functions
152
163
* @startup: pointer to controller setting functions
153
164
* @setup_irq: pointer to initialize IRQ functions
165
+
* @quirks: PCIe device quirks.
154
166
*/
155
167
struct mtk_pcie_soc {
156
-
bool need_fix_class_id;
157
-
bool need_fix_device_id;
158
-
bool no_msi;
159
168
unsigned int device_id;
160
169
struct pci_ops *ops;
161
170
int (*startup)(struct mtk_pcie_port *port);
162
171
int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
172
+
enum mtk_pcie_quirks quirks;
163
173
};
164
174
165
175
/**
···
689
679
regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);
690
680
}
691
681
692
-
/* Assert all reset signals */
693
-
writel(0, port->base + PCIE_RST_CTRL);
682
+
if (!(soc->quirks & MTK_PCIE_SKIP_RSTB)) {
683
+
/* Assert all reset signals */
684
+
writel(0, port->base + PCIE_RST_CTRL);
694
685
695
-
/*
696
-
* Enable PCIe link down reset, if link status changed from link up to
697
-
* link down, this will reset MAC control registers and configuration
698
-
* space.
699
-
*/
700
-
writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
686
+
/*
687
+
* Enable PCIe link down reset, if link status changed from
688
+
* link up to link down, this will reset MAC control registers
689
+
* and configuration space.
690
+
*/
691
+
writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
701
692
702
-
/*
703
-
* Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
704
-
* 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
705
-
* be delayed 100ms (TPVPERL) for the power and clock to become stable.
706
-
*/
707
-
msleep(100);
693
+
msleep(PCIE_T_PVPERL_MS);
708
694
709
-
/* De-assert PHY, PE, PIPE, MAC and configuration reset */
710
-
val = readl(port->base + PCIE_RST_CTRL);
711
-
val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
712
-
PCIE_MAC_SRSTB | PCIE_CRSTB;
713
-
writel(val, port->base + PCIE_RST_CTRL);
695
+
/* De-assert PHY, PE, PIPE, MAC and configuration reset */
696
+
val = readl(port->base + PCIE_RST_CTRL);
697
+
val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
698
+
PCIE_MAC_SRSTB | PCIE_CRSTB;
699
+
writel(val, port->base + PCIE_RST_CTRL);
700
+
}
714
701
715
702
/* Set up vendor ID and class code */
716
-
if (soc->need_fix_class_id) {
703
+
if (soc->quirks & MTK_PCIE_FIX_CLASS_ID) {
717
704
val = PCI_VENDOR_ID_MEDIATEK;
718
705
writew(val, port->base + PCIE_CONF_VEND_ID);
719
706
···
718
711
writew(val, port->base + PCIE_CONF_CLASS_ID);
719
712
}
720
713
721
-
if (soc->need_fix_device_id)
714
+
if (soc->quirks & MTK_PCIE_FIX_DEVICE_ID)
722
715
writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
723
716
724
717
/* 100ms timeout value should be enough for Gen1/2 training */
···
826
819
writel(val, pcie->base + PCIE_CFG_DATA);
827
820
828
821
return 0;
822
+
}
823
+
824
+
static int mtk_pcie_startup_port_an7583(struct mtk_pcie_port *port)
825
+
{
826
+
struct mtk_pcie *pcie = port->pcie;
827
+
struct device *dev = pcie->dev;
828
+
struct pci_host_bridge *host;
829
+
struct resource_entry *entry;
830
+
struct regmap *pbus_regmap;
831
+
resource_size_t addr;
832
+
u32 args[2], size;
833
+
834
+
/*
835
+
* Configure PBus base address and base address mask to allow
836
+
* the hw to detect if a given address is accessible on PCIe
837
+
* controller.
838
+
*/
839
+
pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,
840
+
"mediatek,pbus-csr",
841
+
ARRAY_SIZE(args),
842
+
args);
843
+
if (IS_ERR(pbus_regmap))
844
+
return PTR_ERR(pbus_regmap);
845
+
846
+
host = pci_host_bridge_from_priv(pcie);
847
+
entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
848
+
if (!entry)
849
+
return -ENODEV;
850
+
851
+
addr = entry->res->start - entry->offset;
852
+
regmap_write(pbus_regmap, args[0], lower_32_bits(addr));
853
+
size = lower_32_bits(resource_size(entry->res));
854
+
regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));
855
+
856
+
return mtk_pcie_startup_port_v2(port);
829
857
}
830
858
831
859
static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
···
1141
1099
1142
1100
host->ops = pcie->soc->ops;
1143
1101
host->sysdata = pcie;
1144
-
host->msi_domain = pcie->soc->no_msi;
1102
+
host->msi_domain = !!(pcie->soc->quirks & MTK_PCIE_NO_MSI);
1145
1103
1146
1104
err = pci_host_probe(host);
1147
1105
if (err)
···
1229
1187
};
1230
1188
1231
1189
static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1232
-
.no_msi = true,
1233
1190
.ops = &mtk_pcie_ops,
1234
1191
.startup = mtk_pcie_startup_port,
1192
+
.quirks = MTK_PCIE_NO_MSI,
1235
1193
};
1236
1194
1237
1195
static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
···
1241
1199
};
1242
1200
1243
1201
static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1244
-
.need_fix_class_id = true,
1245
1202
.ops = &mtk_pcie_ops_v2,
1246
1203
.startup = mtk_pcie_startup_port_v2,
1247
1204
.setup_irq = mtk_pcie_setup_irq,
1205
+
.quirks = MTK_PCIE_FIX_CLASS_ID,
1206
+
};
1207
+
1208
+
static const struct mtk_pcie_soc mtk_pcie_soc_an7583 = {
1209
+
.ops = &mtk_pcie_ops_v2,
1210
+
.startup = mtk_pcie_startup_port_an7583,
1211
+
.setup_irq = mtk_pcie_setup_irq,
1212
+
.quirks = MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_SKIP_RSTB,
1248
1213
};
1249
1214
1250
1215
static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1251
-
.need_fix_class_id = true,
1252
-
.need_fix_device_id = true,
1253
1216
.device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1254
1217
.ops = &mtk_pcie_ops_v2,
1255
1218
.startup = mtk_pcie_startup_port_v2,
1256
1219
.setup_irq = mtk_pcie_setup_irq,
1220
+
.quirks = MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_FIX_DEVICE_ID,
1257
1221
};
1258
1222
1259
1223
static const struct of_device_id mtk_pcie_ids[] = {
1224
+
{ .compatible = "airoha,an7583-pcie", .data = &mtk_pcie_soc_an7583 },
1260
1225
{ .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1261
1226
{ .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1262
1227
{ .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
+1761
drivers/pci/controller/pcie-rzg3s-host.c
+1761
drivers/pci/controller/pcie-rzg3s-host.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* PCIe driver for Renesas RZ/G3S SoCs
4
+
*
5
+
* Copyright (C) 2025 Renesas Electronics Corp.
6
+
*
7
+
* Based on:
8
+
* drivers/pci/controller/pcie-rcar-host.c
9
+
* Copyright (C) 2009 - 2011 Paul Mundt
10
+
*/
11
+
12
+
#include <linux/bitfield.h>
13
+
#include <linux/bitmap.h>
14
+
#include <linux/bitops.h>
15
+
#include <linux/cleanup.h>
16
+
#include <linux/clk.h>
17
+
#include <linux/delay.h>
18
+
#include <linux/iopoll.h>
19
+
#include <linux/interrupt.h>
20
+
#include <linux/irq.h>
21
+
#include <linux/irqchip/chained_irq.h>
22
+
#include <linux/irqchip/irq-msi-lib.h>
23
+
#include <linux/irqdomain.h>
24
+
#include <linux/kernel.h>
25
+
#include <linux/mfd/syscon.h>
26
+
#include <linux/mutex.h>
27
+
#include <linux/msi.h>
28
+
#include <linux/of_irq.h>
29
+
#include <linux/pci.h>
30
+
#include <linux/platform_device.h>
31
+
#include <linux/pm_runtime.h>
32
+
#include <linux/regmap.h>
33
+
#include <linux/reset.h>
34
+
#include <linux/sizes.h>
35
+
#include <linux/slab.h>
36
+
#include <linux/units.h>
37
+
38
+
#include "../pci.h"
39
+
40
+
/* AXI registers */
41
+
#define RZG3S_PCI_REQDATA(id) (0x80 + (id) * 0x4)
42
+
#define RZG3S_PCI_REQRCVDAT 0x8c
43
+
44
+
#define RZG3S_PCI_REQADR1 0x90
45
+
#define RZG3S_PCI_REQADR1_BUS GENMASK(31, 24)
46
+
#define RZG3S_PCI_REQADR1_DEV GENMASK(23, 19)
47
+
#define RZG3S_PCI_REQADR1_FUNC GENMASK(18, 16)
48
+
#define RZG3S_PCI_REQADR1_REG GENMASK(11, 0)
49
+
50
+
#define RZG3S_PCI_REQBE 0x98
51
+
#define RZG3S_PCI_REQBE_BYTE_EN GENMASK(3, 0)
52
+
53
+
#define RZG3S_PCI_REQISS 0x9c
54
+
#define RZG3S_PCI_REQISS_MOR_STATUS GENMASK(18, 16)
55
+
#define RZG3S_PCI_REQISS_TR_TYPE GENMASK(11, 8)
56
+
#define RZG3S_PCI_REQISS_TR_TP0_RD FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x4)
57
+
#define RZG3S_PCI_REQISS_TR_TP0_WR FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x5)
58
+
#define RZG3S_PCI_REQISS_TR_TP1_RD FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x6)
59
+
#define RZG3S_PCI_REQISS_TR_TP1_WR FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x7)
60
+
#define RZG3S_PCI_REQISS_REQ_ISSUE BIT(0)
61
+
62
+
#define RZG3S_PCI_MSIRCVWADRL 0x100
63
+
#define RZG3S_PCI_MSIRCVWADRL_MASK GENMASK(31, 3)
64
+
#define RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA BIT(1)
65
+
#define RZG3S_PCI_MSIRCVWADRL_ENA BIT(0)
66
+
67
+
#define RZG3S_PCI_MSIRCVWADRU 0x104
68
+
69
+
#define RZG3S_PCI_MSIRCVWMSKL 0x108
70
+
#define RZG3S_PCI_MSIRCVWMSKL_MASK GENMASK(31, 2)
71
+
72
+
#define RZG3S_PCI_PINTRCVIE 0x110
73
+
#define RZG3S_PCI_PINTRCVIE_INTX(i) BIT(i)
74
+
#define RZG3S_PCI_PINTRCVIE_MSI BIT(4)
75
+
76
+
#define RZG3S_PCI_PINTRCVIS 0x114
77
+
#define RZG3S_PCI_PINTRCVIS_INTX(i) BIT(i)
78
+
#define RZG3S_PCI_PINTRCVIS_MSI BIT(4)
79
+
80
+
#define RZG3S_PCI_MSGRCVIE 0x120
81
+
#define RZG3S_PCI_MSGRCVIE_MSG_RCV BIT(24)
82
+
83
+
#define RZG3S_PCI_MSGRCVIS 0x124
84
+
#define RZG3S_PCI_MSGRCVIS_MRI BIT(24)
85
+
86
+
#define RZG3S_PCI_PEIE0 0x200
87
+
88
+
#define RZG3S_PCI_PEIS0 0x204
89
+
#define RZG3S_PCI_PEIS0_RX_DLLP_PM_ENTER BIT(12)
90
+
#define RZG3S_PCI_PEIS0_DL_UPDOWN BIT(9)
91
+
92
+
#define RZG3S_PCI_PEIE1 0x208
93
+
#define RZG3S_PCI_PEIS1 0x20c
94
+
#define RZG3S_PCI_AMEIS 0x214
95
+
#define RZG3S_PCI_ASEIS1 0x224
96
+
97
+
#define RZG3S_PCI_PCSTAT1 0x408
98
+
#define RZG3S_PCI_PCSTAT1_LTSSM_STATE GENMASK(14, 10)
99
+
#define RZG3S_PCI_PCSTAT1_DL_DOWN_STS BIT(0)
100
+
101
+
#define RZG3S_PCI_PCCTRL2 0x410
102
+
#define RZG3S_PCI_PCCTRL2_LS_CHG GENMASK(9, 8)
103
+
#define RZG3S_PCI_PCCTRL2_LS_CHG_REQ BIT(0)
104
+
105
+
#define RZG3S_PCI_PCSTAT2 0x414
106
+
#define RZG3S_PCI_PCSTAT2_LS_CHG_DONE BIT(28)
107
+
#define RZG3S_PCI_PCSTAT2_SDRIRE GENMASK(7, 1)
108
+
109
+
#define RZG3S_PCI_PERM 0x300
110
+
#define RZG3S_PCI_PERM_CFG_HWINIT_EN BIT(2)
111
+
#define RZG3S_PCI_PERM_PIPE_PHY_REG_EN BIT(1)
112
+
113
+
#define RZG3S_PCI_MSIRE(id) (0x600 + (id) * 0x10)
114
+
#define RZG3S_PCI_MSIRE_ENA BIT(0)
115
+
116
+
#define RZG3S_PCI_MSIRM(id) (0x608 + (id) * 0x10)
117
+
#define RZG3S_PCI_MSIRS(id) (0x60c + (id) * 0x10)
118
+
119
+
#define RZG3S_PCI_AWBASEL(id) (0x1000 + (id) * 0x20)
120
+
#define RZG3S_PCI_AWBASEL_WIN_ENA BIT(0)
121
+
122
+
#define RZG3S_PCI_AWBASEU(id) (0x1004 + (id) * 0x20)
123
+
#define RZG3S_PCI_AWMASKL(id) (0x1008 + (id) * 0x20)
124
+
#define RZG3S_PCI_AWMASKU(id) (0x100c + (id) * 0x20)
125
+
#define RZG3S_PCI_ADESTL(id) (0x1010 + (id) * 0x20)
126
+
#define RZG3S_PCI_ADESTU(id) (0x1014 + (id) * 0x20)
127
+
128
+
#define RZG3S_PCI_PWBASEL(id) (0x1100 + (id) * 0x20)
129
+
#define RZG3S_PCI_PWBASEL_ENA BIT(0)
130
+
131
+
#define RZG3S_PCI_PWBASEU(id) (0x1104 + (id) * 0x20)
132
+
#define RZG3S_PCI_PDESTL(id) (0x1110 + (id) * 0x20)
133
+
#define RZG3S_PCI_PDESTU(id) (0x1114 + (id) * 0x20)
134
+
#define RZG3S_PCI_PWMASKL(id) (0x1108 + (id) * 0x20)
135
+
#define RZG3S_PCI_PWMASKU(id) (0x110c + (id) * 0x20)
136
+
137
+
/* PHY control registers */
138
+
#define RZG3S_PCI_PHY_XCFGD(id) (0x2000 + (id) * 0x10)
139
+
#define RZG3S_PCI_PHY_XCFGD_NUM 39
140
+
141
+
#define RZG3S_PCI_PHY_XCFGA_CMN(id) (0x2400 + (id) * 0x10)
142
+
#define RZG3S_PCI_PHY_XCFGA_CMN_NUM 16
143
+
144
+
#define RZG3S_PCI_PHY_XCFGA_RX(id) (0x2500 + (id) * 0x10)
145
+
#define RZG3S_PCI_PHY_XCFGA_RX_NUM 13
146
+
147
+
#define RZG3S_PCI_PHY_XCFGA_TX 0x25d0
148
+
149
+
#define RZG3S_PCI_PHY_XCFG_CTRL 0x2a20
150
+
#define RZG3S_PCI_PHY_XCFG_CTRL_PHYREG_SEL BIT(0)
151
+
152
+
/* PCIe registers */
153
+
#define RZG3S_PCI_CFG_BASE 0x6000
154
+
#define RZG3S_PCI_CFG_BARMSK00L 0xa0
155
+
#define RZG3S_PCI_CFG_BARMSK00U 0xa4
156
+
157
+
#define RZG3S_PCI_CFG_PCIEC 0x60
158
+
159
+
/* System controller registers */
160
+
#define RZG3S_SYS_PCIE_RST_RSM_B 0xd74
161
+
#define RZG3S_SYS_PCIE_RST_RSM_B_MASK BIT(0)
162
+
163
+
/* Maximum number of windows */
164
+
#define RZG3S_MAX_WINDOWS 8
165
+
166
+
/* Number of MSI interrupts per register */
167
+
#define RZG3S_PCI_MSI_INT_PER_REG 32
168
+
/* The number of MSI interrupts */
169
+
#define RZG3S_PCI_MSI_INT_NR RZG3S_PCI_MSI_INT_PER_REG
170
+
171
+
/* Timeouts experimentally determined */
172
+
#define RZG3S_REQ_ISSUE_TIMEOUT_US 2500
173
+
174
+
/**
175
+
* struct rzg3s_pcie_msi - RZ/G3S PCIe MSI data structure
176
+
* @domain: IRQ domain
177
+
* @map: bitmap with the allocated MSIs
178
+
* @dma_addr: address of the allocated MSI window
179
+
* @window_base: base address of the MSI window
180
+
* @pages: allocated pages for MSI window mapping
181
+
* @map_lock: lock for bitmap with the allocated MSIs
182
+
* @irq: MSI interrupt
183
+
*/
184
+
struct rzg3s_pcie_msi {
185
+
struct irq_domain *domain;
186
+
DECLARE_BITMAP(map, RZG3S_PCI_MSI_INT_NR);
187
+
dma_addr_t dma_addr;
188
+
dma_addr_t window_base;
189
+
unsigned long pages;
190
+
struct mutex map_lock;
191
+
int irq;
192
+
};
193
+
194
+
struct rzg3s_pcie_host;
195
+
196
+
/**
197
+
* struct rzg3s_pcie_soc_data - SoC specific data
198
+
* @init_phy: PHY initialization function
199
+
* @power_resets: array with the resets that need to be de-asserted after
200
+
* power-on
201
+
* @cfg_resets: array with the resets that need to be de-asserted after
202
+
* configuration
203
+
* @num_power_resets: number of power resets
204
+
* @num_cfg_resets: number of configuration resets
205
+
*/
206
+
struct rzg3s_pcie_soc_data {
207
+
int (*init_phy)(struct rzg3s_pcie_host *host);
208
+
const char * const *power_resets;
209
+
const char * const *cfg_resets;
210
+
u8 num_power_resets;
211
+
u8 num_cfg_resets;
212
+
};
213
+
214
+
/**
215
+
* struct rzg3s_pcie_port - RZ/G3S PCIe Root Port data structure
216
+
* @refclk: PCIe reference clock
217
+
* @vendor_id: Vendor ID
218
+
* @device_id: Device ID
219
+
*/
220
+
struct rzg3s_pcie_port {
221
+
struct clk *refclk;
222
+
u32 vendor_id;
223
+
u32 device_id;
224
+
};
225
+
226
+
/**
227
+
* struct rzg3s_pcie_host - RZ/G3S PCIe data structure
228
+
* @axi: base address for AXI registers
229
+
* @pcie: base address for PCIe registers
230
+
* @dev: struct device
231
+
* @power_resets: reset control signals that should be set after power up
232
+
* @cfg_resets: reset control signals that should be set after configuration
233
+
* @sysc: SYSC regmap
234
+
* @intx_domain: INTx IRQ domain
235
+
* @data: SoC specific data
236
+
* @msi: MSI data structure
237
+
* @port: PCIe Root Port
238
+
* @hw_lock: lock for access to the HW resources
239
+
* @intx_irqs: INTx interrupts
240
+
* @max_link_speed: maximum supported link speed
241
+
*/
242
+
struct rzg3s_pcie_host {
243
+
void __iomem *axi;
244
+
void __iomem *pcie;
245
+
struct device *dev;
246
+
struct reset_control_bulk_data *power_resets;
247
+
struct reset_control_bulk_data *cfg_resets;
248
+
struct regmap *sysc;
249
+
struct irq_domain *intx_domain;
250
+
const struct rzg3s_pcie_soc_data *data;
251
+
struct rzg3s_pcie_msi msi;
252
+
struct rzg3s_pcie_port port;
253
+
raw_spinlock_t hw_lock;
254
+
int intx_irqs[PCI_NUM_INTX];
255
+
int max_link_speed;
256
+
};
257
+
258
+
#define rzg3s_msi_to_host(_msi) container_of(_msi, struct rzg3s_pcie_host, msi)
259
+
260
+
static void rzg3s_pcie_update_bits(void __iomem *base, u32 offset, u32 mask,
261
+
u32 val)
262
+
{
263
+
u32 tmp;
264
+
265
+
tmp = readl_relaxed(base + offset);
266
+
tmp &= ~mask;
267
+
tmp |= val & mask;
268
+
writel_relaxed(tmp, base + offset);
269
+
}
270
+
271
+
static int rzg3s_pcie_child_issue_request(struct rzg3s_pcie_host *host)
272
+
{
273
+
u32 val;
274
+
int ret;
275
+
276
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_REQISS,
277
+
RZG3S_PCI_REQISS_REQ_ISSUE,
278
+
RZG3S_PCI_REQISS_REQ_ISSUE);
279
+
ret = readl_poll_timeout_atomic(host->axi + RZG3S_PCI_REQISS, val,
280
+
!(val & RZG3S_PCI_REQISS_REQ_ISSUE),
281
+
5, RZG3S_REQ_ISSUE_TIMEOUT_US);
282
+
283
+
if (val & RZG3S_PCI_REQISS_MOR_STATUS)
284
+
return -EIO;
285
+
286
+
return ret;
287
+
}
288
+
289
+
static void rzg3s_pcie_child_prepare_bus(struct pci_bus *bus,
290
+
unsigned int devfn, int where)
291
+
{
292
+
struct rzg3s_pcie_host *host = bus->sysdata;
293
+
unsigned int dev, func, reg;
294
+
295
+
dev = PCI_SLOT(devfn);
296
+
func = PCI_FUNC(devfn);
297
+
reg = where & ~0x3;
298
+
299
+
/* Set the destination */
300
+
writel_relaxed(FIELD_PREP(RZG3S_PCI_REQADR1_BUS, bus->number) |
301
+
FIELD_PREP(RZG3S_PCI_REQADR1_DEV, dev) |
302
+
FIELD_PREP(RZG3S_PCI_REQADR1_FUNC, func) |
303
+
FIELD_PREP(RZG3S_PCI_REQADR1_REG, reg),
304
+
host->axi + RZG3S_PCI_REQADR1);
305
+
306
+
/* Set byte enable */
307
+
writel_relaxed(RZG3S_PCI_REQBE_BYTE_EN, host->axi + RZG3S_PCI_REQBE);
308
+
}
309
+
310
+
static int rzg3s_pcie_child_read_conf(struct rzg3s_pcie_host *host,
311
+
struct pci_bus *bus, unsigned int devfn,
312
+
int where, u32 *data)
313
+
{
314
+
bool type0 = pci_is_root_bus(bus->parent) ? true : false;
315
+
int ret;
316
+
317
+
rzg3s_pcie_child_prepare_bus(bus, devfn, where);
318
+
319
+
/* Set the type of request */
320
+
writel_relaxed(type0 ? RZG3S_PCI_REQISS_TR_TP0_RD :
321
+
RZG3S_PCI_REQISS_TR_TP1_RD,
322
+
host->axi + RZG3S_PCI_REQISS);
323
+
324
+
/* Issue the request and wait to finish */
325
+
ret = rzg3s_pcie_child_issue_request(host);
326
+
if (ret)
327
+
return PCIBIOS_SET_FAILED;
328
+
329
+
/* Read the data */
330
+
*data = readl_relaxed(host->axi + RZG3S_PCI_REQRCVDAT);
331
+
332
+
return PCIBIOS_SUCCESSFUL;
333
+
}
334
+
335
+
/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
336
+
static int rzg3s_pcie_child_read(struct pci_bus *bus, unsigned int devfn,
337
+
int where, int size, u32 *val)
338
+
{
339
+
struct rzg3s_pcie_host *host = bus->sysdata;
340
+
int ret;
341
+
342
+
ret = rzg3s_pcie_child_read_conf(host, bus, devfn, where, val);
343
+
if (ret != PCIBIOS_SUCCESSFUL)
344
+
return ret;
345
+
346
+
if (size <= 2)
347
+
*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
348
+
349
+
return PCIBIOS_SUCCESSFUL;
350
+
}
351
+
352
+
static int rzg3s_pcie_child_write_conf(struct rzg3s_pcie_host *host,
353
+
struct pci_bus *bus, unsigned int devfn,
354
+
int where, u32 data)
355
+
{
356
+
bool type0 = pci_is_root_bus(bus->parent) ? true : false;
357
+
int ret;
358
+
359
+
rzg3s_pcie_child_prepare_bus(bus, devfn, where);
360
+
361
+
/* Set the write data */
362
+
writel_relaxed(0, host->axi + RZG3S_PCI_REQDATA(0));
363
+
writel_relaxed(0, host->axi + RZG3S_PCI_REQDATA(1));
364
+
writel_relaxed(data, host->axi + RZG3S_PCI_REQDATA(2));
365
+
366
+
/* Set the type of request */
367
+
writel_relaxed(type0 ? RZG3S_PCI_REQISS_TR_TP0_WR :
368
+
RZG3S_PCI_REQISS_TR_TP1_WR,
369
+
host->axi + RZG3S_PCI_REQISS);
370
+
371
+
/* Issue the request and wait to finish */
372
+
ret = rzg3s_pcie_child_issue_request(host);
373
+
if (ret)
374
+
return PCIBIOS_SET_FAILED;
375
+
376
+
return PCIBIOS_SUCCESSFUL;
377
+
}
378
+
379
+
/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
380
+
static int rzg3s_pcie_child_write(struct pci_bus *bus, unsigned int devfn,
381
+
int where, int size, u32 val)
382
+
{
383
+
struct rzg3s_pcie_host *host = bus->sysdata;
384
+
u32 data, shift;
385
+
int ret;
386
+
387
+
if (size == 4)
388
+
return rzg3s_pcie_child_write_conf(host, bus, devfn, where, val);
389
+
390
+
/*
391
+
* Controller does 32 bit accesses. To do byte accesses software need
392
+
* to do read/modify/write. This may have potential side effects. For
393
+
* example, software may perform a 16-bit write. If the hardware only
394
+
* supports 32-bit accesses, we must do a 32-bit read, merge in the 16
395
+
* bits we intend to write, followed by a 32-bit write. If the 16 bits
396
+
* we *don't* intend to write happen to have any RW1C
397
+
* (write-one-to-clear) bits set, we just inadvertently cleared
398
+
* something we shouldn't have.
399
+
*/
400
+
if (!bus->unsafe_warn) {
401
+
dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
402
+
size, pci_domain_nr(bus), bus->number,
403
+
PCI_SLOT(devfn), PCI_FUNC(devfn), where);
404
+
bus->unsafe_warn = 1;
405
+
}
406
+
407
+
ret = rzg3s_pcie_child_read_conf(host, bus, devfn, where, &data);
408
+
if (ret != PCIBIOS_SUCCESSFUL)
409
+
return ret;
410
+
411
+
if (size == 1) {
412
+
shift = BITS_PER_BYTE * (where & 3);
413
+
data &= ~(0xff << shift);
414
+
data |= ((val & 0xff) << shift);
415
+
} else if (size == 2) {
416
+
shift = BITS_PER_BYTE * (where & 2);
417
+
data &= ~(0xffff << shift);
418
+
data |= ((val & 0xffff) << shift);
419
+
} else {
420
+
data = val;
421
+
}
422
+
423
+
return rzg3s_pcie_child_write_conf(host, bus, devfn, where, data);
424
+
}
425
+
426
+
static struct pci_ops rzg3s_pcie_child_ops = {
427
+
.read = rzg3s_pcie_child_read,
428
+
.write = rzg3s_pcie_child_write,
429
+
};
430
+
431
+
static void __iomem *rzg3s_pcie_root_map_bus(struct pci_bus *bus,
432
+
unsigned int devfn, int where)
433
+
{
434
+
struct rzg3s_pcie_host *host = bus->sysdata;
435
+
436
+
if (devfn)
437
+
return NULL;
438
+
439
+
return host->pcie + where;
440
+
}
441
+
442
+
/* Serialized by 'pci_lock' */
443
+
static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
444
+
int where, int size, u32 val)
445
+
{
446
+
struct rzg3s_pcie_host *host = bus->sysdata;
447
+
int ret;
448
+
449
+
/* Enable access control to the CFGU */
450
+
writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
451
+
host->axi + RZG3S_PCI_PERM);
452
+
453
+
ret = pci_generic_config_write(bus, devfn, where, size, val);
454
+
455
+
/* Disable access control to the CFGU */
456
+
writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
457
+
458
+
return ret;
459
+
}
460
+
461
+
static struct pci_ops rzg3s_pcie_root_ops = {
462
+
.read = pci_generic_config_read,
463
+
.write = rzg3s_pcie_root_write,
464
+
.map_bus = rzg3s_pcie_root_map_bus,
465
+
};
466
+
467
+
static void rzg3s_pcie_intx_irq_handler(struct irq_desc *desc)
468
+
{
469
+
struct rzg3s_pcie_host *host = irq_desc_get_handler_data(desc);
470
+
struct irq_chip *chip = irq_desc_get_chip(desc);
471
+
unsigned int irq = irq_desc_get_irq(desc);
472
+
u32 intx = irq - host->intx_irqs[0];
473
+
474
+
chained_irq_enter(chip, desc);
475
+
generic_handle_domain_irq(host->intx_domain, intx);
476
+
chained_irq_exit(chip, desc);
477
+
}
478
+
479
+
static irqreturn_t rzg3s_pcie_msi_irq(int irq, void *data)
480
+
{
481
+
u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG;
482
+
DECLARE_BITMAP(bitmap, RZG3S_PCI_MSI_INT_NR);
483
+
struct rzg3s_pcie_host *host = data;
484
+
struct rzg3s_pcie_msi *msi = &host->msi;
485
+
unsigned long bit;
486
+
u32 status;
487
+
488
+
status = readl_relaxed(host->axi + RZG3S_PCI_PINTRCVIS);
489
+
if (!(status & RZG3S_PCI_PINTRCVIS_MSI))
490
+
return IRQ_NONE;
491
+
492
+
/* Clear the MSI */
493
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS,
494
+
RZG3S_PCI_PINTRCVIS_MSI,
495
+
RZG3S_PCI_PINTRCVIS_MSI);
496
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIS,
497
+
RZG3S_PCI_MSGRCVIS_MRI, RZG3S_PCI_MSGRCVIS_MRI);
498
+
499
+
for (u8 reg_id = 0; reg_id < regs; reg_id++) {
500
+
status = readl_relaxed(host->axi + RZG3S_PCI_MSIRS(reg_id));
501
+
bitmap_write(bitmap, status, reg_id * RZG3S_PCI_MSI_INT_PER_REG,
502
+
RZG3S_PCI_MSI_INT_PER_REG);
503
+
}
504
+
505
+
for_each_set_bit(bit, bitmap, RZG3S_PCI_MSI_INT_NR) {
506
+
int ret;
507
+
508
+
ret = generic_handle_domain_irq(msi->domain, bit);
509
+
if (ret) {
510
+
u8 reg_bit = bit % RZG3S_PCI_MSI_INT_PER_REG;
511
+
u8 reg_id = bit / RZG3S_PCI_MSI_INT_PER_REG;
512
+
513
+
/* Unknown MSI, just clear it */
514
+
writel_relaxed(BIT(reg_bit),
515
+
host->axi + RZG3S_PCI_MSIRS(reg_id));
516
+
}
517
+
}
518
+
519
+
return IRQ_HANDLED;
520
+
}
521
+
522
+
static void rzg3s_pcie_msi_irq_ack(struct irq_data *d)
523
+
{
524
+
struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d);
525
+
struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
526
+
u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG;
527
+
u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG;
528
+
529
+
guard(raw_spinlock_irqsave)(&host->hw_lock);
530
+
531
+
writel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id));
532
+
}
533
+
534
+
static void rzg3s_pcie_msi_irq_mask(struct irq_data *d)
535
+
{
536
+
struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d);
537
+
struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
538
+
u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG;
539
+
u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG;
540
+
541
+
guard(raw_spinlock_irqsave)(&host->hw_lock);
542
+
543
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit),
544
+
BIT(reg_bit));
545
+
}
546
+
547
+
static void rzg3s_pcie_msi_irq_unmask(struct irq_data *d)
548
+
{
549
+
struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d);
550
+
struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
551
+
u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG;
552
+
u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG;
553
+
554
+
guard(raw_spinlock_irqsave)(&host->hw_lock);
555
+
556
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit),
557
+
0);
558
+
}
559
+
560
+
static void rzg3s_pcie_irq_compose_msi_msg(struct irq_data *data,
561
+
struct msi_msg *msg)
562
+
{
563
+
struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(data);
564
+
struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
565
+
u32 lo, hi;
566
+
567
+
/*
568
+
* Enable and msg data enable bits are part of the address lo. Drop
569
+
* them along with the unused bit.
570
+
*/
571
+
lo = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRL) &
572
+
RZG3S_PCI_MSIRCVWADRL_MASK;
573
+
hi = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRU);
574
+
575
+
msg->address_lo = lo;
576
+
msg->address_hi = hi;
577
+
msg->data = data->hwirq;
578
+
}
579
+
580
+
static struct irq_chip rzg3s_pcie_msi_bottom_chip = {
581
+
.name = "rzg3s-pcie-msi",
582
+
.irq_ack = rzg3s_pcie_msi_irq_ack,
583
+
.irq_mask = rzg3s_pcie_msi_irq_mask,
584
+
.irq_unmask = rzg3s_pcie_msi_irq_unmask,
585
+
.irq_compose_msi_msg = rzg3s_pcie_irq_compose_msi_msg,
586
+
};
587
+
588
+
static int rzg3s_pcie_msi_domain_alloc(struct irq_domain *domain,
589
+
unsigned int virq, unsigned int nr_irqs,
590
+
void *args)
591
+
{
592
+
struct rzg3s_pcie_msi *msi = domain->host_data;
593
+
int hwirq;
594
+
595
+
scoped_guard(mutex, &msi->map_lock) {
596
+
hwirq = bitmap_find_free_region(msi->map, RZG3S_PCI_MSI_INT_NR,
597
+
order_base_2(nr_irqs));
598
+
}
599
+
600
+
if (hwirq < 0)
601
+
return -ENOSPC;
602
+
603
+
for (unsigned int i = 0; i < nr_irqs; i++) {
604
+
irq_domain_set_info(domain, virq + i, hwirq + i,
605
+
&rzg3s_pcie_msi_bottom_chip,
606
+
domain->host_data, handle_edge_irq, NULL,
607
+
NULL);
608
+
}
609
+
610
+
return 0;
611
+
}
612
+
613
+
static void rzg3s_pcie_msi_domain_free(struct irq_domain *domain,
614
+
unsigned int virq, unsigned int nr_irqs)
615
+
{
616
+
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
617
+
struct rzg3s_pcie_msi *msi = domain->host_data;
618
+
619
+
guard(mutex)(&msi->map_lock);
620
+
621
+
bitmap_release_region(msi->map, d->hwirq, order_base_2(nr_irqs));
622
+
}
623
+
624
+
static const struct irq_domain_ops rzg3s_pcie_msi_domain_ops = {
625
+
.alloc = rzg3s_pcie_msi_domain_alloc,
626
+
.free = rzg3s_pcie_msi_domain_free,
627
+
};
628
+
629
+
#define RZG3S_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
630
+
MSI_FLAG_USE_DEF_CHIP_OPS | \
631
+
MSI_FLAG_NO_AFFINITY | \
632
+
MSI_FLAG_PCI_MSI_MASK_PARENT)
633
+
634
+
#define RZG3S_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \
635
+
MSI_GENERIC_FLAGS_MASK)
636
+
637
+
static const struct msi_parent_ops rzg3s_pcie_msi_parent_ops = {
638
+
.required_flags = RZG3S_PCIE_MSI_FLAGS_REQUIRED,
639
+
.supported_flags = RZG3S_PCIE_MSI_FLAGS_SUPPORTED,
640
+
.bus_select_token = DOMAIN_BUS_PCI_MSI,
641
+
.chip_flags = MSI_CHIP_FLAG_SET_ACK,
642
+
.prefix = "RZG3S-",
643
+
.init_dev_msi_info = msi_lib_init_dev_msi_info,
644
+
};
645
+
646
+
static int rzg3s_pcie_msi_allocate_domains(struct rzg3s_pcie_msi *msi)
647
+
{
648
+
struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
649
+
struct device *dev = host->dev;
650
+
struct irq_domain_info info = {
651
+
.fwnode = dev_fwnode(dev),
652
+
.ops = &rzg3s_pcie_msi_domain_ops,
653
+
.size = RZG3S_PCI_MSI_INT_NR,
654
+
.host_data = msi,
655
+
};
656
+
657
+
msi->domain = msi_create_parent_irq_domain(&info,
658
+
&rzg3s_pcie_msi_parent_ops);
659
+
if (!msi->domain)
660
+
return dev_err_probe(dev, -ENOMEM,
661
+
"failed to create IRQ domain\n");
662
+
663
+
return 0;
664
+
}
665
+
666
+
static int rzg3s_pcie_msi_hw_setup(struct rzg3s_pcie_host *host)
667
+
{
668
+
u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG;
669
+
struct rzg3s_pcie_msi *msi = &host->msi;
670
+
671
+
/*
672
+
* Set MSI window size. HW will set the window to
673
+
* RZG3S_PCI_MSI_INT_NR * 4 bytes.
674
+
*/
675
+
writel_relaxed(FIELD_PREP(RZG3S_PCI_MSIRCVWMSKL_MASK,
676
+
RZG3S_PCI_MSI_INT_NR - 1),
677
+
host->axi + RZG3S_PCI_MSIRCVWMSKL);
678
+
679
+
/* Set MSI window address and enable MSI window */
680
+
writel_relaxed(upper_32_bits(msi->window_base),
681
+
host->axi + RZG3S_PCI_MSIRCVWADRU);
682
+
writel_relaxed(lower_32_bits(msi->window_base) |
683
+
RZG3S_PCI_MSIRCVWADRL_ENA |
684
+
RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA,
685
+
host->axi + RZG3S_PCI_MSIRCVWADRL);
686
+
687
+
/* Set MSI receive enable */
688
+
for (u8 reg_id = 0; reg_id < regs; reg_id++) {
689
+
writel_relaxed(RZG3S_PCI_MSIRE_ENA,
690
+
host->axi + RZG3S_PCI_MSIRE(reg_id));
691
+
}
692
+
693
+
/* Enable message receive interrupts */
694
+
writel_relaxed(RZG3S_PCI_MSGRCVIE_MSG_RCV,
695
+
host->axi + RZG3S_PCI_MSGRCVIE);
696
+
697
+
/* Enable MSI */
698
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE,
699
+
RZG3S_PCI_PINTRCVIE_MSI,
700
+
RZG3S_PCI_PINTRCVIE_MSI);
701
+
702
+
return 0;
703
+
}
704
+
705
+
static int rzg3s_pcie_msi_setup(struct rzg3s_pcie_host *host)
706
+
{
707
+
size_t size = RZG3S_PCI_MSI_INT_NR * sizeof(u32);
708
+
struct rzg3s_pcie_msi *msi = &host->msi;
709
+
struct device *dev = host->dev;
710
+
int id, ret;
711
+
712
+
msi->pages = __get_free_pages(GFP_KERNEL | GFP_DMA, 0);
713
+
if (!msi->pages)
714
+
return -ENOMEM;
715
+
716
+
msi->dma_addr = dma_map_single(dev, (void *)msi->pages, size * 2,
717
+
DMA_BIDIRECTIONAL);
718
+
if (dma_mapping_error(dev, msi->dma_addr)) {
719
+
ret = -ENOMEM;
720
+
goto free_pages;
721
+
}
722
+
723
+
/*
724
+
* According to the RZ/G3S HW manual (Rev.1.10, section 34.4.5.2 Setting
725
+
* the MSI Window) the MSI window needs to fall within one of the
726
+
* enabled AXI windows. Find an enabled AXI window to setup the MSI
727
+
* window.
728
+
*/
729
+
for (id = 0; id < RZG3S_MAX_WINDOWS; id++) {
730
+
u64 base, basel, baseu;
731
+
u64 mask, maskl, masku;
732
+
733
+
basel = readl_relaxed(host->axi + RZG3S_PCI_AWBASEL(id));
734
+
/* Skip checking this AXI window if it's not enabled */
735
+
if (!(basel & RZG3S_PCI_AWBASEL_WIN_ENA))
736
+
continue;
737
+
738
+
baseu = readl_relaxed(host->axi + RZG3S_PCI_AWBASEU(id));
739
+
base = baseu << 32 | basel;
740
+
741
+
maskl = readl_relaxed(host->axi + RZG3S_PCI_AWMASKL(id));
742
+
masku = readl_relaxed(host->axi + RZG3S_PCI_AWMASKU(id));
743
+
mask = masku << 32 | maskl;
744
+
745
+
if (msi->dma_addr < base || msi->dma_addr > base + mask)
746
+
continue;
747
+
748
+
break;
749
+
}
750
+
751
+
if (id == RZG3S_MAX_WINDOWS) {
752
+
ret = -EINVAL;
753
+
goto dma_unmap;
754
+
}
755
+
756
+
/* The MSI base address must be aligned to the MSI size */
757
+
msi->window_base = ALIGN(msi->dma_addr, size);
758
+
if (msi->window_base < msi->dma_addr) {
759
+
ret = -EINVAL;
760
+
goto dma_unmap;
761
+
}
762
+
763
+
rzg3s_pcie_msi_hw_setup(host);
764
+
765
+
return 0;
766
+
767
+
dma_unmap:
768
+
dma_unmap_single(dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL);
769
+
free_pages:
770
+
free_pages(msi->pages, 0);
771
+
return ret;
772
+
}
773
+
774
+
static void rzg3s_pcie_msi_hw_teardown(struct rzg3s_pcie_host *host)
775
+
{
776
+
u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG;
777
+
778
+
/* Disable MSI */
779
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE,
780
+
RZG3S_PCI_PINTRCVIE_MSI, 0);
781
+
782
+
/* Disable message receive interrupts */
783
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIE,
784
+
RZG3S_PCI_MSGRCVIE_MSG_RCV, 0);
785
+
786
+
/* Disable MSI receive enable */
787
+
for (u8 reg_id = 0; reg_id < regs; reg_id++)
788
+
writel_relaxed(0, host->axi + RZG3S_PCI_MSIRE(reg_id));
789
+
790
+
/* Disable MSI window */
791
+
writel_relaxed(0, host->axi + RZG3S_PCI_MSIRCVWADRL);
792
+
}
793
+
794
+
static void rzg3s_pcie_teardown_msi(struct rzg3s_pcie_host *host)
795
+
{
796
+
size_t size = RZG3S_PCI_MSI_INT_NR * sizeof(u32);
797
+
struct rzg3s_pcie_msi *msi = &host->msi;
798
+
799
+
rzg3s_pcie_msi_hw_teardown(host);
800
+
801
+
free_irq(msi->irq, host);
802
+
irq_domain_remove(msi->domain);
803
+
804
+
/* Free unused memory */
805
+
dma_unmap_single(host->dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL);
806
+
free_pages(msi->pages, 0);
807
+
}
808
+
809
+
static int rzg3s_pcie_init_msi(struct rzg3s_pcie_host *host)
810
+
{
811
+
struct platform_device *pdev = to_platform_device(host->dev);
812
+
struct rzg3s_pcie_msi *msi = &host->msi;
813
+
struct device *dev = host->dev;
814
+
const char *devname;
815
+
int ret;
816
+
817
+
ret = devm_mutex_init(dev, &msi->map_lock);
818
+
if (ret)
819
+
return ret;
820
+
821
+
msi->irq = platform_get_irq_byname(pdev, "msi");
822
+
if (msi->irq < 0)
823
+
return dev_err_probe(dev, msi->irq, "Failed to get MSI IRQ!\n");
824
+
825
+
devname = devm_kasprintf(dev, GFP_KERNEL, "%s-msi", dev_name(dev));
826
+
if (!devname)
827
+
return -ENOMEM;
828
+
829
+
ret = rzg3s_pcie_msi_allocate_domains(msi);
830
+
if (ret)
831
+
return ret;
832
+
833
+
/*
834
+
* Don't use devm_request_irq() as the driver uses non-devm helpers
835
+
* to control clocks. Mixing them may lead to subtle bugs.
836
+
*/
837
+
ret = request_irq(msi->irq, rzg3s_pcie_msi_irq, 0, devname, host);
838
+
if (ret) {
839
+
dev_err_probe(dev, ret, "Failed to request IRQ: %d\n", ret);
840
+
goto free_domains;
841
+
}
842
+
843
+
ret = rzg3s_pcie_msi_setup(host);
844
+
if (ret) {
845
+
dev_err_probe(dev, ret, "Failed to setup MSI!\n");
846
+
goto free_irq;
847
+
}
848
+
849
+
return 0;
850
+
851
+
free_irq:
852
+
free_irq(msi->irq, host);
853
+
free_domains:
854
+
irq_domain_remove(msi->domain);
855
+
return ret;
856
+
}
857
+
858
+
static void rzg3s_pcie_intx_irq_ack(struct irq_data *d)
859
+
{
860
+
struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d);
861
+
862
+
guard(raw_spinlock_irqsave)(&host->hw_lock);
863
+
864
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS,
865
+
RZG3S_PCI_PINTRCVIS_INTX(d->hwirq),
866
+
RZG3S_PCI_PINTRCVIS_INTX(d->hwirq));
867
+
}
868
+
869
+
static void rzg3s_pcie_intx_irq_mask(struct irq_data *d)
870
+
{
871
+
struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d);
872
+
873
+
guard(raw_spinlock_irqsave)(&host->hw_lock);
874
+
875
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE,
876
+
RZG3S_PCI_PINTRCVIE_INTX(d->hwirq), 0);
877
+
}
878
+
879
+
static void rzg3s_pcie_intx_irq_unmask(struct irq_data *d)
880
+
{
881
+
struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d);
882
+
883
+
guard(raw_spinlock_irqsave)(&host->hw_lock);
884
+
885
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE,
886
+
RZG3S_PCI_PINTRCVIE_INTX(d->hwirq),
887
+
RZG3S_PCI_PINTRCVIE_INTX(d->hwirq));
888
+
}
889
+
890
+
static struct irq_chip rzg3s_pcie_intx_irq_chip = {
891
+
.name = "PCIe INTx",
892
+
.irq_ack = rzg3s_pcie_intx_irq_ack,
893
+
.irq_mask = rzg3s_pcie_intx_irq_mask,
894
+
.irq_unmask = rzg3s_pcie_intx_irq_unmask,
895
+
};
896
+
897
+
static int rzg3s_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
898
+
irq_hw_number_t hwirq)
899
+
{
900
+
irq_set_chip_and_handler(irq, &rzg3s_pcie_intx_irq_chip,
901
+
handle_level_irq);
902
+
irq_set_chip_data(irq, domain->host_data);
903
+
904
+
return 0;
905
+
}
906
+
907
+
static const struct irq_domain_ops rzg3s_pcie_intx_domain_ops = {
908
+
.map = rzg3s_pcie_intx_map,
909
+
.xlate = irq_domain_xlate_onetwocell,
910
+
};
911
+
912
+
static int rzg3s_pcie_init_irqdomain(struct rzg3s_pcie_host *host)
913
+
{
914
+
struct device *dev = host->dev;
915
+
struct platform_device *pdev = to_platform_device(dev);
916
+
917
+
for (int i = 0; i < PCI_NUM_INTX; i++) {
918
+
char irq_name[5] = {0};
919
+
int irq;
920
+
921
+
scnprintf(irq_name, ARRAY_SIZE(irq_name), "int%c", 'a' + i);
922
+
923
+
irq = platform_get_irq_byname(pdev, irq_name);
924
+
if (irq < 0)
925
+
return dev_err_probe(dev, -EINVAL,
926
+
"Failed to parse and map INT%c IRQ\n",
927
+
'A' + i);
928
+
929
+
host->intx_irqs[i] = irq;
930
+
irq_set_chained_handler_and_data(irq,
931
+
rzg3s_pcie_intx_irq_handler,
932
+
host);
933
+
}
934
+
935
+
host->intx_domain = irq_domain_create_linear(dev_fwnode(dev),
936
+
PCI_NUM_INTX,
937
+
&rzg3s_pcie_intx_domain_ops,
938
+
host);
939
+
if (!host->intx_domain)
940
+
return dev_err_probe(dev, -EINVAL,
941
+
"Failed to add irq domain for INTx IRQs\n");
942
+
irq_domain_update_bus_token(host->intx_domain, DOMAIN_BUS_WIRED);
943
+
944
+
if (IS_ENABLED(CONFIG_PCI_MSI)) {
945
+
int ret = rzg3s_pcie_init_msi(host);
946
+
947
+
if (ret) {
948
+
irq_domain_remove(host->intx_domain);
949
+
return ret;
950
+
}
951
+
}
952
+
953
+
return 0;
954
+
}
955
+
956
+
static void rzg3s_pcie_teardown_irqdomain(struct rzg3s_pcie_host *host)
957
+
{
958
+
if (IS_ENABLED(CONFIG_PCI_MSI))
959
+
rzg3s_pcie_teardown_msi(host);
960
+
961
+
irq_domain_remove(host->intx_domain);
962
+
}
963
+
964
+
static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host)
965
+
{
966
+
u32 remote_supported_link_speeds, max_supported_link_speeds;
967
+
u32 cs2, tmp, pcie_cap = RZG3S_PCI_CFG_PCIEC;
968
+
u32 cur_link_speed, link_speed;
969
+
u8 ltssm_state_l0 = 0xc;
970
+
int ret;
971
+
u16 ls;
972
+
973
+
/*
974
+
* According to the RZ/G3S HW manual (Rev.1.10, section 34.6.3 Caution
975
+
* when Changing the Speed Spontaneously) link speed change can be done
976
+
* only when the LTSSM is in L0.
977
+
*/
978
+
ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, tmp,
979
+
FIELD_GET(RZG3S_PCI_PCSTAT1_LTSSM_STATE, tmp) == ltssm_state_l0,
980
+
PCIE_LINK_WAIT_SLEEP_MS * MILLI,
981
+
PCIE_LINK_WAIT_SLEEP_MS * MILLI *
982
+
PCIE_LINK_WAIT_MAX_RETRIES);
983
+
if (ret)
984
+
return ret;
985
+
986
+
ls = readw_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKSTA);
987
+
cs2 = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2);
988
+
989
+
switch (pcie_link_speed[host->max_link_speed]) {
990
+
case PCIE_SPEED_5_0GT:
991
+
max_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_5_0GB - 1, 0);
992
+
link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
993
+
break;
994
+
default:
995
+
/* Should not happen */
996
+
return -EINVAL;
997
+
}
998
+
999
+
cur_link_speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, ls);
1000
+
remote_supported_link_speeds = FIELD_GET(RZG3S_PCI_PCSTAT2_SDRIRE, cs2);
1001
+
/* Drop reserved bits */
1002
+
remote_supported_link_speeds &= max_supported_link_speeds;
1003
+
1004
+
/*
1005
+
* Return if max link speed is already set or the connected device
1006
+
* doesn't support it.
1007
+
*/
1008
+
if (cur_link_speed == host->max_link_speed ||
1009
+
remote_supported_link_speeds != max_supported_link_speeds)
1010
+
return 0;
1011
+
1012
+
/* Set target Link speed */
1013
+
rzg3s_pcie_update_bits(host->pcie, pcie_cap + PCI_EXP_LNKCTL2,
1014
+
PCI_EXP_LNKCTL2_TLS,
1015
+
FIELD_PREP(PCI_EXP_LNKCTL2_TLS, link_speed));
1016
+
1017
+
/* Request link speed change */
1018
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2,
1019
+
RZG3S_PCI_PCCTRL2_LS_CHG_REQ |
1020
+
RZG3S_PCI_PCCTRL2_LS_CHG,
1021
+
RZG3S_PCI_PCCTRL2_LS_CHG_REQ |
1022
+
FIELD_PREP(RZG3S_PCI_PCCTRL2_LS_CHG,
1023
+
link_speed - 1));
1024
+
1025
+
ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT2, cs2,
1026
+
(cs2 & RZG3S_PCI_PCSTAT2_LS_CHG_DONE),
1027
+
PCIE_LINK_WAIT_SLEEP_MS * MILLI,
1028
+
PCIE_LINK_WAIT_SLEEP_MS * MILLI *
1029
+
PCIE_LINK_WAIT_MAX_RETRIES);
1030
+
1031
+
/*
1032
+
* According to the RZ/G3S HW manual (Rev.1.10, section 34.6.3 Caution
1033
+
* when Changing the Speed Spontaneously) the PCI_PCCTRL2_LS_CHG_REQ
1034
+
* should be de-asserted after checking for PCI_PCSTAT2_LS_CHG_DONE.
1035
+
*/
1036
+
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2,
1037
+
RZG3S_PCI_PCCTRL2_LS_CHG_REQ, 0);
1038
+
1039
+
return ret;
1040
+
}
1041
+
1042
+
static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)
1043
+
{
1044
+
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
1045
+
struct resource_entry *ft;
1046
+
struct resource *bus;
1047
+
u8 subordinate_bus;
1048
+
u8 secondary_bus;
1049
+
u8 primary_bus;
1050
+
1051
+
ft = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
1052
+
if (!ft)
1053
+
return -ENODEV;
1054
+
1055
+
bus = ft->res;
1056
+
primary_bus = bus->start;
1057
+
secondary_bus = bus->start + 1;
1058
+
subordinate_bus = bus->end;
1059
+
1060
+
/* Enable access control to the CFGU */
1061
+
writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
1062
+
host->axi + RZG3S_PCI_PERM);
1063
+
1064
+
/* HW manual recommends to write 0xffffffff on initialization */
1065
+
writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
1066
+
writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);
1067
+
1068
+
/* Update bus info */
1069
+
writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);
1070
+
writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);
1071
+
writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);
1072
+
1073
+
/* Disable access control to the CFGU */
1074
+
writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
1075
+
1076
+
return 0;
1077
+
}
1078
+
1079
+
static void rzg3s_pcie_irq_init(struct rzg3s_pcie_host *host)
1080
+
{
1081
+
/*
1082
+
* According to the HW manual of the RZ/G3S (Rev.1.10, sections
1083
+
* corresponding to all registers written with ~0U), the hardware
1084
+
* ignores value written to unused bits. Writing ~0U to these registers
1085
+
* should be safe.
1086
+
*/
1087
+
1088
+
/* Clear the link state and PM transitions */
1089
+
writel_relaxed(RZG3S_PCI_PEIS0_DL_UPDOWN |
1090
+
RZG3S_PCI_PEIS0_RX_DLLP_PM_ENTER,
1091
+
host->axi + RZG3S_PCI_PEIS0);
1092
+
1093
+
/* Disable all interrupts */
1094
+
writel_relaxed(0, host->axi + RZG3S_PCI_PEIE0);
1095
+
1096
+
/* Clear all parity and ecc error interrupts */
1097
+
writel_relaxed(~0U, host->axi + RZG3S_PCI_PEIS1);
1098
+
1099
+
/* Disable all parity and ecc error interrupts */
1100
+
writel_relaxed(0, host->axi + RZG3S_PCI_PEIE1);
1101
+
1102
+
/* Clear all AXI master error interrupts */
1103
+
writel_relaxed(~0U, host->axi + RZG3S_PCI_AMEIS);
1104
+
1105
+
/* Clear all AXI slave error interrupts */
1106
+
writel_relaxed(~0U, host->axi + RZG3S_PCI_ASEIS1);
1107
+
1108
+
/* Clear all message receive interrupts */
1109
+
writel_relaxed(~0U, host->axi + RZG3S_PCI_MSGRCVIS);
1110
+
}
1111
+
1112
+
static int rzg3s_pcie_power_resets_deassert(struct rzg3s_pcie_host *host)
1113
+
{
1114
+
const struct rzg3s_pcie_soc_data *data = host->data;
1115
+
1116
+
/*
1117
+
* According to the RZ/G3S HW manual (Rev.1.10, section
1118
+
* 34.5.1.2 De-asserting the Reset) the PCIe IP needs to wait 5ms from
1119
+
* power on to the de-assertion of reset.
1120
+
*/
1121
+
fsleep(5000);
1122
+
return reset_control_bulk_deassert(data->num_power_resets,
1123
+
host->power_resets);
1124
+
}
1125
+
1126
+
static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host)
1127
+
{
1128
+
const struct rzg3s_pcie_soc_data *data = host->data;
1129
+
unsigned int i;
1130
+
int ret;
1131
+
1132
+
host->power_resets = devm_kmalloc_array(host->dev,
1133
+
data->num_power_resets,
1134
+
sizeof(*host->power_resets),
1135
+
GFP_KERNEL);
1136
+
if (!host->power_resets)
1137
+
return -ENOMEM;
1138
+
1139
+
for (i = 0; i < data->num_power_resets; i++)
1140
+
host->power_resets[i].id = data->power_resets[i];
1141
+
1142
+
host->cfg_resets = devm_kmalloc_array(host->dev,
1143
+
data->num_cfg_resets,
1144
+
sizeof(*host->cfg_resets),
1145
+
GFP_KERNEL);
1146
+
if (!host->cfg_resets)
1147
+
return -ENOMEM;
1148
+
1149
+
for (i = 0; i < data->num_cfg_resets; i++)
1150
+
host->cfg_resets[i].id = data->cfg_resets[i];
1151
+
1152
+
ret = devm_reset_control_bulk_get_exclusive(host->dev,
1153
+
data->num_power_resets,
1154
+
host->power_resets);
1155
+
if (ret)
1156
+
return ret;
1157
+
1158
+
return devm_reset_control_bulk_get_exclusive(host->dev,
1159
+
data->num_cfg_resets,
1160
+
host->cfg_resets);
1161
+
}
1162
+
1163
+
static int rzg3s_pcie_host_parse_port(struct rzg3s_pcie_host *host)
1164
+
{
1165
+
struct device_node *of_port = of_get_next_child(host->dev->of_node, NULL);
1166
+
struct rzg3s_pcie_port *port = &host->port;
1167
+
int ret;
1168
+
1169
+
ret = of_property_read_u32(of_port, "vendor-id", &port->vendor_id);
1170
+
if (ret)
1171
+
return ret;
1172
+
1173
+
ret = of_property_read_u32(of_port, "device-id", &port->device_id);
1174
+
if (ret)
1175
+
return ret;
1176
+
1177
+
port->refclk = of_clk_get_by_name(of_port, "ref");
1178
+
if (IS_ERR(port->refclk))
1179
+
return PTR_ERR(port->refclk);
1180
+
1181
+
return 0;
1182
+
}
1183
+
1184
+
static int rzg3s_pcie_host_init_port(struct rzg3s_pcie_host *host)
1185
+
{
1186
+
struct rzg3s_pcie_port *port = &host->port;
1187
+
struct device *dev = host->dev;
1188
+
int ret;
1189
+
1190
+
/* Enable access control to the CFGU */
1191
+
writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
1192
+
host->axi + RZG3S_PCI_PERM);
1193
+
1194
+
/* Update vendor ID and device ID */
1195
+
writew_relaxed(port->vendor_id, host->pcie + PCI_VENDOR_ID);
1196
+
writew_relaxed(port->device_id, host->pcie + PCI_DEVICE_ID);
1197
+
1198
+
/* Disable access control to the CFGU */
1199
+
writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
1200
+
1201
+
ret = clk_prepare_enable(port->refclk);
1202
+
if (ret)
1203
+
return dev_err_probe(dev, ret, "Failed to enable refclk!\n");
1204
+
1205
+
/* Set the PHY, if any */
1206
+
if (host->data->init_phy) {
1207
+
ret = host->data->init_phy(host);
1208
+
if (ret) {
1209
+
dev_err_probe(dev, ret, "Failed to set the PHY!\n");
1210
+
goto refclk_disable;
1211
+
}
1212
+
}
1213
+
1214
+
return 0;
1215
+
1216
+
refclk_disable:
1217
+
clk_disable_unprepare(port->refclk);
1218
+
return ret;
1219
+
}
1220
+
1221
+
static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
1222
+
{
1223
+
u32 val;
1224
+
int ret;
1225
+
1226
+
/* Initialize the PCIe related registers */
1227
+
ret = rzg3s_pcie_config_init(host);
1228
+
if (ret)
1229
+
return ret;
1230
+
1231
+
ret = rzg3s_pcie_host_init_port(host);
1232
+
if (ret)
1233
+
return ret;
1234
+
1235
+
/* Initialize the interrupts */
1236
+
rzg3s_pcie_irq_init(host);
1237
+
1238
+
ret = reset_control_bulk_deassert(host->data->num_cfg_resets,
1239
+
host->cfg_resets);
1240
+
if (ret)
1241
+
goto disable_port_refclk;
1242
+
1243
+
/* Wait for link up */
1244
+
ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, val,
1245
+
!(val & RZG3S_PCI_PCSTAT1_DL_DOWN_STS),
1246
+
PCIE_LINK_WAIT_SLEEP_MS * MILLI,
1247
+
PCIE_LINK_WAIT_SLEEP_MS * MILLI *
1248
+
PCIE_LINK_WAIT_MAX_RETRIES);
1249
+
if (ret)
1250
+
goto cfg_resets_deassert;
1251
+
1252
+
val = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2);
1253
+
dev_info(host->dev, "PCIe link status [0x%x]\n", val);
1254
+
1255
+
return 0;
1256
+
1257
+
cfg_resets_deassert:
1258
+
reset_control_bulk_assert(host->data->num_cfg_resets,
1259
+
host->cfg_resets);
1260
+
disable_port_refclk:
1261
+
clk_disable_unprepare(host->port.refclk);
1262
+
return ret;
1263
+
}
1264
+
1265
+
static void rzg3s_pcie_set_inbound_window(struct rzg3s_pcie_host *host,
1266
+
u64 cpu_addr, u64 pci_addr, u64 size,
1267
+
int id)
1268
+
{
1269
+
/* Set CPU window base address */
1270
+
writel_relaxed(upper_32_bits(cpu_addr),
1271
+
host->axi + RZG3S_PCI_ADESTU(id));
1272
+
writel_relaxed(lower_32_bits(cpu_addr),
1273
+
host->axi + RZG3S_PCI_ADESTL(id));
1274
+
1275
+
/* Set window size */
1276
+
writel_relaxed(upper_32_bits(size), host->axi + RZG3S_PCI_AWMASKU(id));
1277
+
writel_relaxed(lower_32_bits(size), host->axi + RZG3S_PCI_AWMASKL(id));
1278
+
1279
+
/* Set PCIe window base address and enable the window */
1280
+
writel_relaxed(upper_32_bits(pci_addr),
1281
+
host->axi + RZG3S_PCI_AWBASEU(id));
1282
+
writel_relaxed(lower_32_bits(pci_addr) | RZG3S_PCI_AWBASEL_WIN_ENA,
1283
+
host->axi + RZG3S_PCI_AWBASEL(id));
1284
+
}
1285
+
1286
+
static int rzg3s_pcie_set_inbound_windows(struct rzg3s_pcie_host *host,
1287
+
struct resource_entry *entry,
1288
+
int *index)
1289
+
{
1290
+
u64 pci_addr = entry->res->start - entry->offset;
1291
+
u64 cpu_addr = entry->res->start;
1292
+
u64 cpu_end = entry->res->end;
1293
+
u64 size_id = 0;
1294
+
int id = *index;
1295
+
u64 size;
1296
+
1297
+
while (cpu_addr < cpu_end) {
1298
+
if (id >= RZG3S_MAX_WINDOWS)
1299
+
return dev_err_probe(host->dev, -ENOSPC,
1300
+
"Failed to map inbound window for resource (%s)\n",
1301
+
entry->res->name);
1302
+
1303
+
size = resource_size(entry->res) - size_id;
1304
+
1305
+
/*
1306
+
* According to the RZ/G3S HW manual (Rev.1.10,
1307
+
* section 34.3.1.71 AXI Window Mask (Lower) Registers) the min
1308
+
* size is 4K.
1309
+
*/
1310
+
size = max(size, SZ_4K);
1311
+
1312
+
/*
1313
+
* According the RZ/G3S HW manual (Rev.1.10, sections:
1314
+
* - 34.3.1.69 AXI Window Base (Lower) Registers
1315
+
* - 34.3.1.71 AXI Window Mask (Lower) Registers
1316
+
* - 34.3.1.73 AXI Destination (Lower) Registers)
1317
+
* the CPU addr, PCIe addr, size should be 4K aligned and be a
1318
+
* power of 2.
1319
+
*/
1320
+
size = ALIGN(size, SZ_4K);
1321
+
size = roundup_pow_of_two(size);
1322
+
1323
+
cpu_addr = ALIGN(cpu_addr, SZ_4K);
1324
+
pci_addr = ALIGN(pci_addr, SZ_4K);
1325
+
1326
+
/*
1327
+
* According to the RZ/G3S HW manual (Rev.1.10, section
1328
+
* 34.3.1.71 AXI Window Mask (Lower) Registers) HW expects first
1329
+
* 12 LSB bits to be 0xfff. Subtract 1 from size for this.
1330
+
*/
1331
+
rzg3s_pcie_set_inbound_window(host, cpu_addr, pci_addr,
1332
+
size - 1, id);
1333
+
1334
+
pci_addr += size;
1335
+
cpu_addr += size;
1336
+
size_id = size;
1337
+
id++;
1338
+
}
1339
+
*index = id;
1340
+
1341
+
return 0;
1342
+
}
1343
+
1344
+
static int rzg3s_pcie_parse_map_dma_ranges(struct rzg3s_pcie_host *host)
1345
+
{
1346
+
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
1347
+
struct resource_entry *entry;
1348
+
int i = 0, ret;
1349
+
1350
+
resource_list_for_each_entry(entry, &bridge->dma_ranges) {
1351
+
ret = rzg3s_pcie_set_inbound_windows(host, entry, &i);
1352
+
if (ret)
1353
+
return ret;
1354
+
}
1355
+
1356
+
return 0;
1357
+
}
1358
+
1359
+
static void rzg3s_pcie_set_outbound_window(struct rzg3s_pcie_host *host,
1360
+
struct resource_entry *win, int id)
1361
+
{
1362
+
struct resource *res = win->res;
1363
+
resource_size_t size = resource_size(res);
1364
+
resource_size_t res_start;
1365
+
1366
+
if (res->flags & IORESOURCE_IO)
1367
+
res_start = pci_pio_to_address(res->start) - win->offset;
1368
+
else
1369
+
res_start = res->start - win->offset;
1370
+
1371
+
/*
1372
+
* According to the RZ/G3S HW manual (Rev.1.10, section 34.3.1.75 PCIe
1373
+
* Window Base (Lower) Registers) the window base address need to be 4K
1374
+
* aligned.
1375
+
*/
1376
+
res_start = ALIGN(res_start, SZ_4K);
1377
+
1378
+
size = ALIGN(size, SZ_4K);
1379
+
size = roundup_pow_of_two(size) - 1;
1380
+
1381
+
/* Set PCIe destination */
1382
+
writel_relaxed(upper_32_bits(res_start),
1383
+
host->axi + RZG3S_PCI_PDESTU(id));
1384
+
writel_relaxed(lower_32_bits(res_start),
1385
+
host->axi + RZG3S_PCI_PDESTL(id));
1386
+
1387
+
/* Set PCIe window mask */
1388
+
writel_relaxed(upper_32_bits(size), host->axi + RZG3S_PCI_PWMASKU(id));
1389
+
writel_relaxed(lower_32_bits(size), host->axi + RZG3S_PCI_PWMASKL(id));
1390
+
1391
+
/* Set PCIe window base and enable the window */
1392
+
writel_relaxed(upper_32_bits(res_start),
1393
+
host->axi + RZG3S_PCI_PWBASEU(id));
1394
+
writel_relaxed(lower_32_bits(res_start) | RZG3S_PCI_PWBASEL_ENA,
1395
+
host->axi + RZG3S_PCI_PWBASEL(id));
1396
+
}
1397
+
1398
+
static int rzg3s_pcie_parse_map_ranges(struct rzg3s_pcie_host *host)
1399
+
{
1400
+
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
1401
+
struct resource_entry *win;
1402
+
int i = 0;
1403
+
1404
+
resource_list_for_each_entry(win, &bridge->windows) {
1405
+
struct resource *res = win->res;
1406
+
1407
+
if (i >= RZG3S_MAX_WINDOWS)
1408
+
return dev_err_probe(host->dev, -ENOSPC,
1409
+
"Failed to map outbound window for resource (%s)\n",
1410
+
res->name);
1411
+
1412
+
if (!res->flags)
1413
+
continue;
1414
+
1415
+
switch (resource_type(res)) {
1416
+
case IORESOURCE_IO:
1417
+
case IORESOURCE_MEM:
1418
+
rzg3s_pcie_set_outbound_window(host, win, i);
1419
+
i++;
1420
+
break;
1421
+
}
1422
+
}
1423
+
1424
+
return 0;
1425
+
}
1426
+
1427
+
static int rzg3s_soc_pcie_init_phy(struct rzg3s_pcie_host *host)
1428
+
{
1429
+
static const u32 xcfgd_settings[RZG3S_PCI_PHY_XCFGD_NUM] = {
1430
+
[8] = 0xe0006801, 0x007f7e30, 0x183e0000, 0x978ff500,
1431
+
0xec000000, 0x009f1400, 0x0000d009,
1432
+
[17] = 0x78000000,
1433
+
[19] = 0x00880000, 0x000005c0, 0x07000000, 0x00780920,
1434
+
0xc9400ce2, 0x90000c0c, 0x000c1414, 0x00005034,
1435
+
0x00006000, 0x00000001,
1436
+
};
1437
+
static const u32 xcfga_cmn_settings[RZG3S_PCI_PHY_XCFGA_CMN_NUM] = {
1438
+
0x00000d10, 0x08310100, 0x00c21404, 0x013c0010, 0x01874440,
1439
+
0x1a216082, 0x00103440, 0x00000080, 0x00000010, 0x0c1000c1,
1440
+
0x1000c100, 0x0222000c, 0x00640019, 0x00a00028, 0x01d11228,
1441
+
0x0201001d,
1442
+
};
1443
+
static const u32 xcfga_rx_settings[RZG3S_PCI_PHY_XCFGA_RX_NUM] = {
1444
+
0x07d55000, 0x030e3f00, 0x00000288, 0x102c5880, 0x0000000b,
1445
+
0x04141441, 0x00641641, 0x00d63d63, 0x00641641, 0x01970377,
1446
+
0x00190287, 0x00190028, 0x00000028,
1447
+
};
1448
+
unsigned int i;
1449
+
1450
+
/*
1451
+
* Enable access permission for physical layer control and status
1452
+
* registers.
1453
+
*/
1454
+
writel_relaxed(RZG3S_PCI_PERM_PIPE_PHY_REG_EN,
1455
+
host->axi + RZG3S_PCI_PERM);
1456
+
1457
+
for (i = 0; i < RZG3S_PCI_PHY_XCFGD_NUM; i++) {
1458
+
writel_relaxed(xcfgd_settings[i],
1459
+
host->axi + RZG3S_PCI_PHY_XCFGD(i));
1460
+
}
1461
+
1462
+
for (i = 0; i < RZG3S_PCI_PHY_XCFGA_CMN_NUM; i++) {
1463
+
writel_relaxed(xcfga_cmn_settings[i],
1464
+
host->axi + RZG3S_PCI_PHY_XCFGA_CMN(i));
1465
+
}
1466
+
1467
+
for (i = 0; i < RZG3S_PCI_PHY_XCFGA_RX_NUM; i++) {
1468
+
writel_relaxed(xcfga_rx_settings[i],
1469
+
host->axi + RZG3S_PCI_PHY_XCFGA_RX(i));
1470
+
}
1471
+
1472
+
writel_relaxed(0x107, host->axi + RZG3S_PCI_PHY_XCFGA_TX);
1473
+
1474
+
/* Select PHY settings values */
1475
+
writel_relaxed(RZG3S_PCI_PHY_XCFG_CTRL_PHYREG_SEL,
1476
+
host->axi + RZG3S_PCI_PHY_XCFG_CTRL);
1477
+
1478
+
/*
1479
+
* Disable access permission for physical layer control and status
1480
+
* registers.
1481
+
*/
1482
+
writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
1483
+
1484
+
return 0;
1485
+
}
1486
+
1487
+
static int
1488
+
rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host,
1489
+
int (*init_irqdomain)(struct rzg3s_pcie_host *host),
1490
+
void (*teardown_irqdomain)(struct rzg3s_pcie_host *host))
1491
+
{
1492
+
struct device *dev = host->dev;
1493
+
int ret;
1494
+
1495
+
/* Set inbound windows */
1496
+
ret = rzg3s_pcie_parse_map_dma_ranges(host);
1497
+
if (ret)
1498
+
return dev_err_probe(dev, ret,
1499
+
"Failed to set inbound windows!\n");
1500
+
1501
+
/* Set outbound windows */
1502
+
ret = rzg3s_pcie_parse_map_ranges(host);
1503
+
if (ret)
1504
+
return dev_err_probe(dev, ret,
1505
+
"Failed to set outbound windows!\n");
1506
+
1507
+
ret = init_irqdomain(host);
1508
+
if (ret)
1509
+
return dev_err_probe(dev, ret, "Failed to init IRQ domain\n");
1510
+
1511
+
ret = rzg3s_pcie_host_init(host);
1512
+
if (ret) {
1513
+
dev_err_probe(dev, ret, "Failed to initialize the HW!\n");
1514
+
goto teardown_irqdomain;
1515
+
}
1516
+
1517
+
ret = rzg3s_pcie_set_max_link_speed(host);
1518
+
if (ret)
1519
+
dev_info(dev, "Failed to set max link speed\n");
1520
+
1521
+
msleep(PCIE_RESET_CONFIG_WAIT_MS);
1522
+
1523
+
return 0;
1524
+
1525
+
teardown_irqdomain:
1526
+
teardown_irqdomain(host);
1527
+
1528
+
return ret;
1529
+
}
1530
+
1531
+
static int rzg3s_pcie_probe(struct platform_device *pdev)
1532
+
{
1533
+
struct pci_host_bridge *bridge;
1534
+
struct device *dev = &pdev->dev;
1535
+
struct device_node *np = dev->of_node;
1536
+
struct device_node *sysc_np __free(device_node) =
1537
+
of_parse_phandle(np, "renesas,sysc", 0);
1538
+
struct rzg3s_pcie_host *host;
1539
+
int ret;
1540
+
1541
+
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host));
1542
+
if (!bridge)
1543
+
return -ENOMEM;
1544
+
1545
+
host = pci_host_bridge_priv(bridge);
1546
+
host->dev = dev;
1547
+
host->data = device_get_match_data(dev);
1548
+
platform_set_drvdata(pdev, host);
1549
+
1550
+
host->axi = devm_platform_ioremap_resource(pdev, 0);
1551
+
if (IS_ERR(host->axi))
1552
+
return PTR_ERR(host->axi);
1553
+
host->pcie = host->axi + RZG3S_PCI_CFG_BASE;
1554
+
1555
+
host->max_link_speed = of_pci_get_max_link_speed(np);
1556
+
if (host->max_link_speed < 0)
1557
+
host->max_link_speed = 2;
1558
+
1559
+
ret = rzg3s_pcie_host_parse_port(host);
1560
+
if (ret)
1561
+
return ret;
1562
+
1563
+
host->sysc = syscon_node_to_regmap(sysc_np);
1564
+
if (IS_ERR(host->sysc)) {
1565
+
ret = PTR_ERR(host->sysc);
1566
+
goto port_refclk_put;
1567
+
}
1568
+
1569
+
ret = regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B,
1570
+
RZG3S_SYS_PCIE_RST_RSM_B_MASK,
1571
+
FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1));
1572
+
if (ret)
1573
+
goto port_refclk_put;
1574
+
1575
+
ret = rzg3s_pcie_resets_prepare_and_get(host);
1576
+
if (ret)
1577
+
goto sysc_signal_restore;
1578
+
1579
+
ret = rzg3s_pcie_power_resets_deassert(host);
1580
+
if (ret)
1581
+
goto sysc_signal_restore;
1582
+
1583
+
pm_runtime_enable(dev);
1584
+
1585
+
/*
1586
+
* Controller clocks are part of a clock power domain. Enable them
1587
+
* through runtime PM.
1588
+
*/
1589
+
ret = pm_runtime_resume_and_get(dev);
1590
+
if (ret)
1591
+
goto rpm_disable;
1592
+
1593
+
raw_spin_lock_init(&host->hw_lock);
1594
+
1595
+
ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_init_irqdomain,
1596
+
rzg3s_pcie_teardown_irqdomain);
1597
+
if (ret)
1598
+
goto rpm_put;
1599
+
1600
+
bridge->sysdata = host;
1601
+
bridge->ops = &rzg3s_pcie_root_ops;
1602
+
bridge->child_ops = &rzg3s_pcie_child_ops;
1603
+
ret = pci_host_probe(bridge);
1604
+
if (ret)
1605
+
goto host_probe_teardown;
1606
+
1607
+
return 0;
1608
+
1609
+
host_probe_teardown:
1610
+
rzg3s_pcie_teardown_irqdomain(host);
1611
+
reset_control_bulk_deassert(host->data->num_cfg_resets,
1612
+
host->cfg_resets);
1613
+
rpm_put:
1614
+
pm_runtime_put_sync(dev);
1615
+
rpm_disable:
1616
+
pm_runtime_disable(dev);
1617
+
reset_control_bulk_assert(host->data->num_power_resets,
1618
+
host->power_resets);
1619
+
sysc_signal_restore:
1620
+
/*
1621
+
* SYSC RST_RSM_B signal need to be asserted before turning off the
1622
+
* power to the PHY.
1623
+
*/
1624
+
regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B,
1625
+
RZG3S_SYS_PCIE_RST_RSM_B_MASK,
1626
+
FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));
1627
+
port_refclk_put:
1628
+
clk_put(host->port.refclk);
1629
+
1630
+
return ret;
1631
+
}
1632
+
1633
+
static int rzg3s_pcie_suspend_noirq(struct device *dev)
1634
+
{
1635
+
struct rzg3s_pcie_host *host = dev_get_drvdata(dev);
1636
+
const struct rzg3s_pcie_soc_data *data = host->data;
1637
+
struct rzg3s_pcie_port *port = &host->port;
1638
+
struct regmap *sysc = host->sysc;
1639
+
int ret;
1640
+
1641
+
ret = pm_runtime_put_sync(dev);
1642
+
if (ret)
1643
+
return ret;
1644
+
1645
+
clk_disable_unprepare(port->refclk);
1646
+
1647
+
ret = reset_control_bulk_assert(data->num_power_resets,
1648
+
host->power_resets);
1649
+
if (ret)
1650
+
goto refclk_restore;
1651
+
1652
+
ret = reset_control_bulk_assert(data->num_cfg_resets,
1653
+
host->cfg_resets);
1654
+
if (ret)
1655
+
goto power_resets_restore;
1656
+
1657
+
ret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,
1658
+
RZG3S_SYS_PCIE_RST_RSM_B_MASK,
1659
+
FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));
1660
+
if (ret)
1661
+
goto cfg_resets_restore;
1662
+
1663
+
return 0;
1664
+
1665
+
/* Restore the previous state if any error happens */
1666
+
cfg_resets_restore:
1667
+
reset_control_bulk_deassert(data->num_cfg_resets,
1668
+
host->cfg_resets);
1669
+
power_resets_restore:
1670
+
reset_control_bulk_deassert(data->num_power_resets,
1671
+
host->power_resets);
1672
+
refclk_restore:
1673
+
clk_prepare_enable(port->refclk);
1674
+
pm_runtime_resume_and_get(dev);
1675
+
return ret;
1676
+
}
1677
+
1678
+
static int rzg3s_pcie_resume_noirq(struct device *dev)
1679
+
{
1680
+
struct rzg3s_pcie_host *host = dev_get_drvdata(dev);
1681
+
const struct rzg3s_pcie_soc_data *data = host->data;
1682
+
struct regmap *sysc = host->sysc;
1683
+
int ret;
1684
+
1685
+
ret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,
1686
+
RZG3S_SYS_PCIE_RST_RSM_B_MASK,
1687
+
FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1));
1688
+
if (ret)
1689
+
return ret;
1690
+
1691
+
ret = rzg3s_pcie_power_resets_deassert(host);
1692
+
if (ret)
1693
+
goto assert_rst_rsm_b;
1694
+
1695
+
ret = pm_runtime_resume_and_get(dev);
1696
+
if (ret)
1697
+
goto assert_power_resets;
1698
+
1699
+
ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_msi_hw_setup,
1700
+
rzg3s_pcie_msi_hw_teardown);
1701
+
if (ret)
1702
+
goto rpm_put;
1703
+
1704
+
return 0;
1705
+
1706
+
/*
1707
+
* If any error happens there is no way to recover the IP. Put it in the
1708
+
* lowest possible power state.
1709
+
*/
1710
+
rpm_put:
1711
+
pm_runtime_put_sync(dev);
1712
+
assert_power_resets:
1713
+
reset_control_bulk_assert(data->num_power_resets,
1714
+
host->power_resets);
1715
+
assert_rst_rsm_b:
1716
+
regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,
1717
+
RZG3S_SYS_PCIE_RST_RSM_B_MASK,
1718
+
FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));
1719
+
return ret;
1720
+
}
1721
+
1722
+
static const struct dev_pm_ops rzg3s_pcie_pm_ops = {
1723
+
NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3s_pcie_suspend_noirq,
1724
+
rzg3s_pcie_resume_noirq)
1725
+
};
1726
+
1727
+
static const char * const rzg3s_soc_power_resets[] = {
1728
+
"aresetn", "rst_cfg_b", "rst_load_b",
1729
+
};
1730
+
1731
+
static const char * const rzg3s_soc_cfg_resets[] = {
1732
+
"rst_b", "rst_ps_b", "rst_gp_b", "rst_rsm_b",
1733
+
};
1734
+
1735
+
static const struct rzg3s_pcie_soc_data rzg3s_soc_data = {
1736
+
.power_resets = rzg3s_soc_power_resets,
1737
+
.num_power_resets = ARRAY_SIZE(rzg3s_soc_power_resets),
1738
+
.cfg_resets = rzg3s_soc_cfg_resets,
1739
+
.num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets),
1740
+
.init_phy = rzg3s_soc_pcie_init_phy,
1741
+
};
1742
+
1743
+
static const struct of_device_id rzg3s_pcie_of_match[] = {
1744
+
{
1745
+
.compatible = "renesas,r9a08g045-pcie",
1746
+
.data = &rzg3s_soc_data,
1747
+
},
1748
+
{}
1749
+
};
1750
+
1751
+
static struct platform_driver rzg3s_pcie_driver = {
1752
+
.driver = {
1753
+
.name = "rzg3s-pcie-host",
1754
+
.of_match_table = rzg3s_pcie_of_match,
1755
+
.pm = pm_ptr(&rzg3s_pcie_pm_ops),
1756
+
.suppress_bind_attrs = true,
1757
+
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
1758
+
},
1759
+
.probe = rzg3s_pcie_probe,
1760
+
};
1761
+
builtin_platform_driver(rzg3s_pcie_driver);
+17
-23
drivers/pci/controller/vmd.c
+17
-23
drivers/pci/controller/vmd.c
···
578
578
vmd->dev->resource[VMD_MEMBAR2].child = NULL;
579
579
}
580
580
581
-
/*
582
-
* VMD domains start at 0x10000 to not clash with ACPI _SEG domains.
583
-
* Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of which the lower
584
-
* 16 bits are the PCI Segment Group (domain) number. Other bits are
585
-
* currently reserved.
586
-
*/
587
-
static int vmd_find_free_domain(void)
588
-
{
589
-
int domain = 0xffff;
590
-
struct pci_bus *bus = NULL;
591
-
592
-
while ((bus = pci_find_next_bus(bus)) != NULL)
593
-
domain = max_t(int, domain, pci_domain_nr(bus));
594
-
return domain + 1;
595
-
}
596
-
597
581
static int vmd_get_phys_offsets(struct vmd_dev *vmd, bool native_hint,
598
582
resource_size_t *offset1,
599
583
resource_size_t *offset2)
···
862
878
.parent = res,
863
879
};
864
880
865
-
sd->vmd_dev = vmd->dev;
866
-
sd->domain = vmd_find_free_domain();
867
-
if (sd->domain < 0)
868
-
return sd->domain;
869
-
870
-
sd->node = pcibus_to_node(vmd->dev->bus);
871
-
872
881
/*
873
882
* Currently MSI remapping must be enabled in guest passthrough mode
874
883
* due to some missing interrupt remapping plumbing. This is probably
···
887
910
pci_add_resource_offset(&resources, &vmd->resources[1], offset[0]);
888
911
pci_add_resource_offset(&resources, &vmd->resources[2], offset[1]);
889
912
913
+
sd->vmd_dev = vmd->dev;
914
+
915
+
/*
916
+
* Emulated domains start at 0x10000 to not clash with ACPI _SEG
917
+
* domains. Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of
918
+
* which the lower 16 bits are the PCI Segment Group (domain) number.
919
+
* Other bits are currently reserved.
920
+
*/
921
+
sd->domain = pci_bus_find_emul_domain_nr(0, 0x10000, INT_MAX);
922
+
if (sd->domain < 0)
923
+
return sd->domain;
924
+
925
+
sd->node = pcibus_to_node(vmd->dev->bus);
926
+
890
927
vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start,
891
928
&vmd_ops, sd, &resources);
892
929
if (!vmd->bus) {
930
+
pci_bus_release_emul_domain_nr(sd->domain);
893
931
pci_free_resource_list(&resources);
894
932
vmd_remove_irq_domain(vmd);
895
933
return -ENODEV;
···
997
1005
return -ENOMEM;
998
1006
999
1007
vmd->dev = dev;
1008
+
vmd->sysdata.domain = PCI_DOMAIN_NR_NOT_SET;
1000
1009
vmd->instance = ida_alloc(&vmd_instance_ida, GFP_KERNEL);
1001
1010
if (vmd->instance < 0)
1002
1011
return vmd->instance;
···
1063
1070
vmd_detach_resources(vmd);
1064
1071
vmd_remove_irq_domain(vmd);
1065
1072
ida_free(&vmd_instance_ida, vmd->instance);
1073
+
pci_bus_release_emul_domain_nr(vmd->sysdata.domain);
1066
1074
}
1067
1075
1068
1076
static void vmd_shutdown(struct pci_dev *dev)
+3
-2
drivers/pci/endpoint/functions/pci-epf-test.c
+3
-2
drivers/pci/endpoint/functions/pci-epf-test.c
···
729
729
if (bar < BAR_0)
730
730
goto err_doorbell_cleanup;
731
731
732
-
ret = request_irq(epf->db_msg[0].virq, pci_epf_test_doorbell_handler, 0,
733
-
"pci-ep-test-doorbell", epf_test);
732
+
ret = request_threaded_irq(epf->db_msg[0].virq, NULL,
733
+
pci_epf_test_doorbell_handler, IRQF_ONESHOT,
734
+
"pci-ep-test-doorbell", epf_test);
734
735
if (ret) {
735
736
dev_err(&epf->dev,
736
737
"Failed to request doorbell IRQ: %d\n",
+136
-17
drivers/pci/endpoint/functions/pci-epf-vntb.c
+136
-17
drivers/pci/endpoint/functions/pci-epf-vntb.c
···
36
36
* PCIe Root Port PCI EP
37
37
*/
38
38
39
+
#include <linux/atomic.h>
39
40
#include <linux/delay.h>
40
41
#include <linux/io.h>
41
42
#include <linux/module.h>
42
43
#include <linux/slab.h>
43
44
45
+
#include <linux/pci-ep-msi.h>
44
46
#include <linux/pci-epc.h>
45
47
#include <linux/pci-epf.h>
46
48
#include <linux/ntb.h>
···
128
126
u32 db_count;
129
127
u32 spad_count;
130
128
u64 mws_size[MAX_MW];
131
-
u64 db;
129
+
atomic64_t db;
132
130
u32 vbus_number;
133
131
u16 vntb_pid;
134
132
u16 vntb_vid;
135
133
136
134
bool linkup;
135
+
bool msi_doorbell;
137
136
u32 spad_size;
138
137
139
138
enum pci_barno epf_ntb_bar[VNTB_BAR_NUM];
···
261
258
262
259
ntb = container_of(work, struct epf_ntb, cmd_handler.work);
263
260
264
-
for (i = 1; i < ntb->db_count; i++) {
261
+
for (i = 1; i < ntb->db_count && !ntb->msi_doorbell; i++) {
265
262
if (ntb->epf_db[i]) {
266
-
ntb->db |= 1 << (i - 1);
263
+
atomic64_or(1 << (i - 1), &ntb->db);
267
264
ntb_db_event(&ntb->ntb, i);
268
265
ntb->epf_db[i] = 0;
269
266
}
···
322
319
323
320
reset_handler:
324
321
queue_delayed_work(kpcintb_workqueue, &ntb->cmd_handler,
325
-
msecs_to_jiffies(5));
322
+
ntb->msi_doorbell ? msecs_to_jiffies(500) : msecs_to_jiffies(5));
323
+
}
324
+
325
+
static irqreturn_t epf_ntb_doorbell_handler(int irq, void *data)
326
+
{
327
+
struct epf_ntb *ntb = data;
328
+
int i;
329
+
330
+
for (i = 1; i < ntb->db_count; i++)
331
+
if (irq == ntb->epf->db_msg[i].virq) {
332
+
atomic64_or(1 << (i - 1), &ntb->db);
333
+
ntb_db_event(&ntb->ntb, i);
334
+
}
335
+
336
+
return IRQ_HANDLED;
326
337
}
327
338
328
339
/**
···
517
500
return 0;
518
501
}
519
502
503
+
static int epf_ntb_db_bar_init_msi_doorbell(struct epf_ntb *ntb,
504
+
struct pci_epf_bar *db_bar,
505
+
const struct pci_epc_features *epc_features,
506
+
enum pci_barno barno)
507
+
{
508
+
struct pci_epf *epf = ntb->epf;
509
+
dma_addr_t low, high;
510
+
struct msi_msg *msg;
511
+
size_t sz;
512
+
int ret;
513
+
int i;
514
+
515
+
ret = pci_epf_alloc_doorbell(epf, ntb->db_count);
516
+
if (ret)
517
+
return ret;
518
+
519
+
for (i = 0; i < ntb->db_count; i++) {
520
+
ret = request_irq(epf->db_msg[i].virq, epf_ntb_doorbell_handler,
521
+
0, "pci_epf_vntb_db", ntb);
522
+
523
+
if (ret) {
524
+
dev_err(&epf->dev,
525
+
"Failed to request doorbell IRQ: %d\n",
526
+
epf->db_msg[i].virq);
527
+
goto err_free_irq;
528
+
}
529
+
}
530
+
531
+
msg = &epf->db_msg[0].msg;
532
+
533
+
high = 0;
534
+
low = (u64)msg->address_hi << 32 | msg->address_lo;
535
+
536
+
for (i = 0; i < ntb->db_count; i++) {
537
+
struct msi_msg *msg = &epf->db_msg[i].msg;
538
+
dma_addr_t addr = (u64)msg->address_hi << 32 | msg->address_lo;
539
+
540
+
low = min(low, addr);
541
+
high = max(high, addr);
542
+
}
543
+
544
+
sz = high - low + sizeof(u32);
545
+
546
+
ret = pci_epf_assign_bar_space(epf, sz, barno, epc_features, 0, low);
547
+
if (ret) {
548
+
dev_err(&epf->dev, "Failed to assign Doorbell BAR space\n");
549
+
goto err_free_irq;
550
+
}
551
+
552
+
ret = pci_epc_set_bar(ntb->epf->epc, ntb->epf->func_no,
553
+
ntb->epf->vfunc_no, db_bar);
554
+
if (ret) {
555
+
dev_err(&epf->dev, "Failed to set Doorbell BAR\n");
556
+
goto err_free_irq;
557
+
}
558
+
559
+
for (i = 0; i < ntb->db_count; i++) {
560
+
struct msi_msg *msg = &epf->db_msg[i].msg;
561
+
dma_addr_t addr;
562
+
size_t offset;
563
+
564
+
ret = pci_epf_align_inbound_addr(epf, db_bar->barno,
565
+
((u64)msg->address_hi << 32) | msg->address_lo,
566
+
&addr, &offset);
567
+
568
+
if (ret) {
569
+
ntb->msi_doorbell = false;
570
+
goto err_free_irq;
571
+
}
572
+
573
+
ntb->reg->db_data[i] = msg->data;
574
+
ntb->reg->db_offset[i] = offset;
575
+
}
576
+
577
+
ntb->reg->db_entry_size = 0;
578
+
579
+
ntb->msi_doorbell = true;
580
+
581
+
return 0;
582
+
583
+
err_free_irq:
584
+
for (i--; i >= 0; i--)
585
+
free_irq(epf->db_msg[i].virq, ntb);
586
+
587
+
pci_epf_free_doorbell(ntb->epf);
588
+
return ret;
589
+
}
590
+
520
591
/**
521
592
* epf_ntb_db_bar_init() - Configure Doorbell window BARs
522
593
* @ntb: NTB device that facilitates communication between HOST and VHOST
···
625
520
ntb->epf->func_no,
626
521
ntb->epf->vfunc_no);
627
522
barno = ntb->epf_ntb_bar[BAR_DB];
628
-
629
-
mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, epc_features, 0);
630
-
if (!mw_addr) {
631
-
dev_err(dev, "Failed to allocate OB address\n");
632
-
return -ENOMEM;
633
-
}
634
-
635
-
ntb->epf_db = mw_addr;
636
-
637
523
epf_bar = &ntb->epf->bar[barno];
638
524
639
-
ret = pci_epc_set_bar(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no, epf_bar);
525
+
ret = epf_ntb_db_bar_init_msi_doorbell(ntb, epf_bar, epc_features, barno);
640
526
if (ret) {
641
-
dev_err(dev, "Doorbell BAR set failed\n");
527
+
/* fall back to polling mode */
528
+
mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, epc_features, 0);
529
+
if (!mw_addr) {
530
+
dev_err(dev, "Failed to allocate OB address\n");
531
+
return -ENOMEM;
532
+
}
533
+
534
+
ntb->epf_db = mw_addr;
535
+
536
+
ret = pci_epc_set_bar(ntb->epf->epc, ntb->epf->func_no,
537
+
ntb->epf->vfunc_no, epf_bar);
538
+
if (ret) {
539
+
dev_err(dev, "Doorbell BAR set failed\n");
642
540
goto err_alloc_peer_mem;
541
+
}
643
542
}
644
543
return ret;
645
544
···
662
553
static void epf_ntb_db_bar_clear(struct epf_ntb *ntb)
663
554
{
664
555
enum pci_barno barno;
556
+
557
+
if (ntb->msi_doorbell) {
558
+
int i;
559
+
560
+
for (i = 0; i < ntb->db_count; i++)
561
+
free_irq(ntb->epf->db_msg[i].virq, ntb);
562
+
}
563
+
564
+
if (ntb->epf->db_msg)
565
+
pci_epf_free_doorbell(ntb->epf);
665
566
666
567
barno = ntb->epf_ntb_bar[BAR_DB];
667
568
pci_epf_free_space(ntb->epf, ntb->epf_db, barno, 0);
···
1387
1268
{
1388
1269
struct epf_ntb *ntb = ntb_ndev(ndev);
1389
1270
1390
-
return ntb->db;
1271
+
return atomic64_read(&ntb->db);
1391
1272
}
1392
1273
1393
1274
static int vntb_epf_mw_get_align(struct ntb_dev *ndev, int pidx, int idx,
···
1427
1308
{
1428
1309
struct epf_ntb *ntb = ntb_ndev(ndev);
1429
1310
1430
-
ntb->db &= ~db_bits;
1311
+
atomic64_and(~db_bits, &ntb->db);
1431
1312
return 0;
1432
1313
}
1433
1314
+127
-32
drivers/pci/endpoint/pci-epf-core.c
+127
-32
drivers/pci/endpoint/pci-epf-core.c
···
208
208
}
209
209
EXPORT_SYMBOL_GPL(pci_epf_remove_vepf);
210
210
211
+
static int pci_epf_get_required_bar_size(struct pci_epf *epf, size_t *bar_size,
212
+
size_t *aligned_mem_size,
213
+
enum pci_barno bar,
214
+
const struct pci_epc_features *epc_features,
215
+
enum pci_epc_interface_type type)
216
+
{
217
+
u64 bar_fixed_size = epc_features->bar[bar].fixed_size;
218
+
size_t align = epc_features->align;
219
+
size_t size = *bar_size;
220
+
221
+
if (size < 128)
222
+
size = 128;
223
+
224
+
/* According to PCIe base spec, min size for a resizable BAR is 1 MB. */
225
+
if (epc_features->bar[bar].type == BAR_RESIZABLE && size < SZ_1M)
226
+
size = SZ_1M;
227
+
228
+
if (epc_features->bar[bar].type == BAR_FIXED && bar_fixed_size) {
229
+
if (size > bar_fixed_size) {
230
+
dev_err(&epf->dev,
231
+
"requested BAR size is larger than fixed size\n");
232
+
return -ENOMEM;
233
+
}
234
+
size = bar_fixed_size;
235
+
} else {
236
+
/* BAR size must be power of two */
237
+
size = roundup_pow_of_two(size);
238
+
}
239
+
240
+
*bar_size = size;
241
+
242
+
/*
243
+
* The EPC's BAR start address must meet alignment requirements. In most
244
+
* cases, the alignment will match the BAR size. However, differences
245
+
* can occur—for example, when the fixed BAR size (e.g., 128 bytes) is
246
+
* smaller than the required alignment (e.g., 4 KB).
247
+
*/
248
+
*aligned_mem_size = align ? ALIGN(size, align) : size;
249
+
250
+
return 0;
251
+
}
252
+
211
253
/**
212
254
* pci_epf_free_space() - free the allocated PCI EPF register space
213
255
* @epf: the EPF device from whom to free the memory
···
278
236
}
279
237
280
238
dev = epc->dev.parent;
281
-
dma_free_coherent(dev, epf_bar[bar].aligned_size, addr,
239
+
dma_free_coherent(dev, epf_bar[bar].mem_size, addr,
282
240
epf_bar[bar].phys_addr);
283
241
284
242
epf_bar[bar].phys_addr = 0;
285
243
epf_bar[bar].addr = NULL;
286
244
epf_bar[bar].size = 0;
287
-
epf_bar[bar].aligned_size = 0;
245
+
epf_bar[bar].mem_size = 0;
288
246
epf_bar[bar].barno = 0;
289
247
epf_bar[bar].flags = 0;
290
248
}
···
306
264
const struct pci_epc_features *epc_features,
307
265
enum pci_epc_interface_type type)
308
266
{
309
-
u64 bar_fixed_size = epc_features->bar[bar].fixed_size;
310
-
size_t aligned_size, align = epc_features->align;
311
267
struct pci_epf_bar *epf_bar;
312
268
dma_addr_t phys_addr;
313
269
struct pci_epc *epc;
314
270
struct device *dev;
271
+
size_t mem_size;
315
272
void *space;
316
273
317
-
if (size < 128)
318
-
size = 128;
319
-
320
-
/* According to PCIe base spec, min size for a resizable BAR is 1 MB. */
321
-
if (epc_features->bar[bar].type == BAR_RESIZABLE && size < SZ_1M)
322
-
size = SZ_1M;
323
-
324
-
if (epc_features->bar[bar].type == BAR_FIXED && bar_fixed_size) {
325
-
if (size > bar_fixed_size) {
326
-
dev_err(&epf->dev,
327
-
"requested BAR size is larger than fixed size\n");
328
-
return NULL;
329
-
}
330
-
size = bar_fixed_size;
331
-
} else {
332
-
/* BAR size must be power of two */
333
-
size = roundup_pow_of_two(size);
334
-
}
335
-
336
-
/*
337
-
* Allocate enough memory to accommodate the iATU alignment
338
-
* requirement. In most cases, this will be the same as .size but
339
-
* it might be different if, for example, the fixed size of a BAR
340
-
* is smaller than align.
341
-
*/
342
-
aligned_size = align ? ALIGN(size, align) : size;
274
+
if (pci_epf_get_required_bar_size(epf, &size, &mem_size, bar,
275
+
epc_features, type))
276
+
return NULL;
343
277
344
278
if (type == PRIMARY_INTERFACE) {
345
279
epc = epf->epc;
···
326
308
}
327
309
328
310
dev = epc->dev.parent;
329
-
space = dma_alloc_coherent(dev, aligned_size, &phys_addr, GFP_KERNEL);
311
+
space = dma_alloc_coherent(dev, mem_size, &phys_addr, GFP_KERNEL);
330
312
if (!space) {
331
313
dev_err(dev, "failed to allocate mem space\n");
332
314
return NULL;
···
335
317
epf_bar[bar].phys_addr = phys_addr;
336
318
epf_bar[bar].addr = space;
337
319
epf_bar[bar].size = size;
338
-
epf_bar[bar].aligned_size = aligned_size;
320
+
epf_bar[bar].mem_size = mem_size;
339
321
epf_bar[bar].barno = bar;
340
322
if (upper_32_bits(size) || epc_features->bar[bar].only_64bit)
341
323
epf_bar[bar].flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
···
345
327
return space;
346
328
}
347
329
EXPORT_SYMBOL_GPL(pci_epf_alloc_space);
330
+
331
+
/**
332
+
* pci_epf_assign_bar_space() - Assign PCI EPF BAR space
333
+
* @epf: EPF device to assign the BAR memory
334
+
* @size: Size of the memory that has to be assigned
335
+
* @bar: BAR number for which the memory is assigned
336
+
* @epc_features: Features provided by the EPC specific to this EPF
337
+
* @type: Identifies if the assignment is for primary EPC or secondary EPC
338
+
* @bar_addr: Address to be assigned for the @bar
339
+
*
340
+
* Invoke to assign memory for the PCI EPF BAR.
341
+
* Flag PCI_BASE_ADDRESS_MEM_TYPE_64 will automatically get set if the BAR
342
+
* can only be a 64-bit BAR, or if the requested size is larger than 2 GB.
343
+
*/
344
+
int pci_epf_assign_bar_space(struct pci_epf *epf, size_t size,
345
+
enum pci_barno bar,
346
+
const struct pci_epc_features *epc_features,
347
+
enum pci_epc_interface_type type,
348
+
dma_addr_t bar_addr)
349
+
{
350
+
size_t bar_size, aligned_mem_size;
351
+
struct pci_epf_bar *epf_bar;
352
+
dma_addr_t limit;
353
+
int pos;
354
+
355
+
if (!size)
356
+
return -EINVAL;
357
+
358
+
limit = bar_addr + size - 1;
359
+
360
+
/*
361
+
* Bits: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
362
+
* bar_addr: U U U U U U 0 X X X X X X X X X
363
+
* limit: U U U U U U 1 X X X X X X X X X
364
+
*
365
+
* bar_addr^limit 0 0 0 0 0 0 1 X X X X X X X X X
366
+
*
367
+
* U: unchanged address bits in range [bar_addr, limit]
368
+
* X: bit 0 or 1
369
+
*
370
+
* (bar_addr^limit) & BIT_ULL(pos) will find the first set bit from MSB
371
+
* (pos). And value of (2 ^ pos) should be able to cover the BAR range.
372
+
*/
373
+
for (pos = 8 * sizeof(dma_addr_t) - 1; pos > 0; pos--)
374
+
if ((limit ^ bar_addr) & BIT_ULL(pos))
375
+
break;
376
+
377
+
if (pos == 8 * sizeof(dma_addr_t) - 1)
378
+
return -EINVAL;
379
+
380
+
bar_size = BIT_ULL(pos + 1);
381
+
if (pci_epf_get_required_bar_size(epf, &bar_size, &aligned_mem_size,
382
+
bar, epc_features, type))
383
+
return -ENOMEM;
384
+
385
+
if (type == PRIMARY_INTERFACE)
386
+
epf_bar = epf->bar;
387
+
else
388
+
epf_bar = epf->sec_epc_bar;
389
+
390
+
epf_bar[bar].phys_addr = ALIGN_DOWN(bar_addr, aligned_mem_size);
391
+
392
+
if (epf_bar[bar].phys_addr + bar_size < limit)
393
+
return -ENOMEM;
394
+
395
+
epf_bar[bar].addr = NULL;
396
+
epf_bar[bar].size = bar_size;
397
+
epf_bar[bar].mem_size = aligned_mem_size;
398
+
epf_bar[bar].barno = bar;
399
+
if (upper_32_bits(size) || epc_features->bar[bar].only_64bit)
400
+
epf_bar[bar].flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
401
+
else
402
+
epf_bar[bar].flags |= PCI_BASE_ADDRESS_MEM_TYPE_32;
403
+
404
+
return 0;
405
+
}
406
+
EXPORT_SYMBOL_GPL(pci_epf_assign_bar_space);
348
407
349
408
static void pci_epf_remove_cfs(struct pci_epf_driver *driver)
350
409
{
+1
drivers/pci/host-bridge.c
+1
drivers/pci/host-bridge.c
+6
-19
drivers/pci/iov.c
+6
-19
drivers/pci/iov.c
···
158
158
return dev->sriov->barsz[pci_resource_num_to_vf_bar(resno)];
159
159
}
160
160
161
-
void pci_iov_resource_set_size(struct pci_dev *dev, int resno,
162
-
resource_size_t size)
161
+
void pci_iov_resource_set_size(struct pci_dev *dev, int resno, int size)
163
162
{
164
163
if (!pci_resource_is_iov(resno)) {
165
164
pci_warn(dev, "%s is not an IOV resource\n",
···
166
167
return;
167
168
}
168
169
169
-
dev->sriov->barsz[pci_resource_num_to_vf_bar(resno)] = size;
170
+
resno = pci_resource_num_to_vf_bar(resno);
171
+
dev->sriov->barsz[resno] = pci_rebar_size_to_bytes(size);
170
172
}
171
173
172
174
bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev)
···
1339
1339
*/
1340
1340
int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size)
1341
1341
{
1342
-
u32 sizes;
1343
-
int ret;
1344
-
1345
1342
if (!pci_resource_is_iov(resno))
1346
1343
return -EINVAL;
1347
1344
1348
1345
if (pci_iov_is_memory_decoding_enabled(dev))
1349
1346
return -EBUSY;
1350
1347
1351
-
sizes = pci_rebar_get_possible_sizes(dev, resno);
1352
-
if (!sizes)
1353
-
return -ENOTSUPP;
1354
-
1355
-
if (!(sizes & BIT(size)))
1348
+
if (!pci_rebar_size_supported(dev, resno, size))
1356
1349
return -EINVAL;
1357
1350
1358
-
ret = pci_rebar_set_size(dev, resno, size);
1359
-
if (ret)
1360
-
return ret;
1361
-
1362
-
pci_iov_resource_set_size(dev, resno, pci_rebar_size_to_bytes(size));
1363
-
1364
-
return 0;
1351
+
return pci_rebar_set_size(dev, resno, size);
1365
1352
}
1366
1353
EXPORT_SYMBOL_GPL(pci_iov_vf_bar_set_size);
1367
1354
···
1367
1380
u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs)
1368
1381
{
1369
1382
u64 vf_len = pci_resource_len(dev, resno);
1370
-
u32 sizes;
1383
+
u64 sizes;
1371
1384
1372
1385
if (!num_vfs)
1373
1386
return 0;
+4
-2
drivers/pci/pci-driver.c
+4
-2
drivers/pci/pci-driver.c
···
629
629
struct pci_dev *pci_dev = to_pci_dev(dev);
630
630
struct pci_driver *drv = pci_dev->driver;
631
631
632
+
pci_dev->state_saved = false;
633
+
632
634
if (drv && drv->suspend) {
633
635
pci_power_t prev = pci_dev->current_state;
634
636
int error;
···
1038
1036
1039
1037
if (!pm) {
1040
1038
pci_pm_default_suspend(pci_dev);
1039
+
if (!pm_runtime_suspended(dev))
1040
+
pci_dev->state_saved = false;
1041
1041
return 0;
1042
1042
}
1043
1043
···
1132
1128
} else {
1133
1129
pci_pm_reenable_device(pci_dev);
1134
1130
}
1135
-
1136
-
pci_dev->state_saved = false;
1137
1131
1138
1132
return error;
1139
1133
}
+3
-16
drivers/pci/pci-sysfs.c
+3
-16
drivers/pci/pci-sysfs.c
···
1587
1587
pci_config_pm_runtime_get(pdev);
1588
1588
1589
1589
ret = sysfs_emit(buf, "%016llx\n",
1590
-
(u64)pci_rebar_get_possible_sizes(pdev, n));
1590
+
pci_rebar_get_possible_sizes(pdev, n));
1591
1591
1592
1592
pci_config_pm_runtime_put(pdev);
1593
1593
···
1599
1599
{
1600
1600
struct pci_dev *pdev = to_pci_dev(dev);
1601
1601
struct pci_bus *bus = pdev->bus;
1602
-
struct resource *b_win, *res;
1603
1602
unsigned long size;
1604
-
int ret, i;
1603
+
int ret;
1605
1604
u16 cmd;
1606
1605
1607
1606
if (kstrtoul(buf, 0, &size) < 0)
1608
-
return -EINVAL;
1609
-
1610
-
b_win = pbus_select_window(bus, pci_resource_n(pdev, n));
1611
-
if (!b_win)
1612
1607
return -EINVAL;
1613
1608
1614
1609
device_lock(dev);
···
1627
1632
1628
1633
pci_remove_resource_files(pdev);
1629
1634
1630
-
pci_dev_for_each_resource(pdev, res, i) {
1631
-
if (i >= PCI_BRIDGE_RESOURCES)
1632
-
break;
1633
-
1634
-
if (b_win == pbus_select_window(bus, res))
1635
-
pci_release_resource(pdev, i);
1636
-
}
1637
-
1638
-
ret = pci_resize_resource(pdev, n, size);
1635
+
ret = pci_resize_resource(pdev, n, size, 0);
1639
1636
1640
1637
pci_assign_unassigned_bus_resources(bus);
1641
1638
+23
-149
drivers/pci/pci.c
+23
-149
drivers/pci/pci.c
···
1823
1823
}
1824
1824
}
1825
1825
1826
-
static void pci_restore_rebar_state(struct pci_dev *pdev)
1827
-
{
1828
-
unsigned int pos, nbars, i;
1829
-
u32 ctrl;
1830
-
1831
-
pos = pdev->rebar_cap;
1832
-
if (!pos)
1833
-
return;
1834
-
1835
-
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1836
-
nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl);
1837
-
1838
-
for (i = 0; i < nbars; i++, pos += 8) {
1839
-
struct resource *res;
1840
-
int bar_idx, size;
1841
-
1842
-
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1843
-
bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1844
-
res = pci_resource_n(pdev, bar_idx);
1845
-
size = pci_rebar_bytes_to_size(resource_size(res));
1846
-
ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1847
-
ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
1848
-
pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1849
-
}
1850
-
}
1851
-
1852
1826
/**
1853
1827
* pci_restore_state - Restore the saved state of a PCI device
1854
1828
* @dev: PCI device that we're dealing with
1855
1829
*/
1856
1830
void pci_restore_state(struct pci_dev *dev)
1857
1831
{
1858
-
if (!dev->state_saved)
1859
-
return;
1860
-
1861
1832
pci_restore_pcie_state(dev);
1862
1833
pci_restore_pasid_state(dev);
1863
1834
pci_restore_pri_state(dev);
···
3656
3685
* quirks.
3657
3686
*/
3658
3687
pci_enable_acs(dev);
3659
-
}
3660
-
3661
-
void pci_rebar_init(struct pci_dev *pdev)
3662
-
{
3663
-
pdev->rebar_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3664
-
}
3665
-
3666
-
/**
3667
-
* pci_rebar_find_pos - find position of resize ctrl reg for BAR
3668
-
* @pdev: PCI device
3669
-
* @bar: BAR to find
3670
-
*
3671
-
* Helper to find the position of the ctrl register for a BAR.
3672
-
* Returns -ENOTSUPP if resizable BARs are not supported at all.
3673
-
* Returns -ENOENT if no ctrl register for the BAR could be found.
3674
-
*/
3675
-
static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3676
-
{
3677
-
unsigned int pos, nbars, i;
3678
-
u32 ctrl;
3679
-
3680
-
if (pci_resource_is_iov(bar)) {
3681
-
pos = pci_iov_vf_rebar_cap(pdev);
3682
-
bar = pci_resource_num_to_vf_bar(bar);
3683
-
} else {
3684
-
pos = pdev->rebar_cap;
3685
-
}
3686
-
3687
-
if (!pos)
3688
-
return -ENOTSUPP;
3689
-
3690
-
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3691
-
nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl);
3692
-
3693
-
for (i = 0; i < nbars; i++, pos += 8) {
3694
-
int bar_idx;
3695
-
3696
-
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3697
-
bar_idx = FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl);
3698
-
if (bar_idx == bar)
3699
-
return pos;
3700
-
}
3701
-
3702
-
return -ENOENT;
3703
-
}
3704
-
3705
-
/**
3706
-
* pci_rebar_get_possible_sizes - get possible sizes for BAR
3707
-
* @pdev: PCI device
3708
-
* @bar: BAR to query
3709
-
*
3710
-
* Get the possible sizes of a resizable BAR as bitmask defined in the spec
3711
-
* (bit 0=1MB, bit 31=128TB). Returns 0 if BAR isn't resizable.
3712
-
*/
3713
-
u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3714
-
{
3715
-
int pos;
3716
-
u32 cap;
3717
-
3718
-
pos = pci_rebar_find_pos(pdev, bar);
3719
-
if (pos < 0)
3720
-
return 0;
3721
-
3722
-
pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3723
-
cap = FIELD_GET(PCI_REBAR_CAP_SIZES, cap);
3724
-
3725
-
/* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3726
-
if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3727
-
bar == 0 && cap == 0x700)
3728
-
return 0x3f00;
3729
-
3730
-
return cap;
3731
-
}
3732
-
EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3733
-
3734
-
/**
3735
-
* pci_rebar_get_current_size - get the current size of a BAR
3736
-
* @pdev: PCI device
3737
-
* @bar: BAR to set size to
3738
-
*
3739
-
* Read the size of a BAR from the resizable BAR config.
3740
-
* Returns size if found or negative error code.
3741
-
*/
3742
-
int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3743
-
{
3744
-
int pos;
3745
-
u32 ctrl;
3746
-
3747
-
pos = pci_rebar_find_pos(pdev, bar);
3748
-
if (pos < 0)
3749
-
return pos;
3750
-
3751
-
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3752
-
return FIELD_GET(PCI_REBAR_CTRL_BAR_SIZE, ctrl);
3753
-
}
3754
-
3755
-
/**
3756
-
* pci_rebar_set_size - set a new size for a BAR
3757
-
* @pdev: PCI device
3758
-
* @bar: BAR to set size to
3759
-
* @size: new size as defined in the spec (0=1MB, 31=128TB)
3760
-
*
3761
-
* Set the new size of a BAR as defined in the spec.
3762
-
* Returns zero if resizing was successful, error code otherwise.
3763
-
*/
3764
-
int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3765
-
{
3766
-
int pos;
3767
-
u32 ctrl;
3768
-
3769
-
pos = pci_rebar_find_pos(pdev, bar);
3770
-
if (pos < 0)
3771
-
return pos;
3772
-
3773
-
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3774
-
ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3775
-
ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
3776
-
pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3777
-
return 0;
3778
3688
}
3779
3689
3780
3690
/**
···
6508
6656
#endif
6509
6657
}
6510
6658
6659
+
#ifdef CONFIG_PCI_DOMAINS
6660
+
static DEFINE_IDA(pci_domain_nr_dynamic_ida);
6661
+
6662
+
/**
6663
+
* pci_bus_find_emul_domain_nr() - allocate a PCI domain number per constraints
6664
+
* @hint: desired domain, 0 if any ID in the range of @min to @max is acceptable
6665
+
* @min: minimum allowable domain
6666
+
* @max: maximum allowable domain, no IDs higher than INT_MAX will be returned
6667
+
*/
6668
+
int pci_bus_find_emul_domain_nr(u32 hint, u32 min, u32 max)
6669
+
{
6670
+
return ida_alloc_range(&pci_domain_nr_dynamic_ida, max(hint, min), max,
6671
+
GFP_KERNEL);
6672
+
}
6673
+
EXPORT_SYMBOL_GPL(pci_bus_find_emul_domain_nr);
6674
+
6675
+
void pci_bus_release_emul_domain_nr(int domain_nr)
6676
+
{
6677
+
ida_free(&pci_domain_nr_dynamic_ida, domain_nr);
6678
+
}
6679
+
EXPORT_SYMBOL_GPL(pci_bus_release_emul_domain_nr);
6680
+
#endif
6681
+
6511
6682
#ifdef CONFIG_PCI_DOMAINS_GENERIC
6512
6683
static DEFINE_IDA(pci_domain_nr_static_ida);
6513
-
static DEFINE_IDA(pci_domain_nr_dynamic_ida);
6514
6684
6515
6685
static void of_pci_reserve_static_domain_nr(void)
6516
6686
{
+6
-8
drivers/pci/pci.h
+6
-8
drivers/pci/pci.h
···
421
421
struct device *pci_get_host_bridge_device(struct pci_dev *dev);
422
422
void pci_put_host_bridge_device(struct device *dev);
423
423
424
+
void pci_resize_resource_set_size(struct pci_dev *dev, int resno, int size);
425
+
int pci_do_resource_release_and_resize(struct pci_dev *dev, int resno, int size,
426
+
int exclude_bars);
424
427
unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
425
-
int pbus_reassign_bridge_resources(struct pci_bus *bus, struct resource *res);
426
428
int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
427
429
428
430
int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
···
810
808
resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
811
809
void pci_restore_iov_state(struct pci_dev *dev);
812
810
int pci_iov_bus_range(struct pci_bus *bus);
813
-
void pci_iov_resource_set_size(struct pci_dev *dev, int resno,
814
-
resource_size_t size);
811
+
void pci_iov_resource_set_size(struct pci_dev *dev, int resno, int size);
815
812
bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev);
816
813
static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev)
817
814
{
···
852
851
return 0;
853
852
}
854
853
static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resno,
855
-
resource_size_t size) { }
854
+
int size) { }
856
855
static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev)
857
856
{
858
857
return false;
···
1023
1022
#endif
1024
1023
1025
1024
void pci_rebar_init(struct pci_dev *pdev);
1025
+
void pci_restore_rebar_state(struct pci_dev *pdev);
1026
1026
int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
1027
1027
int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
1028
-
static inline u64 pci_rebar_size_to_bytes(int size)
1029
-
{
1030
-
return 1ULL << (size + 20);
1031
-
}
1032
1028
1033
1029
struct device_node;
1034
1030
-1
drivers/pci/pcie/portdrv.c
-1
drivers/pci/pcie/portdrv.c
+23
drivers/pci/pcie/ptm.c
+23
drivers/pci/pcie/ptm.c
···
81
81
dev->ptm_granularity = 0;
82
82
}
83
83
84
+
if (cap & PCI_PTM_CAP_RES)
85
+
dev->ptm_responder = 1;
86
+
if (cap & PCI_PTM_CAP_REQ)
87
+
dev->ptm_requester = 1;
88
+
84
89
if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
85
90
pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM)
86
91
pci_enable_ptm(dev, NULL);
···
147
142
ups = pci_upstream_ptm(dev);
148
143
if (!ups || !ups->ptm_enabled)
149
144
return -EINVAL;
145
+
}
146
+
147
+
switch (pci_pcie_type(dev)) {
148
+
case PCI_EXP_TYPE_ROOT_PORT:
149
+
if (!dev->ptm_root)
150
+
return -EINVAL;
151
+
break;
152
+
case PCI_EXP_TYPE_UPSTREAM:
153
+
if (!dev->ptm_responder)
154
+
return -EINVAL;
155
+
break;
156
+
case PCI_EXP_TYPE_ENDPOINT:
157
+
case PCI_EXP_TYPE_LEG_END:
158
+
if (!dev->ptm_requester)
159
+
return -EINVAL;
160
+
break;
161
+
default:
162
+
return -EINVAL;
150
163
}
151
164
152
165
pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, &ctrl);
+8
-5
drivers/pci/probe.c
+8
-5
drivers/pci/probe.c
···
650
650
651
651
pci_free_resource_list(&bridge->windows);
652
652
pci_free_resource_list(&bridge->dma_ranges);
653
+
654
+
/* Host bridges only have domain_nr set in the emulation case */
655
+
if (bridge->domain_nr != PCI_DOMAIN_NR_NOT_SET)
656
+
pci_bus_release_emul_domain_nr(bridge->domain_nr);
657
+
653
658
kfree(bridge);
654
659
}
655
660
···
1135
1130
device_del(&bridge->dev);
1136
1131
free:
1137
1132
#ifdef CONFIG_PCI_DOMAINS_GENERIC
1138
-
pci_bus_release_domain_nr(parent, bus->domain_nr);
1133
+
if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET)
1134
+
pci_bus_release_domain_nr(parent, bus->domain_nr);
1139
1135
#endif
1140
1136
if (bus_registered)
1141
1137
put_device(&bus->dev);
···
2753
2747
2754
2748
pci_reassigndev_resource_alignment(dev);
2755
2749
2756
-
dev->state_saved = false;
2757
-
2758
2750
pci_init_capabilities(dev);
2759
2751
2760
2752
/*
···
3174
3170
* bus number if there is room.
3175
3171
*/
3176
3172
if (bus->self && bus->self->is_hotplug_bridge) {
3177
-
used_buses = max_t(unsigned int, available_buses,
3178
-
pci_hotplug_bus_size - 1);
3173
+
used_buses = max(available_buses, pci_hotplug_bus_size - 1);
3179
3174
if (max - start < used_buses) {
3180
3175
max = start + used_buses;
3181
3176
+15
drivers/pci/pwrctrl/Kconfig
+15
drivers/pci/pwrctrl/Kconfig
···
22
22
PCI slots. The voltage regulators powering the rails of the PCI slots
23
23
are expected to be defined in the devicetree node of the PCI bridge.
24
24
25
+
config PCI_PWRCTRL_TC9563
26
+
tristate "PCI Power Control driver for TC9563 PCIe switch"
27
+
select PCI_PWRCTRL
28
+
default m if ARCH_QCOM
29
+
depends on I2C
30
+
help
31
+
Say Y here to enable the PCI Power Control driver of TC9563 PCIe
32
+
switch.
33
+
34
+
This driver enables power and configures the TC9563 PCIe switch
35
+
through i2c. TC9563 is a PCIe switch which has one upstream and three
36
+
downstream ports. To one of the downstream ports integrated ethernet
37
+
MAC is connected as endpoint device. Other two downstream ports are
38
+
supposed to connect to external device.
39
+
25
40
# deprecated
26
41
config HAVE_PWRCTL
27
42
bool
+2
drivers/pci/pwrctrl/Makefile
+2
drivers/pci/pwrctrl/Makefile
+648
drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c
+648
drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/array_size.h>
7
+
#include <linux/bitfield.h>
8
+
#include <linux/bits.h>
9
+
#include <linux/delay.h>
10
+
#include <linux/device.h>
11
+
#include <linux/gpio/consumer.h>
12
+
#include <linux/i2c.h>
13
+
#include <linux/mod_devicetable.h>
14
+
#include <linux/module.h>
15
+
#include <linux/of.h>
16
+
#include <linux/of_platform.h>
17
+
#include <linux/pci.h>
18
+
#include <linux/pci-pwrctrl.h>
19
+
#include <linux/platform_device.h>
20
+
#include <linux/regulator/consumer.h>
21
+
#include <linux/string.h>
22
+
#include <linux/types.h>
23
+
#include <linux/unaligned.h>
24
+
25
+
#include "../pci.h"
26
+
27
+
#define TC9563_GPIO_CONFIG 0x801208
28
+
#define TC9563_RESET_GPIO 0x801210
29
+
30
+
#define TC9563_PORT_L0S_DELAY 0x82496c
31
+
#define TC9563_PORT_L1_DELAY 0x824970
32
+
33
+
#define TC9563_EMBEDDED_ETH_DELAY 0x8200d8
34
+
#define TC9563_ETH_L1_DELAY_MASK GENMASK(27, 18)
35
+
#define TC9563_ETH_L1_DELAY_VALUE(x) FIELD_PREP(TC9563_ETH_L1_DELAY_MASK, x)
36
+
#define TC9563_ETH_L0S_DELAY_MASK GENMASK(17, 13)
37
+
#define TC9563_ETH_L0S_DELAY_VALUE(x) FIELD_PREP(TC9563_ETH_L0S_DELAY_MASK, x)
38
+
39
+
#define TC9563_NFTS_2_5_GT 0x824978
40
+
#define TC9563_NFTS_5_GT 0x82497c
41
+
42
+
#define TC9563_PORT_LANE_ACCESS_ENABLE 0x828000
43
+
44
+
#define TC9563_PHY_RATE_CHANGE_OVERRIDE 0x828040
45
+
#define TC9563_PHY_RATE_CHANGE 0x828050
46
+
47
+
#define TC9563_TX_MARGIN 0x828234
48
+
49
+
#define TC9563_DFE_ENABLE 0x828a04
50
+
#define TC9563_DFE_EQ0_MODE 0x828a08
51
+
#define TC9563_DFE_EQ1_MODE 0x828a0c
52
+
#define TC9563_DFE_EQ2_MODE 0x828a14
53
+
#define TC9563_DFE_PD_MASK 0x828254
54
+
55
+
#define TC9563_PORT_SELECT 0x82c02c
56
+
#define TC9563_PORT_ACCESS_ENABLE 0x82c030
57
+
58
+
#define TC9563_POWER_CONTROL 0x82b09c
59
+
#define TC9563_POWER_CONTROL_OVREN 0x82b2c8
60
+
61
+
#define TC9563_GPIO_MASK 0xfffffff3
62
+
#define TC9563_GPIO_DEASSERT_BITS 0xc /* Bits to clear for GPIO deassert */
63
+
64
+
#define TC9563_TX_MARGIN_MIN_UA 400000
65
+
66
+
/*
67
+
* From TC9563 PORSYS rev 0.2, figure 1.1 POR boot sequence
68
+
* wait for 10ms for the internal osc frequency to stabilize.
69
+
*/
70
+
#define TC9563_OSC_STAB_DELAY_US (10 * USEC_PER_MSEC)
71
+
72
+
#define TC9563_L0S_L1_DELAY_UNIT_NS 256 /* Each unit represents 256 nanoseconds */
73
+
74
+
struct tc9563_pwrctrl_reg_setting {
75
+
unsigned int offset;
76
+
unsigned int val;
77
+
};
78
+
79
+
enum tc9563_pwrctrl_ports {
80
+
TC9563_USP,
81
+
TC9563_DSP1,
82
+
TC9563_DSP2,
83
+
TC9563_DSP3,
84
+
TC9563_ETHERNET,
85
+
TC9563_MAX
86
+
};
87
+
88
+
struct tc9563_pwrctrl_cfg {
89
+
u32 l0s_delay;
90
+
u32 l1_delay;
91
+
u32 tx_amp;
92
+
u8 nfts[2]; /* GEN1 & GEN2 */
93
+
bool disable_dfe;
94
+
bool disable_port;
95
+
};
96
+
97
+
#define TC9563_PWRCTL_MAX_SUPPLY 6
98
+
99
+
static const char *const tc9563_supply_names[TC9563_PWRCTL_MAX_SUPPLY] = {
100
+
"vddc",
101
+
"vdd18",
102
+
"vdd09",
103
+
"vddio1",
104
+
"vddio2",
105
+
"vddio18",
106
+
};
107
+
108
+
struct tc9563_pwrctrl_ctx {
109
+
struct regulator_bulk_data supplies[TC9563_PWRCTL_MAX_SUPPLY];
110
+
struct tc9563_pwrctrl_cfg cfg[TC9563_MAX];
111
+
struct gpio_desc *reset_gpio;
112
+
struct i2c_adapter *adapter;
113
+
struct i2c_client *client;
114
+
struct pci_pwrctrl pwrctrl;
115
+
};
116
+
117
+
/*
118
+
* downstream port power off sequence, hardcoding the address
119
+
* as we don't know register names for these register offsets.
120
+
*/
121
+
static const struct tc9563_pwrctrl_reg_setting common_pwroff_seq[] = {
122
+
{0x82900c, 0x1},
123
+
{0x829010, 0x1},
124
+
{0x829018, 0x0},
125
+
{0x829020, 0x1},
126
+
{0x82902c, 0x1},
127
+
{0x829030, 0x1},
128
+
{0x82903c, 0x1},
129
+
{0x829058, 0x0},
130
+
{0x82905c, 0x1},
131
+
{0x829060, 0x1},
132
+
{0x8290cc, 0x1},
133
+
{0x8290d0, 0x1},
134
+
{0x8290d8, 0x1},
135
+
{0x8290e0, 0x1},
136
+
{0x8290e8, 0x1},
137
+
{0x8290ec, 0x1},
138
+
{0x8290f4, 0x1},
139
+
{0x82910c, 0x1},
140
+
{0x829110, 0x1},
141
+
{0x829114, 0x1},
142
+
};
143
+
144
+
static const struct tc9563_pwrctrl_reg_setting dsp1_pwroff_seq[] = {
145
+
{TC9563_PORT_ACCESS_ENABLE, 0x2},
146
+
{TC9563_PORT_LANE_ACCESS_ENABLE, 0x3},
147
+
{TC9563_POWER_CONTROL, 0x014f4804},
148
+
{TC9563_POWER_CONTROL_OVREN, 0x1},
149
+
{TC9563_PORT_ACCESS_ENABLE, 0x4},
150
+
};
151
+
152
+
static const struct tc9563_pwrctrl_reg_setting dsp2_pwroff_seq[] = {
153
+
{TC9563_PORT_ACCESS_ENABLE, 0x8},
154
+
{TC9563_PORT_LANE_ACCESS_ENABLE, 0x1},
155
+
{TC9563_POWER_CONTROL, 0x014f4804},
156
+
{TC9563_POWER_CONTROL_OVREN, 0x1},
157
+
{TC9563_PORT_ACCESS_ENABLE, 0x8},
158
+
};
159
+
160
+
/*
161
+
* Since all transfers are initiated by the probe, no locks are necessary,
162
+
* as there are no concurrent calls.
163
+
*/
164
+
static int tc9563_pwrctrl_i2c_write(struct i2c_client *client,
165
+
u32 reg_addr, u32 reg_val)
166
+
{
167
+
struct i2c_msg msg;
168
+
u8 msg_buf[7];
169
+
int ret;
170
+
171
+
msg.addr = client->addr;
172
+
msg.len = 7;
173
+
msg.flags = 0;
174
+
175
+
/* Big Endian for reg addr */
176
+
put_unaligned_be24(reg_addr, &msg_buf[0]);
177
+
178
+
/* Little Endian for reg val */
179
+
put_unaligned_le32(reg_val, &msg_buf[3]);
180
+
181
+
msg.buf = msg_buf;
182
+
ret = i2c_transfer(client->adapter, &msg, 1);
183
+
return ret == 1 ? 0 : ret;
184
+
}
185
+
186
+
static int tc9563_pwrctrl_i2c_read(struct i2c_client *client,
187
+
u32 reg_addr, u32 *reg_val)
188
+
{
189
+
struct i2c_msg msg[2];
190
+
u8 wr_data[3];
191
+
u32 rd_data;
192
+
int ret;
193
+
194
+
msg[0].addr = client->addr;
195
+
msg[0].len = 3;
196
+
msg[0].flags = 0;
197
+
198
+
/* Big Endian for reg addr */
199
+
put_unaligned_be24(reg_addr, &wr_data[0]);
200
+
201
+
msg[0].buf = wr_data;
202
+
203
+
msg[1].addr = client->addr;
204
+
msg[1].len = 4;
205
+
msg[1].flags = I2C_M_RD;
206
+
207
+
msg[1].buf = (u8 *)&rd_data;
208
+
209
+
ret = i2c_transfer(client->adapter, &msg[0], 2);
210
+
if (ret == 2) {
211
+
*reg_val = get_unaligned_le32(&rd_data);
212
+
return 0;
213
+
}
214
+
215
+
/* If only one message successfully completed, return -EIO */
216
+
return ret == 1 ? -EIO : ret;
217
+
}
218
+
219
+
static int tc9563_pwrctrl_i2c_bulk_write(struct i2c_client *client,
220
+
const struct tc9563_pwrctrl_reg_setting *seq, int len)
221
+
{
222
+
int ret, i;
223
+
224
+
for (i = 0; i < len; i++) {
225
+
ret = tc9563_pwrctrl_i2c_write(client, seq[i].offset, seq[i].val);
226
+
if (ret)
227
+
return ret;
228
+
}
229
+
230
+
return 0;
231
+
}
232
+
233
+
static int tc9563_pwrctrl_disable_port(struct tc9563_pwrctrl_ctx *ctx,
234
+
enum tc9563_pwrctrl_ports port)
235
+
{
236
+
struct tc9563_pwrctrl_cfg *cfg = &ctx->cfg[port];
237
+
const struct tc9563_pwrctrl_reg_setting *seq;
238
+
int ret, len;
239
+
240
+
if (!cfg->disable_port)
241
+
return 0;
242
+
243
+
if (port == TC9563_DSP1) {
244
+
seq = dsp1_pwroff_seq;
245
+
len = ARRAY_SIZE(dsp1_pwroff_seq);
246
+
} else {
247
+
seq = dsp2_pwroff_seq;
248
+
len = ARRAY_SIZE(dsp2_pwroff_seq);
249
+
}
250
+
251
+
ret = tc9563_pwrctrl_i2c_bulk_write(ctx->client, seq, len);
252
+
if (ret)
253
+
return ret;
254
+
255
+
return tc9563_pwrctrl_i2c_bulk_write(ctx->client,
256
+
common_pwroff_seq, ARRAY_SIZE(common_pwroff_seq));
257
+
}
258
+
259
+
static int tc9563_pwrctrl_set_l0s_l1_entry_delay(struct tc9563_pwrctrl_ctx *ctx,
260
+
enum tc9563_pwrctrl_ports port, bool is_l1, u32 ns)
261
+
{
262
+
u32 rd_val, units;
263
+
int ret;
264
+
265
+
if (ns < TC9563_L0S_L1_DELAY_UNIT_NS)
266
+
return 0;
267
+
268
+
/* convert to units of 256ns */
269
+
units = ns / TC9563_L0S_L1_DELAY_UNIT_NS;
270
+
271
+
if (port == TC9563_ETHERNET) {
272
+
ret = tc9563_pwrctrl_i2c_read(ctx->client, TC9563_EMBEDDED_ETH_DELAY, &rd_val);
273
+
if (ret)
274
+
return ret;
275
+
276
+
if (is_l1)
277
+
rd_val = u32_replace_bits(rd_val, units, TC9563_ETH_L1_DELAY_MASK);
278
+
else
279
+
rd_val = u32_replace_bits(rd_val, units, TC9563_ETH_L0S_DELAY_MASK);
280
+
281
+
return tc9563_pwrctrl_i2c_write(ctx->client, TC9563_EMBEDDED_ETH_DELAY, rd_val);
282
+
}
283
+
284
+
ret = tc9563_pwrctrl_i2c_write(ctx->client, TC9563_PORT_SELECT, BIT(port));
285
+
if (ret)
286
+
return ret;
287
+
288
+
return tc9563_pwrctrl_i2c_write(ctx->client,
289
+
is_l1 ? TC9563_PORT_L1_DELAY : TC9563_PORT_L0S_DELAY, units);
290
+
}
291
+
292
+
static int tc9563_pwrctrl_set_tx_amplitude(struct tc9563_pwrctrl_ctx *ctx,
293
+
enum tc9563_pwrctrl_ports port)
294
+
{
295
+
u32 amp = ctx->cfg[port].tx_amp;
296
+
int port_access;
297
+
298
+
if (amp < TC9563_TX_MARGIN_MIN_UA)
299
+
return 0;
300
+
301
+
/* txmargin = (Amp(uV) - 400000) / 3125 */
302
+
amp = (amp - TC9563_TX_MARGIN_MIN_UA) / 3125;
303
+
304
+
switch (port) {
305
+
case TC9563_USP:
306
+
port_access = 0x1;
307
+
break;
308
+
case TC9563_DSP1:
309
+
port_access = 0x2;
310
+
break;
311
+
case TC9563_DSP2:
312
+
port_access = 0x8;
313
+
break;
314
+
default:
315
+
return -EINVAL;
316
+
}
317
+
318
+
struct tc9563_pwrctrl_reg_setting tx_amp_seq[] = {
319
+
{TC9563_PORT_ACCESS_ENABLE, port_access},
320
+
{TC9563_PORT_LANE_ACCESS_ENABLE, 0x3},
321
+
{TC9563_TX_MARGIN, amp},
322
+
};
323
+
324
+
return tc9563_pwrctrl_i2c_bulk_write(ctx->client, tx_amp_seq, ARRAY_SIZE(tx_amp_seq));
325
+
}
326
+
327
+
static int tc9563_pwrctrl_disable_dfe(struct tc9563_pwrctrl_ctx *ctx,
328
+
enum tc9563_pwrctrl_ports port)
329
+
{
330
+
struct tc9563_pwrctrl_cfg *cfg = &ctx->cfg[port];
331
+
int port_access, lane_access = 0x3;
332
+
u32 phy_rate = 0x21;
333
+
334
+
if (!cfg->disable_dfe)
335
+
return 0;
336
+
337
+
switch (port) {
338
+
case TC9563_USP:
339
+
phy_rate = 0x1;
340
+
port_access = 0x1;
341
+
break;
342
+
case TC9563_DSP1:
343
+
port_access = 0x2;
344
+
break;
345
+
case TC9563_DSP2:
346
+
port_access = 0x8;
347
+
lane_access = 0x1;
348
+
break;
349
+
default:
350
+
return -EINVAL;
351
+
}
352
+
353
+
struct tc9563_pwrctrl_reg_setting disable_dfe_seq[] = {
354
+
{TC9563_PORT_ACCESS_ENABLE, port_access},
355
+
{TC9563_PORT_LANE_ACCESS_ENABLE, lane_access},
356
+
{TC9563_DFE_ENABLE, 0x0},
357
+
{TC9563_DFE_EQ0_MODE, 0x411},
358
+
{TC9563_DFE_EQ1_MODE, 0x11},
359
+
{TC9563_DFE_EQ2_MODE, 0x11},
360
+
{TC9563_DFE_PD_MASK, 0x7},
361
+
{TC9563_PHY_RATE_CHANGE_OVERRIDE, 0x10},
362
+
{TC9563_PHY_RATE_CHANGE, phy_rate},
363
+
{TC9563_PHY_RATE_CHANGE, 0x0},
364
+
{TC9563_PHY_RATE_CHANGE_OVERRIDE, 0x0},
365
+
};
366
+
367
+
return tc9563_pwrctrl_i2c_bulk_write(ctx->client,
368
+
disable_dfe_seq, ARRAY_SIZE(disable_dfe_seq));
369
+
}
370
+
371
+
static int tc9563_pwrctrl_set_nfts(struct tc9563_pwrctrl_ctx *ctx,
372
+
enum tc9563_pwrctrl_ports port)
373
+
{
374
+
u8 *nfts = ctx->cfg[port].nfts;
375
+
struct tc9563_pwrctrl_reg_setting nfts_seq[] = {
376
+
{TC9563_NFTS_2_5_GT, nfts[0]},
377
+
{TC9563_NFTS_5_GT, nfts[1]},
378
+
};
379
+
int ret;
380
+
381
+
if (!nfts[0])
382
+
return 0;
383
+
384
+
ret = tc9563_pwrctrl_i2c_write(ctx->client, TC9563_PORT_SELECT, BIT(port));
385
+
if (ret)
386
+
return ret;
387
+
388
+
return tc9563_pwrctrl_i2c_bulk_write(ctx->client, nfts_seq, ARRAY_SIZE(nfts_seq));
389
+
}
390
+
391
+
static int tc9563_pwrctrl_assert_deassert_reset(struct tc9563_pwrctrl_ctx *ctx, bool deassert)
392
+
{
393
+
int ret, val;
394
+
395
+
ret = tc9563_pwrctrl_i2c_write(ctx->client, TC9563_GPIO_CONFIG, TC9563_GPIO_MASK);
396
+
if (ret)
397
+
return ret;
398
+
399
+
val = deassert ? TC9563_GPIO_DEASSERT_BITS : 0;
400
+
401
+
return tc9563_pwrctrl_i2c_write(ctx->client, TC9563_RESET_GPIO, val);
402
+
}
403
+
404
+
static int tc9563_pwrctrl_parse_device_dt(struct tc9563_pwrctrl_ctx *ctx, struct device_node *node,
405
+
enum tc9563_pwrctrl_ports port)
406
+
{
407
+
struct tc9563_pwrctrl_cfg *cfg = &ctx->cfg[port];
408
+
int ret;
409
+
410
+
/* Disable port if the status of the port is disabled. */
411
+
if (!of_device_is_available(node)) {
412
+
cfg->disable_port = true;
413
+
return 0;
414
+
}
415
+
416
+
ret = of_property_read_u32(node, "aspm-l0s-entry-delay-ns", &cfg->l0s_delay);
417
+
if (ret && ret != -EINVAL)
418
+
return ret;
419
+
420
+
ret = of_property_read_u32(node, "aspm-l1-entry-delay-ns", &cfg->l1_delay);
421
+
if (ret && ret != -EINVAL)
422
+
return ret;
423
+
424
+
ret = of_property_read_u32(node, "toshiba,tx-amplitude-microvolt", &cfg->tx_amp);
425
+
if (ret && ret != -EINVAL)
426
+
return ret;
427
+
428
+
ret = of_property_read_u8_array(node, "n-fts", cfg->nfts, ARRAY_SIZE(cfg->nfts));
429
+
if (ret && ret != -EINVAL)
430
+
return ret;
431
+
432
+
cfg->disable_dfe = of_property_read_bool(node, "toshiba,no-dfe-support");
433
+
434
+
return 0;
435
+
}
436
+
437
+
static void tc9563_pwrctrl_power_off(struct tc9563_pwrctrl_ctx *ctx)
438
+
{
439
+
gpiod_set_value(ctx->reset_gpio, 1);
440
+
441
+
regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
442
+
}
443
+
444
+
static int tc9563_pwrctrl_bring_up(struct tc9563_pwrctrl_ctx *ctx)
445
+
{
446
+
struct tc9563_pwrctrl_cfg *cfg;
447
+
int ret, i;
448
+
449
+
ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
450
+
if (ret < 0)
451
+
return dev_err_probe(ctx->pwrctrl.dev, ret, "cannot enable regulators\n");
452
+
453
+
gpiod_set_value(ctx->reset_gpio, 0);
454
+
455
+
fsleep(TC9563_OSC_STAB_DELAY_US);
456
+
457
+
ret = tc9563_pwrctrl_assert_deassert_reset(ctx, false);
458
+
if (ret)
459
+
goto power_off;
460
+
461
+
for (i = 0; i < TC9563_MAX; i++) {
462
+
cfg = &ctx->cfg[i];
463
+
ret = tc9563_pwrctrl_disable_port(ctx, i);
464
+
if (ret) {
465
+
dev_err(ctx->pwrctrl.dev, "Disabling port failed\n");
466
+
goto power_off;
467
+
}
468
+
469
+
ret = tc9563_pwrctrl_set_l0s_l1_entry_delay(ctx, i, false, cfg->l0s_delay);
470
+
if (ret) {
471
+
dev_err(ctx->pwrctrl.dev, "Setting L0s entry delay failed\n");
472
+
goto power_off;
473
+
}
474
+
475
+
ret = tc9563_pwrctrl_set_l0s_l1_entry_delay(ctx, i, true, cfg->l1_delay);
476
+
if (ret) {
477
+
dev_err(ctx->pwrctrl.dev, "Setting L1 entry delay failed\n");
478
+
goto power_off;
479
+
}
480
+
481
+
ret = tc9563_pwrctrl_set_tx_amplitude(ctx, i);
482
+
if (ret) {
483
+
dev_err(ctx->pwrctrl.dev, "Setting Tx amplitude failed\n");
484
+
goto power_off;
485
+
}
486
+
487
+
ret = tc9563_pwrctrl_set_nfts(ctx, i);
488
+
if (ret) {
489
+
dev_err(ctx->pwrctrl.dev, "Setting N_FTS failed\n");
490
+
goto power_off;
491
+
}
492
+
493
+
ret = tc9563_pwrctrl_disable_dfe(ctx, i);
494
+
if (ret) {
495
+
dev_err(ctx->pwrctrl.dev, "Disabling DFE failed\n");
496
+
goto power_off;
497
+
}
498
+
}
499
+
500
+
ret = tc9563_pwrctrl_assert_deassert_reset(ctx, true);
501
+
if (!ret)
502
+
return 0;
503
+
504
+
power_off:
505
+
tc9563_pwrctrl_power_off(ctx);
506
+
return ret;
507
+
}
508
+
509
+
static int tc9563_pwrctrl_probe(struct platform_device *pdev)
510
+
{
511
+
struct pci_host_bridge *bridge = to_pci_host_bridge(pdev->dev.parent);
512
+
struct pci_bus *bus = bridge->bus;
513
+
struct device *dev = &pdev->dev;
514
+
enum tc9563_pwrctrl_ports port;
515
+
struct tc9563_pwrctrl_ctx *ctx;
516
+
struct device_node *i2c_node;
517
+
int ret, addr;
518
+
519
+
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
520
+
if (!ctx)
521
+
return -ENOMEM;
522
+
523
+
ret = of_property_read_u32_index(pdev->dev.of_node, "i2c-parent", 1, &addr);
524
+
if (ret)
525
+
return dev_err_probe(dev, ret, "Failed to read i2c-parent property\n");
526
+
527
+
i2c_node = of_parse_phandle(dev->of_node, "i2c-parent", 0);
528
+
ctx->adapter = of_find_i2c_adapter_by_node(i2c_node);
529
+
of_node_put(i2c_node);
530
+
if (!ctx->adapter)
531
+
return dev_err_probe(dev, -EPROBE_DEFER, "Failed to find I2C adapter\n");
532
+
533
+
ctx->client = i2c_new_dummy_device(ctx->adapter, addr);
534
+
if (IS_ERR(ctx->client)) {
535
+
dev_err(dev, "Failed to create I2C client\n");
536
+
i2c_put_adapter(ctx->adapter);
537
+
return PTR_ERR(ctx->client);
538
+
}
539
+
540
+
for (int i = 0; i < ARRAY_SIZE(tc9563_supply_names); i++)
541
+
ctx->supplies[i].supply = tc9563_supply_names[i];
542
+
543
+
ret = devm_regulator_bulk_get(dev, TC9563_PWRCTL_MAX_SUPPLY, ctx->supplies);
544
+
if (ret) {
545
+
dev_err_probe(dev, ret, "failed to get supply regulator\n");
546
+
goto remove_i2c;
547
+
}
548
+
549
+
ctx->reset_gpio = devm_gpiod_get(dev, "resx", GPIOD_OUT_HIGH);
550
+
if (IS_ERR(ctx->reset_gpio)) {
551
+
ret = dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "failed to get resx GPIO\n");
552
+
goto remove_i2c;
553
+
}
554
+
555
+
pci_pwrctrl_init(&ctx->pwrctrl, dev);
556
+
557
+
port = TC9563_USP;
558
+
ret = tc9563_pwrctrl_parse_device_dt(ctx, pdev->dev.of_node, port);
559
+
if (ret) {
560
+
dev_err(dev, "failed to parse device tree properties: %d\n", ret);
561
+
goto remove_i2c;
562
+
}
563
+
564
+
/*
565
+
* Downstream ports are always children of the upstream port.
566
+
* The first node represents DSP1, the second node represents DSP2, and so on.
567
+
*/
568
+
for_each_child_of_node_scoped(pdev->dev.of_node, child) {
569
+
port++;
570
+
ret = tc9563_pwrctrl_parse_device_dt(ctx, child, port);
571
+
if (ret)
572
+
break;
573
+
/* Embedded ethernet device are under DSP3 */
574
+
if (port == TC9563_DSP3) {
575
+
for_each_child_of_node_scoped(child, child1) {
576
+
port++;
577
+
ret = tc9563_pwrctrl_parse_device_dt(ctx, child1, port);
578
+
if (ret)
579
+
break;
580
+
}
581
+
}
582
+
}
583
+
if (ret) {
584
+
dev_err(dev, "failed to parse device tree properties: %d\n", ret);
585
+
goto remove_i2c;
586
+
}
587
+
588
+
if (bridge->ops->assert_perst) {
589
+
ret = bridge->ops->assert_perst(bus, true);
590
+
if (ret)
591
+
goto remove_i2c;
592
+
}
593
+
594
+
ret = tc9563_pwrctrl_bring_up(ctx);
595
+
if (ret)
596
+
goto remove_i2c;
597
+
598
+
if (bridge->ops->assert_perst) {
599
+
ret = bridge->ops->assert_perst(bus, false);
600
+
if (ret)
601
+
goto power_off;
602
+
}
603
+
604
+
ret = devm_pci_pwrctrl_device_set_ready(dev, &ctx->pwrctrl);
605
+
if (ret)
606
+
goto power_off;
607
+
608
+
platform_set_drvdata(pdev, ctx);
609
+
610
+
return 0;
611
+
612
+
power_off:
613
+
tc9563_pwrctrl_power_off(ctx);
614
+
remove_i2c:
615
+
i2c_unregister_device(ctx->client);
616
+
i2c_put_adapter(ctx->adapter);
617
+
return ret;
618
+
}
619
+
620
+
static void tc9563_pwrctrl_remove(struct platform_device *pdev)
621
+
{
622
+
struct tc9563_pwrctrl_ctx *ctx = platform_get_drvdata(pdev);
623
+
624
+
tc9563_pwrctrl_power_off(ctx);
625
+
i2c_unregister_device(ctx->client);
626
+
i2c_put_adapter(ctx->adapter);
627
+
}
628
+
629
+
static const struct of_device_id tc9563_pwrctrl_of_match[] = {
630
+
{ .compatible = "pci1179,0623"},
631
+
{ }
632
+
};
633
+
MODULE_DEVICE_TABLE(of, tc9563_pwrctrl_of_match);
634
+
635
+
static struct platform_driver tc9563_pwrctrl_driver = {
636
+
.driver = {
637
+
.name = "pwrctrl-tc9563",
638
+
.of_match_table = tc9563_pwrctrl_of_match,
639
+
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
640
+
},
641
+
.probe = tc9563_pwrctrl_probe,
642
+
.remove = tc9563_pwrctrl_remove,
643
+
};
644
+
module_platform_driver(tc9563_pwrctrl_driver);
645
+
646
+
MODULE_AUTHOR("Krishna chaitanya chundru <quic_krichai@quicinc.com>");
647
+
MODULE_DESCRIPTION("TC956x power control driver");
648
+
MODULE_LICENSE("GPL");
+328
drivers/pci/rebar.c
+328
drivers/pci/rebar.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* PCI Resizable BAR Extended Capability handling.
4
+
*/
5
+
6
+
#include <linux/bits.h>
7
+
#include <linux/bitfield.h>
8
+
#include <linux/bitops.h>
9
+
#include <linux/errno.h>
10
+
#include <linux/export.h>
11
+
#include <linux/ioport.h>
12
+
#include <linux/log2.h>
13
+
#include <linux/pci.h>
14
+
#include <linux/sizes.h>
15
+
#include <linux/types.h>
16
+
17
+
#include "pci.h"
18
+
19
+
#define PCI_REBAR_MIN_SIZE ((resource_size_t)SZ_1M)
20
+
21
+
/**
22
+
* pci_rebar_bytes_to_size - Convert size in bytes to PCI BAR Size
23
+
* @bytes: size in bytes
24
+
*
25
+
* Convert size in bytes to encoded BAR Size in Resizable BAR Capability
26
+
* (PCIe r6.2, sec. 7.8.6.3).
27
+
*
28
+
* Return: encoded BAR Size as defined in the PCIe spec (0=1MB, 31=128TB)
29
+
*/
30
+
int pci_rebar_bytes_to_size(u64 bytes)
31
+
{
32
+
int rebar_minsize = ilog2(PCI_REBAR_MIN_SIZE);
33
+
34
+
bytes = roundup_pow_of_two(bytes);
35
+
36
+
return max(ilog2(bytes), rebar_minsize) - rebar_minsize;
37
+
}
38
+
EXPORT_SYMBOL_GPL(pci_rebar_bytes_to_size);
39
+
40
+
/**
41
+
* pci_rebar_size_to_bytes - Convert encoded BAR Size to size in bytes
42
+
* @size: encoded BAR Size as defined in the PCIe spec (0=1MB, 31=128TB)
43
+
*
44
+
* Return: BAR size in bytes
45
+
*/
46
+
resource_size_t pci_rebar_size_to_bytes(int size)
47
+
{
48
+
return 1ULL << (size + ilog2(PCI_REBAR_MIN_SIZE));
49
+
}
50
+
EXPORT_SYMBOL_GPL(pci_rebar_size_to_bytes);
51
+
52
+
void pci_rebar_init(struct pci_dev *pdev)
53
+
{
54
+
pdev->rebar_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
55
+
}
56
+
57
+
/**
58
+
* pci_rebar_find_pos - find position of resize control reg for BAR
59
+
* @pdev: PCI device
60
+
* @bar: BAR to find
61
+
*
62
+
* Helper to find the position of the control register for a BAR.
63
+
*
64
+
* Return:
65
+
* * %-ENOTSUPP if resizable BARs are not supported at all,
66
+
* * %-ENOENT if no control register for the BAR could be found.
67
+
*/
68
+
static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
69
+
{
70
+
unsigned int pos, nbars, i;
71
+
u32 ctrl;
72
+
73
+
if (pci_resource_is_iov(bar)) {
74
+
pos = pci_iov_vf_rebar_cap(pdev);
75
+
bar = pci_resource_num_to_vf_bar(bar);
76
+
} else {
77
+
pos = pdev->rebar_cap;
78
+
}
79
+
80
+
if (!pos)
81
+
return -ENOTSUPP;
82
+
83
+
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
84
+
nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl);
85
+
86
+
for (i = 0; i < nbars; i++, pos += 8) {
87
+
int bar_idx;
88
+
89
+
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
90
+
bar_idx = FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl);
91
+
if (bar_idx == bar)
92
+
return pos;
93
+
}
94
+
95
+
return -ENOENT;
96
+
}
97
+
98
+
/**
99
+
* pci_rebar_get_possible_sizes - get possible sizes for Resizable BAR
100
+
* @pdev: PCI device
101
+
* @bar: BAR to query
102
+
*
103
+
* Get the possible sizes of a resizable BAR as bitmask.
104
+
*
105
+
* Return: A bitmask of possible sizes (bit 0=1MB, bit 31=128TB), or %0 if
106
+
* BAR isn't resizable.
107
+
*/
108
+
u64 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
109
+
{
110
+
int pos;
111
+
u32 cap;
112
+
113
+
pos = pci_rebar_find_pos(pdev, bar);
114
+
if (pos < 0)
115
+
return 0;
116
+
117
+
pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
118
+
cap = FIELD_GET(PCI_REBAR_CAP_SIZES, cap);
119
+
120
+
/* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
121
+
if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
122
+
bar == 0 && cap == 0x700)
123
+
return 0x3f00;
124
+
125
+
return cap;
126
+
}
127
+
EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
128
+
129
+
/**
130
+
* pci_rebar_size_supported - check if size is supported for BAR
131
+
* @pdev: PCI device
132
+
* @bar: BAR to check
133
+
* @size: encoded size as defined in the PCIe spec (0=1MB, 31=128TB)
134
+
*
135
+
* Return: %true if @bar is resizable and @size is supported, otherwise
136
+
* %false.
137
+
*/
138
+
bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size)
139
+
{
140
+
u64 sizes = pci_rebar_get_possible_sizes(pdev, bar);
141
+
142
+
if (size < 0 || size > ilog2(SZ_128T) - ilog2(PCI_REBAR_MIN_SIZE))
143
+
return false;
144
+
145
+
return BIT(size) & sizes;
146
+
}
147
+
EXPORT_SYMBOL_GPL(pci_rebar_size_supported);
148
+
149
+
/**
150
+
* pci_rebar_get_max_size - get the maximum supported size of a BAR
151
+
* @pdev: PCI device
152
+
* @bar: BAR to query
153
+
*
154
+
* Get the largest supported size of a resizable BAR as a size.
155
+
*
156
+
* Return: the encoded maximum BAR size as defined in the PCIe spec
157
+
* (0=1MB, 31=128TB), or %-NOENT on error.
158
+
*/
159
+
int pci_rebar_get_max_size(struct pci_dev *pdev, int bar)
160
+
{
161
+
u64 sizes;
162
+
163
+
sizes = pci_rebar_get_possible_sizes(pdev, bar);
164
+
if (!sizes)
165
+
return -ENOENT;
166
+
167
+
return __fls(sizes);
168
+
}
169
+
EXPORT_SYMBOL_GPL(pci_rebar_get_max_size);
170
+
171
+
/**
172
+
* pci_rebar_get_current_size - get the current size of a Resizable BAR
173
+
* @pdev: PCI device
174
+
* @bar: BAR to get the size from
175
+
*
176
+
* Read the current size of a BAR from the Resizable BAR config.
177
+
*
178
+
* Return: BAR Size if @bar is resizable (0=1MB, 31=128TB), or negative on
179
+
* error.
180
+
*/
181
+
int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
182
+
{
183
+
int pos;
184
+
u32 ctrl;
185
+
186
+
pos = pci_rebar_find_pos(pdev, bar);
187
+
if (pos < 0)
188
+
return pos;
189
+
190
+
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
191
+
return FIELD_GET(PCI_REBAR_CTRL_BAR_SIZE, ctrl);
192
+
}
193
+
194
+
/**
195
+
* pci_rebar_set_size - set a new size for a Resizable BAR
196
+
* @pdev: PCI device
197
+
* @bar: BAR to set size to
198
+
* @size: new size as defined in the PCIe spec (0=1MB, 31=128TB)
199
+
*
200
+
* Set the new size of a BAR as defined in the spec.
201
+
*
202
+
* Return: %0 if resizing was successful, or negative on error.
203
+
*/
204
+
int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
205
+
{
206
+
int pos;
207
+
u32 ctrl;
208
+
209
+
pos = pci_rebar_find_pos(pdev, bar);
210
+
if (pos < 0)
211
+
return pos;
212
+
213
+
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
214
+
ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
215
+
ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
216
+
pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
217
+
218
+
if (pci_resource_is_iov(bar))
219
+
pci_iov_resource_set_size(pdev, bar, size);
220
+
221
+
return 0;
222
+
}
223
+
224
+
void pci_restore_rebar_state(struct pci_dev *pdev)
225
+
{
226
+
unsigned int pos, nbars, i;
227
+
u32 ctrl;
228
+
229
+
pos = pdev->rebar_cap;
230
+
if (!pos)
231
+
return;
232
+
233
+
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
234
+
nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl);
235
+
236
+
for (i = 0; i < nbars; i++, pos += 8) {
237
+
struct resource *res;
238
+
int bar_idx, size;
239
+
240
+
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
241
+
bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
242
+
res = pci_resource_n(pdev, bar_idx);
243
+
size = pci_rebar_bytes_to_size(resource_size(res));
244
+
ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
245
+
ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
246
+
pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
247
+
}
248
+
}
249
+
250
+
static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev,
251
+
int resno)
252
+
{
253
+
u16 cmd;
254
+
255
+
if (pci_resource_is_iov(resno))
256
+
return pci_iov_is_memory_decoding_enabled(dev);
257
+
258
+
pci_read_config_word(dev, PCI_COMMAND, &cmd);
259
+
260
+
return cmd & PCI_COMMAND_MEMORY;
261
+
}
262
+
263
+
void pci_resize_resource_set_size(struct pci_dev *dev, int resno, int size)
264
+
{
265
+
resource_size_t res_size = pci_rebar_size_to_bytes(size);
266
+
struct resource *res = pci_resource_n(dev, resno);
267
+
268
+
if (pci_resource_is_iov(resno))
269
+
res_size *= pci_sriov_get_totalvfs(dev);
270
+
271
+
resource_set_size(res, res_size);
272
+
}
273
+
274
+
/**
275
+
* pci_resize_resource - reconfigure a Resizable BAR and resources
276
+
* @dev: the PCI device
277
+
* @resno: index of the BAR to be resized
278
+
* @size: new size as defined in the spec (0=1MB, 31=128TB)
279
+
* @exclude_bars: a mask of BARs that should not be released
280
+
*
281
+
* Reconfigure @resno to @size and re-run resource assignment algorithm
282
+
* with the new size.
283
+
*
284
+
* Prior to resize, release @dev resources that share a bridge window with
285
+
* @resno. This unpins the bridge window resource to allow changing it.
286
+
*
287
+
* The caller may prevent releasing a particular BAR by providing
288
+
* @exclude_bars mask, but this may result in the resize operation failing
289
+
* due to insufficient space.
290
+
*
291
+
* Return: 0 on success, or negative on error. In case of an error, the
292
+
* resources are restored to their original places.
293
+
*/
294
+
int pci_resize_resource(struct pci_dev *dev, int resno, int size,
295
+
int exclude_bars)
296
+
{
297
+
struct pci_host_bridge *host;
298
+
int old, ret;
299
+
300
+
/* Check if we must preserve the firmware's resource assignment */
301
+
host = pci_find_host_bridge(dev->bus);
302
+
if (host->preserve_config)
303
+
return -ENOTSUPP;
304
+
305
+
if (pci_resize_is_memory_decoding_enabled(dev, resno))
306
+
return -EBUSY;
307
+
308
+
if (!pci_rebar_size_supported(dev, resno, size))
309
+
return -EINVAL;
310
+
311
+
old = pci_rebar_get_current_size(dev, resno);
312
+
if (old < 0)
313
+
return old;
314
+
315
+
ret = pci_rebar_set_size(dev, resno, size);
316
+
if (ret)
317
+
return ret;
318
+
319
+
ret = pci_do_resource_release_and_resize(dev, resno, size, exclude_bars);
320
+
if (ret)
321
+
goto error_resize;
322
+
return 0;
323
+
324
+
error_resize:
325
+
pci_rebar_set_size(dev, resno, old);
326
+
return ret;
327
+
}
328
+
EXPORT_SYMBOL(pci_resize_resource);
+92
-34
drivers/pci/setup-bus.c
+92
-34
drivers/pci/setup-bus.c
···
15
15
*/
16
16
17
17
#include <linux/bitops.h>
18
+
#include <linux/bug.h>
18
19
#include <linux/init.h>
19
20
#include <linux/kernel.h>
20
21
#include <linux/module.h>
···
135
134
static void restore_dev_resource(struct pci_dev_resource *dev_res)
136
135
{
137
136
struct resource *res = dev_res->res;
137
+
138
+
if (WARN_ON_ONCE(res->parent))
139
+
return;
138
140
139
141
res->start = dev_res->start;
140
142
res->end = dev_res->end;
···
2424
2420
* release it when possible. If the bridge window contains assigned
2425
2421
* resources, it cannot be released.
2426
2422
*/
2427
-
int pbus_reassign_bridge_resources(struct pci_bus *bus, struct resource *res)
2423
+
static int pbus_reassign_bridge_resources(struct pci_bus *bus, struct resource *res,
2424
+
struct list_head *saved)
2428
2425
{
2429
2426
unsigned long type = res->flags;
2430
2427
struct pci_dev_resource *dev_res;
2431
-
struct pci_dev *bridge;
2432
-
LIST_HEAD(saved);
2428
+
struct pci_dev *bridge = NULL;
2433
2429
LIST_HEAD(added);
2434
2430
LIST_HEAD(failed);
2435
2431
unsigned int i;
2436
-
int ret;
2437
-
2438
-
down_read(&pci_bus_sem);
2432
+
int ret = 0;
2439
2433
2440
2434
while (!pci_is_root_bus(bus)) {
2441
2435
bridge = bus->self;
···
2445
2443
2446
2444
/* Ignore BARs which are still in use */
2447
2445
if (!res->child) {
2448
-
ret = add_to_list(&saved, bridge, res, 0, 0);
2446
+
ret = add_to_list(saved, bridge, res, 0, 0);
2449
2447
if (ret)
2450
-
goto cleanup;
2448
+
return ret;
2451
2449
2452
2450
pci_release_resource(bridge, i);
2453
2451
} else {
···
2461
2459
bus = bus->parent;
2462
2460
}
2463
2461
2464
-
if (list_empty(&saved)) {
2465
-
up_read(&pci_bus_sem);
2462
+
if (!bridge)
2466
2463
return -ENOENT;
2467
-
}
2468
2464
2469
2465
__pci_bus_size_bridges(bridge->subordinate, &added);
2470
2466
__pci_bridge_assign_resources(bridge, &added, &failed);
···
2470
2470
free_list(&added);
2471
2471
2472
2472
if (!list_empty(&failed)) {
2473
-
if (pci_required_resource_failed(&failed, type)) {
2473
+
if (pci_required_resource_failed(&failed, type))
2474
2474
ret = -ENOSPC;
2475
-
goto cleanup;
2476
-
}
2477
-
/* Only resources with unrelated types failed (again) */
2478
2475
free_list(&failed);
2476
+
if (ret)
2477
+
return ret;
2478
+
2479
+
/* Only resources with unrelated types failed (again) */
2479
2480
}
2480
2481
2481
-
list_for_each_entry(dev_res, &saved, list) {
2482
+
list_for_each_entry(dev_res, saved, list) {
2483
+
struct pci_dev *dev = dev_res->dev;
2484
+
2482
2485
/* Skip the bridge we just assigned resources for */
2483
-
if (bridge == dev_res->dev)
2486
+
if (bridge == dev)
2484
2487
continue;
2485
2488
2486
-
bridge = dev_res->dev;
2487
-
pci_setup_bridge(bridge->subordinate);
2489
+
if (!dev->subordinate)
2490
+
continue;
2491
+
2492
+
pci_setup_bridge(dev->subordinate);
2488
2493
}
2489
2494
2490
-
free_list(&saved);
2491
-
up_read(&pci_bus_sem);
2492
2495
return 0;
2496
+
}
2493
2497
2494
-
cleanup:
2495
-
/* Restore size and flags */
2496
-
list_for_each_entry(dev_res, &failed, list)
2497
-
restore_dev_resource(dev_res);
2498
-
free_list(&failed);
2498
+
int pci_do_resource_release_and_resize(struct pci_dev *pdev, int resno, int size,
2499
+
int exclude_bars)
2500
+
{
2501
+
struct resource *res = pci_resource_n(pdev, resno);
2502
+
struct pci_dev_resource *dev_res;
2503
+
struct pci_bus *bus = pdev->bus;
2504
+
struct resource *b_win, *r;
2505
+
LIST_HEAD(saved);
2506
+
unsigned int i;
2507
+
int ret = 0;
2499
2508
2509
+
b_win = pbus_select_window(bus, res);
2510
+
if (!b_win)
2511
+
return -EINVAL;
2512
+
2513
+
pci_dev_for_each_resource(pdev, r, i) {
2514
+
if (i >= PCI_BRIDGE_RESOURCES)
2515
+
break;
2516
+
2517
+
if (exclude_bars & BIT(i))
2518
+
continue;
2519
+
2520
+
if (b_win != pbus_select_window(bus, r))
2521
+
continue;
2522
+
2523
+
ret = add_to_list(&saved, pdev, r, 0, 0);
2524
+
if (ret)
2525
+
goto restore;
2526
+
pci_release_resource(pdev, i);
2527
+
}
2528
+
2529
+
pci_resize_resource_set_size(pdev, resno, size);
2530
+
2531
+
if (!bus->self)
2532
+
goto out;
2533
+
2534
+
down_read(&pci_bus_sem);
2535
+
ret = pbus_reassign_bridge_resources(bus, res, &saved);
2536
+
if (ret)
2537
+
goto restore;
2538
+
2539
+
out:
2540
+
up_read(&pci_bus_sem);
2541
+
free_list(&saved);
2542
+
return ret;
2543
+
2544
+
restore:
2500
2545
/* Revert to the old configuration */
2501
2546
list_for_each_entry(dev_res, &saved, list) {
2502
2547
struct resource *res = dev_res->res;
2548
+
struct pci_dev *dev = dev_res->dev;
2503
2549
2504
-
bridge = dev_res->dev;
2505
-
i = pci_resource_num(bridge, res);
2550
+
i = pci_resource_num(dev, res);
2551
+
2552
+
if (res->parent) {
2553
+
release_child_resources(res);
2554
+
pci_release_resource(dev, i);
2555
+
}
2506
2556
2507
2557
restore_dev_resource(dev_res);
2508
2558
2509
-
pci_claim_resource(bridge, i);
2510
-
pci_setup_bridge(bridge->subordinate);
2511
-
}
2512
-
free_list(&saved);
2513
-
up_read(&pci_bus_sem);
2559
+
ret = pci_claim_resource(dev, i);
2560
+
if (ret)
2561
+
continue;
2514
2562
2515
-
return ret;
2563
+
if (i < PCI_BRIDGE_RESOURCES) {
2564
+
const char *res_name = pci_resource_name(dev, i);
2565
+
2566
+
pci_update_resource(dev, i);
2567
+
pci_info(dev, "%s %pR: old value restored\n",
2568
+
res_name, res);
2569
+
}
2570
+
if (dev->subordinate)
2571
+
pci_setup_bridge(dev->subordinate);
2572
+
}
2573
+
goto out;
2516
2574
}
2517
2575
2518
2576
void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
-78
drivers/pci/setup-res.c
-78
drivers/pci/setup-res.c
···
431
431
}
432
432
EXPORT_SYMBOL(pci_release_resource);
433
433
434
-
static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev,
435
-
int resno)
436
-
{
437
-
u16 cmd;
438
-
439
-
if (pci_resource_is_iov(resno))
440
-
return pci_iov_is_memory_decoding_enabled(dev);
441
-
442
-
pci_read_config_word(dev, PCI_COMMAND, &cmd);
443
-
444
-
return cmd & PCI_COMMAND_MEMORY;
445
-
}
446
-
447
-
static void pci_resize_resource_set_size(struct pci_dev *dev, int resno,
448
-
int size)
449
-
{
450
-
resource_size_t res_size = pci_rebar_size_to_bytes(size);
451
-
struct resource *res = pci_resource_n(dev, resno);
452
-
453
-
if (!pci_resource_is_iov(resno)) {
454
-
resource_set_size(res, res_size);
455
-
} else {
456
-
resource_set_size(res, res_size * pci_sriov_get_totalvfs(dev));
457
-
pci_iov_resource_set_size(dev, resno, res_size);
458
-
}
459
-
}
460
-
461
-
int pci_resize_resource(struct pci_dev *dev, int resno, int size)
462
-
{
463
-
struct resource *res = pci_resource_n(dev, resno);
464
-
struct pci_host_bridge *host;
465
-
int old, ret;
466
-
u32 sizes;
467
-
468
-
/* Check if we must preserve the firmware's resource assignment */
469
-
host = pci_find_host_bridge(dev->bus);
470
-
if (host->preserve_config)
471
-
return -ENOTSUPP;
472
-
473
-
/* Make sure the resource isn't assigned before resizing it. */
474
-
if (!(res->flags & IORESOURCE_UNSET))
475
-
return -EBUSY;
476
-
477
-
if (pci_resize_is_memory_decoding_enabled(dev, resno))
478
-
return -EBUSY;
479
-
480
-
sizes = pci_rebar_get_possible_sizes(dev, resno);
481
-
if (!sizes)
482
-
return -ENOTSUPP;
483
-
484
-
if (!(sizes & BIT(size)))
485
-
return -EINVAL;
486
-
487
-
old = pci_rebar_get_current_size(dev, resno);
488
-
if (old < 0)
489
-
return old;
490
-
491
-
ret = pci_rebar_set_size(dev, resno, size);
492
-
if (ret)
493
-
return ret;
494
-
495
-
pci_resize_resource_set_size(dev, resno, size);
496
-
497
-
/* Check if the new config works by trying to assign everything. */
498
-
if (dev->bus->self) {
499
-
ret = pbus_reassign_bridge_resources(dev->bus, res);
500
-
if (ret)
501
-
goto error_resize;
502
-
}
503
-
return 0;
504
-
505
-
error_resize:
506
-
pci_rebar_set_size(dev, resno, old);
507
-
pci_resize_resource_set_size(dev, resno, old);
508
-
return ret;
509
-
}
510
-
EXPORT_SYMBOL(pci_resize_resource);
511
-
512
434
int pci_enable_resources(struct pci_dev *dev, int mask)
513
435
{
514
436
u16 cmd, old_cmd;
-1
drivers/scsi/bfa/bfad.c
-1
drivers/scsi/bfa/bfad.c
-1
drivers/scsi/csiostor/csio_init.c
-1
drivers/scsi/csiostor/csio_init.c
-1
drivers/scsi/ipr.c
-1
drivers/scsi/ipr.c
-6
drivers/scsi/lpfc/lpfc_init.c
-6
drivers/scsi/lpfc/lpfc_init.c
···
14434
14434
14435
14435
pci_restore_state(pdev);
14436
14436
14437
-
/*
14438
-
* As the new kernel behavior of pci_restore_state() API call clears
14439
-
* device saved_state flag, need to save the restored state again.
14440
-
*/
14441
-
pci_save_state(pdev);
14442
-
14443
14437
if (pdev->is_busmaster)
14444
14438
pci_set_master(pdev);
14445
14439
-5
drivers/scsi/qla2xxx/qla_os.c
-5
drivers/scsi/qla2xxx/qla_os.c
···
7886
7886
7887
7887
pci_restore_state(pdev);
7888
7888
7889
-
/* pci_restore_state() clears the saved_state flag of the device
7890
-
* save restored state which resets saved_state flag
7891
-
*/
7892
-
pci_save_state(pdev);
7893
-
7894
7889
if (ha->mem_only)
7895
7890
rc = pci_enable_device_mem(pdev);
7896
7891
else
-5
drivers/scsi/qla4xxx/ql4_os.c
-5
drivers/scsi/qla4xxx/ql4_os.c
···
9796
9796
*/
9797
9797
pci_restore_state(pdev);
9798
9798
9799
-
/* pci_restore_state() clears the saved_state flag of the device
9800
-
* save restored state which resets saved_state flag
9801
-
*/
9802
-
pci_save_state(pdev);
9803
-
9804
9799
/* Initialize device or resume if in suspended state */
9805
9800
rc = pci_enable_device(pdev);
9806
9801
if (rc) {
-1
drivers/tty/serial/8250/8250_pci.c
-1
drivers/tty/serial/8250/8250_pci.c
-1
drivers/tty/serial/jsm/jsm_driver.c
-1
drivers/tty/serial/jsm/jsm_driver.c
+9
-3
include/linux/pci-epf.h
+9
-3
include/linux/pci-epf.h
···
115
115
* @phys_addr: physical address that should be mapped to the BAR
116
116
* @addr: virtual address corresponding to the @phys_addr
117
117
* @size: the size of the address space present in BAR
118
-
* @aligned_size: the size actually allocated to accommodate the iATU alignment
119
-
* requirement
118
+
* @mem_size: the size actually allocated to accommodate the iATU alignment
119
+
* requirement
120
120
* @barno: BAR number
121
121
* @flags: flags that are set for the BAR
122
122
*/
···
124
124
dma_addr_t phys_addr;
125
125
void *addr;
126
126
size_t size;
127
-
size_t aligned_size;
127
+
size_t mem_size;
128
128
enum pci_barno barno;
129
129
int flags;
130
130
};
···
241
241
enum pci_epc_interface_type type);
242
242
void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar,
243
243
enum pci_epc_interface_type type);
244
+
245
+
int pci_epf_assign_bar_space(struct pci_epf *epf, size_t size,
246
+
enum pci_barno bar,
247
+
const struct pci_epc_features *epc_features,
248
+
enum pci_epc_interface_type type,
249
+
dma_addr_t bar_addr);
244
250
245
251
int pci_epf_align_inbound_addr(struct pci_epf *epf, enum pci_barno bar,
246
252
u64 addr, dma_addr_t *base, size_t *off);
+19
-8
include/linux/pci.h
+19
-8
include/linux/pci.h
···
502
502
#ifdef CONFIG_PCIE_PTM
503
503
u16 ptm_cap; /* PTM Capability */
504
504
unsigned int ptm_root:1;
505
+
unsigned int ptm_responder:1;
506
+
unsigned int ptm_requester:1;
505
507
unsigned int ptm_enabled:1;
506
508
u8 ptm_granularity;
507
509
#endif
···
650
648
struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
651
649
size_t priv);
652
650
void pci_free_host_bridge(struct pci_host_bridge *bridge);
651
+
struct device *pci_get_host_bridge_device(struct pci_dev *dev);
653
652
struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
654
653
655
654
void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
···
834
831
void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
835
832
int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
836
833
int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
834
+
int (*assert_perst)(struct pci_bus *bus, bool assert);
837
835
};
838
836
839
837
/*
···
1425
1421
void pci_update_resource(struct pci_dev *dev, int resno);
1426
1422
int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1427
1423
int pci_release_resource(struct pci_dev *dev, int resno);
1428
-
static inline int pci_rebar_bytes_to_size(u64 bytes)
1429
-
{
1430
-
bytes = roundup_pow_of_two(bytes);
1431
1424
1432
-
/* Return BAR size as defined in the resizable BAR specification */
1433
-
return max(ilog2(bytes), 20) - 20;
1434
-
}
1425
+
/* Resizable BAR related routines */
1426
+
int pci_rebar_bytes_to_size(u64 bytes);
1427
+
resource_size_t pci_rebar_size_to_bytes(int size);
1428
+
u64 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1429
+
bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size);
1430
+
int pci_rebar_get_max_size(struct pci_dev *pdev, int bar);
1431
+
int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size,
1432
+
int exclude_bars);
1435
1433
1436
-
u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1437
-
int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1438
1434
int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1439
1435
bool pci_device_is_present(struct pci_dev *pdev);
1440
1436
void pci_ignore_hotplug(struct pci_dev *dev);
···
1962
1958
*/
1963
1959
#ifdef CONFIG_PCI_DOMAINS
1964
1960
extern int pci_domains_supported;
1961
+
int pci_bus_find_emul_domain_nr(u32 hint, u32 min, u32 max);
1962
+
void pci_bus_release_emul_domain_nr(int domain_nr);
1965
1963
#else
1966
1964
enum { pci_domains_supported = 0 };
1967
1965
static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1968
1966
static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1967
+
static inline int pci_bus_find_emul_domain_nr(u32 hint, u32 min, u32 max)
1968
+
{
1969
+
return 0;
1970
+
}
1971
+
static inline void pci_bus_release_emul_domain_nr(int domain_nr) { }
1969
1972
#endif /* CONFIG_PCI_DOMAINS */
1970
1973
1971
1974
/*