Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpio: hlwd: use new generic GPIO chip API
Convert the driver to using the new generic GPIO chip interfaces from
linux/gpio/generic.h.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20250910-gpio-mmio-gpio-conv-part4-v2-3-f3d1a4c57124@linaro.org
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
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drivers/gpio/gpio-hlwd.c
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drivers/gpio/gpio-hlwd.c
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// Nintendo Wii (Hollywood) GPIO driver
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#include <linux/gpio/driver.h>
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#include <linux/gpio/generic.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#define HW_GPIO_OWNER 0x3c
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struct hlwd_gpio {
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struct gpio_chip gpioc;
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struct gpio_generic_chip gpioc;
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struct device *dev;
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void __iomem *regs;
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int irq;
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struct hlwd_gpio *hlwd =
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gpiochip_get_data(irq_desc_get_handler_data(desc));
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long flags;
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unsigned long pending;
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int hwirq;
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u32 emulated_pending;
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raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
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pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
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pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
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scoped_guard(gpio_generic_lock_irqsave, &hlwd->gpioc) {
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pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
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pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
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/* Treat interrupts due to edge trigger emulation separately */
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emulated_pending = hlwd->edge_emulation & pending;
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pending &= ~emulated_pending;
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if (emulated_pending) {
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u32 level, rising, falling;
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/* Treat interrupts due to edge trigger emulation separately */
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emulated_pending = hlwd->edge_emulation & pending;
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pending &= ~emulated_pending;
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if (emulated_pending) {
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u32 level, rising, falling;
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level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
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rising = level & emulated_pending;
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falling = ~level & emulated_pending;
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level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
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rising = level & emulated_pending;
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falling = ~level & emulated_pending;
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/* Invert the levels */
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iowrite32be(level ^ emulated_pending,
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hlwd->regs + HW_GPIOB_INTLVL);
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/* Invert the levels */
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iowrite32be(level ^ emulated_pending,
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hlwd->regs + HW_GPIOB_INTLVL);
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/* Ack all emulated-edge interrupts */
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iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
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/* Ack all emulated-edge interrupts */
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iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
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/* Signal interrupts only on the correct edge */
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rising &= hlwd->rising_edge;
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falling &= hlwd->falling_edge;
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/* Signal interrupts only on the correct edge */
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rising &= hlwd->rising_edge;
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falling &= hlwd->falling_edge;
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/* Mark emulated interrupts as pending */
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pending |= rising | falling;
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/* Mark emulated interrupts as pending */
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pending |= rising | falling;
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}
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}
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raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
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chained_irq_enter(chip, desc);
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for_each_set_bit(hwirq, &pending, 32)
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generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq);
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generic_handle_domain_irq(hlwd->gpioc.gc.irq.domain, hwirq);
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chained_irq_exit(chip, desc);
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}
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{
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struct hlwd_gpio *hlwd =
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gpiochip_get_data(irq_data_get_irq_chip_data(data));
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unsigned long flags;
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u32 mask;
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raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
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mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
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mask &= ~BIT(data->hwirq);
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iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
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raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
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gpiochip_disable_irq(&hlwd->gpioc, irqd_to_hwirq(data));
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scoped_guard(gpio_generic_lock_irqsave, &hlwd->gpioc) {
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mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
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mask &= ~BIT(data->hwirq);
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iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
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}
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gpiochip_disable_irq(&hlwd->gpioc.gc, irqd_to_hwirq(data));
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}
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static void hlwd_gpio_irq_unmask(struct irq_data *data)
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{
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struct hlwd_gpio *hlwd =
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gpiochip_get_data(irq_data_get_irq_chip_data(data));
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unsigned long flags;
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u32 mask;
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gpiochip_enable_irq(&hlwd->gpioc, irqd_to_hwirq(data));
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raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
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gpiochip_enable_irq(&hlwd->gpioc.gc, irqd_to_hwirq(data));
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guard(gpio_generic_lock_irqsave)(&hlwd->gpioc);
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mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
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mask |= BIT(data->hwirq);
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iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
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raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
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}
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static void hlwd_gpio_irq_enable(struct irq_data *data)
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{
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struct hlwd_gpio *hlwd =
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gpiochip_get_data(irq_data_get_irq_chip_data(data));
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unsigned long flags;
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u32 level;
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raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
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guard(gpio_generic_lock_irqsave)(&hlwd->gpioc);
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hlwd->edge_emulation &= ~BIT(data->hwirq);
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hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
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break;
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default:
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raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
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return -EINVAL;
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}
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raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
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return 0;
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}
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static int hlwd_gpio_probe(struct platform_device *pdev)
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{
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struct gpio_generic_chip_config config;
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struct hlwd_gpio *hlwd;
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u32 ngpios;
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int res;
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* systems where the AHBPROT memory firewall hasn't been configured to
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* permit PPC access to HW_GPIO_*.
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*
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* Note that this has to happen before bgpio_init reads the
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* HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the wrong
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* values.
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* Note that this has to happen before gpio_generic_chip_init() reads
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* the HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the
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* wrong values.
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*/
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iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);
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res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,
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hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,
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NULL, hlwd->regs + HW_GPIOB_DIR, NULL,
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BGPIOF_BIG_ENDIAN_BYTE_ORDER);
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config = (struct gpio_generic_chip_config) {
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.dev = &pdev->dev,
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.sz = 4,
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.dat = hlwd->regs + HW_GPIOB_IN,
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.set = hlwd->regs + HW_GPIOB_OUT,
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.dirout = hlwd->regs + HW_GPIOB_DIR,
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.flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER,
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};
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res = gpio_generic_chip_init(&hlwd->gpioc, &config);
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if (res < 0) {
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dev_warn(&pdev->dev, "bgpio_init failed: %d\n", res);
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dev_warn(&pdev->dev, "failed to initialize generic GPIO chip: %d\n", res);
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return res;
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}
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res = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios);
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if (res)
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ngpios = 32;
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hlwd->gpioc.ngpio = ngpios;
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hlwd->gpioc.gc.ngpio = ngpios;
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/* Mask and ack all interrupts */
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iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
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return hlwd->irq;
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}
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girq = &hlwd->gpioc.irq;
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girq = &hlwd->gpioc.gc.irq;
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gpio_irq_chip_set_chip(girq, &hlwd_gpio_irq_chip);
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girq->parent_handler = hlwd_gpio_irqhandler;
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girq->num_parents = 1;
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girq->handler = handle_level_irq;
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}
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return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
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return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc.gc, hlwd);
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}
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static const struct of_device_id hlwd_gpio_match[] = {