+5 -5

Documentation/arm64/acpi_object_usage.rst

reviewed

··· 17 17 18 18 - Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT 19 19 20 20 - - Optional: BGRT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT, IORT, 21 21 - MCHI, MPST, MSCT, NFIT, PMTT, RASF, SBST, SLIT, SPMI, SRAT, STAO, 22 22 - TCPA, TPM2, UEFI, XENV 20 20 + - Optional: BGRT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT, IBFT, 21 21 + IORT, MCHI, MPST, MSCT, NFIT, PMTT, RASF, SBST, SLIT, SPMI, SRAT, 22 22 + STAO, TCPA, TPM2, UEFI, XENV 23 23 24 24 - - Not supported: BOOT, DBGP, DMAR, ETDT, HPET, IBFT, IVRS, LPIT, 25 25 - MSDM, OEMx, PSDT, RSDT, SLIC, WAET, WDAT, WDRT, WPBT 24 24 + - Not supported: BOOT, DBGP, DMAR, ETDT, HPET, IVRS, LPIT, MSDM, OEMx, 25 25 + PSDT, RSDT, SLIC, WAET, WDAT, WDRT, WPBT 26 26 27 27 ====== ======================================================================== 28 28 Table Usage for ARMv8 Linux

+3

Documentation/arm64/silicon-errata.rst

reviewed

··· 130 130 | Marvell | ARM-MMU-500 | #582743 | N/A | 131 131 +----------------+-----------------+-----------------+-----------------------------+ 132 132 +----------------+-----------------+-----------------+-----------------------------+ 133 133 + | NVIDIA | Carmel Core | N/A | NVIDIA_CARMEL_CNP_ERRATUM | 134 134 + +----------------+-----------------+-----------------+-----------------------------+ 135 135 + +----------------+-----------------+-----------------+-----------------------------+ 133 136 | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | 134 137 +----------------+-----------------+-----------------+-----------------------------+ 135 138 +----------------+-----------------+-----------------+-----------------------------+

+10

arch/arm64/Kconfig

reviewed

··· 810 810 811 811 If unsure, say Y. 812 812 813 813 + config NVIDIA_CARMEL_CNP_ERRATUM 814 814 + bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 815 815 + default y 816 816 + help 817 817 + If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 818 818 + invalidate shared TLB entries installed by a different core, as it would 819 819 + on standard ARM cores. 820 820 + 821 821 + If unsure, say Y. 822 822 + 813 823 config SOCIONEXT_SYNQUACER_PREITS 814 824 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 815 825 default y

+1 -1

arch/arm64/include/asm/checksum.h

reviewed

··· 37 37 } while (--n > 0); 38 38 39 39 sum += ((sum >> 32) | (sum << 32)); 40 40 - return csum_fold((__force u32)(sum >> 32)); 40 40 + return csum_fold((__force __wsum)(sum >> 32)); 41 41 } 42 42 #define ip_fast_csum ip_fast_csum 43 43

+2 -1

arch/arm64/include/asm/cpucaps.h

reviewed

··· 66 66 #define ARM64_WORKAROUND_1508412 58 67 67 #define ARM64_HAS_LDAPR 59 68 68 #define ARM64_KVM_PROTECTED_MODE 60 69 69 + #define ARM64_WORKAROUND_NVIDIA_CARMEL_CNP 61 69 70 70 70 - #define ARM64_NCAPS 61 71 71 + #define ARM64_NCAPS 62 71 72 72 73 #endif /* __ASM_CPUCAPS_H */

+2

arch/arm64/include/asm/processor.h

reviewed

··· 251 251 extern struct task_struct *cpu_switch_to(struct task_struct *prev, 252 252 struct task_struct *next); 253 253 254 254 + asmlinkage void arm64_preempt_schedule_irq(void); 255 255 + 254 256 #define task_pt_regs(p) \ 255 257 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1) 256 258

+2

arch/arm64/include/asm/thread_info.h

reviewed

··· 55 55 #define arch_setup_new_exec arch_setup_new_exec 56 56 57 57 void arch_release_task_struct(struct task_struct *tsk); 58 58 + int arch_dup_task_struct(struct task_struct *dst, 59 59 + struct task_struct *src); 58 60 59 61 #endif 60 62

+8

arch/arm64/kernel/cpu_errata.c

reviewed

··· 526 526 1, 0), 527 527 }, 528 528 #endif 529 529 + #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM 530 530 + { 531 531 + /* NVIDIA Carmel */ 532 532 + .desc = "NVIDIA Carmel CNP erratum", 533 533 + .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP, 534 534 + ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 535 535 + }, 536 536 + #endif 529 537 { 530 538 } 531 539 };

+4 -1

arch/arm64/kernel/cpufeature.c

reviewed

··· 1321 1321 * may share TLB entries with a CPU stuck in the crashed 1322 1322 * kernel. 1323 1323 */ 1324 1324 - if (is_kdump_kernel()) 1324 1324 + if (is_kdump_kernel()) 1325 1325 + return false; 1326 1326 + 1327 1327 + if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1325 1328 return false; 1326 1329 1327 1330 return has_cpuid_feature(entry, scope);

+1 -1

arch/arm64/kernel/cpuinfo.c

reviewed

··· 353 353 * with the CLIDR_EL1 fields to avoid triggering false warnings 354 354 * when there is a mismatch across the CPUs. Keep track of the 355 355 * effective value of the CTR_EL0 in our internal records for 356 356 - * acurate sanity check and feature enablement. 356 356 + * accurate sanity check and feature enablement. 357 357 */ 358 358 info->reg_ctr = read_cpuid_effective_cachetype(); 359 359 info->reg_dczid = read_cpuid(DCZID_EL0);

+2

arch/arm64/kernel/crash_dump.c

reviewed

··· 64 64 ssize_t elfcorehdr_read(char *buf, size_t count, u64 *ppos) 65 65 { 66 66 memcpy(buf, phys_to_virt((phys_addr_t)*ppos), count); 67 67 + *ppos += count; 68 68 + 67 69 return count; 68 70 }

+2

arch/arm64/kernel/process.c

reviewed

··· 57 57 #include <asm/processor.h> 58 58 #include <asm/pointer_auth.h> 59 59 #include <asm/stacktrace.h> 60 60 + #include <asm/switch_to.h> 61 61 + #include <asm/system_misc.h> 60 62 61 63 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK) 62 64 #include <linux/stackprotector.h>

+5 -4

arch/arm64/kernel/stacktrace.c

reviewed

··· 194 194 195 195 #ifdef CONFIG_STACKTRACE 196 196 197 197 - void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie, 198 198 - struct task_struct *task, struct pt_regs *regs) 197 197 + noinline void arch_stack_walk(stack_trace_consume_fn consume_entry, 198 198 + void *cookie, struct task_struct *task, 199 199 + struct pt_regs *regs) 199 200 { 200 201 struct stackframe frame; 201 202 ··· 204 203 start_backtrace(&frame, regs->regs[29], regs->pc); 205 204 else if (task == current) 206 205 start_backtrace(&frame, 207 207 - (unsigned long)__builtin_frame_address(0), 208 208 - (unsigned long)arch_stack_walk); 206 206 + (unsigned long)__builtin_frame_address(1), 207 207 + (unsigned long)__builtin_return_address(0)); 209 208 else 210 209 start_backtrace(&frame, thread_saved_fp(task), 211 210 thread_saved_pc(task));

+19 -2

arch/arm64/mm/mmu.c

reviewed

··· 1448 1448 struct range arch_get_mappable_range(void) 1449 1449 { 1450 1450 struct range mhp_range; 1451 1451 + u64 start_linear_pa = __pa(_PAGE_OFFSET(vabits_actual)); 1452 1452 + u64 end_linear_pa = __pa(PAGE_END - 1); 1453 1453 + 1454 1454 + if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { 1455 1455 + /* 1456 1456 + * Check for a wrap, it is possible because of randomized linear 1457 1457 + * mapping the start physical address is actually bigger than 1458 1458 + * the end physical address. In this case set start to zero 1459 1459 + * because [0, end_linear_pa] range must still be able to cover 1460 1460 + * all addressable physical addresses. 1461 1461 + */ 1462 1462 + if (start_linear_pa > end_linear_pa) 1463 1463 + start_linear_pa = 0; 1464 1464 + } 1465 1465 + 1466 1466 + WARN_ON(start_linear_pa > end_linear_pa); 1451 1467 1452 1468 /* 1453 1469 * Linear mapping region is the range [PAGE_OFFSET..(PAGE_END - 1)] ··· 1471 1455 * range which can be mapped inside this linear mapping range, must 1472 1456 * also be derived from its end points. 1473 1457 */ 1474 1474 - mhp_range.start = __pa(_PAGE_OFFSET(vabits_actual)); 1475 1475 - mhp_range.end = __pa(PAGE_END - 1); 1458 1458 + mhp_range.start = start_linear_pa; 1459 1459 + mhp_range.end = end_linear_pa; 1460 1460 + 1476 1461 return mhp_range; 1477 1462 } 1478 1463

+17 -5

tools/testing/selftests/arm64/fp/sve-test.S

reviewed

··· 284 284 // Set up test pattern in the FFR 285 285 // x0: pid 286 286 // x2: generation 287 287 + // 288 288 + // We need to generate a canonical FFR value, which consists of a number of 289 289 + // low "1" bits, followed by a number of zeros. This gives us 17 unique values 290 290 + // per 16 bits of FFR, so we create a 4 bit signature out of the PID and 291 291 + // generation, and use that as the initial number of ones in the pattern. 292 292 + // We fill the upper lanes of FFR with zeros. 287 293 // Beware: corrupts P0. 288 294 function setup_ffr 289 295 mov x4, x30 290 296 291 291 - bl pattern 297 297 + and w0, w0, #0x3 298 298 + bfi w0, w2, #2, #2 299 299 + mov w1, #1 300 300 + lsl w1, w1, w0 301 301 + sub w1, w1, #1 302 302 + 292 303 ldr x0, =ffrref 293 293 - ldr x1, =scratch 294 294 - rdvl x2, #1 295 295 - lsr x2, x2, #3 296 296 - bl memcpy 304 304 + strh w1, [x0], 2 305 305 + rdvl x1, #1 306 306 + lsr x1, x1, #3 307 307 + sub x1, x1, #2 308 308 + bl memclr 297 309 298 310 mov x0, #0 299 311 ldr x1, =ffrref