Merge tag 'drm-for-v4.15-part2-fixes' of git://people.freedesktop.org/~airlied/linux

+10 -2

drivers/gpu/drm/drm_edid.c

··· 4831 4831 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 4832 4832 const struct drm_display_mode *mode, 4833 4833 enum hdmi_quantization_range rgb_quant_range, 4834 - bool rgb_quant_range_selectable) 4834 + bool rgb_quant_range_selectable, 4835 + bool is_hdmi2_sink) 4835 4836 { 4836 4837 /* 4837 4838 * CEA-861: ··· 4856 4855 * YQ-field to match the RGB Quantization Range being transmitted 4857 4856 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 4858 4857 * set YQ=1) and the Sink shall ignore the YQ-field." 4858 + * 4859 + * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 4860 + * by non-zero YQ when receiving RGB. There doesn't seem to be any 4861 + * good way to tell which version of CEA-861 the sink supports, so 4862 + * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 4863 + * on on CEA-861-F. 4859 4864 */ 4860 - if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 4865 + if (!is_hdmi2_sink || 4866 + rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 4861 4867 frame->ycc_quantization_range = 4862 4868 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 4863 4869 else

+1

drivers/gpu/drm/drm_plane.c

··· 1030 1030 e->event.base.type = DRM_EVENT_FLIP_COMPLETE; 1031 1031 e->event.base.length = sizeof(e->event); 1032 1032 e->event.vbl.user_data = page_flip->user_data; 1033 + e->event.vbl.crtc_id = crtc->base.id; 1033 1034 ret = drm_event_reserve_init(dev, file_priv, &e->base, &e->event.base); 1034 1035 if (ret) { 1035 1036 kfree(e);

+1 -1

drivers/gpu/drm/i915/gvt/cmd_parser.c

··· 1628 1628 struct intel_shadow_bb_entry *entry_obj; 1629 1629 struct intel_vgpu *vgpu = s->vgpu; 1630 1630 unsigned long gma = 0; 1631 - uint32_t bb_size; 1631 + int bb_size; 1632 1632 void *dst = NULL; 1633 1633 int ret = 0; 1634 1634

+3

drivers/gpu/drm/i915/i915_drv.c

··· 1714 1714 intel_guc_resume(dev_priv); 1715 1715 1716 1716 intel_modeset_init_hw(dev); 1717 + intel_init_clock_gating(dev_priv); 1717 1718 1718 1719 spin_lock_irq(&dev_priv->irq_lock); 1719 1720 if (dev_priv->display.hpd_irq_setup) ··· 2618 2617 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2619 2618 ret = vlv_resume_prepare(dev_priv, true); 2620 2619 } 2620 + 2621 + intel_uncore_runtime_resume(dev_priv); 2621 2622 2622 2623 /* 2623 2624 * No point of rolling back things in case of an error, as the best

+4 -2

drivers/gpu/drm/i915/i915_gem_userptr.c

··· 172 172 spin_lock_init(&mn->lock); 173 173 mn->mn.ops = &i915_gem_userptr_notifier; 174 174 mn->objects = RB_ROOT_CACHED; 175 - mn->wq = alloc_workqueue("i915-userptr-release", WQ_UNBOUND, 0); 175 + mn->wq = alloc_workqueue("i915-userptr-release", 176 + WQ_UNBOUND | WQ_MEM_RECLAIM, 177 + 0); 176 178 if (mn->wq == NULL) { 177 179 kfree(mn); 178 180 return ERR_PTR(-ENOMEM); ··· 829 827 830 828 dev_priv->mm.userptr_wq = 831 829 alloc_workqueue("i915-userptr-acquire", 832 - WQ_HIGHPRI | WQ_MEM_RECLAIM, 830 + WQ_HIGHPRI | WQ_UNBOUND, 833 831 0); 834 832 if (!dev_priv->mm.userptr_wq) 835 833 return -ENOMEM;

+1

drivers/gpu/drm/i915/intel_breadcrumbs.c

··· 517 517 518 518 GEM_BUG_ON(RB_EMPTY_NODE(&wait->node)); 519 519 rb_erase(&wait->node, &b->waiters); 520 + RB_CLEAR_NODE(&wait->node); 520 521 521 522 out: 522 523 GEM_BUG_ON(b->irq_wait == wait);

+2 -1

drivers/gpu/drm/i915/intel_hdmi.c

··· 487 487 crtc_state->limited_color_range ? 488 488 HDMI_QUANTIZATION_RANGE_LIMITED : 489 489 HDMI_QUANTIZATION_RANGE_FULL, 490 - intel_hdmi->rgb_quant_range_selectable); 490 + intel_hdmi->rgb_quant_range_selectable, 491 + is_hdmi2_sink); 491 492 492 493 /* TODO: handle pixel repetition for YCBCR420 outputs */ 493 494 intel_write_infoframe(encoder, crtc_state, &frame);

+13

drivers/gpu/drm/i915/intel_uncore.c

··· 434 434 i915_check_and_clear_faults(dev_priv); 435 435 } 436 436 437 + void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv) 438 + { 439 + iosf_mbi_register_pmic_bus_access_notifier( 440 + &dev_priv->uncore.pmic_bus_access_nb); 441 + } 442 + 437 443 void intel_uncore_sanitize(struct drm_i915_private *dev_priv) 438 444 { 439 445 i915_modparams.enable_rc6 = ··· 1246 1240 * bus, which will be busy after this notification, leading to: 1247 1241 * "render: timed out waiting for forcewake ack request." 1248 1242 * errors. 1243 + * 1244 + * The notifier is unregistered during intel_runtime_suspend(), 1245 + * so it's ok to access the HW here without holding a RPM 1246 + * wake reference -> disable wakeref asserts for the time of 1247 + * the access. 1249 1248 */ 1249 + disable_rpm_wakeref_asserts(dev_priv); 1250 1250 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 1251 + enable_rpm_wakeref_asserts(dev_priv); 1251 1252 break; 1252 1253 case MBI_PMIC_BUS_ACCESS_END: 1253 1254 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

+1

drivers/gpu/drm/i915/intel_uncore.h

··· 134 134 void intel_uncore_fini(struct drm_i915_private *dev_priv); 135 135 void intel_uncore_suspend(struct drm_i915_private *dev_priv); 136 136 void intel_uncore_resume_early(struct drm_i915_private *dev_priv); 137 + void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv); 137 138 138 139 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv); 139 140 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);

+20 -16

drivers/gpu/drm/ttm/ttm_page_alloc.c

··· 744 744 } 745 745 746 746 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 747 - for (j = 0; j < HPAGE_PMD_NR; ++j) 748 - if (p++ != pages[i + j]) 749 - break; 747 + if (!(flags & TTM_PAGE_FLAG_DMA32)) { 748 + for (j = 0; j < HPAGE_PMD_NR; ++j) 749 + if (p++ != pages[i + j]) 750 + break; 750 751 751 - if (j == HPAGE_PMD_NR) 752 - order = HPAGE_PMD_ORDER; 752 + if (j == HPAGE_PMD_NR) 753 + order = HPAGE_PMD_ORDER; 754 + } 753 755 #endif 754 756 755 757 if (page_count(pages[i]) != 1) ··· 867 865 868 866 i = 0; 869 867 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 870 - while (npages >= HPAGE_PMD_NR) { 871 - gfp_t huge_flags = gfp_flags; 868 + if (!(gfp_flags & GFP_DMA32)) { 869 + while (npages >= HPAGE_PMD_NR) { 870 + gfp_t huge_flags = gfp_flags; 872 871 873 - huge_flags |= GFP_TRANSHUGE; 874 - huge_flags &= ~__GFP_MOVABLE; 875 - huge_flags &= ~__GFP_COMP; 876 - p = alloc_pages(huge_flags, HPAGE_PMD_ORDER); 877 - if (!p) 878 - break; 872 + huge_flags |= GFP_TRANSHUGE; 873 + huge_flags &= ~__GFP_MOVABLE; 874 + huge_flags &= ~__GFP_COMP; 875 + p = alloc_pages(huge_flags, HPAGE_PMD_ORDER); 876 + if (!p) 877 + break; 879 878 880 - for (j = 0; j < HPAGE_PMD_NR; ++j) 881 - pages[i++] = p++; 879 + for (j = 0; j < HPAGE_PMD_NR; ++j) 880 + pages[i++] = p++; 882 881 883 - npages -= HPAGE_PMD_NR; 882 + npages -= HPAGE_PMD_NR; 883 + } 884 884 } 885 885 #endif 886 886

+2 -1

drivers/gpu/drm/vc4/vc4_hdmi.c

··· 424 424 vc4_encoder->limited_rgb_range ? 425 425 HDMI_QUANTIZATION_RANGE_LIMITED : 426 426 HDMI_QUANTIZATION_RANGE_FULL, 427 - vc4_encoder->rgb_range_selectable); 427 + vc4_encoder->rgb_range_selectable, 428 + false); 428 429 429 430 vc4_hdmi_write_infoframe(encoder, &frame); 430 431 }

+6

drivers/gpu/drm/vc4/vc4_irq.c

··· 208 208 { 209 209 struct vc4_dev *vc4 = to_vc4_dev(dev); 210 210 211 + /* Undo the effects of a previous vc4_irq_uninstall. */ 212 + enable_irq(dev->irq); 213 + 211 214 /* Enable both the render done and out of memory interrupts. */ 212 215 V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS); 213 216 ··· 227 224 228 225 /* Clear any pending interrupts we might have left. */ 229 226 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS); 227 + 228 + /* Finish any interrupt handler still in flight. */ 229 + disable_irq(dev->irq); 230 230 231 231 cancel_work_sync(&vc4->overflow_mem_work); 232 232 }

+2 -1

include/drm/drm_edid.h

··· 362 362 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 363 363 const struct drm_display_mode *mode, 364 364 enum hdmi_quantization_range rgb_quant_range, 365 - bool rgb_quant_range_selectable); 365 + bool rgb_quant_range_selectable, 366 + bool is_hdmi2_sink); 366 367 367 368 /** 368 369 * drm_eld_mnl - Get ELD monitor name length in bytes.

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