drm/amdgpu: remove hdp flush/invalidation completely for gfx12.1.0/sdma7.1.0

+1 -69

2 changed files

expand all

drivers

gpu

drm

amd

amdgpu

gfx_v12_1.c

sdma_v7_1.c

+1 -37

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

··· 2427 2427 if (r) 2428 2428 return r; 2429 2429 2430 - adev->hdp.funcs->flush_hdp(adev, NULL); 2431 - 2432 2430 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 2433 2431 false : true; 2434 2432 2435 2433 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2436 - /* TODO investigate why this and the hdp flush above is needed, 2434 + /* TODO investigate why TLB flush is needed, 2437 2435 * are we missing a flush somewhere else? */ 2438 2436 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 2439 2437 ··· 3143 3145 } 3144 3146 } 3145 3147 3146 - static void gfx_v12_1_ring_emit_hdp_flush(struct amdgpu_ring *ring) 3147 - { 3148 - struct amdgpu_device *adev = ring->adev; 3149 - u32 ref_and_mask, reg_mem_engine; 3150 - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 3151 - 3152 - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3153 - switch (ring->me) { 3154 - case 1: 3155 - ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 3156 - break; 3157 - case 2: 3158 - ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 3159 - break; 3160 - default: 3161 - return; 3162 - } 3163 - reg_mem_engine = 0; 3164 - } else { 3165 - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 3166 - reg_mem_engine = 1; /* pfp */ 3167 - } 3168 - 3169 - gfx_v12_1_wait_reg_mem(ring, reg_mem_engine, 0, 1, 3170 - adev->nbio.funcs->get_hdp_flush_req_offset(adev), 3171 - adev->nbio.funcs->get_hdp_flush_done_offset(adev), 3172 - ref_and_mask, ref_and_mask, 0x20); 3173 - } 3174 - 3175 3148 static void gfx_v12_1_ring_emit_ib_compute(struct amdgpu_ring *ring, 3176 3149 struct amdgpu_job *job, 3177 3150 struct amdgpu_ib *ib, ··· 3627 3658 .get_wptr = gfx_v12_1_ring_get_wptr_compute, 3628 3659 .set_wptr = gfx_v12_1_ring_set_wptr_compute, 3629 3660 .emit_frame_size = 3630 - 7 + /* gfx_v12_1_ring_emit_hdp_flush */ 3631 - 5 + /* hdp invalidate */ 3632 3661 7 + /* gfx_v12_1_ring_emit_pipeline_sync */ 3633 3662 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 3634 3663 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + ··· 3638 3671 .emit_fence = gfx_v12_1_ring_emit_fence, 3639 3672 .emit_pipeline_sync = gfx_v12_1_ring_emit_pipeline_sync, 3640 3673 .emit_vm_flush = gfx_v12_1_ring_emit_vm_flush, 3641 - .emit_hdp_flush = gfx_v12_1_ring_emit_hdp_flush, 3642 3674 .test_ring = gfx_v12_1_ring_test_ring, 3643 3675 .test_ib = gfx_v12_1_ring_test_ib, 3644 3676 .insert_nop = amdgpu_ring_insert_nop, ··· 3657 3691 .get_wptr = gfx_v12_1_ring_get_wptr_compute, 3658 3692 .set_wptr = gfx_v12_1_ring_set_wptr_compute, 3659 3693 .emit_frame_size = 3660 - 7 + /* gfx_v12_1_ring_emit_hdp_flush */ 3661 - 5 + /*hdp invalidate */ 3662 3694 7 + /* gfx_v12_1_ring_emit_pipeline_sync */ 3663 3695 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 3664 3696 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +

-32

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

··· 32 32 33 33 #include "gc/gc_12_1_0_offset.h" 34 34 #include "gc/gc_12_1_0_sh_mask.h" 35 - #include "hdp/hdp_6_0_0_offset.h" 36 35 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 37 36 38 37 #include "soc15_common.h" ··· 310 311 SDMA_PKT_GCR_REQ_PAYLOAD5_VMID(0)); 311 312 } 312 313 313 - 314 - /** 315 - * sdma_v7_1_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 316 - * 317 - * @ring: amdgpu ring pointer 318 - * 319 - * Emit an hdp flush packet on the requested DMA ring. 320 - */ 321 - static void sdma_v7_1_ring_emit_hdp_flush(struct amdgpu_ring *ring) 322 - { 323 - struct amdgpu_device *adev = ring->adev; 324 - u32 ref_and_mask = 0; 325 - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 326 - 327 - ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 328 - << (ring->me % adev->sdma.num_inst_per_xcc); 329 - 330 - amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 331 - SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 332 - SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 333 - amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 334 - amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 335 - amdgpu_ring_write(ring, ref_and_mask); /* reference */ 336 - amdgpu_ring_write(ring, ref_and_mask); /* mask */ 337 - amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 338 - SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 339 - } 340 314 341 315 /** 342 316 * sdma_v7_1_ring_emit_fence - emit a fence on the DMA ring ··· 1187 1215 1188 1216 /* wait for idle */ 1189 1217 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1190 - SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1191 1218 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1192 1219 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1193 1220 amdgpu_ring_write(ring, addr & 0xfffffffc); ··· 1228 1257 uint32_t val, uint32_t mask) 1229 1258 { 1230 1259 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1231 - SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1232 1260 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1233 1261 amdgpu_ring_write(ring, reg << 2); 1234 1262 amdgpu_ring_write(ring, 0); ··· 1637 1667 .set_wptr = sdma_v7_1_ring_set_wptr, 1638 1668 .emit_frame_size = 1639 1669 5 + /* sdma_v7_1_ring_init_cond_exec */ 1640 - 6 + /* sdma_v7_1_ring_emit_hdp_flush */ 1641 1670 6 + /* sdma_v7_1_ring_emit_pipeline_sync */ 1642 1671 /* sdma_v7_1_ring_emit_vm_flush */ 1643 1672 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + ··· 1648 1679 .emit_fence = sdma_v7_1_ring_emit_fence, 1649 1680 .emit_pipeline_sync = sdma_v7_1_ring_emit_pipeline_sync, 1650 1681 .emit_vm_flush = sdma_v7_1_ring_emit_vm_flush, 1651 - .emit_hdp_flush = sdma_v7_1_ring_emit_hdp_flush, 1652 1682 .test_ring = sdma_v7_1_ring_test_ring, 1653 1683 .test_ib = sdma_v7_1_ring_test_ib, 1654 1684 .insert_nop = sdma_v7_1_ring_insert_nop,

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