Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'aquantia-phy-driver-consolidation-part-1'
Vladimir Oltean says:
====================
Aquantia PHY driver consolidation - part 1
This started out as an effort to add some new features hinging on the
VEND1_GLOBAL_CFG_* registers, but I quickly started to notice that the
Aquantia PHY driver has a large code base, but individual PHYs only
implement arbitrary subsets of it.
The table below lists the PHYs known to me to have the
VEND1_GLOBAL_CFG_* registers.
PHY Access from Access from
aqr107_read_rate() aqr113c_fill_interface_modes()
------------------------------------------------------------------
AQR107 y n
AQCS109 y n
AQR111 y n
AQR111B0 y n
AQR112 y n
AQR412 y n
AQR113 y y
AQR113C y y
AQR813 y n
AQR114C y n
AQR115C y y
Maybe you're wondering, after reading this, why don't more Aquantia PHYs
populate phydev->possible_interfaces based on the registers that they
are known to have? And why do AQR114C and AQR115C, PHYs from the same
generation, just having different max speeds, differ in this behaviour?
And why does AQR813, the 8-port variant of AQR113, not call
aqr113c_config_init(), but aqr107_config_init()?
I did wonder, and I don't know either, but I suspect it has to do with
developers not wanting to break what they can't test, and only touching
what they are interested in. Multiplied at a large enough scale, this
tends to result in unmaintainable code.
The tendency might also be encouraged by the slightly strange and
inconsistent naming scheme in this driver.
The set proposes a naming scheme based on generations, and feature
inheritance from Gen X to Gen X+1. This helps fill in missing
software functionalities where the hardware feature should be present.
I had to put a hard stop at 15 patches, so I've picked the more
meaningful functions to consolidate, rather than going through the
entire driver. Depending on review feedback, I can do more or I can
stop.
Furthermore, the set adds generation-appropriate support for two more
PHY IDs: AQR412 and AQR115, and fixes the improper reporting of AQR412C
as AQR412.
The changes were tested on AQR107, AQR112, AQR412C and AQR115.
====================
Link: https://patch.msgid.link/20250821152022.1065237-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+289
-270
+28
drivers/net/phy/aquantia/aquantia.h
+28
drivers/net/phy/aquantia/aquantia.h
···
174
174
175
175
#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
176
176
177
+
static const struct {
178
+
int speed;
179
+
u16 reg;
180
+
} aqr_global_cfg_regs[] = {
181
+
{ SPEED_10, VEND1_GLOBAL_CFG_10M, },
182
+
{ SPEED_100, VEND1_GLOBAL_CFG_100M, },
183
+
{ SPEED_1000, VEND1_GLOBAL_CFG_1G, },
184
+
{ SPEED_2500, VEND1_GLOBAL_CFG_2_5G, },
185
+
{ SPEED_5000, VEND1_GLOBAL_CFG_5G, },
186
+
{ SPEED_10000, VEND1_GLOBAL_CFG_10G, },
187
+
};
188
+
189
+
#define AQR_NUM_GLOBAL_CFG ARRAY_SIZE(aqr_global_cfg_regs)
190
+
191
+
enum aqr_rate_adaptation {
192
+
AQR_RATE_ADAPT_NONE,
193
+
AQR_RATE_ADAPT_USX,
194
+
AQR_RATE_ADAPT_PAUSE,
195
+
};
196
+
197
+
struct aqr_global_syscfg {
198
+
int speed;
199
+
phy_interface_t interface;
200
+
enum aqr_rate_adaptation rate_adapt;
201
+
};
202
+
177
203
struct aqr107_priv {
178
204
u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
179
205
unsigned long leds_active_low;
180
206
unsigned long leds_active_high;
207
+
bool wait_on_global_cfg;
208
+
struct aqr_global_syscfg global_cfg[AQR_NUM_GLOBAL_CFG];
181
209
};
182
210
183
211
#if IS_REACHABLE(CONFIG_HWMON)
+261
-270
drivers/net/phy/aquantia/aquantia_main.c
+261
-270
drivers/net/phy/aquantia/aquantia_main.c
···
26
26
#define PHY_ID_AQR111 0x03a1b610
27
27
#define PHY_ID_AQR111B0 0x03a1b612
28
28
#define PHY_ID_AQR112 0x03a1b662
29
-
#define PHY_ID_AQR412 0x03a1b712
29
+
#define PHY_ID_AQR412 0x03a1b6f2
30
+
#define PHY_ID_AQR412C 0x03a1b712
30
31
#define PHY_ID_AQR113 0x31c31c40
31
32
#define PHY_ID_AQR113C 0x31c31c12
32
33
#define PHY_ID_AQR114C 0x31c31c22
34
+
#define PHY_ID_AQR115 0x31c31c63
33
35
#define PHY_ID_AQR115C 0x31c31c33
34
36
#define PHY_ID_AQR813 0x31c31cb2
35
37
···
467
465
return genphy_c45_check_and_restart_aneg(phydev, changed);
468
466
}
469
467
470
-
static int aqr105_read_rate(struct phy_device *phydev)
468
+
static int aqr_gen1_read_rate(struct phy_device *phydev)
471
469
{
472
470
int val;
473
471
···
506
504
return 0;
507
505
}
508
506
509
-
static int aqr105_read_status(struct phy_device *phydev)
507
+
static int aqr_gen1_read_status(struct phy_device *phydev)
510
508
{
511
509
int ret;
512
510
int val;
···
564
562
}
565
563
566
564
/* Read rate from vendor register */
567
-
return aqr105_read_rate(phydev);
565
+
return aqr_gen1_read_rate(phydev);
568
566
}
569
567
570
-
static int aqr107_read_rate(struct phy_device *phydev)
568
+
static int aqr_gen2_read_status(struct phy_device *phydev)
571
569
{
572
-
u32 config_reg;
573
-
int val;
570
+
struct aqr107_priv *priv = phydev->priv;
571
+
int i, ret;
574
572
575
-
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
576
-
if (val < 0)
577
-
return val;
578
-
579
-
if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
580
-
phydev->duplex = DUPLEX_FULL;
581
-
else
582
-
phydev->duplex = DUPLEX_HALF;
583
-
584
-
switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
585
-
case MDIO_AN_TX_VEND_STATUS1_10BASET:
586
-
phydev->speed = SPEED_10;
587
-
config_reg = VEND1_GLOBAL_CFG_10M;
588
-
break;
589
-
case MDIO_AN_TX_VEND_STATUS1_100BASETX:
590
-
phydev->speed = SPEED_100;
591
-
config_reg = VEND1_GLOBAL_CFG_100M;
592
-
break;
593
-
case MDIO_AN_TX_VEND_STATUS1_1000BASET:
594
-
phydev->speed = SPEED_1000;
595
-
config_reg = VEND1_GLOBAL_CFG_1G;
596
-
break;
597
-
case MDIO_AN_TX_VEND_STATUS1_2500BASET:
598
-
phydev->speed = SPEED_2500;
599
-
config_reg = VEND1_GLOBAL_CFG_2_5G;
600
-
break;
601
-
case MDIO_AN_TX_VEND_STATUS1_5000BASET:
602
-
phydev->speed = SPEED_5000;
603
-
config_reg = VEND1_GLOBAL_CFG_5G;
604
-
break;
605
-
case MDIO_AN_TX_VEND_STATUS1_10GBASET:
606
-
phydev->speed = SPEED_10000;
607
-
config_reg = VEND1_GLOBAL_CFG_10G;
608
-
break;
609
-
default:
610
-
phydev->speed = SPEED_UNKNOWN;
611
-
return 0;
612
-
}
613
-
614
-
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
615
-
if (val < 0)
616
-
return val;
617
-
618
-
if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
619
-
VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
620
-
phydev->rate_matching = RATE_MATCH_PAUSE;
621
-
else
622
-
phydev->rate_matching = RATE_MATCH_NONE;
623
-
624
-
return 0;
625
-
}
626
-
627
-
static int aqr107_read_status(struct phy_device *phydev)
628
-
{
629
-
int val, ret;
630
-
631
-
ret = aqr_read_status(phydev);
573
+
ret = aqr_gen1_read_status(phydev);
632
574
if (ret)
633
575
return ret;
634
576
635
-
if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
636
-
return 0;
577
+
for (i = 0; i < AQR_NUM_GLOBAL_CFG; i++) {
578
+
struct aqr_global_syscfg *syscfg = &priv->global_cfg[i];
637
579
638
-
/* The status register is not immediately correct on line side link up.
639
-
* Poll periodically until it reflects the correct ON state.
640
-
* Only return fail for read error, timeout defaults to OFF state.
641
-
*/
642
-
ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PHYXS,
643
-
MDIO_PHYXS_VEND_IF_STATUS, val,
644
-
(FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val) !=
645
-
MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF),
646
-
AQR107_OP_IN_PROG_SLEEP,
647
-
AQR107_OP_IN_PROG_TIMEOUT, false);
648
-
if (ret && ret != -ETIMEDOUT)
649
-
return ret;
580
+
if (syscfg->speed != phydev->speed)
581
+
continue;
650
582
651
-
switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
652
-
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
653
-
phydev->interface = PHY_INTERFACE_MODE_10GKR;
654
-
break;
655
-
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
656
-
phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
657
-
break;
658
-
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
659
-
phydev->interface = PHY_INTERFACE_MODE_10GBASER;
660
-
break;
661
-
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
662
-
phydev->interface = PHY_INTERFACE_MODE_USXGMII;
663
-
break;
664
-
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
665
-
phydev->interface = PHY_INTERFACE_MODE_XAUI;
666
-
break;
667
-
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
668
-
phydev->interface = PHY_INTERFACE_MODE_SGMII;
669
-
break;
670
-
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
671
-
phydev->interface = PHY_INTERFACE_MODE_RXAUI;
672
-
break;
673
-
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
674
-
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
675
-
break;
676
-
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF:
677
-
default:
678
-
phydev->link = false;
679
-
phydev->interface = PHY_INTERFACE_MODE_NA;
583
+
if (syscfg->rate_adapt == AQR_RATE_ADAPT_PAUSE)
584
+
phydev->rate_matching = RATE_MATCH_PAUSE;
585
+
else
586
+
phydev->rate_matching = RATE_MATCH_NONE;
680
587
break;
681
588
}
682
589
683
-
/* Read possibly downshifted rate from vendor register */
684
-
return aqr107_read_rate(phydev);
590
+
return 0;
685
591
}
686
592
687
593
static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
···
720
810
mdi_conf | PMAPMD_RSVD_VEND_PROV_MDI_FORCE);
721
811
}
722
812
723
-
static int aqr107_config_init(struct phy_device *phydev)
813
+
static int aqr_gen1_config_init(struct phy_device *phydev)
724
814
{
725
815
struct aqr107_priv *priv = phydev->priv;
726
816
u32 led_idx;
···
769
859
return 0;
770
860
}
771
861
772
-
static int aqcs109_config_init(struct phy_device *phydev)
862
+
/* Walk the media-speed configuration registers to determine which
863
+
* host-side serdes modes may be used by the PHY depending on the
864
+
* negotiated media speed.
865
+
*/
866
+
static int aqr_gen2_read_global_syscfg(struct phy_device *phydev)
867
+
{
868
+
struct aqr107_priv *priv = phydev->priv;
869
+
unsigned int serdes_mode, rate_adapt;
870
+
phy_interface_t interface;
871
+
int i, val;
872
+
873
+
for (i = 0; i < AQR_NUM_GLOBAL_CFG; i++) {
874
+
struct aqr_global_syscfg *syscfg = &priv->global_cfg[i];
875
+
876
+
syscfg->speed = aqr_global_cfg_regs[i].speed;
877
+
878
+
val = phy_read_mmd(phydev, MDIO_MMD_VEND1,
879
+
aqr_global_cfg_regs[i].reg);
880
+
if (val < 0)
881
+
return val;
882
+
883
+
serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val);
884
+
rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val);
885
+
886
+
switch (serdes_mode) {
887
+
case VEND1_GLOBAL_CFG_SERDES_MODE_XFI:
888
+
if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX)
889
+
interface = PHY_INTERFACE_MODE_USXGMII;
890
+
else
891
+
interface = PHY_INTERFACE_MODE_10GBASER;
892
+
break;
893
+
894
+
case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G:
895
+
interface = PHY_INTERFACE_MODE_5GBASER;
896
+
break;
897
+
898
+
case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII:
899
+
interface = PHY_INTERFACE_MODE_2500BASEX;
900
+
break;
901
+
902
+
case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII:
903
+
interface = PHY_INTERFACE_MODE_SGMII;
904
+
break;
905
+
906
+
default:
907
+
phydev_warn(phydev, "unrecognised serdes mode %u\n",
908
+
serdes_mode);
909
+
interface = PHY_INTERFACE_MODE_NA;
910
+
break;
911
+
}
912
+
913
+
syscfg->interface = interface;
914
+
915
+
switch (rate_adapt) {
916
+
case VEND1_GLOBAL_CFG_RATE_ADAPT_NONE:
917
+
syscfg->rate_adapt = AQR_RATE_ADAPT_NONE;
918
+
break;
919
+
case VEND1_GLOBAL_CFG_RATE_ADAPT_USX:
920
+
syscfg->rate_adapt = AQR_RATE_ADAPT_USX;
921
+
break;
922
+
case VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE:
923
+
syscfg->rate_adapt = AQR_RATE_ADAPT_PAUSE;
924
+
break;
925
+
default:
926
+
phydev_warn(phydev, "unrecognized rate adapt mode %u\n",
927
+
rate_adapt);
928
+
break;
929
+
}
930
+
}
931
+
932
+
return 0;
933
+
}
934
+
935
+
static int aqr_gen2_fill_interface_modes(struct phy_device *phydev)
936
+
{
937
+
unsigned long *possible = phydev->possible_interfaces;
938
+
struct aqr107_priv *priv = phydev->priv;
939
+
phy_interface_t interface;
940
+
int i, val, ret;
941
+
942
+
/* It's been observed on some models that - when coming out of suspend
943
+
* - the FW signals that the PHY is ready but the GLOBAL_CFG registers
944
+
* continue on returning zeroes for some time. Let's poll the 100M
945
+
* register until it returns a real value as both 113c and 115c support
946
+
* this mode.
947
+
*/
948
+
if (priv->wait_on_global_cfg) {
949
+
ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
950
+
VEND1_GLOBAL_CFG_100M, val,
951
+
val != 0, 1000, 100000, false);
952
+
if (ret)
953
+
return ret;
954
+
}
955
+
956
+
ret = aqr_gen2_read_global_syscfg(phydev);
957
+
if (ret)
958
+
return ret;
959
+
960
+
for (i = 0; i < AQR_NUM_GLOBAL_CFG; i++) {
961
+
interface = priv->global_cfg[i].interface;
962
+
if (interface != PHY_INTERFACE_MODE_NA)
963
+
__set_bit(interface, possible);
964
+
}
965
+
966
+
return 0;
967
+
}
968
+
969
+
static int aqr_gen2_config_init(struct phy_device *phydev)
773
970
{
774
971
int ret;
775
972
973
+
ret = aqr_gen1_config_init(phydev);
974
+
if (ret)
975
+
return ret;
976
+
977
+
return aqr_gen2_fill_interface_modes(phydev);
978
+
}
979
+
980
+
static int aqr_gen3_config_init(struct phy_device *phydev)
981
+
{
982
+
return aqr_gen2_config_init(phydev);
983
+
}
984
+
985
+
static int aqcs109_config_init(struct phy_device *phydev)
986
+
{
776
987
/* Check that the PHY interface type is compatible */
777
988
if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
778
989
phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
779
990
return -ENODEV;
780
991
781
-
ret = aqr_wait_reset_complete(phydev);
782
-
if (!ret)
783
-
aqr107_chip_info(phydev);
784
-
785
-
return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
992
+
return aqr_gen2_config_init(phydev);
786
993
}
787
994
788
995
static void aqr107_link_change_notify(struct phy_device *phydev)
···
947
920
phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
948
921
}
949
922
950
-
static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
923
+
static int aqr_gen1_wait_processor_intensive_op(struct phy_device *phydev)
951
924
{
952
925
int val, err;
953
926
···
971
944
return 0;
972
945
}
973
946
974
-
static int aqr107_get_rate_matching(struct phy_device *phydev,
975
-
phy_interface_t iface)
947
+
static int aqr_gen2_get_rate_matching(struct phy_device *phydev,
948
+
phy_interface_t iface)
976
949
{
977
950
if (iface == PHY_INTERFACE_MODE_10GBASER ||
978
-
iface == PHY_INTERFACE_MODE_2500BASEX ||
979
-
iface == PHY_INTERFACE_MODE_NA)
951
+
iface == PHY_INTERFACE_MODE_2500BASEX)
980
952
return RATE_MATCH_PAUSE;
981
953
return RATE_MATCH_NONE;
982
954
}
983
955
984
-
static int aqr107_suspend(struct phy_device *phydev)
956
+
static int aqr_gen1_suspend(struct phy_device *phydev)
985
957
{
986
958
int err;
987
959
···
989
963
if (err)
990
964
return err;
991
965
992
-
return aqr107_wait_processor_intensive_op(phydev);
966
+
return aqr_gen1_wait_processor_intensive_op(phydev);
993
967
}
994
968
995
-
static int aqr107_resume(struct phy_device *phydev)
969
+
static int aqr_gen1_resume(struct phy_device *phydev)
996
970
{
997
971
int err;
998
972
···
1001
975
if (err)
1002
976
return err;
1003
977
1004
-
return aqr107_wait_processor_intensive_op(phydev);
1005
-
}
1006
-
1007
-
static const u16 aqr_global_cfg_regs[] = {
1008
-
VEND1_GLOBAL_CFG_10M,
1009
-
VEND1_GLOBAL_CFG_100M,
1010
-
VEND1_GLOBAL_CFG_1G,
1011
-
VEND1_GLOBAL_CFG_2_5G,
1012
-
VEND1_GLOBAL_CFG_5G,
1013
-
VEND1_GLOBAL_CFG_10G
1014
-
};
1015
-
1016
-
static int aqr107_fill_interface_modes(struct phy_device *phydev)
1017
-
{
1018
-
unsigned long *possible = phydev->possible_interfaces;
1019
-
unsigned int serdes_mode, rate_adapt;
1020
-
phy_interface_t interface;
1021
-
int i, val;
1022
-
1023
-
/* Walk the media-speed configuration registers to determine which
1024
-
* host-side serdes modes may be used by the PHY depending on the
1025
-
* negotiated media speed.
1026
-
*/
1027
-
for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) {
1028
-
val = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1029
-
aqr_global_cfg_regs[i]);
1030
-
if (val < 0)
1031
-
return val;
1032
-
1033
-
serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val);
1034
-
rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val);
1035
-
1036
-
switch (serdes_mode) {
1037
-
case VEND1_GLOBAL_CFG_SERDES_MODE_XFI:
1038
-
if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX)
1039
-
interface = PHY_INTERFACE_MODE_USXGMII;
1040
-
else
1041
-
interface = PHY_INTERFACE_MODE_10GBASER;
1042
-
break;
1043
-
1044
-
case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G:
1045
-
interface = PHY_INTERFACE_MODE_5GBASER;
1046
-
break;
1047
-
1048
-
case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII:
1049
-
interface = PHY_INTERFACE_MODE_2500BASEX;
1050
-
break;
1051
-
1052
-
case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII:
1053
-
interface = PHY_INTERFACE_MODE_SGMII;
1054
-
break;
1055
-
1056
-
default:
1057
-
phydev_warn(phydev, "unrecognised serdes mode %u\n",
1058
-
serdes_mode);
1059
-
interface = PHY_INTERFACE_MODE_NA;
1060
-
break;
1061
-
}
1062
-
1063
-
if (interface != PHY_INTERFACE_MODE_NA)
1064
-
__set_bit(interface, possible);
1065
-
}
1066
-
1067
-
return 0;
1068
-
}
1069
-
1070
-
static int aqr113c_fill_interface_modes(struct phy_device *phydev)
1071
-
{
1072
-
int val, ret;
1073
-
1074
-
/* It's been observed on some models that - when coming out of suspend
1075
-
* - the FW signals that the PHY is ready but the GLOBAL_CFG registers
1076
-
* continue on returning zeroes for some time. Let's poll the 100M
1077
-
* register until it returns a real value as both 113c and 115c support
1078
-
* this mode.
1079
-
*/
1080
-
ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
1081
-
VEND1_GLOBAL_CFG_100M, val, val != 0,
1082
-
1000, 100000, false);
1083
-
if (ret)
1084
-
return ret;
1085
-
1086
-
return aqr107_fill_interface_modes(phydev);
978
+
return aqr_gen1_wait_processor_intensive_op(phydev);
1087
979
}
1088
980
1089
981
static int aqr115c_get_features(struct phy_device *phydev)
···
1029
1085
return 0;
1030
1086
}
1031
1087
1032
-
static int aqr113c_config_init(struct phy_device *phydev)
1088
+
static int aqr_gen4_config_init(struct phy_device *phydev)
1033
1089
{
1090
+
struct aqr107_priv *priv = phydev->priv;
1034
1091
int ret;
1035
1092
1036
-
ret = aqr107_config_init(phydev);
1093
+
priv->wait_on_global_cfg = true;
1094
+
1095
+
ret = aqr_gen3_config_init(phydev);
1037
1096
if (ret < 0)
1038
1097
return ret;
1039
1098
···
1045
1098
if (ret)
1046
1099
return ret;
1047
1100
1048
-
ret = aqr107_wait_processor_intensive_op(phydev);
1049
-
if (ret)
1050
-
return ret;
1051
-
1052
-
return aqr113c_fill_interface_modes(phydev);
1101
+
return aqr_gen1_wait_processor_intensive_op(phydev);
1053
1102
}
1054
1103
1055
1104
static int aqr107_probe(struct phy_device *phydev)
···
1087
1144
.name = "Aquantia AQR105",
1088
1145
.get_features = aqr105_get_features,
1089
1146
.probe = aqr107_probe,
1090
-
.config_init = aqr107_config_init,
1147
+
.config_init = aqr_gen1_config_init,
1091
1148
.config_aneg = aqr105_config_aneg,
1092
1149
.config_intr = aqr_config_intr,
1093
1150
.handle_interrupt = aqr_handle_interrupt,
1094
-
.read_status = aqr105_read_status,
1095
-
.suspend = aqr107_suspend,
1096
-
.resume = aqr107_resume,
1151
+
.read_status = aqr_gen1_read_status,
1152
+
.suspend = aqr_gen1_suspend,
1153
+
.resume = aqr_gen1_resume,
1097
1154
},
1098
1155
{
1099
1156
PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
···
1107
1164
PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
1108
1165
.name = "Aquantia AQR107",
1109
1166
.probe = aqr107_probe,
1110
-
.get_rate_matching = aqr107_get_rate_matching,
1111
-
.config_init = aqr107_config_init,
1167
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1168
+
.config_init = aqr_gen2_config_init,
1112
1169
.config_aneg = aqr_config_aneg,
1113
1170
.config_intr = aqr_config_intr,
1114
1171
.handle_interrupt = aqr_handle_interrupt,
1115
-
.read_status = aqr107_read_status,
1172
+
.read_status = aqr_gen2_read_status,
1116
1173
.get_tunable = aqr107_get_tunable,
1117
1174
.set_tunable = aqr107_set_tunable,
1118
-
.suspend = aqr107_suspend,
1119
-
.resume = aqr107_resume,
1175
+
.suspend = aqr_gen1_suspend,
1176
+
.resume = aqr_gen1_resume,
1120
1177
.get_sset_count = aqr107_get_sset_count,
1121
1178
.get_strings = aqr107_get_strings,
1122
1179
.get_stats = aqr107_get_stats,
···
1131
1188
PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
1132
1189
.name = "Aquantia AQCS109",
1133
1190
.probe = aqr107_probe,
1134
-
.get_rate_matching = aqr107_get_rate_matching,
1191
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1135
1192
.config_init = aqcs109_config_init,
1136
1193
.config_aneg = aqr_config_aneg,
1137
1194
.config_intr = aqr_config_intr,
1138
1195
.handle_interrupt = aqr_handle_interrupt,
1139
-
.read_status = aqr107_read_status,
1196
+
.read_status = aqr_gen2_read_status,
1140
1197
.get_tunable = aqr107_get_tunable,
1141
1198
.set_tunable = aqr107_set_tunable,
1142
-
.suspend = aqr107_suspend,
1143
-
.resume = aqr107_resume,
1199
+
.suspend = aqr_gen1_suspend,
1200
+
.resume = aqr_gen1_resume,
1144
1201
.get_sset_count = aqr107_get_sset_count,
1145
1202
.get_strings = aqr107_get_strings,
1146
1203
.get_stats = aqr107_get_stats,
···
1156
1213
PHY_ID_MATCH_MODEL(PHY_ID_AQR111),
1157
1214
.name = "Aquantia AQR111",
1158
1215
.probe = aqr107_probe,
1159
-
.get_rate_matching = aqr107_get_rate_matching,
1160
-
.config_init = aqr107_config_init,
1216
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1217
+
.config_init = aqr_gen3_config_init,
1161
1218
.config_aneg = aqr_config_aneg,
1162
1219
.config_intr = aqr_config_intr,
1163
1220
.handle_interrupt = aqr_handle_interrupt,
1164
-
.read_status = aqr107_read_status,
1221
+
.read_status = aqr_gen2_read_status,
1165
1222
.get_tunable = aqr107_get_tunable,
1166
1223
.set_tunable = aqr107_set_tunable,
1167
-
.suspend = aqr107_suspend,
1168
-
.resume = aqr107_resume,
1224
+
.suspend = aqr_gen1_suspend,
1225
+
.resume = aqr_gen1_resume,
1169
1226
.get_sset_count = aqr107_get_sset_count,
1170
1227
.get_strings = aqr107_get_strings,
1171
1228
.get_stats = aqr107_get_stats,
···
1181
1238
PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0),
1182
1239
.name = "Aquantia AQR111B0",
1183
1240
.probe = aqr107_probe,
1184
-
.get_rate_matching = aqr107_get_rate_matching,
1185
-
.config_init = aqr107_config_init,
1241
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1242
+
.config_init = aqr_gen3_config_init,
1186
1243
.config_aneg = aqr_config_aneg,
1187
1244
.config_intr = aqr_config_intr,
1188
1245
.handle_interrupt = aqr_handle_interrupt,
1189
-
.read_status = aqr107_read_status,
1246
+
.read_status = aqr_gen2_read_status,
1190
1247
.get_tunable = aqr107_get_tunable,
1191
1248
.set_tunable = aqr107_set_tunable,
1192
-
.suspend = aqr107_suspend,
1193
-
.resume = aqr107_resume,
1249
+
.suspend = aqr_gen1_suspend,
1250
+
.resume = aqr_gen1_resume,
1194
1251
.get_sset_count = aqr107_get_sset_count,
1195
1252
.get_strings = aqr107_get_strings,
1196
1253
.get_stats = aqr107_get_stats,
···
1214
1271
PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
1215
1272
.name = "Aquantia AQR112",
1216
1273
.probe = aqr107_probe,
1274
+
.config_init = aqr_gen3_config_init,
1217
1275
.config_aneg = aqr_config_aneg,
1218
1276
.config_intr = aqr_config_intr,
1219
1277
.handle_interrupt = aqr_handle_interrupt,
1220
1278
.get_tunable = aqr107_get_tunable,
1221
1279
.set_tunable = aqr107_set_tunable,
1222
-
.suspend = aqr107_suspend,
1223
-
.resume = aqr107_resume,
1224
-
.read_status = aqr107_read_status,
1225
-
.get_rate_matching = aqr107_get_rate_matching,
1280
+
.suspend = aqr_gen1_suspend,
1281
+
.resume = aqr_gen1_resume,
1282
+
.read_status = aqr_gen2_read_status,
1283
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1226
1284
.get_sset_count = aqr107_get_sset_count,
1227
1285
.get_strings = aqr107_get_strings,
1228
1286
.get_stats = aqr107_get_stats,
···
1238
1294
PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
1239
1295
.name = "Aquantia AQR412",
1240
1296
.probe = aqr107_probe,
1297
+
.config_init = aqr_gen3_config_init,
1241
1298
.config_aneg = aqr_config_aneg,
1242
1299
.config_intr = aqr_config_intr,
1243
1300
.handle_interrupt = aqr_handle_interrupt,
1244
1301
.get_tunable = aqr107_get_tunable,
1245
1302
.set_tunable = aqr107_set_tunable,
1246
-
.suspend = aqr107_suspend,
1247
-
.resume = aqr107_resume,
1248
-
.read_status = aqr107_read_status,
1249
-
.get_rate_matching = aqr107_get_rate_matching,
1303
+
.suspend = aqr_gen1_suspend,
1304
+
.resume = aqr_gen1_resume,
1305
+
.read_status = aqr_gen2_read_status,
1306
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1307
+
.get_sset_count = aqr107_get_sset_count,
1308
+
.get_strings = aqr107_get_strings,
1309
+
.get_stats = aqr107_get_stats,
1310
+
.link_change_notify = aqr107_link_change_notify,
1311
+
},
1312
+
{
1313
+
PHY_ID_MATCH_MODEL(PHY_ID_AQR412C),
1314
+
.name = "Aquantia AQR412C",
1315
+
.probe = aqr107_probe,
1316
+
.config_init = aqr_gen3_config_init,
1317
+
.config_aneg = aqr_config_aneg,
1318
+
.config_intr = aqr_config_intr,
1319
+
.handle_interrupt = aqr_handle_interrupt,
1320
+
.get_tunable = aqr107_get_tunable,
1321
+
.set_tunable = aqr107_set_tunable,
1322
+
.suspend = aqr_gen1_suspend,
1323
+
.resume = aqr_gen1_resume,
1324
+
.read_status = aqr_gen2_read_status,
1325
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1250
1326
.get_sset_count = aqr107_get_sset_count,
1251
1327
.get_strings = aqr107_get_strings,
1252
1328
.get_stats = aqr107_get_stats,
···
1276
1312
PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
1277
1313
.name = "Aquantia AQR113",
1278
1314
.probe = aqr107_probe,
1279
-
.get_rate_matching = aqr107_get_rate_matching,
1280
-
.config_init = aqr113c_config_init,
1315
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1316
+
.config_init = aqr_gen4_config_init,
1281
1317
.config_aneg = aqr_config_aneg,
1282
1318
.config_intr = aqr_config_intr,
1283
1319
.handle_interrupt = aqr_handle_interrupt,
1284
-
.read_status = aqr107_read_status,
1320
+
.read_status = aqr_gen2_read_status,
1285
1321
.get_tunable = aqr107_get_tunable,
1286
1322
.set_tunable = aqr107_set_tunable,
1287
-
.suspend = aqr107_suspend,
1288
-
.resume = aqr107_resume,
1323
+
.suspend = aqr_gen1_suspend,
1324
+
.resume = aqr_gen1_resume,
1289
1325
.get_sset_count = aqr107_get_sset_count,
1290
1326
.get_strings = aqr107_get_strings,
1291
1327
.get_stats = aqr107_get_stats,
···
1300
1336
PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
1301
1337
.name = "Aquantia AQR113C",
1302
1338
.probe = aqr107_probe,
1303
-
.get_rate_matching = aqr107_get_rate_matching,
1304
-
.config_init = aqr113c_config_init,
1339
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1340
+
.config_init = aqr_gen4_config_init,
1305
1341
.config_aneg = aqr_config_aneg,
1306
1342
.config_intr = aqr_config_intr,
1307
1343
.handle_interrupt = aqr_handle_interrupt,
1308
-
.read_status = aqr107_read_status,
1344
+
.read_status = aqr_gen2_read_status,
1309
1345
.get_tunable = aqr107_get_tunable,
1310
1346
.set_tunable = aqr107_set_tunable,
1311
-
.suspend = aqr107_suspend,
1312
-
.resume = aqr107_resume,
1347
+
.suspend = aqr_gen1_suspend,
1348
+
.resume = aqr_gen1_resume,
1313
1349
.get_sset_count = aqr107_get_sset_count,
1314
1350
.get_strings = aqr107_get_strings,
1315
1351
.get_stats = aqr107_get_stats,
···
1324
1360
PHY_ID_MATCH_MODEL(PHY_ID_AQR114C),
1325
1361
.name = "Aquantia AQR114C",
1326
1362
.probe = aqr107_probe,
1327
-
.get_rate_matching = aqr107_get_rate_matching,
1328
-
.config_init = aqr107_config_init,
1363
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1364
+
.config_init = aqr_gen4_config_init,
1329
1365
.config_aneg = aqr_config_aneg,
1330
1366
.config_intr = aqr_config_intr,
1331
1367
.handle_interrupt = aqr_handle_interrupt,
1332
-
.read_status = aqr107_read_status,
1368
+
.read_status = aqr_gen2_read_status,
1333
1369
.get_tunable = aqr107_get_tunable,
1334
1370
.set_tunable = aqr107_set_tunable,
1335
-
.suspend = aqr107_suspend,
1336
-
.resume = aqr107_resume,
1371
+
.suspend = aqr_gen1_suspend,
1372
+
.resume = aqr_gen1_resume,
1337
1373
.get_sset_count = aqr107_get_sset_count,
1338
1374
.get_strings = aqr107_get_strings,
1339
1375
.get_stats = aqr107_get_stats,
···
1346
1382
.led_polarity_set = aqr_phy_led_polarity_set,
1347
1383
},
1348
1384
{
1385
+
PHY_ID_MATCH_MODEL(PHY_ID_AQR115),
1386
+
.name = "Aquantia AQR115",
1387
+
.probe = aqr107_probe,
1388
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1389
+
.config_init = aqr_gen4_config_init,
1390
+
.config_aneg = aqr_config_aneg,
1391
+
.config_intr = aqr_config_intr,
1392
+
.handle_interrupt = aqr_handle_interrupt,
1393
+
.read_status = aqr_gen2_read_status,
1394
+
.get_tunable = aqr107_get_tunable,
1395
+
.set_tunable = aqr107_set_tunable,
1396
+
.suspend = aqr_gen1_suspend,
1397
+
.resume = aqr_gen1_resume,
1398
+
.get_sset_count = aqr107_get_sset_count,
1399
+
.get_strings = aqr107_get_strings,
1400
+
.get_stats = aqr107_get_stats,
1401
+
.get_features = aqr115c_get_features,
1402
+
.link_change_notify = aqr107_link_change_notify,
1403
+
.led_brightness_set = aqr_phy_led_brightness_set,
1404
+
.led_hw_is_supported = aqr_phy_led_hw_is_supported,
1405
+
.led_hw_control_set = aqr_phy_led_hw_control_set,
1406
+
.led_hw_control_get = aqr_phy_led_hw_control_get,
1407
+
.led_polarity_set = aqr_phy_led_polarity_set,
1408
+
},
1409
+
{
1349
1410
PHY_ID_MATCH_MODEL(PHY_ID_AQR115C),
1350
1411
.name = "Aquantia AQR115C",
1351
1412
.probe = aqr107_probe,
1352
-
.get_rate_matching = aqr107_get_rate_matching,
1353
-
.config_init = aqr113c_config_init,
1413
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1414
+
.config_init = aqr_gen4_config_init,
1354
1415
.config_aneg = aqr_config_aneg,
1355
1416
.config_intr = aqr_config_intr,
1356
1417
.handle_interrupt = aqr_handle_interrupt,
1357
-
.read_status = aqr107_read_status,
1418
+
.read_status = aqr_gen2_read_status,
1358
1419
.get_tunable = aqr107_get_tunable,
1359
1420
.set_tunable = aqr107_set_tunable,
1360
-
.suspend = aqr107_suspend,
1361
-
.resume = aqr107_resume,
1421
+
.suspend = aqr_gen1_suspend,
1422
+
.resume = aqr_gen1_resume,
1362
1423
.get_sset_count = aqr107_get_sset_count,
1363
1424
.get_strings = aqr107_get_strings,
1364
1425
.get_stats = aqr107_get_stats,
···
1399
1410
PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
1400
1411
.name = "Aquantia AQR813",
1401
1412
.probe = aqr107_probe,
1402
-
.get_rate_matching = aqr107_get_rate_matching,
1403
-
.config_init = aqr107_config_init,
1413
+
.get_rate_matching = aqr_gen2_get_rate_matching,
1414
+
.config_init = aqr_gen4_config_init,
1404
1415
.config_aneg = aqr_config_aneg,
1405
1416
.config_intr = aqr_config_intr,
1406
1417
.handle_interrupt = aqr_handle_interrupt,
1407
-
.read_status = aqr107_read_status,
1418
+
.read_status = aqr_gen2_read_status,
1408
1419
.get_tunable = aqr107_get_tunable,
1409
1420
.set_tunable = aqr107_set_tunable,
1410
-
.suspend = aqr107_suspend,
1411
-
.resume = aqr107_resume,
1421
+
.suspend = aqr_gen1_suspend,
1422
+
.resume = aqr_gen1_resume,
1412
1423
.get_sset_count = aqr107_get_sset_count,
1413
1424
.get_strings = aqr107_get_strings,
1414
1425
.get_stats = aqr107_get_stats,
···
1435
1446
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
1436
1447
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
1437
1448
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
1449
+
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412C) },
1438
1450
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
1439
1451
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
1440
1452
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) },
1453
+
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR115) },
1441
1454
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) },
1442
1455
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
1443
1456
{ }