Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'perf-urgent-2022-08-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 perf fixes from Ingo Molnar:
"Misc fixes: an Arch-LBR fix, a PEBS enumeration fix, an Intel DS fix,
PEBS constraints fix on Alder Lake CPUs and an Intel uncore PMU fix"
* tag 'perf-urgent-2022-08-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/intel/uncore: Fix broken read_counter() for SNB IMC PMU
perf/x86/intel: Fix pebs event constraints for ADL
perf/x86/intel/ds: Fix precise store latency handling
perf/x86/core: Set pebs_capable and PMU_FL_PEBS_ALL for the Baseline
perf/x86/lbr: Enable the branch type for the Arch LBR by default
+36
-7
-4
arch/x86/events/intel/core.c
-4
arch/x86/events/intel/core.c
···
6291
6291
x86_pmu.pebs_aliases = NULL;
6292
6292
x86_pmu.pebs_prec_dist = true;
6293
6293
x86_pmu.pebs_block = true;
6294
-
x86_pmu.pebs_capable = ~0ULL;
6295
6294
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6296
6295
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6297
-
x86_pmu.flags |= PMU_FL_PEBS_ALL;
6298
6296
x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6299
6297
x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6300
6298
···
6335
6337
x86_pmu.pebs_aliases = NULL;
6336
6338
x86_pmu.pebs_prec_dist = true;
6337
6339
x86_pmu.pebs_block = true;
6338
-
x86_pmu.pebs_capable = ~0ULL;
6339
6340
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6340
6341
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6341
-
x86_pmu.flags |= PMU_FL_PEBS_ALL;
6342
6342
x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6343
6343
x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6344
6344
x86_pmu.lbr_pt_coexist = true;
+11
-2
arch/x86/events/intel/ds.c
+11
-2
arch/x86/events/intel/ds.c
···
291
291
static u64 store_latency_data(struct perf_event *event, u64 status)
292
292
{
293
293
union intel_x86_pebs_dse dse;
294
+
union perf_mem_data_src src;
294
295
u64 val;
295
296
296
297
dse.val = status;
···
305
304
306
305
val |= P(BLK, NA);
307
306
308
-
return val;
307
+
/*
308
+
* the pebs_data_source table is only for loads
309
+
* so override the mem_op to say STORE instead
310
+
*/
311
+
src.val = val;
312
+
src.mem_op = P(OP,STORE);
313
+
314
+
return src.val;
309
315
}
310
316
311
317
struct pebs_record_core {
···
830
822
831
823
struct event_constraint intel_grt_pebs_event_constraints[] = {
832
824
/* Allow all events as PEBS with no flags */
833
-
INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xf),
825
+
INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
834
826
INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf),
835
827
EVENT_CONSTRAINT_END
836
828
};
···
2270
2262
PERF_SAMPLE_BRANCH_STACK |
2271
2263
PERF_SAMPLE_TIME;
2272
2264
x86_pmu.flags |= PMU_FL_PEBS_ALL;
2265
+
x86_pmu.pebs_capable = ~0ULL;
2273
2266
pebs_qual = "-baseline";
2274
2267
x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
2275
2268
} else {
+8
arch/x86/events/intel/lbr.c
+8
arch/x86/events/intel/lbr.c
···
1097
1097
1098
1098
if (static_cpu_has(X86_FEATURE_ARCH_LBR)) {
1099
1099
reg->config = mask;
1100
+
1101
+
/*
1102
+
* The Arch LBR HW can retrieve the common branch types
1103
+
* from the LBR_INFO. It doesn't require the high overhead
1104
+
* SW disassemble.
1105
+
* Enable the branch type by default for the Arch LBR.
1106
+
*/
1107
+
reg->reg |= X86_BR_TYPE_SAVE;
1100
1108
return 0;
1101
1109
}
1102
1110
+17
-1
arch/x86/events/intel/uncore_snb.c
+17
-1
arch/x86/events/intel/uncore_snb.c
···
841
841
return 0;
842
842
}
843
843
844
+
static u64 snb_uncore_imc_read_counter(struct intel_uncore_box *box, struct perf_event *event)
845
+
{
846
+
struct hw_perf_event *hwc = &event->hw;
847
+
848
+
/*
849
+
* SNB IMC counters are 32-bit and are laid out back to back
850
+
* in MMIO space. Therefore we must use a 32-bit accessor function
851
+
* using readq() from uncore_mmio_read_counter() causes problems
852
+
* because it is reading 64-bit at a time. This is okay for the
853
+
* uncore_perf_event_update() function because it drops the upper
854
+
* 32-bits but not okay for plain uncore_read_counter() as invoked
855
+
* in uncore_pmu_event_start().
856
+
*/
857
+
return (u64)readl(box->io_addr + hwc->event_base);
858
+
}
859
+
844
860
static struct pmu snb_uncore_imc_pmu = {
845
861
.task_ctx_nr = perf_invalid_context,
846
862
.event_init = snb_uncore_imc_event_init,
···
876
860
.disable_event = snb_uncore_imc_disable_event,
877
861
.enable_event = snb_uncore_imc_enable_event,
878
862
.hw_config = snb_uncore_imc_hw_config,
879
-
.read_counter = uncore_mmio_read_counter,
863
+
.read_counter = snb_uncore_imc_read_counter,
880
864
};
881
865
882
866
static struct intel_uncore_type snb_uncore_imc = {