Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue
Tony Nguyen says:
====================
Intel Wired LAN Driver Updates 2025-01-07 (ice, igc)
For ice:
Arkadiusz corrects mask value being used to determine DPLL phase range.
Przemyslaw corrects frequency value for E823 devices.
For igc:
En-Wei Wu adds a check and, early, return for failed register read.
* '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue:
igc: return early when failing to read EECD register
ice: fix incorrect PHY settings for 100 GB/s
ice: fix max values for dpll pin phase adjust
====================
Link: https://patch.msgid.link/20250107190150.1758577-1-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+33
-14
+2
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
+2
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
+23
-12
drivers/net/ethernet/intel/ice/ice_dpll.c
+23
-12
drivers/net/ethernet/intel/ice/ice_dpll.c
···
2065
2065
}
2066
2066
2067
2067
/**
2068
+
* ice_dpll_phase_range_set - initialize phase adjust range helper
2069
+
* @range: pointer to phase adjust range struct to be initialized
2070
+
* @phase_adj: a value to be used as min(-)/max(+) boundary
2071
+
*/
2072
+
static void ice_dpll_phase_range_set(struct dpll_pin_phase_adjust_range *range,
2073
+
u32 phase_adj)
2074
+
{
2075
+
range->min = -phase_adj;
2076
+
range->max = phase_adj;
2077
+
}
2078
+
2079
+
/**
2068
2080
* ice_dpll_init_info_pins_generic - initializes generic pins info
2069
2081
* @pf: board private structure
2070
2082
* @input: if input pins initialized
···
2117
2105
for (i = 0; i < pin_num; i++) {
2118
2106
pins[i].idx = i;
2119
2107
pins[i].prop.board_label = labels[i];
2120
-
pins[i].prop.phase_range.min = phase_adj_max;
2121
-
pins[i].prop.phase_range.max = -phase_adj_max;
2108
+
ice_dpll_phase_range_set(&pins[i].prop.phase_range,
2109
+
phase_adj_max);
2122
2110
pins[i].prop.capabilities = cap;
2123
2111
pins[i].pf = pf;
2124
2112
ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL);
···
2164
2152
struct ice_hw *hw = &pf->hw;
2165
2153
struct ice_dpll_pin *pins;
2166
2154
unsigned long caps;
2155
+
u32 phase_adj_max;
2167
2156
u8 freq_supp_num;
2168
2157
bool input;
2169
2158
···
2172
2159
case ICE_DPLL_PIN_TYPE_INPUT:
2173
2160
pins = pf->dplls.inputs;
2174
2161
num_pins = pf->dplls.num_inputs;
2162
+
phase_adj_max = pf->dplls.input_phase_adj_max;
2175
2163
input = true;
2176
2164
break;
2177
2165
case ICE_DPLL_PIN_TYPE_OUTPUT:
2178
2166
pins = pf->dplls.outputs;
2179
2167
num_pins = pf->dplls.num_outputs;
2168
+
phase_adj_max = pf->dplls.output_phase_adj_max;
2180
2169
input = false;
2181
2170
break;
2182
2171
default:
···
2203
2188
return ret;
2204
2189
caps |= (DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE |
2205
2190
DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE);
2206
-
pins[i].prop.phase_range.min =
2207
-
pf->dplls.input_phase_adj_max;
2208
-
pins[i].prop.phase_range.max =
2209
-
-pf->dplls.input_phase_adj_max;
2210
2191
} else {
2211
-
pins[i].prop.phase_range.min =
2212
-
pf->dplls.output_phase_adj_max;
2213
-
pins[i].prop.phase_range.max =
2214
-
-pf->dplls.output_phase_adj_max;
2215
2192
ret = ice_cgu_get_output_pin_state_caps(hw, i, &caps);
2216
2193
if (ret)
2217
2194
return ret;
2218
2195
}
2196
+
ice_dpll_phase_range_set(&pins[i].prop.phase_range,
2197
+
phase_adj_max);
2219
2198
pins[i].prop.capabilities = caps;
2220
2199
ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL);
2221
2200
if (ret)
···
2317
2308
dp->dpll_idx = abilities.pps_dpll_idx;
2318
2309
d->num_inputs = abilities.num_inputs;
2319
2310
d->num_outputs = abilities.num_outputs;
2320
-
d->input_phase_adj_max = le32_to_cpu(abilities.max_in_phase_adj);
2321
-
d->output_phase_adj_max = le32_to_cpu(abilities.max_out_phase_adj);
2311
+
d->input_phase_adj_max = le32_to_cpu(abilities.max_in_phase_adj) &
2312
+
ICE_AQC_GET_CGU_MAX_PHASE_ADJ;
2313
+
d->output_phase_adj_max = le32_to_cpu(abilities.max_out_phase_adj) &
2314
+
ICE_AQC_GET_CGU_MAX_PHASE_ADJ;
2322
2315
2323
2316
alloc_size = sizeof(*d->inputs) * d->num_inputs;
2324
2317
d->inputs = kzalloc(alloc_size, GFP_KERNEL);
+2
-2
drivers/net/ethernet/intel/ice/ice_ptp_consts.h
+2
-2
drivers/net/ethernet/intel/ice/ice_ptp_consts.h
···
761
761
/* rx_desk_rsgb_par */
762
762
644531250, /* 644.53125 MHz Reed Solomon gearbox */
763
763
/* tx_desk_rsgb_pcs */
764
-
644531250, /* 644.53125 MHz Reed Solomon gearbox */
764
+
390625000, /* 390.625 MHz Reed Solomon gearbox */
765
765
/* rx_desk_rsgb_pcs */
766
-
644531250, /* 644.53125 MHz Reed Solomon gearbox */
766
+
390625000, /* 390.625 MHz Reed Solomon gearbox */
767
767
/* tx_fixed_delay */
768
768
1620,
769
769
/* pmd_adj_divisor */
+6
drivers/net/ethernet/intel/igc/igc_base.c
+6
drivers/net/ethernet/intel/igc/igc_base.c
···
68
68
u32 eecd = rd32(IGC_EECD);
69
69
u16 size;
70
70
71
+
/* failed to read reg and got all F's */
72
+
if (!(~eecd))
73
+
return -ENXIO;
74
+
71
75
size = FIELD_GET(IGC_EECD_SIZE_EX_MASK, eecd);
72
76
73
77
/* Added to a constant, "size" becomes the left-shift value
···
225
221
226
222
/* NVM initialization */
227
223
ret_val = igc_init_nvm_params_base(hw);
224
+
if (ret_val)
225
+
goto out;
228
226
switch (hw->mac.type) {
229
227
case igc_i225:
230
228
ret_val = igc_init_nvm_params_i225(hw);