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usb: dwc2: Add hibernation updates for ULPI PHY

Added programmming of ULPI_LATCH_EN_DURING_HIB_ENTRY bit in GPWRDN
register when using ULPI PHY during entry/exit to/from hibernation.
This bit set to 1 during entering to hibernation if ULPI PHY used.
On exiting from hibernation this bit reset to 0.
Applicable for both host and device modes.

Signed-off-by: Minas Harutyunyan <Minas.Harutyunyan@synopsys.com>
Link: https://lore.kernel.org/r/e024cb39a7177ec201c873df25ca6365f2e55947.1708948356.git.Minas.Harutyunyan@synopsys.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Minas Harutyunyan and committed by
Greg Kroah-Hartman 4483ef3c 535a88dc

+43
+5
drivers/usb/dwc2/core.c
··· 249 249 dwc2_writel(hsotg, gpwrdn, GPWRDN); 250 250 udelay(10); 251 251 252 + /* Reset ULPI latch */ 253 + gpwrdn = dwc2_readl(hsotg, GPWRDN); 254 + gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY; 255 + dwc2_writel(hsotg, gpwrdn, GPWRDN); 256 + 252 257 /* Disable PMU interrupt */ 253 258 gpwrdn = dwc2_readl(hsotg, GPWRDN); 254 259 gpwrdn &= ~GPWRDN_PMUINTSEL;
+5
drivers/usb/dwc2/core_intr.c
··· 705 705 gpwrdn_tmp &= ~GPWRDN_PMUINTSEL; 706 706 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); 707 707 708 + /* Reset ULPI latch */ 709 + gpwrdn = dwc2_readl(hsotg, GPWRDN); 710 + gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY; 711 + dwc2_writel(hsotg, gpwrdn, GPWRDN); 712 + 708 713 /* De-assert Wakeup Logic */ 709 714 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); 710 715 gpwrdn_tmp &= ~GPWRDN_PMUACTV;
+23
drivers/usb/dwc2/gadget.c
··· 5309 5309 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 5310 5310 { 5311 5311 u32 gpwrdn; 5312 + u32 gusbcfg; 5313 + u32 pcgcctl; 5312 5314 int ret = 0; 5313 5315 5314 5316 /* Change to L2(suspend) state */ ··· 5330 5328 } 5331 5329 5332 5330 gpwrdn = GPWRDN_PWRDNRSTN; 5331 + udelay(10); 5332 + gusbcfg = dwc2_readl(hsotg, GUSBCFG); 5333 + if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) { 5334 + /* ULPI interface */ 5335 + gpwrdn |= GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY; 5336 + } 5337 + dwc2_writel(hsotg, gpwrdn, GPWRDN); 5338 + udelay(10); 5339 + 5340 + /* Suspend the Phy Clock */ 5341 + pcgcctl = dwc2_readl(hsotg, PCGCTL); 5342 + pcgcctl |= PCGCTL_STOPPCLK; 5343 + dwc2_writel(hsotg, pcgcctl, PCGCTL); 5344 + udelay(10); 5345 + 5346 + gpwrdn = dwc2_readl(hsotg, GPWRDN); 5333 5347 gpwrdn |= GPWRDN_PMUACTV; 5334 5348 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5335 5349 udelay(10); ··· 5445 5427 /* On USB Reset, reset device address to zero */ 5446 5428 if (reset) 5447 5429 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); 5430 + 5431 + /* Reset ULPI latch */ 5432 + gpwrdn = dwc2_readl(hsotg, GPWRDN); 5433 + gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY; 5434 + dwc2_writel(hsotg, gpwrdn, GPWRDN); 5448 5435 5449 5436 /* De-assert Wakeup Logic */ 5450 5437 gpwrdn = dwc2_readl(hsotg, GPWRDN);
+10
drivers/usb/dwc2/hcd.c
··· 5503 5503 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 5504 5504 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) { 5505 5505 /* ULPI interface */ 5506 + udelay(10); 5507 + gpwrdn = dwc2_readl(hsotg, GPWRDN); 5508 + gpwrdn |= GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY; 5509 + dwc2_writel(hsotg, gpwrdn, GPWRDN); 5510 + udelay(10); 5506 5511 /* Suspend the Phy Clock */ 5507 5512 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5508 5513 pcgcctl |= PCGCTL_STOPPCLK; ··· 5613 5608 /* Restore GUSBCFG, HCFG */ 5614 5609 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); 5615 5610 dwc2_writel(hsotg, hr->hcfg, HCFG); 5611 + 5612 + /* Reset ULPI latch */ 5613 + gpwrdn = dwc2_readl(hsotg, GPWRDN); 5614 + gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY; 5615 + dwc2_writel(hsotg, gpwrdn, GPWRDN); 5616 5616 5617 5617 /* De-assert Wakeup Logic */ 5618 5618 gpwrdn = dwc2_readl(hsotg, GPWRDN);