tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Olof Johansson:
"A set of fixes that have trickled in over the last couple of weeks:

- MAINTAINER update for Cavium/Marvell ThunderX2

- stm32 tweaks to pinmux for Joystick/Camera, and RAM allocation for
CAN interfaces

- i.MX fixes for voltage regulator GPIO mappings, fixes voltage
scaling issues

- More i.MX fixes for various issues on i.MX eval boards: interrupt
storm due to u-boot leaving pins in new states, fixing power button
config, a couple of compatible-string corrections.

- Powerdown and Suspend/Resume fixes for Allwinner A83-based tablets

- A few documentation tweaks and a fix of a memory leak in the reset
subsystem"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
MAINTAINERS: update Cavium ThunderX2 maintainers
ARM: dts: stm32: change joystick pinctrl definition on stm32mp157c-ev1
ARM: dts: stm32: remove OV5640 pinctrl definition on stm32mp157c-ev1
ARM: dts: stm32: Fix CAN RAM mapping on stm32mp157c
ARM: dts: stm32: relax qspi pins slew-rate for stm32mp157
arm64: dts: zii-ultra: fix ARM regulator GPIO handle
ARM: sunxi: Fix CPU powerdown on A83T
ARM: dts: sun8i-a83t-tbs-a711: Fix WiFi resume from suspend
arm64: dts: imx8mn: fix compatible string for sdma
arm64: dts: imx8mm: fix compatible string for sdma
reset: fix reset_control_ops kerneldoc comment
ARM: dts: imx6-logicpd: Re-enable SNVS power key
soc: imx: gpc: fix initialiser format
ARM: dts: imx6qdl-sabreauto: Fix storm of accelerometer interrupts
arm64: dts: ls1028a: fix a compatible issue
reset: fix reset_control_get_exclusive kerneldoc comment
reset: fix reset_control_lookup kerneldoc comment
reset: fix of_reset_control_get_count kerneldoc comment
reset: fix of_reset_simple_xlate kerneldoc comment
reset: Fix memory leak in reset_control_array_put()

Linus Torvalds 44866956 dd892625

+44 -32
+4
.mailmap
··· 108 108 Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com> 109 109 Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com> 110 110 <javier@osg.samsung.com> <javier.martinez@collabora.co.uk> 111 + Jayachandran C <c.jayachandran@gmail.com> <jayachandranc@netlogicmicro.com> 112 + Jayachandran C <c.jayachandran@gmail.com> <jchandra@broadcom.com> 113 + Jayachandran C <c.jayachandran@gmail.com> <jchandra@digeo.com> 114 + Jayachandran C <c.jayachandran@gmail.com> <jnair@caviumnetworks.com> 111 115 Jean Tourrilhes <jt@hpl.hp.com> 112 116 <jean-philippe@linaro.org> <jean-philippe.brucker@arm.com> 113 117 Jeff Garzik <jgarzik@pretzel.yyz.us>
-1
MAINTAINERS
··· 3738 3738 3739 3739 CAVIUM THUNDERX2 ARM64 SOC 3740 3740 M: Robert Richter <rrichter@cavium.com> 3741 - M: Jayachandran C <jnair@caviumnetworks.com> 3742 3741 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 3743 3742 S: Maintained 3744 3743 F: arch/arm64/boot/dts/cavium/thunder2-99xx*
+4
arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
··· 328 328 pinctrl-0 = <&pinctrl_pwm3>; 329 329 }; 330 330 331 + &snvs_pwrkey { 332 + status = "okay"; 333 + }; 334 + 331 335 &ssi2 { 332 336 status = "okay"; 333 337 };
+8
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
··· 230 230 accelerometer@1c { 231 231 compatible = "fsl,mma8451"; 232 232 reg = <0x1c>; 233 + pinctrl-names = "default"; 234 + pinctrl-0 = <&pinctrl_mma8451_int>; 233 235 interrupt-parent = <&gpio6>; 234 236 interrupts = <31 IRQ_TYPE_LEVEL_LOW>; 235 237 }; ··· 627 625 pinctrl_max7310: max7310grp { 628 626 fsl,pins = < 629 627 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 628 + >; 629 + }; 630 + 631 + pinctrl_mma8451_int: mma8451intgrp { 632 + fsl,pins = < 633 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 630 634 >; 631 635 }; 632 636
+2 -11
arch/arm/boot/dts/stm32mp157c-ev1.dts
··· 183 183 184 184 ov5640: camera@3c { 185 185 compatible = "ovti,ov5640"; 186 - pinctrl-names = "default"; 187 - pinctrl-0 = <&ov5640_pins>; 188 186 reg = <0x3c>; 189 187 clocks = <&clk_ext_camera>; 190 188 clock-names = "xclk"; 191 189 DOVDD-supply = <&v2v8>; 192 - powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>; 193 - reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>; 190 + powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; 191 + reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; 194 192 rotation = <180>; 195 193 status = "okay"; 196 194 ··· 221 223 222 224 joystick_pins: joystick { 223 225 pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; 224 - drive-push-pull; 225 226 bias-pull-down; 226 - }; 227 - 228 - ov5640_pins: camera { 229 - pins = "agpio2", "agpio3"; /* stmfx pins 18 & 19 */ 230 - drive-push-pull; 231 - output-low; 232 227 }; 233 228 }; 234 229 };
+2 -2
arch/arm/boot/dts/stm32mp157c.dtsi
··· 932 932 interrupt-names = "int0", "int1"; 933 933 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; 934 934 clock-names = "hclk", "cclk"; 935 - bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; 935 + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; 936 936 status = "disabled"; 937 937 }; 938 938 ··· 945 945 interrupt-names = "int0", "int1"; 946 946 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; 947 947 clock-names = "hclk", "cclk"; 948 - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; 948 + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; 949 949 status = "disabled"; 950 950 }; 951 951
+1
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
··· 192 192 vqmmc-supply = <&reg_dldo1>; 193 193 non-removable; 194 194 wakeup-source; 195 + keep-power-in-suspend; 195 196 status = "okay"; 196 197 197 198 brcmf: wifi@1 {
+5 -1
arch/arm/mach-sunxi/mc_smp.c
··· 481 481 static int sunxi_cpu_powerdown(unsigned int cpu, unsigned int cluster) 482 482 { 483 483 u32 reg; 484 + int gating_bit = cpu; 484 485 485 486 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu); 486 487 if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS) 487 488 return -EINVAL; 488 489 490 + if (is_a83t && cpu == 0) 491 + gating_bit = 4; 492 + 489 493 /* gate processor power */ 490 494 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); 491 - reg |= PRCM_PWROFF_GATING_REG_CORE(cpu); 495 + reg |= PRCM_PWROFF_GATING_REG_CORE(gating_bit); 492 496 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); 493 497 udelay(20); 494 498
+1 -1
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
··· 127 127 status = "okay"; 128 128 129 129 i2c-mux@77 { 130 - compatible = "nxp,pca9847"; 130 + compatible = "nxp,pca9547"; 131 131 reg = <0x77>; 132 132 #address-cells = <1>; 133 133 #size-cells = <0>;
+3 -3
arch/arm64/boot/dts/freescale/imx8mm.dtsi
··· 394 394 }; 395 395 396 396 sdma2: dma-controller@302c0000 { 397 - compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; 397 + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 398 398 reg = <0x302c0000 0x10000>; 399 399 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 400 400 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, ··· 405 405 }; 406 406 407 407 sdma3: dma-controller@302b0000 { 408 - compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; 408 + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 409 409 reg = <0x302b0000 0x10000>; 410 410 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 411 411 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, ··· 737 737 }; 738 738 739 739 sdma1: dma-controller@30bd0000 { 740 - compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; 740 + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 741 741 reg = <0x30bd0000 0x10000>; 742 742 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 743 743 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
+3 -3
arch/arm64/boot/dts/freescale/imx8mn.dtsi
··· 288 288 }; 289 289 290 290 sdma3: dma-controller@302b0000 { 291 - compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; 291 + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 292 292 reg = <0x302b0000 0x10000>; 293 293 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 294 294 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, ··· 299 299 }; 300 300 301 301 sdma2: dma-controller@302c0000 { 302 - compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; 302 + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 303 303 reg = <0x302c0000 0x10000>; 304 304 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 305 305 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, ··· 612 612 }; 613 613 614 614 sdma1: dma-controller@30bd0000 { 615 - compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; 615 + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 616 616 reg = <0x30bd0000 0x10000>; 617 617 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 618 618 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
+1 -1
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
··· 88 88 regulator-name = "0V9_ARM"; 89 89 regulator-min-microvolt = <900000>; 90 90 regulator-max-microvolt = <1000000>; 91 - gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 91 + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 92 92 states = <1000000 0x1 93 93 900000 0x0>; 94 94 regulator-always-on;
+3 -2
drivers/reset/core.c
··· 76 76 * of_reset_simple_xlate - translate reset_spec to the reset line number 77 77 * @rcdev: a pointer to the reset controller device 78 78 * @reset_spec: reset line specifier as found in the device tree 79 - * @flags: a flags pointer to fill in (optional) 80 79 * 81 80 * This simple translation function should be used for reset controllers 82 81 * with 1:1 mapping, where reset lines can be indexed by number without gaps. ··· 747 748 for (i = 0; i < resets->num_rstcs; i++) 748 749 __reset_control_put_internal(resets->rstc[i]); 749 750 mutex_unlock(&reset_list_mutex); 751 + kfree(resets); 750 752 } 751 753 752 754 /** ··· 825 825 } 826 826 EXPORT_SYMBOL_GPL(__device_reset); 827 827 828 - /** 828 + /* 829 829 * APIs to manage an array of reset controls. 830 830 */ 831 + 831 832 /** 832 833 * of_reset_control_get_count - Count number of resets available with a device 833 834 *
+4 -4
drivers/soc/imx/gpc.c
··· 249 249 }; 250 250 251 251 static struct imx_pm_domain imx_gpc_domains[] = { 252 - [GPC_PGC_DOMAIN_ARM] { 252 + [GPC_PGC_DOMAIN_ARM] = { 253 253 .base = { 254 254 .name = "ARM", 255 255 .flags = GENPD_FLAG_ALWAYS_ON, 256 256 }, 257 257 }, 258 - [GPC_PGC_DOMAIN_PU] { 258 + [GPC_PGC_DOMAIN_PU] = { 259 259 .base = { 260 260 .name = "PU", 261 261 .power_off = imx6_pm_domain_power_off, ··· 266 266 .reg_offs = 0x260, 267 267 .cntr_pdn_bit = 0, 268 268 }, 269 - [GPC_PGC_DOMAIN_DISPLAY] { 269 + [GPC_PGC_DOMAIN_DISPLAY] = { 270 270 .base = { 271 271 .name = "DISPLAY", 272 272 .power_off = imx6_pm_domain_power_off, ··· 275 275 .reg_offs = 0x240, 276 276 .cntr_pdn_bit = 4, 277 277 }, 278 - [GPC_PGC_DOMAIN_PCI] { 278 + [GPC_PGC_DOMAIN_PCI] = { 279 279 .base = { 280 280 .name = "PCI", 281 281 .power_off = imx6_pm_domain_power_off,
+2 -2
include/linux/reset-controller.h
··· 7 7 struct reset_controller_dev; 8 8 9 9 /** 10 - * struct reset_control_ops 10 + * struct reset_control_ops - reset controller driver callbacks 11 11 * 12 12 * @reset: for self-deasserting resets, does all necessary 13 13 * things to reset the device ··· 33 33 * @provider: name of the reset controller device controlling this reset line 34 34 * @index: ID of the reset controller in the reset controller device 35 35 * @dev_id: name of the device associated with this reset line 36 - * @con_id name of the reset line (can be NULL) 36 + * @con_id: name of the reset line (can be NULL) 37 37 */ 38 38 struct reset_control_lookup { 39 39 struct list_head list;
+1 -1
include/linux/reset.h
··· 143 143 * If this function is called more than once for the same reset_control it will 144 144 * return -EBUSY. 145 145 * 146 - * See reset_control_get_shared for details on shared references to 146 + * See reset_control_get_shared() for details on shared references to 147 147 * reset-controls. 148 148 * 149 149 * Use of id names is optional.