Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'perf_urgent_for_v6.9_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 perf fixes from Borislav Petkov:
- Define the correct set of default hw events on AMD Zen4
- Use the correct stalled cycles PMCs on AMD Zen2 and newer
- Fix detection of the LBR freeze feature on AMD
* tag 'perf_urgent_for_v6.9_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/amd/core: Define a proper ref-cycles event for Zen 4 and later
perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later
perf/x86/amd/lbr: Use freeze based on availability
x86/cpufeatures: Add new word for scattered features
+62
-16
+34
-5
arch/x86/events/amd/core.c
+34
-5
arch/x86/events/amd/core.c
···
250
250
/*
251
251
* AMD Performance Monitor Family 17h and later:
252
252
*/
253
-
static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
253
+
static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX] =
254
254
{
255
255
[PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
256
256
[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
···
262
262
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x0187,
263
263
};
264
264
265
+
static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
266
+
{
267
+
[PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
268
+
[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
269
+
[PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
270
+
[PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
271
+
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
272
+
[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
273
+
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
274
+
};
275
+
276
+
static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =
277
+
{
278
+
[PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
279
+
[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
280
+
[PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
281
+
[PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
282
+
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
283
+
[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
284
+
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
285
+
[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x100000120,
286
+
};
287
+
265
288
static u64 amd_pmu_event_map(int hw_event)
266
289
{
267
-
if (boot_cpu_data.x86 >= 0x17)
268
-
return amd_f17h_perfmon_event_map[hw_event];
290
+
if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >= 0x1a)
291
+
return amd_zen4_perfmon_event_map[hw_event];
292
+
293
+
if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
294
+
return amd_zen2_perfmon_event_map[hw_event];
295
+
296
+
if (cpu_feature_enabled(X86_FEATURE_ZEN1))
297
+
return amd_zen1_perfmon_event_map[hw_event];
269
298
270
299
return amd_perfmon_event_map[hw_event];
271
300
}
···
933
904
if (!status)
934
905
goto done;
935
906
936
-
/* Read branch records before unfreezing */
937
-
if (status & GLOBAL_STATUS_LBRS_FROZEN) {
907
+
/* Read branch records */
908
+
if (x86_pmu.lbr_nr) {
938
909
amd_pmu_lbr_read();
939
910
status &= ~GLOBAL_STATUS_LBRS_FROZEN;
940
911
}
+10
-6
arch/x86/events/amd/lbr.c
+10
-6
arch/x86/events/amd/lbr.c
···
402
402
wrmsrl(MSR_AMD64_LBR_SELECT, lbr_select);
403
403
}
404
404
405
-
rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
406
-
rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
405
+
if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {
406
+
rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
407
+
wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
408
+
}
407
409
408
-
wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
410
+
rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
409
411
wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN);
410
412
}
411
413
···
420
418
return;
421
419
422
420
rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
423
-
rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
424
-
425
421
wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN);
426
-
wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
422
+
423
+
if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {
424
+
rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
425
+
wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
426
+
}
427
427
}
428
428
429
429
__init int amd_pmu_lbr_init(void)
+4
-2
arch/x86/include/asm/cpufeature.h
+4
-2
arch/x86/include/asm/cpufeature.h
···
91
91
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \
92
92
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) || \
93
93
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 20, feature_bit) || \
94
+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 21, feature_bit) || \
94
95
REQUIRED_MASK_CHECK || \
95
-
BUILD_BUG_ON_ZERO(NCAPINTS != 21))
96
+
BUILD_BUG_ON_ZERO(NCAPINTS != 22))
96
97
97
98
#define DISABLED_MASK_BIT_SET(feature_bit) \
98
99
( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \
···
117
116
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \
118
117
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) || \
119
118
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 20, feature_bit) || \
119
+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 21, feature_bit) || \
120
120
DISABLED_MASK_CHECK || \
121
-
BUILD_BUG_ON_ZERO(NCAPINTS != 21))
121
+
BUILD_BUG_ON_ZERO(NCAPINTS != 22))
122
122
123
123
#define cpu_has(c, bit) \
124
124
(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
+9
-1
arch/x86/include/asm/cpufeatures.h
+9
-1
arch/x86/include/asm/cpufeatures.h
···
13
13
/*
14
14
* Defines x86 CPU feature bits
15
15
*/
16
-
#define NCAPINTS 21 /* N 32-bit words worth of info */
16
+
#define NCAPINTS 22 /* N 32-bit words worth of info */
17
17
#define NBUGINTS 2 /* N 32-bit bug flags */
18
18
19
19
/*
···
458
458
#define X86_FEATURE_SBPB (20*32+27) /* "" Selective Branch Prediction Barrier */
459
459
#define X86_FEATURE_IBPB_BRTYPE (20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */
460
460
#define X86_FEATURE_SRSO_NO (20*32+29) /* "" CPU is not affected by SRSO */
461
+
462
+
/*
463
+
* Extended auxiliary flags: Linux defined - for features scattered in various
464
+
* CPUID levels like 0x80000022, etc.
465
+
*
466
+
* Reuse free bits when adding new feature flags!
467
+
*/
468
+
#define X86_FEATURE_AMD_LBR_PMC_FREEZE (21*32+ 0) /* AMD LBR and PMC Freeze */
461
469
462
470
/*
463
471
* BUG word(s)
+2
-1
arch/x86/include/asm/disabled-features.h
+2
-1
arch/x86/include/asm/disabled-features.h
···
155
155
#define DISABLED_MASK18 (DISABLE_IBT)
156
156
#define DISABLED_MASK19 (DISABLE_SEV_SNP)
157
157
#define DISABLED_MASK20 0
158
-
#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)
158
+
#define DISABLED_MASK21 0
159
+
#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 22)
159
160
160
161
#endif /* _ASM_X86_DISABLED_FEATURES_H */
+2
-1
arch/x86/include/asm/required-features.h
+2
-1
arch/x86/include/asm/required-features.h
···
99
99
#define REQUIRED_MASK18 0
100
100
#define REQUIRED_MASK19 0
101
101
#define REQUIRED_MASK20 0
102
-
#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)
102
+
#define REQUIRED_MASK21 0
103
+
#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 22)
103
104
104
105
#endif /* _ASM_X86_REQUIRED_FEATURES_H */
+1
arch/x86/kernel/cpu/scattered.c
+1
arch/x86/kernel/cpu/scattered.c