Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'char-misc-6.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull Char/Misc updates from Greg KH:
"Here is the big set of char/misc and other driver subsystem updates
for 6.5-rc1.
Lots of different, tiny, stuff in here, from a range of smaller driver
subsystems, including pulls from some substems directly:
- IIO driver updates and additions
- W1 driver updates and fixes (and a new maintainer!)
- FPGA driver updates and fixes
- Counter driver updates
- Extcon driver updates
- Interconnect driver updates
- Coresight driver updates
- mfd tree tag merge needed for other updates on top of that, lots of
small driver updates as patches, including:
- static const updates for class structures
- nvmem driver updates
- pcmcia driver fix
- lots of other small driver updates and fixes
All of these have been in linux-next for a while with no reported
problems"
* tag 'char-misc-6.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (243 commits)
bsr: fix build problem with bsr_class static cleanup
comedi: make all 'class' structures const
char: xillybus: make xillybus_class a static const structure
xilinx_hwicap: make icap_class a static const structure
virtio_console: make port class a static const structure
ppdev: make ppdev_class a static const structure
char: misc: make misc_class a static const structure
/dev/mem: make mem_class a static const structure
char: lp: make lp_class a static const structure
dsp56k: make dsp56k_class a static const structure
bsr: make bsr_class a static const structure
oradax: make 'cl' a static const structure
hwtracing: hisi_ptt: Fix potential sleep in atomic context
hwtracing: hisi_ptt: Advertise PERF_PMU_CAP_NO_EXCLUDE for PTT PMU
hwtracing: hisi_ptt: Export available filters through sysfs
hwtracing: hisi_ptt: Add support for dynamically updating the filter list
hwtracing: hisi_ptt: Factor out filter allocation and release operation
samples: pfsm: add CC_CAN_LINK dependency
misc: fastrpc: check return value of devm_kasprintf()
coresight: dummy: Update type of mode parameter in dummy_{sink,source}_enable()
...
+8593
-2569
+54
Documentation/ABI/testing/sysfs-bus-counter
+54
Documentation/ABI/testing/sysfs-bus-counter
···
90
90
counter does not freeze at the boundary points, but
91
91
counts continuously throughout.
92
92
93
+
interrupt on terminal count:
94
+
The output signal is initially low, and will remain low
95
+
until the counter reaches zero. The output signal then
96
+
goes high and remains high until a new preset value is
97
+
set.
98
+
99
+
hardware retriggerable one-shot:
100
+
The output signal is initially high. The output signal
101
+
will go low by a trigger input signal, and will remain
102
+
low until the counter reaches zero. The output will then
103
+
go high and remain high until the next trigger. A
104
+
trigger results in loading the counter to the preset
105
+
value and setting the output signal low, thus starting
106
+
the one-shot pulse.
107
+
108
+
rate generator:
109
+
The output signal is initially high. When the counter
110
+
has decremented to 1, the output signal goes low for one
111
+
clock pulse. The output signal then goes high again, the
112
+
counter is reloaded to the preset value, and the process
113
+
repeats in a periodic manner as such.
114
+
115
+
square wave mode:
116
+
The output signal is initially high.
117
+
118
+
If the initial count is even, the counter is decremented
119
+
by two on succeeding clock pulses. When the count
120
+
expires, the output signal changes value and the
121
+
counter is reloaded to the preset value. The process
122
+
repeats in periodic manner as such.
123
+
124
+
If the initial count is odd, the initial count minus one
125
+
(an even number) is loaded and then is decremented by
126
+
two on succeeding clock pulses. One clock pulse after
127
+
the count expires, the output signal goes low and the
128
+
counter is reloaded to the preset value minus one.
129
+
Succeeding clock pulses decrement the count by two. When
130
+
the count expires, the output goes high again and the
131
+
counter is reloaded to the preset value minus one. The
132
+
process repeats in a periodic manner as such.
133
+
134
+
software triggered strobe:
135
+
The output signal is initially high. When the count
136
+
expires, the output will go low for one clock pulse and
137
+
then go high again. The counting sequence is "triggered"
138
+
by setting the preset value.
139
+
140
+
hardware triggered strobe:
141
+
The output signal is initially high. Counting is started
142
+
by a trigger input signal. When the count expires, the
143
+
output signal will go low for one clock pulse and then
144
+
go high again. A trigger results in loading the counter
145
+
to the preset value.
146
+
93
147
What: /sys/bus/counter/devices/counterX/countY/count_mode_available
94
148
What: /sys/bus/counter/devices/counterX/countY/error_noise_available
95
149
What: /sys/bus/counter/devices/counterX/countY/function_available
+52
Documentation/ABI/testing/sysfs-devices-hisi_ptt
+52
Documentation/ABI/testing/sysfs-devices-hisi_ptt
···
59
59
The available tune data is [0, 1, 2]. Writing a negative value
60
60
will return an error, and out of range values will be converted
61
61
to 2. The value indicates a probable level of the event.
62
+
63
+
What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters
64
+
Date: May 2023
65
+
KernelVersion: 6.5
66
+
Contact: Yicong Yang <yangyicong@hisilicon.com>
67
+
Description: This directory contains the files providing the PCIe Root Port filters
68
+
information used for PTT trace. Each file is named after the supported
69
+
Root Port device name <domain>:<bus>:<device>.<function>.
70
+
71
+
See the description of the "filter" in Documentation/trace/hisi-ptt.rst
72
+
for more information.
73
+
74
+
What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters/multiselect
75
+
Date: May 2023
76
+
KernelVersion: 6.5
77
+
Contact: Yicong Yang <yangyicong@hisilicon.com>
78
+
Description: (Read) Indicates if this kind of filter can be selected at the same
79
+
time as others filters, or must be used on it's own. 1 indicates
80
+
the former case and 0 indicates the latter.
81
+
82
+
What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters/<bdf>
83
+
Date: May 2023
84
+
KernelVersion: 6.5
85
+
Contact: Yicong Yang <yangyicong@hisilicon.com>
86
+
Description: (Read) Indicates the filter value of this Root Port filter, which
87
+
can be used to control the TLP headers to trace by the PTT trace.
88
+
89
+
What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters
90
+
Date: May 2023
91
+
KernelVersion: 6.5
92
+
Contact: Yicong Yang <yangyicong@hisilicon.com>
93
+
Description: This directory contains the files providing the PCIe Requester filters
94
+
information used for PTT trace. Each file is named after the supported
95
+
Endpoint device name <domain>:<bus>:<device>.<function>.
96
+
97
+
See the description of the "filter" in Documentation/trace/hisi-ptt.rst
98
+
for more information.
99
+
100
+
What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters/multiselect
101
+
Date: May 2023
102
+
KernelVersion: 6.5
103
+
Contact: Yicong Yang <yangyicong@hisilicon.com>
104
+
Description: (Read) Indicates if this kind of filter can be selected at the same
105
+
time as others filters, or must be used on it's own. 1 indicates
106
+
the former case and 0 indicates the latter.
107
+
108
+
What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters/<bdf>
109
+
Date: May 2023
110
+
KernelVersion: 6.5
111
+
Contact: Yicong Yang <yangyicong@hisilicon.com>
112
+
Description: (Read) Indicates the filter value of this Requester filter, which
113
+
can be used to control the TLP headers to trace by the PTT trace.
+73
Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml
+73
Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/arm/arm,coresight-dummy-sink.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: ARM Coresight Dummy sink component
8
+
9
+
description: |
10
+
CoreSight components are compliant with the ARM CoreSight architecture
11
+
specification and can be connected in various topologies to suit a particular
12
+
SoCs tracing needs. These trace components can generally be classified as
13
+
sinks, links and sources. Trace data produced by one or more sources flows
14
+
through the intermediate links connecting the source to the currently selected
15
+
sink.
16
+
17
+
The Coresight dummy sink component is for the specific coresight sink devices
18
+
kernel don't have permission to access or configure, e.g., CoreSight EUD on
19
+
Qualcomm platforms. It is a mini-USB hub implemented to support the USB-based
20
+
debug and trace capabilities. For this device, a dummy driver is needed to
21
+
register it as Coresight sink device in kernel side, so that path can be
22
+
created in the driver. Then the trace flow would be transferred to EUD via
23
+
coresight link of AP processor. It provides Coresight API for operations on
24
+
dummy source devices, such as enabling and disabling them. It also provides
25
+
the Coresight dummy source paths for debugging.
26
+
27
+
The primary use case of the coresight dummy sink is to build path in kernel
28
+
side for dummy sink component.
29
+
30
+
maintainers:
31
+
- Mike Leach <mike.leach@linaro.org>
32
+
- Suzuki K Poulose <suzuki.poulose@arm.com>
33
+
- James Clark <james.clark@arm.com>
34
+
- Mao Jinlong <quic_jinlmao@quicinc.com>
35
+
- Hao Zhang <quic_hazha@quicinc.com>
36
+
37
+
properties:
38
+
compatible:
39
+
enum:
40
+
- arm,coresight-dummy-sink
41
+
42
+
in-ports:
43
+
$ref: /schemas/graph.yaml#/properties/ports
44
+
45
+
properties:
46
+
port:
47
+
description: Input connection from the Coresight Trace bus to
48
+
dummy sink, such as Embedded USB debugger(EUD).
49
+
50
+
$ref: /schemas/graph.yaml#/properties/port
51
+
52
+
required:
53
+
- compatible
54
+
- in-ports
55
+
56
+
additionalProperties: false
57
+
58
+
examples:
59
+
# Minimum dummy sink definition. Dummy sink connect to coresight replicator.
60
+
- |
61
+
sink {
62
+
compatible = "arm,coresight-dummy-sink";
63
+
64
+
in-ports {
65
+
port {
66
+
eud_in_replicator_swao: endpoint {
67
+
remote-endpoint = <&replicator_swao_out_eud>;
68
+
};
69
+
};
70
+
};
71
+
};
72
+
73
+
...
+71
Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml
+71
Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: ARM Coresight Dummy source component
8
+
9
+
description: |
10
+
CoreSight components are compliant with the ARM CoreSight architecture
11
+
specification and can be connected in various topologies to suit a particular
12
+
SoCs tracing needs. These trace components can generally be classified as
13
+
sinks, links and sources. Trace data produced by one or more sources flows
14
+
through the intermediate links connecting the source to the currently selected
15
+
sink.
16
+
17
+
The Coresight dummy source component is for the specific coresight source
18
+
devices kernel don't have permission to access or configure. For some SOCs,
19
+
there would be Coresight source trace components on sub-processor which
20
+
are conneted to AP processor via debug bus. For these devices, a dummy driver
21
+
is needed to register them as Coresight source devices, so that paths can be
22
+
created in the driver. It provides Coresight API for operations on dummy
23
+
source devices, such as enabling and disabling them. It also provides the
24
+
Coresight dummy source paths for debugging.
25
+
26
+
The primary use case of the coresight dummy source is to build path in kernel
27
+
side for dummy source component.
28
+
29
+
maintainers:
30
+
- Mike Leach <mike.leach@linaro.org>
31
+
- Suzuki K Poulose <suzuki.poulose@arm.com>
32
+
- James Clark <james.clark@arm.com>
33
+
- Mao Jinlong <quic_jinlmao@quicinc.com>
34
+
- Hao Zhang <quic_hazha@quicinc.com>
35
+
36
+
properties:
37
+
compatible:
38
+
enum:
39
+
- arm,coresight-dummy-source
40
+
41
+
out-ports:
42
+
$ref: /schemas/graph.yaml#/properties/ports
43
+
44
+
properties:
45
+
port:
46
+
description: Output connection from the source to Coresight
47
+
Trace bus.
48
+
$ref: /schemas/graph.yaml#/properties/port
49
+
50
+
required:
51
+
- compatible
52
+
- out-ports
53
+
54
+
additionalProperties: false
55
+
56
+
examples:
57
+
# Minimum dummy source definition. Dummy source connect to coresight funnel.
58
+
- |
59
+
source {
60
+
compatible = "arm,coresight-dummy-source";
61
+
62
+
out-ports {
63
+
port {
64
+
dummy_riscv_out_funnel_swao: endpoint {
65
+
remote-endpoint = <&funnel_swao_in_dummy_riscv>;
66
+
};
67
+
};
68
+
};
69
+
};
70
+
71
+
...
+9
-5
Documentation/devicetree/bindings/extcon/qcom,pm8941-misc.yaml
+9
-5
Documentation/devicetree/bindings/extcon/qcom,pm8941-misc.yaml
···
27
27
28
28
interrupt-names:
29
29
minItems: 1
30
-
items:
31
-
- const: usb_id
32
-
- const: usb_vbus
33
-
30
+
anyOf:
31
+
- items:
32
+
- const: usb_id
33
+
- const: usb_vbus
34
+
- items:
35
+
- const: usb_id
36
+
- items:
37
+
- const: usb_vbus
34
38
required:
35
39
- compatible
36
40
- reg
···
53
49
interrupt-controller;
54
50
#interrupt-cells = <4>;
55
51
56
-
usb_id: misc@900 {
52
+
usb_id: usb-detect@900 {
57
53
compatible = "qcom,pm8941-misc";
58
54
reg = <0x900>;
59
55
interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
+7
-7
Documentation/devicetree/bindings/extcon/wlf,arizona.yaml
+7
-7
Documentation/devicetree/bindings/extcon/wlf,arizona.yaml
···
23
23
headphone detect mode to HPDETL, ARIZONA_ACCDET_MODE_HPR/2 sets it
24
24
to HPDETR. If this node is not included or if the value is unknown,
25
25
then headphone detection mode is set to HPDETL.
26
-
$ref: "/schemas/types.yaml#/definitions/uint32"
26
+
$ref: /schemas/types.yaml#/definitions/uint32
27
27
minimum: 1
28
28
maximum: 2
29
29
···
51
51
description:
52
52
Additional software microphone detection debounce specified in
53
53
milliseconds.
54
-
$ref: "/schemas/types.yaml#/definitions/uint32"
54
+
$ref: /schemas/types.yaml#/definitions/uint32
55
55
56
56
wlf,micd-pol-gpio:
57
57
description:
···
63
63
description:
64
64
Time allowed for MICBIAS to startup prior to performing microphone
65
65
detection, specified as per the ARIZONA_MICD_TIME_XXX defines.
66
-
$ref: "/schemas/types.yaml#/definitions/uint32"
66
+
$ref: /schemas/types.yaml#/definitions/uint32
67
67
minimum: 0
68
68
maximum: 12
69
69
···
71
71
description:
72
72
Delay between successive microphone detection measurements, specified
73
73
as per the ARIZONA_MICD_TIME_XXX defines.
74
-
$ref: "/schemas/types.yaml#/definitions/uint32"
74
+
$ref: /schemas/types.yaml#/definitions/uint32
75
75
minimum: 0
76
76
maximum: 12
77
77
···
79
79
description:
80
80
Microphone detection hardware debounces specified as the number of
81
81
measurements to take.
82
-
$ref: "/schemas/types.yaml#/definitions/uint32"
82
+
$ref: /schemas/types.yaml#/definitions/uint32
83
83
enum: [2, 4]
84
84
85
85
wlf,micd-timeout-ms:
···
97
97
CTIA / OMTP headsets), the field can be of variable length but
98
98
should always be a multiple of 3 cells long, each three cell group
99
99
represents one polarity configuration.
100
-
$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
100
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
101
101
items:
102
102
items:
103
103
- description:
···
119
119
description:
120
120
Settings for the general purpose switch, set as one of the
121
121
ARIZONA_GPSW_XXX defines.
122
-
$ref: "/schemas/types.yaml#/definitions/uint32"
122
+
$ref: /schemas/types.yaml#/definitions/uint32
123
123
minimum: 0
124
124
maximum: 3
125
125
+5
Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
+5
Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
···
47
47
avdd-supply:
48
48
description: AVdd voltage supply
49
49
50
+
vref-supply:
51
+
description: VRef voltage supply
52
+
50
53
adi,rejection-60-Hz-enable:
51
54
description: |
52
55
This bit enables a notch at 60 Hz when the first notch of the sinc
···
92
89
- interrupts
93
90
- dvdd-supply
94
91
- avdd-supply
92
+
- vref-supply
95
93
- spi-cpol
96
94
- spi-cpha
97
95
···
119
115
interrupt-parent = <&gpio>;
120
116
dvdd-supply = <&dvdd>;
121
117
avdd-supply = <&avdd>;
118
+
vref-supply = <&vref>;
122
119
123
120
adi,refin2-pins-enable;
124
121
adi,rejection-60-Hz-enable;
+1
Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
+1
Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
+15
-13
Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
+15
-13
Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
···
54
54
- '#io-channel-cells'
55
55
56
56
patternProperties:
57
-
"^.*@[0-9a-f]+$":
57
+
"^channel@[0-9a-f]+$":
58
58
type: object
59
59
additionalProperties: false
60
60
description: |
···
101
101
oneOf:
102
102
- items:
103
103
- const: 1
104
-
- enum: [ 1, 3, 4, 6, 20, 8, 10 ]
104
+
- enum: [ 1, 3, 4, 6, 20, 8, 10, 16 ]
105
105
- items:
106
106
- const: 10
107
107
- const: 81
···
148
148
149
149
then:
150
150
patternProperties:
151
-
"^.*@[0-9a-f]+$":
151
+
"^channel@[0-9a-f]+$":
152
152
properties:
153
153
qcom,decimation:
154
154
enum: [ 512, 1024, 2048, 4096 ]
···
171
171
172
172
then:
173
173
patternProperties:
174
-
"^.*@[0-9a-f]+$":
174
+
"^channel@[0-9a-f]+$":
175
175
properties:
176
176
qcom,decimation:
177
177
enum: [ 256, 512, 1024 ]
···
194
194
195
195
then:
196
196
patternProperties:
197
-
"^.*@[0-9a-f]+$":
197
+
"^channel@[0-9a-f]+$":
198
198
properties:
199
199
qcom,decimation:
200
200
enum: [ 250, 420, 840 ]
···
217
217
218
218
then:
219
219
patternProperties:
220
-
"^.*@[0-9a-f]+$":
220
+
"^channel@[0-9a-f]+$":
221
221
properties:
222
222
qcom,decimation:
223
223
enum: [ 85, 340, 1360 ]
···
249
249
#io-channel-cells = <1>;
250
250
251
251
/* Channel node */
252
-
adc-chan@39 {
252
+
channel@39 {
253
253
reg = <0x39>;
254
254
qcom,decimation = <512>;
255
255
qcom,ratiometric;
···
258
258
qcom,pre-scaling = <1 3>;
259
259
};
260
260
261
-
adc-chan@9 {
261
+
channel@9 {
262
262
reg = <0x9>;
263
263
};
264
264
265
-
adc-chan@a {
265
+
channel@a {
266
266
reg = <0xa>;
267
267
};
268
268
269
-
adc-chan@e {
269
+
channel@e {
270
270
reg = <0xe>;
271
271
};
272
272
273
-
adc-chan@f {
273
+
channel@f {
274
274
reg = <0xf>;
275
275
};
276
276
};
···
292
292
#io-channel-cells = <1>;
293
293
294
294
/* Other properties are omitted */
295
-
xo-therm@44 {
295
+
channel@44 {
296
296
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
297
297
qcom,ratiometric;
298
298
qcom,hw-settle-time = <200>;
299
+
label = "xo_therm";
299
300
};
300
301
301
-
conn-therm@47 {
302
+
channel@47 {
302
303
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
303
304
qcom,ratiometric;
304
305
qcom,hw-settle-time = <200>;
306
+
label = "conn_therm";
305
307
};
306
308
};
307
309
};
+1
Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml
+1
Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml
+1
-1
Documentation/devicetree/bindings/iio/afe/voltage-divider.yaml
+1
-1
Documentation/devicetree/bindings/iio/afe/voltage-divider.yaml
+3
Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml
+3
Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml
+1
Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml
+1
Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml
+49
Documentation/devicetree/bindings/iio/light/rohm,bu27008.yaml
+49
Documentation/devicetree/bindings/iio/light/rohm,bu27008.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/light/rohm,bu27008.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: ROHM BU27008 color sensor
8
+
9
+
maintainers:
10
+
- Matti Vaittinen <mazziesaccount@gmail.com>
11
+
12
+
description:
13
+
The ROHM BU27008 is a sensor with 5 photodiodes (red, green, blue, clear
14
+
and IR) with four configurable channels. Red and green being always
15
+
available and two out of the rest three (blue, clear, IR) can be
16
+
selected to be simultaneously measured. Typical application is adjusting
17
+
LCD backlight of TVs, mobile phones and tablet PCs.
18
+
19
+
properties:
20
+
compatible:
21
+
const: rohm,bu27008
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
vdd-supply: true
30
+
31
+
required:
32
+
- compatible
33
+
- reg
34
+
35
+
additionalProperties: false
36
+
37
+
examples:
38
+
- |
39
+
i2c {
40
+
#address-cells = <1>;
41
+
#size-cells = <0>;
42
+
43
+
light-sensor@38 {
44
+
compatible = "rohm,bu27008";
45
+
reg = <0x38>;
46
+
};
47
+
};
48
+
49
+
...
+68
Documentation/devicetree/bindings/iio/light/ti,opt4001.yaml
+68
Documentation/devicetree/bindings/iio/light/ti,opt4001.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/light/ti,opt4001.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Texas Instruments OPT4001 Ambient Light Sensor
8
+
9
+
maintainers:
10
+
- Stefan Windfeldt-Prytz <stefan.windfeldt-prytz@axis.com>
11
+
12
+
description:
13
+
Ambient light sensor with an i2c interface.
14
+
Last part of compatible is for the packaging used.
15
+
Picostar is a 4 pinned SMT and sot-5x3 is a 8 pinned SOT.
16
+
https://www.ti.com/lit/gpn/opt4001
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- ti,opt4001-picostar
22
+
- ti,opt4001-sot-5x3
23
+
24
+
reg:
25
+
maxItems: 1
26
+
27
+
interrupts:
28
+
maxItems: 1
29
+
30
+
vdd-supply:
31
+
description: Regulator that provides power to the sensor
32
+
33
+
required:
34
+
- compatible
35
+
- reg
36
+
37
+
allOf:
38
+
- if:
39
+
properties:
40
+
compatible:
41
+
contains:
42
+
const: ti,opt4001-sot-5x3
43
+
then:
44
+
properties:
45
+
interrupts:
46
+
maxItems: 1
47
+
else:
48
+
properties:
49
+
interrupts: false
50
+
51
+
additionalProperties: false
52
+
53
+
examples:
54
+
- |
55
+
#include <dt-bindings/interrupt-controller/irq.h>
56
+
i2c {
57
+
#address-cells = <1>;
58
+
#size-cells = <0>;
59
+
60
+
light-sensor@44 {
61
+
compatible = "ti,opt4001-sot-5x3";
62
+
reg = <0x44>;
63
+
vdd-supply = <&vdd_reg>;
64
+
interrupt-parent = <&gpio1>;
65
+
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
66
+
};
67
+
};
68
+
...
+78
Documentation/devicetree/bindings/iio/potentiometer/renesas,x9250.yaml
+78
Documentation/devicetree/bindings/iio/potentiometer/renesas,x9250.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/potentiometer/renesas,x9250.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Renesas X9250 quad potentiometers
8
+
9
+
maintainers:
10
+
- Herve Codina <herve.codina@bootlin.com>
11
+
12
+
description:
13
+
The Renesas X9250 integrates four digitally controlled potentiometers.
14
+
On each potentiometer, the X9250T has a 100 kOhms total resistance and the
15
+
X9250U has a 50 kOhms total resistance.
16
+
17
+
allOf:
18
+
- $ref: /schemas/spi/spi-peripheral-props.yaml
19
+
20
+
properties:
21
+
compatible:
22
+
enum:
23
+
- renesas,x9250t
24
+
- renesas,x9250u
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
vcc-supply:
30
+
description:
31
+
Regulator for the VCC power supply.
32
+
33
+
avp-supply:
34
+
description:
35
+
Regulator for the analog V+ power supply.
36
+
37
+
avn-supply:
38
+
description:
39
+
Regulator for the analog V- power supply.
40
+
41
+
'#io-channel-cells':
42
+
const: 1
43
+
44
+
spi-max-frequency:
45
+
maximum: 2000000
46
+
47
+
wp-gpios:
48
+
maxItems: 1
49
+
description:
50
+
GPIO connected to the write-protect pin.
51
+
52
+
required:
53
+
- compatible
54
+
- reg
55
+
- vcc-supply
56
+
- avp-supply
57
+
- avn-supply
58
+
- '#io-channel-cells'
59
+
60
+
unevaluatedProperties: false
61
+
62
+
examples:
63
+
- |
64
+
#include <dt-bindings/gpio/gpio.h>
65
+
spi {
66
+
#address-cells = <1>;
67
+
#size-cells = <0>;
68
+
potentiometer@0 {
69
+
compatible = "renesas,x9250t";
70
+
reg = <0>;
71
+
vcc-supply = <&vcc_regulator>;
72
+
avp-supply = <&avp_regulator>;
73
+
avn-supply = <&avp_regulator>;
74
+
wp-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
75
+
spi-max-frequency = <2000000>;
76
+
#io-channel-cells = <1>;
77
+
};
78
+
};
+104
Documentation/devicetree/bindings/iio/pressure/honeywell,mprls0025pa.yaml
+104
Documentation/devicetree/bindings/iio/pressure/honeywell,mprls0025pa.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/pressure/honeywell,mprls0025pa.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Honeywell mprls0025pa pressure sensor
8
+
9
+
maintainers:
10
+
- Andreas Klinger <ak@it-klinger.de>
11
+
12
+
description: |
13
+
Honeywell pressure sensor of model mprls0025pa.
14
+
15
+
This sensor has an I2C and SPI interface. Only the I2C interface is
16
+
implemented.
17
+
18
+
There are many models with different pressure ranges available. The vendor
19
+
calls them "mpr series". All of them have the identical programming model and
20
+
differ in the pressure range, unit and transfer function.
21
+
22
+
To support different models one need to specify the pressure range as well as
23
+
the transfer function. Pressure range needs to be converted from its unit to
24
+
pascal.
25
+
26
+
The transfer function defines the ranges of numerical values delivered by the
27
+
sensor. The minimal range value stands for the minimum pressure and the
28
+
maximum value also for the maximum pressure with linear relation inside the
29
+
range.
30
+
31
+
Specifications about the devices can be found at:
32
+
https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/
33
+
products/sensors/pressure-sensors/board-mount-pressure-sensors/
34
+
micropressure-mpr-series/documents/
35
+
sps-siot-mpr-series-datasheet-32332628-ciid-172626.pdf
36
+
37
+
properties:
38
+
compatible:
39
+
const: honeywell,mprls0025pa
40
+
41
+
reg:
42
+
maxItems: 1
43
+
44
+
interrupts:
45
+
maxItems: 1
46
+
47
+
reset-gpios:
48
+
description:
49
+
Optional GPIO for resetting the device.
50
+
If not present the device is not resetted during the probe.
51
+
maxItems: 1
52
+
53
+
honeywell,pmin-pascal:
54
+
description:
55
+
Minimum pressure value the sensor can measure in pascal.
56
+
$ref: /schemas/types.yaml#/definitions/uint32
57
+
58
+
honeywell,pmax-pascal:
59
+
description:
60
+
Maximum pressure value the sensor can measure in pascal.
61
+
$ref: /schemas/types.yaml#/definitions/uint32
62
+
63
+
honeywell,transfer-function:
64
+
description: |
65
+
Transfer function which defines the range of valid values delivered by the
66
+
sensor.
67
+
1 - A, 10% to 90% of 2^24 (1677722 .. 15099494)
68
+
2 - B, 2.5% to 22.5% of 2^24 (419430 .. 3774874)
69
+
3 - C, 20% to 80% of 2^24 (3355443 .. 13421773)
70
+
$ref: /schemas/types.yaml#/definitions/uint32
71
+
72
+
vdd-supply:
73
+
description: provide VDD power to the sensor.
74
+
75
+
required:
76
+
- compatible
77
+
- reg
78
+
- honeywell,pmin-pascal
79
+
- honeywell,pmax-pascal
80
+
- honeywell,transfer-function
81
+
- vdd-supply
82
+
83
+
additionalProperties: false
84
+
85
+
examples:
86
+
- |
87
+
#include <dt-bindings/gpio/gpio.h>
88
+
#include <dt-bindings/interrupt-controller/irq.h>
89
+
i2c {
90
+
#address-cells = <1>;
91
+
#size-cells = <0>;
92
+
93
+
pressure@18 {
94
+
compatible = "honeywell,mprls0025pa";
95
+
reg = <0x18>;
96
+
reset-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
97
+
interrupt-parent = <&gpio3>;
98
+
interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
99
+
honeywell,pmin-pascal = <0>;
100
+
honeywell,pmax-pascal = <172369>;
101
+
honeywell,transfer-function = <1>;
102
+
vdd-supply = <&vcc_3v3>;
103
+
};
104
+
};
+1
Documentation/devicetree/bindings/iio/st,st-sensors.yaml
+1
Documentation/devicetree/bindings/iio/st,st-sensors.yaml
+4
-2
Documentation/devicetree/bindings/iio/temperature/melexis,mlx90614.yaml
+4
-2
Documentation/devicetree/bindings/iio/temperature/melexis,mlx90614.yaml
···
4
4
$id: http://devicetree.org/schemas/iio/temperature/melexis,mlx90614.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Melexis MLX90614 contactless IR temperature sensor
7
+
title: Melexis MLX90614/MLX90615 contactless IR temperature sensor
8
8
9
9
maintainers:
10
10
- Peter Meerwald <pmeerw@pmeerw.net>
···
15
15
16
16
properties:
17
17
compatible:
18
-
const: melexis,mlx90614
18
+
enum:
19
+
- melexis,mlx90614
20
+
- melexis,mlx90615
19
21
20
22
reg:
21
23
maxItems: 1
+42
Documentation/devicetree/bindings/iio/temperature/ti,tmp006.yaml
+42
Documentation/devicetree/bindings/iio/temperature/ti,tmp006.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/temperature/ti,tmp006.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TI TMP006 IR thermopile sensor
8
+
9
+
maintainers:
10
+
- Peter Meerwald <pmeerw@pmeerw.net>
11
+
12
+
description: |
13
+
TI TMP006 - Infrared Thermopile Sensor in Chip-Scale Package.
14
+
https://cdn.sparkfun.com/datasheets/Sensors/Temp/tmp006.pdf
15
+
16
+
properties:
17
+
compatible:
18
+
const: ti,tmp006
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
vdd-supply:
24
+
description: provide VDD power to the sensor.
25
+
26
+
required:
27
+
- compatible
28
+
- reg
29
+
30
+
additionalProperties: false
31
+
32
+
examples:
33
+
- |
34
+
i2c {
35
+
#address-cells = <1>;
36
+
#size-cells = <0>;
37
+
temperature-sensor@40 {
38
+
compatible = "ti,tmp006";
39
+
reg = <0x40>;
40
+
vdd-supply = <&ldo4_reg>;
41
+
};
42
+
};
+1
-1
Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml
+1
-1
Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml
+15
Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml
+15
Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml
···
36
36
et0macaddr:
37
37
type: object
38
38
description: First Ethernet interface's MAC address
39
+
properties:
40
+
"#nvmem-cell-cells":
41
+
description: The first argument is a MAC address offset.
42
+
const: 1
43
+
additionalProperties: false
39
44
40
45
et1macaddr:
41
46
type: object
42
47
description: Second Ethernet interface's MAC address
48
+
properties:
49
+
"#nvmem-cell-cells":
50
+
description: The first argument is a MAC address offset.
51
+
const: 1
52
+
additionalProperties: false
43
53
44
54
et2macaddr:
45
55
type: object
46
56
description: Third Ethernet interface's MAC address
57
+
properties:
58
+
"#nvmem-cell-cells":
59
+
description: The first argument is a MAC address offset.
60
+
const: 1
61
+
additionalProperties: false
47
62
48
63
unevaluatedProperties: false
49
64
+3
-23
Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml
+3
-23
Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml
···
4
4
$id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Freescale i.MX6 On-Chip OTP Controller (OCOTP)
7
+
title: Freescale i.MX On-Chip OTP Controller (OCOTP)
8
8
9
9
maintainers:
10
10
- Anson Huang <Anson.Huang@nxp.com>
···
12
12
description: |
13
13
This binding represents the on-chip eFuse OTP controller found on
14
14
i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL,
15
-
i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN and i.MX8MP SoCs.
15
+
i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN i.MX8MP and i.MX93 SoCs.
16
16
17
17
allOf:
18
18
- $ref: nvmem.yaml#
···
32
32
- fsl,imx7ulp-ocotp
33
33
- fsl,imx8mq-ocotp
34
34
- fsl,imx8mm-ocotp
35
+
- fsl,imx93-ocotp
35
36
- const: syscon
36
37
- items:
37
38
- enum:
···
47
46
reg:
48
47
maxItems: 1
49
48
50
-
"#address-cells":
51
-
const: 1
52
-
53
-
"#size-cells":
54
-
const: 1
55
-
56
49
clocks:
57
50
maxItems: 1
58
51
···
55
60
- "#size-cells"
56
61
- compatible
57
62
- reg
58
-
59
-
patternProperties:
60
-
"^.*@[0-9a-f]+$":
61
-
type: object
62
-
63
-
properties:
64
-
reg:
65
-
maxItems: 1
66
-
description:
67
-
Offset and size in bytes within the storage device.
68
-
69
-
required:
70
-
- reg
71
-
72
-
additionalProperties: false
73
63
74
64
unevaluatedProperties: false
75
65
+31
Documentation/devicetree/bindings/nvmem/layouts/fixed-cell.yaml
+31
Documentation/devicetree/bindings/nvmem/layouts/fixed-cell.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/nvmem/layouts/fixed-cell.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Fixed offset & size NVMEM cell
8
+
9
+
maintainers:
10
+
- Rafał Miłecki <rafal@milecki.pl>
11
+
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
12
+
13
+
properties:
14
+
reg:
15
+
maxItems: 1
16
+
17
+
bits:
18
+
$ref: /schemas/types.yaml#/definitions/uint32-array
19
+
items:
20
+
- minimum: 0
21
+
maximum: 7
22
+
description:
23
+
Offset in bit within the address range specified by reg.
24
+
- minimum: 1
25
+
description:
26
+
Size in bit within the address range specified by reg.
27
+
28
+
required:
29
+
- reg
30
+
31
+
additionalProperties: true
+50
Documentation/devicetree/bindings/nvmem/layouts/fixed-layout.yaml
+50
Documentation/devicetree/bindings/nvmem/layouts/fixed-layout.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/nvmem/layouts/fixed-layout.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVMEM layout for fixed NVMEM cells
8
+
9
+
description:
10
+
Many NVMEM devices have hardcoded cells layout (offset and size of defined
11
+
NVMEM content doesn't change).
12
+
13
+
This binding allows defining such NVMEM layout with its cells. It can be used
14
+
on top of any NVMEM device.
15
+
16
+
maintainers:
17
+
- Rafał Miłecki <rafal@milecki.pl>
18
+
19
+
properties:
20
+
compatible:
21
+
const: fixed-layout
22
+
23
+
"#address-cells":
24
+
const: 1
25
+
26
+
"#size-cells":
27
+
const: 1
28
+
29
+
patternProperties:
30
+
"@[a-f0-9]+$":
31
+
type: object
32
+
$ref: fixed-cell.yaml
33
+
unevaluatedProperties: false
34
+
35
+
required:
36
+
- compatible
37
+
38
+
additionalProperties: false
39
+
40
+
examples:
41
+
- |
42
+
nvmem-layout {
43
+
compatible = "fixed-layout";
44
+
#address-cells = <1>;
45
+
#size-cells = <1>;
46
+
47
+
calibration@4000 {
48
+
reg = <0x4000 0x100>;
49
+
};
50
+
};
+1
-4
Documentation/devicetree/bindings/nvmem/layouts/nvmem-layout.yaml
+1
-4
Documentation/devicetree/bindings/nvmem/layouts/nvmem-layout.yaml
···
18
18
perform their parsing. The nvmem-layout container is here to describe these.
19
19
20
20
oneOf:
21
+
- $ref: fixed-layout.yaml
21
22
- $ref: kontron,sl28-vpd.yaml
22
23
- $ref: onie,tlv-layout.yaml
23
24
24
25
properties:
25
26
compatible: true
26
-
27
-
'#address-cells': false
28
-
29
-
'#size-cells': false
30
27
31
28
required:
32
29
- compatible
+1
Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
+1
Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
+1
-7
Documentation/devicetree/bindings/nvmem/mxs-ocotp.yaml
+1
-7
Documentation/devicetree/bindings/nvmem/mxs-ocotp.yaml
···
18
18
- fsl,imx23-ocotp
19
19
- fsl,imx28-ocotp
20
20
21
-
"#address-cells":
22
-
const: 1
23
-
24
-
"#size-cells":
25
-
const: 1
26
-
27
21
reg:
28
22
maxItems: 1
29
23
···
29
35
- reg
30
36
- clocks
31
37
32
-
additionalProperties: false
38
+
unevaluatedProperties: false
33
39
34
40
examples:
35
41
- |
+23
-32
Documentation/devicetree/bindings/nvmem/nvmem.yaml
+23
-32
Documentation/devicetree/bindings/nvmem/nvmem.yaml
···
49
49
patternProperties:
50
50
"@[0-9a-f]+(,[0-7])?$":
51
51
type: object
52
-
53
-
properties:
54
-
reg:
55
-
maxItems: 1
56
-
description:
57
-
Offset and size in bytes within the storage device.
58
-
59
-
bits:
60
-
$ref: /schemas/types.yaml#/definitions/uint32-array
61
-
items:
62
-
- minimum: 0
63
-
maximum: 7
64
-
description:
65
-
Offset in bit within the address range specified by reg.
66
-
- minimum: 1
67
-
description:
68
-
Size in bit within the address range specified by reg.
52
+
$ref: layouts/fixed-cell.yaml
53
+
deprecated: true
69
54
70
55
additionalProperties: true
71
56
···
68
83
69
84
/* ... */
70
85
71
-
/* Data cells */
72
-
tsens_calibration: calib@404 {
73
-
reg = <0x404 0x10>;
74
-
};
86
+
nvmem-layout {
87
+
compatible = "fixed-layout";
88
+
#address-cells = <1>;
89
+
#size-cells = <1>;
75
90
76
-
tsens_calibration_bckp: calib_bckp@504 {
77
-
reg = <0x504 0x11>;
78
-
bits = <6 128>;
79
-
};
91
+
/* Data cells */
92
+
tsens_calibration: calib@404 {
93
+
reg = <0x404 0x10>;
94
+
};
80
95
81
-
pvs_version: pvs-version@6 {
82
-
reg = <0x6 0x2>;
83
-
bits = <7 2>;
84
-
};
96
+
tsens_calibration_bckp: calib_bckp@504 {
97
+
reg = <0x504 0x11>;
98
+
bits = <6 128>;
99
+
};
85
100
86
-
speed_bin: speed-bin@c{
87
-
reg = <0xc 0x1>;
88
-
bits = <2 3>;
101
+
pvs_version: pvs-version@6 {
102
+
reg = <0x6 0x2>;
103
+
bits = <7 2>;
104
+
};
105
+
106
+
speed_bin: speed-bin@c{
107
+
reg = <0xc 0x1>;
108
+
bits = <2 3>;
109
+
};
89
110
};
90
111
};
91
112
-6
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
-6
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
-6
Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml
-6
Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml
+1
Documentation/devicetree/bindings/nvmem/rmem.yaml
+1
Documentation/devicetree/bindings/nvmem/rmem.yaml
+122
Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml
+122
Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip internal OTP (One Time Programmable) memory
8
+
9
+
maintainers:
10
+
- Heiko Stuebner <heiko@sntech.de>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- rockchip,px30-otp
16
+
- rockchip,rk3308-otp
17
+
- rockchip,rk3588-otp
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
clocks:
23
+
minItems: 3
24
+
maxItems: 4
25
+
26
+
clock-names:
27
+
minItems: 3
28
+
items:
29
+
- const: otp
30
+
- const: apb_pclk
31
+
- const: phy
32
+
- const: arb
33
+
34
+
resets:
35
+
minItems: 1
36
+
maxItems: 3
37
+
38
+
reset-names:
39
+
minItems: 1
40
+
maxItems: 3
41
+
42
+
required:
43
+
- compatible
44
+
- reg
45
+
- clocks
46
+
- clock-names
47
+
- resets
48
+
- reset-names
49
+
50
+
allOf:
51
+
- $ref: nvmem.yaml#
52
+
53
+
- if:
54
+
properties:
55
+
compatible:
56
+
contains:
57
+
enum:
58
+
- rockchip,px30-otp
59
+
- rockchip,rk3308-otp
60
+
then:
61
+
properties:
62
+
clocks:
63
+
maxItems: 3
64
+
resets:
65
+
maxItems: 1
66
+
reset-names:
67
+
items:
68
+
- const: phy
69
+
70
+
- if:
71
+
properties:
72
+
compatible:
73
+
contains:
74
+
enum:
75
+
- rockchip,rk3588-otp
76
+
then:
77
+
properties:
78
+
clocks:
79
+
minItems: 4
80
+
resets:
81
+
minItems: 3
82
+
reset-names:
83
+
items:
84
+
- const: otp
85
+
- const: apb
86
+
- const: arb
87
+
88
+
unevaluatedProperties: false
89
+
90
+
examples:
91
+
- |
92
+
#include <dt-bindings/clock/px30-cru.h>
93
+
94
+
soc {
95
+
#address-cells = <2>;
96
+
#size-cells = <2>;
97
+
98
+
otp: efuse@ff290000 {
99
+
compatible = "rockchip,px30-otp";
100
+
reg = <0x0 0xff290000 0x0 0x4000>;
101
+
clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
102
+
<&cru PCLK_OTP_PHY>;
103
+
clock-names = "otp", "apb_pclk", "phy";
104
+
resets = <&cru SRST_OTP_PHY>;
105
+
reset-names = "phy";
106
+
#address-cells = <1>;
107
+
#size-cells = <1>;
108
+
109
+
cpu_id: id@7 {
110
+
reg = <0x07 0x10>;
111
+
};
112
+
113
+
cpu_leakage: cpu-leakage@17 {
114
+
reg = <0x17 0x1>;
115
+
};
116
+
117
+
performance: performance@1e {
118
+
reg = <0x1e 0x1>;
119
+
bits = <4 3>;
120
+
};
121
+
};
122
+
};
-25
Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
-25
Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
···
1
-
Rockchip internal OTP (One Time Programmable) memory device tree bindings
2
-
3
-
Required properties:
4
-
- compatible: Should be one of the following.
5
-
- "rockchip,px30-otp" - for PX30 SoCs.
6
-
- "rockchip,rk3308-otp" - for RK3308 SoCs.
7
-
- reg: Should contain the registers location and size
8
-
- clocks: Must contain an entry for each entry in clock-names.
9
-
- clock-names: Should be "otp", "apb_pclk" and "phy".
10
-
- resets: Must contain an entry for each entry in reset-names.
11
-
See ../../reset/reset.txt for details.
12
-
- reset-names: Should be "phy".
13
-
14
-
See nvmem.txt for more information.
15
-
16
-
Example:
17
-
otp: otp@ff290000 {
18
-
compatible = "rockchip,px30-otp";
19
-
reg = <0x0 0xff290000 0x0 0x4000>;
20
-
#address-cells = <1>;
21
-
#size-cells = <1>;
22
-
clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
23
-
<&cru PCLK_OTP_PHY>;
24
-
clock-names = "otp", "apb_pclk", "phy";
25
-
};
-3
Documentation/devicetree/bindings/nvmem/socionext,uniphier-efuse.yaml
-3
Documentation/devicetree/bindings/nvmem/socionext,uniphier-efuse.yaml
-6
Documentation/devicetree/bindings/nvmem/sunplus,sp7021-ocotp.yaml
-6
Documentation/devicetree/bindings/nvmem/sunplus,sp7021-ocotp.yaml
+1
Documentation/driver-api/driver-model/devres.rst
+1
Documentation/driver-api/driver-model/devres.rst
+1
-1
Documentation/fault-injection/provoke-crashes.rst
+1
-1
Documentation/fault-injection/provoke-crashes.rst
···
29
29
cpoint_name
30
30
Where in the kernel to trigger the action. It can be
31
31
one of INT_HARDWARE_ENTRY, INT_HW_IRQ_EN, INT_TASKLET_ENTRY,
32
-
FS_DEVRW, MEM_SWAPOUT, TIMERADD, SCSI_QUEUE_RQ, or DIRECT.
32
+
FS_SUBMIT_BH, MEM_SWAPOUT, TIMERADD, SCSI_QUEUE_RQ, or DIRECT.
33
33
34
34
cpoint_type
35
35
Indicates the action to be taken on hitting the crash point.
+1
Documentation/misc-devices/index.rst
+1
Documentation/misc-devices/index.rst
+87
Documentation/misc-devices/tps6594-pfsm.rst
+87
Documentation/misc-devices/tps6594-pfsm.rst
···
1
+
.. SPDX-License-Identifier: GPL-2.0
2
+
3
+
=====================================
4
+
Texas Instruments TPS6594 PFSM driver
5
+
=====================================
6
+
7
+
Author: Julien Panis (jpanis@baylibre.com)
8
+
9
+
Overview
10
+
========
11
+
12
+
Strictly speaking, PFSM (Pre-configurable Finite State Machine) is not
13
+
hardware. It is a piece of code.
14
+
15
+
The TPS6594 PMIC (Power Management IC) integrates a state machine which
16
+
manages operational modes. Depending on the current operational mode,
17
+
some voltage domains remain energized while others can be off.
18
+
19
+
The PFSM driver can be used to trigger transitions between configured
20
+
states. It also provides R/W access to the device registers.
21
+
22
+
Supported chips
23
+
---------------
24
+
25
+
- tps6594-q1
26
+
- tps6593-q1
27
+
- lp8764-q1
28
+
29
+
Driver location
30
+
===============
31
+
32
+
drivers/misc/tps6594-pfsm.c
33
+
34
+
Driver type definitions
35
+
=======================
36
+
37
+
include/uapi/linux/tps6594_pfsm.h
38
+
39
+
Driver IOCTLs
40
+
=============
41
+
42
+
:c:macro::`PMIC_GOTO_STANDBY`
43
+
All device resources are powered down. The processor is off, and
44
+
no voltage domains are energized.
45
+
46
+
:c:macro::`PMIC_GOTO_LP_STANDBY`
47
+
The digital and analog functions of the PMIC, which are not
48
+
required to be always-on, are turned off (low-power).
49
+
50
+
:c:macro::`PMIC_UPDATE_PGM`
51
+
Triggers a firmware update.
52
+
53
+
:c:macro::`PMIC_SET_ACTIVE_STATE`
54
+
One of the operational modes.
55
+
The PMICs are fully functional and supply power to all PDN loads.
56
+
All voltage domains are energized in both MCU and Main processor
57
+
sections.
58
+
59
+
:c:macro::`PMIC_SET_MCU_ONLY_STATE`
60
+
One of the operational modes.
61
+
Only the power resources assigned to the MCU Safety Island are on.
62
+
63
+
:c:macro::`PMIC_SET_RETENTION_STATE`
64
+
One of the operational modes.
65
+
Depending on the triggers set, some DDR/GPIO voltage domains can
66
+
remain energized, while all other domains are off to minimize
67
+
total system power.
68
+
69
+
Driver usage
70
+
============
71
+
72
+
See available PFSMs::
73
+
74
+
# ls /dev/pfsm*
75
+
76
+
Dump the registers of pages 0 and 1::
77
+
78
+
# hexdump -C /dev/pfsm-0-0x48
79
+
80
+
See PFSM events::
81
+
82
+
# cat /proc/interrupts
83
+
84
+
Userspace code example
85
+
----------------------
86
+
87
+
samples/pfsm/pfsm-wakeup.c
+32
Documentation/trace/coresight/coresight-dummy.rst
+32
Documentation/trace/coresight/coresight-dummy.rst
···
1
+
.. SPDX-License-Identifier: GPL-2.0
2
+
3
+
=============================
4
+
Coresight Dummy Trace Module
5
+
=============================
6
+
7
+
:Author: Hao Zhang <quic_hazha@quicinc.com>
8
+
:Date: June 2023
9
+
10
+
Introduction
11
+
------------
12
+
13
+
The Coresight dummy trace module is for the specific devices that kernel don't
14
+
have permission to access or configure, e.g., CoreSight TPDMs on Qualcomm
15
+
platforms. For these devices, a dummy driver is needed to register them as
16
+
Coresight devices. The module may also be used to define components that may
17
+
not have any programming interfaces, so that paths can be created in the driver.
18
+
It provides Coresight API for operations on dummy devices, such as enabling and
19
+
disabling them. It also provides the Coresight dummy sink/source paths for
20
+
debugging.
21
+
22
+
Config details
23
+
--------------
24
+
25
+
There are two types of nodes, dummy sink and dummy source. These nodes
26
+
are available at ``/sys/bus/coresight/devices``.
27
+
28
+
Example output::
29
+
30
+
$ ls -l /sys/bus/coresight/devices | grep dummy
31
+
dummy_sink0 -> ../../../devices/platform/soc@0/soc@0:sink/dummy_sink0
32
+
dummy_source0 -> ../../../devices/platform/soc@0/soc@0:source/dummy_source0
+9
-3
Documentation/trace/hisi-ptt.rst
+9
-3
Documentation/trace/hisi-ptt.rst
···
148
148
value will be 0x00101. If the desired filter is Root Port 0000:00:10.0 then
149
149
then filter value is calculated as 0x80001.
150
150
151
+
The driver also presents every supported Root Port and Requester filter through
152
+
sysfs. Each filter will be an individual file with name of its related PCIe
153
+
device name (domain:bus:device.function). The files of Root Port filters are
154
+
under $(PTT PMU dir)/root_port_filters and files of Requester filters
155
+
are under $(PTT PMU dir)/requester_filters.
156
+
151
157
Note that multiple Root Ports can be specified at one time, but only one
152
158
Endpoint function can be specified in one trace. Specifying both Root Port
153
159
and function at the same time is not supported. Driver maintains a list of
154
160
available filters and will check the invalid inputs.
155
161
156
-
Currently the available filters are detected in driver's probe. If the supported
157
-
devices are removed/added after probe, you may need to reload the driver to update
158
-
the filters.
162
+
The available filters will be dynamically updated, which means you will always
163
+
get correct filter information when hotplug events happen, or when you manually
164
+
remove/rescan the devices.
159
165
160
166
2. Type
161
167
-------
+1
Documentation/userspace-api/ioctl/ioctl-number.rst
+1
Documentation/userspace-api/ioctl/ioctl-number.rst
···
180
180
'P' 00-0F drivers/usb/class/usblp.c conflict!
181
181
'P' 01-09 drivers/misc/pci_endpoint_test.c conflict!
182
182
'P' 00-0F xen/privcmd.h conflict!
183
+
'P' 00-05 linux/tps6594_pfsm.h conflict!
183
184
'Q' all linux/soundcard.h
184
185
'R' 00-1F linux/random.h conflict!
185
186
'R' 01 linux/rfkill.h conflict!
+24
-1
MAINTAINERS
+24
-1
MAINTAINERS
···
2103
2103
ARM/CORESIGHT FRAMEWORK AND DRIVERS
2104
2104
M: Suzuki K Poulose <suzuki.poulose@arm.com>
2105
2105
R: Mike Leach <mike.leach@linaro.org>
2106
+
R: James Clark <james.clark@arm.com>
2106
2107
R: Leo Yan <leo.yan@linaro.org>
2107
2108
L: coresight@lists.linaro.org (moderated for non-subscribers)
2108
2109
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
···
9491
9490
F: mm/hmm*
9492
9491
F: tools/testing/selftests/mm/*hmm*
9493
9492
9493
+
HONEYWELL MPRLS0025PA PRESSURE SENSOR SERIES IIO DRIVER
9494
+
M: Andreas Klinger <ak@it-klinger.de>
9495
+
L: linux-iio@vger.kernel.org
9496
+
S: Maintained
9497
+
F: Documentation/devicetree/bindings/iio/pressure/honeywell,mprls0025pa.yaml
9498
+
F: drivers/iio/pressure/mprls0025pa.c
9499
+
9494
9500
HOST AP DRIVER
9495
9501
M: Jouni Malinen <j@w1.fi>
9496
9502
L: linux-wireless@vger.kernel.org
···
10341
10333
L: linux-fbdev@vger.kernel.org
10342
10334
S: Maintained
10343
10335
F: drivers/video/fbdev/i810/
10336
+
10337
+
INTEL 8254 COUNTER DRIVER
10338
+
M: William Breathitt Gray <william.gray@linaro.org>
10339
+
L: linux-iio@vger.kernel.org
10340
+
S: Maintained
10341
+
F: drivers/counter/i8254.c
10342
+
F: include/linux/i8254.h
10344
10343
10345
10344
INTEL 8255 GPIO DRIVER
10346
10345
M: William Breathitt Gray <william.gray@linaro.org>
···
18201
18186
F: Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml
18202
18187
F: drivers/clk/clk-versaclock7.c
18203
18188
18189
+
RENESAS X9250 DIGITAL POTENTIOMETERS DRIVER
18190
+
M: Herve Codina <herve.codina@bootlin.com>
18191
+
L: linux-iio@vger.kernel.org
18192
+
S: Maintained
18193
+
F: Documentation/devicetree/bindings/iio/potentiometer/renesas,x9250.yaml
18194
+
F: drivers/iio/potentiometer/x9250.c
18195
+
18204
18196
RESET CONTROLLER FRAMEWORK
18205
18197
M: Philipp Zabel <p.zabel@pengutronix.de>
18206
18198
S: Maintained
···
18420
18398
F: Documentation/devicetree/bindings/iio/light/bh1750.yaml
18421
18399
F: drivers/iio/light/bh1750.c
18422
18400
18423
-
ROHM BU27034 AMBIENT LIGHT SENSOR DRIVER
18401
+
ROHM BU270xx LIGHT SENSOR DRIVERs
18424
18402
M: Matti Vaittinen <mazziesaccount@gmail.com>
18425
18403
L: linux-iio@vger.kernel.org
18426
18404
S: Supported
18405
+
F: drivers/iio/light/rohm-bu27008.c
18427
18406
F: drivers/iio/light/rohm-bu27034.c
18428
18407
18429
18408
ROHM MULTIFUNCTION BD9571MWV-M PMIC DEVICE DRIVERS
+1
drivers/accessibility/speakup/Kconfig
+1
drivers/accessibility/speakup/Kconfig
+1
-1
drivers/accessibility/speakup/main.c
+1
-1
drivers/accessibility/speakup/main.c
···
1287
1287
[PUNC_LEVEL_ID] = { PUNC_LEVEL, .u.n = {NULL, 1, 0, 4, 0, 0, NULL} },
1288
1288
[READING_PUNC_ID] = { READING_PUNC, .u.n = {NULL, 1, 0, 4, 0, 0, NULL} },
1289
1289
[CURSOR_TIME_ID] = { CURSOR_TIME, .u.n = {NULL, 120, 50, 600, 0, 0, NULL} },
1290
-
[SAY_CONTROL_ID] { SAY_CONTROL, TOGGLE_0},
1290
+
[SAY_CONTROL_ID] = { SAY_CONTROL, TOGGLE_0},
1291
1291
[SAY_WORD_CTL_ID] = {SAY_WORD_CTL, TOGGLE_0},
1292
1292
[NO_INTERRUPT_ID] = { NO_INTERRUPT, TOGGLE_0},
1293
1293
[KEY_ECHO_ID] = { KEY_ECHO, .u.n = {NULL, 1, 0, 2, 0, 0, NULL} },
+11
-4
drivers/android/binder.c
+11
-4
drivers/android/binder.c
···
66
66
#include <linux/syscalls.h>
67
67
#include <linux/task_work.h>
68
68
#include <linux/sizes.h>
69
+
#include <linux/ktime.h>
69
70
70
71
#include <uapi/linux/android/binder.h>
71
72
···
2919
2918
binder_size_t last_fixup_min_off = 0;
2920
2919
struct binder_context *context = proc->context;
2921
2920
int t_debug_id = atomic_inc_return(&binder_last_id);
2921
+
ktime_t t_start_time = ktime_get();
2922
2922
char *secctx = NULL;
2923
2923
u32 secctx_sz = 0;
2924
2924
struct list_head sgc_head;
···
3161
3159
binder_stats_created(BINDER_STAT_TRANSACTION_COMPLETE);
3162
3160
3163
3161
t->debug_id = t_debug_id;
3162
+
t->start_time = t_start_time;
3164
3163
3165
3164
if (reply)
3166
3165
binder_debug(BINDER_DEBUG_TRANSACTION,
···
3186
3183
t->from = thread;
3187
3184
else
3188
3185
t->from = NULL;
3186
+
t->from_pid = proc->pid;
3187
+
t->from_tid = thread->pid;
3189
3188
t->sender_euid = task_euid(proc->tsk);
3190
3189
t->to_proc = target_proc;
3191
3190
t->to_thread = target_thread;
···
5949
5944
{
5950
5945
struct binder_proc *to_proc;
5951
5946
struct binder_buffer *buffer = t->buffer;
5947
+
ktime_t current_time = ktime_get();
5952
5948
5953
5949
spin_lock(&t->lock);
5954
5950
to_proc = t->to_proc;
5955
5951
seq_printf(m,
5956
-
"%s %d: %pK from %d:%d to %d:%d code %x flags %x pri %ld r%d",
5952
+
"%s %d: %pK from %d:%d to %d:%d code %x flags %x pri %ld r%d elapsed %lldms",
5957
5953
prefix, t->debug_id, t,
5958
-
t->from ? t->from->proc->pid : 0,
5959
-
t->from ? t->from->pid : 0,
5954
+
t->from_pid,
5955
+
t->from_tid,
5960
5956
to_proc ? to_proc->pid : 0,
5961
5957
t->to_thread ? t->to_thread->pid : 0,
5962
-
t->code, t->flags, t->priority, t->need_reply);
5958
+
t->code, t->flags, t->priority, t->need_reply,
5959
+
ktime_ms_delta(current_time, t->start_time));
5963
5960
spin_unlock(&t->lock);
5964
5961
5965
5962
if (proc != to_proc) {
+3
drivers/android/binder_internal.h
+3
drivers/android/binder_internal.h
···
515
515
int debug_id;
516
516
struct binder_work work;
517
517
struct binder_thread *from;
518
+
pid_t from_pid;
519
+
pid_t from_tid;
518
520
struct binder_transaction *from_parent;
519
521
struct binder_proc *to_proc;
520
522
struct binder_thread *to_thread;
···
530
528
long priority;
531
529
long saved_priority;
532
530
kuid_t sender_euid;
531
+
ktime_t start_time;
533
532
struct list_head fd_fixups;
534
533
binder_uintptr_t security_ctx;
535
534
/**
+6
drivers/bus/fsl-mc/dprc-driver.c
+6
drivers/bus/fsl-mc/dprc-driver.c
···
45
45
struct fsl_mc_child_objs *objs;
46
46
struct fsl_mc_device *mc_dev;
47
47
48
+
if (!dev_is_fsl_mc(dev))
49
+
return 0;
50
+
48
51
mc_dev = to_fsl_mc_device(dev);
49
52
objs = data;
50
53
···
67
64
68
65
static int __fsl_mc_device_remove(struct device *dev, void *data)
69
66
{
67
+
if (!dev_is_fsl_mc(dev))
68
+
return 0;
69
+
70
70
fsl_mc_device_remove(to_fsl_mc_device(dev));
71
71
return 0;
72
72
}
+18
drivers/cdx/cdx.c
+18
drivers/cdx/cdx.c
···
62
62
#include <linux/mm.h>
63
63
#include <linux/xarray.h>
64
64
#include <linux/cdx/cdx_bus.h>
65
+
#include <linux/iommu.h>
66
+
#include <linux/dma-map-ops.h>
65
67
#include "cdx.h"
66
68
67
69
/* Default DMA mask for devices on a CDX bus */
···
259
257
260
258
static int cdx_dma_configure(struct device *dev)
261
259
{
260
+
struct cdx_driver *cdx_drv = to_cdx_driver(dev->driver);
262
261
struct cdx_device *cdx_dev = to_cdx_device(dev);
263
262
u32 input_id = cdx_dev->req_id;
264
263
int ret;
···
270
267
return ret;
271
268
}
272
269
270
+
if (!ret && !cdx_drv->driver_managed_dma) {
271
+
ret = iommu_device_use_default_domain(dev);
272
+
if (ret)
273
+
arch_teardown_dma_ops(dev);
274
+
}
275
+
273
276
return 0;
277
+
}
278
+
279
+
static void cdx_dma_cleanup(struct device *dev)
280
+
{
281
+
struct cdx_driver *cdx_drv = to_cdx_driver(dev->driver);
282
+
283
+
if (!cdx_drv->driver_managed_dma)
284
+
iommu_device_unuse_default_domain(dev);
274
285
}
275
286
276
287
/* show configuration fields */
···
422
405
.remove = cdx_remove,
423
406
.shutdown = cdx_shutdown,
424
407
.dma_configure = cdx_dma_configure,
408
+
.dma_cleanup = cdx_dma_cleanup,
425
409
.bus_groups = cdx_bus_groups,
426
410
.dev_groups = cdx_dev_groups,
427
411
};
-10
drivers/cdx/controller/Kconfig
-10
drivers/cdx/controller/Kconfig
+9
-77
drivers/cdx/controller/mcdi.c
+9
-77
drivers/cdx/controller/mcdi.c
···
31
31
struct cdx_dword buffer[DIV_ROUND_UP(MCDI_CTL_SDU_LEN_MAX, 4)];
32
32
};
33
33
34
-
#ifdef CONFIG_MCDI_LOGGING
35
-
#define LOG_LINE_MAX (1024 - 32)
36
-
#endif
37
-
38
34
static void cdx_mcdi_cancel_cmd(struct cdx_mcdi *cdx, struct cdx_mcdi_cmd *cmd);
39
35
static void cdx_mcdi_wait_for_cleanup(struct cdx_mcdi *cdx);
40
36
static int cdx_mcdi_rpc_async_internal(struct cdx_mcdi *cdx,
···
115
119
mcdi = cdx_mcdi_if(cdx);
116
120
mcdi->cdx = cdx;
117
121
118
-
#ifdef CONFIG_MCDI_LOGGING
119
-
mcdi->logging_buffer = kmalloc(LOG_LINE_MAX, GFP_KERNEL);
120
-
if (!mcdi->logging_buffer)
121
-
goto fail2;
122
-
#endif
123
122
mcdi->workqueue = alloc_ordered_workqueue("mcdi_wq", 0);
124
123
if (!mcdi->workqueue)
125
-
goto fail3;
124
+
goto fail2;
126
125
mutex_init(&mcdi->iface_lock);
127
126
mcdi->mode = MCDI_MODE_EVENTS;
128
127
INIT_LIST_HEAD(&mcdi->cmd_list);
···
126
135
mcdi->new_epoch = true;
127
136
128
137
return 0;
129
-
fail3:
130
-
#ifdef CONFIG_MCDI_LOGGING
131
-
kfree(mcdi->logging_buffer);
132
138
fail2:
133
-
#endif
134
139
kfree(cdx->mcdi);
135
140
cdx->mcdi = NULL;
136
141
fail:
···
142
155
return;
143
156
144
157
cdx_mcdi_wait_for_cleanup(cdx);
145
-
146
-
#ifdef CONFIG_MCDI_LOGGING
147
-
kfree(mcdi->logging_buffer);
148
-
#endif
149
158
150
159
destroy_workqueue(mcdi->workqueue);
151
160
kfree(cdx->mcdi);
···
229
246
size_t hdr_len;
230
247
bool not_epoch;
231
248
u32 xflags;
232
-
#ifdef CONFIG_MCDI_LOGGING
233
-
char *buf;
234
-
#endif
235
249
236
250
if (!mcdi)
237
251
return;
238
-
#ifdef CONFIG_MCDI_LOGGING
239
-
buf = mcdi->logging_buffer; /* page-sized */
240
-
#endif
241
252
242
253
mcdi->prev_seq = cmd->seq;
243
254
mcdi->seq_held_by[cmd->seq] = cmd;
···
258
281
MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_PLATFORM);
259
282
hdr_len = 8;
260
283
261
-
#ifdef CONFIG_MCDI_LOGGING
262
-
if (!WARN_ON_ONCE(!buf)) {
263
-
const struct cdx_dword *frags[] = { hdr, inbuf };
264
-
const size_t frag_len[] = { hdr_len, round_up(inlen, 4) };
265
-
int bytes = 0;
266
-
int i, j;
267
-
268
-
for (j = 0; j < ARRAY_SIZE(frags); j++) {
269
-
const struct cdx_dword *frag;
270
-
271
-
frag = frags[j];
272
-
for (i = 0;
273
-
i < frag_len[j] / 4;
274
-
i++) {
275
-
/*
276
-
* Do not exceed the internal printk limit.
277
-
* The string before that is just over 70 bytes.
278
-
*/
279
-
if ((bytes + 75) > LOG_LINE_MAX) {
280
-
pr_info("MCDI RPC REQ:%s \\\n", buf);
281
-
bytes = 0;
282
-
}
283
-
bytes += snprintf(buf + bytes,
284
-
LOG_LINE_MAX - bytes, " %08x",
285
-
le32_to_cpu(frag[i].cdx_u32));
286
-
}
287
-
}
288
-
289
-
pr_info("MCDI RPC REQ:%s\n", buf);
290
-
}
291
-
#endif
292
284
hdr[0].cdx_u32 |= (__force __le32)(cdx_mcdi_payload_csum(hdr, hdr_len, inbuf, inlen) <<
293
285
MCDI_HEADER_XFLAGS_LBN);
286
+
287
+
print_hex_dump_debug("MCDI REQ HEADER: ", DUMP_PREFIX_NONE, 32, 4, hdr, hdr_len, false);
288
+
print_hex_dump_debug("MCDI REQ PAYLOAD: ", DUMP_PREFIX_NONE, 32, 4, inbuf, inlen, false);
289
+
294
290
cdx->mcdi_ops->mcdi_request(cdx, hdr, hdr_len, inbuf, inlen);
295
291
296
292
mcdi->new_epoch = false;
···
650
700
resp_data_len = 0;
651
701
}
652
702
653
-
#ifdef CONFIG_MCDI_LOGGING
654
-
if (!WARN_ON_ONCE(!mcdi->logging_buffer)) {
655
-
char *log = mcdi->logging_buffer;
656
-
int i, bytes = 0;
657
-
size_t rlen;
658
-
659
-
WARN_ON_ONCE(resp_hdr_len % 4);
660
-
661
-
rlen = resp_hdr_len / 4 + DIV_ROUND_UP(resp_data_len, 4);
662
-
663
-
for (i = 0; i < rlen; i++) {
664
-
if ((bytes + 75) > LOG_LINE_MAX) {
665
-
pr_info("MCDI RPC RESP:%s \\\n", log);
666
-
bytes = 0;
667
-
}
668
-
bytes += snprintf(log + bytes, LOG_LINE_MAX - bytes,
669
-
" %08x", le32_to_cpu(outbuf[i].cdx_u32));
670
-
}
671
-
672
-
pr_info("MCDI RPC RESP:%s\n", log);
673
-
}
674
-
#endif
703
+
print_hex_dump_debug("MCDI RESP HEADER: ", DUMP_PREFIX_NONE, 32, 4,
704
+
outbuf, resp_hdr_len, false);
705
+
print_hex_dump_debug("MCDI RESP PAYLOAD: ", DUMP_PREFIX_NONE, 32, 4,
706
+
outbuf + (resp_hdr_len / 4), resp_data_len, false);
675
707
676
708
if (error && resp_data_len == 0) {
677
709
/* MC rebooted during command */
-6
drivers/cdx/controller/mcdi.h
-6
drivers/cdx/controller/mcdi.h
···
153
153
* @mode: Poll for mcdi completion, or wait for an mcdi_event
154
154
* @prev_seq: The last used sequence number
155
155
* @new_epoch: Indicates start of day or start of MC reboot recovery
156
-
* @logging_buffer: Buffer that may be used to build MCDI tracing messages
157
-
* @logging_enabled: Whether to trace MCDI
158
156
*/
159
157
struct cdx_mcdi_iface {
160
158
struct cdx_mcdi *cdx;
···
168
170
enum cdx_mcdi_mode mode;
169
171
u8 prev_seq;
170
172
bool new_epoch;
171
-
#ifdef CONFIG_MCDI_LOGGING
172
-
bool logging_enabled;
173
-
char *logging_buffer;
174
-
#endif
175
173
};
176
174
177
175
/**
+2
-1
drivers/char/Kconfig
+2
-1
drivers/char/Kconfig
···
34
34
config PRINTER
35
35
tristate "Parallel printer support"
36
36
depends on PARPORT
37
+
depends on HAS_IOPORT || PARPORT_NOT_PC
37
38
help
38
39
If you intend to attach a printer to the parallel port of your Linux
39
40
box (as opposed to using a serial printer; if the connector at the
···
341
340
342
341
config DEVPORT
343
342
bool "/dev/port character device"
344
-
depends on ISA || PCI
343
+
depends on HAS_IOPORT
345
344
default y
346
345
help
347
346
Say Y here if you want to support the /dev/port device. The /dev/port
+10
-11
drivers/char/bsr.c
+10
-11
drivers/char/bsr.c
···
61
61
62
62
static unsigned total_bsr_devs;
63
63
static LIST_HEAD(bsr_devs);
64
-
static struct class *bsr_class;
65
64
static int bsr_major;
66
65
67
66
enum {
···
106
107
NULL,
107
108
};
108
109
ATTRIBUTE_GROUPS(bsr_dev);
110
+
111
+
static const struct class bsr_class = {
112
+
.name = "bsr",
113
+
.dev_groups = bsr_dev_groups,
114
+
};
109
115
110
116
static int bsr_mmap(struct file *filp, struct vm_area_struct *vma)
111
117
{
···
248
244
goto out_err;
249
245
}
250
246
251
-
cur->bsr_device = device_create(bsr_class, NULL, cur->bsr_dev,
247
+
cur->bsr_device = device_create(&bsr_class, NULL, cur->bsr_dev,
252
248
cur, "%s", cur->bsr_name);
253
249
if (IS_ERR(cur->bsr_device)) {
254
250
printk(KERN_ERR "device_create failed for %s\n",
···
297
293
if (!np)
298
294
goto out_err;
299
295
300
-
bsr_class = class_create("bsr");
301
-
if (IS_ERR(bsr_class)) {
302
-
printk(KERN_ERR "class_create() failed for bsr_class\n");
303
-
ret = PTR_ERR(bsr_class);
296
+
ret = class_register(&bsr_class);
297
+
if (ret)
304
298
goto out_err_1;
305
-
}
306
-
bsr_class->dev_groups = bsr_dev_groups;
307
299
308
300
ret = alloc_chrdev_region(&bsr_dev, 0, BSR_MAX_DEVS, "bsr");
309
301
bsr_major = MAJOR(bsr_dev);
···
320
320
unregister_chrdev_region(bsr_dev, BSR_MAX_DEVS);
321
321
322
322
out_err_2:
323
-
class_destroy(bsr_class);
323
+
class_unregister(&bsr_class);
324
324
325
325
out_err_1:
326
326
of_node_put(np);
···
335
335
336
336
bsr_cleanup_devs();
337
337
338
-
if (bsr_class)
339
-
class_destroy(bsr_class);
338
+
class_unregister(&bsr_class);
340
339
341
340
if (bsr_major)
342
341
unregister_chrdev_region(MKDEV(bsr_major, 0), BSR_MAX_DEVS);
+9
-9
drivers/char/dsp56k.c
+9
-9
drivers/char/dsp56k.c
···
101
101
int tx_wsize, rx_wsize;
102
102
} dsp56k;
103
103
104
-
static struct class *dsp56k_class;
104
+
static const struct class dsp56k_class = {
105
+
.name = "dsp56k",
106
+
};
105
107
106
108
static int dsp56k_reset(void)
107
109
{
···
495
493
496
494
static int __init dsp56k_init_driver(void)
497
495
{
498
-
int err = 0;
496
+
int err;
499
497
500
498
if(!MACH_IS_ATARI || !ATARIHW_PRESENT(DSP56K)) {
501
499
printk("DSP56k driver: Hardware not present\n");
···
506
504
printk("DSP56k driver: Unable to register driver\n");
507
505
return -ENODEV;
508
506
}
509
-
dsp56k_class = class_create("dsp56k");
510
-
if (IS_ERR(dsp56k_class)) {
511
-
err = PTR_ERR(dsp56k_class);
507
+
err = class_register(&dsp56k_class);
508
+
if (err)
512
509
goto out_chrdev;
513
-
}
514
-
device_create(dsp56k_class, NULL, MKDEV(DSP56K_MAJOR, 0), NULL,
510
+
device_create(&dsp56k_class, NULL, MKDEV(DSP56K_MAJOR, 0), NULL,
515
511
"dsp56k");
516
512
517
513
printk(banner);
···
524
524
525
525
static void __exit dsp56k_cleanup_driver(void)
526
526
{
527
-
device_destroy(dsp56k_class, MKDEV(DSP56K_MAJOR, 0));
528
-
class_destroy(dsp56k_class);
527
+
device_destroy(&dsp56k_class, MKDEV(DSP56K_MAJOR, 0));
528
+
class_unregister(&dsp56k_class);
529
529
unregister_chrdev(DSP56K_MAJOR, "dsp56k");
530
530
}
531
531
module_exit(dsp56k_cleanup_driver);
+9
-9
drivers/char/lp.c
+9
-9
drivers/char/lp.c
···
145
145
static int port_num[LP_NO];
146
146
147
147
static unsigned int lp_count = 0;
148
-
static struct class *lp_class;
148
+
static const struct class lp_class = {
149
+
.name = "printer",
150
+
};
149
151
150
152
#ifdef CONFIG_LP_CONSOLE
151
153
static struct parport *console_registered;
···
934
932
if (reset)
935
933
lp_reset(nr);
936
934
937
-
device_create(lp_class, port->dev, MKDEV(LP_MAJOR, nr), NULL,
935
+
device_create(&lp_class, port->dev, MKDEV(LP_MAJOR, nr), NULL,
938
936
"lp%d", nr);
939
937
940
938
printk(KERN_INFO "lp%d: using %s (%s).\n", nr, port->name,
···
1006
1004
if (port_num[n] == port->number) {
1007
1005
port_num[n] = -1;
1008
1006
lp_count--;
1009
-
device_destroy(lp_class, MKDEV(LP_MAJOR, n));
1007
+
device_destroy(&lp_class, MKDEV(LP_MAJOR, n));
1010
1008
parport_unregister_device(lp_table[n].dev);
1011
1009
}
1012
1010
}
···
1051
1049
return -EIO;
1052
1050
}
1053
1051
1054
-
lp_class = class_create("printer");
1055
-
if (IS_ERR(lp_class)) {
1056
-
err = PTR_ERR(lp_class);
1052
+
err = class_register(&lp_class);
1053
+
if (err)
1057
1054
goto out_reg;
1058
-
}
1059
1055
1060
1056
if (parport_register_driver(&lp_driver)) {
1061
1057
printk(KERN_ERR "lp: unable to register with parport\n");
···
1072
1072
return 0;
1073
1073
1074
1074
out_class:
1075
-
class_destroy(lp_class);
1075
+
class_unregister(&lp_class);
1076
1076
out_reg:
1077
1077
unregister_chrdev(LP_MAJOR, "lp");
1078
1078
return err;
···
1115
1115
#endif
1116
1116
1117
1117
unregister_chrdev(LP_MAJOR, "lp");
1118
-
class_destroy(lp_class);
1118
+
class_unregister(&lp_class);
1119
1119
}
1120
1120
1121
1121
__setup("lp=", lp_setup);
+9
-6
drivers/char/mem.c
+9
-6
drivers/char/mem.c
···
746
746
return NULL;
747
747
}
748
748
749
-
static struct class *mem_class;
749
+
static const struct class mem_class = {
750
+
.name = "mem",
751
+
.devnode = mem_devnode,
752
+
};
750
753
751
754
static int __init chr_dev_init(void)
752
755
{
756
+
int retval;
753
757
int minor;
754
758
755
759
if (register_chrdev(MEM_MAJOR, "mem", &memory_fops))
756
760
printk("unable to get major %d for memory devs\n", MEM_MAJOR);
757
761
758
-
mem_class = class_create("mem");
759
-
if (IS_ERR(mem_class))
760
-
return PTR_ERR(mem_class);
762
+
retval = class_register(&mem_class);
763
+
if (retval)
764
+
return retval;
761
765
762
-
mem_class->devnode = mem_devnode;
763
766
for (minor = 1; minor < ARRAY_SIZE(devlist); minor++) {
764
767
if (!devlist[minor].name)
765
768
continue;
···
773
770
if ((minor == DEVPORT_MINOR) && !arch_has_dev_port())
774
771
continue;
775
772
776
-
device_create(mem_class, NULL, MKDEV(MEM_MAJOR, minor),
773
+
device_create(&mem_class, NULL, MKDEV(MEM_MAJOR, minor),
777
774
NULL, devlist[minor].name);
778
775
}
779
776
+20
-19
drivers/char/misc.c
+20
-19
drivers/char/misc.c
···
168
168
return err;
169
169
}
170
170
171
-
static struct class *misc_class;
171
+
static char *misc_devnode(const struct device *dev, umode_t *mode)
172
+
{
173
+
const struct miscdevice *c = dev_get_drvdata(dev);
174
+
175
+
if (mode && c->mode)
176
+
*mode = c->mode;
177
+
if (c->nodename)
178
+
return kstrdup(c->nodename, GFP_KERNEL);
179
+
return NULL;
180
+
}
181
+
182
+
static const struct class misc_class = {
183
+
.name = "misc",
184
+
.devnode = misc_devnode,
185
+
};
172
186
173
187
static const struct file_operations misc_fops = {
174
188
.owner = THIS_MODULE,
···
240
226
dev = MKDEV(MISC_MAJOR, misc->minor);
241
227
242
228
misc->this_device =
243
-
device_create_with_groups(misc_class, misc->parent, dev,
229
+
device_create_with_groups(&misc_class, misc->parent, dev,
244
230
misc, misc->groups, "%s", misc->name);
245
231
if (IS_ERR(misc->this_device)) {
246
232
if (is_dynamic) {
···
277
263
278
264
mutex_lock(&misc_mtx);
279
265
list_del(&misc->list);
280
-
device_destroy(misc_class, MKDEV(MISC_MAJOR, misc->minor));
266
+
device_destroy(&misc_class, MKDEV(MISC_MAJOR, misc->minor));
281
267
misc_minor_free(misc->minor);
282
268
mutex_unlock(&misc_mtx);
283
269
}
284
270
EXPORT_SYMBOL(misc_deregister);
285
-
286
-
static char *misc_devnode(const struct device *dev, umode_t *mode)
287
-
{
288
-
const struct miscdevice *c = dev_get_drvdata(dev);
289
-
290
-
if (mode && c->mode)
291
-
*mode = c->mode;
292
-
if (c->nodename)
293
-
return kstrdup(c->nodename, GFP_KERNEL);
294
-
return NULL;
295
-
}
296
271
297
272
static int __init misc_init(void)
298
273
{
···
289
286
struct proc_dir_entry *ret;
290
287
291
288
ret = proc_create_seq("misc", 0, NULL, &misc_seq_ops);
292
-
misc_class = class_create("misc");
293
-
err = PTR_ERR(misc_class);
294
-
if (IS_ERR(misc_class))
289
+
err = class_register(&misc_class);
290
+
if (err)
295
291
goto fail_remove;
296
292
297
293
err = -EIO;
298
294
if (register_chrdev(MISC_MAJOR, "misc", &misc_fops))
299
295
goto fail_printk;
300
-
misc_class->devnode = misc_devnode;
301
296
return 0;
302
297
303
298
fail_printk:
304
299
pr_err("unable to get major %d for misc devices\n", MISC_MAJOR);
305
-
class_destroy(misc_class);
300
+
class_unregister(&misc_class);
306
301
fail_remove:
307
302
if (ret)
308
303
remove_proc_entry("misc", NULL);
+10
-9
drivers/char/ppdev.c
+10
-9
drivers/char/ppdev.c
···
773
773
return mask;
774
774
}
775
775
776
-
static struct class *ppdev_class;
776
+
static const struct class ppdev_class = {
777
+
.name = CHRDEV,
778
+
};
777
779
778
780
static const struct file_operations pp_fops = {
779
781
.owner = THIS_MODULE,
···
796
794
if (devices[port->number])
797
795
return;
798
796
799
-
ret = device_create(ppdev_class, port->dev,
797
+
ret = device_create(&ppdev_class, port->dev,
800
798
MKDEV(PP_MAJOR, port->number), NULL,
801
799
"parport%d", port->number);
802
800
if (IS_ERR(ret)) {
···
812
810
if (!devices[port->number])
813
811
return;
814
812
815
-
device_destroy(ppdev_class, MKDEV(PP_MAJOR, port->number));
813
+
device_destroy(&ppdev_class, MKDEV(PP_MAJOR, port->number));
816
814
devices[port->number] = NULL;
817
815
}
818
816
···
843
841
pr_warn(CHRDEV ": unable to get major %d\n", PP_MAJOR);
844
842
return -EIO;
845
843
}
846
-
ppdev_class = class_create(CHRDEV);
847
-
if (IS_ERR(ppdev_class)) {
848
-
err = PTR_ERR(ppdev_class);
844
+
err = class_register(&ppdev_class);
845
+
if (err)
849
846
goto out_chrdev;
850
-
}
847
+
851
848
err = parport_register_driver(&pp_driver);
852
849
if (err < 0) {
853
850
pr_warn(CHRDEV ": unable to register with parport\n");
···
857
856
goto out;
858
857
859
858
out_class:
860
-
class_destroy(ppdev_class);
859
+
class_unregister(&ppdev_class);
861
860
out_chrdev:
862
861
unregister_chrdev(PP_MAJOR, CHRDEV);
863
862
out:
···
868
867
{
869
868
/* Clean up all parport stuff */
870
869
parport_unregister_driver(&pp_driver);
871
-
class_destroy(ppdev_class);
870
+
class_unregister(&ppdev_class);
872
871
unregister_chrdev(PP_MAJOR, CHRDEV);
873
872
}
874
873
+11
-13
drivers/char/virtio_console.c
+11
-13
drivers/char/virtio_console.c
···
40
40
* across multiple devices and multiple ports per device.
41
41
*/
42
42
struct ports_driver_data {
43
-
/* Used for registering chardevs */
44
-
struct class *class;
45
-
46
43
/* Used for exporting per-port information to debugfs */
47
44
struct dentry *debugfs_dir;
48
45
···
51
54
};
52
55
53
56
static struct ports_driver_data pdrvdata;
57
+
58
+
static const struct class port_class = {
59
+
.name = "virtio-ports",
60
+
};
54
61
55
62
static DEFINE_SPINLOCK(pdrvdata_lock);
56
63
static DECLARE_COMPLETION(early_console_added);
···
1400
1399
"Error %d adding cdev for port %u\n", err, id);
1401
1400
goto free_cdev;
1402
1401
}
1403
-
port->dev = device_create(pdrvdata.class, &port->portdev->vdev->dev,
1402
+
port->dev = device_create(&port_class, &port->portdev->vdev->dev,
1404
1403
devt, port, "vport%up%u",
1405
1404
port->portdev->vdev->index, id);
1406
1405
if (IS_ERR(port->dev)) {
···
1466
1465
1467
1466
free_inbufs:
1468
1467
free_device:
1469
-
device_destroy(pdrvdata.class, port->dev->devt);
1468
+
device_destroy(&port_class, port->dev->devt);
1470
1469
free_cdev:
1471
1470
cdev_del(port->cdev);
1472
1471
free_port:
···
1541
1540
port->portdev = NULL;
1542
1541
1543
1542
sysfs_remove_group(&port->dev->kobj, &port_attribute_group);
1544
-
device_destroy(pdrvdata.class, port->dev->devt);
1543
+
device_destroy(&port_class, port->dev->devt);
1545
1544
cdev_del(port->cdev);
1546
1545
1547
1546
debugfs_remove(port->debugfs_file);
···
2245
2244
{
2246
2245
int err;
2247
2246
2248
-
pdrvdata.class = class_create("virtio-ports");
2249
-
if (IS_ERR(pdrvdata.class)) {
2250
-
err = PTR_ERR(pdrvdata.class);
2251
-
pr_err("Error %d creating virtio-ports class\n", err);
2247
+
err = class_register(&port_class);
2248
+
if (err)
2252
2249
return err;
2253
-
}
2254
2250
2255
2251
pdrvdata.debugfs_dir = debugfs_create_dir("virtio-ports", NULL);
2256
2252
INIT_LIST_HEAD(&pdrvdata.consoles);
···
2269
2271
unregister_virtio_driver(&virtio_console);
2270
2272
free:
2271
2273
debugfs_remove_recursive(pdrvdata.debugfs_dir);
2272
-
class_destroy(pdrvdata.class);
2274
+
class_unregister(&port_class);
2273
2275
return err;
2274
2276
}
2275
2277
···
2280
2282
unregister_virtio_driver(&virtio_console);
2281
2283
unregister_virtio_driver(&virtio_rproc_serial);
2282
2284
2283
-
class_destroy(pdrvdata.class);
2285
+
class_unregister(&port_class);
2284
2286
debugfs_remove_recursive(pdrvdata.debugfs_dir);
2285
2287
}
2286
2288
module_init(virtio_console_init);
+24
-28
drivers/char/xilinx_hwicap/xilinx_hwicap.c
+24
-28
drivers/char/xilinx_hwicap/xilinx_hwicap.c
···
113
113
static bool probed_devices[HWICAP_DEVICES];
114
114
static struct mutex icap_sem;
115
115
116
-
static struct class *icap_class;
116
+
static const struct class icap_class = {
117
+
.name = "xilinx_config",
118
+
};
117
119
118
120
#define UNIMPLEMENTED 0xFFFF
119
121
···
689
687
goto failed3;
690
688
}
691
689
692
-
device_create(icap_class, dev, devt, NULL, "%s%d", DRIVER_NAME, id);
690
+
device_create(&icap_class, dev, devt, NULL, "%s%d", DRIVER_NAME, id);
693
691
return 0; /* success */
694
692
695
693
failed3:
···
722
720
.get_status = fifo_icap_get_status,
723
721
.reset = fifo_icap_reset,
724
722
};
725
-
726
-
static int hwicap_remove(struct device *dev)
727
-
{
728
-
struct hwicap_drvdata *drvdata;
729
-
730
-
drvdata = dev_get_drvdata(dev);
731
-
732
-
if (!drvdata)
733
-
return 0;
734
-
735
-
device_destroy(icap_class, drvdata->devt);
736
-
cdev_del(&drvdata->cdev);
737
-
iounmap(drvdata->base_address);
738
-
release_mem_region(drvdata->mem_start, drvdata->mem_size);
739
-
kfree(drvdata);
740
-
741
-
mutex_lock(&icap_sem);
742
-
probed_devices[MINOR(dev->devt)-XHWICAP_MINOR] = 0;
743
-
mutex_unlock(&icap_sem);
744
-
return 0; /* success */
745
-
}
746
723
747
724
#ifdef CONFIG_OF
748
725
static int hwicap_of_probe(struct platform_device *op,
···
806
825
&buffer_icap_config, regs);
807
826
}
808
827
809
-
static int hwicap_drv_remove(struct platform_device *pdev)
828
+
static void hwicap_drv_remove(struct platform_device *pdev)
810
829
{
811
-
return hwicap_remove(&pdev->dev);
830
+
struct device *dev = &pdev->dev;
831
+
struct hwicap_drvdata *drvdata;
832
+
833
+
drvdata = dev_get_drvdata(dev);
834
+
835
+
device_destroy(&icap_class, drvdata->devt);
836
+
cdev_del(&drvdata->cdev);
837
+
iounmap(drvdata->base_address);
838
+
release_mem_region(drvdata->mem_start, drvdata->mem_size);
839
+
kfree(drvdata);
840
+
841
+
mutex_lock(&icap_sem);
842
+
probed_devices[MINOR(dev->devt)-XHWICAP_MINOR] = 0;
843
+
mutex_unlock(&icap_sem);
812
844
}
813
845
814
846
#ifdef CONFIG_OF
···
838
844
839
845
static struct platform_driver hwicap_platform_driver = {
840
846
.probe = hwicap_drv_probe,
841
-
.remove = hwicap_drv_remove,
847
+
.remove_new = hwicap_drv_remove,
842
848
.driver = {
843
849
.name = DRIVER_NAME,
844
850
.of_match_table = hwicap_of_match,
···
850
856
dev_t devt;
851
857
int retval;
852
858
853
-
icap_class = class_create("xilinx_config");
859
+
retval = class_register(&icap_class);
860
+
if (retval)
861
+
return retval;
854
862
mutex_init(&icap_sem);
855
863
856
864
devt = MKDEV(XHWICAP_MAJOR, XHWICAP_MINOR);
···
878
882
{
879
883
dev_t devt = MKDEV(XHWICAP_MAJOR, XHWICAP_MINOR);
880
884
881
-
class_destroy(icap_class);
885
+
class_unregister(&icap_class);
882
886
883
887
platform_driver_unregister(&hwicap_platform_driver);
884
888
+8
-13
drivers/char/xillybus/xillybus_class.c
+8
-13
drivers/char/xillybus/xillybus_class.c
···
23
23
24
24
static DEFINE_MUTEX(unit_mutex);
25
25
static LIST_HEAD(unit_list);
26
-
static struct class *xillybus_class;
26
+
static const struct class xillybus_class = {
27
+
.name = "xillybus",
28
+
};
27
29
28
30
#define UNITNAMELEN 16
29
31
···
123
121
len -= namelen + 1;
124
122
idt += namelen + 1;
125
123
126
-
device = device_create(xillybus_class,
124
+
device = device_create(&xillybus_class,
127
125
NULL,
128
126
MKDEV(unit->major,
129
127
i + unit->lowest_minor),
···
154
152
155
153
unroll_device_create:
156
154
for (i--; i >= 0; i--)
157
-
device_destroy(xillybus_class, MKDEV(unit->major,
155
+
device_destroy(&xillybus_class, MKDEV(unit->major,
158
156
i + unit->lowest_minor));
159
157
160
158
cdev_del(unit->cdev);
···
195
193
for (minor = unit->lowest_minor;
196
194
minor < (unit->lowest_minor + unit->num_nodes);
197
195
minor++)
198
-
device_destroy(xillybus_class, MKDEV(unit->major, minor));
196
+
device_destroy(&xillybus_class, MKDEV(unit->major, minor));
199
197
200
198
cdev_del(unit->cdev);
201
199
···
244
242
245
243
static int __init xillybus_class_init(void)
246
244
{
247
-
xillybus_class = class_create("xillybus");
248
-
249
-
if (IS_ERR(xillybus_class)) {
250
-
pr_warn("Failed to register xillybus class\n");
251
-
252
-
return PTR_ERR(xillybus_class);
253
-
}
254
-
return 0;
245
+
return class_register(&xillybus_class);
255
246
}
256
247
257
248
static void __exit xillybus_class_exit(void)
258
249
{
259
-
class_destroy(xillybus_class);
250
+
class_unregister(&xillybus_class);
260
251
}
261
252
262
253
module_init(xillybus_class_init);
+1
drivers/clk/qcom/Kconfig
+1
drivers/clk/qcom/Kconfig
+59
-1
drivers/clk/qcom/clk-cbf-8996.c
+59
-1
drivers/clk/qcom/clk-cbf-8996.c
···
5
5
#include <linux/bitfield.h>
6
6
#include <linux/clk.h>
7
7
#include <linux/clk-provider.h>
8
+
#include <linux/interconnect-clk.h>
9
+
#include <linux/interconnect-provider.h>
8
10
#include <linux/of.h>
9
11
#include <linux/module.h>
10
12
#include <linux/platform_device.h>
11
13
#include <linux/regmap.h>
14
+
15
+
#include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12
16
13
17
#include "clk-alpha-pll.h"
14
18
#include "clk-regmap.h"
···
227
223
.val_format_endian = REGMAP_ENDIAN_LITTLE,
228
224
};
229
225
226
+
#ifdef CONFIG_INTERCONNECT
227
+
228
+
/* Random ID that doesn't clash with main qnoc and OSM */
229
+
#define CBF_MASTER_NODE 2000
230
+
231
+
static int qcom_msm8996_cbf_icc_register(struct platform_device *pdev, struct clk_hw *cbf_hw)
232
+
{
233
+
struct device *dev = &pdev->dev;
234
+
struct clk *clk = devm_clk_hw_get_clk(dev, cbf_hw, "cbf");
235
+
const struct icc_clk_data data[] = {
236
+
{ .clk = clk, .name = "cbf", },
237
+
};
238
+
struct icc_provider *provider;
239
+
240
+
provider = icc_clk_register(dev, CBF_MASTER_NODE, ARRAY_SIZE(data), data);
241
+
if (IS_ERR(provider))
242
+
return PTR_ERR(provider);
243
+
244
+
platform_set_drvdata(pdev, provider);
245
+
246
+
return 0;
247
+
}
248
+
249
+
static int qcom_msm8996_cbf_icc_remove(struct platform_device *pdev)
250
+
{
251
+
struct icc_provider *provider = platform_get_drvdata(pdev);
252
+
253
+
icc_clk_unregister(provider);
254
+
255
+
return 0;
256
+
}
257
+
#define qcom_msm8996_cbf_icc_sync_state icc_sync_state
258
+
#else
259
+
static int qcom_msm8996_cbf_icc_register(struct platform_device *pdev, struct clk_hw *cbf_hw)
260
+
{
261
+
dev_warn(&pdev->dev, "CONFIG_INTERCONNECT is disabled, CBF clock is fixed\n");
262
+
263
+
return 0;
264
+
}
265
+
#define qcom_msm8996_cbf_icc_remove(pdev) (0)
266
+
#define qcom_msm8996_cbf_icc_sync_state NULL
267
+
#endif
268
+
230
269
static int qcom_msm8996_cbf_probe(struct platform_device *pdev)
231
270
{
232
271
void __iomem *base;
···
328
281
if (ret)
329
282
return ret;
330
283
331
-
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &cbf_mux.clkr.hw);
284
+
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &cbf_mux.clkr.hw);
285
+
if (ret)
286
+
return ret;
287
+
288
+
return qcom_msm8996_cbf_icc_register(pdev, &cbf_mux.clkr.hw);
289
+
}
290
+
291
+
static int qcom_msm8996_cbf_remove(struct platform_device *pdev)
292
+
{
293
+
return qcom_msm8996_cbf_icc_remove(pdev);
332
294
}
333
295
334
296
static const struct of_device_id qcom_msm8996_cbf_match_table[] = {
···
348
292
349
293
static struct platform_driver qcom_msm8996_cbf_driver = {
350
294
.probe = qcom_msm8996_cbf_probe,
295
+
.remove = qcom_msm8996_cbf_remove,
351
296
.driver = {
352
297
.name = "qcom-msm8996-cbf",
353
298
.of_match_table = qcom_msm8996_cbf_match_table,
299
+
.sync_state = qcom_msm8996_cbf_icc_sync_state,
354
300
},
355
301
};
356
302
+68
-35
drivers/comedi/Kconfig
+68
-35
drivers/comedi/Kconfig
···
67
67
68
68
config COMEDI_PARPORT
69
69
tristate "Parallel port support"
70
+
depends on HAS_IOPORT
70
71
help
71
72
Enable support for the standard parallel port.
72
73
A cheap and easy way to get a few more digital I/O lines. Steal
···
80
79
config COMEDI_SSV_DNP
81
80
tristate "SSV Embedded Systems DIL/Net-PC support"
82
81
depends on X86_32 || COMPILE_TEST
82
+
depends on HAS_IOPORT
83
83
help
84
84
Enable support for SSV Embedded Systems DIL/Net-PC
85
85
···
91
89
92
90
menuconfig COMEDI_ISA_DRIVERS
93
91
bool "Comedi ISA and PC/104 drivers"
92
+
depends on ISA
94
93
help
95
94
Enable comedi ISA and PC/104 drivers to be built
96
95
···
103
100
104
101
config COMEDI_PCL711
105
102
tristate "Advantech PCL-711/711b and ADlink ACL-8112 ISA card support"
106
-
select COMEDI_8254
103
+
depends on HAS_IOPORT
104
+
depends on COMEDI_8254
107
105
help
108
106
Enable support for Advantech PCL-711 and 711b, ADlink ACL-8112
109
107
···
165
161
166
162
config COMEDI_PCL812
167
163
tristate "Advantech PCL-812/813 and ADlink ACL-8112/8113/8113/8216"
164
+
depends on HAS_IOPORT
168
165
select COMEDI_ISADMA if ISA_DMA_API
169
-
select COMEDI_8254
166
+
depends on COMEDI_8254
170
167
help
171
168
Enable support for Advantech PCL-812/PG, PCL-813/B, ADLink
172
169
ACL-8112DG/HG/PG, ACL-8113, ACL-8216, ICP DAS A-821PGH/PGL/PGL-NDA,
···
178
173
179
174
config COMEDI_PCL816
180
175
tristate "Advantech PCL-814 and PCL-816 ISA card support"
176
+
depends on HAS_IOPORT
181
177
select COMEDI_ISADMA if ISA_DMA_API
182
-
select COMEDI_8254
178
+
depends on COMEDI_8254
183
179
help
184
180
Enable support for Advantech PCL-814 and PCL-816 ISA cards
185
181
···
189
183
190
184
config COMEDI_PCL818
191
185
tristate "Advantech PCL-718 and PCL-818 ISA card support"
186
+
depends on HAS_IOPORT
192
187
select COMEDI_ISADMA if ISA_DMA_API
193
-
select COMEDI_8254
188
+
depends on COMEDI_8254
194
189
help
195
190
Enable support for Advantech PCL-818 ISA cards
196
191
PCL-818L, PCL-818H, PCL-818HD, PCL-818HG, PCL-818 and PCL-718
···
210
203
211
204
config COMEDI_AMPLC_DIO200_ISA
212
205
tristate "Amplicon PC212E/PC214E/PC215E/PC218E/PC272E"
213
-
select COMEDI_AMPLC_DIO200
206
+
depends on COMEDI_AMPLC_DIO200
214
207
help
215
208
Enable support for Amplicon PC212E, PC214E, PC215E, PC218E and
216
209
PC272E ISA DIO boards
···
262
255
263
256
config COMEDI_DAS16M1
264
257
tristate "MeasurementComputing CIO-DAS16/M1DAS-16 ISA card support"
265
-
select COMEDI_8254
258
+
depends on HAS_IOPORT
259
+
depends on COMEDI_8254
266
260
select COMEDI_8255
267
261
help
268
262
Enable support for Measurement Computing CIO-DAS16/M1 ISA cards.
···
273
265
274
266
config COMEDI_DAS08_ISA
275
267
tristate "DAS-08 compatible ISA and PC/104 card support"
276
-
select COMEDI_DAS08
268
+
depends on COMEDI_DAS08
277
269
help
278
270
Enable support for Keithley Metrabyte/ComputerBoards DAS08
279
271
and compatible ISA and PC/104 cards:
···
286
278
287
279
config COMEDI_DAS16
288
280
tristate "DAS-16 compatible ISA and PC/104 card support"
281
+
depends on HAS_IOPORT
289
282
select COMEDI_ISADMA if ISA_DMA_API
290
-
select COMEDI_8254
283
+
depends on COMEDI_8254
291
284
select COMEDI_8255
292
285
help
293
286
Enable support for Keithley Metrabyte/ComputerBoards DAS16
···
305
296
306
297
config COMEDI_DAS800
307
298
tristate "DAS800 and compatible ISA card support"
308
-
select COMEDI_8254
299
+
depends on HAS_IOPORT
300
+
depends on COMEDI_8254
309
301
help
310
302
Enable support for Keithley Metrabyte DAS800 and compatible ISA cards
311
303
Keithley Metrabyte DAS-800, DAS-801, DAS-802
···
318
308
319
309
config COMEDI_DAS1800
320
310
tristate "DAS1800 and compatible ISA card support"
311
+
depends on HAS_IOPORT
321
312
select COMEDI_ISADMA if ISA_DMA_API
322
-
select COMEDI_8254
313
+
depends on COMEDI_8254
323
314
help
324
315
Enable support for DAS1800 and compatible ISA cards
325
316
Keithley Metrabyte DAS-1701ST, DAS-1701ST-DA, DAS-1701/AO,
···
334
323
335
324
config COMEDI_DAS6402
336
325
tristate "DAS6402 and compatible ISA card support"
337
-
select COMEDI_8254
326
+
depends on HAS_IOPORT
327
+
depends on COMEDI_8254
338
328
help
339
329
Enable support for DAS6402 and compatible ISA cards
340
330
Computerboards, Keithley Metrabyte DAS6402 and compatibles
···
414
402
415
403
config COMEDI_AIO_AIO12_8
416
404
tristate "I/O Products PC/104 AIO12-8 Analog I/O Board support"
417
-
select COMEDI_8254
405
+
depends on HAS_IOPORT
406
+
depends on COMEDI_8254
418
407
select COMEDI_8255
419
408
help
420
409
Enable support for I/O Products PC/104 AIO12-8 Analog I/O Board
···
469
456
470
457
config COMEDI_NI_AT_A2150
471
458
tristate "NI AT-A2150 ISA card support"
459
+
depends on HAS_IOPORT
472
460
select COMEDI_ISADMA if ISA_DMA_API
473
-
select COMEDI_8254
461
+
depends on COMEDI_8254
474
462
help
475
463
Enable support for National Instruments AT-A2150 cards
476
464
···
480
466
481
467
config COMEDI_NI_AT_AO
482
468
tristate "NI AT-AO-6/10 EISA card support"
483
-
select COMEDI_8254
469
+
depends on HAS_IOPORT
470
+
depends on COMEDI_8254
484
471
help
485
472
Enable support for National Instruments AT-AO-6/10 cards
486
473
···
512
497
513
498
config COMEDI_NI_LABPC_ISA
514
499
tristate "NI Lab-PC and compatibles ISA support"
515
-
select COMEDI_NI_LABPC
500
+
depends on COMEDI_NI_LABPC
516
501
help
517
502
Enable support for National Instruments Lab-PC and compatibles
518
503
Lab-PC-1200, Lab-PC-1200AI, Lab-PC+.
···
576
561
577
562
menuconfig COMEDI_PCI_DRIVERS
578
563
tristate "Comedi PCI drivers"
579
-
depends on PCI
564
+
depends on PCI && HAS_IOPORT
580
565
help
581
566
Enable support for comedi PCI drivers.
582
567
···
725
710
726
711
config COMEDI_ADL_PCI9111
727
712
tristate "ADLink PCI-9111HR support"
728
-
select COMEDI_8254
713
+
depends on HAS_IOPORT
714
+
depends on COMEDI_8254
729
715
help
730
716
Enable support for ADlink PCI9111 cards
731
717
···
736
720
config COMEDI_ADL_PCI9118
737
721
tristate "ADLink PCI-9118DG, PCI-9118HG, PCI-9118HR support"
738
722
depends on HAS_DMA
739
-
select COMEDI_8254
723
+
depends on COMEDI_8254
740
724
help
741
725
Enable support for ADlink PCI-9118DG, PCI-9118HG, PCI-9118HR cards
742
726
···
745
729
746
730
config COMEDI_ADV_PCI1710
747
731
tristate "Advantech PCI-171x and PCI-1731 support"
748
-
select COMEDI_8254
732
+
depends on HAS_IOPORT
733
+
depends on COMEDI_8254
749
734
help
750
735
Enable support for Advantech PCI-1710, PCI-1710HG, PCI-1711,
751
736
PCI-1713 and PCI-1731
···
790
773
791
774
config COMEDI_ADV_PCI_DIO
792
775
tristate "Advantech PCI DIO card support"
793
-
select COMEDI_8254
776
+
depends on HAS_IOPORT
777
+
depends on COMEDI_8254
794
778
select COMEDI_8255
795
779
help
796
780
Enable support for Advantech PCI DIO cards
···
804
786
805
787
config COMEDI_AMPLC_DIO200_PCI
806
788
tristate "Amplicon PCI215/PCI272/PCIe215/PCIe236/PCIe296 DIO support"
807
-
select COMEDI_AMPLC_DIO200
789
+
depends on COMEDI_AMPLC_DIO200
808
790
help
809
791
Enable support for Amplicon PCI215, PCI272, PCIe215, PCIe236
810
792
and PCIe296 DIO boards.
···
832
814
833
815
config COMEDI_AMPLC_PCI224
834
816
tristate "Amplicon PCI224 and PCI234 support"
835
-
select COMEDI_8254
817
+
depends on HAS_IOPORT
818
+
depends on COMEDI_8254
836
819
help
837
820
Enable support for Amplicon PCI224 and PCI234 AO boards
838
821
···
842
823
843
824
config COMEDI_AMPLC_PCI230
844
825
tristate "Amplicon PCI230 and PCI260 support"
845
-
select COMEDI_8254
826
+
depends on HAS_IOPORT
827
+
depends on COMEDI_8254
846
828
select COMEDI_8255
847
829
help
848
830
Enable support for Amplicon PCI230 and PCI260 Multifunction I/O
···
862
842
863
843
config COMEDI_DAS08_PCI
864
844
tristate "DAS-08 PCI support"
865
-
select COMEDI_DAS08
845
+
depends on COMEDI_DAS08
866
846
help
867
847
Enable support for PCI DAS-08 cards.
868
848
···
949
929
950
930
config COMEDI_CB_PCIDAS
951
931
tristate "MeasurementComputing PCI-DAS support"
952
-
select COMEDI_8254
932
+
depends on HAS_IOPORT
933
+
depends on COMEDI_8254
953
934
select COMEDI_8255
954
935
help
955
936
Enable support for ComputerBoards/MeasurementComputing PCI-DAS with
···
974
953
975
954
config COMEDI_CB_PCIMDAS
976
955
tristate "MeasurementComputing PCIM-DAS1602/16, PCIe-DAS1602/16 support"
977
-
select COMEDI_8254
956
+
depends on HAS_IOPORT
957
+
depends on COMEDI_8254
978
958
select COMEDI_8255
979
959
help
980
960
Enable support for ComputerBoards/MeasurementComputing PCI Migration
···
995
973
996
974
config COMEDI_ME4000
997
975
tristate "Meilhaus ME-4000 support"
998
-
select COMEDI_8254
976
+
depends on HAS_IOPORT
977
+
depends on COMEDI_8254
999
978
help
1000
979
Enable support for Meilhaus PCI data acquisition cards
1001
980
ME-4650, ME-4670i, ME-4680, ME-4680i and ME-4680is
···
1054
1031
1055
1032
config COMEDI_NI_LABPC_PCI
1056
1033
tristate "NI Lab-PC PCI-1200 support"
1057
-
select COMEDI_NI_LABPC
1034
+
depends on COMEDI_NI_LABPC
1058
1035
help
1059
1036
Enable support for National Instruments Lab-PC PCI-1200.
1060
1037
···
1076
1053
config COMEDI_NI_PCIMIO
1077
1054
tristate "NI PCI-MIO-E series and M series support"
1078
1055
depends on HAS_DMA
1056
+
depends on HAS_IOPORT
1079
1057
select COMEDI_NI_TIOCMD
1080
1058
select COMEDI_8255
1081
1059
help
···
1098
1074
1099
1075
config COMEDI_RTD520
1100
1076
tristate "Real Time Devices PCI4520/DM7520 support"
1101
-
select COMEDI_8254
1077
+
depends on HAS_IOPORT
1078
+
depends on COMEDI_8254
1102
1079
help
1103
1080
Enable support for Real Time Devices PCI4520/DM7520
1104
1081
···
1139
1114
1140
1115
config COMEDI_CB_DAS16_CS
1141
1116
tristate "CB DAS16 series PCMCIA support"
1142
-
select COMEDI_8254
1117
+
depends on HAS_IOPORT
1118
+
depends on COMEDI_8254
1143
1119
help
1144
1120
Enable support for the ComputerBoards/MeasurementComputing PCMCIA
1145
1121
cards DAS16/16, PCM-DAS16D/12 and PCM-DAS16s/16
···
1150
1124
1151
1125
config COMEDI_DAS08_CS
1152
1126
tristate "CB DAS08 PCMCIA support"
1153
-
select COMEDI_DAS08
1127
+
depends on COMEDI_DAS08
1154
1128
help
1155
1129
Enable support for the ComputerBoards/MeasurementComputing DAS-08
1156
1130
PCMCIA card
···
1160
1134
1161
1135
config COMEDI_NI_DAQ_700_CS
1162
1136
tristate "NI DAQCard-700 PCMCIA support"
1137
+
depends on HAS_IOPORT
1163
1138
help
1164
1139
Enable support for the National Instruments PCMCIA DAQCard-700 DIO
1165
1140
···
1169
1142
1170
1143
config COMEDI_NI_DAQ_DIO24_CS
1171
1144
tristate "NI DAQ-Card DIO-24 PCMCIA support"
1145
+
depends on HAS_IOPORT
1172
1146
select COMEDI_8255
1173
1147
help
1174
1148
Enable support for the National Instruments PCMCIA DAQ-Card DIO-24
···
1179
1151
1180
1152
config COMEDI_NI_LABPC_CS
1181
1153
tristate "NI DAQCard-1200 PCMCIA support"
1182
-
select COMEDI_NI_LABPC
1154
+
depends on COMEDI_NI_LABPC
1183
1155
help
1184
1156
Enable support for the National Instruments PCMCIA DAQCard-1200
1185
1157
···
1188
1160
1189
1161
config COMEDI_NI_MIO_CS
1190
1162
tristate "NI DAQCard E series PCMCIA support"
1163
+
depends on HAS_IOPORT
1191
1164
select COMEDI_NI_TIO
1192
1165
select COMEDI_8255
1193
1166
help
···
1201
1172
1202
1173
config COMEDI_QUATECH_DAQP_CS
1203
1174
tristate "Quatech DAQP PCMCIA data capture card support"
1175
+
depends on HAS_IOPORT
1204
1176
help
1205
1177
Enable support for the Quatech DAQP PCMCIA data capture cards
1206
1178
DAQP-208 and DAQP-308
···
1278
1248
1279
1249
config COMEDI_8254
1280
1250
tristate
1251
+
depends on HAS_IOPORT
1281
1252
1282
1253
config COMEDI_8255
1283
1254
tristate
1284
1255
1285
1256
config COMEDI_8255_SA
1286
1257
tristate "Standalone 8255 support"
1258
+
depends on HAS_IOPORT
1287
1259
select COMEDI_8255
1288
1260
help
1289
1261
Enable support for 8255 digital I/O as a standalone driver.
···
1317
1285
called kcomedilib.
1318
1286
1319
1287
config COMEDI_AMPLC_DIO200
1320
-
select COMEDI_8254
1288
+
depends on COMEDI_8254
1321
1289
tristate
1322
1290
1323
1291
config COMEDI_AMPLC_PC236
···
1326
1294
1327
1295
config COMEDI_DAS08
1328
1296
tristate
1329
-
select COMEDI_8254
1297
+
depends on COMEDI_8254
1330
1298
select COMEDI_8255
1331
1299
1332
1300
config COMEDI_ISADMA
···
1334
1302
1335
1303
config COMEDI_NI_LABPC
1336
1304
tristate
1337
-
select COMEDI_8254
1305
+
depends on HAS_IOPORT
1306
+
depends on COMEDI_8254
1338
1307
select COMEDI_8255
1339
1308
1340
1309
config COMEDI_NI_LABPC_ISADMA
+24
-23
drivers/comedi/comedi_fops.c
+24
-23
drivers/comedi/comedi_fops.c
···
97
97
static struct comedi_subdevice
98
98
*comedi_subdevice_minor_table[COMEDI_NUM_SUBDEVICE_MINORS];
99
99
100
-
static struct class *comedi_class;
101
100
static struct cdev comedi_cdev;
102
101
103
102
static void comedi_device_init(struct comedi_device *dev)
···
184
185
comedi_board_minor_table[minor] = NULL;
185
186
mutex_unlock(&comedi_board_minor_table_lock);
186
187
return dev;
187
-
}
188
-
189
-
static void comedi_free_board_dev(struct comedi_device *dev)
190
-
{
191
-
if (dev) {
192
-
comedi_device_cleanup(dev);
193
-
if (dev->class_dev) {
194
-
device_destroy(comedi_class,
195
-
MKDEV(COMEDI_MAJOR, dev->minor));
196
-
}
197
-
comedi_dev_put(dev);
198
-
}
199
188
}
200
189
201
190
static struct comedi_subdevice *
···
597
610
NULL,
598
611
};
599
612
ATTRIBUTE_GROUPS(comedi_dev);
613
+
614
+
static const struct class comedi_class = {
615
+
.name = "comedi",
616
+
.dev_groups = comedi_dev_groups,
617
+
};
618
+
619
+
static void comedi_free_board_dev(struct comedi_device *dev)
620
+
{
621
+
if (dev) {
622
+
comedi_device_cleanup(dev);
623
+
if (dev->class_dev) {
624
+
device_destroy(&comedi_class,
625
+
MKDEV(COMEDI_MAJOR, dev->minor));
626
+
}
627
+
comedi_dev_put(dev);
628
+
}
629
+
}
600
630
601
631
static void __comedi_clear_subdevice_runflags(struct comedi_subdevice *s,
602
632
unsigned int bits)
···
3267
3263
return ERR_PTR(-EBUSY);
3268
3264
}
3269
3265
dev->minor = i;
3270
-
csdev = device_create(comedi_class, hardware_device,
3266
+
csdev = device_create(&comedi_class, hardware_device,
3271
3267
MKDEV(COMEDI_MAJOR, i), NULL, "comedi%i", i);
3272
3268
if (!IS_ERR(csdev))
3273
3269
dev->class_dev = get_device(csdev);
···
3316
3312
}
3317
3313
i += COMEDI_NUM_BOARD_MINORS;
3318
3314
s->minor = i;
3319
-
csdev = device_create(comedi_class, dev->class_dev,
3315
+
csdev = device_create(&comedi_class, dev->class_dev,
3320
3316
MKDEV(COMEDI_MAJOR, i), NULL, "comedi%i_subd%i",
3321
3317
dev->minor, s->index);
3322
3318
if (!IS_ERR(csdev))
···
3341
3337
comedi_subdevice_minor_table[i] = NULL;
3342
3338
mutex_unlock(&comedi_subdevice_minor_table_lock);
3343
3339
if (s->class_dev) {
3344
-
device_destroy(comedi_class, MKDEV(COMEDI_MAJOR, s->minor));
3340
+
device_destroy(&comedi_class, MKDEV(COMEDI_MAJOR, s->minor));
3345
3341
s->class_dev = NULL;
3346
3342
}
3347
3343
}
···
3387
3383
if (retval)
3388
3384
goto out_unregister_chrdev_region;
3389
3385
3390
-
comedi_class = class_create("comedi");
3391
-
if (IS_ERR(comedi_class)) {
3392
-
retval = PTR_ERR(comedi_class);
3386
+
retval = class_register(&comedi_class);
3387
+
if (retval) {
3393
3388
pr_err("failed to create class\n");
3394
3389
goto out_cdev_del;
3395
3390
}
3396
-
3397
-
comedi_class->dev_groups = comedi_dev_groups;
3398
3391
3399
3392
/* create devices files for legacy/manual use */
3400
3393
for (i = 0; i < comedi_num_legacy_minors; i++) {
···
3414
3413
3415
3414
out_cleanup_board_minors:
3416
3415
comedi_cleanup_board_minors();
3417
-
class_destroy(comedi_class);
3416
+
class_unregister(&comedi_class);
3418
3417
out_cdev_del:
3419
3418
cdev_del(&comedi_cdev);
3420
3419
out_unregister_chrdev_region:
···
3426
3425
static void __exit comedi_cleanup(void)
3427
3426
{
3428
3427
comedi_cleanup_board_minors();
3429
-
class_destroy(comedi_class);
3428
+
class_unregister(&comedi_class);
3430
3429
cdev_del(&comedi_cdev);
3431
3430
unregister_chrdev_region(MKDEV(COMEDI_MAJOR, 0), COMEDI_NUM_MINORS);
3432
3431
+11
-12
drivers/comedi/drivers/comedi_test.c
+11
-12
drivers/comedi/drivers/comedi_test.c
···
60
60
static bool config_mode;
61
61
static unsigned int set_amplitude;
62
62
static unsigned int set_period;
63
-
static struct class *ctcls;
63
+
static const struct class ctcls = {
64
+
.name = CLASS_NAME,
65
+
};
64
66
static struct device *ctdev;
65
67
66
68
module_param_named(noauto, config_mode, bool, 0444);
···
797
795
}
798
796
799
797
if (!config_mode) {
800
-
ctcls = class_create(CLASS_NAME);
801
-
if (IS_ERR(ctcls)) {
798
+
ret = class_register(&ctcls);
799
+
if (ret) {
802
800
pr_warn("comedi_test: unable to create class\n");
803
801
goto clean3;
804
802
}
805
803
806
-
ctdev = device_create(ctcls, NULL, MKDEV(0, 0), NULL, DEV_NAME);
804
+
ctdev = device_create(&ctcls, NULL, MKDEV(0, 0), NULL, DEV_NAME);
807
805
if (IS_ERR(ctdev)) {
808
806
pr_warn("comedi_test: unable to create device\n");
809
807
goto clean2;
···
819
817
return 0;
820
818
821
819
clean:
822
-
device_destroy(ctcls, MKDEV(0, 0));
820
+
device_destroy(&ctcls, MKDEV(0, 0));
823
821
clean2:
824
-
class_destroy(ctcls);
825
-
ctdev = NULL;
822
+
class_unregister(&ctcls);
826
823
clean3:
827
-
ctcls = NULL;
828
-
829
824
return 0;
830
825
}
831
826
module_init(comedi_test_init);
···
832
833
if (ctdev)
833
834
comedi_auto_unconfig(ctdev);
834
835
835
-
if (ctcls) {
836
-
device_destroy(ctcls, MKDEV(0, 0));
837
-
class_destroy(ctcls);
836
+
if (class_is_registered(&ctcls)) {
837
+
device_destroy(&ctcls, MKDEV(0, 0));
838
+
class_unregister(&ctcls);
838
839
}
839
840
840
841
comedi_driver_unregister(&waveform_driver);
+439
-363
drivers/counter/104-quad-8.c
+439
-363
drivers/counter/104-quad-8.c
···
5
5
*
6
6
* This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
7
7
*/
8
-
#include <linux/bitops.h>
8
+
#include <linux/bitfield.h>
9
+
#include <linux/bits.h>
9
10
#include <linux/counter.h>
10
11
#include <linux/device.h>
11
-
#include <linux/errno.h>
12
+
#include <linux/err.h>
12
13
#include <linux/io.h>
13
14
#include <linux/ioport.h>
14
15
#include <linux/interrupt.h>
···
18
17
#include <linux/list.h>
19
18
#include <linux/module.h>
20
19
#include <linux/moduleparam.h>
21
-
#include <linux/types.h>
20
+
#include <linux/regmap.h>
22
21
#include <linux/spinlock.h>
22
+
#include <linux/types.h>
23
+
24
+
#include <asm/unaligned.h>
23
25
24
26
#define QUAD8_EXTENT 32
25
27
···
38
34
39
35
#define QUAD8_NUM_COUNTERS 8
40
36
41
-
/**
42
-
* struct channel_reg - channel register structure
43
-
* @data: Count data
44
-
* @control: Channel flags and control
45
-
*/
46
-
struct channel_reg {
47
-
u8 data;
48
-
u8 control;
49
-
};
50
-
51
-
/**
52
-
* struct quad8_reg - device register structure
53
-
* @channel: quadrature counter data and control
54
-
* @interrupt_status: channel interrupt status
55
-
* @channel_oper: enable/reset counters and interrupt functions
56
-
* @index_interrupt: enable channel interrupts
57
-
* @reserved: reserved for Factory Use
58
-
* @index_input_levels: index signal logical input level
59
-
* @cable_status: differential encoder cable status
60
-
*/
61
-
struct quad8_reg {
62
-
struct channel_reg channel[QUAD8_NUM_COUNTERS];
63
-
u8 interrupt_status;
64
-
u8 channel_oper;
65
-
u8 index_interrupt;
66
-
u8 reserved[3];
67
-
u8 index_input_levels;
68
-
u8 cable_status;
69
-
};
37
+
#define QUAD8_DATA(_channel) ((_channel) * 2)
38
+
#define QUAD8_CONTROL(_channel) (QUAD8_DATA(_channel) + 1)
39
+
#define QUAD8_INTERRUPT_STATUS 0x10
40
+
#define QUAD8_CHANNEL_OPERATION 0x11
41
+
#define QUAD8_INDEX_INTERRUPT 0x12
42
+
#define QUAD8_INDEX_INPUT_LEVELS 0x16
43
+
#define QUAD8_CABLE_STATUS 0x17
70
44
71
45
/**
72
46
* struct quad8 - device private data structure
73
47
* @lock: lock to prevent clobbering device states during R/W ops
74
-
* @counter: instance of the counter_device
48
+
* @cmr: array of Counter Mode Register states
49
+
* @ior: array of Input / Output Control Register states
50
+
* @idr: array of Index Control Register states
75
51
* @fck_prescaler: array of filter clock prescaler configurations
76
52
* @preset: array of preset values
77
-
* @count_mode: array of count mode configurations
78
-
* @quadrature_mode: array of quadrature mode configurations
79
-
* @quadrature_scale: array of quadrature mode scale configurations
80
-
* @ab_enable: array of A and B inputs enable configurations
81
-
* @preset_enable: array of set_to_preset_on_index attribute configurations
82
-
* @irq_trigger: array of current IRQ trigger function configurations
83
-
* @synchronous_mode: array of index function synchronous mode configurations
84
-
* @index_polarity: array of index function polarity configurations
85
53
* @cable_fault_enable: differential encoder cable status enable configurations
86
-
* @reg: I/O address offset for the device registers
54
+
* @map: regmap for the device
87
55
*/
88
56
struct quad8 {
89
57
spinlock_t lock;
58
+
u8 cmr[QUAD8_NUM_COUNTERS];
59
+
u8 ior[QUAD8_NUM_COUNTERS];
60
+
u8 idr[QUAD8_NUM_COUNTERS];
90
61
unsigned int fck_prescaler[QUAD8_NUM_COUNTERS];
91
62
unsigned int preset[QUAD8_NUM_COUNTERS];
92
-
unsigned int count_mode[QUAD8_NUM_COUNTERS];
93
-
unsigned int quadrature_mode[QUAD8_NUM_COUNTERS];
94
-
unsigned int quadrature_scale[QUAD8_NUM_COUNTERS];
95
-
unsigned int ab_enable[QUAD8_NUM_COUNTERS];
96
-
unsigned int preset_enable[QUAD8_NUM_COUNTERS];
97
-
unsigned int irq_trigger[QUAD8_NUM_COUNTERS];
98
-
unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
99
-
unsigned int index_polarity[QUAD8_NUM_COUNTERS];
100
63
unsigned int cable_fault_enable;
101
-
struct quad8_reg __iomem *reg;
64
+
struct regmap *map;
65
+
};
66
+
67
+
static const struct regmap_range quad8_wr_ranges[] = {
68
+
regmap_reg_range(0x0, 0xF), regmap_reg_range(0x11, 0x12), regmap_reg_range(0x17, 0x17),
69
+
};
70
+
static const struct regmap_range quad8_rd_ranges[] = {
71
+
regmap_reg_range(0x0, 0x12), regmap_reg_range(0x16, 0x18),
72
+
};
73
+
static const struct regmap_access_table quad8_wr_table = {
74
+
.yes_ranges = quad8_wr_ranges,
75
+
.n_yes_ranges = ARRAY_SIZE(quad8_wr_ranges),
76
+
};
77
+
static const struct regmap_access_table quad8_rd_table = {
78
+
.yes_ranges = quad8_rd_ranges,
79
+
.n_yes_ranges = ARRAY_SIZE(quad8_rd_ranges),
80
+
};
81
+
static const struct regmap_config quad8_regmap_config = {
82
+
.reg_bits = 8,
83
+
.reg_stride = 1,
84
+
.val_bits = 8,
85
+
.io_port = true,
86
+
.wr_table = &quad8_wr_table,
87
+
.rd_table = &quad8_rd_table,
102
88
};
103
89
104
90
/* Error flag */
105
-
#define QUAD8_FLAG_E BIT(4)
91
+
#define FLAG_E BIT(4)
106
92
/* Up/Down flag */
107
-
#define QUAD8_FLAG_UD BIT(5)
93
+
#define FLAG_UD BIT(5)
94
+
/* Counting up */
95
+
#define UP 0x1
96
+
97
+
#define REGISTER_SELECTION GENMASK(6, 5)
98
+
108
99
/* Reset and Load Signal Decoders */
109
-
#define QUAD8_CTR_RLD 0x00
100
+
#define SELECT_RLD u8_encode_bits(0x0, REGISTER_SELECTION)
110
101
/* Counter Mode Register */
111
-
#define QUAD8_CTR_CMR 0x20
102
+
#define SELECT_CMR u8_encode_bits(0x1, REGISTER_SELECTION)
112
103
/* Input / Output Control Register */
113
-
#define QUAD8_CTR_IOR 0x40
104
+
#define SELECT_IOR u8_encode_bits(0x2, REGISTER_SELECTION)
114
105
/* Index Control Register */
115
-
#define QUAD8_CTR_IDR 0x60
106
+
#define SELECT_IDR u8_encode_bits(0x3, REGISTER_SELECTION)
107
+
108
+
/*
109
+
* Reset and Load Signal Decoders
110
+
*/
111
+
#define RESETS GENMASK(2, 1)
112
+
#define LOADS GENMASK(4, 3)
116
113
/* Reset Byte Pointer (three byte data pointer) */
117
-
#define QUAD8_RLD_RESET_BP 0x01
118
-
/* Reset Counter */
119
-
#define QUAD8_RLD_RESET_CNTR 0x02
120
-
/* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */
121
-
#define QUAD8_RLD_RESET_FLAGS 0x04
114
+
#define RESET_BP BIT(0)
115
+
/* Reset Borrow Toggle, Carry toggle, Compare toggle, Sign, and Index flags */
116
+
#define RESET_BT_CT_CPT_S_IDX u8_encode_bits(0x2, RESETS)
122
117
/* Reset Error flag */
123
-
#define QUAD8_RLD_RESET_E 0x06
118
+
#define RESET_E u8_encode_bits(0x3, RESETS)
124
119
/* Preset Register to Counter */
125
-
#define QUAD8_RLD_PRESET_CNTR 0x08
120
+
#define TRANSFER_PR_TO_CNTR u8_encode_bits(0x1, LOADS)
126
121
/* Transfer Counter to Output Latch */
127
-
#define QUAD8_RLD_CNTR_OUT 0x10
122
+
#define TRANSFER_CNTR_TO_OL u8_encode_bits(0x2, LOADS)
128
123
/* Transfer Preset Register LSB to FCK Prescaler */
129
-
#define QUAD8_RLD_PRESET_PSC 0x18
130
-
#define QUAD8_CHAN_OP_RESET_COUNTERS 0x01
131
-
#define QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC 0x04
132
-
#define QUAD8_CMR_QUADRATURE_X1 0x08
133
-
#define QUAD8_CMR_QUADRATURE_X2 0x10
134
-
#define QUAD8_CMR_QUADRATURE_X4 0x18
124
+
#define TRANSFER_PR0_TO_PSC u8_encode_bits(0x3, LOADS)
125
+
126
+
/*
127
+
* Counter Mode Registers
128
+
*/
129
+
#define COUNT_ENCODING BIT(0)
130
+
#define COUNT_MODE GENMASK(2, 1)
131
+
#define QUADRATURE_MODE GENMASK(4, 3)
132
+
/* Binary count */
133
+
#define BINARY u8_encode_bits(0x0, COUNT_ENCODING)
134
+
/* Normal count */
135
+
#define NORMAL_COUNT 0x0
136
+
/* Range Limit */
137
+
#define RANGE_LIMIT 0x1
138
+
/* Non-recycle count */
139
+
#define NON_RECYCLE_COUNT 0x2
140
+
/* Modulo-N */
141
+
#define MODULO_N 0x3
142
+
/* Non-quadrature */
143
+
#define NON_QUADRATURE 0x0
144
+
/* Quadrature X1 */
145
+
#define QUADRATURE_X1 0x1
146
+
/* Quadrature X2 */
147
+
#define QUADRATURE_X2 0x2
148
+
/* Quadrature X4 */
149
+
#define QUADRATURE_X4 0x3
150
+
151
+
/*
152
+
* Input/Output Control Register
153
+
*/
154
+
#define AB_GATE BIT(0)
155
+
#define LOAD_PIN BIT(1)
156
+
#define FLG_PINS GENMASK(4, 3)
157
+
/* Disable inputs A and B */
158
+
#define DISABLE_AB u8_encode_bits(0x0, AB_GATE)
159
+
/* Load Counter input */
160
+
#define LOAD_CNTR 0x0
161
+
/* FLG1 = CARRY(active low); FLG2 = BORROW(active low) */
162
+
#define FLG1_CARRY_FLG2_BORROW 0x0
163
+
/* FLG1 = COMPARE(active low); FLG2 = BORROW(active low) */
164
+
#define FLG1_COMPARE_FLG2_BORROW 0x1
165
+
/* FLG1 = Carry(active low)/Borrow(active low); FLG2 = U/D(active low) flag */
166
+
#define FLG1_CARRYBORROW_FLG2_UD 0x2
167
+
/* FLG1 = INDX (low pulse at INDEX pin active level); FLG2 = E flag */
168
+
#define FLG1_INDX_FLG2_E 0x3
169
+
170
+
/*
171
+
* INDEX CONTROL REGISTERS
172
+
*/
173
+
#define INDEX_MODE BIT(0)
174
+
#define INDEX_POLARITY BIT(1)
175
+
/* Disable Index mode */
176
+
#define DISABLE_INDEX_MODE 0x0
177
+
/* Enable Index mode */
178
+
#define ENABLE_INDEX_MODE 0x1
179
+
/* Negative Index Polarity */
180
+
#define NEGATIVE_INDEX_POLARITY 0x0
181
+
/* Positive Index Polarity */
182
+
#define POSITIVE_INDEX_POLARITY 0x1
183
+
184
+
/*
185
+
* Channel Operation Register
186
+
*/
187
+
#define COUNTERS_OPERATION BIT(0)
188
+
#define INTERRUPT_FUNCTION BIT(2)
189
+
/* Enable all Counters */
190
+
#define ENABLE_COUNTERS u8_encode_bits(0x0, COUNTERS_OPERATION)
191
+
/* Reset all Counters */
192
+
#define RESET_COUNTERS u8_encode_bits(0x1, COUNTERS_OPERATION)
193
+
/* Disable the interrupt function */
194
+
#define DISABLE_INTERRUPT_FUNCTION u8_encode_bits(0x0, INTERRUPT_FUNCTION)
195
+
/* Enable the interrupt function */
196
+
#define ENABLE_INTERRUPT_FUNCTION u8_encode_bits(0x1, INTERRUPT_FUNCTION)
197
+
/* Any write to the Channel Operation register clears any pending interrupts */
198
+
#define CLEAR_PENDING_INTERRUPTS (ENABLE_COUNTERS | ENABLE_INTERRUPT_FUNCTION)
135
199
136
200
/* Each Counter is 24 bits wide */
137
201
#define LS7267_CNTR_MAX GENMASK(23, 0)
202
+
203
+
static __always_inline int quad8_control_register_update(struct regmap *const map, u8 *const buf,
204
+
const size_t channel, const u8 val,
205
+
const u8 field)
206
+
{
207
+
u8p_replace_bits(&buf[channel], val, field);
208
+
return regmap_write(map, QUAD8_CONTROL(channel), buf[channel]);
209
+
}
138
210
139
211
static int quad8_signal_read(struct counter_device *counter,
140
212
struct counter_signal *signal,
141
213
enum counter_signal_level *level)
142
214
{
143
215
const struct quad8 *const priv = counter_priv(counter);
144
-
unsigned int state;
216
+
int ret;
145
217
146
218
/* Only Index signal levels can be read */
147
219
if (signal->id < 16)
148
220
return -EINVAL;
149
221
150
-
state = ioread8(&priv->reg->index_input_levels) & BIT(signal->id - 16);
222
+
ret = regmap_test_bits(priv->map, QUAD8_INDEX_INPUT_LEVELS, BIT(signal->id - 16));
223
+
if (ret < 0)
224
+
return ret;
151
225
152
-
*level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
226
+
*level = (ret) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
153
227
154
228
return 0;
155
229
}
···
236
154
struct counter_count *count, u64 *val)
237
155
{
238
156
struct quad8 *const priv = counter_priv(counter);
239
-
struct channel_reg __iomem *const chan = priv->reg->channel + count->id;
240
157
unsigned long irqflags;
241
-
int i;
242
-
243
-
*val = 0;
158
+
u8 value[3];
159
+
int ret;
244
160
245
161
spin_lock_irqsave(&priv->lock, irqflags);
246
162
247
-
/* Reset Byte Pointer; transfer Counter to Output Latch */
248
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
249
-
&chan->control);
163
+
ret = regmap_write(priv->map, QUAD8_CONTROL(count->id),
164
+
SELECT_RLD | RESET_BP | TRANSFER_CNTR_TO_OL);
165
+
if (ret)
166
+
goto exit_unlock;
167
+
ret = regmap_noinc_read(priv->map, QUAD8_DATA(count->id), value, sizeof(value));
250
168
251
-
for (i = 0; i < 3; i++)
252
-
*val |= (unsigned long)ioread8(&chan->data) << (8 * i);
253
-
169
+
exit_unlock:
254
170
spin_unlock_irqrestore(&priv->lock, irqflags);
255
171
256
-
return 0;
172
+
*val = get_unaligned_le24(value);
173
+
174
+
return ret;
175
+
}
176
+
177
+
static int quad8_preset_register_set(struct quad8 *const priv, const size_t id,
178
+
const unsigned long preset)
179
+
{
180
+
u8 value[3];
181
+
int ret;
182
+
183
+
put_unaligned_le24(preset, value);
184
+
185
+
ret = regmap_write(priv->map, QUAD8_CONTROL(id), SELECT_RLD | RESET_BP);
186
+
if (ret)
187
+
return ret;
188
+
return regmap_noinc_write(priv->map, QUAD8_DATA(id), value, sizeof(value));
189
+
}
190
+
191
+
static int quad8_flag_register_reset(struct quad8 *const priv, const size_t id)
192
+
{
193
+
int ret;
194
+
195
+
ret = regmap_write(priv->map, QUAD8_CONTROL(id), SELECT_RLD | RESET_BT_CT_CPT_S_IDX);
196
+
if (ret)
197
+
return ret;
198
+
return regmap_write(priv->map, QUAD8_CONTROL(id), SELECT_RLD | RESET_E);
257
199
}
258
200
259
201
static int quad8_count_write(struct counter_device *counter,
260
202
struct counter_count *count, u64 val)
261
203
{
262
204
struct quad8 *const priv = counter_priv(counter);
263
-
struct channel_reg __iomem *const chan = priv->reg->channel + count->id;
264
205
unsigned long irqflags;
265
-
int i;
206
+
int ret;
266
207
267
208
if (val > LS7267_CNTR_MAX)
268
209
return -ERANGE;
269
210
270
211
spin_lock_irqsave(&priv->lock, irqflags);
271
212
272
-
/* Reset Byte Pointer */
273
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
274
-
275
213
/* Counter can only be set via Preset Register */
276
-
for (i = 0; i < 3; i++)
277
-
iowrite8(val >> (8 * i), &chan->data);
214
+
ret = quad8_preset_register_set(priv, count->id, val);
215
+
if (ret)
216
+
goto exit_unlock;
217
+
ret = regmap_write(priv->map, QUAD8_CONTROL(count->id), SELECT_RLD | TRANSFER_PR_TO_CNTR);
218
+
if (ret)
219
+
goto exit_unlock;
278
220
279
-
/* Transfer Preset Register to Counter */
280
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, &chan->control);
281
-
282
-
/* Reset Byte Pointer */
283
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
221
+
ret = quad8_flag_register_reset(priv, count->id);
222
+
if (ret)
223
+
goto exit_unlock;
284
224
285
225
/* Set Preset Register back to original value */
286
-
val = priv->preset[count->id];
287
-
for (i = 0; i < 3; i++)
288
-
iowrite8(val >> (8 * i), &chan->data);
226
+
ret = quad8_preset_register_set(priv, count->id, priv->preset[count->id]);
289
227
290
-
/* Reset Borrow, Carry, Compare, and Sign flags */
291
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control);
292
-
/* Reset Error flag */
293
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control);
294
-
228
+
exit_unlock:
295
229
spin_unlock_irqrestore(&priv->lock, irqflags);
296
230
297
-
return 0;
231
+
return ret;
298
232
}
299
233
300
234
static const enum counter_function quad8_count_functions_list[] = {
···
323
225
static int quad8_function_get(const struct quad8 *const priv, const size_t id,
324
226
enum counter_function *const function)
325
227
{
326
-
if (!priv->quadrature_mode[id]) {
228
+
switch (u8_get_bits(priv->cmr[id], QUADRATURE_MODE)) {
229
+
case NON_QUADRATURE:
327
230
*function = COUNTER_FUNCTION_PULSE_DIRECTION;
328
231
return 0;
329
-
}
330
-
331
-
switch (priv->quadrature_scale[id]) {
332
-
case 0:
232
+
case QUADRATURE_X1:
333
233
*function = COUNTER_FUNCTION_QUADRATURE_X1_A;
334
234
return 0;
335
-
case 1:
235
+
case QUADRATURE_X2:
336
236
*function = COUNTER_FUNCTION_QUADRATURE_X2_A;
337
237
return 0;
338
-
case 2:
238
+
case QUADRATURE_X4:
339
239
*function = COUNTER_FUNCTION_QUADRATURE_X4;
340
240
return 0;
341
241
default:
···
365
269
{
366
270
struct quad8 *const priv = counter_priv(counter);
367
271
const int id = count->id;
368
-
unsigned int *const quadrature_mode = priv->quadrature_mode + id;
369
-
unsigned int *const scale = priv->quadrature_scale + id;
370
-
unsigned int *const synchronous_mode = priv->synchronous_mode + id;
371
-
u8 __iomem *const control = &priv->reg->channel[id].control;
372
272
unsigned long irqflags;
373
273
unsigned int mode_cfg;
374
-
unsigned int idr_cfg;
274
+
bool synchronous_mode;
275
+
int ret;
276
+
277
+
switch (function) {
278
+
case COUNTER_FUNCTION_PULSE_DIRECTION:
279
+
mode_cfg = NON_QUADRATURE;
280
+
break;
281
+
case COUNTER_FUNCTION_QUADRATURE_X1_A:
282
+
mode_cfg = QUADRATURE_X1;
283
+
break;
284
+
case COUNTER_FUNCTION_QUADRATURE_X2_A:
285
+
mode_cfg = QUADRATURE_X2;
286
+
break;
287
+
case COUNTER_FUNCTION_QUADRATURE_X4:
288
+
mode_cfg = QUADRATURE_X4;
289
+
break;
290
+
default:
291
+
/* should never reach this path */
292
+
return -EINVAL;
293
+
}
375
294
376
295
spin_lock_irqsave(&priv->lock, irqflags);
377
296
378
-
mode_cfg = priv->count_mode[id] << 1;
379
-
idr_cfg = priv->index_polarity[id] << 1;
380
-
381
-
if (function == COUNTER_FUNCTION_PULSE_DIRECTION) {
382
-
*quadrature_mode = 0;
383
-
384
-
/* Quadrature scaling only available in quadrature mode */
385
-
*scale = 0;
386
-
387
-
/* Synchronous function not supported in non-quadrature mode */
388
-
if (*synchronous_mode) {
389
-
*synchronous_mode = 0;
390
-
/* Disable synchronous function mode */
391
-
iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
392
-
}
393
-
} else {
394
-
*quadrature_mode = 1;
395
-
396
-
switch (function) {
397
-
case COUNTER_FUNCTION_QUADRATURE_X1_A:
398
-
*scale = 0;
399
-
mode_cfg |= QUAD8_CMR_QUADRATURE_X1;
400
-
break;
401
-
case COUNTER_FUNCTION_QUADRATURE_X2_A:
402
-
*scale = 1;
403
-
mode_cfg |= QUAD8_CMR_QUADRATURE_X2;
404
-
break;
405
-
case COUNTER_FUNCTION_QUADRATURE_X4:
406
-
*scale = 2;
407
-
mode_cfg |= QUAD8_CMR_QUADRATURE_X4;
408
-
break;
409
-
default:
410
-
/* should never reach this path */
411
-
spin_unlock_irqrestore(&priv->lock, irqflags);
412
-
return -EINVAL;
413
-
}
297
+
/* Synchronous function not supported in non-quadrature mode */
298
+
synchronous_mode = u8_get_bits(priv->idr[id], INDEX_MODE) == ENABLE_INDEX_MODE;
299
+
if (synchronous_mode && mode_cfg == NON_QUADRATURE) {
300
+
ret = quad8_control_register_update(priv->map, priv->idr, id, DISABLE_INDEX_MODE,
301
+
INDEX_MODE);
302
+
if (ret)
303
+
goto exit_unlock;
414
304
}
415
305
416
-
/* Load mode configuration to Counter Mode Register */
417
-
iowrite8(QUAD8_CTR_CMR | mode_cfg, control);
306
+
ret = quad8_control_register_update(priv->map, priv->cmr, id, mode_cfg, QUADRATURE_MODE);
418
307
308
+
exit_unlock:
419
309
spin_unlock_irqrestore(&priv->lock, irqflags);
420
310
421
-
return 0;
311
+
return ret;
422
312
}
423
313
424
314
static int quad8_direction_read(struct counter_device *counter,
···
412
330
enum counter_count_direction *direction)
413
331
{
414
332
const struct quad8 *const priv = counter_priv(counter);
415
-
unsigned int ud_flag;
416
-
u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control;
333
+
unsigned int flag;
334
+
int ret;
417
335
418
-
/* U/D flag: nonzero = up, zero = down */
419
-
ud_flag = ioread8(flag_addr) & QUAD8_FLAG_UD;
420
-
421
-
*direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD :
336
+
ret = regmap_read(priv->map, QUAD8_CONTROL(count->id), &flag);
337
+
if (ret)
338
+
return ret;
339
+
*direction = (u8_get_bits(flag, FLAG_UD) == UP) ? COUNTER_COUNT_DIRECTION_FORWARD :
422
340
COUNTER_COUNT_DIRECTION_BACKWARD;
423
341
424
342
return 0;
···
448
366
const size_t signal_a_id = count->synapses[0].signal->id;
449
367
enum counter_count_direction direction;
450
368
369
+
/* Default action mode */
370
+
*action = COUNTER_SYNAPSE_ACTION_NONE;
371
+
451
372
/* Handle Index signals */
452
373
if (synapse->signal->id >= 16) {
453
-
if (!priv->preset_enable[count->id])
374
+
if (u8_get_bits(priv->ior[count->id], LOAD_PIN) == LOAD_CNTR)
454
375
*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
455
-
else
456
-
*action = COUNTER_SYNAPSE_ACTION_NONE;
457
-
458
376
return 0;
459
377
}
460
378
···
473
391
}
474
392
475
393
spin_unlock_irqrestore(&priv->lock, irqflags);
476
-
477
-
/* Default action mode */
478
-
*action = COUNTER_SYNAPSE_ACTION_NONE;
479
394
480
395
/* Determine action mode based on current count function mode */
481
396
switch (function) {
···
501
422
}
502
423
}
503
424
504
-
enum {
505
-
QUAD8_EVENT_CARRY = 0,
506
-
QUAD8_EVENT_COMPARE = 1,
507
-
QUAD8_EVENT_CARRY_BORROW = 2,
508
-
QUAD8_EVENT_INDEX = 3,
509
-
};
510
-
511
425
static int quad8_events_configure(struct counter_device *counter)
512
426
{
513
427
struct quad8 *const priv = counter_priv(counter);
514
428
unsigned long irq_enabled = 0;
515
429
unsigned long irqflags;
516
430
struct counter_event_node *event_node;
517
-
unsigned int next_irq_trigger;
518
-
unsigned long ior_cfg;
431
+
u8 flg_pins;
432
+
int ret;
519
433
520
434
spin_lock_irqsave(&priv->lock, irqflags);
521
435
522
436
list_for_each_entry(event_node, &counter->events_list, l) {
523
437
switch (event_node->event) {
524
438
case COUNTER_EVENT_OVERFLOW:
525
-
next_irq_trigger = QUAD8_EVENT_CARRY;
439
+
flg_pins = FLG1_CARRY_FLG2_BORROW;
526
440
break;
527
441
case COUNTER_EVENT_THRESHOLD:
528
-
next_irq_trigger = QUAD8_EVENT_COMPARE;
442
+
flg_pins = FLG1_COMPARE_FLG2_BORROW;
529
443
break;
530
444
case COUNTER_EVENT_OVERFLOW_UNDERFLOW:
531
-
next_irq_trigger = QUAD8_EVENT_CARRY_BORROW;
445
+
flg_pins = FLG1_CARRYBORROW_FLG2_UD;
532
446
break;
533
447
case COUNTER_EVENT_INDEX:
534
-
next_irq_trigger = QUAD8_EVENT_INDEX;
448
+
flg_pins = FLG1_INDX_FLG2_E;
535
449
break;
536
450
default:
537
451
/* should never reach this path */
538
-
spin_unlock_irqrestore(&priv->lock, irqflags);
539
-
return -EINVAL;
452
+
ret = -EINVAL;
453
+
goto exit_unlock;
540
454
}
541
455
542
456
/* Enable IRQ line */
543
457
irq_enabled |= BIT(event_node->channel);
544
458
545
459
/* Skip configuration if it is the same as previously set */
546
-
if (priv->irq_trigger[event_node->channel] == next_irq_trigger)
460
+
if (flg_pins == u8_get_bits(priv->ior[event_node->channel], FLG_PINS))
547
461
continue;
548
462
549
463
/* Save new IRQ function configuration */
550
-
priv->irq_trigger[event_node->channel] = next_irq_trigger;
551
-
552
-
/* Load configuration to I/O Control Register */
553
-
ior_cfg = priv->ab_enable[event_node->channel] |
554
-
priv->preset_enable[event_node->channel] << 1 |
555
-
priv->irq_trigger[event_node->channel] << 3;
556
-
iowrite8(QUAD8_CTR_IOR | ior_cfg,
557
-
&priv->reg->channel[event_node->channel].control);
464
+
ret = quad8_control_register_update(priv->map, priv->ior, event_node->channel,
465
+
flg_pins, FLG_PINS);
466
+
if (ret)
467
+
goto exit_unlock;
558
468
}
559
469
560
-
iowrite8(irq_enabled, &priv->reg->index_interrupt);
470
+
ret = regmap_write(priv->map, QUAD8_INDEX_INTERRUPT, irq_enabled);
561
471
472
+
exit_unlock:
562
473
spin_unlock_irqrestore(&priv->lock, irqflags);
563
474
564
-
return 0;
475
+
return ret;
565
476
}
566
477
567
478
static int quad8_watch_validate(struct counter_device *counter,
···
600
531
const struct quad8 *const priv = counter_priv(counter);
601
532
const size_t channel_id = signal->id - 16;
602
533
603
-
*index_polarity = priv->index_polarity[channel_id];
534
+
*index_polarity = u8_get_bits(priv->idr[channel_id], INDEX_POLARITY);
604
535
605
536
return 0;
606
537
}
···
611
542
{
612
543
struct quad8 *const priv = counter_priv(counter);
613
544
const size_t channel_id = signal->id - 16;
614
-
u8 __iomem *const control = &priv->reg->channel[channel_id].control;
615
545
unsigned long irqflags;
616
-
unsigned int idr_cfg = index_polarity << 1;
546
+
int ret;
617
547
618
548
spin_lock_irqsave(&priv->lock, irqflags);
619
549
620
-
idr_cfg |= priv->synchronous_mode[channel_id];
621
-
622
-
priv->index_polarity[channel_id] = index_polarity;
623
-
624
-
/* Load Index Control configuration to Index Control Register */
625
-
iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
550
+
ret = quad8_control_register_update(priv->map, priv->idr, channel_id, index_polarity,
551
+
INDEX_POLARITY);
626
552
627
553
spin_unlock_irqrestore(&priv->lock, irqflags);
628
554
629
-
return 0;
555
+
return ret;
630
556
}
631
557
632
558
static int quad8_polarity_read(struct counter_device *counter,
···
635
571
if (err)
636
572
return err;
637
573
638
-
*polarity = (index_polarity) ? COUNTER_SIGNAL_POLARITY_POSITIVE :
574
+
*polarity = (index_polarity == POSITIVE_INDEX_POLARITY) ? COUNTER_SIGNAL_POLARITY_POSITIVE :
639
575
COUNTER_SIGNAL_POLARITY_NEGATIVE;
640
576
641
577
return 0;
···
645
581
struct counter_signal *signal,
646
582
enum counter_signal_polarity polarity)
647
583
{
648
-
const u32 pol = (polarity == COUNTER_SIGNAL_POLARITY_POSITIVE) ? 1 : 0;
584
+
const u32 pol = (polarity == COUNTER_SIGNAL_POLARITY_POSITIVE) ? POSITIVE_INDEX_POLARITY :
585
+
NEGATIVE_INDEX_POLARITY;
649
586
650
587
return quad8_index_polarity_set(counter, signal, pol);
651
588
}
···
663
598
const struct quad8 *const priv = counter_priv(counter);
664
599
const size_t channel_id = signal->id - 16;
665
600
666
-
*synchronous_mode = priv->synchronous_mode[channel_id];
601
+
*synchronous_mode = u8_get_bits(priv->idr[channel_id], INDEX_MODE);
667
602
668
603
return 0;
669
604
}
···
674
609
{
675
610
struct quad8 *const priv = counter_priv(counter);
676
611
const size_t channel_id = signal->id - 16;
677
-
u8 __iomem *const control = &priv->reg->channel[channel_id].control;
612
+
u8 quadrature_mode;
678
613
unsigned long irqflags;
679
-
unsigned int idr_cfg = synchronous_mode;
614
+
int ret;
680
615
681
616
spin_lock_irqsave(&priv->lock, irqflags);
682
617
683
-
idr_cfg |= priv->index_polarity[channel_id] << 1;
684
-
685
618
/* Index function must be non-synchronous in non-quadrature mode */
686
-
if (synchronous_mode && !priv->quadrature_mode[channel_id]) {
687
-
spin_unlock_irqrestore(&priv->lock, irqflags);
688
-
return -EINVAL;
619
+
quadrature_mode = u8_get_bits(priv->idr[channel_id], QUADRATURE_MODE);
620
+
if (synchronous_mode && quadrature_mode == NON_QUADRATURE) {
621
+
ret = -EINVAL;
622
+
goto exit_unlock;
689
623
}
690
624
691
-
priv->synchronous_mode[channel_id] = synchronous_mode;
625
+
ret = quad8_control_register_update(priv->map, priv->idr, channel_id, synchronous_mode,
626
+
INDEX_MODE);
692
627
693
-
/* Load Index Control configuration to Index Control Register */
694
-
iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
695
-
628
+
exit_unlock:
696
629
spin_unlock_irqrestore(&priv->lock, irqflags);
697
630
698
-
return 0;
631
+
return ret;
699
632
}
700
633
701
634
static int quad8_count_floor_read(struct counter_device *counter,
···
711
648
{
712
649
const struct quad8 *const priv = counter_priv(counter);
713
650
714
-
/* Map 104-QUAD-8 count mode to Generic Counter count mode */
715
-
switch (priv->count_mode[count->id]) {
716
-
case 0:
651
+
switch (u8_get_bits(priv->cmr[count->id], COUNT_MODE)) {
652
+
case NORMAL_COUNT:
717
653
*cnt_mode = COUNTER_COUNT_MODE_NORMAL;
718
654
break;
719
-
case 1:
655
+
case RANGE_LIMIT:
720
656
*cnt_mode = COUNTER_COUNT_MODE_RANGE_LIMIT;
721
657
break;
722
-
case 2:
658
+
case NON_RECYCLE_COUNT:
723
659
*cnt_mode = COUNTER_COUNT_MODE_NON_RECYCLE;
724
660
break;
725
-
case 3:
661
+
case MODULO_N:
726
662
*cnt_mode = COUNTER_COUNT_MODE_MODULO_N;
727
663
break;
728
664
}
···
735
673
{
736
674
struct quad8 *const priv = counter_priv(counter);
737
675
unsigned int count_mode;
738
-
unsigned int mode_cfg;
739
-
u8 __iomem *const control = &priv->reg->channel[count->id].control;
740
676
unsigned long irqflags;
677
+
int ret;
741
678
742
-
/* Map Generic Counter count mode to 104-QUAD-8 count mode */
743
679
switch (cnt_mode) {
744
680
case COUNTER_COUNT_MODE_NORMAL:
745
-
count_mode = 0;
681
+
count_mode = NORMAL_COUNT;
746
682
break;
747
683
case COUNTER_COUNT_MODE_RANGE_LIMIT:
748
-
count_mode = 1;
684
+
count_mode = RANGE_LIMIT;
749
685
break;
750
686
case COUNTER_COUNT_MODE_NON_RECYCLE:
751
-
count_mode = 2;
687
+
count_mode = NON_RECYCLE_COUNT;
752
688
break;
753
689
case COUNTER_COUNT_MODE_MODULO_N:
754
-
count_mode = 3;
690
+
count_mode = MODULO_N;
755
691
break;
756
692
default:
757
693
/* should never reach this path */
···
758
698
759
699
spin_lock_irqsave(&priv->lock, irqflags);
760
700
761
-
priv->count_mode[count->id] = count_mode;
762
-
763
-
/* Set count mode configuration value */
764
-
mode_cfg = count_mode << 1;
765
-
766
-
/* Add quadrature mode configuration */
767
-
if (priv->quadrature_mode[count->id])
768
-
mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3;
769
-
770
-
/* Load mode configuration to Counter Mode Register */
771
-
iowrite8(QUAD8_CTR_CMR | mode_cfg, control);
701
+
ret = quad8_control_register_update(priv->map, priv->cmr, count->id, count_mode,
702
+
COUNT_MODE);
772
703
773
704
spin_unlock_irqrestore(&priv->lock, irqflags);
774
705
775
-
return 0;
706
+
return ret;
776
707
}
777
708
778
709
static int quad8_count_enable_read(struct counter_device *counter,
···
771
720
{
772
721
const struct quad8 *const priv = counter_priv(counter);
773
722
774
-
*enable = priv->ab_enable[count->id];
723
+
*enable = u8_get_bits(priv->ior[count->id], AB_GATE);
775
724
776
725
return 0;
777
726
}
···
780
729
struct counter_count *count, u8 enable)
781
730
{
782
731
struct quad8 *const priv = counter_priv(counter);
783
-
u8 __iomem *const control = &priv->reg->channel[count->id].control;
784
732
unsigned long irqflags;
785
-
unsigned int ior_cfg;
733
+
int ret;
786
734
787
735
spin_lock_irqsave(&priv->lock, irqflags);
788
736
789
-
priv->ab_enable[count->id] = enable;
790
-
791
-
ior_cfg = enable | priv->preset_enable[count->id] << 1 |
792
-
priv->irq_trigger[count->id] << 3;
793
-
794
-
/* Load I/O control configuration */
795
-
iowrite8(QUAD8_CTR_IOR | ior_cfg, control);
737
+
ret = quad8_control_register_update(priv->map, priv->ior, count->id, enable, AB_GATE);
796
738
797
739
spin_unlock_irqrestore(&priv->lock, irqflags);
798
740
799
-
return 0;
741
+
return ret;
800
742
}
801
743
802
744
static const char *const quad8_noise_error_states[] = {
···
801
757
struct counter_count *count, u32 *noise_error)
802
758
{
803
759
const struct quad8 *const priv = counter_priv(counter);
804
-
u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control;
760
+
unsigned int flag;
761
+
int ret;
805
762
806
-
*noise_error = !!(ioread8(flag_addr) & QUAD8_FLAG_E);
763
+
ret = regmap_read(priv->map, QUAD8_CONTROL(count->id), &flag);
764
+
if (ret)
765
+
return ret;
766
+
*noise_error = u8_get_bits(flag, FLAG_E);
807
767
808
768
return 0;
809
769
}
···
822
774
return 0;
823
775
}
824
776
825
-
static void quad8_preset_register_set(struct quad8 *const priv, const int id,
826
-
const unsigned int preset)
827
-
{
828
-
struct channel_reg __iomem *const chan = priv->reg->channel + id;
829
-
int i;
830
-
831
-
priv->preset[id] = preset;
832
-
833
-
/* Reset Byte Pointer */
834
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
835
-
836
-
/* Set Preset Register */
837
-
for (i = 0; i < 3; i++)
838
-
iowrite8(preset >> (8 * i), &chan->data);
839
-
}
840
-
841
777
static int quad8_count_preset_write(struct counter_device *counter,
842
778
struct counter_count *count, u64 preset)
843
779
{
844
780
struct quad8 *const priv = counter_priv(counter);
845
781
unsigned long irqflags;
782
+
int ret;
846
783
847
784
if (preset > LS7267_CNTR_MAX)
848
785
return -ERANGE;
849
786
850
787
spin_lock_irqsave(&priv->lock, irqflags);
851
788
852
-
quad8_preset_register_set(priv, count->id, preset);
789
+
priv->preset[count->id] = preset;
790
+
ret = quad8_preset_register_set(priv, count->id, preset);
853
791
854
792
spin_unlock_irqrestore(&priv->lock, irqflags);
855
793
856
-
return 0;
794
+
return ret;
857
795
}
858
796
859
797
static int quad8_count_ceiling_read(struct counter_device *counter,
···
851
817
spin_lock_irqsave(&priv->lock, irqflags);
852
818
853
819
/* Range Limit and Modulo-N count modes use preset value as ceiling */
854
-
switch (priv->count_mode[count->id]) {
855
-
case 1:
856
-
case 3:
820
+
switch (u8_get_bits(priv->cmr[count->id], COUNT_MODE)) {
821
+
case RANGE_LIMIT:
822
+
case MODULO_N:
857
823
*ceiling = priv->preset[count->id];
858
824
break;
859
825
default:
···
871
837
{
872
838
struct quad8 *const priv = counter_priv(counter);
873
839
unsigned long irqflags;
840
+
int ret;
874
841
875
842
if (ceiling > LS7267_CNTR_MAX)
876
843
return -ERANGE;
···
879
844
spin_lock_irqsave(&priv->lock, irqflags);
880
845
881
846
/* Range Limit and Modulo-N count modes use preset value as ceiling */
882
-
switch (priv->count_mode[count->id]) {
883
-
case 1:
884
-
case 3:
885
-
quad8_preset_register_set(priv, count->id, ceiling);
886
-
spin_unlock_irqrestore(&priv->lock, irqflags);
887
-
return 0;
847
+
switch (u8_get_bits(priv->cmr[count->id], COUNT_MODE)) {
848
+
case RANGE_LIMIT:
849
+
case MODULO_N:
850
+
priv->preset[count->id] = ceiling;
851
+
ret = quad8_preset_register_set(priv, count->id, ceiling);
852
+
break;
853
+
default:
854
+
ret = -EINVAL;
855
+
break;
888
856
}
889
857
890
858
spin_unlock_irqrestore(&priv->lock, irqflags);
891
859
892
-
return -EINVAL;
860
+
return ret;
893
861
}
894
862
895
863
static int quad8_count_preset_enable_read(struct counter_device *counter,
···
901
863
{
902
864
const struct quad8 *const priv = counter_priv(counter);
903
865
904
-
*preset_enable = !priv->preset_enable[count->id];
866
+
/* Preset enable is active low in Input/Output Control register */
867
+
*preset_enable = !u8_get_bits(priv->ior[count->id], LOAD_PIN);
905
868
906
869
return 0;
907
870
}
···
912
873
u8 preset_enable)
913
874
{
914
875
struct quad8 *const priv = counter_priv(counter);
915
-
u8 __iomem *const control = &priv->reg->channel[count->id].control;
916
876
unsigned long irqflags;
917
-
unsigned int ior_cfg;
918
-
919
-
/* Preset enable is active low in Input/Output Control register */
920
-
preset_enable = !preset_enable;
877
+
int ret;
921
878
922
879
spin_lock_irqsave(&priv->lock, irqflags);
923
880
924
-
priv->preset_enable[count->id] = preset_enable;
925
-
926
-
ior_cfg = priv->ab_enable[count->id] | preset_enable << 1 |
927
-
priv->irq_trigger[count->id] << 3;
928
-
929
-
/* Load I/O control configuration to Input / Output Control Register */
930
-
iowrite8(QUAD8_CTR_IOR | ior_cfg, control);
881
+
/* Preset enable is active low in Input/Output Control register */
882
+
ret = quad8_control_register_update(priv->map, priv->ior, count->id, !preset_enable,
883
+
LOAD_PIN);
931
884
932
885
spin_unlock_irqrestore(&priv->lock, irqflags);
933
886
934
-
return 0;
887
+
return ret;
935
888
}
936
889
937
890
static int quad8_signal_cable_fault_read(struct counter_device *counter,
···
934
903
const size_t channel_id = signal->id / 2;
935
904
unsigned long irqflags;
936
905
bool disabled;
937
-
unsigned int status;
906
+
int ret;
938
907
939
908
spin_lock_irqsave(&priv->lock, irqflags);
940
909
···
945
914
return -EINVAL;
946
915
}
947
916
948
-
/* Logic 0 = cable fault */
949
-
status = ioread8(&priv->reg->cable_status);
917
+
ret = regmap_test_bits(priv->map, QUAD8_CABLE_STATUS, BIT(channel_id));
918
+
if (ret < 0) {
919
+
spin_unlock_irqrestore(&priv->lock, irqflags);
920
+
return ret;
921
+
}
950
922
951
923
spin_unlock_irqrestore(&priv->lock, irqflags);
952
924
953
-
/* Mask respective channel and invert logic */
954
-
*cable_fault = !(status & BIT(channel_id));
925
+
/* Logic 0 = cable fault */
926
+
*cable_fault = !ret;
955
927
956
928
return 0;
957
929
}
···
979
945
const size_t channel_id = signal->id / 2;
980
946
unsigned long irqflags;
981
947
unsigned int cable_fault_enable;
948
+
int ret;
982
949
983
950
spin_lock_irqsave(&priv->lock, irqflags);
984
951
···
991
956
/* Enable is active low in Differential Encoder Cable Status register */
992
957
cable_fault_enable = ~priv->cable_fault_enable;
993
958
994
-
iowrite8(cable_fault_enable, &priv->reg->cable_status);
959
+
ret = regmap_write(priv->map, QUAD8_CABLE_STATUS, cable_fault_enable);
995
960
996
961
spin_unlock_irqrestore(&priv->lock, irqflags);
997
962
998
-
return 0;
963
+
return ret;
999
964
}
1000
965
1001
966
static int quad8_signal_fck_prescaler_read(struct counter_device *counter,
···
1009
974
return 0;
1010
975
}
1011
976
977
+
static int quad8_filter_clock_prescaler_set(struct quad8 *const priv, const size_t id,
978
+
const u8 prescaler)
979
+
{
980
+
int ret;
981
+
982
+
ret = regmap_write(priv->map, QUAD8_CONTROL(id), SELECT_RLD | RESET_BP);
983
+
if (ret)
984
+
return ret;
985
+
ret = regmap_write(priv->map, QUAD8_DATA(id), prescaler);
986
+
if (ret)
987
+
return ret;
988
+
return regmap_write(priv->map, QUAD8_CONTROL(id), SELECT_RLD | TRANSFER_PR0_TO_PSC);
989
+
}
990
+
1012
991
static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
1013
992
struct counter_signal *signal,
1014
993
u8 prescaler)
1015
994
{
1016
995
struct quad8 *const priv = counter_priv(counter);
1017
996
const size_t channel_id = signal->id / 2;
1018
-
struct channel_reg __iomem *const chan = priv->reg->channel + channel_id;
1019
997
unsigned long irqflags;
998
+
int ret;
1020
999
1021
1000
spin_lock_irqsave(&priv->lock, irqflags);
1022
1001
1023
1002
priv->fck_prescaler[channel_id] = prescaler;
1024
-
1025
-
/* Reset Byte Pointer */
1026
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
1027
-
1028
-
/* Set filter clock factor */
1029
-
iowrite8(prescaler, &chan->data);
1030
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
1031
-
&chan->control);
1003
+
ret = quad8_filter_clock_prescaler_set(priv, channel_id, prescaler);
1032
1004
1033
1005
spin_unlock_irqrestore(&priv->lock, irqflags);
1034
1006
1035
-
return 0;
1007
+
return ret;
1036
1008
}
1037
1009
1038
1010
static struct counter_comp quad8_signal_ext[] = {
···
1192
1150
{
1193
1151
struct counter_device *counter = private;
1194
1152
struct quad8 *const priv = counter_priv(counter);
1153
+
unsigned int status;
1195
1154
unsigned long irq_status;
1196
1155
unsigned long channel;
1156
+
unsigned int flg_pins;
1197
1157
u8 event;
1158
+
int ret;
1198
1159
1199
-
irq_status = ioread8(&priv->reg->interrupt_status);
1200
-
if (!irq_status)
1160
+
ret = regmap_read(priv->map, QUAD8_INTERRUPT_STATUS, &status);
1161
+
if (ret)
1162
+
return ret;
1163
+
if (!status)
1201
1164
return IRQ_NONE;
1202
1165
1166
+
irq_status = status;
1203
1167
for_each_set_bit(channel, &irq_status, QUAD8_NUM_COUNTERS) {
1204
-
switch (priv->irq_trigger[channel]) {
1205
-
case QUAD8_EVENT_CARRY:
1168
+
flg_pins = u8_get_bits(priv->ior[channel], FLG_PINS);
1169
+
switch (flg_pins) {
1170
+
case FLG1_CARRY_FLG2_BORROW:
1206
1171
event = COUNTER_EVENT_OVERFLOW;
1207
1172
break;
1208
-
case QUAD8_EVENT_COMPARE:
1173
+
case FLG1_COMPARE_FLG2_BORROW:
1209
1174
event = COUNTER_EVENT_THRESHOLD;
1210
1175
break;
1211
-
case QUAD8_EVENT_CARRY_BORROW:
1176
+
case FLG1_CARRYBORROW_FLG2_UD:
1212
1177
event = COUNTER_EVENT_OVERFLOW_UNDERFLOW;
1213
1178
break;
1214
-
case QUAD8_EVENT_INDEX:
1179
+
case FLG1_INDX_FLG2_E:
1215
1180
event = COUNTER_EVENT_INDEX;
1216
1181
break;
1217
1182
default:
1218
1183
/* should never reach this path */
1219
1184
WARN_ONCE(true, "invalid interrupt trigger function %u configured for channel %lu\n",
1220
-
priv->irq_trigger[channel], channel);
1185
+
flg_pins, channel);
1221
1186
continue;
1222
1187
}
1223
1188
1224
1189
counter_push_event(counter, event, channel);
1225
1190
}
1226
1191
1227
-
/* Clear pending interrupts on device */
1228
-
iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper);
1192
+
ret = regmap_write(priv->map, QUAD8_CHANNEL_OPERATION, CLEAR_PENDING_INTERRUPTS);
1193
+
if (ret)
1194
+
return ret;
1229
1195
1230
1196
return IRQ_HANDLED;
1231
1197
}
1232
1198
1233
-
static void quad8_init_counter(struct channel_reg __iomem *const chan)
1199
+
static int quad8_init_counter(struct quad8 *const priv, const size_t channel)
1234
1200
{
1235
-
unsigned long i;
1201
+
int ret;
1236
1202
1237
-
/* Reset Byte Pointer */
1238
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
1239
-
/* Reset filter clock factor */
1240
-
iowrite8(0, &chan->data);
1241
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
1242
-
&chan->control);
1243
-
/* Reset Byte Pointer */
1244
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
1245
-
/* Reset Preset Register */
1246
-
for (i = 0; i < 3; i++)
1247
-
iowrite8(0x00, &chan->data);
1248
-
/* Reset Borrow, Carry, Compare, and Sign flags */
1249
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control);
1250
-
/* Reset Error flag */
1251
-
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control);
1203
+
ret = quad8_filter_clock_prescaler_set(priv, channel, 0);
1204
+
if (ret)
1205
+
return ret;
1206
+
ret = quad8_preset_register_set(priv, channel, 0);
1207
+
if (ret)
1208
+
return ret;
1209
+
ret = quad8_flag_register_reset(priv, channel);
1210
+
if (ret)
1211
+
return ret;
1212
+
1252
1213
/* Binary encoding; Normal count; non-quadrature mode */
1253
-
iowrite8(QUAD8_CTR_CMR, &chan->control);
1214
+
priv->cmr[channel] = SELECT_CMR | BINARY | u8_encode_bits(NORMAL_COUNT, COUNT_MODE) |
1215
+
u8_encode_bits(NON_QUADRATURE, QUADRATURE_MODE);
1216
+
ret = regmap_write(priv->map, QUAD8_CONTROL(channel), priv->cmr[channel]);
1217
+
if (ret)
1218
+
return ret;
1219
+
1254
1220
/* Disable A and B inputs; preset on index; FLG1 as Carry */
1255
-
iowrite8(QUAD8_CTR_IOR, &chan->control);
1221
+
priv->ior[channel] = SELECT_IOR | DISABLE_AB | u8_encode_bits(LOAD_CNTR, LOAD_PIN) |
1222
+
u8_encode_bits(FLG1_CARRY_FLG2_BORROW, FLG_PINS);
1223
+
ret = regmap_write(priv->map, QUAD8_CONTROL(channel), priv->ior[channel]);
1224
+
if (ret)
1225
+
return ret;
1226
+
1256
1227
/* Disable index function; negative index polarity */
1257
-
iowrite8(QUAD8_CTR_IDR, &chan->control);
1228
+
priv->idr[channel] = SELECT_IDR | u8_encode_bits(DISABLE_INDEX_MODE, INDEX_MODE) |
1229
+
u8_encode_bits(NEGATIVE_INDEX_POLARITY, INDEX_POLARITY);
1230
+
return regmap_write(priv->map, QUAD8_CONTROL(channel), priv->idr[channel]);
1258
1231
}
1259
1232
1260
1233
static int quad8_probe(struct device *dev, unsigned int id)
1261
1234
{
1262
1235
struct counter_device *counter;
1263
1236
struct quad8 *priv;
1237
+
void __iomem *regs;
1264
1238
unsigned long i;
1265
-
int err;
1239
+
int ret;
1266
1240
1267
1241
if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) {
1268
1242
dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
···
1291
1233
return -ENOMEM;
1292
1234
priv = counter_priv(counter);
1293
1235
1294
-
priv->reg = devm_ioport_map(dev, base[id], QUAD8_EXTENT);
1295
-
if (!priv->reg)
1236
+
regs = devm_ioport_map(dev, base[id], QUAD8_EXTENT);
1237
+
if (!regs)
1296
1238
return -ENOMEM;
1239
+
1240
+
priv->map = devm_regmap_init_mmio(dev, regs, &quad8_regmap_config);
1241
+
if (IS_ERR(priv->map))
1242
+
return dev_err_probe(dev, PTR_ERR(priv->map),
1243
+
"Unable to initialize register map\n");
1297
1244
1298
1245
/* Initialize Counter device and driver data */
1299
1246
counter->name = dev_name(dev);
···
1312
1249
spin_lock_init(&priv->lock);
1313
1250
1314
1251
/* Reset Index/Interrupt Register */
1315
-
iowrite8(0x00, &priv->reg->index_interrupt);
1252
+
ret = regmap_write(priv->map, QUAD8_INDEX_INTERRUPT, 0x00);
1253
+
if (ret)
1254
+
return ret;
1316
1255
/* Reset all counters and disable interrupt function */
1317
-
iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, &priv->reg->channel_oper);
1256
+
ret = regmap_write(priv->map, QUAD8_CHANNEL_OPERATION,
1257
+
RESET_COUNTERS | DISABLE_INTERRUPT_FUNCTION);
1258
+
if (ret)
1259
+
return ret;
1318
1260
/* Set initial configuration for all counters */
1319
-
for (i = 0; i < QUAD8_NUM_COUNTERS; i++)
1320
-
quad8_init_counter(priv->reg->channel + i);
1261
+
for (i = 0; i < QUAD8_NUM_COUNTERS; i++) {
1262
+
ret = quad8_init_counter(priv, i);
1263
+
if (ret)
1264
+
return ret;
1265
+
}
1321
1266
/* Disable Differential Encoder Cable Status for all channels */
1322
-
iowrite8(0xFF, &priv->reg->cable_status);
1267
+
ret = regmap_write(priv->map, QUAD8_CABLE_STATUS, GENMASK(7, 0));
1268
+
if (ret)
1269
+
return ret;
1323
1270
/* Enable all counters and enable interrupt function */
1324
-
iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper);
1271
+
ret = regmap_write(priv->map, QUAD8_CHANNEL_OPERATION,
1272
+
ENABLE_COUNTERS | ENABLE_INTERRUPT_FUNCTION);
1273
+
if (ret)
1274
+
return ret;
1325
1275
1326
-
err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler,
1276
+
ret = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler,
1327
1277
IRQF_SHARED, counter->name, counter);
1328
-
if (err)
1329
-
return err;
1278
+
if (ret)
1279
+
return ret;
1330
1280
1331
-
err = devm_counter_add(dev, counter);
1332
-
if (err < 0)
1333
-
return dev_err_probe(dev, err, "Failed to add counter\n");
1281
+
ret = devm_counter_add(dev, counter);
1282
+
if (ret < 0)
1283
+
return dev_err_probe(dev, ret, "Failed to add counter\n");
1334
1284
1335
1285
return 0;
1336
1286
}
+20
-3
drivers/counter/Kconfig
+20
-3
drivers/counter/Kconfig
···
10
10
interface. You only need to enable this, if you also want to enable
11
11
one or more of the counter device drivers below.
12
12
13
+
config I8254
14
+
tristate
15
+
select COUNTER
16
+
select REGMAP
17
+
help
18
+
Enables support for the i8254 interface library functions. The i8254
19
+
interface library provides functions to facilitate communication with
20
+
interfaces compatible with the venerable Intel 8254 Programmable
21
+
Interval Timer (PIT). The Intel 825x family of chips was first
22
+
released in the early 1980s but compatible interfaces are nowadays
23
+
typically found embedded in larger VLSI processing chips and FPGA
24
+
components.
25
+
26
+
If built as a module its name will be i8254.
27
+
13
28
if COUNTER
14
29
15
30
config 104_QUAD_8
16
31
tristate "ACCES 104-QUAD-8 driver"
17
32
depends on (PC104 && X86) || COMPILE_TEST
33
+
depends on HAS_IOPORT_MAP
18
34
select ISA_BUS_API
35
+
select REGMAP_MMIO
19
36
help
20
37
Say yes here to build support for the ACCES 104-QUAD-8 quadrature
21
38
encoder counter/interface device family (104-QUAD-8, 104-QUAD-4).
22
39
23
40
A counter's respective error flag may be cleared by performing a write
24
-
operation on the respective count value attribute. Although the
25
-
104-QUAD-8 counters have a 25-bit range, only the lower 24 bits may be
26
-
set, either directly or via the counter's preset attribute.
41
+
operation on the respective count value attribute. The 104-QUAD-8
42
+
counters may be set either directly or via the counter's preset
43
+
attribute.
27
44
28
45
The base port addresses for the devices may be configured via the base
29
46
array module parameter. The interrupt line numbers for the devices may
+1
drivers/counter/Makefile
+1
drivers/counter/Makefile
+7
-1
drivers/counter/counter-sysfs.c
+7
-1
drivers/counter/counter-sysfs.c
···
88
88
[COUNTER_COUNT_MODE_NORMAL] = "normal",
89
89
[COUNTER_COUNT_MODE_RANGE_LIMIT] = "range limit",
90
90
[COUNTER_COUNT_MODE_NON_RECYCLE] = "non-recycle",
91
-
[COUNTER_COUNT_MODE_MODULO_N] = "modulo-n"
91
+
[COUNTER_COUNT_MODE_MODULO_N] = "modulo-n",
92
+
[COUNTER_COUNT_MODE_INTERRUPT_ON_TERMINAL_COUNT] = "interrupt on terminal count",
93
+
[COUNTER_COUNT_MODE_HARDWARE_RETRIGGERABLE_ONESHOT] = "hardware retriggerable one-shot",
94
+
[COUNTER_COUNT_MODE_RATE_GENERATOR] = "rate generator",
95
+
[COUNTER_COUNT_MODE_SQUARE_WAVE_MODE] = "square wave mode",
96
+
[COUNTER_COUNT_MODE_SOFTWARE_TRIGGERED_STROBE] = "software triggered strobe",
97
+
[COUNTER_COUNT_MODE_HARDWARE_TRIGGERED_STROBE] = "hardware triggered strobe",
92
98
};
93
99
94
100
static const char *const counter_signal_polarity_str[] = {
+447
drivers/counter/i8254.c
+447
drivers/counter/i8254.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Intel 8254 Programmable Interval Timer
4
+
* Copyright (C) William Breathitt Gray
5
+
*/
6
+
#include <linux/bitfield.h>
7
+
#include <linux/bits.h>
8
+
#include <linux/counter.h>
9
+
#include <linux/device.h>
10
+
#include <linux/err.h>
11
+
#include <linux/export.h>
12
+
#include <linux/i8254.h>
13
+
#include <linux/limits.h>
14
+
#include <linux/module.h>
15
+
#include <linux/mutex.h>
16
+
#include <linux/regmap.h>
17
+
18
+
#include <asm/unaligned.h>
19
+
20
+
#define I8254_COUNTER_REG(_counter) (_counter)
21
+
#define I8254_CONTROL_REG 0x3
22
+
23
+
#define I8254_SC GENMASK(7, 6)
24
+
#define I8254_RW GENMASK(5, 4)
25
+
#define I8254_M GENMASK(3, 1)
26
+
#define I8254_CONTROL(_sc, _rw, _m) \
27
+
(u8_encode_bits(_sc, I8254_SC) | u8_encode_bits(_rw, I8254_RW) | \
28
+
u8_encode_bits(_m, I8254_M))
29
+
30
+
#define I8254_RW_TWO_BYTE 0x3
31
+
#define I8254_MODE_INTERRUPT_ON_TERMINAL_COUNT 0
32
+
#define I8254_MODE_HARDWARE_RETRIGGERABLE_ONESHOT 1
33
+
#define I8254_MODE_RATE_GENERATOR 2
34
+
#define I8254_MODE_SQUARE_WAVE_MODE 3
35
+
#define I8254_MODE_SOFTWARE_TRIGGERED_STROBE 4
36
+
#define I8254_MODE_HARDWARE_TRIGGERED_STROBE 5
37
+
38
+
#define I8254_COUNTER_LATCH(_counter) I8254_CONTROL(_counter, 0x0, 0x0)
39
+
#define I8254_PROGRAM_COUNTER(_counter, _mode) I8254_CONTROL(_counter, I8254_RW_TWO_BYTE, _mode)
40
+
41
+
#define I8254_NUM_COUNTERS 3
42
+
43
+
/**
44
+
* struct i8254 - I8254 device private data structure
45
+
* @lock: synchronization lock to prevent I/O race conditions
46
+
* @preset: array of Counter Register states
47
+
* @out_mode: array of mode configuration states
48
+
* @map: Regmap for the device
49
+
*/
50
+
struct i8254 {
51
+
struct mutex lock;
52
+
u16 preset[I8254_NUM_COUNTERS];
53
+
u8 out_mode[I8254_NUM_COUNTERS];
54
+
struct regmap *map;
55
+
};
56
+
57
+
static int i8254_count_read(struct counter_device *const counter, struct counter_count *const count,
58
+
u64 *const val)
59
+
{
60
+
struct i8254 *const priv = counter_priv(counter);
61
+
int ret;
62
+
u8 value[2];
63
+
64
+
mutex_lock(&priv->lock);
65
+
66
+
ret = regmap_write(priv->map, I8254_CONTROL_REG, I8254_COUNTER_LATCH(count->id));
67
+
if (ret) {
68
+
mutex_unlock(&priv->lock);
69
+
return ret;
70
+
}
71
+
ret = regmap_noinc_read(priv->map, I8254_COUNTER_REG(count->id), value, sizeof(value));
72
+
if (ret) {
73
+
mutex_unlock(&priv->lock);
74
+
return ret;
75
+
}
76
+
77
+
mutex_unlock(&priv->lock);
78
+
79
+
*val = get_unaligned_le16(value);
80
+
81
+
return ret;
82
+
}
83
+
84
+
static int i8254_function_read(struct counter_device *const counter,
85
+
struct counter_count *const count,
86
+
enum counter_function *const function)
87
+
{
88
+
*function = COUNTER_FUNCTION_DECREASE;
89
+
return 0;
90
+
}
91
+
92
+
#define I8254_SYNAPSES_PER_COUNT 2
93
+
#define I8254_SIGNAL_ID_CLK 0
94
+
#define I8254_SIGNAL_ID_GATE 1
95
+
96
+
static int i8254_action_read(struct counter_device *const counter,
97
+
struct counter_count *const count,
98
+
struct counter_synapse *const synapse,
99
+
enum counter_synapse_action *const action)
100
+
{
101
+
struct i8254 *const priv = counter_priv(counter);
102
+
103
+
switch (synapse->signal->id % I8254_SYNAPSES_PER_COUNT) {
104
+
case I8254_SIGNAL_ID_CLK:
105
+
*action = COUNTER_SYNAPSE_ACTION_FALLING_EDGE;
106
+
return 0;
107
+
case I8254_SIGNAL_ID_GATE:
108
+
switch (priv->out_mode[count->id]) {
109
+
case I8254_MODE_HARDWARE_RETRIGGERABLE_ONESHOT:
110
+
case I8254_MODE_RATE_GENERATOR:
111
+
case I8254_MODE_SQUARE_WAVE_MODE:
112
+
case I8254_MODE_HARDWARE_TRIGGERED_STROBE:
113
+
*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
114
+
return 0;
115
+
default:
116
+
*action = COUNTER_SYNAPSE_ACTION_NONE;
117
+
return 0;
118
+
}
119
+
default:
120
+
/* should never reach this path */
121
+
return -EINVAL;
122
+
}
123
+
}
124
+
125
+
static int i8254_count_ceiling_read(struct counter_device *const counter,
126
+
struct counter_count *const count, u64 *const ceiling)
127
+
{
128
+
struct i8254 *const priv = counter_priv(counter);
129
+
130
+
mutex_lock(&priv->lock);
131
+
132
+
switch (priv->out_mode[count->id]) {
133
+
case I8254_MODE_RATE_GENERATOR:
134
+
/* Rate Generator decrements 0 by one and the counter "wraps around" */
135
+
*ceiling = (priv->preset[count->id] == 0) ? U16_MAX : priv->preset[count->id];
136
+
break;
137
+
case I8254_MODE_SQUARE_WAVE_MODE:
138
+
if (priv->preset[count->id] % 2)
139
+
*ceiling = priv->preset[count->id] - 1;
140
+
else if (priv->preset[count->id] == 0)
141
+
/* Square Wave Mode decrements 0 by two and the counter "wraps around" */
142
+
*ceiling = U16_MAX - 1;
143
+
else
144
+
*ceiling = priv->preset[count->id];
145
+
break;
146
+
default:
147
+
*ceiling = U16_MAX;
148
+
break;
149
+
}
150
+
151
+
mutex_unlock(&priv->lock);
152
+
153
+
return 0;
154
+
}
155
+
156
+
static int i8254_count_mode_read(struct counter_device *const counter,
157
+
struct counter_count *const count,
158
+
enum counter_count_mode *const count_mode)
159
+
{
160
+
const struct i8254 *const priv = counter_priv(counter);
161
+
162
+
switch (priv->out_mode[count->id]) {
163
+
case I8254_MODE_INTERRUPT_ON_TERMINAL_COUNT:
164
+
*count_mode = COUNTER_COUNT_MODE_INTERRUPT_ON_TERMINAL_COUNT;
165
+
return 0;
166
+
case I8254_MODE_HARDWARE_RETRIGGERABLE_ONESHOT:
167
+
*count_mode = COUNTER_COUNT_MODE_HARDWARE_RETRIGGERABLE_ONESHOT;
168
+
return 0;
169
+
case I8254_MODE_RATE_GENERATOR:
170
+
*count_mode = COUNTER_COUNT_MODE_RATE_GENERATOR;
171
+
return 0;
172
+
case I8254_MODE_SQUARE_WAVE_MODE:
173
+
*count_mode = COUNTER_COUNT_MODE_SQUARE_WAVE_MODE;
174
+
return 0;
175
+
case I8254_MODE_SOFTWARE_TRIGGERED_STROBE:
176
+
*count_mode = COUNTER_COUNT_MODE_SOFTWARE_TRIGGERED_STROBE;
177
+
return 0;
178
+
case I8254_MODE_HARDWARE_TRIGGERED_STROBE:
179
+
*count_mode = COUNTER_COUNT_MODE_HARDWARE_TRIGGERED_STROBE;
180
+
return 0;
181
+
default:
182
+
/* should never reach this path */
183
+
return -EINVAL;
184
+
}
185
+
}
186
+
187
+
static int i8254_count_mode_write(struct counter_device *const counter,
188
+
struct counter_count *const count,
189
+
const enum counter_count_mode count_mode)
190
+
{
191
+
struct i8254 *const priv = counter_priv(counter);
192
+
u8 out_mode;
193
+
int ret;
194
+
195
+
switch (count_mode) {
196
+
case COUNTER_COUNT_MODE_INTERRUPT_ON_TERMINAL_COUNT:
197
+
out_mode = I8254_MODE_INTERRUPT_ON_TERMINAL_COUNT;
198
+
break;
199
+
case COUNTER_COUNT_MODE_HARDWARE_RETRIGGERABLE_ONESHOT:
200
+
out_mode = I8254_MODE_HARDWARE_RETRIGGERABLE_ONESHOT;
201
+
break;
202
+
case COUNTER_COUNT_MODE_RATE_GENERATOR:
203
+
out_mode = I8254_MODE_RATE_GENERATOR;
204
+
break;
205
+
case COUNTER_COUNT_MODE_SQUARE_WAVE_MODE:
206
+
out_mode = I8254_MODE_SQUARE_WAVE_MODE;
207
+
break;
208
+
case COUNTER_COUNT_MODE_SOFTWARE_TRIGGERED_STROBE:
209
+
out_mode = I8254_MODE_SOFTWARE_TRIGGERED_STROBE;
210
+
break;
211
+
case COUNTER_COUNT_MODE_HARDWARE_TRIGGERED_STROBE:
212
+
out_mode = I8254_MODE_HARDWARE_TRIGGERED_STROBE;
213
+
break;
214
+
default:
215
+
/* should never reach this path */
216
+
return -EINVAL;
217
+
}
218
+
219
+
mutex_lock(&priv->lock);
220
+
221
+
/* Counter Register is cleared when the counter is programmed */
222
+
priv->preset[count->id] = 0;
223
+
priv->out_mode[count->id] = out_mode;
224
+
ret = regmap_write(priv->map, I8254_CONTROL_REG,
225
+
I8254_PROGRAM_COUNTER(count->id, out_mode));
226
+
227
+
mutex_unlock(&priv->lock);
228
+
229
+
return ret;
230
+
}
231
+
232
+
static int i8254_count_floor_read(struct counter_device *const counter,
233
+
struct counter_count *const count, u64 *const floor)
234
+
{
235
+
struct i8254 *const priv = counter_priv(counter);
236
+
237
+
mutex_lock(&priv->lock);
238
+
239
+
switch (priv->out_mode[count->id]) {
240
+
case I8254_MODE_RATE_GENERATOR:
241
+
/* counter is always reloaded after 1, but 0 is a possible reload value */
242
+
*floor = (priv->preset[count->id] == 0) ? 0 : 1;
243
+
break;
244
+
case I8254_MODE_SQUARE_WAVE_MODE:
245
+
/* counter is always reloaded after 2 for even preset values */
246
+
*floor = (priv->preset[count->id] % 2 || priv->preset[count->id] == 0) ? 0 : 2;
247
+
break;
248
+
default:
249
+
*floor = 0;
250
+
break;
251
+
}
252
+
253
+
mutex_unlock(&priv->lock);
254
+
255
+
return 0;
256
+
}
257
+
258
+
static int i8254_count_preset_read(struct counter_device *const counter,
259
+
struct counter_count *const count, u64 *const preset)
260
+
{
261
+
const struct i8254 *const priv = counter_priv(counter);
262
+
263
+
*preset = priv->preset[count->id];
264
+
265
+
return 0;
266
+
}
267
+
268
+
static int i8254_count_preset_write(struct counter_device *const counter,
269
+
struct counter_count *const count, const u64 preset)
270
+
{
271
+
struct i8254 *const priv = counter_priv(counter);
272
+
int ret;
273
+
u8 value[2];
274
+
275
+
if (preset > U16_MAX)
276
+
return -ERANGE;
277
+
278
+
mutex_lock(&priv->lock);
279
+
280
+
if (priv->out_mode[count->id] == I8254_MODE_RATE_GENERATOR ||
281
+
priv->out_mode[count->id] == I8254_MODE_SQUARE_WAVE_MODE) {
282
+
if (preset == 1) {
283
+
mutex_unlock(&priv->lock);
284
+
return -EINVAL;
285
+
}
286
+
}
287
+
288
+
priv->preset[count->id] = preset;
289
+
290
+
put_unaligned_le16(preset, value);
291
+
ret = regmap_noinc_write(priv->map, I8254_COUNTER_REG(count->id), value, 2);
292
+
293
+
mutex_unlock(&priv->lock);
294
+
295
+
return ret;
296
+
}
297
+
298
+
static int i8254_init_hw(struct regmap *const map)
299
+
{
300
+
unsigned long i;
301
+
int ret;
302
+
303
+
for (i = 0; i < I8254_NUM_COUNTERS; i++) {
304
+
/* Initialize each counter to Mode 0 */
305
+
ret = regmap_write(map, I8254_CONTROL_REG,
306
+
I8254_PROGRAM_COUNTER(i, I8254_MODE_INTERRUPT_ON_TERMINAL_COUNT));
307
+
if (ret)
308
+
return ret;
309
+
}
310
+
311
+
return 0;
312
+
}
313
+
314
+
static const struct counter_ops i8254_ops = {
315
+
.count_read = i8254_count_read,
316
+
.function_read = i8254_function_read,
317
+
.action_read = i8254_action_read,
318
+
};
319
+
320
+
#define I8254_SIGNAL(_id, _name) { \
321
+
.id = (_id), \
322
+
.name = (_name), \
323
+
}
324
+
325
+
static struct counter_signal i8254_signals[] = {
326
+
I8254_SIGNAL(0, "CLK 0"), I8254_SIGNAL(1, "GATE 0"),
327
+
I8254_SIGNAL(2, "CLK 1"), I8254_SIGNAL(3, "GATE 1"),
328
+
I8254_SIGNAL(4, "CLK 2"), I8254_SIGNAL(5, "GATE 2"),
329
+
};
330
+
331
+
static const enum counter_synapse_action i8254_clk_actions[] = {
332
+
COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
333
+
};
334
+
static const enum counter_synapse_action i8254_gate_actions[] = {
335
+
COUNTER_SYNAPSE_ACTION_NONE,
336
+
COUNTER_SYNAPSE_ACTION_RISING_EDGE,
337
+
};
338
+
339
+
#define I8254_SYNAPSES_BASE(_id) ((_id) * I8254_SYNAPSES_PER_COUNT)
340
+
#define I8254_SYNAPSE_CLK(_id) { \
341
+
.actions_list = i8254_clk_actions, \
342
+
.num_actions = ARRAY_SIZE(i8254_clk_actions), \
343
+
.signal = &i8254_signals[I8254_SYNAPSES_BASE(_id) + 0], \
344
+
}
345
+
#define I8254_SYNAPSE_GATE(_id) { \
346
+
.actions_list = i8254_gate_actions, \
347
+
.num_actions = ARRAY_SIZE(i8254_gate_actions), \
348
+
.signal = &i8254_signals[I8254_SYNAPSES_BASE(_id) + 1], \
349
+
}
350
+
351
+
static struct counter_synapse i8254_synapses[] = {
352
+
I8254_SYNAPSE_CLK(0), I8254_SYNAPSE_GATE(0),
353
+
I8254_SYNAPSE_CLK(1), I8254_SYNAPSE_GATE(1),
354
+
I8254_SYNAPSE_CLK(2), I8254_SYNAPSE_GATE(2),
355
+
};
356
+
357
+
static const enum counter_function i8254_functions_list[] = {
358
+
COUNTER_FUNCTION_DECREASE,
359
+
};
360
+
361
+
static const enum counter_count_mode i8254_count_modes[] = {
362
+
COUNTER_COUNT_MODE_INTERRUPT_ON_TERMINAL_COUNT,
363
+
COUNTER_COUNT_MODE_HARDWARE_RETRIGGERABLE_ONESHOT,
364
+
COUNTER_COUNT_MODE_RATE_GENERATOR,
365
+
COUNTER_COUNT_MODE_SQUARE_WAVE_MODE,
366
+
COUNTER_COUNT_MODE_SOFTWARE_TRIGGERED_STROBE,
367
+
COUNTER_COUNT_MODE_HARDWARE_TRIGGERED_STROBE,
368
+
};
369
+
370
+
static DEFINE_COUNTER_AVAILABLE(i8254_count_modes_available, i8254_count_modes);
371
+
372
+
static struct counter_comp i8254_count_ext[] = {
373
+
COUNTER_COMP_CEILING(i8254_count_ceiling_read, NULL),
374
+
COUNTER_COMP_COUNT_MODE(i8254_count_mode_read, i8254_count_mode_write,
375
+
i8254_count_modes_available),
376
+
COUNTER_COMP_FLOOR(i8254_count_floor_read, NULL),
377
+
COUNTER_COMP_PRESET(i8254_count_preset_read, i8254_count_preset_write),
378
+
};
379
+
380
+
#define I8254_COUNT(_id, _name) { \
381
+
.id = (_id), \
382
+
.name = (_name), \
383
+
.functions_list = i8254_functions_list, \
384
+
.num_functions = ARRAY_SIZE(i8254_functions_list), \
385
+
.synapses = &i8254_synapses[I8254_SYNAPSES_BASE(_id)], \
386
+
.num_synapses = I8254_SYNAPSES_PER_COUNT, \
387
+
.ext = i8254_count_ext, \
388
+
.num_ext = ARRAY_SIZE(i8254_count_ext) \
389
+
}
390
+
391
+
static struct counter_count i8254_counts[I8254_NUM_COUNTERS] = {
392
+
I8254_COUNT(0, "Counter 0"), I8254_COUNT(1, "Counter 1"), I8254_COUNT(2, "Counter 2"),
393
+
};
394
+
395
+
/**
396
+
* devm_i8254_regmap_register - Register an i8254 Counter device
397
+
* @dev: device that is registering this i8254 Counter device
398
+
* @config: configuration for i8254_regmap_config
399
+
*
400
+
* Registers an Intel 8254 Programmable Interval Timer Counter device. Returns 0 on success and
401
+
* negative error number on failure.
402
+
*/
403
+
int devm_i8254_regmap_register(struct device *const dev,
404
+
const struct i8254_regmap_config *const config)
405
+
{
406
+
struct counter_device *counter;
407
+
struct i8254 *priv;
408
+
int err;
409
+
410
+
if (!config->parent)
411
+
return -EINVAL;
412
+
413
+
if (!config->map)
414
+
return -EINVAL;
415
+
416
+
counter = devm_counter_alloc(dev, sizeof(*priv));
417
+
if (!counter)
418
+
return -ENOMEM;
419
+
priv = counter_priv(counter);
420
+
priv->map = config->map;
421
+
422
+
counter->name = dev_name(config->parent);
423
+
counter->parent = config->parent;
424
+
counter->ops = &i8254_ops;
425
+
counter->counts = i8254_counts;
426
+
counter->num_counts = ARRAY_SIZE(i8254_counts);
427
+
counter->signals = i8254_signals;
428
+
counter->num_signals = ARRAY_SIZE(i8254_signals);
429
+
430
+
mutex_init(&priv->lock);
431
+
432
+
err = i8254_init_hw(priv->map);
433
+
if (err)
434
+
return err;
435
+
436
+
err = devm_counter_add(dev, counter);
437
+
if (err < 0)
438
+
return dev_err_probe(dev, err, "Failed to add counter\n");
439
+
440
+
return 0;
441
+
}
442
+
EXPORT_SYMBOL_NS_GPL(devm_i8254_regmap_register, I8254);
443
+
444
+
MODULE_AUTHOR("William Breathitt Gray");
445
+
MODULE_DESCRIPTION("Intel 8254 Programmable Interval Timer");
446
+
MODULE_LICENSE("GPL");
447
+
MODULE_IMPORT_NS(COUNTER);
+3
drivers/counter/stm32-timer-cnt.c
+3
drivers/counter/stm32-timer-cnt.c
+1
drivers/extcon/Kconfig
+1
drivers/extcon/Kconfig
+1
-1
drivers/extcon/extcon-axp288.c
+1
-1
drivers/extcon/extcon-axp288.c
···
393
393
adev = acpi_dev_get_first_match_dev("INT3496", NULL, -1);
394
394
if (adev) {
395
395
info->id_extcon = extcon_get_extcon_dev(acpi_dev_name(adev));
396
-
put_device(&adev->dev);
396
+
acpi_dev_put(adev);
397
397
if (IS_ERR(info->id_extcon))
398
398
return PTR_ERR(info->id_extcon);
399
399
+1
-1
drivers/extcon/extcon-fsa9480.c
+1
-1
drivers/extcon/extcon-fsa9480.c
-1
drivers/extcon/extcon-palmas.c
-1
drivers/extcon/extcon-palmas.c
+1
-1
drivers/extcon/extcon-ptn5150.c
+1
-1
drivers/extcon/extcon-ptn5150.c
+2
-2
drivers/extcon/extcon-qcom-spmi-misc.c
+2
-2
drivers/extcon/extcon-qcom-spmi-misc.c
···
123
123
if (ret)
124
124
return ret;
125
125
126
-
info->id_irq = platform_get_irq_byname(pdev, "usb_id");
126
+
info->id_irq = platform_get_irq_byname_optional(pdev, "usb_id");
127
127
if (info->id_irq > 0) {
128
128
ret = devm_request_threaded_irq(dev, info->id_irq, NULL,
129
129
qcom_usb_irq_handler,
···
136
136
}
137
137
}
138
138
139
-
info->vbus_irq = platform_get_irq_byname(pdev, "usb_vbus");
139
+
info->vbus_irq = platform_get_irq_byname_optional(pdev, "usb_vbus");
140
140
if (info->vbus_irq > 0) {
141
141
ret = devm_request_threaded_irq(dev, info->vbus_irq, NULL,
142
142
qcom_usb_irq_handler,
+1
-1
drivers/extcon/extcon-rt8973a.c
+1
-1
drivers/extcon/extcon-rt8973a.c
+1
-1
drivers/extcon/extcon-sm5502.c
+1
-1
drivers/extcon/extcon-sm5502.c
+126
-33
drivers/extcon/extcon-usbc-tusb320.c
+126
-33
drivers/extcon/extcon-usbc-tusb320.c
···
15
15
#include <linux/module.h>
16
16
#include <linux/regmap.h>
17
17
#include <linux/usb/typec.h>
18
+
#include <linux/usb/typec_altmode.h>
19
+
#include <linux/usb/role.h>
18
20
19
21
#define TUSB320_REG8 0x8
20
22
#define TUSB320_REG8_CURRENT_MODE_ADVERTISE GENMASK(7, 6)
···
28
26
#define TUSB320_REG8_CURRENT_MODE_DETECT_MED 0x1
29
27
#define TUSB320_REG8_CURRENT_MODE_DETECT_ACC 0x2
30
28
#define TUSB320_REG8_CURRENT_MODE_DETECT_HI 0x3
31
-
#define TUSB320_REG8_ACCESSORY_CONNECTED GENMASK(3, 2)
29
+
#define TUSB320_REG8_ACCESSORY_CONNECTED GENMASK(3, 1)
32
30
#define TUSB320_REG8_ACCESSORY_CONNECTED_NONE 0x0
33
31
#define TUSB320_REG8_ACCESSORY_CONNECTED_AUDIO 0x4
34
-
#define TUSB320_REG8_ACCESSORY_CONNECTED_ACC 0x5
35
-
#define TUSB320_REG8_ACCESSORY_CONNECTED_DEBUG 0x6
32
+
#define TUSB320_REG8_ACCESSORY_CONNECTED_ACHRG 0x5
33
+
#define TUSB320_REG8_ACCESSORY_CONNECTED_DBGDFP 0x6
34
+
#define TUSB320_REG8_ACCESSORY_CONNECTED_DBGUFP 0x7
36
35
#define TUSB320_REG8_ACTIVE_CABLE_DETECTION BIT(0)
37
36
38
37
#define TUSB320_REG9 0x9
39
-
#define TUSB320_REG9_ATTACHED_STATE_SHIFT 6
40
-
#define TUSB320_REG9_ATTACHED_STATE_MASK 0x3
38
+
#define TUSB320_REG9_ATTACHED_STATE GENMASK(7, 6)
41
39
#define TUSB320_REG9_CABLE_DIRECTION BIT(5)
42
40
#define TUSB320_REG9_INTERRUPT_STATUS BIT(4)
43
41
···
80
78
struct typec_capability cap;
81
79
enum typec_port_type port_type;
82
80
enum typec_pwr_opmode pwr_opmode;
81
+
struct fwnode_handle *connector_fwnode;
82
+
struct usb_role_switch *role_sw;
83
83
};
84
84
85
85
static const char * const tusb_attached_states[] = {
···
253
249
{
254
250
int state, polarity;
255
251
256
-
state = (reg >> TUSB320_REG9_ATTACHED_STATE_SHIFT) &
257
-
TUSB320_REG9_ATTACHED_STATE_MASK;
252
+
state = FIELD_GET(TUSB320_REG9_ATTACHED_STATE, reg);
258
253
polarity = !!(reg & TUSB320_REG9_CABLE_DIRECTION);
259
254
260
255
dev_dbg(priv->dev, "attached state: %s, polarity: %d\n",
···
279
276
{
280
277
struct typec_port *port = priv->port;
281
278
struct device *dev = priv->dev;
282
-
u8 mode, role, state;
279
+
int typec_mode;
280
+
enum usb_role usb_role;
281
+
enum typec_role pwr_role;
282
+
enum typec_data_role data_role;
283
+
u8 state, mode, accessory;
283
284
int ret, reg8;
284
285
bool ori;
285
-
286
-
ori = reg9 & TUSB320_REG9_CABLE_DIRECTION;
287
-
typec_set_orientation(port, ori ? TYPEC_ORIENTATION_REVERSE :
288
-
TYPEC_ORIENTATION_NORMAL);
289
-
290
-
state = (reg9 >> TUSB320_REG9_ATTACHED_STATE_SHIFT) &
291
-
TUSB320_REG9_ATTACHED_STATE_MASK;
292
-
if (state == TUSB320_ATTACHED_STATE_DFP)
293
-
role = TYPEC_SOURCE;
294
-
else
295
-
role = TYPEC_SINK;
296
-
297
-
typec_set_vconn_role(port, role);
298
-
typec_set_pwr_role(port, role);
299
-
typec_set_data_role(port, role == TYPEC_SOURCE ?
300
-
TYPEC_HOST : TYPEC_DEVICE);
301
286
302
287
ret = regmap_read(priv->regmap, TUSB320_REG8, ®8);
303
288
if (ret) {
304
289
dev_err(dev, "error during reg8 i2c read, ret=%d!\n", ret);
305
290
return;
306
291
}
292
+
293
+
ori = reg9 & TUSB320_REG9_CABLE_DIRECTION;
294
+
typec_set_orientation(port, ori ? TYPEC_ORIENTATION_REVERSE :
295
+
TYPEC_ORIENTATION_NORMAL);
296
+
297
+
state = FIELD_GET(TUSB320_REG9_ATTACHED_STATE, reg9);
298
+
accessory = FIELD_GET(TUSB320_REG8_ACCESSORY_CONNECTED, reg8);
299
+
300
+
switch (state) {
301
+
case TUSB320_ATTACHED_STATE_DFP:
302
+
typec_mode = TYPEC_MODE_USB2;
303
+
usb_role = USB_ROLE_HOST;
304
+
pwr_role = TYPEC_SOURCE;
305
+
data_role = TYPEC_HOST;
306
+
break;
307
+
case TUSB320_ATTACHED_STATE_UFP:
308
+
typec_mode = TYPEC_MODE_USB2;
309
+
usb_role = USB_ROLE_DEVICE;
310
+
pwr_role = TYPEC_SINK;
311
+
data_role = TYPEC_DEVICE;
312
+
break;
313
+
case TUSB320_ATTACHED_STATE_ACC:
314
+
/*
315
+
* Accessory detected. For debug accessories, just make some
316
+
* qualified guesses as to the role for lack of a better option.
317
+
*/
318
+
if (accessory == TUSB320_REG8_ACCESSORY_CONNECTED_AUDIO ||
319
+
accessory == TUSB320_REG8_ACCESSORY_CONNECTED_ACHRG) {
320
+
typec_mode = TYPEC_MODE_AUDIO;
321
+
usb_role = USB_ROLE_NONE;
322
+
pwr_role = TYPEC_SINK;
323
+
data_role = TYPEC_DEVICE;
324
+
break;
325
+
} else if (accessory ==
326
+
TUSB320_REG8_ACCESSORY_CONNECTED_DBGDFP) {
327
+
typec_mode = TYPEC_MODE_DEBUG;
328
+
pwr_role = TYPEC_SOURCE;
329
+
usb_role = USB_ROLE_HOST;
330
+
data_role = TYPEC_HOST;
331
+
break;
332
+
} else if (accessory ==
333
+
TUSB320_REG8_ACCESSORY_CONNECTED_DBGUFP) {
334
+
typec_mode = TYPEC_MODE_DEBUG;
335
+
pwr_role = TYPEC_SINK;
336
+
usb_role = USB_ROLE_DEVICE;
337
+
data_role = TYPEC_DEVICE;
338
+
break;
339
+
}
340
+
341
+
dev_warn(priv->dev, "unexpected ACCESSORY_CONNECTED state %d\n",
342
+
accessory);
343
+
344
+
fallthrough;
345
+
default:
346
+
typec_mode = TYPEC_MODE_USB2;
347
+
usb_role = USB_ROLE_NONE;
348
+
pwr_role = TYPEC_SINK;
349
+
data_role = TYPEC_DEVICE;
350
+
break;
351
+
}
352
+
353
+
typec_set_vconn_role(port, pwr_role);
354
+
typec_set_pwr_role(port, pwr_role);
355
+
typec_set_data_role(port, data_role);
356
+
typec_set_mode(port, typec_mode);
357
+
usb_role_switch_set_role(priv->role_sw, usb_role);
307
358
308
359
mode = FIELD_GET(TUSB320_REG8_CURRENT_MODE_DETECT, reg8);
309
360
if (mode == TUSB320_REG8_CURRENT_MODE_DETECT_DEF)
···
448
391
/* Type-C connector found. */
449
392
ret = typec_get_fw_cap(&priv->cap, connector);
450
393
if (ret)
451
-
return ret;
394
+
goto err_put;
452
395
453
396
priv->port_type = priv->cap.type;
454
397
455
398
/* This goes into register 0x8 field CURRENT_MODE_ADVERTISE */
456
399
ret = fwnode_property_read_string(connector, "typec-power-opmode", &cap_str);
457
400
if (ret)
458
-
return ret;
401
+
goto err_put;
459
402
460
403
ret = typec_find_pwr_opmode(cap_str);
461
404
if (ret < 0)
462
-
return ret;
463
-
if (ret == TYPEC_PWR_MODE_PD)
464
-
return -EINVAL;
405
+
goto err_put;
465
406
466
407
priv->pwr_opmode = ret;
467
408
468
409
/* Initialize the hardware with the devicetree settings. */
469
410
ret = tusb320_set_adv_pwr_mode(priv);
470
411
if (ret)
471
-
return ret;
412
+
goto err_put;
472
413
473
414
priv->cap.revision = USB_TYPEC_REV_1_1;
474
415
priv->cap.accessory[0] = TYPEC_ACCESSORY_AUDIO;
···
477
422
priv->cap.fwnode = connector;
478
423
479
424
priv->port = typec_register_port(&client->dev, &priv->cap);
480
-
if (IS_ERR(priv->port))
481
-
return PTR_ERR(priv->port);
425
+
if (IS_ERR(priv->port)) {
426
+
ret = PTR_ERR(priv->port);
427
+
goto err_put;
428
+
}
429
+
430
+
/* Find any optional USB role switch that needs reporting to */
431
+
priv->role_sw = fwnode_usb_role_switch_get(connector);
432
+
if (IS_ERR(priv->role_sw)) {
433
+
ret = PTR_ERR(priv->role_sw);
434
+
goto err_unreg;
435
+
}
436
+
437
+
priv->connector_fwnode = connector;
482
438
483
439
return 0;
440
+
441
+
err_unreg:
442
+
typec_unregister_port(priv->port);
443
+
444
+
err_put:
445
+
fwnode_handle_put(connector);
446
+
447
+
return ret;
448
+
}
449
+
450
+
static void tusb320_typec_remove(struct tusb320_priv *priv)
451
+
{
452
+
usb_role_switch_put(priv->role_sw);
453
+
typec_unregister_port(priv->port);
454
+
fwnode_handle_put(priv->connector_fwnode);
484
455
}
485
456
486
457
static int tusb320_probe(struct i2c_client *client)
···
519
438
priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
520
439
if (!priv)
521
440
return -ENOMEM;
441
+
522
442
priv->dev = &client->dev;
443
+
i2c_set_clientdata(client, priv);
523
444
524
445
priv->regmap = devm_regmap_init_i2c(client, &tusb320_regmap_config);
525
446
if (IS_ERR(priv->regmap))
···
572
489
tusb320_irq_handler,
573
490
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
574
491
client->name, priv);
492
+
if (ret)
493
+
tusb320_typec_remove(priv);
575
494
576
495
return ret;
496
+
}
497
+
498
+
static void tusb320_remove(struct i2c_client *client)
499
+
{
500
+
struct tusb320_priv *priv = i2c_get_clientdata(client);
501
+
502
+
tusb320_typec_remove(priv);
577
503
}
578
504
579
505
static const struct of_device_id tusb320_extcon_dt_match[] = {
···
593
501
MODULE_DEVICE_TABLE(of, tusb320_extcon_dt_match);
594
502
595
503
static struct i2c_driver tusb320_extcon_driver = {
596
-
.probe_new = tusb320_probe,
504
+
.probe = tusb320_probe,
505
+
.remove = tusb320_remove,
597
506
.driver = {
598
507
.name = "extcon-tusb320",
599
508
.of_match_table = tusb320_extcon_dt_match,
+213
-155
drivers/extcon/extcon.c
+213
-155
drivers/extcon/extcon.c
···
16
16
17
17
#include <linux/module.h>
18
18
#include <linux/types.h>
19
+
#include <linux/idr.h>
19
20
#include <linux/init.h>
20
21
#include <linux/device.h>
21
22
#include <linux/fs.h>
···
207
206
* @attr_name: "name" sysfs entry
208
207
* @attr_state: "state" sysfs entry
209
208
* @attrs: the array pointing to attr_name and attr_state for attr_g
209
+
* @usb_propval: the array of USB connector properties
210
+
* @chg_propval: the array of charger connector properties
211
+
* @jack_propval: the array of jack connector properties
212
+
* @disp_propval: the array of display connector properties
213
+
* @usb_bits: the bit array of the USB connector property capabilities
214
+
* @chg_bits: the bit array of the charger connector property capabilities
215
+
* @jack_bits: the bit array of the jack connector property capabilities
216
+
* @disp_bits: the bit array of the display connector property capabilities
210
217
*/
211
218
struct extcon_cable {
212
219
struct extcon_dev *edev;
···
231
222
union extcon_property_value jack_propval[EXTCON_PROP_JACK_CNT];
232
223
union extcon_property_value disp_propval[EXTCON_PROP_DISP_CNT];
233
224
234
-
unsigned long usb_bits[BITS_TO_LONGS(EXTCON_PROP_USB_CNT)];
235
-
unsigned long chg_bits[BITS_TO_LONGS(EXTCON_PROP_CHG_CNT)];
236
-
unsigned long jack_bits[BITS_TO_LONGS(EXTCON_PROP_JACK_CNT)];
237
-
unsigned long disp_bits[BITS_TO_LONGS(EXTCON_PROP_DISP_CNT)];
225
+
DECLARE_BITMAP(usb_bits, EXTCON_PROP_USB_CNT);
226
+
DECLARE_BITMAP(chg_bits, EXTCON_PROP_CHG_CNT);
227
+
DECLARE_BITMAP(jack_bits, EXTCON_PROP_JACK_CNT);
228
+
DECLARE_BITMAP(disp_bits, EXTCON_PROP_DISP_CNT);
238
229
};
239
230
240
231
static struct class *extcon_class;
241
232
233
+
static DEFINE_IDA(extcon_dev_ids);
242
234
static LIST_HEAD(extcon_dev_list);
243
235
static DEFINE_MUTEX(extcon_dev_list_lock);
244
236
245
237
static int check_mutually_exclusive(struct extcon_dev *edev, u32 new_state)
246
238
{
247
-
int i = 0;
239
+
int i;
248
240
249
241
if (!edev->mutually_exclusive)
250
242
return 0;
···
372
362
struct extcon_dev *edev = dev_get_drvdata(dev);
373
363
374
364
if (edev->max_supported == 0)
375
-
return sprintf(buf, "%u\n", edev->state);
365
+
return sysfs_emit(buf, "%u\n", edev->state);
376
366
377
367
for (i = 0; i < edev->max_supported; i++) {
378
-
count += sprintf(buf + count, "%s=%d\n",
379
-
extcon_info[edev->supported_cable[i]].name,
380
-
!!(edev->state & BIT(i)));
368
+
count += sysfs_emit_at(buf, count, "%s=%d\n",
369
+
extcon_info[edev->supported_cable[i]].name,
370
+
!!(edev->state & BIT(i)));
381
371
}
382
372
383
373
return count;
···
389
379
{
390
380
struct extcon_dev *edev = dev_get_drvdata(dev);
391
381
392
-
return sprintf(buf, "%s\n", edev->name);
382
+
return sysfs_emit(buf, "%s\n", edev->name);
393
383
}
394
384
static DEVICE_ATTR_RO(name);
395
385
···
400
390
attr_name);
401
391
int i = cable->cable_index;
402
392
403
-
return sprintf(buf, "%s\n",
404
-
extcon_info[cable->edev->supported_cable[i]].name);
393
+
return sysfs_emit(buf, "%s\n",
394
+
extcon_info[cable->edev->supported_cable[i]].name);
405
395
}
406
396
407
397
static ssize_t cable_state_show(struct device *dev,
···
412
402
413
403
int i = cable->cable_index;
414
404
415
-
return sprintf(buf, "%d\n",
416
-
extcon_get_state(cable->edev, cable->edev->supported_cable[i]));
405
+
return sysfs_emit(buf, "%d\n",
406
+
extcon_get_state(cable->edev, cable->edev->supported_cable[i]));
417
407
}
418
408
419
409
/**
···
1022
1012
1023
1013
static int create_extcon_class(void)
1024
1014
{
1025
-
if (!extcon_class) {
1026
-
extcon_class = class_create("extcon");
1027
-
if (IS_ERR(extcon_class))
1028
-
return PTR_ERR(extcon_class);
1029
-
extcon_class->dev_groups = extcon_groups;
1030
-
}
1015
+
if (extcon_class)
1016
+
return 0;
1017
+
1018
+
extcon_class = class_create("extcon");
1019
+
if (IS_ERR(extcon_class))
1020
+
return PTR_ERR(extcon_class);
1021
+
extcon_class->dev_groups = extcon_groups;
1031
1022
1032
1023
return 0;
1033
1024
}
···
1081
1070
EXPORT_SYMBOL_GPL(extcon_dev_free);
1082
1071
1083
1072
/**
1073
+
* extcon_alloc_cables() - alloc the cables for extcon device
1074
+
* @edev: extcon device which has cables
1075
+
*
1076
+
* Returns 0 if success or error number if fail.
1077
+
*/
1078
+
static int extcon_alloc_cables(struct extcon_dev *edev)
1079
+
{
1080
+
int index;
1081
+
char *str;
1082
+
struct extcon_cable *cable;
1083
+
1084
+
if (!edev)
1085
+
return -EINVAL;
1086
+
1087
+
if (!edev->max_supported)
1088
+
return 0;
1089
+
1090
+
edev->cables = kcalloc(edev->max_supported, sizeof(*edev->cables),
1091
+
GFP_KERNEL);
1092
+
if (!edev->cables)
1093
+
return -ENOMEM;
1094
+
1095
+
for (index = 0; index < edev->max_supported; index++) {
1096
+
cable = &edev->cables[index];
1097
+
1098
+
str = kasprintf(GFP_KERNEL, "cable.%d", index);
1099
+
if (!str) {
1100
+
for (index--; index >= 0; index--) {
1101
+
cable = &edev->cables[index];
1102
+
kfree(cable->attr_g.name);
1103
+
}
1104
+
1105
+
kfree(edev->cables);
1106
+
return -ENOMEM;
1107
+
}
1108
+
1109
+
cable->edev = edev;
1110
+
cable->cable_index = index;
1111
+
cable->attrs[0] = &cable->attr_name.attr;
1112
+
cable->attrs[1] = &cable->attr_state.attr;
1113
+
cable->attrs[2] = NULL;
1114
+
cable->attr_g.name = str;
1115
+
cable->attr_g.attrs = cable->attrs;
1116
+
1117
+
sysfs_attr_init(&cable->attr_name.attr);
1118
+
cable->attr_name.attr.name = "name";
1119
+
cable->attr_name.attr.mode = 0444;
1120
+
cable->attr_name.show = cable_name_show;
1121
+
1122
+
sysfs_attr_init(&cable->attr_state.attr);
1123
+
cable->attr_state.attr.name = "state";
1124
+
cable->attr_state.attr.mode = 0444;
1125
+
cable->attr_state.show = cable_state_show;
1126
+
}
1127
+
1128
+
return 0;
1129
+
}
1130
+
1131
+
/**
1132
+
* extcon_alloc_muex() - alloc the mutual exclusive for extcon device
1133
+
* @edev: extcon device
1134
+
*
1135
+
* Returns 0 if success or error number if fail.
1136
+
*/
1137
+
static int extcon_alloc_muex(struct extcon_dev *edev)
1138
+
{
1139
+
char *name;
1140
+
int index;
1141
+
1142
+
if (!edev)
1143
+
return -EINVAL;
1144
+
1145
+
if (!(edev->max_supported && edev->mutually_exclusive))
1146
+
return 0;
1147
+
1148
+
/* Count the size of mutually_exclusive array */
1149
+
for (index = 0; edev->mutually_exclusive[index]; index++)
1150
+
;
1151
+
1152
+
edev->attrs_muex = kcalloc(index + 1, sizeof(*edev->attrs_muex),
1153
+
GFP_KERNEL);
1154
+
if (!edev->attrs_muex)
1155
+
return -ENOMEM;
1156
+
1157
+
edev->d_attrs_muex = kcalloc(index, sizeof(*edev->d_attrs_muex),
1158
+
GFP_KERNEL);
1159
+
if (!edev->d_attrs_muex) {
1160
+
kfree(edev->attrs_muex);
1161
+
return -ENOMEM;
1162
+
}
1163
+
1164
+
for (index = 0; edev->mutually_exclusive[index]; index++) {
1165
+
name = kasprintf(GFP_KERNEL, "0x%x",
1166
+
edev->mutually_exclusive[index]);
1167
+
if (!name) {
1168
+
for (index--; index >= 0; index--)
1169
+
kfree(edev->d_attrs_muex[index].attr.name);
1170
+
1171
+
kfree(edev->d_attrs_muex);
1172
+
kfree(edev->attrs_muex);
1173
+
return -ENOMEM;
1174
+
}
1175
+
sysfs_attr_init(&edev->d_attrs_muex[index].attr);
1176
+
edev->d_attrs_muex[index].attr.name = name;
1177
+
edev->d_attrs_muex[index].attr.mode = 0000;
1178
+
edev->attrs_muex[index] = &edev->d_attrs_muex[index].attr;
1179
+
}
1180
+
edev->attr_g_muex.name = muex_name;
1181
+
edev->attr_g_muex.attrs = edev->attrs_muex;
1182
+
1183
+
return 0;
1184
+
}
1185
+
1186
+
/**
1187
+
* extcon_alloc_groups() - alloc the groups for extcon device
1188
+
* @edev: extcon device
1189
+
*
1190
+
* Returns 0 if success or error number if fail.
1191
+
*/
1192
+
static int extcon_alloc_groups(struct extcon_dev *edev)
1193
+
{
1194
+
int index;
1195
+
1196
+
if (!edev)
1197
+
return -EINVAL;
1198
+
1199
+
if (!edev->max_supported)
1200
+
return 0;
1201
+
1202
+
edev->extcon_dev_type.groups = kcalloc(edev->max_supported + 2,
1203
+
sizeof(*edev->extcon_dev_type.groups),
1204
+
GFP_KERNEL);
1205
+
if (!edev->extcon_dev_type.groups)
1206
+
return -ENOMEM;
1207
+
1208
+
edev->extcon_dev_type.name = dev_name(&edev->dev);
1209
+
edev->extcon_dev_type.release = dummy_sysfs_dev_release;
1210
+
1211
+
for (index = 0; index < edev->max_supported; index++)
1212
+
edev->extcon_dev_type.groups[index] = &edev->cables[index].attr_g;
1213
+
1214
+
if (edev->mutually_exclusive)
1215
+
edev->extcon_dev_type.groups[index] = &edev->attr_g_muex;
1216
+
1217
+
edev->dev.type = &edev->extcon_dev_type;
1218
+
1219
+
return 0;
1220
+
}
1221
+
1222
+
/**
1084
1223
* extcon_dev_register() - Register an new extcon device
1085
1224
* @edev: the extcon device to be registered
1086
1225
*
···
1246
1085
*/
1247
1086
int extcon_dev_register(struct extcon_dev *edev)
1248
1087
{
1249
-
int ret, index = 0;
1250
-
static atomic_t edev_no = ATOMIC_INIT(-1);
1088
+
int ret, index;
1251
1089
1252
-
if (!extcon_class) {
1253
-
ret = create_extcon_class();
1254
-
if (ret < 0)
1255
-
return ret;
1256
-
}
1090
+
ret = create_extcon_class();
1091
+
if (ret < 0)
1092
+
return ret;
1257
1093
1258
1094
if (!edev || !edev->supported_cable)
1259
1095
return -EINVAL;
1260
1096
1261
-
for (; edev->supported_cable[index] != EXTCON_NONE; index++);
1097
+
for (index = 0; edev->supported_cable[index] != EXTCON_NONE; index++);
1262
1098
1263
1099
edev->max_supported = index;
1264
1100
if (index > SUPPORTED_CABLE_MAX) {
···
1273
1115
"extcon device name is null\n");
1274
1116
return -EINVAL;
1275
1117
}
1276
-
dev_set_name(&edev->dev, "extcon%lu",
1277
-
(unsigned long)atomic_inc_return(&edev_no));
1278
1118
1279
-
if (edev->max_supported) {
1280
-
char *str;
1281
-
struct extcon_cable *cable;
1119
+
ret = ida_alloc(&extcon_dev_ids, GFP_KERNEL);
1120
+
if (ret < 0)
1121
+
return ret;
1282
1122
1283
-
edev->cables = kcalloc(edev->max_supported,
1284
-
sizeof(struct extcon_cable),
1285
-
GFP_KERNEL);
1286
-
if (!edev->cables) {
1287
-
ret = -ENOMEM;
1288
-
goto err_sysfs_alloc;
1289
-
}
1290
-
for (index = 0; index < edev->max_supported; index++) {
1291
-
cable = &edev->cables[index];
1123
+
edev->id = ret;
1292
1124
1293
-
str = kasprintf(GFP_KERNEL, "cable.%d", index);
1294
-
if (!str) {
1295
-
for (index--; index >= 0; index--) {
1296
-
cable = &edev->cables[index];
1297
-
kfree(cable->attr_g.name);
1298
-
}
1299
-
ret = -ENOMEM;
1125
+
dev_set_name(&edev->dev, "extcon%d", edev->id);
1300
1126
1301
-
goto err_alloc_cables;
1302
-
}
1127
+
ret = extcon_alloc_cables(edev);
1128
+
if (ret < 0)
1129
+
goto err_alloc_cables;
1303
1130
1304
-
cable->edev = edev;
1305
-
cable->cable_index = index;
1306
-
cable->attrs[0] = &cable->attr_name.attr;
1307
-
cable->attrs[1] = &cable->attr_state.attr;
1308
-
cable->attrs[2] = NULL;
1309
-
cable->attr_g.name = str;
1310
-
cable->attr_g.attrs = cable->attrs;
1131
+
ret = extcon_alloc_muex(edev);
1132
+
if (ret < 0)
1133
+
goto err_alloc_muex;
1311
1134
1312
-
sysfs_attr_init(&cable->attr_name.attr);
1313
-
cable->attr_name.attr.name = "name";
1314
-
cable->attr_name.attr.mode = 0444;
1315
-
cable->attr_name.show = cable_name_show;
1316
-
1317
-
sysfs_attr_init(&cable->attr_state.attr);
1318
-
cable->attr_state.attr.name = "state";
1319
-
cable->attr_state.attr.mode = 0444;
1320
-
cable->attr_state.show = cable_state_show;
1321
-
}
1322
-
}
1323
-
1324
-
if (edev->max_supported && edev->mutually_exclusive) {
1325
-
char *name;
1326
-
1327
-
/* Count the size of mutually_exclusive array */
1328
-
for (index = 0; edev->mutually_exclusive[index]; index++)
1329
-
;
1330
-
1331
-
edev->attrs_muex = kcalloc(index + 1,
1332
-
sizeof(struct attribute *),
1333
-
GFP_KERNEL);
1334
-
if (!edev->attrs_muex) {
1335
-
ret = -ENOMEM;
1336
-
goto err_muex;
1337
-
}
1338
-
1339
-
edev->d_attrs_muex = kcalloc(index,
1340
-
sizeof(struct device_attribute),
1341
-
GFP_KERNEL);
1342
-
if (!edev->d_attrs_muex) {
1343
-
ret = -ENOMEM;
1344
-
kfree(edev->attrs_muex);
1345
-
goto err_muex;
1346
-
}
1347
-
1348
-
for (index = 0; edev->mutually_exclusive[index]; index++) {
1349
-
name = kasprintf(GFP_KERNEL, "0x%x",
1350
-
edev->mutually_exclusive[index]);
1351
-
if (!name) {
1352
-
for (index--; index >= 0; index--) {
1353
-
kfree(edev->d_attrs_muex[index].attr.
1354
-
name);
1355
-
}
1356
-
kfree(edev->d_attrs_muex);
1357
-
kfree(edev->attrs_muex);
1358
-
ret = -ENOMEM;
1359
-
goto err_muex;
1360
-
}
1361
-
sysfs_attr_init(&edev->d_attrs_muex[index].attr);
1362
-
edev->d_attrs_muex[index].attr.name = name;
1363
-
edev->d_attrs_muex[index].attr.mode = 0000;
1364
-
edev->attrs_muex[index] = &edev->d_attrs_muex[index]
1365
-
.attr;
1366
-
}
1367
-
edev->attr_g_muex.name = muex_name;
1368
-
edev->attr_g_muex.attrs = edev->attrs_muex;
1369
-
1370
-
}
1371
-
1372
-
if (edev->max_supported) {
1373
-
edev->extcon_dev_type.groups =
1374
-
kcalloc(edev->max_supported + 2,
1375
-
sizeof(struct attribute_group *),
1376
-
GFP_KERNEL);
1377
-
if (!edev->extcon_dev_type.groups) {
1378
-
ret = -ENOMEM;
1379
-
goto err_alloc_groups;
1380
-
}
1381
-
1382
-
edev->extcon_dev_type.name = dev_name(&edev->dev);
1383
-
edev->extcon_dev_type.release = dummy_sysfs_dev_release;
1384
-
1385
-
for (index = 0; index < edev->max_supported; index++)
1386
-
edev->extcon_dev_type.groups[index] =
1387
-
&edev->cables[index].attr_g;
1388
-
if (edev->mutually_exclusive)
1389
-
edev->extcon_dev_type.groups[index] =
1390
-
&edev->attr_g_muex;
1391
-
1392
-
edev->dev.type = &edev->extcon_dev_type;
1393
-
}
1135
+
ret = extcon_alloc_groups(edev);
1136
+
if (ret < 0)
1137
+
goto err_alloc_groups;
1394
1138
1395
1139
spin_lock_init(&edev->lock);
1396
1140
if (edev->max_supported) {
···
1337
1277
kfree(edev->d_attrs_muex);
1338
1278
kfree(edev->attrs_muex);
1339
1279
}
1340
-
err_muex:
1280
+
err_alloc_muex:
1341
1281
for (index = 0; index < edev->max_supported; index++)
1342
1282
kfree(edev->cables[index].attr_g.name);
1343
-
err_alloc_cables:
1344
1283
if (edev->max_supported)
1345
1284
kfree(edev->cables);
1346
-
err_sysfs_alloc:
1285
+
err_alloc_cables:
1286
+
ida_free(&extcon_dev_ids, edev->id);
1287
+
1347
1288
return ret;
1348
1289
}
1349
1290
EXPORT_SYMBOL_GPL(extcon_dev_register);
···
1367
1306
list_del(&edev->entry);
1368
1307
mutex_unlock(&extcon_dev_list_lock);
1369
1308
1370
-
if (IS_ERR_OR_NULL(get_device(&edev->dev))) {
1371
-
dev_err(&edev->dev, "Failed to unregister extcon_dev (%s)\n",
1372
-
dev_name(&edev->dev));
1309
+
if (!get_device(&edev->dev)) {
1310
+
dev_err(&edev->dev, "Failed to unregister extcon_dev\n");
1373
1311
return;
1374
1312
}
1313
+
1314
+
ida_free(&extcon_dev_ids, edev->id);
1375
1315
1376
1316
device_unregister(&edev->dev);
1377
1317
···
1411
1349
1412
1350
mutex_lock(&extcon_dev_list_lock);
1413
1351
list_for_each_entry(edev, &extcon_dev_list, entry)
1414
-
if (edev->dev.parent && edev->dev.parent->of_node == node)
1352
+
if (edev->dev.parent && device_match_of_node(edev->dev.parent, node))
1415
1353
goto out;
1416
1354
edev = ERR_PTR(-EPROBE_DEFER);
1417
1355
out:
···
1429
1367
*/
1430
1368
struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev, int index)
1431
1369
{
1432
-
struct device_node *node;
1370
+
struct device_node *node, *np = dev_of_node(dev);
1433
1371
struct extcon_dev *edev;
1434
1372
1435
-
if (!dev)
1436
-
return ERR_PTR(-EINVAL);
1437
-
1438
-
if (!dev->of_node) {
1373
+
if (!np) {
1439
1374
dev_dbg(dev, "device does not have a device node entry\n");
1440
1375
return ERR_PTR(-EINVAL);
1441
1376
}
1442
1377
1443
-
node = of_parse_phandle(dev->of_node, "extcon", index);
1378
+
node = of_parse_phandle(np, "extcon", index);
1444
1379
if (!node) {
1445
-
dev_dbg(dev, "failed to get phandle in %pOF node\n",
1446
-
dev->of_node);
1380
+
dev_dbg(dev, "failed to get phandle in %pOF node\n", np);
1447
1381
return ERR_PTR(-ENODEV);
1448
1382
}
1449
1383
+5
-3
drivers/extcon/extcon.h
+5
-3
drivers/extcon/extcon.h
···
13
13
* are disabled.
14
14
* @mutually_exclusive: Array of mutually exclusive set of cables that cannot
15
15
* be attached simultaneously. The array should be
16
-
* ending with NULL or be NULL (no mutually exclusive
17
-
* cables). For example, if it is { 0x7, 0x30, 0}, then,
16
+
* ending with 0 or be NULL (no mutually exclusive cables).
17
+
* For example, if it is {0x7, 0x30, 0}, then,
18
18
* {0, 1}, {0, 1, 2}, {0, 2}, {1, 2}, or {4, 5} cannot
19
19
* be attached simulataneously. {0x7, 0} is equivalent to
20
20
* {0x3, 0x6, 0x5, 0}. If it is {0xFFFFFFFF, 0}, there
21
21
* can be no simultaneous connections.
22
22
* @dev: Device of this extcon.
23
+
* @id: Unique device ID of this extcon.
23
24
* @state: Attach/detach state of this extcon. Do not provide at
24
25
* register-time.
25
26
* @nh_all: Notifier for the state change events for all supported
···
28
27
* @nh: Notifier for the state change events from this extcon
29
28
* @entry: To support list of extcon devices so that users can
30
29
* search for extcon devices based on the extcon name.
31
-
* @lock:
30
+
* @lock: Protects device state and serialises device registration
32
31
* @max_supported: Internal value to store the number of cables.
33
32
* @extcon_dev_type: Device_type struct to provide attribute_groups
34
33
* customized for each extcon device.
···
47
46
48
47
/* Internal data. Please do not set. */
49
48
struct device dev;
49
+
unsigned int id;
50
50
struct raw_notifier_head nh_all;
51
51
struct raw_notifier_head *nh;
52
52
struct list_head entry;
+4
drivers/firmware/dmi-sysfs.c
+4
drivers/firmware/dmi-sysfs.c
···
310
310
.default_groups = dmi_sysfs_sel_groups,
311
311
};
312
312
313
+
#ifdef CONFIG_HAS_IOPORT
313
314
typedef u8 (*sel_io_reader)(const struct dmi_system_event_log *sel,
314
315
loff_t offset);
315
316
···
375
374
376
375
return wrote;
377
376
}
377
+
#endif
378
378
379
379
static ssize_t dmi_sel_raw_read_phys32(struct dmi_sysfs_entry *entry,
380
380
const struct dmi_system_event_log *sel,
···
411
409
memcpy(&sel, dh, sizeof(sel));
412
410
413
411
switch (sel.access_method) {
412
+
#ifdef CONFIG_HAS_IOPORT
414
413
case DMI_SEL_ACCESS_METHOD_IO8:
415
414
case DMI_SEL_ACCESS_METHOD_IO2x8:
416
415
case DMI_SEL_ACCESS_METHOD_IO16:
417
416
return dmi_sel_raw_read_io(entry, &sel, state->buf,
418
417
state->pos, state->count);
418
+
#endif
419
419
case DMI_SEL_ACCESS_METHOD_PHYS32:
420
420
return dmi_sel_raw_read_phys32(entry, &sel, state->buf,
421
421
state->pos, state->count);
+1
-1
drivers/firmware/stratix10-svc.c
+1
-1
drivers/firmware/stratix10-svc.c
···
755
755
end = rounddown(sh_memory->addr + sh_memory->size, PAGE_SIZE);
756
756
paddr = begin;
757
757
size = end - begin;
758
-
va = memremap(paddr, size, MEMREMAP_WC);
758
+
va = devm_memremap(dev, paddr, size, MEMREMAP_WC);
759
759
if (!va) {
760
760
dev_err(dev, "fail to remap shared memory\n");
761
761
return ERR_PTR(-EINVAL);
+1
-1
drivers/firmware/xilinx/zynqmp-debug.c
+1
-1
drivers/firmware/xilinx/zynqmp-debug.c
+1
-1
drivers/firmware/xilinx/zynqmp-debug.h
+1
-1
drivers/firmware/xilinx/zynqmp-debug.h
+1
-1
drivers/firmware/xilinx/zynqmp.c
+1
-1
drivers/firmware/xilinx/zynqmp.c
+2
-2
drivers/fpga/dfl-fme-main.c
+2
-2
drivers/fpga/dfl-fme-main.c
···
265
265
.read = thermal_hwmon_read,
266
266
};
267
267
268
-
static const struct hwmon_channel_info *thermal_hwmon_info[] = {
268
+
static const struct hwmon_channel_info * const thermal_hwmon_info[] = {
269
269
HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_EMERGENCY |
270
270
HWMON_T_MAX | HWMON_T_MAX_ALARM |
271
271
HWMON_T_CRIT | HWMON_T_CRIT_ALARM),
···
465
465
.write = power_hwmon_write,
466
466
};
467
467
468
-
static const struct hwmon_channel_info *power_hwmon_info[] = {
468
+
static const struct hwmon_channel_info * const power_hwmon_info[] = {
469
469
HWMON_CHANNEL_INFO(power, HWMON_P_INPUT |
470
470
HWMON_P_MAX | HWMON_P_MAX_ALARM |
471
471
HWMON_P_CRIT | HWMON_P_CRIT_ALARM),
+4
-4
drivers/fpga/zynq-fpga.c
+4
-4
drivers/fpga/zynq-fpga.c
···
493
493
if (err)
494
494
return err;
495
495
496
-
/* Release 'PR' control back to the ICAP */
497
-
zynq_fpga_write(priv, CTRL_OFFSET,
498
-
zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
499
-
500
496
err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,
501
497
intr_status & IXR_PCFG_DONE_MASK,
502
498
INIT_POLL_DELAY,
503
499
INIT_POLL_TIMEOUT);
500
+
501
+
/* Release 'PR' control back to the ICAP */
502
+
zynq_fpga_write(priv, CTRL_OFFSET,
503
+
zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
504
504
505
505
clk_disable(priv->clk);
506
506
+11
drivers/hwtracing/coresight/Kconfig
+11
drivers/hwtracing/coresight/Kconfig
···
236
236
237
237
To compile this driver as a module, choose M here: the module will be
238
238
called coresight-tpda.
239
+
240
+
config CORESIGHT_DUMMY
241
+
tristate "Dummy driver support"
242
+
help
243
+
Enables support for dummy driver. Dummy driver can be used for
244
+
CoreSight sources/sinks that are owned and configured by some
245
+
other subsystem and use Linux drivers to configure rest of trace
246
+
path.
247
+
248
+
To compile this driver as a module, choose M here: the module will be
249
+
called coresight-dummy.
239
250
endif
+1
drivers/hwtracing/coresight/Makefile
+1
drivers/hwtracing/coresight/Makefile
+17
-4
drivers/hwtracing/coresight/coresight-catu.c
+17
-4
drivers/hwtracing/coresight/coresight-catu.c
···
395
395
return coresight_timeout(csa, CATU_STATUS, CATU_STATUS_READY, 1);
396
396
}
397
397
398
-
static int catu_enable_hw(struct catu_drvdata *drvdata, void *data)
398
+
static int catu_enable_hw(struct catu_drvdata *drvdata, enum cs_mode cs_mode,
399
+
void *data)
399
400
{
400
401
int rc;
401
402
u32 control, mode;
402
-
struct etr_buf *etr_buf = data;
403
+
struct etr_buf *etr_buf = NULL;
403
404
struct device *dev = &drvdata->csdev->dev;
404
405
struct coresight_device *csdev = drvdata->csdev;
406
+
struct coresight_device *etrdev;
407
+
union coresight_dev_subtype etr_subtype = {
408
+
.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM
409
+
};
405
410
406
411
if (catu_wait_for_ready(drvdata))
407
412
dev_warn(dev, "Timeout while waiting for READY\n");
···
421
416
if (rc)
422
417
return rc;
423
418
419
+
etrdev = coresight_find_input_type(
420
+
csdev->pdata, CORESIGHT_DEV_TYPE_SINK, etr_subtype);
421
+
if (etrdev) {
422
+
etr_buf = tmc_etr_get_buffer(etrdev, cs_mode, data);
423
+
if (IS_ERR(etr_buf))
424
+
return PTR_ERR(etr_buf);
425
+
}
424
426
control |= BIT(CATU_CONTROL_ENABLE);
425
427
426
428
if (etr_buf && etr_buf->mode == ETR_MODE_CATU) {
···
453
441
return 0;
454
442
}
455
443
456
-
static int catu_enable(struct coresight_device *csdev, void *data)
444
+
static int catu_enable(struct coresight_device *csdev, enum cs_mode mode,
445
+
void *data)
457
446
{
458
447
int rc;
459
448
struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev);
460
449
461
450
CS_UNLOCK(catu_drvdata->base);
462
-
rc = catu_enable_hw(catu_drvdata, data);
451
+
rc = catu_enable_hw(catu_drvdata, mode, data);
463
452
CS_LOCK(catu_drvdata->base);
464
453
return rc;
465
454
}
+329
-294
drivers/hwtracing/coresight/coresight-core.c
+329
-294
drivers/hwtracing/coresight/coresight-core.c
···
3
3
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
4
4
*/
5
5
6
+
#include <linux/build_bug.h>
6
7
#include <linux/kernel.h>
7
8
#include <linux/init.h>
8
9
#include <linux/types.h>
···
113
112
}
114
113
EXPORT_SYMBOL_GPL(coresight_get_percpu_sink);
115
114
116
-
static int coresight_find_link_inport(struct coresight_device *csdev,
117
-
struct coresight_device *parent)
115
+
static struct coresight_connection *
116
+
coresight_find_out_connection(struct coresight_device *src_dev,
117
+
struct coresight_device *dest_dev)
118
118
{
119
119
int i;
120
120
struct coresight_connection *conn;
121
121
122
-
for (i = 0; i < parent->pdata->nr_outport; i++) {
123
-
conn = &parent->pdata->conns[i];
124
-
if (conn->child_dev == csdev)
125
-
return conn->child_port;
122
+
for (i = 0; i < src_dev->pdata->nr_outconns; i++) {
123
+
conn = src_dev->pdata->out_conns[i];
124
+
if (conn->dest_dev == dest_dev)
125
+
return conn;
126
126
}
127
127
128
-
dev_err(&csdev->dev, "couldn't find inport, parent: %s, child: %s\n",
129
-
dev_name(&parent->dev), dev_name(&csdev->dev));
128
+
dev_err(&src_dev->dev,
129
+
"couldn't find output connection, src_dev: %s, dest_dev: %s\n",
130
+
dev_name(&src_dev->dev), dev_name(&dest_dev->dev));
130
131
131
-
return -ENODEV;
132
-
}
133
-
134
-
static int coresight_find_link_outport(struct coresight_device *csdev,
135
-
struct coresight_device *child)
136
-
{
137
-
int i;
138
-
struct coresight_connection *conn;
139
-
140
-
for (i = 0; i < csdev->pdata->nr_outport; i++) {
141
-
conn = &csdev->pdata->conns[i];
142
-
if (conn->child_dev == child)
143
-
return conn->outport;
144
-
}
145
-
146
-
dev_err(&csdev->dev, "couldn't find outport, parent: %s, child: %s\n",
147
-
dev_name(&csdev->dev), dev_name(&child->dev));
148
-
149
-
return -ENODEV;
132
+
return ERR_PTR(-ENODEV);
150
133
}
151
134
152
135
static inline u32 coresight_read_claim_tags(struct coresight_device *csdev)
···
237
252
}
238
253
EXPORT_SYMBOL_GPL(coresight_disclaim_device);
239
254
240
-
/* enable or disable an associated CTI device of the supplied CS device */
241
-
static int
242
-
coresight_control_assoc_ectdev(struct coresight_device *csdev, bool enable)
243
-
{
244
-
int ect_ret = 0;
245
-
struct coresight_device *ect_csdev = csdev->ect_dev;
246
-
struct module *mod;
247
-
248
-
if (!ect_csdev)
249
-
return 0;
250
-
if ((!ect_ops(ect_csdev)->enable) || (!ect_ops(ect_csdev)->disable))
251
-
return 0;
252
-
253
-
mod = ect_csdev->dev.parent->driver->owner;
254
-
if (enable) {
255
-
if (try_module_get(mod)) {
256
-
ect_ret = ect_ops(ect_csdev)->enable(ect_csdev);
257
-
if (ect_ret) {
258
-
module_put(mod);
259
-
} else {
260
-
get_device(ect_csdev->dev.parent);
261
-
csdev->ect_enabled = true;
262
-
}
263
-
} else
264
-
ect_ret = -ENODEV;
265
-
} else {
266
-
if (csdev->ect_enabled) {
267
-
ect_ret = ect_ops(ect_csdev)->disable(ect_csdev);
268
-
put_device(ect_csdev->dev.parent);
269
-
module_put(mod);
270
-
csdev->ect_enabled = false;
271
-
}
272
-
}
273
-
274
-
/* output warning if ECT enable is preventing trace operation */
275
-
if (ect_ret)
276
-
dev_info(&csdev->dev, "Associated ECT device (%s) %s failed\n",
277
-
dev_name(&ect_csdev->dev),
278
-
enable ? "enable" : "disable");
279
-
return ect_ret;
280
-
}
281
-
282
255
/*
283
-
* Set the associated ect / cti device while holding the coresight_mutex
284
-
* to avoid a race with coresight_enable that may try to use this value.
256
+
* Add a helper as an output device. This function takes the @coresight_mutex
257
+
* because it's assumed that it's called from the helper device, outside of the
258
+
* core code where the mutex would already be held. Don't add new calls to this
259
+
* from inside the core code, instead try to add the new helper to the DT and
260
+
* ACPI where it will be picked up and linked automatically.
285
261
*/
286
-
void coresight_set_assoc_ectdev_mutex(struct coresight_device *csdev,
287
-
struct coresight_device *ect_csdev)
262
+
void coresight_add_helper(struct coresight_device *csdev,
263
+
struct coresight_device *helper)
288
264
{
265
+
int i;
266
+
struct coresight_connection conn = {};
267
+
struct coresight_connection *new_conn;
268
+
289
269
mutex_lock(&coresight_mutex);
290
-
csdev->ect_dev = ect_csdev;
270
+
conn.dest_fwnode = fwnode_handle_get(dev_fwnode(&helper->dev));
271
+
conn.dest_dev = helper;
272
+
conn.dest_port = conn.src_port = -1;
273
+
conn.src_dev = csdev;
274
+
275
+
/*
276
+
* Check for duplicates because this is called every time a helper
277
+
* device is re-loaded. Existing connections will get re-linked
278
+
* automatically.
279
+
*/
280
+
for (i = 0; i < csdev->pdata->nr_outconns; ++i)
281
+
if (csdev->pdata->out_conns[i]->dest_fwnode == conn.dest_fwnode)
282
+
goto unlock;
283
+
284
+
new_conn = coresight_add_out_conn(csdev->dev.parent, csdev->pdata,
285
+
&conn);
286
+
if (!IS_ERR(new_conn))
287
+
coresight_add_in_conn(new_conn);
288
+
289
+
unlock:
291
290
mutex_unlock(&coresight_mutex);
292
291
}
293
-
EXPORT_SYMBOL_GPL(coresight_set_assoc_ectdev_mutex);
292
+
EXPORT_SYMBOL_GPL(coresight_add_helper);
294
293
295
294
static int coresight_enable_sink(struct coresight_device *csdev,
296
-
u32 mode, void *data)
295
+
enum cs_mode mode, void *data)
297
296
{
298
297
int ret;
299
298
···
288
319
if (!sink_ops(csdev)->enable)
289
320
return -EINVAL;
290
321
291
-
ret = coresight_control_assoc_ectdev(csdev, true);
322
+
ret = sink_ops(csdev)->enable(csdev, mode, data);
292
323
if (ret)
293
324
return ret;
294
-
ret = sink_ops(csdev)->enable(csdev, mode, data);
295
-
if (ret) {
296
-
coresight_control_assoc_ectdev(csdev, false);
297
-
return ret;
298
-
}
325
+
299
326
csdev->enable = true;
300
327
301
328
return 0;
···
307
342
ret = sink_ops(csdev)->disable(csdev);
308
343
if (ret)
309
344
return;
310
-
coresight_control_assoc_ectdev(csdev, false);
311
345
csdev->enable = false;
312
346
}
313
347
···
316
352
{
317
353
int ret = 0;
318
354
int link_subtype;
319
-
int inport, outport;
355
+
struct coresight_connection *inconn, *outconn;
320
356
321
357
if (!parent || !child)
322
358
return -EINVAL;
323
359
324
-
inport = coresight_find_link_inport(csdev, parent);
325
-
outport = coresight_find_link_outport(csdev, child);
360
+
inconn = coresight_find_out_connection(parent, csdev);
361
+
outconn = coresight_find_out_connection(csdev, child);
326
362
link_subtype = csdev->subtype.link_subtype;
327
363
328
-
if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG && inport < 0)
329
-
return inport;
330
-
if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT && outport < 0)
331
-
return outport;
364
+
if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG && IS_ERR(inconn))
365
+
return PTR_ERR(inconn);
366
+
if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT && IS_ERR(outconn))
367
+
return PTR_ERR(outconn);
332
368
333
369
if (link_ops(csdev)->enable) {
334
-
ret = coresight_control_assoc_ectdev(csdev, true);
335
-
if (!ret) {
336
-
ret = link_ops(csdev)->enable(csdev, inport, outport);
337
-
if (ret)
338
-
coresight_control_assoc_ectdev(csdev, false);
339
-
}
370
+
ret = link_ops(csdev)->enable(csdev, inconn, outconn);
371
+
if (!ret)
372
+
csdev->enable = true;
340
373
}
341
-
342
-
if (!ret)
343
-
csdev->enable = true;
344
374
345
375
return ret;
346
376
}
···
343
385
struct coresight_device *parent,
344
386
struct coresight_device *child)
345
387
{
346
-
int i, nr_conns;
388
+
int i;
347
389
int link_subtype;
348
-
int inport, outport;
390
+
struct coresight_connection *inconn, *outconn;
349
391
350
392
if (!parent || !child)
351
393
return;
352
394
353
-
inport = coresight_find_link_inport(csdev, parent);
354
-
outport = coresight_find_link_outport(csdev, child);
395
+
inconn = coresight_find_out_connection(parent, csdev);
396
+
outconn = coresight_find_out_connection(csdev, child);
355
397
link_subtype = csdev->subtype.link_subtype;
356
398
357
-
if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG) {
358
-
nr_conns = csdev->pdata->nr_inport;
359
-
} else if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT) {
360
-
nr_conns = csdev->pdata->nr_outport;
361
-
} else {
362
-
nr_conns = 1;
363
-
}
364
-
365
399
if (link_ops(csdev)->disable) {
366
-
link_ops(csdev)->disable(csdev, inport, outport);
367
-
coresight_control_assoc_ectdev(csdev, false);
400
+
link_ops(csdev)->disable(csdev, inconn, outconn);
368
401
}
369
402
370
-
for (i = 0; i < nr_conns; i++)
371
-
if (atomic_read(&csdev->refcnt[i]) != 0)
403
+
if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG) {
404
+
for (i = 0; i < csdev->pdata->nr_inconns; i++)
405
+
if (atomic_read(&csdev->pdata->in_conns[i]->dest_refcnt) !=
406
+
0)
407
+
return;
408
+
} else if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT) {
409
+
for (i = 0; i < csdev->pdata->nr_outconns; i++)
410
+
if (atomic_read(&csdev->pdata->out_conns[i]->src_refcnt) !=
411
+
0)
412
+
return;
413
+
} else {
414
+
if (atomic_read(&csdev->refcnt) != 0)
372
415
return;
416
+
}
373
417
374
418
csdev->enable = false;
375
419
}
376
420
377
-
static int coresight_enable_source(struct coresight_device *csdev, u32 mode)
421
+
int coresight_enable_source(struct coresight_device *csdev, enum cs_mode mode,
422
+
void *data)
378
423
{
379
424
int ret;
380
425
381
426
if (!csdev->enable) {
382
427
if (source_ops(csdev)->enable) {
383
-
ret = coresight_control_assoc_ectdev(csdev, true);
428
+
ret = source_ops(csdev)->enable(csdev, data, mode);
384
429
if (ret)
385
430
return ret;
386
-
ret = source_ops(csdev)->enable(csdev, NULL, mode);
387
-
if (ret) {
388
-
coresight_control_assoc_ectdev(csdev, false);
389
-
return ret;
390
-
}
391
431
}
392
432
csdev->enable = true;
393
433
}
394
434
395
-
atomic_inc(csdev->refcnt);
435
+
atomic_inc(&csdev->refcnt);
396
436
397
437
return 0;
438
+
}
439
+
EXPORT_SYMBOL_GPL(coresight_enable_source);
440
+
441
+
static bool coresight_is_helper(struct coresight_device *csdev)
442
+
{
443
+
return csdev->type == CORESIGHT_DEV_TYPE_HELPER;
444
+
}
445
+
446
+
static int coresight_enable_helper(struct coresight_device *csdev,
447
+
enum cs_mode mode, void *data)
448
+
{
449
+
int ret;
450
+
451
+
if (!helper_ops(csdev)->enable)
452
+
return 0;
453
+
ret = helper_ops(csdev)->enable(csdev, mode, data);
454
+
if (ret)
455
+
return ret;
456
+
457
+
csdev->enable = true;
458
+
return 0;
459
+
}
460
+
461
+
static void coresight_disable_helper(struct coresight_device *csdev)
462
+
{
463
+
int ret;
464
+
465
+
if (!helper_ops(csdev)->disable)
466
+
return;
467
+
468
+
ret = helper_ops(csdev)->disable(csdev, NULL);
469
+
if (ret)
470
+
return;
471
+
csdev->enable = false;
472
+
}
473
+
474
+
static void coresight_disable_helpers(struct coresight_device *csdev)
475
+
{
476
+
int i;
477
+
struct coresight_device *helper;
478
+
479
+
for (i = 0; i < csdev->pdata->nr_outconns; ++i) {
480
+
helper = csdev->pdata->out_conns[i]->dest_dev;
481
+
if (helper && coresight_is_helper(helper))
482
+
coresight_disable_helper(helper);
483
+
}
398
484
}
399
485
400
486
/**
···
446
444
* the device if there are no users left.
447
445
*
448
446
* @csdev: The coresight device to disable
447
+
* @data: Opaque data to pass on to the disable function of the source device.
448
+
* For example in perf mode this is a pointer to the struct perf_event.
449
449
*
450
450
* Returns true if the device has been disabled.
451
451
*/
452
-
static bool coresight_disable_source(struct coresight_device *csdev)
452
+
bool coresight_disable_source(struct coresight_device *csdev, void *data)
453
453
{
454
-
if (atomic_dec_return(csdev->refcnt) == 0) {
454
+
if (atomic_dec_return(&csdev->refcnt) == 0) {
455
455
if (source_ops(csdev)->disable)
456
-
source_ops(csdev)->disable(csdev, NULL);
457
-
coresight_control_assoc_ectdev(csdev, false);
456
+
source_ops(csdev)->disable(csdev, data);
457
+
coresight_disable_helpers(csdev);
458
458
csdev->enable = false;
459
459
}
460
460
return !csdev->enable;
461
461
}
462
+
EXPORT_SYMBOL_GPL(coresight_disable_source);
462
463
463
464
/*
464
465
* coresight_disable_path_from : Disable components in the given path beyond
···
512
507
default:
513
508
break;
514
509
}
510
+
511
+
/* Disable all helpers adjacent along the path last */
512
+
coresight_disable_helpers(csdev);
515
513
}
516
514
}
517
515
···
524
516
}
525
517
EXPORT_SYMBOL_GPL(coresight_disable_path);
526
518
527
-
int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data)
519
+
static int coresight_enable_helpers(struct coresight_device *csdev,
520
+
enum cs_mode mode, void *data)
528
521
{
522
+
int i, ret = 0;
523
+
struct coresight_device *helper;
529
524
525
+
for (i = 0; i < csdev->pdata->nr_outconns; ++i) {
526
+
helper = csdev->pdata->out_conns[i]->dest_dev;
527
+
if (!helper || !coresight_is_helper(helper))
528
+
continue;
529
+
530
+
ret = coresight_enable_helper(helper, mode, data);
531
+
if (ret)
532
+
return ret;
533
+
}
534
+
535
+
return 0;
536
+
}
537
+
538
+
int coresight_enable_path(struct list_head *path, enum cs_mode mode,
539
+
void *sink_data)
540
+
{
530
541
int ret = 0;
531
542
u32 type;
532
543
struct coresight_node *nd;
···
555
528
csdev = nd->csdev;
556
529
type = csdev->type;
557
530
531
+
/* Enable all helpers adjacent to the path first */
532
+
ret = coresight_enable_helpers(csdev, mode, sink_data);
533
+
if (ret)
534
+
goto err;
558
535
/*
559
536
* ETF devices are tricky... They can be a link or a sink,
560
537
* depending on how they are configured. If an ETF has been
···
633
602
/*
634
603
* Recursively explore each port found on this element.
635
604
*/
636
-
for (i = 0; i < csdev->pdata->nr_outport; i++) {
605
+
for (i = 0; i < csdev->pdata->nr_outconns; i++) {
637
606
struct coresight_device *child_dev;
638
607
639
-
child_dev = csdev->pdata->conns[i].child_dev;
608
+
child_dev = csdev->pdata->out_conns[i]->dest_dev;
640
609
if (child_dev)
641
610
sink = coresight_find_enabled_sink(child_dev);
642
611
if (sink)
···
749
718
{
750
719
int i;
751
720
752
-
for (i = 0; i < csdev->pdata->nr_outport; i++) {
721
+
for (i = 0; i < csdev->pdata->nr_outconns; i++) {
753
722
struct coresight_device *child;
754
723
755
-
child = csdev->pdata->conns[i].child_dev;
756
-
if (child && child->type == CORESIGHT_DEV_TYPE_HELPER)
724
+
child = csdev->pdata->out_conns[i]->dest_dev;
725
+
if (child && coresight_is_helper(child))
757
726
if (!coresight_get_ref(child))
758
727
goto err;
759
728
}
···
763
732
for (i--; i >= 0; i--) {
764
733
struct coresight_device *child;
765
734
766
-
child = csdev->pdata->conns[i].child_dev;
767
-
if (child && child->type == CORESIGHT_DEV_TYPE_HELPER)
735
+
child = csdev->pdata->out_conns[i]->dest_dev;
736
+
if (child && coresight_is_helper(child))
768
737
coresight_put_ref(child);
769
738
}
770
739
return -ENODEV;
···
779
748
int i;
780
749
781
750
coresight_put_ref(csdev);
782
-
for (i = 0; i < csdev->pdata->nr_outport; i++) {
751
+
for (i = 0; i < csdev->pdata->nr_outconns; i++) {
783
752
struct coresight_device *child;
784
753
785
-
child = csdev->pdata->conns[i].child_dev;
786
-
if (child && child->type == CORESIGHT_DEV_TYPE_HELPER)
754
+
child = csdev->pdata->out_conns[i]->dest_dev;
755
+
if (child && coresight_is_helper(child))
787
756
coresight_put_ref(child);
788
757
}
789
758
}
···
821
790
}
822
791
823
792
/* Not a sink - recursively explore each port found on this element */
824
-
for (i = 0; i < csdev->pdata->nr_outport; i++) {
793
+
for (i = 0; i < csdev->pdata->nr_outconns; i++) {
825
794
struct coresight_device *child_dev;
826
795
827
-
child_dev = csdev->pdata->conns[i].child_dev;
796
+
child_dev = csdev->pdata->out_conns[i]->dest_dev;
828
797
if (child_dev &&
829
798
_coresight_build_path(child_dev, sink, path) == 0) {
830
799
found = true;
···
990
959
* Not a sink we want - or possible child sink may be better.
991
960
* recursively explore each port found on this element.
992
961
*/
993
-
for (i = 0; i < csdev->pdata->nr_outport; i++) {
962
+
for (i = 0; i < csdev->pdata->nr_outconns; i++) {
994
963
struct coresight_device *child_dev, *sink = NULL;
995
964
int child_depth = curr_depth;
996
965
997
-
child_dev = csdev->pdata->conns[i].child_dev;
966
+
child_dev = csdev->pdata->out_conns[i]->dest_dev;
998
967
if (child_dev)
999
968
sink = coresight_find_sink(child_dev, &child_depth);
1000
969
···
1124
1093
* source is already enabled.
1125
1094
*/
1126
1095
if (subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE)
1127
-
atomic_inc(csdev->refcnt);
1096
+
atomic_inc(&csdev->refcnt);
1128
1097
goto out;
1129
1098
}
1130
1099
···
1145
1114
if (ret)
1146
1115
goto err_path;
1147
1116
1148
-
ret = coresight_enable_source(csdev, CS_MODE_SYSFS);
1117
+
ret = coresight_enable_source(csdev, CS_MODE_SYSFS, NULL);
1149
1118
if (ret)
1150
1119
goto err_source;
1151
1120
···
1202
1171
if (ret)
1203
1172
goto out;
1204
1173
1205
-
if (!csdev->enable || !coresight_disable_source(csdev))
1174
+
if (!csdev->enable || !coresight_disable_source(csdev, NULL))
1206
1175
goto out;
1207
1176
1208
1177
switch (csdev->subtype.source_subtype) {
···
1327
1296
},
1328
1297
{
1329
1298
.name = "helper",
1330
-
},
1331
-
{
1332
-
.name = "ect",
1333
-
},
1299
+
}
1334
1300
};
1301
+
/* Ensure the enum matches the names and groups */
1302
+
static_assert(ARRAY_SIZE(coresight_dev_type) == CORESIGHT_DEV_TYPE_MAX);
1335
1303
1336
1304
static void coresight_device_release(struct device *dev)
1337
1305
{
1338
1306
struct coresight_device *csdev = to_coresight_device(dev);
1339
1307
1340
1308
fwnode_handle_put(csdev->dev.fwnode);
1341
-
kfree(csdev->refcnt);
1342
1309
kfree(csdev);
1343
1310
}
1344
1311
···
1344
1315
{
1345
1316
int i, ret = 0;
1346
1317
bool still_orphan = false;
1347
-
struct coresight_device *csdev, *i_csdev;
1318
+
struct coresight_device *dst_csdev = data;
1319
+
struct coresight_device *src_csdev = to_coresight_device(dev);
1348
1320
struct coresight_connection *conn;
1349
-
1350
-
csdev = data;
1351
-
i_csdev = to_coresight_device(dev);
1352
-
1353
-
/* No need to check oneself */
1354
-
if (csdev == i_csdev)
1355
-
return 0;
1321
+
bool fixup_self = (src_csdev == dst_csdev);
1356
1322
1357
1323
/* Move on to another component if no connection is orphan */
1358
-
if (!i_csdev->orphan)
1324
+
if (!src_csdev->orphan)
1359
1325
return 0;
1360
1326
/*
1361
-
* Circle throuch all the connection of that component. If we find
1362
-
* an orphan connection whose name matches @csdev, link it.
1327
+
* Circle through all the connections of that component. If we find
1328
+
* an orphan connection whose name matches @dst_csdev, link it.
1363
1329
*/
1364
-
for (i = 0; i < i_csdev->pdata->nr_outport; i++) {
1365
-
conn = &i_csdev->pdata->conns[i];
1330
+
for (i = 0; i < src_csdev->pdata->nr_outconns; i++) {
1331
+
conn = src_csdev->pdata->out_conns[i];
1366
1332
1367
-
/* Skip the port if FW doesn't describe it */
1368
-
if (!conn->child_fwnode)
1333
+
/* Skip the port if it's already connected. */
1334
+
if (conn->dest_dev)
1369
1335
continue;
1370
-
/* We have found at least one orphan connection */
1371
-
if (conn->child_dev == NULL) {
1372
-
/* Does it match this newly added device? */
1373
-
if (conn->child_fwnode == csdev->dev.fwnode) {
1374
-
ret = coresight_make_links(i_csdev,
1375
-
conn, csdev);
1376
-
if (ret)
1377
-
return ret;
1378
-
} else {
1379
-
/* This component still has an orphan */
1380
-
still_orphan = true;
1381
-
}
1336
+
1337
+
/*
1338
+
* If we are at the "new" device, which triggered this search,
1339
+
* we must find the remote device from the fwnode in the
1340
+
* connection.
1341
+
*/
1342
+
if (fixup_self)
1343
+
dst_csdev = coresight_find_csdev_by_fwnode(
1344
+
conn->dest_fwnode);
1345
+
1346
+
/* Does it match this newly added device? */
1347
+
if (dst_csdev && conn->dest_fwnode == dst_csdev->dev.fwnode) {
1348
+
ret = coresight_make_links(src_csdev, conn, dst_csdev);
1349
+
if (ret)
1350
+
return ret;
1351
+
1352
+
/*
1353
+
* Install the device connection. This also indicates that
1354
+
* the links are operational on both ends.
1355
+
*/
1356
+
conn->dest_dev = dst_csdev;
1357
+
conn->src_dev = src_csdev;
1358
+
1359
+
ret = coresight_add_in_conn(conn);
1360
+
if (ret)
1361
+
return ret;
1362
+
} else {
1363
+
/* This component still has an orphan */
1364
+
still_orphan = true;
1382
1365
}
1383
1366
}
1384
1367
1385
-
i_csdev->orphan = still_orphan;
1368
+
src_csdev->orphan = still_orphan;
1386
1369
1387
1370
/*
1388
1371
* Returning '0' in case we didn't encounter any error,
···
1409
1368
csdev, coresight_orphan_match);
1410
1369
}
1411
1370
1412
-
1413
-
static int coresight_fixup_device_conns(struct coresight_device *csdev)
1414
-
{
1415
-
int i, ret = 0;
1416
-
1417
-
for (i = 0; i < csdev->pdata->nr_outport; i++) {
1418
-
struct coresight_connection *conn = &csdev->pdata->conns[i];
1419
-
1420
-
if (!conn->child_fwnode)
1421
-
continue;
1422
-
conn->child_dev =
1423
-
coresight_find_csdev_by_fwnode(conn->child_fwnode);
1424
-
if (conn->child_dev && conn->child_dev->has_conns_grp) {
1425
-
ret = coresight_make_links(csdev, conn,
1426
-
conn->child_dev);
1427
-
if (ret)
1428
-
break;
1429
-
} else {
1430
-
csdev->orphan = true;
1431
-
}
1432
-
}
1433
-
1434
-
return ret;
1435
-
}
1436
-
1437
-
static int coresight_remove_match(struct device *dev, void *data)
1438
-
{
1439
-
int i;
1440
-
struct coresight_device *csdev, *iterator;
1441
-
struct coresight_connection *conn;
1442
-
1443
-
csdev = data;
1444
-
iterator = to_coresight_device(dev);
1445
-
1446
-
/* No need to check oneself */
1447
-
if (csdev == iterator)
1448
-
return 0;
1449
-
1450
-
/*
1451
-
* Circle throuch all the connection of that component. If we find
1452
-
* a connection whose name matches @csdev, remove it.
1453
-
*/
1454
-
for (i = 0; i < iterator->pdata->nr_outport; i++) {
1455
-
conn = &iterator->pdata->conns[i];
1456
-
1457
-
if (conn->child_dev == NULL || conn->child_fwnode == NULL)
1458
-
continue;
1459
-
1460
-
if (csdev->dev.fwnode == conn->child_fwnode) {
1461
-
iterator->orphan = true;
1462
-
coresight_remove_links(iterator, conn);
1463
-
/*
1464
-
* Drop the reference to the handle for the remote
1465
-
* device acquired in parsing the connections from
1466
-
* platform data.
1467
-
*/
1468
-
fwnode_handle_put(conn->child_fwnode);
1469
-
conn->child_fwnode = NULL;
1470
-
/* No need to continue */
1471
-
break;
1472
-
}
1473
-
}
1474
-
1475
-
/*
1476
-
* Returning '0' ensures that all known component on the
1477
-
* bus will be checked.
1478
-
*/
1479
-
return 0;
1480
-
}
1481
-
1482
-
/*
1483
-
* coresight_remove_conns - Remove references to this given devices
1484
-
* from the connections of other devices.
1485
-
*/
1371
+
/* coresight_remove_conns - Remove other device's references to this device */
1486
1372
static void coresight_remove_conns(struct coresight_device *csdev)
1487
1373
{
1374
+
int i, j;
1375
+
struct coresight_connection *conn;
1376
+
1488
1377
/*
1489
-
* Another device will point to this device only if there is
1490
-
* an output port connected to this one. i.e, if the device
1491
-
* doesn't have at least one input port, there is no point
1492
-
* in searching all the devices.
1378
+
* Remove the input connection references from the destination device
1379
+
* for each output connection.
1493
1380
*/
1494
-
if (csdev->pdata->nr_inport)
1495
-
bus_for_each_dev(&coresight_bustype, NULL,
1496
-
csdev, coresight_remove_match);
1381
+
for (i = 0; i < csdev->pdata->nr_outconns; i++) {
1382
+
conn = csdev->pdata->out_conns[i];
1383
+
if (!conn->dest_dev)
1384
+
continue;
1385
+
1386
+
for (j = 0; j < conn->dest_dev->pdata->nr_inconns; ++j)
1387
+
if (conn->dest_dev->pdata->in_conns[j] == conn) {
1388
+
conn->dest_dev->pdata->in_conns[j] = NULL;
1389
+
break;
1390
+
}
1391
+
}
1392
+
1393
+
/*
1394
+
* For all input connections, remove references to this device.
1395
+
* Connection objects are shared so modifying this device's input
1396
+
* connections affects the other device's output connection.
1397
+
*/
1398
+
for (i = 0; i < csdev->pdata->nr_inconns; ++i) {
1399
+
conn = csdev->pdata->in_conns[i];
1400
+
/* Input conns array is sparse */
1401
+
if (!conn)
1402
+
continue;
1403
+
1404
+
conn->src_dev->orphan = true;
1405
+
coresight_remove_links(conn->src_dev, conn);
1406
+
conn->dest_dev = NULL;
1407
+
}
1497
1408
}
1498
1409
1499
1410
/**
···
1537
1544
* to the output port of this device.
1538
1545
*/
1539
1546
void coresight_release_platform_data(struct coresight_device *csdev,
1547
+
struct device *dev,
1540
1548
struct coresight_platform_data *pdata)
1541
1549
{
1542
1550
int i;
1543
-
struct coresight_connection *conns = pdata->conns;
1551
+
struct coresight_connection **conns = pdata->out_conns;
1544
1552
1545
-
for (i = 0; i < pdata->nr_outport; i++) {
1553
+
for (i = 0; i < pdata->nr_outconns; i++) {
1546
1554
/* If we have made the links, remove them now */
1547
-
if (csdev && conns[i].child_dev)
1548
-
coresight_remove_links(csdev, &conns[i]);
1555
+
if (csdev && conns[i]->dest_dev)
1556
+
coresight_remove_links(csdev, conns[i]);
1549
1557
/*
1550
1558
* Drop the refcount and clear the handle as this device
1551
1559
* is going away
1552
1560
*/
1553
-
if (conns[i].child_fwnode) {
1554
-
fwnode_handle_put(conns[i].child_fwnode);
1555
-
pdata->conns[i].child_fwnode = NULL;
1556
-
}
1561
+
fwnode_handle_put(conns[i]->dest_fwnode);
1562
+
conns[i]->dest_fwnode = NULL;
1563
+
devm_kfree(dev, conns[i]);
1557
1564
}
1565
+
devm_kfree(dev, pdata->out_conns);
1566
+
devm_kfree(dev, pdata->in_conns);
1567
+
devm_kfree(dev, pdata);
1558
1568
if (csdev)
1559
1569
coresight_remove_conns_sysfs_group(csdev);
1560
1570
}
···
1565
1569
struct coresight_device *coresight_register(struct coresight_desc *desc)
1566
1570
{
1567
1571
int ret;
1568
-
int link_subtype;
1569
-
int nr_refcnts = 1;
1570
-
atomic_t *refcnts = NULL;
1571
1572
struct coresight_device *csdev;
1572
1573
bool registered = false;
1573
1574
···
1574
1581
goto err_out;
1575
1582
}
1576
1583
1577
-
if (desc->type == CORESIGHT_DEV_TYPE_LINK ||
1578
-
desc->type == CORESIGHT_DEV_TYPE_LINKSINK) {
1579
-
link_subtype = desc->subtype.link_subtype;
1580
-
1581
-
if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG)
1582
-
nr_refcnts = desc->pdata->nr_inport;
1583
-
else if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT)
1584
-
nr_refcnts = desc->pdata->nr_outport;
1585
-
}
1586
-
1587
-
refcnts = kcalloc(nr_refcnts, sizeof(*refcnts), GFP_KERNEL);
1588
-
if (!refcnts) {
1589
-
ret = -ENOMEM;
1590
-
kfree(csdev);
1591
-
goto err_out;
1592
-
}
1593
-
1594
-
csdev->refcnt = refcnts;
1595
-
1596
1584
csdev->pdata = desc->pdata;
1597
1585
1598
1586
csdev->type = desc->type;
1599
1587
csdev->subtype = desc->subtype;
1600
1588
csdev->ops = desc->ops;
1601
1589
csdev->access = desc->access;
1602
-
csdev->orphan = false;
1590
+
csdev->orphan = true;
1603
1591
1604
1592
csdev->dev.type = &coresight_dev_type[desc->type];
1605
1593
csdev->dev.groups = desc->groups;
···
1631
1657
1632
1658
ret = coresight_create_conns_sysfs_group(csdev);
1633
1659
if (!ret)
1634
-
ret = coresight_fixup_device_conns(csdev);
1635
-
if (!ret)
1636
1660
ret = coresight_fixup_orphan_conns(csdev);
1637
1661
1638
1662
out_unlock:
···
1650
1678
1651
1679
err_out:
1652
1680
/* Cleanup the connection information */
1653
-
coresight_release_platform_data(NULL, desc->pdata);
1681
+
coresight_release_platform_data(NULL, desc->dev, desc->pdata);
1654
1682
return ERR_PTR(ret);
1655
1683
}
1656
1684
EXPORT_SYMBOL_GPL(coresight_register);
···
1663
1691
cti_assoc_ops->remove(csdev);
1664
1692
coresight_remove_conns(csdev);
1665
1693
coresight_clear_default_sink(csdev);
1666
-
coresight_release_platform_data(csdev, csdev->pdata);
1694
+
coresight_release_platform_data(csdev, csdev->dev.parent, csdev->pdata);
1667
1695
device_unregister(&csdev->dev);
1668
1696
}
1669
1697
EXPORT_SYMBOL_GPL(coresight_unregister);
···
1685
1713
return i;
1686
1714
return -ENOENT;
1687
1715
}
1716
+
1717
+
static bool coresight_compare_type(enum coresight_dev_type type_a,
1718
+
union coresight_dev_subtype subtype_a,
1719
+
enum coresight_dev_type type_b,
1720
+
union coresight_dev_subtype subtype_b)
1721
+
{
1722
+
if (type_a != type_b)
1723
+
return false;
1724
+
1725
+
switch (type_a) {
1726
+
case CORESIGHT_DEV_TYPE_SINK:
1727
+
return subtype_a.sink_subtype == subtype_b.sink_subtype;
1728
+
case CORESIGHT_DEV_TYPE_LINK:
1729
+
return subtype_a.link_subtype == subtype_b.link_subtype;
1730
+
case CORESIGHT_DEV_TYPE_LINKSINK:
1731
+
return subtype_a.link_subtype == subtype_b.link_subtype &&
1732
+
subtype_a.sink_subtype == subtype_b.sink_subtype;
1733
+
case CORESIGHT_DEV_TYPE_SOURCE:
1734
+
return subtype_a.source_subtype == subtype_b.source_subtype;
1735
+
case CORESIGHT_DEV_TYPE_HELPER:
1736
+
return subtype_a.helper_subtype == subtype_b.helper_subtype;
1737
+
default:
1738
+
return false;
1739
+
}
1740
+
}
1741
+
1742
+
struct coresight_device *
1743
+
coresight_find_input_type(struct coresight_platform_data *pdata,
1744
+
enum coresight_dev_type type,
1745
+
union coresight_dev_subtype subtype)
1746
+
{
1747
+
int i;
1748
+
struct coresight_connection *conn;
1749
+
1750
+
for (i = 0; i < pdata->nr_inconns; ++i) {
1751
+
conn = pdata->in_conns[i];
1752
+
if (conn &&
1753
+
coresight_compare_type(type, subtype, conn->src_dev->type,
1754
+
conn->src_dev->subtype))
1755
+
return conn->src_dev;
1756
+
}
1757
+
return NULL;
1758
+
}
1759
+
EXPORT_SYMBOL_GPL(coresight_find_input_type);
1760
+
1761
+
struct coresight_device *
1762
+
coresight_find_output_type(struct coresight_platform_data *pdata,
1763
+
enum coresight_dev_type type,
1764
+
union coresight_dev_subtype subtype)
1765
+
{
1766
+
int i;
1767
+
struct coresight_connection *conn;
1768
+
1769
+
for (i = 0; i < pdata->nr_outconns; ++i) {
1770
+
conn = pdata->out_conns[i];
1771
+
if (conn->dest_dev &&
1772
+
coresight_compare_type(type, subtype, conn->dest_dev->type,
1773
+
conn->dest_dev->subtype))
1774
+
return conn->dest_dev;
1775
+
}
1776
+
return NULL;
1777
+
}
1778
+
EXPORT_SYMBOL_GPL(coresight_find_output_type);
1688
1779
1689
1780
bool coresight_loses_context_with_cpu(struct device *dev)
1690
1781
{
+28
-24
drivers/hwtracing/coresight/coresight-cti-core.c
+28
-24
drivers/hwtracing/coresight/coresight-cti-core.c
···
555
555
mutex_lock(&ect_mutex);
556
556
557
557
/* exit if current is an ECT device.*/
558
-
if ((csdev->type == CORESIGHT_DEV_TYPE_ECT) || list_empty(&ect_net))
558
+
if ((csdev->type == CORESIGHT_DEV_TYPE_HELPER &&
559
+
csdev->subtype.helper_subtype ==
560
+
CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI) ||
561
+
list_empty(&ect_net))
559
562
goto cti_add_done;
560
563
561
564
/* if we didn't find the csdev previously we used the fwnode name */
···
574
571
* if we found a matching csdev then update the ECT
575
572
* association pointer for the device with this CTI.
576
573
*/
577
-
coresight_set_assoc_ectdev_mutex(csdev,
578
-
ect_item->csdev);
574
+
coresight_add_helper(csdev, ect_item->csdev);
579
575
break;
580
576
}
581
577
}
···
584
582
585
583
/*
586
584
* Removing the associated devices is easier.
587
-
* A CTI will not have a value for csdev->ect_dev.
588
585
*/
589
586
static void cti_remove_assoc_from_csdev(struct coresight_device *csdev)
590
587
{
591
588
struct cti_drvdata *ctidrv;
592
589
struct cti_trig_con *tc;
593
590
struct cti_device *ctidev;
591
+
union coresight_dev_subtype cti_subtype = {
592
+
.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI
593
+
};
594
+
struct coresight_device *cti_csdev = coresight_find_output_type(
595
+
csdev->pdata, CORESIGHT_DEV_TYPE_HELPER, cti_subtype);
596
+
597
+
if (!cti_csdev)
598
+
return;
594
599
595
600
mutex_lock(&ect_mutex);
596
-
if (csdev->ect_dev) {
597
-
ctidrv = csdev_to_cti_drvdata(csdev->ect_dev);
598
-
ctidev = &ctidrv->ctidev;
599
-
list_for_each_entry(tc, &ctidev->trig_cons, node) {
600
-
if (tc->con_dev == csdev) {
601
-
cti_remove_sysfs_link(ctidrv, tc);
602
-
tc->con_dev = NULL;
603
-
break;
604
-
}
601
+
ctidrv = csdev_to_cti_drvdata(cti_csdev);
602
+
ctidev = &ctidrv->ctidev;
603
+
list_for_each_entry(tc, &ctidev->trig_cons, node) {
604
+
if (tc->con_dev == csdev) {
605
+
cti_remove_sysfs_link(ctidrv, tc);
606
+
tc->con_dev = NULL;
607
+
break;
605
608
}
606
-
csdev->ect_dev = NULL;
607
609
}
608
610
mutex_unlock(&ect_mutex);
609
611
}
···
636
630
/* if we can set the sysfs link */
637
631
if (cti_add_sysfs_link(drvdata, tc))
638
632
/* set the CTI/csdev association */
639
-
coresight_set_assoc_ectdev_mutex(tc->con_dev,
640
-
drvdata->csdev);
633
+
coresight_add_helper(tc->con_dev,
634
+
drvdata->csdev);
641
635
else
642
636
/* otherwise remove reference from CTI */
643
637
tc->con_dev = NULL;
···
652
646
653
647
list_for_each_entry(tc, &ctidev->trig_cons, node) {
654
648
if (tc->con_dev) {
655
-
coresight_set_assoc_ectdev_mutex(tc->con_dev,
656
-
NULL);
657
649
cti_remove_sysfs_link(drvdata, tc);
658
650
tc->con_dev = NULL;
659
651
}
···
799
795
}
800
796
801
797
/** cti ect operations **/
802
-
int cti_enable(struct coresight_device *csdev)
798
+
int cti_enable(struct coresight_device *csdev, enum cs_mode mode, void *data)
803
799
{
804
800
struct cti_drvdata *drvdata = csdev_to_cti_drvdata(csdev);
805
801
806
802
return cti_enable_hw(drvdata);
807
803
}
808
804
809
-
int cti_disable(struct coresight_device *csdev)
805
+
int cti_disable(struct coresight_device *csdev, void *data)
810
806
{
811
807
struct cti_drvdata *drvdata = csdev_to_cti_drvdata(csdev);
812
808
813
809
return cti_disable_hw(drvdata);
814
810
}
815
811
816
-
static const struct coresight_ops_ect cti_ops_ect = {
812
+
static const struct coresight_ops_helper cti_ops_ect = {
817
813
.enable = cti_enable,
818
814
.disable = cti_disable,
819
815
};
820
816
821
817
static const struct coresight_ops cti_ops = {
822
-
.ect_ops = &cti_ops_ect,
818
+
.helper_ops = &cti_ops_ect,
823
819
};
824
820
825
821
/*
···
926
922
927
923
/* set up coresight component description */
928
924
cti_desc.pdata = pdata;
929
-
cti_desc.type = CORESIGHT_DEV_TYPE_ECT;
930
-
cti_desc.subtype.ect_subtype = CORESIGHT_DEV_SUBTYPE_ECT_CTI;
925
+
cti_desc.type = CORESIGHT_DEV_TYPE_HELPER;
926
+
cti_desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI;
931
927
cti_desc.ops = &cti_ops;
932
928
cti_desc.groups = drvdata->ctidev.con_groups;
933
929
cti_desc.dev = dev;
+2
-2
drivers/hwtracing/coresight/coresight-cti-sysfs.c
+2
-2
drivers/hwtracing/coresight/coresight-cti-sysfs.c
···
112
112
ret = pm_runtime_resume_and_get(dev->parent);
113
113
if (ret)
114
114
return ret;
115
-
ret = cti_enable(drvdata->csdev);
115
+
ret = cti_enable(drvdata->csdev, CS_MODE_SYSFS, NULL);
116
116
if (ret)
117
117
pm_runtime_put(dev->parent);
118
118
} else {
119
-
ret = cti_disable(drvdata->csdev);
119
+
ret = cti_disable(drvdata->csdev, NULL);
120
120
if (!ret)
121
121
pm_runtime_put(dev->parent);
122
122
}
+2
-2
drivers/hwtracing/coresight/coresight-cti.h
+2
-2
drivers/hwtracing/coresight/coresight-cti.h
···
215
215
const char *assoc_dev_name);
216
216
struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs,
217
217
int out_sigs);
218
-
int cti_enable(struct coresight_device *csdev);
219
-
int cti_disable(struct coresight_device *csdev);
218
+
int cti_enable(struct coresight_device *csdev, enum cs_mode mode, void *data);
219
+
int cti_disable(struct coresight_device *csdev, void *data);
220
220
void cti_write_all_hw_regs(struct cti_drvdata *drvdata);
221
221
void cti_write_intack(struct device *dev, u32 ackval);
222
222
void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value);
+163
drivers/hwtracing/coresight/coresight-dummy.c
+163
drivers/hwtracing/coresight/coresight-dummy.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/coresight.h>
7
+
#include <linux/kernel.h>
8
+
#include <linux/module.h>
9
+
#include <linux/of.h>
10
+
#include <linux/platform_device.h>
11
+
#include <linux/pm_runtime.h>
12
+
13
+
#include "coresight-priv.h"
14
+
15
+
struct dummy_drvdata {
16
+
struct device *dev;
17
+
struct coresight_device *csdev;
18
+
};
19
+
20
+
DEFINE_CORESIGHT_DEVLIST(source_devs, "dummy_source");
21
+
DEFINE_CORESIGHT_DEVLIST(sink_devs, "dummy_sink");
22
+
23
+
static int dummy_source_enable(struct coresight_device *csdev,
24
+
struct perf_event *event, enum cs_mode mode)
25
+
{
26
+
dev_dbg(csdev->dev.parent, "Dummy source enabled\n");
27
+
28
+
return 0;
29
+
}
30
+
31
+
static void dummy_source_disable(struct coresight_device *csdev,
32
+
struct perf_event *event)
33
+
{
34
+
dev_dbg(csdev->dev.parent, "Dummy source disabled\n");
35
+
}
36
+
37
+
static int dummy_sink_enable(struct coresight_device *csdev, enum cs_mode mode,
38
+
void *data)
39
+
{
40
+
dev_dbg(csdev->dev.parent, "Dummy sink enabled\n");
41
+
42
+
return 0;
43
+
}
44
+
45
+
static int dummy_sink_disable(struct coresight_device *csdev)
46
+
{
47
+
dev_dbg(csdev->dev.parent, "Dummy sink disabled\n");
48
+
49
+
return 0;
50
+
}
51
+
52
+
static const struct coresight_ops_source dummy_source_ops = {
53
+
.enable = dummy_source_enable,
54
+
.disable = dummy_source_disable,
55
+
};
56
+
57
+
static const struct coresight_ops dummy_source_cs_ops = {
58
+
.source_ops = &dummy_source_ops,
59
+
};
60
+
61
+
static const struct coresight_ops_sink dummy_sink_ops = {
62
+
.enable = dummy_sink_enable,
63
+
.disable = dummy_sink_disable,
64
+
};
65
+
66
+
static const struct coresight_ops dummy_sink_cs_ops = {
67
+
.sink_ops = &dummy_sink_ops,
68
+
};
69
+
70
+
static int dummy_probe(struct platform_device *pdev)
71
+
{
72
+
struct device *dev = &pdev->dev;
73
+
struct device_node *node = dev->of_node;
74
+
struct coresight_platform_data *pdata;
75
+
struct dummy_drvdata *drvdata;
76
+
struct coresight_desc desc = { 0 };
77
+
78
+
if (of_device_is_compatible(node, "arm,coresight-dummy-source")) {
79
+
80
+
desc.name = coresight_alloc_device_name(&source_devs, dev);
81
+
if (!desc.name)
82
+
return -ENOMEM;
83
+
84
+
desc.type = CORESIGHT_DEV_TYPE_SOURCE;
85
+
desc.subtype.source_subtype =
86
+
CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS;
87
+
desc.ops = &dummy_source_cs_ops;
88
+
} else if (of_device_is_compatible(node, "arm,coresight-dummy-sink")) {
89
+
desc.name = coresight_alloc_device_name(&sink_devs, dev);
90
+
if (!desc.name)
91
+
return -ENOMEM;
92
+
93
+
desc.type = CORESIGHT_DEV_TYPE_SINK;
94
+
desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_DUMMY;
95
+
desc.ops = &dummy_sink_cs_ops;
96
+
} else {
97
+
dev_err(dev, "Device type not set\n");
98
+
return -EINVAL;
99
+
}
100
+
101
+
pdata = coresight_get_platform_data(dev);
102
+
if (IS_ERR(pdata))
103
+
return PTR_ERR(pdata);
104
+
pdev->dev.platform_data = pdata;
105
+
106
+
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
107
+
if (!drvdata)
108
+
return -ENOMEM;
109
+
110
+
drvdata->dev = &pdev->dev;
111
+
platform_set_drvdata(pdev, drvdata);
112
+
113
+
desc.pdata = pdev->dev.platform_data;
114
+
desc.dev = &pdev->dev;
115
+
drvdata->csdev = coresight_register(&desc);
116
+
if (IS_ERR(drvdata->csdev))
117
+
return PTR_ERR(drvdata->csdev);
118
+
119
+
pm_runtime_enable(dev);
120
+
dev_dbg(dev, "Dummy device initialized\n");
121
+
122
+
return 0;
123
+
}
124
+
125
+
static int dummy_remove(struct platform_device *pdev)
126
+
{
127
+
struct dummy_drvdata *drvdata = platform_get_drvdata(pdev);
128
+
struct device *dev = &pdev->dev;
129
+
130
+
pm_runtime_disable(dev);
131
+
coresight_unregister(drvdata->csdev);
132
+
return 0;
133
+
}
134
+
135
+
static const struct of_device_id dummy_match[] = {
136
+
{.compatible = "arm,coresight-dummy-source"},
137
+
{.compatible = "arm,coresight-dummy-sink"},
138
+
{},
139
+
};
140
+
141
+
static struct platform_driver dummy_driver = {
142
+
.probe = dummy_probe,
143
+
.remove = dummy_remove,
144
+
.driver = {
145
+
.name = "coresight-dummy",
146
+
.of_match_table = dummy_match,
147
+
},
148
+
};
149
+
150
+
static int __init dummy_init(void)
151
+
{
152
+
return platform_driver_register(&dummy_driver);
153
+
}
154
+
module_init(dummy_init);
155
+
156
+
static void __exit dummy_exit(void)
157
+
{
158
+
platform_driver_unregister(&dummy_driver);
159
+
}
160
+
module_exit(dummy_exit);
161
+
162
+
MODULE_LICENSE("GPL");
163
+
MODULE_DESCRIPTION("CoreSight dummy driver");
+7
-6
drivers/hwtracing/coresight/coresight-etb10.c
+7
-6
drivers/hwtracing/coresight/coresight-etb10.c
···
163
163
drvdata->mode = CS_MODE_SYSFS;
164
164
}
165
165
166
-
atomic_inc(csdev->refcnt);
166
+
atomic_inc(&csdev->refcnt);
167
167
out:
168
168
spin_unlock_irqrestore(&drvdata->spinlock, flags);
169
169
return ret;
···
199
199
* use for this session.
200
200
*/
201
201
if (drvdata->pid == pid) {
202
-
atomic_inc(csdev->refcnt);
202
+
atomic_inc(&csdev->refcnt);
203
203
goto out;
204
204
}
205
205
···
217
217
/* Associate with monitored process. */
218
218
drvdata->pid = pid;
219
219
drvdata->mode = CS_MODE_PERF;
220
-
atomic_inc(csdev->refcnt);
220
+
atomic_inc(&csdev->refcnt);
221
221
}
222
222
223
223
out:
···
225
225
return ret;
226
226
}
227
227
228
-
static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
228
+
static int etb_enable(struct coresight_device *csdev, enum cs_mode mode,
229
+
void *data)
229
230
{
230
231
int ret;
231
232
···
356
355
357
356
spin_lock_irqsave(&drvdata->spinlock, flags);
358
357
359
-
if (atomic_dec_return(csdev->refcnt)) {
358
+
if (atomic_dec_return(&csdev->refcnt)) {
360
359
spin_unlock_irqrestore(&drvdata->spinlock, flags);
361
360
return -EBUSY;
362
361
}
···
447
446
spin_lock_irqsave(&drvdata->spinlock, flags);
448
447
449
448
/* Don't do anything if another tracer is using this sink */
450
-
if (atomic_read(csdev->refcnt) != 1)
449
+
if (atomic_read(&csdev->refcnt) != 1)
451
450
goto out;
452
451
453
452
__etb_disable_hw(drvdata);
+2
-2
drivers/hwtracing/coresight/coresight-etm-perf.c
+2
-2
drivers/hwtracing/coresight/coresight-etm-perf.c
···
493
493
goto fail_end_stop;
494
494
495
495
/* Finally enable the tracer */
496
-
if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF))
496
+
if (coresight_enable_source(csdev, CS_MODE_PERF, event))
497
497
goto fail_disable_path;
498
498
499
499
/*
···
587
587
return;
588
588
589
589
/* stop tracer */
590
-
source_ops(csdev)->disable(csdev, event);
590
+
coresight_disable_source(csdev, event);
591
591
592
592
/* tell the core */
593
593
event->hw.state = PERF_HES_STOPPED;
+3
-3
drivers/hwtracing/coresight/coresight-etm3x-core.c
+3
-3
drivers/hwtracing/coresight/coresight-etm3x-core.c
···
552
552
return ret;
553
553
}
554
554
555
-
static int etm_enable(struct coresight_device *csdev,
556
-
struct perf_event *event, u32 mode)
555
+
static int etm_enable(struct coresight_device *csdev, struct perf_event *event,
556
+
enum cs_mode mode)
557
557
{
558
558
int ret;
559
559
u32 val;
···
671
671
static void etm_disable(struct coresight_device *csdev,
672
672
struct perf_event *event)
673
673
{
674
-
u32 mode;
674
+
enum cs_mode mode;
675
675
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
676
676
677
677
/*
+11
-9
drivers/hwtracing/coresight/coresight-etm4x-core.c
+11
-9
drivers/hwtracing/coresight/coresight-etm4x-core.c
···
822
822
return ret;
823
823
}
824
824
825
-
static int etm4_enable(struct coresight_device *csdev,
826
-
struct perf_event *event, u32 mode)
825
+
static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
826
+
enum cs_mode mode)
827
827
{
828
828
int ret;
829
829
u32 val;
···
989
989
static void etm4_disable(struct coresight_device *csdev,
990
990
struct perf_event *event)
991
991
{
992
-
u32 mode;
992
+
enum cs_mode mode;
993
993
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
994
994
995
995
/*
···
2190
2190
per_cpu(delayed_probe, cpu) = NULL;
2191
2191
}
2192
2192
2193
-
static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)
2193
+
static void __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)
2194
2194
{
2195
2195
bool had_delayed_probe;
2196
2196
/*
···
2217
2217
cscfg_unregister_csdev(drvdata->csdev);
2218
2218
coresight_unregister(drvdata->csdev);
2219
2219
}
2220
-
2221
-
return 0;
2222
2220
}
2223
2221
2224
2222
static void __exit etm4_remove_amba(struct amba_device *adev)
···
2229
2231
2230
2232
static int __exit etm4_remove_platform_dev(struct platform_device *pdev)
2231
2233
{
2232
-
int ret = 0;
2233
2234
struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2234
2235
2235
2236
if (drvdata)
2236
-
ret = etm4_remove_dev(drvdata);
2237
+
etm4_remove_dev(drvdata);
2237
2238
pm_runtime_disable(&pdev->dev);
2238
-
return ret;
2239
+
return 0;
2239
2240
}
2240
2241
2241
2242
static const struct amba_id etm4_ids[] = {
···
2257
2260
CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2258
2261
CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2259
2262
CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2263
+
/*
2264
+
* Match all PIDs with ETM4 DEVARCH. No need for adding any of the new
2265
+
* CPUs to the list here.
2266
+
*/
2267
+
CS_AMBA_MATCH_ALL_UCI(uci_id_etm4),
2260
2268
{},
2261
2269
};
2262
2270
+18
-9
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+18
-9
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
···
2411
2411
2412
2412
return sysfs_emit(buf, "0x%x\n", trace_id);
2413
2413
}
2414
-
static DEVICE_ATTR_RO(trctraceid);
2415
2414
2416
2415
struct etmv4_reg {
2417
2416
struct coresight_device *csdev;
···
2527
2528
return 0;
2528
2529
}
2529
2530
2530
-
#define coresight_etm4x_reg(name, offset) \
2531
-
&((struct dev_ext_attribute[]) { \
2532
-
{ \
2533
-
__ATTR(name, 0444, coresight_etm4x_reg_show, NULL), \
2534
-
(void *)(unsigned long)offset \
2535
-
} \
2536
-
})[0].attr.attr
2531
+
/*
2532
+
* Macro to set an RO ext attribute with offset and show function.
2533
+
* Offset is used in mgmt group to ensure only correct registers for
2534
+
* the ETM / ETE variant are visible.
2535
+
*/
2536
+
#define coresight_etm4x_reg_showfn(name, offset, showfn) ( \
2537
+
&((struct dev_ext_attribute[]) { \
2538
+
{ \
2539
+
__ATTR(name, 0444, showfn, NULL), \
2540
+
(void *)(unsigned long)offset \
2541
+
} \
2542
+
})[0].attr.attr \
2543
+
)
2544
+
2545
+
/* macro using the default coresight_etm4x_reg_show function */
2546
+
#define coresight_etm4x_reg(name, offset) \
2547
+
coresight_etm4x_reg_showfn(name, offset, coresight_etm4x_reg_show)
2537
2548
2538
2549
static struct attribute *coresight_etmv4_mgmt_attrs[] = {
2539
2550
coresight_etm4x_reg(trcpdcr, TRCPDCR),
···
2558
2549
coresight_etm4x_reg(trcpidr3, TRCPIDR3),
2559
2550
coresight_etm4x_reg(trcoslsr, TRCOSLSR),
2560
2551
coresight_etm4x_reg(trcconfig, TRCCONFIGR),
2561
-
&dev_attr_trctraceid.attr,
2552
+
coresight_etm4x_reg_showfn(trctraceid, TRCTRACEIDR, trctraceid_show),
2562
2553
coresight_etm4x_reg(trcdevarch, TRCDEVARCH),
2563
2554
NULL,
2564
2555
};
+15
-11
drivers/hwtracing/coresight/coresight-funnel.c
+15
-11
drivers/hwtracing/coresight/coresight-funnel.c
···
74
74
return rc;
75
75
}
76
76
77
-
static int funnel_enable(struct coresight_device *csdev, int inport,
78
-
int outport)
77
+
static int funnel_enable(struct coresight_device *csdev,
78
+
struct coresight_connection *in,
79
+
struct coresight_connection *out)
79
80
{
80
81
int rc = 0;
81
82
struct funnel_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
···
84
83
bool first_enable = false;
85
84
86
85
spin_lock_irqsave(&drvdata->spinlock, flags);
87
-
if (atomic_read(&csdev->refcnt[inport]) == 0) {
86
+
if (atomic_read(&in->dest_refcnt) == 0) {
88
87
if (drvdata->base)
89
-
rc = dynamic_funnel_enable_hw(drvdata, inport);
88
+
rc = dynamic_funnel_enable_hw(drvdata, in->dest_port);
90
89
if (!rc)
91
90
first_enable = true;
92
91
}
93
92
if (!rc)
94
-
atomic_inc(&csdev->refcnt[inport]);
93
+
atomic_inc(&in->dest_refcnt);
95
94
spin_unlock_irqrestore(&drvdata->spinlock, flags);
96
95
97
96
if (first_enable)
98
-
dev_dbg(&csdev->dev, "FUNNEL inport %d enabled\n", inport);
97
+
dev_dbg(&csdev->dev, "FUNNEL inport %d enabled\n",
98
+
in->dest_port);
99
99
return rc;
100
100
}
101
101
···
119
117
CS_LOCK(drvdata->base);
120
118
}
121
119
122
-
static void funnel_disable(struct coresight_device *csdev, int inport,
123
-
int outport)
120
+
static void funnel_disable(struct coresight_device *csdev,
121
+
struct coresight_connection *in,
122
+
struct coresight_connection *out)
124
123
{
125
124
struct funnel_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
126
125
unsigned long flags;
127
126
bool last_disable = false;
128
127
129
128
spin_lock_irqsave(&drvdata->spinlock, flags);
130
-
if (atomic_dec_return(&csdev->refcnt[inport]) == 0) {
129
+
if (atomic_dec_return(&in->dest_refcnt) == 0) {
131
130
if (drvdata->base)
132
-
dynamic_funnel_disable_hw(drvdata, inport);
131
+
dynamic_funnel_disable_hw(drvdata, in->dest_port);
133
132
last_disable = true;
134
133
}
135
134
spin_unlock_irqrestore(&drvdata->spinlock, flags);
136
135
137
136
if (last_disable)
138
-
dev_dbg(&csdev->dev, "FUNNEL inport %d disabled\n", inport);
137
+
dev_dbg(&csdev->dev, "FUNNEL inport %d disabled\n",
138
+
in->dest_port);
139
139
}
140
140
141
141
static const struct coresight_ops_link funnel_link_ops = {
+106
-163
drivers/hwtracing/coresight/coresight-platform.c
+106
-163
drivers/hwtracing/coresight/coresight-platform.c
···
19
19
#include <asm/smp_plat.h>
20
20
21
21
#include "coresight-priv.h"
22
+
22
23
/*
23
-
* coresight_alloc_conns: Allocate connections record for each output
24
-
* port from the device.
24
+
* Add an entry to the connection list and assign @conn's contents to it.
25
+
*
26
+
* If the output port is already assigned on this device, return -EINVAL
25
27
*/
26
-
static int coresight_alloc_conns(struct device *dev,
27
-
struct coresight_platform_data *pdata)
28
+
struct coresight_connection *
29
+
coresight_add_out_conn(struct device *dev,
30
+
struct coresight_platform_data *pdata,
31
+
const struct coresight_connection *new_conn)
28
32
{
29
-
if (pdata->nr_outport) {
30
-
pdata->conns = devm_kcalloc(dev, pdata->nr_outport,
31
-
sizeof(*pdata->conns), GFP_KERNEL);
32
-
if (!pdata->conns)
33
-
return -ENOMEM;
33
+
int i;
34
+
struct coresight_connection *conn;
35
+
36
+
/*
37
+
* Warn on any existing duplicate output port.
38
+
*/
39
+
for (i = 0; i < pdata->nr_outconns; ++i) {
40
+
conn = pdata->out_conns[i];
41
+
/* Output == -1 means ignore the port for example for helpers */
42
+
if (conn->src_port != -1 &&
43
+
conn->src_port == new_conn->src_port) {
44
+
dev_warn(dev, "Duplicate output port %d\n",
45
+
conn->src_port);
46
+
return ERR_PTR(-EINVAL);
47
+
}
34
48
}
35
49
50
+
pdata->nr_outconns++;
51
+
pdata->out_conns =
52
+
devm_krealloc_array(dev, pdata->out_conns, pdata->nr_outconns,
53
+
sizeof(*pdata->out_conns), GFP_KERNEL);
54
+
if (!pdata->out_conns)
55
+
return ERR_PTR(-ENOMEM);
56
+
57
+
conn = devm_kmalloc(dev, sizeof(struct coresight_connection),
58
+
GFP_KERNEL);
59
+
if (!conn)
60
+
return ERR_PTR(-ENOMEM);
61
+
62
+
/*
63
+
* Copy the new connection into the allocation, save the pointer to the
64
+
* end of the connection array and also return it in case it needs to be
65
+
* used right away.
66
+
*/
67
+
*conn = *new_conn;
68
+
pdata->out_conns[pdata->nr_outconns - 1] = conn;
69
+
return conn;
70
+
}
71
+
EXPORT_SYMBOL_GPL(coresight_add_out_conn);
72
+
73
+
/*
74
+
* Add an input connection reference to @out_conn in the target's in_conns array
75
+
*
76
+
* @out_conn: Existing output connection to store as an input on the
77
+
* connection's remote device.
78
+
*/
79
+
int coresight_add_in_conn(struct coresight_connection *out_conn)
80
+
{
81
+
int i;
82
+
struct device *dev = out_conn->dest_dev->dev.parent;
83
+
struct coresight_platform_data *pdata = out_conn->dest_dev->pdata;
84
+
85
+
for (i = 0; i < pdata->nr_inconns; ++i)
86
+
if (!pdata->in_conns[i]) {
87
+
pdata->in_conns[i] = out_conn;
88
+
return 0;
89
+
}
90
+
91
+
pdata->nr_inconns++;
92
+
pdata->in_conns =
93
+
devm_krealloc_array(dev, pdata->in_conns, pdata->nr_inconns,
94
+
sizeof(*pdata->in_conns), GFP_KERNEL);
95
+
if (!pdata->in_conns)
96
+
return -ENOMEM;
97
+
pdata->in_conns[pdata->nr_inconns - 1] = out_conn;
36
98
return 0;
37
99
}
100
+
EXPORT_SYMBOL_GPL(coresight_add_in_conn);
38
101
39
102
static struct device *
40
103
coresight_find_device_by_fwnode(struct fwnode_handle *fwnode)
···
146
83
return of_property_read_bool(ep, "slave-mode");
147
84
}
148
85
149
-
static void of_coresight_get_ports_legacy(const struct device_node *node,
150
-
int *nr_inport, int *nr_outport)
151
-
{
152
-
struct device_node *ep = NULL;
153
-
struct of_endpoint endpoint;
154
-
int in = 0, out = 0;
155
-
156
-
/*
157
-
* Avoid warnings in of_graph_get_next_endpoint()
158
-
* if the device doesn't have any graph connections
159
-
*/
160
-
if (!of_graph_is_present(node))
161
-
return;
162
-
do {
163
-
ep = of_graph_get_next_endpoint(node, ep);
164
-
if (!ep)
165
-
break;
166
-
167
-
if (of_graph_parse_endpoint(ep, &endpoint))
168
-
continue;
169
-
170
-
if (of_coresight_legacy_ep_is_input(ep)) {
171
-
in = (endpoint.port + 1 > in) ?
172
-
endpoint.port + 1 : in;
173
-
} else {
174
-
out = (endpoint.port + 1) > out ?
175
-
endpoint.port + 1 : out;
176
-
}
177
-
178
-
} while (ep);
179
-
180
-
*nr_inport = in;
181
-
*nr_outport = out;
182
-
}
183
-
184
86
static struct device_node *of_coresight_get_port_parent(struct device_node *ep)
185
87
{
186
88
struct device_node *parent = of_graph_get_port_parent(ep);
···
162
134
}
163
135
164
136
static inline struct device_node *
165
-
of_coresight_get_input_ports_node(const struct device_node *node)
166
-
{
167
-
return of_get_child_by_name(node, "in-ports");
168
-
}
169
-
170
-
static inline struct device_node *
171
137
of_coresight_get_output_ports_node(const struct device_node *node)
172
138
{
173
139
return of_get_child_by_name(node, "out-ports");
174
-
}
175
-
176
-
static inline int
177
-
of_coresight_count_ports(struct device_node *port_parent)
178
-
{
179
-
int i = 0;
180
-
struct device_node *ep = NULL;
181
-
struct of_endpoint endpoint;
182
-
183
-
while ((ep = of_graph_get_next_endpoint(port_parent, ep))) {
184
-
/* Defer error handling to parsing */
185
-
if (of_graph_parse_endpoint(ep, &endpoint))
186
-
continue;
187
-
if (endpoint.port + 1 > i)
188
-
i = endpoint.port + 1;
189
-
}
190
-
191
-
return i;
192
-
}
193
-
194
-
static void of_coresight_get_ports(const struct device_node *node,
195
-
int *nr_inport, int *nr_outport)
196
-
{
197
-
struct device_node *input_ports = NULL, *output_ports = NULL;
198
-
199
-
input_ports = of_coresight_get_input_ports_node(node);
200
-
output_ports = of_coresight_get_output_ports_node(node);
201
-
202
-
if (input_ports || output_ports) {
203
-
if (input_ports) {
204
-
*nr_inport = of_coresight_count_ports(input_ports);
205
-
of_node_put(input_ports);
206
-
}
207
-
if (output_ports) {
208
-
*nr_outport = of_coresight_count_ports(output_ports);
209
-
of_node_put(output_ports);
210
-
}
211
-
} else {
212
-
/* Fall back to legacy DT bindings parsing */
213
-
of_coresight_get_ports_legacy(node, nr_inport, nr_outport);
214
-
}
215
140
}
216
141
217
142
static int of_coresight_get_cpu(struct device *dev)
···
187
206
188
207
/*
189
208
* of_coresight_parse_endpoint : Parse the given output endpoint @ep
190
-
* and fill the connection information in @conn
209
+
* and fill the connection information in @pdata->out_conns
191
210
*
192
211
* Parses the local port, remote device name and the remote port.
193
212
*
···
205
224
struct device_node *rep = NULL;
206
225
struct device *rdev = NULL;
207
226
struct fwnode_handle *rdev_fwnode;
208
-
struct coresight_connection *conn;
227
+
struct coresight_connection conn = {};
228
+
struct coresight_connection *new_conn;
209
229
210
230
do {
211
231
/* Parse the local port details */
···
233
251
break;
234
252
}
235
253
236
-
conn = &pdata->conns[endpoint.port];
237
-
if (conn->child_fwnode) {
238
-
dev_warn(dev, "Duplicate output port %d\n",
239
-
endpoint.port);
240
-
ret = -EINVAL;
241
-
break;
242
-
}
243
-
conn->outport = endpoint.port;
254
+
conn.src_port = endpoint.port;
244
255
/*
245
256
* Hold the refcount to the target device. This could be
246
257
* released via:
···
242
267
* 2) While removing the target device via
243
268
* coresight_remove_match()
244
269
*/
245
-
conn->child_fwnode = fwnode_handle_get(rdev_fwnode);
246
-
conn->child_port = rendpoint.port;
270
+
conn.dest_fwnode = fwnode_handle_get(rdev_fwnode);
271
+
conn.dest_port = rendpoint.port;
272
+
273
+
new_conn = coresight_add_out_conn(dev, pdata, &conn);
274
+
if (IS_ERR_VALUE(new_conn)) {
275
+
fwnode_handle_put(conn.dest_fwnode);
276
+
return PTR_ERR(new_conn);
277
+
}
247
278
/* Connection record updated */
248
279
} while (0);
249
280
···
269
288
bool legacy_binding = false;
270
289
struct device_node *node = dev->of_node;
271
290
272
-
/* Get the number of input and output port for this component */
273
-
of_coresight_get_ports(node, &pdata->nr_inport, &pdata->nr_outport);
274
-
275
-
/* If there are no output connections, we are done */
276
-
if (!pdata->nr_outport)
277
-
return 0;
278
-
279
-
ret = coresight_alloc_conns(dev, pdata);
280
-
if (ret)
281
-
return ret;
282
-
283
291
parent = of_coresight_get_output_ports_node(node);
284
292
/*
285
293
* If the DT uses obsoleted bindings, the ports are listed
···
276
306
* ports.
277
307
*/
278
308
if (!parent) {
309
+
/*
310
+
* Avoid warnings in of_graph_get_next_endpoint()
311
+
* if the device doesn't have any graph connections
312
+
*/
313
+
if (!of_graph_is_present(node))
314
+
return 0;
279
315
legacy_binding = true;
280
316
parent = node;
281
317
dev_warn_once(dev, "Uses obsolete Coresight DT bindings\n");
···
625
649
626
650
dir = fields[3].integer.value;
627
651
if (dir == ACPI_CORESIGHT_LINK_MASTER) {
628
-
conn->outport = fields[0].integer.value;
629
-
conn->child_port = fields[1].integer.value;
652
+
conn->src_port = fields[0].integer.value;
653
+
conn->dest_port = fields[1].integer.value;
630
654
rdev = coresight_find_device_by_fwnode(&r_adev->fwnode);
631
655
if (!rdev)
632
656
return -EPROBE_DEFER;
···
638
662
* 2) While removing the target device via
639
663
* coresight_remove_match().
640
664
*/
641
-
conn->child_fwnode = fwnode_handle_get(&r_adev->fwnode);
665
+
conn->dest_fwnode = fwnode_handle_get(&r_adev->fwnode);
642
666
} else if (dir == ACPI_CORESIGHT_LINK_SLAVE) {
643
667
/*
644
668
* We are only interested in the port number
645
669
* for the input ports at this component.
646
670
* Store the port number in child_port.
647
671
*/
648
-
conn->child_port = fields[0].integer.value;
672
+
conn->dest_port = fields[0].integer.value;
649
673
} else {
650
674
/* Invalid direction */
651
675
return -EINVAL;
···
659
683
* connection information and populate the supplied coresight_platform_data
660
684
* instance.
661
685
*/
662
-
static int acpi_coresight_parse_graph(struct acpi_device *adev,
686
+
static int acpi_coresight_parse_graph(struct device *dev,
687
+
struct acpi_device *adev,
663
688
struct coresight_platform_data *pdata)
664
689
{
665
-
int rc, i, nlinks;
690
+
int i, nlinks;
666
691
const union acpi_object *graph;
667
-
struct coresight_connection *conns, *ptr;
692
+
struct coresight_connection conn, zero_conn = {};
693
+
struct coresight_connection *new_conn;
668
694
669
-
pdata->nr_inport = pdata->nr_outport = 0;
670
695
graph = acpi_get_coresight_graph(adev);
671
696
if (!graph)
672
697
return -ENOENT;
···
676
699
if (!nlinks)
677
700
return 0;
678
701
679
-
/*
680
-
* To avoid scanning the table twice (once for finding the number of
681
-
* output links and then later for parsing the output links),
682
-
* cache the links information in one go and then later copy
683
-
* it to the pdata.
684
-
*/
685
-
conns = devm_kcalloc(&adev->dev, nlinks, sizeof(*conns), GFP_KERNEL);
686
-
if (!conns)
687
-
return -ENOMEM;
688
-
ptr = conns;
689
702
for (i = 0; i < nlinks; i++) {
690
703
const union acpi_object *link = &graph->package.elements[3 + i];
691
704
int dir;
692
705
693
-
dir = acpi_coresight_parse_link(adev, link, ptr);
706
+
conn = zero_conn;
707
+
dir = acpi_coresight_parse_link(adev, link, &conn);
694
708
if (dir < 0)
695
709
return dir;
696
710
697
711
if (dir == ACPI_CORESIGHT_LINK_MASTER) {
698
-
if (ptr->outport >= pdata->nr_outport)
699
-
pdata->nr_outport = ptr->outport + 1;
700
-
ptr++;
701
-
} else {
702
-
WARN_ON(pdata->nr_inport == ptr->child_port + 1);
703
-
/*
704
-
* We do not track input port connections for a device.
705
-
* However we need the highest port number described,
706
-
* which can be recorded now and reuse this connection
707
-
* record for an output connection. Hence, do not move
708
-
* the ptr for input connections
709
-
*/
710
-
if (ptr->child_port >= pdata->nr_inport)
711
-
pdata->nr_inport = ptr->child_port + 1;
712
+
new_conn = coresight_add_out_conn(dev, pdata, &conn);
713
+
if (IS_ERR(new_conn))
714
+
return PTR_ERR(new_conn);
712
715
}
713
716
}
714
717
715
-
rc = coresight_alloc_conns(&adev->dev, pdata);
716
-
if (rc)
717
-
return rc;
718
-
719
-
/* Copy the connection information to the final location */
720
-
for (i = 0; conns + i < ptr; i++) {
721
-
int port = conns[i].outport;
722
-
723
-
/* Duplicate output port */
724
-
WARN_ON(pdata->conns[port].child_fwnode);
725
-
pdata->conns[port] = conns[i];
726
-
}
727
-
728
-
devm_kfree(&adev->dev, conns);
729
718
return 0;
730
719
}
731
720
···
752
809
if (!adev)
753
810
return -EINVAL;
754
811
755
-
return acpi_coresight_parse_graph(adev, pdata);
812
+
return acpi_coresight_parse_graph(dev, adev, pdata);
756
813
}
757
814
758
815
#else
···
806
863
error:
807
864
if (!IS_ERR_OR_NULL(pdata))
808
865
/* Cleanup the connection information */
809
-
coresight_release_platform_data(NULL, pdata);
866
+
coresight_release_platform_data(NULL, dev, pdata);
810
867
return ERR_PTR(ret);
811
868
}
812
869
EXPORT_SYMBOL_GPL(coresight_get_platform_data);
+25
-11
drivers/hwtracing/coresight/coresight-priv.h
+25
-11
drivers/hwtracing/coresight/coresight-priv.h
···
82
82
ETM_ADDR_TYPE_STOP,
83
83
};
84
84
85
-
enum cs_mode {
86
-
CS_MODE_DISABLED,
87
-
CS_MODE_SYSFS,
88
-
CS_MODE_PERF,
89
-
};
90
-
91
85
/**
92
86
* struct cs_buffer - keep track of a recording session' specifics
93
87
* @cur: index of the current buffer
···
127
133
}
128
134
129
135
void coresight_disable_path(struct list_head *path);
130
-
int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data);
136
+
int coresight_enable_path(struct list_head *path, enum cs_mode mode,
137
+
void *sink_data);
131
138
struct coresight_device *coresight_get_sink(struct list_head *path);
132
139
struct coresight_device *
133
140
coresight_get_enabled_sink(struct coresight_device *source);
···
188
193
}
189
194
190
195
/* coresight AMBA ID, full UCI structure: id table entry. */
191
-
#define CS_AMBA_UCI_ID(pid, uci_ptr) \
196
+
#define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \
192
197
{ \
193
198
.id = pid, \
194
-
.mask = 0x000fffff, \
199
+
.mask = m, \
195
200
.data = (void *)uci_ptr \
196
201
}
202
+
#define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci)
203
+
/*
204
+
* PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the
205
+
* PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that
206
+
* as a match value for blanket matching all devices in the given CoreSight
207
+
* device type and architecture.
208
+
*/
209
+
#define PIDR2_JEDEC BIT(3)
210
+
#define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16)
211
+
/*
212
+
* Match all PIDs in a given CoreSight device type and architecture, defined
213
+
* by the uci.
214
+
*/
215
+
#define CS_AMBA_MATCH_ALL_UCI(uci) \
216
+
__CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)
197
217
198
218
/* extract the data value from a UCI structure given amba_id pointer. */
199
219
static inline void *coresight_get_uci_data(const struct amba_id *id)
···
222
212
}
223
213
224
214
void coresight_release_platform_data(struct coresight_device *csdev,
215
+
struct device *dev,
225
216
struct coresight_platform_data *pdata);
226
217
struct coresight_device *
227
218
coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode);
228
-
void coresight_set_assoc_ectdev_mutex(struct coresight_device *csdev,
229
-
struct coresight_device *ect_csdev);
219
+
void coresight_add_helper(struct coresight_device *csdev,
220
+
struct coresight_device *helper);
230
221
231
222
void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev);
232
223
struct coresight_device *coresight_get_percpu_sink(int cpu);
224
+
int coresight_enable_source(struct coresight_device *csdev, enum cs_mode mode,
225
+
void *data);
226
+
bool coresight_disable_source(struct coresight_device *csdev, void *data);
233
227
234
228
#endif
+13
-10
drivers/hwtracing/coresight/coresight-replicator.c
+13
-10
drivers/hwtracing/coresight/coresight-replicator.c
···
114
114
return rc;
115
115
}
116
116
117
-
static int replicator_enable(struct coresight_device *csdev, int inport,
118
-
int outport)
117
+
static int replicator_enable(struct coresight_device *csdev,
118
+
struct coresight_connection *in,
119
+
struct coresight_connection *out)
119
120
{
120
121
int rc = 0;
121
122
struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
···
124
123
bool first_enable = false;
125
124
126
125
spin_lock_irqsave(&drvdata->spinlock, flags);
127
-
if (atomic_read(&csdev->refcnt[outport]) == 0) {
126
+
if (atomic_read(&out->src_refcnt) == 0) {
128
127
if (drvdata->base)
129
-
rc = dynamic_replicator_enable(drvdata, inport,
130
-
outport);
128
+
rc = dynamic_replicator_enable(drvdata, in->dest_port,
129
+
out->src_port);
131
130
if (!rc)
132
131
first_enable = true;
133
132
}
134
133
if (!rc)
135
-
atomic_inc(&csdev->refcnt[outport]);
134
+
atomic_inc(&out->src_refcnt);
136
135
spin_unlock_irqrestore(&drvdata->spinlock, flags);
137
136
138
137
if (first_enable)
···
169
168
CS_LOCK(drvdata->base);
170
169
}
171
170
172
-
static void replicator_disable(struct coresight_device *csdev, int inport,
173
-
int outport)
171
+
static void replicator_disable(struct coresight_device *csdev,
172
+
struct coresight_connection *in,
173
+
struct coresight_connection *out)
174
174
{
175
175
struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
176
176
unsigned long flags;
177
177
bool last_disable = false;
178
178
179
179
spin_lock_irqsave(&drvdata->spinlock, flags);
180
-
if (atomic_dec_return(&csdev->refcnt[outport]) == 0) {
180
+
if (atomic_dec_return(&out->src_refcnt) == 0) {
181
181
if (drvdata->base)
182
-
dynamic_replicator_disable(drvdata, inport, outport);
182
+
dynamic_replicator_disable(drvdata, in->dest_port,
183
+
out->src_port);
183
184
last_disable = true;
184
185
}
185
186
spin_unlock_irqrestore(&drvdata->spinlock, flags);
+3
-3
drivers/hwtracing/coresight/coresight-stm.c
+3
-3
drivers/hwtracing/coresight/coresight-stm.c
···
119
119
* @spinlock: only one at a time pls.
120
120
* @chs: the channels accociated to this STM.
121
121
* @stm: structure associated to the generic STM interface.
122
-
* @mode: this tracer's mode, i.e sysFS, or disabled.
122
+
* @mode: this tracer's mode (enum cs_mode), i.e sysFS, or disabled.
123
123
* @traceid: value of the current ID for this component.
124
124
* @write_bytes: Maximus bytes this STM can write at a time.
125
125
* @stmsper: settings for register STMSPER.
···
192
192
CS_LOCK(drvdata->base);
193
193
}
194
194
195
-
static int stm_enable(struct coresight_device *csdev,
196
-
struct perf_event *event, u32 mode)
195
+
static int stm_enable(struct coresight_device *csdev, struct perf_event *event,
196
+
enum cs_mode mode)
197
197
{
198
198
u32 val;
199
199
struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+7
-10
drivers/hwtracing/coresight/coresight-sysfs.c
+7
-10
drivers/hwtracing/coresight/coresight-sysfs.c
···
148
148
char *outs = NULL, *ins = NULL;
149
149
struct coresight_sysfs_link *link = NULL;
150
150
151
+
/* Helper devices aren't shown in sysfs */
152
+
if (conn->dest_port == -1 && conn->src_port == -1)
153
+
return 0;
154
+
151
155
do {
152
156
outs = devm_kasprintf(&orig->dev, GFP_KERNEL,
153
-
"out:%d", conn->outport);
157
+
"out:%d", conn->src_port);
154
158
if (!outs)
155
159
break;
156
160
ins = devm_kasprintf(&target->dev, GFP_KERNEL,
157
-
"in:%d", conn->child_port);
161
+
"in:%d", conn->dest_port);
158
162
if (!ins)
159
163
break;
160
164
link = devm_kzalloc(&orig->dev,
···
177
173
break;
178
174
179
175
conn->link = link;
180
-
181
-
/*
182
-
* Install the device connection. This also indicates that
183
-
* the links are operational on both ends.
184
-
*/
185
-
conn->child_dev = target;
186
176
return 0;
187
177
} while (0);
188
178
···
196
198
197
199
coresight_remove_sysfs_link(conn->link);
198
200
199
-
devm_kfree(&conn->child_dev->dev, conn->link->target_name);
201
+
devm_kfree(&conn->dest_dev->dev, conn->link->target_name);
200
202
devm_kfree(&orig->dev, conn->link->orig_name);
201
203
devm_kfree(&orig->dev, conn->link);
202
204
conn->link = NULL;
203
-
conn->child_dev = NULL;
204
205
}
+14
-12
drivers/hwtracing/coresight/coresight-tmc-etf.c
+14
-12
drivers/hwtracing/coresight/coresight-tmc-etf.c
···
206
206
* touched.
207
207
*/
208
208
if (drvdata->mode == CS_MODE_SYSFS) {
209
-
atomic_inc(csdev->refcnt);
209
+
atomic_inc(&csdev->refcnt);
210
210
goto out;
211
211
}
212
212
···
229
229
ret = tmc_etb_enable_hw(drvdata);
230
230
if (!ret) {
231
231
drvdata->mode = CS_MODE_SYSFS;
232
-
atomic_inc(csdev->refcnt);
232
+
atomic_inc(&csdev->refcnt);
233
233
} else {
234
234
/* Free up the buffer if we failed to enable */
235
235
used = false;
···
284
284
* use for this session.
285
285
*/
286
286
if (drvdata->pid == pid) {
287
-
atomic_inc(csdev->refcnt);
287
+
atomic_inc(&csdev->refcnt);
288
288
break;
289
289
}
290
290
···
293
293
/* Associate with monitored process. */
294
294
drvdata->pid = pid;
295
295
drvdata->mode = CS_MODE_PERF;
296
-
atomic_inc(csdev->refcnt);
296
+
atomic_inc(&csdev->refcnt);
297
297
}
298
298
} while (0);
299
299
spin_unlock_irqrestore(&drvdata->spinlock, flags);
···
302
302
}
303
303
304
304
static int tmc_enable_etf_sink(struct coresight_device *csdev,
305
-
u32 mode, void *data)
305
+
enum cs_mode mode, void *data)
306
306
{
307
307
int ret;
308
308
···
338
338
return -EBUSY;
339
339
}
340
340
341
-
if (atomic_dec_return(csdev->refcnt)) {
341
+
if (atomic_dec_return(&csdev->refcnt)) {
342
342
spin_unlock_irqrestore(&drvdata->spinlock, flags);
343
343
return -EBUSY;
344
344
}
···
357
357
}
358
358
359
359
static int tmc_enable_etf_link(struct coresight_device *csdev,
360
-
int inport, int outport)
360
+
struct coresight_connection *in,
361
+
struct coresight_connection *out)
361
362
{
362
363
int ret = 0;
363
364
unsigned long flags;
···
371
370
return -EBUSY;
372
371
}
373
372
374
-
if (atomic_read(&csdev->refcnt[0]) == 0) {
373
+
if (atomic_read(&csdev->refcnt) == 0) {
375
374
ret = tmc_etf_enable_hw(drvdata);
376
375
if (!ret) {
377
376
drvdata->mode = CS_MODE_SYSFS;
···
379
378
}
380
379
}
381
380
if (!ret)
382
-
atomic_inc(&csdev->refcnt[0]);
381
+
atomic_inc(&csdev->refcnt);
383
382
spin_unlock_irqrestore(&drvdata->spinlock, flags);
384
383
385
384
if (first_enable)
···
388
387
}
389
388
390
389
static void tmc_disable_etf_link(struct coresight_device *csdev,
391
-
int inport, int outport)
390
+
struct coresight_connection *in,
391
+
struct coresight_connection *out)
392
392
{
393
393
unsigned long flags;
394
394
struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
···
401
399
return;
402
400
}
403
401
404
-
if (atomic_dec_return(&csdev->refcnt[0]) == 0) {
402
+
if (atomic_dec_return(&csdev->refcnt) == 0) {
405
403
tmc_etf_disable_hw(drvdata);
406
404
drvdata->mode = CS_MODE_DISABLED;
407
405
last_disable = true;
···
489
487
spin_lock_irqsave(&drvdata->spinlock, flags);
490
488
491
489
/* Don't do anything if another tracer is using this sink */
492
-
if (atomic_read(csdev->refcnt) != 1)
490
+
if (atomic_read(&csdev->refcnt) != 1)
493
491
goto out;
494
492
495
493
CS_UNLOCK(drvdata->base);
+57
-53
drivers/hwtracing/coresight/coresight-tmc-etr.c
+57
-53
drivers/hwtracing/coresight/coresight-tmc-etr.c
···
775
775
struct coresight_device *
776
776
tmc_etr_get_catu_device(struct tmc_drvdata *drvdata)
777
777
{
778
-
int i;
779
-
struct coresight_device *tmp, *etr = drvdata->csdev;
778
+
struct coresight_device *etr = drvdata->csdev;
779
+
union coresight_dev_subtype catu_subtype = {
780
+
.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CATU
781
+
};
780
782
781
783
if (!IS_ENABLED(CONFIG_CORESIGHT_CATU))
782
784
return NULL;
783
785
784
-
for (i = 0; i < etr->pdata->nr_outport; i++) {
785
-
tmp = etr->pdata->conns[i].child_dev;
786
-
if (tmp && coresight_is_catu_device(tmp))
787
-
return tmp;
788
-
}
789
-
790
-
return NULL;
786
+
return coresight_find_output_type(etr->pdata, CORESIGHT_DEV_TYPE_HELPER,
787
+
catu_subtype);
791
788
}
792
789
EXPORT_SYMBOL_GPL(tmc_etr_get_catu_device);
793
-
794
-
static inline int tmc_etr_enable_catu(struct tmc_drvdata *drvdata,
795
-
struct etr_buf *etr_buf)
796
-
{
797
-
struct coresight_device *catu = tmc_etr_get_catu_device(drvdata);
798
-
799
-
if (catu && helper_ops(catu)->enable)
800
-
return helper_ops(catu)->enable(catu, etr_buf);
801
-
return 0;
802
-
}
803
-
804
-
static inline void tmc_etr_disable_catu(struct tmc_drvdata *drvdata)
805
-
{
806
-
struct coresight_device *catu = tmc_etr_get_catu_device(drvdata);
807
-
808
-
if (catu && helper_ops(catu)->disable)
809
-
helper_ops(catu)->disable(catu, drvdata->etr_buf);
810
-
}
811
790
812
791
static const struct etr_buf_operations *etr_buf_ops[] = {
813
792
[ETR_MODE_FLAT] = &etr_flat_buf_ops,
···
1037
1058
if (WARN_ON(drvdata->etr_buf))
1038
1059
return -EBUSY;
1039
1060
1040
-
/*
1041
-
* If this ETR is connected to a CATU, enable it before we turn
1042
-
* this on.
1043
-
*/
1044
-
rc = tmc_etr_enable_catu(drvdata, etr_buf);
1045
-
if (rc)
1046
-
return rc;
1047
1061
rc = coresight_claim_device(drvdata->csdev);
1048
1062
if (!rc) {
1049
1063
drvdata->etr_buf = etr_buf;
···
1044
1072
if (rc) {
1045
1073
drvdata->etr_buf = NULL;
1046
1074
coresight_disclaim_device(drvdata->csdev);
1047
-
tmc_etr_disable_catu(drvdata);
1048
1075
}
1049
1076
}
1050
1077
···
1133
1162
void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
1134
1163
{
1135
1164
__tmc_etr_disable_hw(drvdata);
1136
-
/* Disable CATU device if this ETR is connected to one */
1137
-
tmc_etr_disable_catu(drvdata);
1138
1165
coresight_disclaim_device(drvdata->csdev);
1139
1166
/* Reset the ETR buf used by hardware */
1140
1167
drvdata->etr_buf = NULL;
1141
1168
}
1142
1169
1143
-
static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
1170
+
static struct etr_buf *tmc_etr_get_sysfs_buffer(struct coresight_device *csdev)
1144
1171
{
1145
1172
int ret = 0;
1146
1173
unsigned long flags;
···
1161
1192
/* Allocate memory with the locks released */
1162
1193
free_buf = new_buf = tmc_etr_setup_sysfs_buf(drvdata);
1163
1194
if (IS_ERR(new_buf))
1164
-
return PTR_ERR(new_buf);
1195
+
return new_buf;
1165
1196
1166
1197
/* Let's try again */
1167
1198
spin_lock_irqsave(&drvdata->spinlock, flags);
···
1178
1209
* touched, even if the buffer size has changed.
1179
1210
*/
1180
1211
if (drvdata->mode == CS_MODE_SYSFS) {
1181
-
atomic_inc(csdev->refcnt);
1212
+
atomic_inc(&csdev->refcnt);
1182
1213
goto out;
1183
1214
}
1184
1215
···
1192
1223
drvdata->sysfs_buf = new_buf;
1193
1224
}
1194
1225
1195
-
ret = tmc_etr_enable_hw(drvdata, drvdata->sysfs_buf);
1196
-
if (!ret) {
1197
-
drvdata->mode = CS_MODE_SYSFS;
1198
-
atomic_inc(csdev->refcnt);
1199
-
}
1200
1226
out:
1201
1227
spin_unlock_irqrestore(&drvdata->spinlock, flags);
1202
1228
1203
1229
/* Free memory outside the spinlock if need be */
1204
1230
if (free_buf)
1205
1231
tmc_etr_free_sysfs_buf(free_buf);
1232
+
return ret ? ERR_PTR(ret) : drvdata->sysfs_buf;
1233
+
}
1234
+
1235
+
static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
1236
+
{
1237
+
int ret;
1238
+
unsigned long flags;
1239
+
struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
1240
+
struct etr_buf *sysfs_buf = tmc_etr_get_sysfs_buffer(csdev);
1241
+
1242
+
if (IS_ERR(sysfs_buf))
1243
+
return PTR_ERR(sysfs_buf);
1244
+
1245
+
spin_lock_irqsave(&drvdata->spinlock, flags);
1246
+
ret = tmc_etr_enable_hw(drvdata, sysfs_buf);
1247
+
if (!ret) {
1248
+
drvdata->mode = CS_MODE_SYSFS;
1249
+
atomic_inc(&csdev->refcnt);
1250
+
}
1251
+
1252
+
spin_unlock_irqrestore(&drvdata->spinlock, flags);
1206
1253
1207
1254
if (!ret)
1208
1255
dev_dbg(&csdev->dev, "TMC-ETR enabled\n");
1209
1256
1210
1257
return ret;
1211
1258
}
1259
+
1260
+
struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev,
1261
+
enum cs_mode mode, void *data)
1262
+
{
1263
+
struct perf_output_handle *handle = data;
1264
+
struct etr_perf_buffer *etr_perf;
1265
+
1266
+
switch (mode) {
1267
+
case CS_MODE_SYSFS:
1268
+
return tmc_etr_get_sysfs_buffer(csdev);
1269
+
case CS_MODE_PERF:
1270
+
etr_perf = etm_perf_sink_config(handle);
1271
+
if (WARN_ON(!etr_perf || !etr_perf->etr_buf))
1272
+
return ERR_PTR(-EINVAL);
1273
+
return etr_perf->etr_buf;
1274
+
default:
1275
+
return ERR_PTR(-EINVAL);
1276
+
}
1277
+
}
1278
+
EXPORT_SYMBOL_GPL(tmc_etr_get_buffer);
1212
1279
1213
1280
/*
1214
1281
* alloc_etr_buf: Allocate ETR buffer for use by perf.
···
1540
1535
spin_lock_irqsave(&drvdata->spinlock, flags);
1541
1536
1542
1537
/* Don't do anything if another tracer is using this sink */
1543
-
if (atomic_read(csdev->refcnt) != 1) {
1538
+
if (atomic_read(&csdev->refcnt) != 1) {
1544
1539
spin_unlock_irqrestore(&drvdata->spinlock, flags);
1545
1540
goto out;
1546
1541
}
···
1652
1647
* use for this session.
1653
1648
*/
1654
1649
if (drvdata->pid == pid) {
1655
-
atomic_inc(csdev->refcnt);
1650
+
atomic_inc(&csdev->refcnt);
1656
1651
goto unlock_out;
1657
1652
}
1658
1653
···
1662
1657
drvdata->pid = pid;
1663
1658
drvdata->mode = CS_MODE_PERF;
1664
1659
drvdata->perf_buf = etr_perf->etr_buf;
1665
-
atomic_inc(csdev->refcnt);
1660
+
atomic_inc(&csdev->refcnt);
1666
1661
}
1667
1662
1668
1663
unlock_out:
···
1671
1666
}
1672
1667
1673
1668
static int tmc_enable_etr_sink(struct coresight_device *csdev,
1674
-
u32 mode, void *data)
1669
+
enum cs_mode mode, void *data)
1675
1670
{
1676
1671
switch (mode) {
1677
1672
case CS_MODE_SYSFS:
1678
1673
return tmc_enable_etr_sink_sysfs(csdev);
1679
1674
case CS_MODE_PERF:
1680
1675
return tmc_enable_etr_sink_perf(csdev, data);
1676
+
default:
1677
+
return -EINVAL;
1681
1678
}
1682
-
1683
-
/* We shouldn't be here */
1684
-
return -EINVAL;
1685
1679
}
1686
1680
1687
1681
static int tmc_disable_etr_sink(struct coresight_device *csdev)
···
1695
1691
return -EBUSY;
1696
1692
}
1697
1693
1698
-
if (atomic_dec_return(csdev->refcnt)) {
1694
+
if (atomic_dec_return(&csdev->refcnt)) {
1699
1695
spin_unlock_irqrestore(&drvdata->spinlock, flags);
1700
1696
return -EBUSY;
1701
1697
}
+2
drivers/hwtracing/coresight/coresight-tmc.h
+2
drivers/hwtracing/coresight/coresight-tmc.h
+13
-10
drivers/hwtracing/coresight/coresight-tpda.c
+13
-10
drivers/hwtracing/coresight/coresight-tpda.c
···
54
54
CS_LOCK(drvdata->base);
55
55
}
56
56
57
-
static int tpda_enable(struct coresight_device *csdev, int inport, int outport)
57
+
static int tpda_enable(struct coresight_device *csdev,
58
+
struct coresight_connection *in,
59
+
struct coresight_connection *out)
58
60
{
59
61
struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
60
62
61
63
spin_lock(&drvdata->spinlock);
62
-
if (atomic_read(&csdev->refcnt[inport]) == 0)
63
-
__tpda_enable(drvdata, inport);
64
+
if (atomic_read(&in->dest_refcnt) == 0)
65
+
__tpda_enable(drvdata, in->dest_port);
64
66
65
-
atomic_inc(&csdev->refcnt[inport]);
67
+
atomic_inc(&in->dest_refcnt);
66
68
spin_unlock(&drvdata->spinlock);
67
69
68
-
dev_dbg(drvdata->dev, "TPDA inport %d enabled.\n", inport);
70
+
dev_dbg(drvdata->dev, "TPDA inport %d enabled.\n", in->dest_port);
69
71
return 0;
70
72
}
71
73
···
84
82
CS_LOCK(drvdata->base);
85
83
}
86
84
87
-
static void tpda_disable(struct coresight_device *csdev, int inport,
88
-
int outport)
85
+
static void tpda_disable(struct coresight_device *csdev,
86
+
struct coresight_connection *in,
87
+
struct coresight_connection *out)
89
88
{
90
89
struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
91
90
92
91
spin_lock(&drvdata->spinlock);
93
-
if (atomic_dec_return(&csdev->refcnt[inport]) == 0)
94
-
__tpda_disable(drvdata, inport);
92
+
if (atomic_dec_return(&in->dest_refcnt) == 0)
93
+
__tpda_disable(drvdata, in->dest_port);
95
94
96
95
spin_unlock(&drvdata->spinlock);
97
96
98
-
dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", inport);
97
+
dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", in->dest_port);
99
98
}
100
99
101
100
static const struct coresight_ops_link tpda_link_ops = {
+2
-2
drivers/hwtracing/coresight/coresight-tpdm.c
+2
-2
drivers/hwtracing/coresight/coresight-tpdm.c
···
42
42
CS_LOCK(drvdata->base);
43
43
}
44
44
45
-
static int tpdm_enable(struct coresight_device *csdev,
46
-
struct perf_event *event, u32 mode)
45
+
static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event,
46
+
enum cs_mode mode)
47
47
{
48
48
struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
49
49
+4
-3
drivers/hwtracing/coresight/coresight-tpiu.c
+4
-3
drivers/hwtracing/coresight/coresight-tpiu.c
···
69
69
CS_LOCK(csa->base);
70
70
}
71
71
72
-
static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused)
72
+
static int tpiu_enable(struct coresight_device *csdev, enum cs_mode mode,
73
+
void *__unused)
73
74
{
74
75
tpiu_enable_hw(&csdev->access);
75
-
atomic_inc(csdev->refcnt);
76
+
atomic_inc(&csdev->refcnt);
76
77
dev_dbg(&csdev->dev, "TPIU enabled\n");
77
78
return 0;
78
79
}
···
96
95
97
96
static int tpiu_disable(struct coresight_device *csdev)
98
97
{
99
-
if (atomic_dec_return(csdev->refcnt))
98
+
if (atomic_dec_return(&csdev->refcnt))
100
99
return -EBUSY;
101
100
102
101
tpiu_disable_hw(&csdev->access);
+2
-1
drivers/hwtracing/coresight/coresight-trbe.c
+2
-1
drivers/hwtracing/coresight/coresight-trbe.c
···
1006
1006
return ret;
1007
1007
}
1008
1008
1009
-
static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
1009
+
static int arm_trbe_enable(struct coresight_device *csdev, enum cs_mode mode,
1010
+
void *data)
1010
1011
{
1011
1012
struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
1012
1013
struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
+6
-5
drivers/hwtracing/coresight/ultrasoc-smb.c
+6
-5
drivers/hwtracing/coresight/ultrasoc-smb.c
···
106
106
goto out;
107
107
}
108
108
109
-
if (atomic_read(drvdata->csdev->refcnt)) {
109
+
if (atomic_read(&drvdata->csdev->refcnt)) {
110
110
ret = -EBUSY;
111
111
goto out;
112
112
}
···
256
256
return 0;
257
257
}
258
258
259
-
static int smb_enable(struct coresight_device *csdev, u32 mode, void *data)
259
+
static int smb_enable(struct coresight_device *csdev, enum cs_mode mode,
260
+
void *data)
260
261
{
261
262
struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent);
262
263
int ret = 0;
···
290
289
if (ret)
291
290
goto out;
292
291
293
-
atomic_inc(csdev->refcnt);
292
+
atomic_inc(&csdev->refcnt);
294
293
295
294
dev_dbg(&csdev->dev, "Ultrasoc SMB enabled\n");
296
295
out:
···
311
310
goto out;
312
311
}
313
312
314
-
if (atomic_dec_return(csdev->refcnt)) {
313
+
if (atomic_dec_return(&csdev->refcnt)) {
315
314
ret = -EBUSY;
316
315
goto out;
317
316
}
···
411
410
mutex_lock(&drvdata->mutex);
412
411
413
412
/* Don't do anything if another tracer is using this sink. */
414
-
if (atomic_read(csdev->refcnt) != 1)
413
+
if (atomic_read(&csdev->refcnt) != 1)
415
414
goto out;
416
415
417
416
smb_disable_hw(drvdata);
+1
-1
drivers/hwtracing/coresight/ultrasoc-smb.h
+1
-1
drivers/hwtracing/coresight/ultrasoc-smb.h
+409
-35
drivers/hwtracing/ptt/hisi_ptt.c
+409
-35
drivers/hwtracing/ptt/hisi_ptt.c
···
341
341
if (ret < 0)
342
342
return ret;
343
343
344
-
ret = devm_request_threaded_irq(&pdev->dev,
345
-
pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ),
344
+
hisi_ptt->trace_irq = pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ);
345
+
ret = devm_request_threaded_irq(&pdev->dev, hisi_ptt->trace_irq,
346
346
NULL, hisi_ptt_isr, 0,
347
347
DRV_NAME, hisi_ptt);
348
348
if (ret) {
349
349
pci_err(pdev, "failed to request irq %d, ret = %d\n",
350
-
pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ), ret);
350
+
hisi_ptt->trace_irq, ret);
351
351
return ret;
352
352
}
353
+
354
+
return 0;
355
+
}
356
+
357
+
static void hisi_ptt_del_free_filter(struct hisi_ptt *hisi_ptt,
358
+
struct hisi_ptt_filter_desc *filter)
359
+
{
360
+
if (filter->is_port)
361
+
hisi_ptt->port_mask &= ~hisi_ptt_get_filter_val(filter->devid, true);
362
+
363
+
list_del(&filter->list);
364
+
kfree(filter->name);
365
+
kfree(filter);
366
+
}
367
+
368
+
static struct hisi_ptt_filter_desc *
369
+
hisi_ptt_alloc_add_filter(struct hisi_ptt *hisi_ptt, u16 devid, bool is_port)
370
+
{
371
+
struct hisi_ptt_filter_desc *filter;
372
+
u8 devfn = devid & 0xff;
373
+
char *filter_name;
374
+
375
+
filter_name = kasprintf(GFP_KERNEL, "%04x:%02x:%02x.%d", pci_domain_nr(hisi_ptt->pdev->bus),
376
+
PCI_BUS_NUM(devid), PCI_SLOT(devfn), PCI_FUNC(devfn));
377
+
if (!filter_name) {
378
+
pci_err(hisi_ptt->pdev, "failed to allocate name for filter %04x:%02x:%02x.%d\n",
379
+
pci_domain_nr(hisi_ptt->pdev->bus), PCI_BUS_NUM(devid),
380
+
PCI_SLOT(devfn), PCI_FUNC(devfn));
381
+
return NULL;
382
+
}
383
+
384
+
filter = kzalloc(sizeof(*filter), GFP_KERNEL);
385
+
if (!filter) {
386
+
pci_err(hisi_ptt->pdev, "failed to add filter for %s\n",
387
+
filter_name);
388
+
kfree(filter_name);
389
+
return NULL;
390
+
}
391
+
392
+
filter->name = filter_name;
393
+
filter->is_port = is_port;
394
+
filter->devid = devid;
395
+
396
+
if (filter->is_port) {
397
+
list_add_tail(&filter->list, &hisi_ptt->port_filters);
398
+
399
+
/* Update the available port mask */
400
+
hisi_ptt->port_mask |= hisi_ptt_get_filter_val(filter->devid, true);
401
+
} else {
402
+
list_add_tail(&filter->list, &hisi_ptt->req_filters);
403
+
}
404
+
405
+
return filter;
406
+
}
407
+
408
+
static ssize_t hisi_ptt_filter_show(struct device *dev, struct device_attribute *attr,
409
+
char *buf)
410
+
{
411
+
struct hisi_ptt_filter_desc *filter;
412
+
unsigned long filter_val;
413
+
414
+
filter = container_of(attr, struct hisi_ptt_filter_desc, attr);
415
+
filter_val = hisi_ptt_get_filter_val(filter->devid, filter->is_port) |
416
+
(filter->is_port ? HISI_PTT_PMU_FILTER_IS_PORT : 0);
417
+
418
+
return sysfs_emit(buf, "0x%05lx\n", filter_val);
419
+
}
420
+
421
+
static int hisi_ptt_create_rp_filter_attr(struct hisi_ptt *hisi_ptt,
422
+
struct hisi_ptt_filter_desc *filter)
423
+
{
424
+
struct kobject *kobj = &hisi_ptt->hisi_ptt_pmu.dev->kobj;
425
+
426
+
sysfs_attr_init(&filter->attr.attr);
427
+
filter->attr.attr.name = filter->name;
428
+
filter->attr.attr.mode = 0400; /* DEVICE_ATTR_ADMIN_RO */
429
+
filter->attr.show = hisi_ptt_filter_show;
430
+
431
+
return sysfs_add_file_to_group(kobj, &filter->attr.attr,
432
+
HISI_PTT_RP_FILTERS_GRP_NAME);
433
+
}
434
+
435
+
static void hisi_ptt_remove_rp_filter_attr(struct hisi_ptt *hisi_ptt,
436
+
struct hisi_ptt_filter_desc *filter)
437
+
{
438
+
struct kobject *kobj = &hisi_ptt->hisi_ptt_pmu.dev->kobj;
439
+
440
+
sysfs_remove_file_from_group(kobj, &filter->attr.attr,
441
+
HISI_PTT_RP_FILTERS_GRP_NAME);
442
+
}
443
+
444
+
static int hisi_ptt_create_req_filter_attr(struct hisi_ptt *hisi_ptt,
445
+
struct hisi_ptt_filter_desc *filter)
446
+
{
447
+
struct kobject *kobj = &hisi_ptt->hisi_ptt_pmu.dev->kobj;
448
+
449
+
sysfs_attr_init(&filter->attr.attr);
450
+
filter->attr.attr.name = filter->name;
451
+
filter->attr.attr.mode = 0400; /* DEVICE_ATTR_ADMIN_RO */
452
+
filter->attr.show = hisi_ptt_filter_show;
453
+
454
+
return sysfs_add_file_to_group(kobj, &filter->attr.attr,
455
+
HISI_PTT_REQ_FILTERS_GRP_NAME);
456
+
}
457
+
458
+
static void hisi_ptt_remove_req_filter_attr(struct hisi_ptt *hisi_ptt,
459
+
struct hisi_ptt_filter_desc *filter)
460
+
{
461
+
struct kobject *kobj = &hisi_ptt->hisi_ptt_pmu.dev->kobj;
462
+
463
+
sysfs_remove_file_from_group(kobj, &filter->attr.attr,
464
+
HISI_PTT_REQ_FILTERS_GRP_NAME);
465
+
}
466
+
467
+
static int hisi_ptt_create_filter_attr(struct hisi_ptt *hisi_ptt,
468
+
struct hisi_ptt_filter_desc *filter)
469
+
{
470
+
int ret;
471
+
472
+
if (filter->is_port)
473
+
ret = hisi_ptt_create_rp_filter_attr(hisi_ptt, filter);
474
+
else
475
+
ret = hisi_ptt_create_req_filter_attr(hisi_ptt, filter);
476
+
477
+
if (ret)
478
+
pci_err(hisi_ptt->pdev, "failed to create sysfs attribute for filter %s\n",
479
+
filter->name);
480
+
481
+
return ret;
482
+
}
483
+
484
+
static void hisi_ptt_remove_filter_attr(struct hisi_ptt *hisi_ptt,
485
+
struct hisi_ptt_filter_desc *filter)
486
+
{
487
+
if (filter->is_port)
488
+
hisi_ptt_remove_rp_filter_attr(hisi_ptt, filter);
489
+
else
490
+
hisi_ptt_remove_req_filter_attr(hisi_ptt, filter);
491
+
}
492
+
493
+
static void hisi_ptt_remove_all_filter_attributes(void *data)
494
+
{
495
+
struct hisi_ptt_filter_desc *filter;
496
+
struct hisi_ptt *hisi_ptt = data;
497
+
498
+
mutex_lock(&hisi_ptt->filter_lock);
499
+
500
+
list_for_each_entry(filter, &hisi_ptt->req_filters, list)
501
+
hisi_ptt_remove_filter_attr(hisi_ptt, filter);
502
+
503
+
list_for_each_entry(filter, &hisi_ptt->port_filters, list)
504
+
hisi_ptt_remove_filter_attr(hisi_ptt, filter);
505
+
506
+
hisi_ptt->sysfs_inited = false;
507
+
mutex_unlock(&hisi_ptt->filter_lock);
508
+
}
509
+
510
+
static int hisi_ptt_init_filter_attributes(struct hisi_ptt *hisi_ptt)
511
+
{
512
+
struct hisi_ptt_filter_desc *filter;
513
+
int ret;
514
+
515
+
mutex_lock(&hisi_ptt->filter_lock);
516
+
517
+
/*
518
+
* Register the reset callback in the first stage. In reset we traverse
519
+
* the filters list to remove the sysfs attributes so the callback can
520
+
* be called safely even without below filter attributes creation.
521
+
*/
522
+
ret = devm_add_action(&hisi_ptt->pdev->dev,
523
+
hisi_ptt_remove_all_filter_attributes,
524
+
hisi_ptt);
525
+
if (ret)
526
+
goto out;
527
+
528
+
list_for_each_entry(filter, &hisi_ptt->port_filters, list) {
529
+
ret = hisi_ptt_create_filter_attr(hisi_ptt, filter);
530
+
if (ret)
531
+
goto out;
532
+
}
533
+
534
+
list_for_each_entry(filter, &hisi_ptt->req_filters, list) {
535
+
ret = hisi_ptt_create_filter_attr(hisi_ptt, filter);
536
+
if (ret)
537
+
goto out;
538
+
}
539
+
540
+
hisi_ptt->sysfs_inited = true;
541
+
out:
542
+
mutex_unlock(&hisi_ptt->filter_lock);
543
+
return ret;
544
+
}
545
+
546
+
static void hisi_ptt_update_filters(struct work_struct *work)
547
+
{
548
+
struct delayed_work *delayed_work = to_delayed_work(work);
549
+
struct hisi_ptt_filter_update_info info;
550
+
struct hisi_ptt_filter_desc *filter;
551
+
struct hisi_ptt *hisi_ptt;
552
+
553
+
hisi_ptt = container_of(delayed_work, struct hisi_ptt, work);
554
+
555
+
if (!mutex_trylock(&hisi_ptt->filter_lock)) {
556
+
schedule_delayed_work(&hisi_ptt->work, HISI_PTT_WORK_DELAY_MS);
557
+
return;
558
+
}
559
+
560
+
while (kfifo_get(&hisi_ptt->filter_update_kfifo, &info)) {
561
+
if (info.is_add) {
562
+
/*
563
+
* Notify the users if failed to add this filter, others
564
+
* still work and available. See the comments in
565
+
* hisi_ptt_init_filters().
566
+
*/
567
+
filter = hisi_ptt_alloc_add_filter(hisi_ptt, info.devid, info.is_port);
568
+
if (!filter)
569
+
continue;
570
+
571
+
/*
572
+
* If filters' sysfs entries hasn't been initialized,
573
+
* then we're still at probe stage. Add the filters to
574
+
* the list and later hisi_ptt_init_filter_attributes()
575
+
* will create sysfs attributes for all the filters.
576
+
*/
577
+
if (hisi_ptt->sysfs_inited &&
578
+
hisi_ptt_create_filter_attr(hisi_ptt, filter)) {
579
+
hisi_ptt_del_free_filter(hisi_ptt, filter);
580
+
continue;
581
+
}
582
+
} else {
583
+
struct hisi_ptt_filter_desc *tmp;
584
+
struct list_head *target_list;
585
+
586
+
target_list = info.is_port ? &hisi_ptt->port_filters :
587
+
&hisi_ptt->req_filters;
588
+
589
+
list_for_each_entry_safe(filter, tmp, target_list, list)
590
+
if (filter->devid == info.devid) {
591
+
if (hisi_ptt->sysfs_inited)
592
+
hisi_ptt_remove_filter_attr(hisi_ptt, filter);
593
+
594
+
hisi_ptt_del_free_filter(hisi_ptt, filter);
595
+
break;
596
+
}
597
+
}
598
+
}
599
+
600
+
mutex_unlock(&hisi_ptt->filter_lock);
601
+
}
602
+
603
+
/*
604
+
* A PCI bus notifier is used here for dynamically updating the filter
605
+
* list.
606
+
*/
607
+
static int hisi_ptt_notifier_call(struct notifier_block *nb, unsigned long action,
608
+
void *data)
609
+
{
610
+
struct hisi_ptt *hisi_ptt = container_of(nb, struct hisi_ptt, hisi_ptt_nb);
611
+
struct hisi_ptt_filter_update_info info;
612
+
struct pci_dev *pdev, *root_port;
613
+
struct device *dev = data;
614
+
u32 port_devid;
615
+
616
+
pdev = to_pci_dev(dev);
617
+
root_port = pcie_find_root_port(pdev);
618
+
if (!root_port)
619
+
return 0;
620
+
621
+
port_devid = PCI_DEVID(root_port->bus->number, root_port->devfn);
622
+
if (port_devid < hisi_ptt->lower_bdf ||
623
+
port_devid > hisi_ptt->upper_bdf)
624
+
return 0;
625
+
626
+
info.is_port = pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT;
627
+
info.devid = PCI_DEVID(pdev->bus->number, pdev->devfn);
628
+
629
+
switch (action) {
630
+
case BUS_NOTIFY_ADD_DEVICE:
631
+
info.is_add = true;
632
+
break;
633
+
case BUS_NOTIFY_DEL_DEVICE:
634
+
info.is_add = false;
635
+
break;
636
+
default:
637
+
return 0;
638
+
}
639
+
640
+
/*
641
+
* The FIFO size is 16 which is sufficient for almost all the cases,
642
+
* since each PCIe core will have most 8 Root Ports (typically only
643
+
* 1~4 Root Ports). On failure log the failed filter and let user
644
+
* handle it.
645
+
*/
646
+
if (kfifo_in_spinlocked(&hisi_ptt->filter_update_kfifo, &info, 1,
647
+
&hisi_ptt->filter_update_lock))
648
+
schedule_delayed_work(&hisi_ptt->work, 0);
649
+
else
650
+
pci_warn(hisi_ptt->pdev,
651
+
"filter update fifo overflow for target %s\n",
652
+
pci_name(pdev));
353
653
354
654
return 0;
355
655
}
···
674
374
* should be partial initialized and users would know which filter fails
675
375
* through the log. Other functions of PTT device are still available.
676
376
*/
677
-
filter = kzalloc(sizeof(*filter), GFP_KERNEL);
678
-
if (!filter) {
679
-
pci_err(hisi_ptt->pdev, "failed to add filter %s\n", pci_name(pdev));
377
+
filter = hisi_ptt_alloc_add_filter(hisi_ptt, PCI_DEVID(pdev->bus->number, pdev->devfn),
378
+
pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT);
379
+
if (!filter)
680
380
return -ENOMEM;
681
-
}
682
-
683
-
filter->devid = PCI_DEVID(pdev->bus->number, pdev->devfn);
684
-
685
-
if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) {
686
-
filter->is_port = true;
687
-
list_add_tail(&filter->list, &hisi_ptt->port_filters);
688
-
689
-
/* Update the available port mask */
690
-
hisi_ptt->port_mask |= hisi_ptt_get_filter_val(filter->devid, true);
691
-
} else {
692
-
list_add_tail(&filter->list, &hisi_ptt->req_filters);
693
-
}
694
381
695
382
return 0;
696
383
}
···
687
400
struct hisi_ptt_filter_desc *filter, *tmp;
688
401
struct hisi_ptt *hisi_ptt = data;
689
402
690
-
list_for_each_entry_safe(filter, tmp, &hisi_ptt->req_filters, list) {
691
-
list_del(&filter->list);
692
-
kfree(filter);
693
-
}
403
+
list_for_each_entry_safe(filter, tmp, &hisi_ptt->req_filters, list)
404
+
hisi_ptt_del_free_filter(hisi_ptt, filter);
694
405
695
-
list_for_each_entry_safe(filter, tmp, &hisi_ptt->port_filters, list) {
696
-
list_del(&filter->list);
697
-
kfree(filter);
698
-
}
406
+
list_for_each_entry_safe(filter, tmp, &hisi_ptt->port_filters, list)
407
+
hisi_ptt_del_free_filter(hisi_ptt, filter);
699
408
}
700
409
701
410
static int hisi_ptt_config_trace_buf(struct hisi_ptt *hisi_ptt)
···
734
451
int ret;
735
452
u32 reg;
736
453
454
+
INIT_DELAYED_WORK(&hisi_ptt->work, hisi_ptt_update_filters);
455
+
INIT_KFIFO(hisi_ptt->filter_update_kfifo);
456
+
spin_lock_init(&hisi_ptt->filter_update_lock);
457
+
737
458
INIT_LIST_HEAD(&hisi_ptt->port_filters);
738
459
INIT_LIST_HEAD(&hisi_ptt->req_filters);
460
+
mutex_init(&hisi_ptt->filter_lock);
739
461
740
462
ret = hisi_ptt_config_trace_buf(hisi_ptt);
741
463
if (ret)
···
816
528
.attrs = hisi_ptt_pmu_format_attrs,
817
529
};
818
530
531
+
static ssize_t hisi_ptt_filter_multiselect_show(struct device *dev,
532
+
struct device_attribute *attr,
533
+
char *buf)
534
+
{
535
+
struct dev_ext_attribute *ext_attr;
536
+
537
+
ext_attr = container_of(attr, struct dev_ext_attribute, attr);
538
+
return sysfs_emit(buf, "%s\n", (char *)ext_attr->var);
539
+
}
540
+
541
+
static struct dev_ext_attribute root_port_filters_multiselect = {
542
+
.attr = {
543
+
.attr = { .name = "multiselect", .mode = 0400 },
544
+
.show = hisi_ptt_filter_multiselect_show,
545
+
},
546
+
.var = "1",
547
+
};
548
+
549
+
static struct attribute *hisi_ptt_pmu_root_ports_attrs[] = {
550
+
&root_port_filters_multiselect.attr.attr,
551
+
NULL
552
+
};
553
+
554
+
static struct attribute_group hisi_ptt_pmu_root_ports_group = {
555
+
.name = HISI_PTT_RP_FILTERS_GRP_NAME,
556
+
.attrs = hisi_ptt_pmu_root_ports_attrs,
557
+
};
558
+
559
+
static struct dev_ext_attribute requester_filters_multiselect = {
560
+
.attr = {
561
+
.attr = { .name = "multiselect", .mode = 0400 },
562
+
.show = hisi_ptt_filter_multiselect_show,
563
+
},
564
+
.var = "0",
565
+
};
566
+
567
+
static struct attribute *hisi_ptt_pmu_requesters_attrs[] = {
568
+
&requester_filters_multiselect.attr.attr,
569
+
NULL
570
+
};
571
+
572
+
static struct attribute_group hisi_ptt_pmu_requesters_group = {
573
+
.name = HISI_PTT_REQ_FILTERS_GRP_NAME,
574
+
.attrs = hisi_ptt_pmu_requesters_attrs,
575
+
};
576
+
819
577
static const struct attribute_group *hisi_ptt_pmu_groups[] = {
820
578
&hisi_ptt_cpumask_attr_group,
821
579
&hisi_ptt_pmu_format_group,
822
580
&hisi_ptt_tune_group,
581
+
&hisi_ptt_pmu_root_ports_group,
582
+
&hisi_ptt_pmu_requesters_group,
823
583
NULL
824
584
};
825
585
···
941
605
{
942
606
unsigned long val, port_mask = hisi_ptt->port_mask;
943
607
struct hisi_ptt_filter_desc *filter;
608
+
int ret = 0;
944
609
945
610
hisi_ptt->trace_ctrl.is_port = FIELD_GET(HISI_PTT_PMU_FILTER_IS_PORT, config);
946
611
val = FIELD_GET(HISI_PTT_PMU_FILTER_VAL_MASK, config);
···
955
618
* For Requester ID filters, walk the available filter list to see
956
619
* whether we have one matched.
957
620
*/
621
+
mutex_lock(&hisi_ptt->filter_lock);
958
622
if (!hisi_ptt->trace_ctrl.is_port) {
959
623
list_for_each_entry(filter, &hisi_ptt->req_filters, list) {
960
624
if (val == hisi_ptt_get_filter_val(filter->devid, filter->is_port))
961
-
return 0;
625
+
goto out;
962
626
}
963
627
} else if (bitmap_subset(&val, &port_mask, BITS_PER_LONG)) {
964
-
return 0;
628
+
goto out;
965
629
}
966
630
967
-
return -EINVAL;
631
+
ret = -EINVAL;
632
+
out:
633
+
mutex_unlock(&hisi_ptt->filter_lock);
634
+
return ret;
968
635
}
969
636
970
637
static void hisi_ptt_pmu_init_configs(struct hisi_ptt *hisi_ptt, struct perf_event *event)
···
1098
757
* core in event_function_local(). If CPU passed is offline we'll fail
1099
758
* here, just log it since we can do nothing here.
1100
759
*/
1101
-
ret = irq_set_affinity(pci_irq_vector(hisi_ptt->pdev, HISI_PTT_TRACE_DMA_IRQ),
1102
-
cpumask_of(cpu));
760
+
ret = irq_set_affinity(hisi_ptt->trace_irq, cpumask_of(cpu));
1103
761
if (ret)
1104
762
dev_warn(dev, "failed to set the affinity of trace interrupt\n");
1105
763
···
1211
871
1212
872
hisi_ptt->hisi_ptt_pmu = (struct pmu) {
1213
873
.module = THIS_MODULE,
1214
-
.capabilities = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE,
874
+
.capabilities = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_NO_EXCLUDE,
1215
875
.task_ctx_nr = perf_sw_context,
1216
876
.attr_groups = hisi_ptt_pmu_groups,
1217
877
.event_init = hisi_ptt_pmu_event_init,
···
1239
899
return devm_add_action_or_reset(&hisi_ptt->pdev->dev,
1240
900
hisi_ptt_unregister_pmu,
1241
901
&hisi_ptt->hisi_ptt_pmu);
902
+
}
903
+
904
+
static void hisi_ptt_unregister_filter_update_notifier(void *data)
905
+
{
906
+
struct hisi_ptt *hisi_ptt = data;
907
+
908
+
bus_unregister_notifier(&pci_bus_type, &hisi_ptt->hisi_ptt_nb);
909
+
910
+
/* Cancel any work that has been queued */
911
+
cancel_delayed_work_sync(&hisi_ptt->work);
912
+
}
913
+
914
+
/* Register the bus notifier for dynamically updating the filter list */
915
+
static int hisi_ptt_register_filter_update_notifier(struct hisi_ptt *hisi_ptt)
916
+
{
917
+
int ret;
918
+
919
+
hisi_ptt->hisi_ptt_nb.notifier_call = hisi_ptt_notifier_call;
920
+
ret = bus_register_notifier(&pci_bus_type, &hisi_ptt->hisi_ptt_nb);
921
+
if (ret)
922
+
return ret;
923
+
924
+
return devm_add_action_or_reset(&hisi_ptt->pdev->dev,
925
+
hisi_ptt_unregister_filter_update_notifier,
926
+
hisi_ptt);
1242
927
}
1243
928
1244
929
/*
···
1337
972
return ret;
1338
973
}
1339
974
975
+
ret = hisi_ptt_register_filter_update_notifier(hisi_ptt);
976
+
if (ret)
977
+
pci_warn(pdev, "failed to register filter update notifier, ret = %d", ret);
978
+
1340
979
ret = hisi_ptt_register_pmu(hisi_ptt);
1341
980
if (ret) {
1342
981
pci_err(pdev, "failed to register PMU device, ret = %d", ret);
982
+
return ret;
983
+
}
984
+
985
+
ret = hisi_ptt_init_filter_attributes(hisi_ptt);
986
+
if (ret) {
987
+
pci_err(pdev, "failed to init sysfs filter attributes, ret = %d", ret);
1343
988
return ret;
1344
989
}
1345
990
···
1393
1018
* Also make sure the interrupt bind to the migrated CPU as well. Warn
1394
1019
* the user on failure here.
1395
1020
*/
1396
-
if (irq_set_affinity(pci_irq_vector(hisi_ptt->pdev, HISI_PTT_TRACE_DMA_IRQ),
1397
-
cpumask_of(target)))
1021
+
if (irq_set_affinity(hisi_ptt->trace_irq, cpumask_of(target)))
1398
1022
dev_warn(dev, "failed to set the affinity of trace interrupt\n");
1399
1023
1400
1024
hisi_ptt->trace_ctrl.on_cpu = target;
+56
drivers/hwtracing/ptt/hisi_ptt.h
+56
drivers/hwtracing/ptt/hisi_ptt.h
···
11
11
12
12
#include <linux/bits.h>
13
13
#include <linux/cpumask.h>
14
+
#include <linux/device.h>
15
+
#include <linux/kfifo.h>
14
16
#include <linux/list.h>
15
17
#include <linux/mutex.h>
18
+
#include <linux/notifier.h>
16
19
#include <linux/pci.h>
17
20
#include <linux/perf_event.h>
18
21
#include <linux/spinlock.h>
19
22
#include <linux/types.h>
23
+
#include <linux/workqueue.h>
20
24
21
25
#define DRV_NAME "hisi_ptt"
22
26
···
74
70
#define HISI_PTT_WAIT_TUNE_TIMEOUT_US 1000000UL
75
71
#define HISI_PTT_WAIT_TRACE_TIMEOUT_US 100UL
76
72
#define HISI_PTT_WAIT_POLL_INTERVAL_US 10UL
73
+
74
+
/* FIFO size for dynamically updating the PTT trace filter list. */
75
+
#define HISI_PTT_FILTER_UPDATE_FIFO_SIZE 16
76
+
/* Delay time for filter updating work */
77
+
#define HISI_PTT_WORK_DELAY_MS 100UL
77
78
78
79
#define HISI_PCIE_CORE_PORT_ID(devfn) ((PCI_SLOT(devfn) & 0x7) << 1)
79
80
···
140
131
u32 type:4;
141
132
};
142
133
134
+
/*
135
+
* sysfs attribute group name for root port filters and requester filters:
136
+
* /sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters
137
+
* and
138
+
* /sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters
139
+
*/
140
+
#define HISI_PTT_RP_FILTERS_GRP_NAME "root_port_filters"
141
+
#define HISI_PTT_REQ_FILTERS_GRP_NAME "requester_filters"
142
+
143
143
/**
144
144
* struct hisi_ptt_filter_desc - Descriptor of the PTT trace filter
145
+
* @attr: sysfs attribute of this filter
145
146
* @list: entry of this descriptor in the filter list
146
147
* @is_port: the PCI device of the filter is a Root Port or not
148
+
* @name: name of this filter, same as the name of the related PCI device
147
149
* @devid: the PCI device's devid of the filter
148
150
*/
149
151
struct hisi_ptt_filter_desc {
152
+
struct device_attribute attr;
150
153
struct list_head list;
151
154
bool is_port;
155
+
char *name;
156
+
u16 devid;
157
+
};
158
+
159
+
/**
160
+
* struct hisi_ptt_filter_update_info - Information for PTT filter updating
161
+
* @is_port: the PCI device to update is a Root Port or not
162
+
* @is_add: adding to the filter or not
163
+
* @devid: the PCI device's devid of the filter
164
+
*/
165
+
struct hisi_ptt_filter_update_info {
166
+
bool is_port;
167
+
bool is_add;
152
168
u16 devid;
153
169
};
154
170
···
194
160
/**
195
161
* struct hisi_ptt - Per PTT device data
196
162
* @trace_ctrl: the control information of PTT trace
163
+
* @hisi_ptt_nb: dynamic filter update notifier
197
164
* @hotplug_node: node for register cpu hotplug event
198
165
* @hisi_ptt_pmu: the pum device of trace
199
166
* @iobase: base IO address of the device
200
167
* @pdev: pci_dev of this PTT device
201
168
* @tune_lock: lock to serialize the tune process
202
169
* @pmu_lock: lock to serialize the perf process
170
+
* @trace_irq: interrupt number used by trace
203
171
* @upper_bdf: the upper BDF range of the PCI devices managed by this PTT device
204
172
* @lower_bdf: the lower BDF range of the PCI devices managed by this PTT device
205
173
* @port_filters: the filter list of root ports
206
174
* @req_filters: the filter list of requester ID
175
+
* @filter_lock: lock to protect the filters
176
+
* @sysfs_inited: whether the filters' sysfs entries has been initialized
207
177
* @port_mask: port mask of the managed root ports
178
+
* @work: delayed work for filter updating
179
+
* @filter_update_lock: spinlock to protect the filter update fifo
180
+
* @filter_update_fifo: fifo of the filters waiting to update the filter list
208
181
*/
209
182
struct hisi_ptt {
210
183
struct hisi_ptt_trace_ctrl trace_ctrl;
184
+
struct notifier_block hisi_ptt_nb;
211
185
struct hlist_node hotplug_node;
212
186
struct pmu hisi_ptt_pmu;
213
187
void __iomem *iobase;
214
188
struct pci_dev *pdev;
215
189
struct mutex tune_lock;
216
190
spinlock_t pmu_lock;
191
+
int trace_irq;
217
192
u32 upper_bdf;
218
193
u32 lower_bdf;
219
194
···
235
192
*/
236
193
struct list_head port_filters;
237
194
struct list_head req_filters;
195
+
struct mutex filter_lock;
196
+
bool sysfs_inited;
238
197
u16 port_mask;
198
+
199
+
/*
200
+
* We use a delayed work here to avoid indefinitely waiting for
201
+
* the hisi_ptt->mutex which protecting the filter list. The
202
+
* work will be delayed only if the mutex can not be held,
203
+
* otherwise no delay will be applied.
204
+
*/
205
+
struct delayed_work work;
206
+
spinlock_t filter_update_lock;
207
+
DECLARE_KFIFO(filter_update_kfifo, struct hisi_ptt_filter_update_info,
208
+
HISI_PTT_FILTER_UPDATE_FIFO_SIZE);
239
209
};
240
210
241
211
#define to_hisi_ptt(pmu) container_of(pmu, struct hisi_ptt, hisi_ptt_pmu)
+1
-1
drivers/iio/accel/adxl313_i2c.c
+1
-1
drivers/iio/accel/adxl313_i2c.c
+1
-1
drivers/iio/accel/adxl345_i2c.c
+1
-1
drivers/iio/accel/adxl345_i2c.c
+1
-1
drivers/iio/accel/adxl355_i2c.c
+1
-1
drivers/iio/accel/adxl355_i2c.c
+1
-1
drivers/iio/accel/adxl367_i2c.c
+1
-1
drivers/iio/accel/adxl367_i2c.c
+1
-1
drivers/iio/accel/adxl372_i2c.c
+1
-1
drivers/iio/accel/adxl372_i2c.c
+1
-1
drivers/iio/accel/bma180.c
+1
-1
drivers/iio/accel/bma180.c
+1
-2
drivers/iio/accel/bma400_core.c
+1
-2
drivers/iio/accel/bma400_core.c
···
868
868
ARRAY_SIZE(regulator_names),
869
869
regulator_names);
870
870
if (ret)
871
-
return dev_err_probe(data->dev, ret, "Failed to get regulators: %d\n",
872
-
ret);
871
+
return dev_err_probe(data->dev, ret, "Failed to get regulators\n");
873
872
874
873
/* Try to read chip_id register. It must return 0x90. */
875
874
ret = regmap_read(data->regmap, BMA400_CHIP_ID_REG, &val);
+1
-1
drivers/iio/accel/bma400_i2c.c
+1
-1
drivers/iio/accel/bma400_i2c.c
+1
-1
drivers/iio/accel/bmc150-accel-i2c.c
+1
-1
drivers/iio/accel/bmc150-accel-i2c.c
+1
-1
drivers/iio/accel/da280.c
+1
-1
drivers/iio/accel/da280.c
+1
-1
drivers/iio/accel/da311.c
+1
-1
drivers/iio/accel/da311.c
+1
-1
drivers/iio/accel/dmard06.c
+1
-1
drivers/iio/accel/dmard06.c
+1
-1
drivers/iio/accel/dmard09.c
+1
-1
drivers/iio/accel/dmard09.c
+1
-1
drivers/iio/accel/dmard10.c
+1
-1
drivers/iio/accel/dmard10.c
+4
-4
drivers/iio/accel/fxls8962af-core.c
+4
-4
drivers/iio/accel/fxls8962af-core.c
···
724
724
.sign = 's', \
725
725
.realbits = 12, \
726
726
.storagebits = 16, \
727
-
.shift = 4, \
728
-
.endianness = IIO_BE, \
727
+
.endianness = IIO_LE, \
729
728
}, \
730
729
.event_spec = fxls8962af_event, \
731
730
.num_event_specs = ARRAY_SIZE(fxls8962af_event), \
···
903
904
int total_length = samples * sample_length;
904
905
int ret;
905
906
906
-
if (i2c_verify_client(dev))
907
+
if (i2c_verify_client(dev) &&
908
+
data->chip_info->chip_id == FXLS8962AF_DEVICE_ID)
907
909
/*
908
-
* Due to errata bug:
910
+
* Due to errata bug (only applicable on fxls8962af):
909
911
* E3: FIFO burst read operation error using I2C interface
910
912
* We have to avoid burst reads on I2C..
911
913
*/
+1
-1
drivers/iio/accel/fxls8962af-i2c.c
+1
-1
drivers/iio/accel/fxls8962af-i2c.c
+2
-1
drivers/iio/accel/kionix-kx022a-i2c.c
+2
-1
drivers/iio/accel/kionix-kx022a-i2c.c
+1
drivers/iio/accel/kionix-kx022a-spi.c
+1
drivers/iio/accel/kionix-kx022a-spi.c
+1
-12
drivers/iio/accel/kionix-kx022a.c
+1
-12
drivers/iio/accel/kionix-kx022a.c
···
516
516
return -EINVAL;
517
517
};
518
518
519
-
static int kx022a_validate_trigger(struct iio_dev *idev,
520
-
struct iio_trigger *trig)
521
-
{
522
-
struct kx022a_data *data = iio_priv(idev);
523
-
524
-
if (data->trig != trig)
525
-
return -EINVAL;
526
-
527
-
return 0;
528
-
}
529
-
530
519
static int kx022a_set_watermark(struct iio_dev *idev, unsigned int val)
531
520
{
532
521
struct kx022a_data *data = iio_priv(idev);
···
714
725
.write_raw = &kx022a_write_raw,
715
726
.read_avail = &kx022a_read_avail,
716
727
717
-
.validate_trigger = kx022a_validate_trigger,
728
+
.validate_trigger = iio_validate_own_trigger,
718
729
.hwfifo_set_watermark = kx022a_set_watermark,
719
730
.hwfifo_flush_to_buffer = kx022a_fifo_flush,
720
731
};
+1
-1
drivers/iio/accel/kxcjk-1013.c
+1
-1
drivers/iio/accel/kxcjk-1013.c
+1
-1
drivers/iio/accel/kxsd9-i2c.c
+1
-1
drivers/iio/accel/kxsd9-i2c.c
+1
-1
drivers/iio/accel/mc3230.c
+1
-1
drivers/iio/accel/mc3230.c
+1
-1
drivers/iio/accel/mma7455_i2c.c
+1
-1
drivers/iio/accel/mma7455_i2c.c
+1
-1
drivers/iio/accel/mma7660.c
+1
-1
drivers/iio/accel/mma7660.c
+1
-1
drivers/iio/accel/mma8452.c
+1
-1
drivers/iio/accel/mma8452.c
+1
-1
drivers/iio/accel/mma9551.c
+1
-1
drivers/iio/accel/mma9551.c
+1
-1
drivers/iio/accel/mma9553.c
+1
-1
drivers/iio/accel/mma9553.c
+1
-1
drivers/iio/accel/msa311.c
+1
-1
drivers/iio/accel/msa311.c
+1
-1
drivers/iio/accel/mxc4005.c
+1
-1
drivers/iio/accel/mxc4005.c
+1
-1
drivers/iio/accel/mxc6255.c
+1
-1
drivers/iio/accel/mxc6255.c
+1
drivers/iio/accel/st_accel_core.c
+1
drivers/iio/accel/st_accel_core.c
+1
-1
drivers/iio/accel/st_accel_i2c.c
+1
-1
drivers/iio/accel/st_accel_i2c.c
+1
-1
drivers/iio/accel/stk8312.c
+1
-1
drivers/iio/accel/stk8312.c
+1
-1
drivers/iio/accel/stk8ba50.c
+1
-1
drivers/iio/accel/stk8ba50.c
+1
-1
drivers/iio/adc/Kconfig
+1
-1
drivers/iio/adc/Kconfig
+1
-1
drivers/iio/adc/ad7091r5.c
+1
-1
drivers/iio/adc/ad7091r5.c
+4
-4
drivers/iio/adc/ad7192.c
+4
-4
drivers/iio/adc/ad7192.c
···
367
367
clock_sel = AD7192_CLK_INT;
368
368
369
369
/* use internal clock */
370
-
if (st->mclk) {
370
+
if (!st->mclk) {
371
371
if (of_property_read_bool(np, "adi,int-clock-output-enable"))
372
372
clock_sel = AD7192_CLK_INT_CO;
373
373
} else {
···
380
380
return clock_sel;
381
381
}
382
382
383
-
static int ad7192_setup(struct ad7192_state *st, struct device_node *np)
383
+
static int ad7192_setup(struct iio_dev *indio_dev, struct device_node *np)
384
384
{
385
-
struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
385
+
struct ad7192_state *st = iio_priv(indio_dev);
386
386
bool rej60_en, refin2_en;
387
387
bool buf_en, bipolar, burnout_curr_en;
388
388
unsigned long long scale_uv;
···
1069
1069
}
1070
1070
}
1071
1071
1072
-
ret = ad7192_setup(st, spi->dev.of_node);
1072
+
ret = ad7192_setup(indio_dev, spi->dev.of_node);
1073
1073
if (ret)
1074
1074
return ret;
1075
1075
+1
-1
drivers/iio/adc/ad7291.c
+1
-1
drivers/iio/adc/ad7291.c
+1
-1
drivers/iio/adc/ad799x.c
+1
-1
drivers/iio/adc/ad799x.c
+1
-1
drivers/iio/adc/ina2xx-adc.c
+1
-1
drivers/iio/adc/ina2xx-adc.c
+1
-1
drivers/iio/adc/ltc2471.c
+1
-1
drivers/iio/adc/ltc2471.c
+1
-1
drivers/iio/adc/ltc2485.c
+1
-1
drivers/iio/adc/ltc2485.c
+1
-1
drivers/iio/adc/ltc2497.c
+1
-1
drivers/iio/adc/ltc2497.c
+1
-1
drivers/iio/adc/max1363.c
+1
-1
drivers/iio/adc/max1363.c
+1
-1
drivers/iio/adc/max9611.c
+1
-1
drivers/iio/adc/max9611.c
+1
-1
drivers/iio/adc/mcp3422.c
+1
-1
drivers/iio/adc/mcp3422.c
+1
-1
drivers/iio/adc/meson_saradc.c
+1
-1
drivers/iio/adc/meson_saradc.c
···
72
72
#define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
73
73
#define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
74
74
#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
75
-
#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
75
+
#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6
76
76
#define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
77
77
#define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
78
78
+1
-1
drivers/iio/adc/nau7802.c
+1
-1
drivers/iio/adc/nau7802.c
-1
drivers/iio/adc/palmas_gpadc.c
-1
drivers/iio/adc/palmas_gpadc.c
+7
-8
drivers/iio/adc/qcom-spmi-adc5.c
+7
-8
drivers/iio/adc/qcom-spmi-adc5.c
···
114
114
* that is an average of multiple measurements.
115
115
* @scale_fn_type: Represents the scaling function to convert voltage
116
116
* physical units desired by the client for the channel.
117
-
* @datasheet_name: Channel name used in device tree.
117
+
* @channel_name: Channel name used in device tree.
118
118
*/
119
119
struct adc5_channel_prop {
120
120
unsigned int channel;
···
126
126
unsigned int hw_settle_time;
127
127
unsigned int avg_samples;
128
128
enum vadc_scale_fn_type scale_fn_type;
129
-
const char *datasheet_name;
129
+
const char *channel_name;
130
130
};
131
131
132
132
/**
···
657
657
chan = chan & ADC_CHANNEL_MASK;
658
658
}
659
659
660
-
if (chan > ADC5_PARALLEL_ISENSE_VBAT_IDATA ||
661
-
!data->adc_chans[chan].datasheet_name) {
660
+
if (chan > ADC5_PARALLEL_ISENSE_VBAT_IDATA) {
662
661
dev_err(dev, "%s invalid channel number %d\n", name, chan);
663
662
return -EINVAL;
664
663
}
···
668
669
669
670
ret = fwnode_property_read_string(fwnode, "label", &channel_name);
670
671
if (ret)
671
-
channel_name = name;
672
+
channel_name = data->adc_chans[chan].datasheet_name;
672
673
673
-
prop->datasheet_name = channel_name;
674
+
prop->channel_name = channel_name;
674
675
675
676
ret = fwnode_property_read_u32(fwnode, "qcom,decimation", &value);
676
677
if (!ret) {
···
860
861
adc_chan = &adc->data->adc_chans[prop.channel];
861
862
862
863
iio_chan->channel = prop.channel;
863
-
iio_chan->datasheet_name = prop.datasheet_name;
864
-
iio_chan->extend_name = prop.datasheet_name;
864
+
iio_chan->datasheet_name = adc_chan->datasheet_name;
865
+
iio_chan->extend_name = prop.channel_name;
865
866
iio_chan->info_mask_separate = adc_chan->info_mask;
866
867
iio_chan->type = adc_chan->type;
867
868
iio_chan->address = index;
+18
-1
drivers/iio/adc/qcom-spmi-vadc.c
+18
-1
drivers/iio/adc/qcom-spmi-vadc.c
···
84
84
* that is an average of multiple measurements.
85
85
* @scale_fn_type: Represents the scaling function to convert voltage
86
86
* physical units desired by the client for the channel.
87
+
* @channel_name: Channel name used in device tree.
87
88
*/
88
89
struct vadc_channel_prop {
89
90
unsigned int channel;
···
94
93
unsigned int hw_settle_time;
95
94
unsigned int avg_samples;
96
95
enum vadc_scale_fn_type scale_fn_type;
96
+
const char *channel_name;
97
97
};
98
98
99
99
/**
···
497
495
return -EINVAL;
498
496
}
499
497
498
+
static int vadc_read_label(struct iio_dev *indio_dev,
499
+
struct iio_chan_spec const *chan, char *label)
500
+
{
501
+
struct vadc_priv *vadc = iio_priv(indio_dev);
502
+
const char *name = vadc->chan_props[chan->address].channel_name;
503
+
504
+
return sysfs_emit(label, "%s\n", name);
505
+
}
506
+
500
507
static const struct iio_info vadc_info = {
501
508
.read_raw = vadc_read_raw,
509
+
.read_label = vadc_read_label,
502
510
.fwnode_xlate = vadc_fwnode_xlate,
503
511
};
504
512
···
664
652
struct vadc_channel_prop *prop,
665
653
struct fwnode_handle *fwnode)
666
654
{
667
-
const char *name = fwnode_get_name(fwnode);
655
+
const char *name = fwnode_get_name(fwnode), *label;
668
656
u32 chan, value, varr[2];
669
657
int ret;
670
658
···
678
666
dev_err(dev, "%s invalid channel number %d\n", name, chan);
679
667
return -EINVAL;
680
668
}
669
+
670
+
ret = fwnode_property_read_string(fwnode, "label", &label);
671
+
if (ret)
672
+
label = vadc_chans[chan].datasheet_name;
673
+
prop->channel_name = label;
681
674
682
675
/* the channel has DT description */
683
676
prop->channel = chan;
+155
-91
drivers/iio/adc/rockchip_saradc.c
+155
-91
drivers/iio/adc/rockchip_saradc.c
···
4
4
* Copyright (C) 2014 ROCKCHIP, Inc.
5
5
*/
6
6
7
+
#include <linux/bitfield.h>
7
8
#include <linux/module.h>
8
9
#include <linux/mutex.h>
9
10
#include <linux/platform_device.h>
···
39
38
#define SARADC_TIMEOUT msecs_to_jiffies(100)
40
39
#define SARADC_MAX_CHANNELS 8
41
40
41
+
/* v2 registers */
42
+
#define SARADC2_CONV_CON 0x000
43
+
#define SARADC_T_PD_SOC 0x004
44
+
#define SARADC_T_DAS_SOC 0x00c
45
+
#define SARADC2_END_INT_EN 0x104
46
+
#define SARADC2_ST_CON 0x108
47
+
#define SARADC2_STATUS 0x10c
48
+
#define SARADC2_END_INT_ST 0x110
49
+
#define SARADC2_DATA_BASE 0x120
50
+
51
+
#define SARADC2_EN_END_INT BIT(0)
52
+
#define SARADC2_START BIT(4)
53
+
#define SARADC2_SINGLE_MODE BIT(5)
54
+
55
+
#define SARADC2_CONV_CHANNELS GENMASK(15, 0)
56
+
57
+
struct rockchip_saradc;
58
+
42
59
struct rockchip_saradc_data {
43
60
const struct iio_chan_spec *channels;
44
61
int num_channels;
45
62
unsigned long clk_rate;
63
+
void (*start)(struct rockchip_saradc *info, int chn);
64
+
int (*read)(struct rockchip_saradc *info);
65
+
void (*power_down)(struct rockchip_saradc *info);
46
66
};
47
67
48
68
struct rockchip_saradc {
···
82
60
struct notifier_block nb;
83
61
};
84
62
85
-
static void rockchip_saradc_power_down(struct rockchip_saradc *info)
63
+
static void rockchip_saradc_reset_controller(struct reset_control *reset);
64
+
65
+
static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn)
86
66
{
87
-
/* Clear irq & power down adc */
67
+
/* 8 clock periods as delay between power up and start cmd */
68
+
writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
69
+
/* Select the channel to be used and trigger conversion */
70
+
writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) |
71
+
SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
72
+
}
73
+
74
+
static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
75
+
{
76
+
int val;
77
+
78
+
if (info->reset)
79
+
rockchip_saradc_reset_controller(info->reset);
80
+
81
+
writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
82
+
writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
83
+
val = FIELD_PREP(SARADC2_EN_END_INT, 1);
84
+
val |= val << 16;
85
+
writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
86
+
val = FIELD_PREP(SARADC2_START, 1) |
87
+
FIELD_PREP(SARADC2_SINGLE_MODE, 1) |
88
+
FIELD_PREP(SARADC2_CONV_CHANNELS, chn);
89
+
val |= val << 16;
90
+
writel(val, info->regs + SARADC2_CONV_CON);
91
+
}
92
+
93
+
static void rockchip_saradc_start(struct rockchip_saradc *info, int chn)
94
+
{
95
+
info->data->start(info, chn);
96
+
}
97
+
98
+
static int rockchip_saradc_read_v1(struct rockchip_saradc *info)
99
+
{
100
+
return readl_relaxed(info->regs + SARADC_DATA);
101
+
}
102
+
103
+
static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
104
+
{
105
+
int offset;
106
+
107
+
/* Clear irq */
108
+
writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
109
+
110
+
offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4;
111
+
112
+
return readl_relaxed(info->regs + offset);
113
+
}
114
+
115
+
static int rockchip_saradc_read(struct rockchip_saradc *info)
116
+
{
117
+
return info->data->read(info);
118
+
}
119
+
120
+
static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info)
121
+
{
88
122
writel_relaxed(0, info->regs + SARADC_CTRL);
89
123
}
90
124
125
+
static void rockchip_saradc_power_down(struct rockchip_saradc *info)
126
+
{
127
+
if (info->data->power_down)
128
+
info->data->power_down(info);
129
+
}
130
+
91
131
static int rockchip_saradc_conversion(struct rockchip_saradc *info,
92
-
struct iio_chan_spec const *chan)
132
+
struct iio_chan_spec const *chan)
93
133
{
94
134
reinit_completion(&info->completion);
95
135
96
-
/* 8 clock periods as delay between power up and start cmd */
97
-
writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
98
-
99
136
info->last_chan = chan;
100
-
101
-
/* Select the channel to be used and trigger conversion */
102
-
writel(SARADC_CTRL_POWER_CTRL
103
-
| (chan->channel & SARADC_CTRL_CHN_MASK)
104
-
| SARADC_CTRL_IRQ_ENABLE,
105
-
info->regs + SARADC_CTRL);
137
+
rockchip_saradc_start(info, chan->channel);
106
138
107
139
if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
108
140
return -ETIMEDOUT;
···
199
123
struct rockchip_saradc *info = dev_id;
200
124
201
125
/* Read value */
202
-
info->last_val = readl_relaxed(info->regs + SARADC_DATA);
126
+
info->last_val = rockchip_saradc_read(info);
203
127
info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
204
128
205
129
rockchip_saradc_power_down(info);
···
239
163
.channels = rockchip_saradc_iio_channels,
240
164
.num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
241
165
.clk_rate = 1000000,
166
+
.start = rockchip_saradc_start_v1,
167
+
.read = rockchip_saradc_read_v1,
168
+
.power_down = rockchip_saradc_power_down_v1,
242
169
};
243
170
244
171
static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
···
253
174
.channels = rockchip_rk3066_tsadc_iio_channels,
254
175
.num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
255
176
.clk_rate = 50000,
177
+
.start = rockchip_saradc_start_v1,
178
+
.read = rockchip_saradc_read_v1,
179
+
.power_down = rockchip_saradc_power_down_v1,
256
180
};
257
181
258
182
static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
···
271
189
.channels = rockchip_rk3399_saradc_iio_channels,
272
190
.num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
273
191
.clk_rate = 1000000,
192
+
.start = rockchip_saradc_start_v1,
193
+
.read = rockchip_saradc_read_v1,
194
+
.power_down = rockchip_saradc_power_down_v1,
274
195
};
275
196
276
197
static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
···
291
206
.channels = rockchip_rk3568_saradc_iio_channels,
292
207
.num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
293
208
.clk_rate = 1000000,
209
+
.start = rockchip_saradc_start_v1,
210
+
.read = rockchip_saradc_read_v1,
211
+
.power_down = rockchip_saradc_power_down_v1,
212
+
};
213
+
214
+
static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
215
+
SARADC_CHANNEL(0, "adc0", 12),
216
+
SARADC_CHANNEL(1, "adc1", 12),
217
+
SARADC_CHANNEL(2, "adc2", 12),
218
+
SARADC_CHANNEL(3, "adc3", 12),
219
+
SARADC_CHANNEL(4, "adc4", 12),
220
+
SARADC_CHANNEL(5, "adc5", 12),
221
+
SARADC_CHANNEL(6, "adc6", 12),
222
+
SARADC_CHANNEL(7, "adc7", 12),
223
+
};
224
+
225
+
static const struct rockchip_saradc_data rk3588_saradc_data = {
226
+
.channels = rockchip_rk3588_saradc_iio_channels,
227
+
.num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
228
+
.clk_rate = 1000000,
229
+
.start = rockchip_saradc_start_v2,
230
+
.read = rockchip_saradc_read_v2,
294
231
};
295
232
296
233
static const struct of_device_id rockchip_saradc_match[] = {
···
328
221
}, {
329
222
.compatible = "rockchip,rk3568-saradc",
330
223
.data = &rk3568_saradc_data,
224
+
}, {
225
+
.compatible = "rockchip,rk3588-saradc",
226
+
.data = &rk3588_saradc_data,
331
227
},
332
228
{},
333
229
};
···
344
234
reset_control_assert(reset);
345
235
usleep_range(10, 20);
346
236
reset_control_deassert(reset);
347
-
}
348
-
349
-
static void rockchip_saradc_clk_disable(void *data)
350
-
{
351
-
struct rockchip_saradc *info = data;
352
-
353
-
clk_disable_unprepare(info->clk);
354
-
}
355
-
356
-
static void rockchip_saradc_pclk_disable(void *data)
357
-
{
358
-
struct rockchip_saradc *info = data;
359
-
360
-
clk_disable_unprepare(info->pclk);
361
237
}
362
238
363
239
static void rockchip_saradc_regulator_disable(void *data)
···
394
298
}
395
299
396
300
static int rockchip_saradc_volt_notify(struct notifier_block *nb,
397
-
unsigned long event,
398
-
void *data)
301
+
unsigned long event, void *data)
399
302
{
400
303
struct rockchip_saradc *info =
401
304
container_of(nb, struct rockchip_saradc, nb);
···
414
319
415
320
static int rockchip_saradc_probe(struct platform_device *pdev)
416
321
{
322
+
const struct rockchip_saradc_data *match_data;
417
323
struct rockchip_saradc *info = NULL;
418
324
struct device_node *np = pdev->dev.of_node;
419
325
struct iio_dev *indio_dev = NULL;
420
-
const struct of_device_id *match;
421
326
int ret;
422
327
int irq;
423
328
···
425
330
return -ENODEV;
426
331
427
332
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
428
-
if (!indio_dev) {
429
-
dev_err(&pdev->dev, "failed allocating iio device\n");
430
-
return -ENOMEM;
431
-
}
333
+
if (!indio_dev)
334
+
return dev_err_probe(&pdev->dev, -ENOMEM,
335
+
"failed allocating iio device\n");
336
+
432
337
info = iio_priv(indio_dev);
433
338
434
-
match = of_match_device(rockchip_saradc_match, &pdev->dev);
435
-
if (!match) {
436
-
dev_err(&pdev->dev, "failed to match device\n");
437
-
return -ENODEV;
438
-
}
339
+
match_data = of_device_get_match_data(&pdev->dev);
340
+
if (!match_data)
341
+
return dev_err_probe(&pdev->dev, -ENODEV,
342
+
"failed to match device\n");
439
343
440
-
info->data = match->data;
344
+
info->data = match_data;
441
345
442
346
/* Sanity check for possible later IP variants with more channels */
443
-
if (info->data->num_channels > SARADC_MAX_CHANNELS) {
444
-
dev_err(&pdev->dev, "max channels exceeded");
445
-
return -EINVAL;
446
-
}
347
+
if (info->data->num_channels > SARADC_MAX_CHANNELS)
348
+
return dev_err_probe(&pdev->dev, -EINVAL,
349
+
"max channels exceeded");
447
350
448
351
info->regs = devm_platform_ioremap_resource(pdev, 0);
449
352
if (IS_ERR(info->regs))
···
476
383
return ret;
477
384
}
478
385
479
-
info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
480
-
if (IS_ERR(info->pclk))
481
-
return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
482
-
"failed to get pclk\n");
483
-
484
-
info->clk = devm_clk_get(&pdev->dev, "saradc");
485
-
if (IS_ERR(info->clk))
486
-
return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
487
-
"failed to get adc clock\n");
488
-
489
386
info->vref = devm_regulator_get(&pdev->dev, "vref");
490
387
if (IS_ERR(info->vref))
491
388
return dev_err_probe(&pdev->dev, PTR_ERR(info->vref),
···
489
406
* This may become user-configurable in the future.
490
407
*/
491
408
ret = clk_set_rate(info->clk, info->data->clk_rate);
492
-
if (ret < 0) {
493
-
dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
494
-
return ret;
495
-
}
409
+
if (ret < 0)
410
+
return dev_err_probe(&pdev->dev, ret,
411
+
"failed to set adc clk rate\n");
496
412
497
413
ret = regulator_enable(info->vref);
498
-
if (ret < 0) {
499
-
dev_err(&pdev->dev, "failed to enable vref regulator\n");
500
-
return ret;
501
-
}
414
+
if (ret < 0)
415
+
return dev_err_probe(&pdev->dev, ret,
416
+
"failed to enable vref regulator\n");
417
+
502
418
ret = devm_add_action_or_reset(&pdev->dev,
503
419
rockchip_saradc_regulator_disable, info);
504
-
if (ret) {
505
-
dev_err(&pdev->dev, "failed to register devm action, %d\n",
506
-
ret);
507
-
return ret;
508
-
}
420
+
if (ret)
421
+
return dev_err_probe(&pdev->dev, ret,
422
+
"failed to register devm action\n");
509
423
510
424
ret = regulator_get_voltage(info->vref);
511
425
if (ret < 0)
···
510
430
511
431
info->uv_vref = ret;
512
432
513
-
ret = clk_prepare_enable(info->pclk);
514
-
if (ret < 0) {
515
-
dev_err(&pdev->dev, "failed to enable pclk\n");
516
-
return ret;
517
-
}
518
-
ret = devm_add_action_or_reset(&pdev->dev,
519
-
rockchip_saradc_pclk_disable, info);
520
-
if (ret) {
521
-
dev_err(&pdev->dev, "failed to register devm action, %d\n",
522
-
ret);
523
-
return ret;
524
-
}
433
+
info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
434
+
if (IS_ERR(info->pclk))
435
+
return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
436
+
"failed to get pclk\n");
525
437
526
-
ret = clk_prepare_enable(info->clk);
527
-
if (ret < 0) {
528
-
dev_err(&pdev->dev, "failed to enable converter clock\n");
529
-
return ret;
530
-
}
531
-
ret = devm_add_action_or_reset(&pdev->dev,
532
-
rockchip_saradc_clk_disable, info);
533
-
if (ret) {
534
-
dev_err(&pdev->dev, "failed to register devm action, %d\n",
535
-
ret);
536
-
return ret;
537
-
}
438
+
info->clk = devm_clk_get_enabled(&pdev->dev, "saradc");
439
+
if (IS_ERR(info->clk))
440
+
return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
441
+
"failed to get adc clock\n");
538
442
539
443
platform_set_drvdata(pdev, indio_dev);
540
444
+1
-1
drivers/iio/adc/rtq6056.c
+1
-1
drivers/iio/adc/rtq6056.c
+2
drivers/iio/adc/stm32-adc.c
+2
drivers/iio/adc/stm32-adc.c
···
1993
1993
const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1994
1994
int num_channels = 0, ret;
1995
1995
1996
+
dev_dbg(&indio_dev->dev, "using legacy channel config\n");
1997
+
1996
1998
ret = device_property_count_u32(dev, "st,adc-channels");
1997
1999
if (ret > adc_info->max_channels) {
1998
2000
dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
+1
-1
drivers/iio/adc/ti-adc081c.c
+1
-1
drivers/iio/adc/ti-adc081c.c
+1
-1
drivers/iio/adc/ti-ads1015.c
+1
-1
drivers/iio/adc/ti-ads1015.c
+1
-1
drivers/iio/adc/ti-ads1100.c
+1
-1
drivers/iio/adc/ti-ads1100.c
+1
-1
drivers/iio/adc/ti-ads7924.c
+1
-1
drivers/iio/adc/ti-ads7924.c
+6
-5
drivers/iio/addac/ad74413r.c
+6
-5
drivers/iio/addac/ad74413r.c
···
1317
1317
}
1318
1318
1319
1319
if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1320
-
config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER)
1320
+
config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) {
1321
1321
st->comp_gpio_offsets[comp_gpio_i++] = i;
1322
1322
1323
-
strength = config->drive_strength;
1324
-
ret = ad74413r_set_comp_drive_strength(st, i, strength);
1325
-
if (ret)
1326
-
return ret;
1323
+
strength = config->drive_strength;
1324
+
ret = ad74413r_set_comp_drive_strength(st, i, strength);
1325
+
if (ret)
1326
+
return ret;
1327
+
}
1327
1328
1328
1329
ret = ad74413r_set_gpo_config(st, i, gpo_config);
1329
1330
if (ret)
+1
-1
drivers/iio/amplifiers/ad8366.c
+1
-1
drivers/iio/amplifiers/ad8366.c
+1
-1
drivers/iio/cdc/ad7150.c
+1
-1
drivers/iio/cdc/ad7150.c
+1
-1
drivers/iio/cdc/ad7746.c
+1
-1
drivers/iio/cdc/ad7746.c
+1
-1
drivers/iio/chemical/ams-iaq-core.c
+1
-1
drivers/iio/chemical/ams-iaq-core.c
+1
-1
drivers/iio/chemical/atlas-ezo-sensor.c
+1
-1
drivers/iio/chemical/atlas-ezo-sensor.c
+1
-1
drivers/iio/chemical/atlas-sensor.c
+1
-1
drivers/iio/chemical/atlas-sensor.c
+1
-1
drivers/iio/chemical/bme680_i2c.c
+1
-1
drivers/iio/chemical/bme680_i2c.c
+1
-1
drivers/iio/chemical/ccs811.c
+1
-1
drivers/iio/chemical/ccs811.c
+1
-1
drivers/iio/chemical/scd30_i2c.c
+1
-1
drivers/iio/chemical/scd30_i2c.c
+1
-1
drivers/iio/chemical/scd4x.c
+1
-1
drivers/iio/chemical/scd4x.c
+1
-1
drivers/iio/chemical/sgp30.c
+1
-1
drivers/iio/chemical/sgp30.c
+1
-1
drivers/iio/chemical/sgp40.c
+1
-1
drivers/iio/chemical/sgp40.c
+1
-1
drivers/iio/chemical/sps30_i2c.c
+1
-1
drivers/iio/chemical/sps30_i2c.c
+1
-1
drivers/iio/chemical/sunrise_co2.c
+1
-1
drivers/iio/chemical/sunrise_co2.c
+1
-1
drivers/iio/chemical/vz89x.c
+1
-1
drivers/iio/chemical/vz89x.c
+1
-1
drivers/iio/dac/ad5064.c
+1
-1
drivers/iio/dac/ad5064.c
+1
-1
drivers/iio/dac/ad5380.c
+1
-1
drivers/iio/dac/ad5380.c
+1
-1
drivers/iio/dac/ad5446.c
+1
-1
drivers/iio/dac/ad5446.c
+1
-1
drivers/iio/dac/ad5593r.c
+1
-1
drivers/iio/dac/ad5593r.c
+1
-1
drivers/iio/dac/ad5696-i2c.c
+1
-1
drivers/iio/dac/ad5696-i2c.c
+1
-1
drivers/iio/dac/ds4424.c
+1
-1
drivers/iio/dac/ds4424.c
+1
-1
drivers/iio/dac/m62332.c
+1
-1
drivers/iio/dac/m62332.c
+1
-1
drivers/iio/dac/max517.c
+1
-1
drivers/iio/dac/max517.c
+1
-1
drivers/iio/dac/max5821.c
+1
-1
drivers/iio/dac/max5821.c
+1
-1
drivers/iio/dac/mcp4725.c
+1
-1
drivers/iio/dac/mcp4725.c
+1
-1
drivers/iio/dac/ti-dac5571.c
+1
-1
drivers/iio/dac/ti-dac5571.c
+1
-1
drivers/iio/gyro/bmg160_i2c.c
+1
-1
drivers/iio/gyro/bmg160_i2c.c
+1
-1
drivers/iio/gyro/fxas21002c_i2c.c
+1
-1
drivers/iio/gyro/fxas21002c_i2c.c
+1
-1
drivers/iio/gyro/itg3200_core.c
+1
-1
drivers/iio/gyro/itg3200_core.c
+1
-1
drivers/iio/gyro/mpu3050-i2c.c
+1
-1
drivers/iio/gyro/mpu3050-i2c.c
+1
-1
drivers/iio/gyro/st_gyro_i2c.c
+1
-1
drivers/iio/gyro/st_gyro_i2c.c
+1
-1
drivers/iio/health/afe4404.c
+1
-1
drivers/iio/health/afe4404.c
+1
-1
drivers/iio/health/max30100.c
+1
-1
drivers/iio/health/max30100.c
+1
-1
drivers/iio/health/max30102.c
+1
-1
drivers/iio/health/max30102.c
+1
-1
drivers/iio/humidity/am2315.c
+1
-1
drivers/iio/humidity/am2315.c
+1
-1
drivers/iio/humidity/hdc100x.c
+1
-1
drivers/iio/humidity/hdc100x.c
+1
-1
drivers/iio/humidity/hdc2010.c
+1
-1
drivers/iio/humidity/hdc2010.c
+1
-1
drivers/iio/humidity/hts221_i2c.c
+1
-1
drivers/iio/humidity/hts221_i2c.c
+1
-1
drivers/iio/humidity/htu21.c
+1
-1
drivers/iio/humidity/htu21.c
+1
-1
drivers/iio/humidity/si7005.c
+1
-1
drivers/iio/humidity/si7005.c
+1
-1
drivers/iio/humidity/si7020.c
+1
-1
drivers/iio/humidity/si7020.c
+1
-1
drivers/iio/imu/bmi160/bmi160_i2c.c
+1
-1
drivers/iio/imu/bmi160/bmi160_i2c.c
+1
-1
drivers/iio/imu/bno055/bno055_i2c.c
+1
-1
drivers/iio/imu/bno055/bno055_i2c.c
+1
-1
drivers/iio/imu/fxos8700_i2c.c
+1
-1
drivers/iio/imu/fxos8700_i2c.c
+1
-1
drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c
+1
-1
drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c
+26
-23
drivers/iio/imu/inv_icm42600/inv_icm42600_timestamp.c
+26
-23
drivers/iio/imu/inv_icm42600/inv_icm42600_timestamp.c
···
93
93
return false;
94
94
}
95
95
96
-
static bool inv_compute_chip_period(struct inv_icm42600_timestamp *ts,
97
-
uint32_t mult, uint32_t period)
96
+
static bool inv_update_chip_period(struct inv_icm42600_timestamp *ts,
97
+
uint32_t mult, uint32_t period)
98
98
{
99
99
uint32_t new_chip_period;
100
100
···
104
104
/* update chip internal period estimation */
105
105
new_chip_period = period / mult;
106
106
inv_update_acc(&ts->chip_period, new_chip_period);
107
+
ts->period = ts->mult * ts->chip_period.val;
107
108
108
109
return true;
110
+
}
111
+
112
+
static void inv_align_timestamp_it(struct inv_icm42600_timestamp *ts)
113
+
{
114
+
int64_t delta, jitter;
115
+
int64_t adjust;
116
+
117
+
/* delta time between last sample and last interrupt */
118
+
delta = ts->it.lo - ts->timestamp;
119
+
120
+
/* adjust timestamp while respecting jitter */
121
+
jitter = div_s64((int64_t)ts->period * INV_ICM42600_TIMESTAMP_JITTER, 100);
122
+
if (delta > jitter)
123
+
adjust = jitter;
124
+
else if (delta < -jitter)
125
+
adjust = -jitter;
126
+
else
127
+
adjust = 0;
128
+
129
+
ts->timestamp += adjust;
109
130
}
110
131
111
132
void inv_icm42600_timestamp_interrupt(struct inv_icm42600_timestamp *ts,
···
137
116
int64_t delta, interval;
138
117
const uint32_t fifo_mult = fifo_period / INV_ICM42600_TIMESTAMP_PERIOD;
139
118
uint32_t period = ts->period;
140
-
int32_t m;
141
119
bool valid = false;
142
120
143
121
if (fifo_nb == 0)
···
150
130
if (it->lo != 0) {
151
131
/* compute period: delta time divided by number of samples */
152
132
period = div_s64(delta, fifo_nb);
153
-
valid = inv_compute_chip_period(ts, fifo_mult, period);
154
-
/* update sensor period if chip internal period is updated */
155
-
if (valid)
156
-
ts->period = ts->mult * ts->chip_period.val;
133
+
valid = inv_update_chip_period(ts, fifo_mult, period);
157
134
}
158
135
159
136
/* no previous data, compute theoritical value from interrupt */
···
162
145
}
163
146
164
147
/* if interrupt interval is valid, sync with interrupt timestamp */
165
-
if (valid) {
166
-
/* compute measured fifo_period */
167
-
fifo_period = fifo_mult * ts->chip_period.val;
168
-
/* delta time between last sample and last interrupt */
169
-
delta = it->lo - ts->timestamp;
170
-
/* if there are multiple samples, go back to first one */
171
-
while (delta >= (fifo_period * 3 / 2))
172
-
delta -= fifo_period;
173
-
/* compute maximal adjustment value */
174
-
m = INV_ICM42600_TIMESTAMP_MAX_PERIOD(ts->period) - ts->period;
175
-
if (delta > m)
176
-
delta = m;
177
-
else if (delta < -m)
178
-
delta = -m;
179
-
ts->timestamp += delta;
180
-
}
148
+
if (valid)
149
+
inv_align_timestamp_it(ts);
181
150
}
182
151
183
152
void inv_icm42600_timestamp_apply_odr(struct inv_icm42600_timestamp *ts,
+2
-2
drivers/iio/imu/inv_mpu6050/Kconfig
+2
-2
drivers/iio/imu/inv_mpu6050/Kconfig
···
16
16
select REGMAP_I2C
17
17
help
18
18
This driver supports the Invensense MPU6050/9150,
19
-
MPU6500/6515/6880/9250/9255, ICM20608(D)/20609/20689, ICM20602/ICM20690
19
+
MPU6500/6515/6880/9250/9255, ICM20608(D)/20609/20689, ICM20600/20602/20690
20
20
and IAM20680 motion tracking devices over I2C.
21
21
This driver can be built as a module. The module will be called
22
22
inv-mpu6050-i2c.
···
28
28
select REGMAP_SPI
29
29
help
30
30
This driver supports the Invensense MPU6000,
31
-
MPU6500/6515/6880/9250/9255, ICM20608(D)/20609/20689, ICM20602/ICM20690
31
+
MPU6500/6515/6880/9250/9255, ICM20608(D)/20609/20689, ICM20600/20602/20690
32
32
and IAM20680 motion tracking devices over SPI.
33
33
This driver can be built as a module. The module will be called
34
34
inv-mpu6050-spi.
+10
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
+10
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
···
245
245
.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
246
246
},
247
247
{
248
+
.whoami = INV_ICM20600_WHOAMI_VALUE,
249
+
.name = "ICM20600",
250
+
.reg = ®_set_icm20602,
251
+
.config = &chip_config_6500,
252
+
.fifo_size = 1008,
253
+
.temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
254
+
.startup_time = {INV_ICM20602_GYRO_STARTUP_TIME, INV_ICM20602_ACCEL_STARTUP_TIME},
255
+
},
256
+
{
248
257
.whoami = INV_ICM20602_WHOAMI_VALUE,
249
258
.name = "ICM20602",
250
259
.reg = ®_set_icm20602,
···
1606
1597
indio_dev->num_channels = ARRAY_SIZE(inv_mpu9250_channels);
1607
1598
indio_dev->available_scan_masks = inv_mpu9x50_scan_masks;
1608
1599
break;
1600
+
case INV_ICM20600:
1609
1601
case INV_ICM20602:
1610
1602
indio_dev->channels = inv_mpu_channels;
1611
1603
indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
+7
-1
drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c
+7
-1
drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c
···
32
32
case INV_ICM20608D:
33
33
case INV_ICM20609:
34
34
case INV_ICM20689:
35
+
case INV_ICM20600:
35
36
case INV_ICM20602:
36
37
case INV_IAM20680:
37
38
/* no i2c auxiliary bus on the chip */
···
184
183
{"icm20608d", INV_ICM20608D},
185
184
{"icm20609", INV_ICM20609},
186
185
{"icm20689", INV_ICM20689},
186
+
{"icm20600", INV_ICM20600},
187
187
{"icm20602", INV_ICM20602},
188
188
{"icm20690", INV_ICM20690},
189
189
{"iam20680", INV_IAM20680},
···
239
237
.data = (void *)INV_ICM20689
240
238
},
241
239
{
240
+
.compatible = "invensense,icm20600",
241
+
.data = (void *)INV_ICM20600
242
+
},
243
+
{
242
244
.compatible = "invensense,icm20602",
243
245
.data = (void *)INV_ICM20602
244
246
},
···
265
259
MODULE_DEVICE_TABLE(acpi, inv_acpi_match);
266
260
267
261
static struct i2c_driver inv_mpu_driver = {
268
-
.probe_new = inv_mpu_probe,
262
+
.probe = inv_mpu_probe,
269
263
.remove = inv_mpu_remove,
270
264
.id_table = inv_mpu_id,
271
265
.driver = {
+2
drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
+2
drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
···
79
79
INV_ICM20608D,
80
80
INV_ICM20609,
81
81
INV_ICM20689,
82
+
INV_ICM20600,
82
83
INV_ICM20602,
83
84
INV_ICM20690,
84
85
INV_IAM20680,
···
399
398
#define INV_ICM20608D_WHOAMI_VALUE 0xAE
400
399
#define INV_ICM20609_WHOAMI_VALUE 0xA6
401
400
#define INV_ICM20689_WHOAMI_VALUE 0x98
401
+
#define INV_ICM20600_WHOAMI_VALUE 0x11
402
402
#define INV_ICM20602_WHOAMI_VALUE 0x12
403
403
#define INV_ICM20690_WHOAMI_VALUE 0x20
404
404
#define INV_IAM20680_WHOAMI_VALUE 0xA9
+5
drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c
+5
drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c
···
76
76
{"icm20608d", INV_ICM20608D},
77
77
{"icm20609", INV_ICM20609},
78
78
{"icm20689", INV_ICM20689},
79
+
{"icm20600", INV_ICM20600},
79
80
{"icm20602", INV_ICM20602},
80
81
{"icm20690", INV_ICM20690},
81
82
{"iam20680", INV_IAM20680},
···
125
124
{
126
125
.compatible = "invensense,icm20689",
127
126
.data = (void *)INV_ICM20689
127
+
},
128
+
{
129
+
.compatible = "invensense,icm20600",
130
+
.data = (void *)INV_ICM20600
128
131
},
129
132
{
130
133
.compatible = "invensense,icm20602",
+1
-1
drivers/iio/imu/kmx61.c
+1
-1
drivers/iio/imu/kmx61.c
+1
-1
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c
+1
-1
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c
···
179
179
.of_match_table = st_lsm6dsx_i2c_of_match,
180
180
.acpi_match_table = st_lsm6dsx_i2c_acpi_match,
181
181
},
182
-
.probe_new = st_lsm6dsx_i2c_probe,
182
+
.probe = st_lsm6dsx_i2c_probe,
183
183
.id_table = st_lsm6dsx_i2c_id_table,
184
184
};
185
185
module_i2c_driver(st_lsm6dsx_driver);
+2
-1
drivers/iio/imu/st_lsm9ds0/Kconfig
+2
-1
drivers/iio/imu/st_lsm9ds0/Kconfig
···
10
10
11
11
help
12
12
Say yes here to build support for STMicroelectronics LSM9DS0 IMU
13
-
sensor. Supported devices: accelerometer/magnetometer of lsm9ds0.
13
+
sensor. Supported devices: accelerometer/magnetometer of lsm9ds0
14
+
and lsm303d.
14
15
15
16
To compile this driver as a module, choose M here: the module
16
17
will be called st_lsm9ds0.
+13
-1
drivers/iio/imu/st_lsm9ds0/st_lsm9ds0_i2c.c
+13
-1
drivers/iio/imu/st_lsm9ds0/st_lsm9ds0_i2c.c
···
19
19
20
20
static const struct of_device_id st_lsm9ds0_of_match[] = {
21
21
{
22
+
.compatible = "st,lsm303d-imu",
23
+
.data = LSM303D_IMU_DEV_NAME,
24
+
},
25
+
{
22
26
.compatible = "st,lsm9ds0-imu",
23
27
.data = LSM9DS0_IMU_DEV_NAME,
24
28
},
···
31
27
MODULE_DEVICE_TABLE(of, st_lsm9ds0_of_match);
32
28
33
29
static const struct i2c_device_id st_lsm9ds0_id_table[] = {
30
+
{ LSM303D_IMU_DEV_NAME },
34
31
{ LSM9DS0_IMU_DEV_NAME },
35
32
{}
36
33
};
37
34
MODULE_DEVICE_TABLE(i2c, st_lsm9ds0_id_table);
35
+
36
+
static const struct acpi_device_id st_lsm9ds0_acpi_match[] = {
37
+
{"ACCL0001", (kernel_ulong_t)LSM303D_IMU_DEV_NAME},
38
+
{ },
39
+
};
40
+
MODULE_DEVICE_TABLE(acpi, st_lsm9ds0_acpi_match);
38
41
39
42
static const struct regmap_config st_lsm9ds0_regmap_config = {
40
43
.reg_bits = 8,
···
79
68
.driver = {
80
69
.name = "st-lsm9ds0-i2c",
81
70
.of_match_table = st_lsm9ds0_of_match,
71
+
.acpi_match_table = st_lsm9ds0_acpi_match,
82
72
},
83
-
.probe_new = st_lsm9ds0_i2c_probe,
73
+
.probe = st_lsm9ds0_i2c_probe,
84
74
.id_table = st_lsm9ds0_id_table,
85
75
};
86
76
module_i2c_driver(st_lsm9ds0_driver);
+5
drivers/iio/imu/st_lsm9ds0/st_lsm9ds0_spi.c
+5
drivers/iio/imu/st_lsm9ds0/st_lsm9ds0_spi.c
···
19
19
20
20
static const struct of_device_id st_lsm9ds0_of_match[] = {
21
21
{
22
+
.compatible = "st,lsm303d-imu",
23
+
.data = LSM303D_IMU_DEV_NAME,
24
+
},
25
+
{
22
26
.compatible = "st,lsm9ds0-imu",
23
27
.data = LSM9DS0_IMU_DEV_NAME,
24
28
},
···
31
27
MODULE_DEVICE_TABLE(of, st_lsm9ds0_of_match);
32
28
33
29
static const struct spi_device_id st_lsm9ds0_id_table[] = {
30
+
{ LSM303D_IMU_DEV_NAME },
34
31
{ LSM9DS0_IMU_DEV_NAME },
35
32
{}
36
33
};
+49
-49
drivers/iio/industrialio-buffer.c
+49
-49
drivers/iio/industrialio-buffer.c
···
194
194
written = 0;
195
195
add_wait_queue(&rb->pollq, &wait);
196
196
do {
197
-
if (indio_dev->info == NULL)
197
+
if (!indio_dev->info)
198
198
return -ENODEV;
199
199
200
200
if (!iio_buffer_space_available(rb)) {
···
210
210
}
211
211
212
212
wait_woken(&wait, TASK_INTERRUPTIBLE,
213
-
MAX_SCHEDULE_TIMEOUT);
213
+
MAX_SCHEDULE_TIMEOUT);
214
214
continue;
215
215
}
216
216
···
242
242
struct iio_buffer *rb = ib->buffer;
243
243
struct iio_dev *indio_dev = ib->indio_dev;
244
244
245
-
if (!indio_dev->info || rb == NULL)
245
+
if (!indio_dev->info || !rb)
246
246
return 0;
247
247
248
248
poll_wait(filp, &rb->pollq, wait);
···
407
407
408
408
/* Note NULL used as error indicator as it doesn't make sense. */
409
409
static const unsigned long *iio_scan_mask_match(const unsigned long *av_masks,
410
-
unsigned int masklength,
411
-
const unsigned long *mask,
412
-
bool strict)
410
+
unsigned int masklength,
411
+
const unsigned long *mask,
412
+
bool strict)
413
413
{
414
414
if (bitmap_empty(mask, masklength))
415
415
return NULL;
···
427
427
}
428
428
429
429
static bool iio_validate_scan_mask(struct iio_dev *indio_dev,
430
-
const unsigned long *mask)
430
+
const unsigned long *mask)
431
431
{
432
432
if (!indio_dev->setup_ops->validate_scan_mask)
433
433
return true;
···
446
446
* individual buffers request is plausible.
447
447
*/
448
448
static int iio_scan_mask_set(struct iio_dev *indio_dev,
449
-
struct iio_buffer *buffer, int bit)
449
+
struct iio_buffer *buffer, int bit)
450
450
{
451
451
const unsigned long *mask;
452
452
unsigned long *trialmask;
···
539
539
mutex_unlock(&iio_dev_opaque->mlock);
540
540
541
541
return ret < 0 ? ret : len;
542
-
543
542
}
544
543
545
544
static ssize_t iio_scan_el_ts_show(struct device *dev,
···
705
706
}
706
707
707
708
static int iio_compute_scan_bytes(struct iio_dev *indio_dev,
708
-
const unsigned long *mask, bool timestamp)
709
+
const unsigned long *mask, bool timestamp)
709
710
{
710
711
unsigned int bytes = 0;
711
712
int length, i, largest = 0;
···
731
732
}
732
733
733
734
static void iio_buffer_activate(struct iio_dev *indio_dev,
734
-
struct iio_buffer *buffer)
735
+
struct iio_buffer *buffer)
735
736
{
736
737
struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev);
737
738
···
752
753
struct iio_buffer *buffer, *_buffer;
753
754
754
755
list_for_each_entry_safe(buffer, _buffer,
755
-
&iio_dev_opaque->buffer_list, buffer_list)
756
+
&iio_dev_opaque->buffer_list, buffer_list)
756
757
iio_buffer_deactivate(buffer);
757
758
}
758
759
759
760
static int iio_buffer_enable(struct iio_buffer *buffer,
760
-
struct iio_dev *indio_dev)
761
+
struct iio_dev *indio_dev)
761
762
{
762
763
if (!buffer->access->enable)
763
764
return 0;
···
765
766
}
766
767
767
768
static int iio_buffer_disable(struct iio_buffer *buffer,
768
-
struct iio_dev *indio_dev)
769
+
struct iio_dev *indio_dev)
769
770
{
770
771
if (!buffer->access->disable)
771
772
return 0;
···
773
774
}
774
775
775
776
static void iio_buffer_update_bytes_per_datum(struct iio_dev *indio_dev,
776
-
struct iio_buffer *buffer)
777
+
struct iio_buffer *buffer)
777
778
{
778
779
unsigned int bytes;
779
780
···
781
782
return;
782
783
783
784
bytes = iio_compute_scan_bytes(indio_dev, buffer->scan_mask,
784
-
buffer->scan_timestamp);
785
+
buffer->scan_timestamp);
785
786
786
787
buffer->access->set_bytes_per_datum(buffer, bytes);
787
788
}
788
789
789
790
static int iio_buffer_request_update(struct iio_dev *indio_dev,
790
-
struct iio_buffer *buffer)
791
+
struct iio_buffer *buffer)
791
792
{
792
793
int ret;
793
794
···
796
797
ret = buffer->access->request_update(buffer);
797
798
if (ret) {
798
799
dev_dbg(&indio_dev->dev,
799
-
"Buffer not started: buffer parameter update failed (%d)\n",
800
+
"Buffer not started: buffer parameter update failed (%d)\n",
800
801
ret);
801
802
return ret;
802
803
}
···
806
807
}
807
808
808
809
static void iio_free_scan_mask(struct iio_dev *indio_dev,
809
-
const unsigned long *mask)
810
+
const unsigned long *mask)
810
811
{
811
812
/* If the mask is dynamically allocated free it, otherwise do nothing */
812
813
if (!indio_dev->available_scan_masks)
···
822
823
};
823
824
824
825
static int iio_verify_update(struct iio_dev *indio_dev,
825
-
struct iio_buffer *insert_buffer, struct iio_buffer *remove_buffer,
826
-
struct iio_device_config *config)
826
+
struct iio_buffer *insert_buffer,
827
+
struct iio_buffer *remove_buffer,
828
+
struct iio_device_config *config)
827
829
{
828
830
struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev);
829
831
unsigned long *compound_mask;
···
864
864
if (insert_buffer) {
865
865
modes &= insert_buffer->access->modes;
866
866
config->watermark = min(config->watermark,
867
-
insert_buffer->watermark);
867
+
insert_buffer->watermark);
868
868
}
869
869
870
870
/* Definitely possible for devices to support both of these. */
···
890
890
891
891
/* What scan mask do we actually have? */
892
892
compound_mask = bitmap_zalloc(indio_dev->masklength, GFP_KERNEL);
893
-
if (compound_mask == NULL)
893
+
if (!compound_mask)
894
894
return -ENOMEM;
895
895
896
896
scan_timestamp = false;
···
911
911
912
912
if (indio_dev->available_scan_masks) {
913
913
scan_mask = iio_scan_mask_match(indio_dev->available_scan_masks,
914
-
indio_dev->masklength,
915
-
compound_mask,
916
-
strict_scanmask);
914
+
indio_dev->masklength,
915
+
compound_mask,
916
+
strict_scanmask);
917
917
bitmap_free(compound_mask);
918
-
if (scan_mask == NULL)
918
+
if (!scan_mask)
919
919
return -EINVAL;
920
920
} else {
921
921
scan_mask = compound_mask;
922
922
}
923
923
924
924
config->scan_bytes = iio_compute_scan_bytes(indio_dev,
925
-
scan_mask, scan_timestamp);
925
+
scan_mask, scan_timestamp);
926
926
config->scan_mask = scan_mask;
927
927
config->scan_timestamp = scan_timestamp;
928
928
···
954
954
}
955
955
956
956
static int iio_buffer_add_demux(struct iio_buffer *buffer,
957
-
struct iio_demux_table **p, unsigned int in_loc, unsigned int out_loc,
958
-
unsigned int length)
957
+
struct iio_demux_table **p, unsigned int in_loc,
958
+
unsigned int out_loc,
959
+
unsigned int length)
959
960
{
960
-
961
961
if (*p && (*p)->from + (*p)->length == in_loc &&
962
-
(*p)->to + (*p)->length == out_loc) {
962
+
(*p)->to + (*p)->length == out_loc) {
963
963
(*p)->length += length;
964
964
} else {
965
965
*p = kmalloc(sizeof(**p), GFP_KERNEL);
966
-
if (*p == NULL)
966
+
if (!(*p))
967
967
return -ENOMEM;
968
968
(*p)->from = in_loc;
969
969
(*p)->to = out_loc;
···
1027
1027
out_loc += length;
1028
1028
}
1029
1029
buffer->demux_bounce = kzalloc(out_loc, GFP_KERNEL);
1030
-
if (buffer->demux_bounce == NULL) {
1030
+
if (!buffer->demux_bounce) {
1031
1031
ret = -ENOMEM;
1032
1032
goto error_clear_mux_table;
1033
1033
}
···
1060
1060
}
1061
1061
1062
1062
static int iio_enable_buffers(struct iio_dev *indio_dev,
1063
-
struct iio_device_config *config)
1063
+
struct iio_device_config *config)
1064
1064
{
1065
1065
struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev);
1066
1066
struct iio_buffer *buffer, *tmp = NULL;
···
1078
1078
ret = indio_dev->setup_ops->preenable(indio_dev);
1079
1079
if (ret) {
1080
1080
dev_dbg(&indio_dev->dev,
1081
-
"Buffer not started: buffer preenable failed (%d)\n", ret);
1081
+
"Buffer not started: buffer preenable failed (%d)\n", ret);
1082
1082
goto err_undo_config;
1083
1083
}
1084
1084
}
···
1118
1118
ret = indio_dev->setup_ops->postenable(indio_dev);
1119
1119
if (ret) {
1120
1120
dev_dbg(&indio_dev->dev,
1121
-
"Buffer not started: postenable failed (%d)\n", ret);
1121
+
"Buffer not started: postenable failed (%d)\n", ret);
1122
1122
goto err_detach_pollfunc;
1123
1123
}
1124
1124
}
···
1194
1194
}
1195
1195
1196
1196
static int __iio_update_buffers(struct iio_dev *indio_dev,
1197
-
struct iio_buffer *insert_buffer,
1198
-
struct iio_buffer *remove_buffer)
1197
+
struct iio_buffer *insert_buffer,
1198
+
struct iio_buffer *remove_buffer)
1199
1199
{
1200
1200
struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev);
1201
1201
struct iio_device_config new_config;
1202
1202
int ret;
1203
1203
1204
1204
ret = iio_verify_update(indio_dev, insert_buffer, remove_buffer,
1205
-
&new_config);
1205
+
&new_config);
1206
1206
if (ret)
1207
1207
return ret;
1208
1208
···
1258
1258
return 0;
1259
1259
1260
1260
if (insert_buffer &&
1261
-
(insert_buffer->direction == IIO_BUFFER_DIRECTION_OUT))
1261
+
insert_buffer->direction == IIO_BUFFER_DIRECTION_OUT)
1262
1262
return -EINVAL;
1263
1263
1264
1264
mutex_lock(&iio_dev_opaque->info_exist_lock);
···
1275
1275
goto out_unlock;
1276
1276
}
1277
1277
1278
-
if (indio_dev->info == NULL) {
1278
+
if (!indio_dev->info) {
1279
1279
ret = -ENODEV;
1280
1280
goto out_unlock;
1281
1281
}
···
1615
1615
1616
1616
buffer_attrcount = 0;
1617
1617
if (buffer->attrs) {
1618
-
while (buffer->attrs[buffer_attrcount] != NULL)
1618
+
while (buffer->attrs[buffer_attrcount])
1619
1619
buffer_attrcount++;
1620
1620
}
1621
1621
buffer_attrcount += ARRAY_SIZE(iio_buffer_attrs);
···
1643
1643
}
1644
1644
1645
1645
ret = iio_buffer_add_channel_sysfs(indio_dev, buffer,
1646
-
&channels[i]);
1646
+
&channels[i]);
1647
1647
if (ret < 0)
1648
1648
goto error_cleanup_dynamic;
1649
1649
scan_el_attrcount += ret;
···
1651
1651
iio_dev_opaque->scan_index_timestamp =
1652
1652
channels[i].scan_index;
1653
1653
}
1654
-
if (indio_dev->masklength && buffer->scan_mask == NULL) {
1654
+
if (indio_dev->masklength && !buffer->scan_mask) {
1655
1655
buffer->scan_mask = bitmap_zalloc(indio_dev->masklength,
1656
1656
GFP_KERNEL);
1657
-
if (buffer->scan_mask == NULL) {
1657
+
if (!buffer->scan_mask) {
1658
1658
ret = -ENOMEM;
1659
1659
goto error_cleanup_dynamic;
1660
1660
}
···
1771
1771
goto error_unwind_sysfs_and_mask;
1772
1772
}
1773
1773
1774
-
sz = sizeof(*(iio_dev_opaque->buffer_ioctl_handler));
1774
+
sz = sizeof(*iio_dev_opaque->buffer_ioctl_handler);
1775
1775
iio_dev_opaque->buffer_ioctl_handler = kzalloc(sz, GFP_KERNEL);
1776
1776
if (!iio_dev_opaque->buffer_ioctl_handler) {
1777
1777
ret = -ENOMEM;
···
1820
1820
* a time.
1821
1821
*/
1822
1822
bool iio_validate_scan_mask_onehot(struct iio_dev *indio_dev,
1823
-
const unsigned long *mask)
1823
+
const unsigned long *mask)
1824
1824
{
1825
1825
return bitmap_weight(mask, indio_dev->masklength) == 1;
1826
1826
}
1827
1827
EXPORT_SYMBOL_GPL(iio_validate_scan_mask_onehot);
1828
1828
1829
1829
static const void *iio_demux(struct iio_buffer *buffer,
1830
-
const void *datain)
1830
+
const void *datain)
1831
1831
{
1832
1832
struct iio_demux_table *t;
1833
1833
+21
-1
drivers/iio/industrialio-trigger.c
+21
-1
drivers/iio/industrialio-trigger.c
···
322
322
* this is the case if the IIO device and the trigger device share the
323
323
* same parent device.
324
324
*/
325
-
if (pf->indio_dev->dev.parent == trig->dev.parent)
325
+
if (iio_validate_own_trigger(pf->indio_dev, trig))
326
326
trig->attached_own_device = true;
327
327
328
328
return ret;
···
727
727
return indio_dev->trig->attached_own_device;
728
728
}
729
729
EXPORT_SYMBOL(iio_trigger_using_own);
730
+
731
+
/**
732
+
* iio_validate_own_trigger - Check if a trigger and IIO device belong to
733
+
* the same device
734
+
* @idev: the IIO device to check
735
+
* @trig: the IIO trigger to check
736
+
*
737
+
* This function can be used as the validate_trigger callback for triggers that
738
+
* can only be attached to their own device.
739
+
*
740
+
* Return: 0 if both the trigger and the IIO device belong to the same
741
+
* device, -EINVAL otherwise.
742
+
*/
743
+
int iio_validate_own_trigger(struct iio_dev *idev, struct iio_trigger *trig)
744
+
{
745
+
if (idev->dev.parent != trig->dev.parent)
746
+
return -EINVAL;
747
+
return 0;
748
+
}
749
+
EXPORT_SYMBOL_GPL(iio_validate_own_trigger);
730
750
731
751
/**
732
752
* iio_trigger_validate_own_device - Check if a trigger and IIO device belong to
+25
drivers/iio/light/Kconfig
+25
drivers/iio/light/Kconfig
···
289
289
To compile this driver as a module, choose M here:
290
290
the module will be called jsa1212.
291
291
292
+
config ROHM_BU27008
293
+
tristate "ROHM BU27008 color (RGB+C/IR) sensor"
294
+
depends on I2C
295
+
select REGMAP_I2C
296
+
select IIO_GTS_HELPER
297
+
help
298
+
Enable support for the ROHM BU27008 color sensor.
299
+
The ROHM BU27008 is a sensor with 5 photodiodes (red, green,
300
+
blue, clear and IR) with four configurable channels. Red and
301
+
green being always available and two out of the rest three
302
+
(blue, clear, IR) can be selected to be simultaneously measured.
303
+
Typical application is adjusting LCD backlight of TVs,
304
+
mobile phones and tablet PCs.
305
+
292
306
config ROHM_BU27034
293
307
tristate "ROHM BU27034 ambient light sensor"
294
308
depends on I2C
···
426
412
427
413
If built as a dynamically linked module, it will be called
428
414
opt3001.
415
+
416
+
config OPT4001
417
+
tristate "Texas Instruments OPT4001 Light Sensor"
418
+
depends on I2C
419
+
select REGMAP_I2C
420
+
help
421
+
If you say Y or M here, you get support for Texas Instruments
422
+
OPT4001 Ambient Light Sensor.
423
+
424
+
If built as a dynamically linked module, it will be called
425
+
opt4001.
429
426
430
427
config PA12203001
431
428
tristate "TXC PA12203001 light and proximity sensor"
+2
drivers/iio/light/Makefile
+2
drivers/iio/light/Makefile
···
37
37
obj-$(CONFIG_MAX44009) += max44009.o
38
38
obj-$(CONFIG_NOA1305) += noa1305.o
39
39
obj-$(CONFIG_OPT3001) += opt3001.o
40
+
obj-$(CONFIG_OPT4001) += opt4001.o
40
41
obj-$(CONFIG_PA12203001) += pa12203001.o
42
+
obj-$(CONFIG_ROHM_BU27008) += rohm-bu27008.o
41
43
obj-$(CONFIG_ROHM_BU27034) += rohm-bu27034.o
42
44
obj-$(CONFIG_RPR0521) += rpr0521.o
43
45
obj-$(CONFIG_SI1133) += si1133.o
+1
-1
drivers/iio/light/adjd_s311.c
+1
-1
drivers/iio/light/adjd_s311.c
+1
-1
drivers/iio/light/adux1020.c
+1
-1
drivers/iio/light/adux1020.c
+1
-1
drivers/iio/light/al3010.c
+1
-1
drivers/iio/light/al3010.c
+9
-1
drivers/iio/light/al3320a.c
+9
-1
drivers/iio/light/al3320a.c
···
16
16
#include <linux/i2c.h>
17
17
#include <linux/module.h>
18
18
#include <linux/of.h>
19
+
#include <linux/mod_devicetable.h>
19
20
20
21
#include <linux/iio/iio.h>
21
22
#include <linux/iio/sysfs.h>
···
248
247
};
249
248
MODULE_DEVICE_TABLE(of, al3320a_of_match);
250
249
250
+
static const struct acpi_device_id al3320a_acpi_match[] = {
251
+
{"CALS0001"},
252
+
{ },
253
+
};
254
+
MODULE_DEVICE_TABLE(acpi, al3320a_acpi_match);
255
+
251
256
static struct i2c_driver al3320a_driver = {
252
257
.driver = {
253
258
.name = AL3320A_DRV_NAME,
254
259
.of_match_table = al3320a_of_match,
255
260
.pm = pm_sleep_ptr(&al3320a_pm_ops),
261
+
.acpi_match_table = al3320a_acpi_match,
256
262
},
257
-
.probe_new = al3320a_probe,
263
+
.probe = al3320a_probe,
258
264
.id_table = al3320a_id,
259
265
};
260
266
+1
-1
drivers/iio/light/apds9300.c
+1
-1
drivers/iio/light/apds9300.c
+1
-1
drivers/iio/light/apds9960.c
+1
-1
drivers/iio/light/apds9960.c
+1
-1
drivers/iio/light/as73211.c
+1
-1
drivers/iio/light/as73211.c
+1
-1
drivers/iio/light/bh1750.c
+1
-1
drivers/iio/light/bh1750.c
+1
-1
drivers/iio/light/bh1780.c
+1
-1
drivers/iio/light/bh1780.c
+1
-1
drivers/iio/light/cm32181.c
+1
-1
drivers/iio/light/cm32181.c
+1
-1
drivers/iio/light/cm3232.c
+1
-1
drivers/iio/light/cm3232.c
+1
-1
drivers/iio/light/cm3323.c
+1
-1
drivers/iio/light/cm3323.c
+1
-1
drivers/iio/light/cm36651.c
+1
-1
drivers/iio/light/cm36651.c
+1
-1
drivers/iio/light/gp2ap002.c
+1
-1
drivers/iio/light/gp2ap002.c
+1
-1
drivers/iio/light/gp2ap020a00f.c
+1
-1
drivers/iio/light/gp2ap020a00f.c
+1
-1
drivers/iio/light/isl29018.c
+1
-1
drivers/iio/light/isl29018.c
+1
-1
drivers/iio/light/isl29028.c
+1
-1
drivers/iio/light/isl29028.c
+1
-1
drivers/iio/light/isl29125.c
+1
-1
drivers/iio/light/isl29125.c
+1
-1
drivers/iio/light/jsa1212.c
+1
-1
drivers/iio/light/jsa1212.c
+1
-1
drivers/iio/light/ltr501.c
+1
-1
drivers/iio/light/ltr501.c
+1
-1
drivers/iio/light/ltrf216a.c
+1
-1
drivers/iio/light/ltrf216a.c
+1
-1
drivers/iio/light/lv0104cs.c
+1
-1
drivers/iio/light/lv0104cs.c
+1
-1
drivers/iio/light/max44000.c
+1
-1
drivers/iio/light/max44000.c
+1
-1
drivers/iio/light/max44009.c
+1
-1
drivers/iio/light/max44009.c
+1
-1
drivers/iio/light/noa1305.c
+1
-1
drivers/iio/light/noa1305.c
+1
-1
drivers/iio/light/opt3001.c
+1
-1
drivers/iio/light/opt3001.c
+467
drivers/iio/light/opt4001.c
+467
drivers/iio/light/opt4001.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2023 Axis Communications AB
4
+
*
5
+
* Datasheet: https://www.ti.com/lit/gpn/opt4001
6
+
*
7
+
* Device driver for the Texas Instruments OPT4001.
8
+
*/
9
+
10
+
#include <linux/bitfield.h>
11
+
#include <linux/i2c.h>
12
+
#include <linux/iio/iio.h>
13
+
#include <linux/math64.h>
14
+
#include <linux/module.h>
15
+
#include <linux/property.h>
16
+
#include <linux/regmap.h>
17
+
#include <linux/regulator/consumer.h>
18
+
19
+
/* OPT4001 register set */
20
+
#define OPT4001_LIGHT1_MSB 0x00
21
+
#define OPT4001_LIGHT1_LSB 0x01
22
+
#define OPT4001_CTRL 0x0A
23
+
#define OPT4001_DEVICE_ID 0x11
24
+
25
+
/* OPT4001 register mask */
26
+
#define OPT4001_EXPONENT_MASK GENMASK(15, 12)
27
+
#define OPT4001_MSB_MASK GENMASK(11, 0)
28
+
#define OPT4001_LSB_MASK GENMASK(15, 8)
29
+
#define OPT4001_COUNTER_MASK GENMASK(7, 4)
30
+
#define OPT4001_CRC_MASK GENMASK(3, 0)
31
+
32
+
/* OPT4001 device id mask */
33
+
#define OPT4001_DEVICE_ID_MASK GENMASK(11, 0)
34
+
35
+
/* OPT4001 control registers mask */
36
+
#define OPT4001_CTRL_QWAKE_MASK GENMASK(15, 15)
37
+
#define OPT4001_CTRL_RANGE_MASK GENMASK(13, 10)
38
+
#define OPT4001_CTRL_CONV_TIME_MASK GENMASK(9, 6)
39
+
#define OPT4001_CTRL_OPER_MODE_MASK GENMASK(5, 4)
40
+
#define OPT4001_CTRL_LATCH_MASK GENMASK(3, 3)
41
+
#define OPT4001_CTRL_INT_POL_MASK GENMASK(2, 2)
42
+
#define OPT4001_CTRL_FAULT_COUNT GENMASK(0, 1)
43
+
44
+
/* OPT4001 constants */
45
+
#define OPT4001_DEVICE_ID_VAL 0x121
46
+
47
+
/* OPT4001 operating modes */
48
+
#define OPT4001_CTRL_OPER_MODE_OFF 0x0
49
+
#define OPT4001_CTRL_OPER_MODE_FORCED 0x1
50
+
#define OPT4001_CTRL_OPER_MODE_ONE_SHOT 0x2
51
+
#define OPT4001_CTRL_OPER_MODE_CONTINUOUS 0x3
52
+
53
+
/* OPT4001 conversion control register definitions */
54
+
#define OPT4001_CTRL_CONVERSION_0_6MS 0x0
55
+
#define OPT4001_CTRL_CONVERSION_1MS 0x1
56
+
#define OPT4001_CTRL_CONVERSION_1_8MS 0x2
57
+
#define OPT4001_CTRL_CONVERSION_3_4MS 0x3
58
+
#define OPT4001_CTRL_CONVERSION_6_5MS 0x4
59
+
#define OPT4001_CTRL_CONVERSION_12_7MS 0x5
60
+
#define OPT4001_CTRL_CONVERSION_25MS 0x6
61
+
#define OPT4001_CTRL_CONVERSION_50MS 0x7
62
+
#define OPT4001_CTRL_CONVERSION_100MS 0x8
63
+
#define OPT4001_CTRL_CONVERSION_200MS 0x9
64
+
#define OPT4001_CTRL_CONVERSION_400MS 0xa
65
+
#define OPT4001_CTRL_CONVERSION_800MS 0xb
66
+
67
+
/* OPT4001 scale light level range definitions */
68
+
#define OPT4001_CTRL_LIGHT_SCALE_AUTO 12
69
+
70
+
/* OPT4001 default values */
71
+
#define OPT4001_DEFAULT_CONVERSION_TIME OPT4001_CTRL_CONVERSION_800MS
72
+
73
+
/*
74
+
* The different packaging of OPT4001 has different constants used when calculating
75
+
* lux values.
76
+
*/
77
+
struct opt4001_chip_info {
78
+
int mul;
79
+
int div;
80
+
const char *name;
81
+
};
82
+
83
+
struct opt4001_chip {
84
+
struct regmap *regmap;
85
+
struct i2c_client *client;
86
+
u8 int_time;
87
+
const struct opt4001_chip_info *chip_info;
88
+
};
89
+
90
+
static const struct opt4001_chip_info opt4001_sot_5x3_info = {
91
+
.mul = 4375,
92
+
.div = 10000000,
93
+
.name = "opt4001-sot-5x3"
94
+
};
95
+
96
+
static const struct opt4001_chip_info opt4001_picostar_info = {
97
+
.mul = 3125,
98
+
.div = 10000000,
99
+
.name = "opt4001-picostar"
100
+
};
101
+
102
+
static const int opt4001_int_time_available[][2] = {
103
+
{ 0, 600 },
104
+
{ 0, 1000 },
105
+
{ 0, 1800 },
106
+
{ 0, 3400 },
107
+
{ 0, 6500 },
108
+
{ 0, 12700 },
109
+
{ 0, 25000 },
110
+
{ 0, 50000 },
111
+
{ 0, 100000 },
112
+
{ 0, 200000 },
113
+
{ 0, 400000 },
114
+
{ 0, 800000 },
115
+
};
116
+
117
+
/*
118
+
* Conversion time is integration time + time to set register
119
+
* this is used as integration time.
120
+
*/
121
+
static const int opt4001_int_time_reg[][2] = {
122
+
{ 600, OPT4001_CTRL_CONVERSION_0_6MS },
123
+
{ 1000, OPT4001_CTRL_CONVERSION_1MS },
124
+
{ 1800, OPT4001_CTRL_CONVERSION_1_8MS },
125
+
{ 3400, OPT4001_CTRL_CONVERSION_3_4MS },
126
+
{ 6500, OPT4001_CTRL_CONVERSION_6_5MS },
127
+
{ 12700, OPT4001_CTRL_CONVERSION_12_7MS },
128
+
{ 25000, OPT4001_CTRL_CONVERSION_25MS },
129
+
{ 50000, OPT4001_CTRL_CONVERSION_50MS },
130
+
{ 100000, OPT4001_CTRL_CONVERSION_100MS },
131
+
{ 200000, OPT4001_CTRL_CONVERSION_200MS },
132
+
{ 400000, OPT4001_CTRL_CONVERSION_400MS },
133
+
{ 800000, OPT4001_CTRL_CONVERSION_800MS },
134
+
};
135
+
136
+
static int opt4001_als_time_to_index(const u32 als_integration_time)
137
+
{
138
+
int i;
139
+
140
+
for (i = 0; i < ARRAY_SIZE(opt4001_int_time_available); i++) {
141
+
if (als_integration_time == opt4001_int_time_available[i][1])
142
+
return i;
143
+
}
144
+
145
+
return -EINVAL;
146
+
}
147
+
148
+
static u8 opt4001_calculate_crc(u8 exp, u32 mantissa, u8 count)
149
+
{
150
+
u8 crc;
151
+
152
+
crc = (hweight32(mantissa) + hweight32(exp) + hweight32(count)) % 2;
153
+
crc |= ((hweight32(mantissa & 0xAAAAA) + hweight32(exp & 0xA)
154
+
+ hweight32(count & 0xA)) % 2) << 1;
155
+
crc |= ((hweight32(mantissa & 0x88888) + hweight32(exp & 0x8)
156
+
+ hweight32(count & 0x8)) % 2) << 2;
157
+
crc |= (hweight32(mantissa & 0x80808) % 2) << 3;
158
+
159
+
return crc;
160
+
}
161
+
162
+
static int opt4001_read_lux_value(struct iio_dev *indio_dev,
163
+
int *val, int *val2)
164
+
{
165
+
struct opt4001_chip *chip = iio_priv(indio_dev);
166
+
struct device *dev = &chip->client->dev;
167
+
unsigned int light1;
168
+
unsigned int light2;
169
+
u16 msb;
170
+
u16 lsb;
171
+
u8 exp;
172
+
u8 count;
173
+
u8 crc;
174
+
u8 calc_crc;
175
+
u64 lux_raw;
176
+
int ret;
177
+
178
+
ret = regmap_read(chip->regmap, OPT4001_LIGHT1_MSB, &light1);
179
+
if (ret < 0) {
180
+
dev_err(dev, "Failed to read data bytes");
181
+
return ret;
182
+
}
183
+
184
+
ret = regmap_read(chip->regmap, OPT4001_LIGHT1_LSB, &light2);
185
+
if (ret < 0) {
186
+
dev_err(dev, "Failed to read data bytes");
187
+
return ret;
188
+
}
189
+
190
+
count = FIELD_GET(OPT4001_COUNTER_MASK, light2);
191
+
exp = FIELD_GET(OPT4001_EXPONENT_MASK, light1);
192
+
crc = FIELD_GET(OPT4001_CRC_MASK, light2);
193
+
msb = FIELD_GET(OPT4001_MSB_MASK, light1);
194
+
lsb = FIELD_GET(OPT4001_LSB_MASK, light2);
195
+
lux_raw = (msb << 8) + lsb;
196
+
calc_crc = opt4001_calculate_crc(exp, lux_raw, count);
197
+
if (calc_crc != crc)
198
+
return -EIO;
199
+
200
+
lux_raw = lux_raw << exp;
201
+
lux_raw = lux_raw * chip->chip_info->mul;
202
+
*val = div_u64_rem(lux_raw, chip->chip_info->div, val2);
203
+
*val2 = *val2 * 100;
204
+
205
+
return IIO_VAL_INT_PLUS_NANO;
206
+
}
207
+
208
+
static int opt4001_set_conf(struct opt4001_chip *chip)
209
+
{
210
+
struct device *dev = &chip->client->dev;
211
+
u16 reg;
212
+
int ret;
213
+
214
+
reg = FIELD_PREP(OPT4001_CTRL_RANGE_MASK, OPT4001_CTRL_LIGHT_SCALE_AUTO);
215
+
reg |= FIELD_PREP(OPT4001_CTRL_CONV_TIME_MASK, chip->int_time);
216
+
reg |= FIELD_PREP(OPT4001_CTRL_OPER_MODE_MASK, OPT4001_CTRL_OPER_MODE_CONTINUOUS);
217
+
218
+
ret = regmap_write(chip->regmap, OPT4001_CTRL, reg);
219
+
if (ret)
220
+
dev_err(dev, "Failed to set configuration\n");
221
+
222
+
return ret;
223
+
}
224
+
225
+
static int opt4001_power_down(struct opt4001_chip *chip)
226
+
{
227
+
struct device *dev = &chip->client->dev;
228
+
int ret;
229
+
unsigned int reg;
230
+
231
+
ret = regmap_read(chip->regmap, OPT4001_DEVICE_ID, ®);
232
+
if (ret) {
233
+
dev_err(dev, "Failed to read configuration\n");
234
+
return ret;
235
+
}
236
+
237
+
/* MODE_OFF is 0x0 so just set bits to 0 */
238
+
reg &= ~OPT4001_CTRL_OPER_MODE_MASK;
239
+
240
+
ret = regmap_write(chip->regmap, OPT4001_CTRL, reg);
241
+
if (ret)
242
+
dev_err(dev, "Failed to set configuration to power down\n");
243
+
244
+
return ret;
245
+
}
246
+
247
+
static void opt4001_chip_off_action(void *data)
248
+
{
249
+
struct opt4001_chip *chip = data;
250
+
251
+
opt4001_power_down(chip);
252
+
}
253
+
254
+
static const struct iio_chan_spec opt4001_channels[] = {
255
+
{
256
+
.type = IIO_LIGHT,
257
+
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
258
+
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME),
259
+
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME)
260
+
},
261
+
};
262
+
263
+
static int opt4001_read_raw(struct iio_dev *indio_dev,
264
+
struct iio_chan_spec const *chan,
265
+
int *val, int *val2, long mask)
266
+
{
267
+
struct opt4001_chip *chip = iio_priv(indio_dev);
268
+
269
+
switch (mask) {
270
+
case IIO_CHAN_INFO_PROCESSED:
271
+
return opt4001_read_lux_value(indio_dev, val, val2);
272
+
case IIO_CHAN_INFO_INT_TIME:
273
+
*val = 0;
274
+
*val2 = opt4001_int_time_reg[chip->int_time][0];
275
+
return IIO_VAL_INT_PLUS_MICRO;
276
+
default:
277
+
return -EINVAL;
278
+
}
279
+
}
280
+
281
+
static int opt4001_write_raw(struct iio_dev *indio_dev,
282
+
struct iio_chan_spec const *chan,
283
+
int val, int val2, long mask)
284
+
{
285
+
struct opt4001_chip *chip = iio_priv(indio_dev);
286
+
int int_time;
287
+
288
+
switch (mask) {
289
+
case IIO_CHAN_INFO_INT_TIME:
290
+
int_time = opt4001_als_time_to_index(val2);
291
+
if (int_time < 0)
292
+
return int_time;
293
+
chip->int_time = int_time;
294
+
return opt4001_set_conf(chip);
295
+
default:
296
+
return -EINVAL;
297
+
}
298
+
}
299
+
300
+
static int opt4001_read_available(struct iio_dev *indio_dev,
301
+
struct iio_chan_spec const *chan,
302
+
const int **vals, int *type, int *length,
303
+
long mask)
304
+
{
305
+
switch (mask) {
306
+
case IIO_CHAN_INFO_INT_TIME:
307
+
*length = ARRAY_SIZE(opt4001_int_time_available) * 2;
308
+
*vals = (const int *)opt4001_int_time_available;
309
+
*type = IIO_VAL_INT_PLUS_MICRO;
310
+
return IIO_AVAIL_LIST;
311
+
312
+
default:
313
+
return -EINVAL;
314
+
}
315
+
}
316
+
317
+
static const struct iio_info opt4001_info_no_irq = {
318
+
.read_raw = opt4001_read_raw,
319
+
.write_raw = opt4001_write_raw,
320
+
.read_avail = opt4001_read_available,
321
+
};
322
+
323
+
static int opt4001_load_defaults(struct opt4001_chip *chip)
324
+
{
325
+
chip->int_time = OPT4001_DEFAULT_CONVERSION_TIME;
326
+
327
+
return opt4001_set_conf(chip);
328
+
}
329
+
330
+
static bool opt4001_readable_reg(struct device *dev, unsigned int reg)
331
+
{
332
+
switch (reg) {
333
+
case OPT4001_LIGHT1_MSB:
334
+
case OPT4001_LIGHT1_LSB:
335
+
case OPT4001_CTRL:
336
+
case OPT4001_DEVICE_ID:
337
+
return true;
338
+
default:
339
+
return false;
340
+
}
341
+
}
342
+
343
+
static bool opt4001_writable_reg(struct device *dev, unsigned int reg)
344
+
{
345
+
switch (reg) {
346
+
case OPT4001_CTRL:
347
+
return true;
348
+
default:
349
+
return false;
350
+
}
351
+
}
352
+
353
+
static bool opt4001_volatile_reg(struct device *dev, unsigned int reg)
354
+
{
355
+
switch (reg) {
356
+
case OPT4001_LIGHT1_MSB:
357
+
case OPT4001_LIGHT1_LSB:
358
+
return true;
359
+
default:
360
+
return false;
361
+
}
362
+
}
363
+
364
+
static const struct regmap_config opt4001_regmap_config = {
365
+
.name = "opt4001",
366
+
.reg_bits = 8,
367
+
.val_bits = 16,
368
+
.cache_type = REGCACHE_RBTREE,
369
+
.max_register = OPT4001_DEVICE_ID,
370
+
.readable_reg = opt4001_readable_reg,
371
+
.writeable_reg = opt4001_writable_reg,
372
+
.volatile_reg = opt4001_volatile_reg,
373
+
.val_format_endian = REGMAP_ENDIAN_BIG,
374
+
};
375
+
376
+
static int opt4001_probe(struct i2c_client *client)
377
+
{
378
+
struct opt4001_chip *chip;
379
+
struct iio_dev *indio_dev;
380
+
int ret;
381
+
uint dev_id;
382
+
383
+
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
384
+
if (!indio_dev)
385
+
return -ENOMEM;
386
+
387
+
chip = iio_priv(indio_dev);
388
+
389
+
ret = devm_regulator_get_enable(&client->dev, "vdd");
390
+
if (ret)
391
+
return dev_err_probe(&client->dev, ret, "Failed to enable vdd supply\n");
392
+
393
+
chip->regmap = devm_regmap_init_i2c(client, &opt4001_regmap_config);
394
+
if (IS_ERR(chip->regmap))
395
+
return dev_err_probe(&client->dev, PTR_ERR(chip->regmap),
396
+
"regmap initialization failed\n");
397
+
chip->client = client;
398
+
399
+
indio_dev->info = &opt4001_info_no_irq;
400
+
401
+
ret = regmap_reinit_cache(chip->regmap, &opt4001_regmap_config);
402
+
if (ret)
403
+
return dev_err_probe(&client->dev, ret,
404
+
"failed to reinit regmap cache\n");
405
+
406
+
ret = regmap_read(chip->regmap, OPT4001_DEVICE_ID, &dev_id);
407
+
if (ret < 0)
408
+
return dev_err_probe(&client->dev, ret,
409
+
"Failed to read the device ID register\n");
410
+
411
+
dev_id = FIELD_GET(OPT4001_DEVICE_ID_MASK, dev_id);
412
+
if (dev_id != OPT4001_DEVICE_ID_VAL)
413
+
dev_warn(&client->dev, "Device ID: %#04x unknown\n", dev_id);
414
+
415
+
chip->chip_info = device_get_match_data(&client->dev);
416
+
417
+
indio_dev->channels = opt4001_channels;
418
+
indio_dev->num_channels = ARRAY_SIZE(opt4001_channels);
419
+
indio_dev->modes = INDIO_DIRECT_MODE;
420
+
indio_dev->name = chip->chip_info->name;
421
+
422
+
ret = opt4001_load_defaults(chip);
423
+
if (ret < 0)
424
+
return dev_err_probe(&client->dev, ret,
425
+
"Failed to set sensor defaults\n");
426
+
427
+
ret = devm_add_action_or_reset(&client->dev,
428
+
opt4001_chip_off_action,
429
+
chip);
430
+
if (ret < 0)
431
+
return dev_err_probe(&client->dev, ret,
432
+
"Failed to setup power off action\n");
433
+
434
+
return devm_iio_device_register(&client->dev, indio_dev);
435
+
}
436
+
437
+
/*
438
+
* The compatible string determines which constants to use depending on
439
+
* opt4001 packaging
440
+
*/
441
+
static const struct i2c_device_id opt4001_id[] = {
442
+
{ "opt4001-sot-5x3", (kernel_ulong_t)&opt4001_sot_5x3_info },
443
+
{ "opt4001-picostar", (kernel_ulong_t)&opt4001_picostar_info },
444
+
{ }
445
+
};
446
+
MODULE_DEVICE_TABLE(i2c, opt4001_id);
447
+
448
+
static const struct of_device_id opt4001_of_match[] = {
449
+
{ .compatible = "ti,opt4001-sot-5x3", .data = &opt4001_sot_5x3_info},
450
+
{ .compatible = "ti,opt4001-picostar", .data = &opt4001_picostar_info},
451
+
{}
452
+
};
453
+
MODULE_DEVICE_TABLE(of, opt4001_of_match);
454
+
455
+
static struct i2c_driver opt4001_driver = {
456
+
.driver = {
457
+
.name = "opt4001",
458
+
.of_match_table = opt4001_of_match,
459
+
},
460
+
.probe = opt4001_probe,
461
+
.id_table = opt4001_id,
462
+
};
463
+
module_i2c_driver(opt4001_driver);
464
+
465
+
MODULE_AUTHOR("Stefan Windfeldt-Prytz <stefan.windfeldt-prytz@axis.com>");
466
+
MODULE_DESCRIPTION("Texas Instruments opt4001 ambient light sensor driver");
467
+
MODULE_LICENSE("GPL");
+1
-1
drivers/iio/light/pa12203001.c
+1
-1
drivers/iio/light/pa12203001.c
+1026
drivers/iio/light/rohm-bu27008.c
+1026
drivers/iio/light/rohm-bu27008.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* BU27008 ROHM Colour Sensor
4
+
*
5
+
* Copyright (c) 2023, ROHM Semiconductor.
6
+
*/
7
+
8
+
#include <linux/bitfield.h>
9
+
#include <linux/bitops.h>
10
+
#include <linux/device.h>
11
+
#include <linux/i2c.h>
12
+
#include <linux/interrupt.h>
13
+
#include <linux/module.h>
14
+
#include <linux/property.h>
15
+
#include <linux/regmap.h>
16
+
#include <linux/regulator/consumer.h>
17
+
#include <linux/units.h>
18
+
19
+
#include <linux/iio/iio.h>
20
+
#include <linux/iio/iio-gts-helper.h>
21
+
#include <linux/iio/trigger.h>
22
+
#include <linux/iio/trigger_consumer.h>
23
+
#include <linux/iio/triggered_buffer.h>
24
+
25
+
#define BU27008_REG_SYSTEM_CONTROL 0x40
26
+
#define BU27008_MASK_SW_RESET BIT(7)
27
+
#define BU27008_MASK_PART_ID GENMASK(5, 0)
28
+
#define BU27008_ID 0x1a
29
+
#define BU27008_REG_MODE_CONTROL1 0x41
30
+
#define BU27008_MASK_MEAS_MODE GENMASK(2, 0)
31
+
#define BU27008_MASK_CHAN_SEL GENMASK(3, 2)
32
+
33
+
#define BU27008_REG_MODE_CONTROL2 0x42
34
+
#define BU27008_MASK_RGBC_GAIN GENMASK(7, 3)
35
+
#define BU27008_MASK_IR_GAIN_LO GENMASK(2, 0)
36
+
#define BU27008_SHIFT_IR_GAIN 3
37
+
38
+
#define BU27008_REG_MODE_CONTROL3 0x43
39
+
#define BU27008_MASK_VALID BIT(7)
40
+
#define BU27008_MASK_INT_EN BIT(1)
41
+
#define BU27008_INT_EN BU27008_MASK_INT_EN
42
+
#define BU27008_INT_DIS 0
43
+
#define BU27008_MASK_MEAS_EN BIT(0)
44
+
#define BU27008_MEAS_EN BIT(0)
45
+
#define BU27008_MEAS_DIS 0
46
+
47
+
#define BU27008_REG_DATA0_LO 0x50
48
+
#define BU27008_REG_DATA1_LO 0x52
49
+
#define BU27008_REG_DATA2_LO 0x54
50
+
#define BU27008_REG_DATA3_LO 0x56
51
+
#define BU27008_REG_DATA3_HI 0x57
52
+
#define BU27008_REG_MANUFACTURER_ID 0x92
53
+
#define BU27008_REG_MAX BU27008_REG_MANUFACTURER_ID
54
+
55
+
/**
56
+
* enum bu27008_chan_type - BU27008 channel types
57
+
* @BU27008_RED: Red channel. Always via data0.
58
+
* @BU27008_GREEN: Green channel. Always via data1.
59
+
* @BU27008_BLUE: Blue channel. Via data2 (when used).
60
+
* @BU27008_CLEAR: Clear channel. Via data2 or data3 (when used).
61
+
* @BU27008_IR: IR channel. Via data3 (when used).
62
+
* @BU27008_NUM_CHANS: Number of channel types.
63
+
*/
64
+
enum bu27008_chan_type {
65
+
BU27008_RED,
66
+
BU27008_GREEN,
67
+
BU27008_BLUE,
68
+
BU27008_CLEAR,
69
+
BU27008_IR,
70
+
BU27008_NUM_CHANS
71
+
};
72
+
73
+
/**
74
+
* enum bu27008_chan - BU27008 physical data channel
75
+
* @BU27008_DATA0: Always red.
76
+
* @BU27008_DATA1: Always green.
77
+
* @BU27008_DATA2: Blue or clear.
78
+
* @BU27008_DATA3: IR or clear.
79
+
* @BU27008_NUM_HW_CHANS: Number of physical channels
80
+
*/
81
+
enum bu27008_chan {
82
+
BU27008_DATA0,
83
+
BU27008_DATA1,
84
+
BU27008_DATA2,
85
+
BU27008_DATA3,
86
+
BU27008_NUM_HW_CHANS
87
+
};
88
+
89
+
/* We can always measure red and green at same time */
90
+
#define ALWAYS_SCANNABLE (BIT(BU27008_RED) | BIT(BU27008_GREEN))
91
+
92
+
/* We use these data channel configs. Ensure scan_masks below follow them too */
93
+
#define BU27008_BLUE2_CLEAR3 0x0 /* buffer is R, G, B, C */
94
+
#define BU27008_CLEAR2_IR3 0x1 /* buffer is R, G, C, IR */
95
+
#define BU27008_BLUE2_IR3 0x2 /* buffer is R, G, B, IR */
96
+
97
+
static const unsigned long bu27008_scan_masks[] = {
98
+
/* buffer is R, G, B, C */
99
+
ALWAYS_SCANNABLE | BIT(BU27008_BLUE) | BIT(BU27008_CLEAR),
100
+
/* buffer is R, G, C, IR */
101
+
ALWAYS_SCANNABLE | BIT(BU27008_CLEAR) | BIT(BU27008_IR),
102
+
/* buffer is R, G, B, IR */
103
+
ALWAYS_SCANNABLE | BIT(BU27008_BLUE) | BIT(BU27008_IR),
104
+
0
105
+
};
106
+
107
+
/*
108
+
* Available scales with gain 1x - 1024x, timings 55, 100, 200, 400 mS
109
+
* Time impacts to gain: 1x, 2x, 4x, 8x.
110
+
*
111
+
* => Max total gain is HWGAIN * gain by integration time (8 * 1024) = 8192
112
+
*
113
+
* Max amplification is (HWGAIN * MAX integration-time multiplier) 1024 * 8
114
+
* = 8192. With NANO scale we get rid of accuracy loss when we start with the
115
+
* scale 16.0 for HWGAIN1, INT-TIME 55 mS. This way the nano scale for MAX
116
+
* total gain 8192 will be 1953125
117
+
*/
118
+
#define BU27008_SCALE_1X 16
119
+
120
+
/* See the data sheet for the "Gain Setting" table */
121
+
#define BU27008_GSEL_1X 0x00
122
+
#define BU27008_GSEL_4X 0x08
123
+
#define BU27008_GSEL_8X 0x09
124
+
#define BU27008_GSEL_16X 0x0a
125
+
#define BU27008_GSEL_32X 0x0b
126
+
#define BU27008_GSEL_64X 0x0c
127
+
#define BU27008_GSEL_256X 0x18
128
+
#define BU27008_GSEL_512X 0x19
129
+
#define BU27008_GSEL_1024X 0x1a
130
+
131
+
static const struct iio_gain_sel_pair bu27008_gains[] = {
132
+
GAIN_SCALE_GAIN(1, BU27008_GSEL_1X),
133
+
GAIN_SCALE_GAIN(4, BU27008_GSEL_4X),
134
+
GAIN_SCALE_GAIN(8, BU27008_GSEL_8X),
135
+
GAIN_SCALE_GAIN(16, BU27008_GSEL_16X),
136
+
GAIN_SCALE_GAIN(32, BU27008_GSEL_32X),
137
+
GAIN_SCALE_GAIN(64, BU27008_GSEL_64X),
138
+
GAIN_SCALE_GAIN(256, BU27008_GSEL_256X),
139
+
GAIN_SCALE_GAIN(512, BU27008_GSEL_512X),
140
+
GAIN_SCALE_GAIN(1024, BU27008_GSEL_1024X),
141
+
};
142
+
143
+
static const struct iio_gain_sel_pair bu27008_gains_ir[] = {
144
+
GAIN_SCALE_GAIN(2, BU27008_GSEL_1X),
145
+
GAIN_SCALE_GAIN(4, BU27008_GSEL_4X),
146
+
GAIN_SCALE_GAIN(8, BU27008_GSEL_8X),
147
+
GAIN_SCALE_GAIN(16, BU27008_GSEL_16X),
148
+
GAIN_SCALE_GAIN(32, BU27008_GSEL_32X),
149
+
GAIN_SCALE_GAIN(64, BU27008_GSEL_64X),
150
+
GAIN_SCALE_GAIN(256, BU27008_GSEL_256X),
151
+
GAIN_SCALE_GAIN(512, BU27008_GSEL_512X),
152
+
GAIN_SCALE_GAIN(1024, BU27008_GSEL_1024X),
153
+
};
154
+
155
+
#define BU27008_MEAS_MODE_100MS 0x00
156
+
#define BU27008_MEAS_MODE_55MS 0x01
157
+
#define BU27008_MEAS_MODE_200MS 0x02
158
+
#define BU27008_MEAS_MODE_400MS 0x04
159
+
#define BU27008_MEAS_TIME_MAX_MS 400
160
+
161
+
static const struct iio_itime_sel_mul bu27008_itimes[] = {
162
+
GAIN_SCALE_ITIME_US(400000, BU27008_MEAS_MODE_400MS, 8),
163
+
GAIN_SCALE_ITIME_US(200000, BU27008_MEAS_MODE_200MS, 4),
164
+
GAIN_SCALE_ITIME_US(100000, BU27008_MEAS_MODE_100MS, 2),
165
+
GAIN_SCALE_ITIME_US(55000, BU27008_MEAS_MODE_55MS, 1),
166
+
};
167
+
168
+
/*
169
+
* All the RGBC channels share the same gain.
170
+
* IR gain can be fine-tuned from the gain set for the RGBC by 2 bit, but this
171
+
* would yield quite complex gain setting. Especially since not all bit
172
+
* compinations are supported. And in any case setting GAIN for RGBC will
173
+
* always also change the IR-gain.
174
+
*
175
+
* On top of this, the selector '0' which corresponds to hw-gain 1X on RGBC,
176
+
* corresponds to gain 2X on IR. Rest of the selctors correspond to same gains
177
+
* though. This, however, makes it not possible to use shared gain for all
178
+
* RGBC and IR settings even though they are all changed at the one go.
179
+
*/
180
+
#define BU27008_CHAN(color, data, separate_avail) \
181
+
{ \
182
+
.type = IIO_INTENSITY, \
183
+
.modified = 1, \
184
+
.channel2 = IIO_MOD_LIGHT_##color, \
185
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
186
+
BIT(IIO_CHAN_INFO_SCALE), \
187
+
.info_mask_separate_available = (separate_avail), \
188
+
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME), \
189
+
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME), \
190
+
.address = BU27008_REG_##data##_LO, \
191
+
.scan_index = BU27008_##color, \
192
+
.scan_type = { \
193
+
.sign = 's', \
194
+
.realbits = 16, \
195
+
.storagebits = 16, \
196
+
.endianness = IIO_LE, \
197
+
}, \
198
+
}
199
+
200
+
/* For raw reads we always configure DATA3 for CLEAR */
201
+
static const struct iio_chan_spec bu27008_channels[] = {
202
+
BU27008_CHAN(RED, DATA0, BIT(IIO_CHAN_INFO_SCALE)),
203
+
BU27008_CHAN(GREEN, DATA1, BIT(IIO_CHAN_INFO_SCALE)),
204
+
BU27008_CHAN(BLUE, DATA2, BIT(IIO_CHAN_INFO_SCALE)),
205
+
BU27008_CHAN(CLEAR, DATA2, BIT(IIO_CHAN_INFO_SCALE)),
206
+
/*
207
+
* We don't allow setting scale for IR (because of shared gain bits).
208
+
* Hence we don't advertise available ones either.
209
+
*/
210
+
BU27008_CHAN(IR, DATA3, 0),
211
+
IIO_CHAN_SOFT_TIMESTAMP(BU27008_NUM_CHANS),
212
+
};
213
+
214
+
struct bu27008_data {
215
+
struct regmap *regmap;
216
+
struct iio_trigger *trig;
217
+
struct device *dev;
218
+
struct iio_gts gts;
219
+
struct iio_gts gts_ir;
220
+
int irq;
221
+
222
+
/*
223
+
* Prevent changing gain/time config when scale is read/written.
224
+
* Similarly, protect the integration_time read/change sequence.
225
+
* Prevent changing gain/time when data is read.
226
+
*/
227
+
struct mutex mutex;
228
+
};
229
+
230
+
static const struct regmap_range bu27008_volatile_ranges[] = {
231
+
{
232
+
.range_min = BU27008_REG_SYSTEM_CONTROL, /* SWRESET */
233
+
.range_max = BU27008_REG_SYSTEM_CONTROL,
234
+
}, {
235
+
.range_min = BU27008_REG_MODE_CONTROL3, /* VALID */
236
+
.range_max = BU27008_REG_MODE_CONTROL3,
237
+
}, {
238
+
.range_min = BU27008_REG_DATA0_LO, /* DATA */
239
+
.range_max = BU27008_REG_DATA3_HI,
240
+
},
241
+
};
242
+
243
+
static const struct regmap_access_table bu27008_volatile_regs = {
244
+
.yes_ranges = &bu27008_volatile_ranges[0],
245
+
.n_yes_ranges = ARRAY_SIZE(bu27008_volatile_ranges),
246
+
};
247
+
248
+
static const struct regmap_range bu27008_read_only_ranges[] = {
249
+
{
250
+
.range_min = BU27008_REG_DATA0_LO,
251
+
.range_max = BU27008_REG_DATA3_HI,
252
+
}, {
253
+
.range_min = BU27008_REG_MANUFACTURER_ID,
254
+
.range_max = BU27008_REG_MANUFACTURER_ID,
255
+
},
256
+
};
257
+
258
+
static const struct regmap_access_table bu27008_ro_regs = {
259
+
.no_ranges = &bu27008_read_only_ranges[0],
260
+
.n_no_ranges = ARRAY_SIZE(bu27008_read_only_ranges),
261
+
};
262
+
263
+
static const struct regmap_config bu27008_regmap = {
264
+
.reg_bits = 8,
265
+
.val_bits = 8,
266
+
.max_register = BU27008_REG_MAX,
267
+
.cache_type = REGCACHE_RBTREE,
268
+
.volatile_table = &bu27008_volatile_regs,
269
+
.wr_table = &bu27008_ro_regs,
270
+
/*
271
+
* All register writes are serialized by the mutex which protects the
272
+
* scale setting/getting. This is needed because scale is combined by
273
+
* gain and integration time settings and we need to ensure those are
274
+
* not read / written when scale is being computed.
275
+
*
276
+
* As a result of this serializing, we don't need regmap locking. Note,
277
+
* this is not true if we add any configurations which are not
278
+
* serialized by the mutex and which may need for example a protected
279
+
* read-modify-write cycle (eg. regmap_update_bits()). Please, revise
280
+
* this when adding features to the driver.
281
+
*/
282
+
.disable_locking = true,
283
+
};
284
+
285
+
#define BU27008_MAX_VALID_RESULT_WAIT_US 50000
286
+
#define BU27008_VALID_RESULT_WAIT_QUANTA_US 1000
287
+
288
+
static int bu27008_chan_read_data(struct bu27008_data *data, int reg, int *val)
289
+
{
290
+
int ret, valid;
291
+
__le16 tmp;
292
+
293
+
ret = regmap_read_poll_timeout(data->regmap, BU27008_REG_MODE_CONTROL3,
294
+
valid, (valid & BU27008_MASK_VALID),
295
+
BU27008_VALID_RESULT_WAIT_QUANTA_US,
296
+
BU27008_MAX_VALID_RESULT_WAIT_US);
297
+
if (ret)
298
+
return ret;
299
+
300
+
ret = regmap_bulk_read(data->regmap, reg, &tmp, sizeof(tmp));
301
+
if (ret)
302
+
dev_err(data->dev, "Reading channel data failed\n");
303
+
304
+
*val = le16_to_cpu(tmp);
305
+
306
+
return ret;
307
+
}
308
+
309
+
static int bu27008_get_gain(struct bu27008_data *data, struct iio_gts *gts, int *gain)
310
+
{
311
+
int ret, sel;
312
+
313
+
ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL2, &sel);
314
+
if (ret)
315
+
return ret;
316
+
317
+
sel = FIELD_GET(BU27008_MASK_RGBC_GAIN, sel);
318
+
319
+
ret = iio_gts_find_gain_by_sel(gts, sel);
320
+
if (ret < 0) {
321
+
dev_err(data->dev, "unknown gain value 0x%x\n", sel);
322
+
return ret;
323
+
}
324
+
325
+
*gain = ret;
326
+
327
+
return 0;
328
+
}
329
+
330
+
static int bu27008_write_gain_sel(struct bu27008_data *data, int sel)
331
+
{
332
+
int regval;
333
+
334
+
regval = FIELD_PREP(BU27008_MASK_RGBC_GAIN, sel);
335
+
336
+
/*
337
+
* We do always set also the LOW bits of IR-gain because othervice we
338
+
* would risk resulting an invalid GAIN register value.
339
+
*
340
+
* We could allow setting separate gains for RGBC and IR when the
341
+
* values were such that HW could support both gain settings.
342
+
* Eg, when the shared bits were same for both gain values.
343
+
*
344
+
* This, however, has a negligible benefit compared to the increased
345
+
* software complexity when we would need to go through the gains
346
+
* for both channels separately when the integration time changes.
347
+
* This would end up with nasty logic for computing gain values for
348
+
* both channels - and rejecting them if shared bits changed.
349
+
*
350
+
* We should then build the logic by guessing what a user prefers.
351
+
* RGBC or IR gains correctly set while other jumps to odd value?
352
+
* Maybe look-up a value where both gains are somehow optimized
353
+
* <what this somehow is, is ATM unknown to us>. Or maybe user would
354
+
* expect us to reject changes when optimal gains can't be set to both
355
+
* channels w/given integration time. At best that would result
356
+
* solution that works well for a very specific subset of
357
+
* configurations but causes unexpected corner-cases.
358
+
*
359
+
* So, we keep it simple. Always set same selector to IR and RGBC.
360
+
* We disallow setting IR (as I expect that most of the users are
361
+
* interested in RGBC). This way we can show the user that the scales
362
+
* for RGBC and IR channels are different (1X Vs 2X with sel 0) while
363
+
* still keeping the operation deterministic.
364
+
*/
365
+
regval |= FIELD_PREP(BU27008_MASK_IR_GAIN_LO, sel);
366
+
367
+
return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL2,
368
+
BU27008_MASK_RGBC_GAIN, regval);
369
+
}
370
+
371
+
static int bu27008_set_gain(struct bu27008_data *data, int gain)
372
+
{
373
+
int ret;
374
+
375
+
ret = iio_gts_find_sel_by_gain(&data->gts, gain);
376
+
if (ret < 0)
377
+
return ret;
378
+
379
+
return bu27008_write_gain_sel(data, ret);
380
+
}
381
+
382
+
static int bu27008_get_int_time_sel(struct bu27008_data *data, int *sel)
383
+
{
384
+
int ret, val;
385
+
386
+
ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL1, &val);
387
+
*sel = FIELD_GET(BU27008_MASK_MEAS_MODE, val);
388
+
389
+
return ret;
390
+
}
391
+
392
+
static int bu27008_set_int_time_sel(struct bu27008_data *data, int sel)
393
+
{
394
+
return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL1,
395
+
BU27008_MASK_MEAS_MODE, sel);
396
+
}
397
+
398
+
static int bu27008_get_int_time_us(struct bu27008_data *data)
399
+
{
400
+
int ret, sel;
401
+
402
+
ret = bu27008_get_int_time_sel(data, &sel);
403
+
if (ret)
404
+
return ret;
405
+
406
+
return iio_gts_find_int_time_by_sel(&data->gts, sel);
407
+
}
408
+
409
+
static int _bu27008_get_scale(struct bu27008_data *data, bool ir, int *val,
410
+
int *val2)
411
+
{
412
+
struct iio_gts *gts;
413
+
int gain, ret;
414
+
415
+
if (ir)
416
+
gts = &data->gts_ir;
417
+
else
418
+
gts = &data->gts;
419
+
420
+
ret = bu27008_get_gain(data, gts, &gain);
421
+
if (ret)
422
+
return ret;
423
+
424
+
ret = bu27008_get_int_time_us(data);
425
+
if (ret < 0)
426
+
return ret;
427
+
428
+
return iio_gts_get_scale(gts, gain, ret, val, val2);
429
+
}
430
+
431
+
static int bu27008_get_scale(struct bu27008_data *data, bool ir, int *val,
432
+
int *val2)
433
+
{
434
+
int ret;
435
+
436
+
mutex_lock(&data->mutex);
437
+
ret = _bu27008_get_scale(data, ir, val, val2);
438
+
mutex_unlock(&data->mutex);
439
+
440
+
return ret;
441
+
}
442
+
443
+
static int bu27008_set_int_time(struct bu27008_data *data, int time)
444
+
{
445
+
int ret;
446
+
447
+
ret = iio_gts_find_sel_by_int_time(&data->gts, time);
448
+
if (ret < 0)
449
+
return ret;
450
+
451
+
return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL1,
452
+
BU27008_MASK_MEAS_MODE, ret);
453
+
}
454
+
455
+
/* Try to change the time so that the scale is maintained */
456
+
static int bu27008_try_set_int_time(struct bu27008_data *data, int int_time_new)
457
+
{
458
+
int ret, old_time_sel, new_time_sel, old_gain, new_gain;
459
+
460
+
mutex_lock(&data->mutex);
461
+
462
+
ret = bu27008_get_int_time_sel(data, &old_time_sel);
463
+
if (ret < 0)
464
+
goto unlock_out;
465
+
466
+
if (!iio_gts_valid_time(&data->gts, int_time_new)) {
467
+
dev_dbg(data->dev, "Unsupported integration time %u\n",
468
+
int_time_new);
469
+
470
+
ret = -EINVAL;
471
+
goto unlock_out;
472
+
}
473
+
474
+
/* If we already use requested time, then we're done */
475
+
new_time_sel = iio_gts_find_sel_by_int_time(&data->gts, int_time_new);
476
+
if (new_time_sel == old_time_sel)
477
+
goto unlock_out;
478
+
479
+
ret = bu27008_get_gain(data, &data->gts, &old_gain);
480
+
if (ret)
481
+
goto unlock_out;
482
+
483
+
ret = iio_gts_find_new_gain_sel_by_old_gain_time(&data->gts, old_gain,
484
+
old_time_sel, new_time_sel, &new_gain);
485
+
if (ret) {
486
+
int scale1, scale2;
487
+
bool ok;
488
+
489
+
_bu27008_get_scale(data, false, &scale1, &scale2);
490
+
dev_dbg(data->dev,
491
+
"Can't support time %u with current scale %u %u\n",
492
+
int_time_new, scale1, scale2);
493
+
494
+
if (new_gain < 0)
495
+
goto unlock_out;
496
+
497
+
/*
498
+
* If caller requests for integration time change and we
499
+
* can't support the scale - then the caller should be
500
+
* prepared to 'pick up the pieces and deal with the
501
+
* fact that the scale changed'.
502
+
*/
503
+
ret = iio_find_closest_gain_low(&data->gts, new_gain, &ok);
504
+
if (!ok)
505
+
dev_dbg(data->dev, "optimal gain out of range\n");
506
+
507
+
if (ret < 0) {
508
+
dev_dbg(data->dev,
509
+
"Total gain increase. Risk of saturation");
510
+
ret = iio_gts_get_min_gain(&data->gts);
511
+
if (ret < 0)
512
+
goto unlock_out;
513
+
}
514
+
new_gain = ret;
515
+
dev_dbg(data->dev, "scale changed, new gain %u\n", new_gain);
516
+
}
517
+
518
+
ret = bu27008_set_gain(data, new_gain);
519
+
if (ret)
520
+
goto unlock_out;
521
+
522
+
ret = bu27008_set_int_time(data, int_time_new);
523
+
524
+
unlock_out:
525
+
mutex_unlock(&data->mutex);
526
+
527
+
return ret;
528
+
}
529
+
530
+
static int bu27008_meas_set(struct bu27008_data *data, int state)
531
+
{
532
+
return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL3,
533
+
BU27008_MASK_MEAS_EN, state);
534
+
}
535
+
536
+
static int bu27008_chan_cfg(struct bu27008_data *data,
537
+
struct iio_chan_spec const *chan)
538
+
{
539
+
int chan_sel;
540
+
541
+
if (chan->scan_index == BU27008_BLUE)
542
+
chan_sel = BU27008_BLUE2_CLEAR3;
543
+
else
544
+
chan_sel = BU27008_CLEAR2_IR3;
545
+
546
+
chan_sel = FIELD_PREP(BU27008_MASK_CHAN_SEL, chan_sel);
547
+
548
+
return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL3,
549
+
BU27008_MASK_CHAN_SEL, chan_sel);
550
+
}
551
+
552
+
static int bu27008_read_one(struct bu27008_data *data, struct iio_dev *idev,
553
+
struct iio_chan_spec const *chan, int *val, int *val2)
554
+
{
555
+
int ret, int_time;
556
+
557
+
ret = bu27008_chan_cfg(data, chan);
558
+
if (ret)
559
+
return ret;
560
+
561
+
ret = bu27008_meas_set(data, BU27008_MEAS_EN);
562
+
if (ret)
563
+
return ret;
564
+
565
+
ret = bu27008_get_int_time_us(data);
566
+
if (ret < 0)
567
+
int_time = BU27008_MEAS_TIME_MAX_MS;
568
+
else
569
+
int_time = ret / USEC_PER_MSEC;
570
+
571
+
msleep(int_time);
572
+
573
+
ret = bu27008_chan_read_data(data, chan->address, val);
574
+
if (!ret)
575
+
ret = IIO_VAL_INT;
576
+
577
+
if (bu27008_meas_set(data, BU27008_MEAS_DIS))
578
+
dev_warn(data->dev, "measurement disabling failed\n");
579
+
580
+
return ret;
581
+
}
582
+
583
+
static int bu27008_read_raw(struct iio_dev *idev,
584
+
struct iio_chan_spec const *chan,
585
+
int *val, int *val2, long mask)
586
+
{
587
+
struct bu27008_data *data = iio_priv(idev);
588
+
int busy, ret;
589
+
590
+
switch (mask) {
591
+
case IIO_CHAN_INFO_RAW:
592
+
busy = iio_device_claim_direct_mode(idev);
593
+
if (busy)
594
+
return -EBUSY;
595
+
596
+
mutex_lock(&data->mutex);
597
+
ret = bu27008_read_one(data, idev, chan, val, val2);
598
+
mutex_unlock(&data->mutex);
599
+
600
+
iio_device_release_direct_mode(idev);
601
+
602
+
return ret;
603
+
604
+
case IIO_CHAN_INFO_SCALE:
605
+
ret = bu27008_get_scale(data, chan->scan_index == BU27008_IR,
606
+
val, val2);
607
+
if (ret)
608
+
return ret;
609
+
610
+
return IIO_VAL_INT_PLUS_NANO;
611
+
612
+
case IIO_CHAN_INFO_INT_TIME:
613
+
ret = bu27008_get_int_time_us(data);
614
+
if (ret < 0)
615
+
return ret;
616
+
617
+
*val = 0;
618
+
*val2 = ret;
619
+
620
+
return IIO_VAL_INT_PLUS_MICRO;
621
+
622
+
default:
623
+
return -EINVAL;
624
+
}
625
+
}
626
+
627
+
/* Called if the new scale could not be supported with existing int-time */
628
+
static int bu27008_try_find_new_time_gain(struct bu27008_data *data, int val,
629
+
int val2, int *gain_sel)
630
+
{
631
+
int i, ret, new_time_sel;
632
+
633
+
for (i = 0; i < data->gts.num_itime; i++) {
634
+
new_time_sel = data->gts.itime_table[i].sel;
635
+
ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts,
636
+
new_time_sel, val, val2 * 1000, gain_sel);
637
+
if (!ret)
638
+
break;
639
+
}
640
+
if (i == data->gts.num_itime) {
641
+
dev_err(data->dev, "Can't support scale %u %u\n", val, val2);
642
+
643
+
return -EINVAL;
644
+
}
645
+
646
+
return bu27008_set_int_time_sel(data, new_time_sel);
647
+
}
648
+
649
+
static int bu27008_set_scale(struct bu27008_data *data,
650
+
struct iio_chan_spec const *chan,
651
+
int val, int val2)
652
+
{
653
+
int ret, gain_sel, time_sel;
654
+
655
+
if (chan->scan_index == BU27008_IR)
656
+
return -EINVAL;
657
+
658
+
mutex_lock(&data->mutex);
659
+
660
+
ret = bu27008_get_int_time_sel(data, &time_sel);
661
+
if (ret < 0)
662
+
goto unlock_out;
663
+
664
+
ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts, time_sel,
665
+
val, val2 * 1000, &gain_sel);
666
+
if (ret) {
667
+
ret = bu27008_try_find_new_time_gain(data, val, val2, &gain_sel);
668
+
if (ret)
669
+
goto unlock_out;
670
+
671
+
}
672
+
ret = bu27008_write_gain_sel(data, gain_sel);
673
+
674
+
unlock_out:
675
+
mutex_unlock(&data->mutex);
676
+
677
+
return ret;
678
+
}
679
+
680
+
static int bu27008_write_raw(struct iio_dev *idev,
681
+
struct iio_chan_spec const *chan,
682
+
int val, int val2, long mask)
683
+
{
684
+
struct bu27008_data *data = iio_priv(idev);
685
+
int ret;
686
+
687
+
/*
688
+
* Do not allow changing scale when measurement is ongoing as doing so
689
+
* could make values in the buffer inconsistent.
690
+
*/
691
+
ret = iio_device_claim_direct_mode(idev);
692
+
if (ret)
693
+
return ret;
694
+
695
+
switch (mask) {
696
+
case IIO_CHAN_INFO_SCALE:
697
+
ret = bu27008_set_scale(data, chan, val, val2);
698
+
break;
699
+
case IIO_CHAN_INFO_INT_TIME:
700
+
if (val) {
701
+
ret = -EINVAL;
702
+
break;
703
+
}
704
+
ret = bu27008_try_set_int_time(data, val2);
705
+
break;
706
+
default:
707
+
ret = -EINVAL;
708
+
break;
709
+
}
710
+
iio_device_release_direct_mode(idev);
711
+
712
+
return ret;
713
+
}
714
+
715
+
static int bu27008_read_avail(struct iio_dev *idev,
716
+
struct iio_chan_spec const *chan, const int **vals,
717
+
int *type, int *length, long mask)
718
+
{
719
+
struct bu27008_data *data = iio_priv(idev);
720
+
721
+
switch (mask) {
722
+
case IIO_CHAN_INFO_INT_TIME:
723
+
return iio_gts_avail_times(&data->gts, vals, type, length);
724
+
case IIO_CHAN_INFO_SCALE:
725
+
if (chan->channel2 == IIO_MOD_LIGHT_IR)
726
+
return iio_gts_all_avail_scales(&data->gts_ir, vals,
727
+
type, length);
728
+
return iio_gts_all_avail_scales(&data->gts, vals, type, length);
729
+
default:
730
+
return -EINVAL;
731
+
}
732
+
}
733
+
734
+
static int bu27008_update_scan_mode(struct iio_dev *idev,
735
+
const unsigned long *scan_mask)
736
+
{
737
+
struct bu27008_data *data = iio_priv(idev);
738
+
int chan_sel;
739
+
740
+
/* Configure channel selection */
741
+
if (test_bit(BU27008_BLUE, idev->active_scan_mask)) {
742
+
if (test_bit(BU27008_CLEAR, idev->active_scan_mask))
743
+
chan_sel = BU27008_BLUE2_CLEAR3;
744
+
else
745
+
chan_sel = BU27008_BLUE2_IR3;
746
+
} else {
747
+
chan_sel = BU27008_CLEAR2_IR3;
748
+
}
749
+
750
+
chan_sel = FIELD_PREP(BU27008_MASK_CHAN_SEL, chan_sel);
751
+
752
+
return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL3,
753
+
BU27008_MASK_CHAN_SEL, chan_sel);
754
+
}
755
+
756
+
static const struct iio_info bu27008_info = {
757
+
.read_raw = &bu27008_read_raw,
758
+
.write_raw = &bu27008_write_raw,
759
+
.read_avail = &bu27008_read_avail,
760
+
.update_scan_mode = bu27008_update_scan_mode,
761
+
.validate_trigger = iio_validate_own_trigger,
762
+
};
763
+
764
+
static int bu27008_chip_init(struct bu27008_data *data)
765
+
{
766
+
int ret;
767
+
768
+
ret = regmap_write_bits(data->regmap, BU27008_REG_SYSTEM_CONTROL,
769
+
BU27008_MASK_SW_RESET, BU27008_MASK_SW_RESET);
770
+
if (ret)
771
+
return dev_err_probe(data->dev, ret, "Sensor reset failed\n");
772
+
773
+
/*
774
+
* The data-sheet does not tell how long performing the IC reset takes.
775
+
* However, the data-sheet says the minimum time it takes the IC to be
776
+
* able to take inputs after power is applied, is 100 uS. I'd assume
777
+
* > 1 mS is enough.
778
+
*/
779
+
msleep(1);
780
+
781
+
ret = regmap_reinit_cache(data->regmap, &bu27008_regmap);
782
+
if (ret)
783
+
dev_err(data->dev, "Failed to reinit reg cache\n");
784
+
785
+
return ret;
786
+
}
787
+
788
+
static int bu27008_set_drdy_irq(struct bu27008_data *data, int state)
789
+
{
790
+
return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL3,
791
+
BU27008_MASK_INT_EN, state);
792
+
}
793
+
794
+
static int bu27008_trigger_set_state(struct iio_trigger *trig,
795
+
bool state)
796
+
{
797
+
struct bu27008_data *data = iio_trigger_get_drvdata(trig);
798
+
int ret;
799
+
800
+
if (state)
801
+
ret = bu27008_set_drdy_irq(data, BU27008_INT_EN);
802
+
else
803
+
ret = bu27008_set_drdy_irq(data, BU27008_INT_DIS);
804
+
if (ret)
805
+
dev_err(data->dev, "Failed to set trigger state\n");
806
+
807
+
return ret;
808
+
}
809
+
810
+
static void bu27008_trigger_reenable(struct iio_trigger *trig)
811
+
{
812
+
struct bu27008_data *data = iio_trigger_get_drvdata(trig);
813
+
814
+
enable_irq(data->irq);
815
+
}
816
+
817
+
static const struct iio_trigger_ops bu27008_trigger_ops = {
818
+
.set_trigger_state = bu27008_trigger_set_state,
819
+
.reenable = bu27008_trigger_reenable,
820
+
};
821
+
822
+
static irqreturn_t bu27008_trigger_handler(int irq, void *p)
823
+
{
824
+
struct iio_poll_func *pf = p;
825
+
struct iio_dev *idev = pf->indio_dev;
826
+
struct bu27008_data *data = iio_priv(idev);
827
+
struct {
828
+
__le16 chan[BU27008_NUM_HW_CHANS];
829
+
s64 ts __aligned(8);
830
+
} raw;
831
+
int ret, dummy;
832
+
833
+
memset(&raw, 0, sizeof(raw));
834
+
835
+
/*
836
+
* After some measurements, it seems reading the
837
+
* BU27008_REG_MODE_CONTROL3 debounces the IRQ line
838
+
*/
839
+
ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL3, &dummy);
840
+
if (ret < 0)
841
+
goto err_read;
842
+
843
+
ret = regmap_bulk_read(data->regmap, BU27008_REG_DATA0_LO, &raw.chan,
844
+
sizeof(raw.chan));
845
+
if (ret < 0)
846
+
goto err_read;
847
+
848
+
iio_push_to_buffers_with_timestamp(idev, &raw, pf->timestamp);
849
+
err_read:
850
+
iio_trigger_notify_done(idev->trig);
851
+
852
+
return IRQ_HANDLED;
853
+
}
854
+
855
+
static int bu27008_buffer_preenable(struct iio_dev *idev)
856
+
{
857
+
struct bu27008_data *data = iio_priv(idev);
858
+
859
+
return bu27008_meas_set(data, BU27008_MEAS_EN);
860
+
}
861
+
862
+
static int bu27008_buffer_postdisable(struct iio_dev *idev)
863
+
{
864
+
struct bu27008_data *data = iio_priv(idev);
865
+
866
+
return bu27008_meas_set(data, BU27008_MEAS_DIS);
867
+
}
868
+
869
+
static const struct iio_buffer_setup_ops bu27008_buffer_ops = {
870
+
.preenable = bu27008_buffer_preenable,
871
+
.postdisable = bu27008_buffer_postdisable,
872
+
};
873
+
874
+
static irqreturn_t bu27008_data_rdy_poll(int irq, void *private)
875
+
{
876
+
/*
877
+
* The BU27008 keeps IRQ asserted until we read the VALID bit from
878
+
* a register. We need to keep the IRQ disabled until then.
879
+
*/
880
+
disable_irq_nosync(irq);
881
+
iio_trigger_poll(private);
882
+
883
+
return IRQ_HANDLED;
884
+
}
885
+
886
+
static int bu27008_setup_trigger(struct bu27008_data *data, struct iio_dev *idev)
887
+
{
888
+
struct iio_trigger *itrig;
889
+
char *name;
890
+
int ret;
891
+
892
+
ret = devm_iio_triggered_buffer_setup(data->dev, idev,
893
+
&iio_pollfunc_store_time,
894
+
bu27008_trigger_handler,
895
+
&bu27008_buffer_ops);
896
+
if (ret)
897
+
return dev_err_probe(data->dev, ret,
898
+
"iio_triggered_buffer_setup_ext FAIL\n");
899
+
900
+
itrig = devm_iio_trigger_alloc(data->dev, "%sdata-rdy-dev%d",
901
+
idev->name, iio_device_id(idev));
902
+
if (!itrig)
903
+
return -ENOMEM;
904
+
905
+
data->trig = itrig;
906
+
907
+
itrig->ops = &bu27008_trigger_ops;
908
+
iio_trigger_set_drvdata(itrig, data);
909
+
910
+
name = devm_kasprintf(data->dev, GFP_KERNEL, "%s-bu27008",
911
+
dev_name(data->dev));
912
+
913
+
ret = devm_request_irq(data->dev, data->irq,
914
+
&bu27008_data_rdy_poll,
915
+
0, name, itrig);
916
+
if (ret)
917
+
return dev_err_probe(data->dev, ret, "Could not request IRQ\n");
918
+
919
+
ret = devm_iio_trigger_register(data->dev, itrig);
920
+
if (ret)
921
+
return dev_err_probe(data->dev, ret,
922
+
"Trigger registration failed\n");
923
+
924
+
/* set default trigger */
925
+
idev->trig = iio_trigger_get(itrig);
926
+
927
+
return 0;
928
+
}
929
+
930
+
static int bu27008_probe(struct i2c_client *i2c)
931
+
{
932
+
struct device *dev = &i2c->dev;
933
+
struct bu27008_data *data;
934
+
struct regmap *regmap;
935
+
unsigned int part_id, reg;
936
+
struct iio_dev *idev;
937
+
int ret;
938
+
939
+
regmap = devm_regmap_init_i2c(i2c, &bu27008_regmap);
940
+
if (IS_ERR(regmap))
941
+
return dev_err_probe(dev, PTR_ERR(regmap),
942
+
"Failed to initialize Regmap\n");
943
+
944
+
idev = devm_iio_device_alloc(dev, sizeof(*data));
945
+
if (!idev)
946
+
return -ENOMEM;
947
+
948
+
ret = devm_regulator_get_enable(dev, "vdd");
949
+
if (ret)
950
+
return dev_err_probe(dev, ret, "Failed to get regulator\n");
951
+
952
+
data = iio_priv(idev);
953
+
954
+
ret = regmap_read(regmap, BU27008_REG_SYSTEM_CONTROL, ®);
955
+
if (ret)
956
+
return dev_err_probe(dev, ret, "Failed to access sensor\n");
957
+
958
+
part_id = FIELD_GET(BU27008_MASK_PART_ID, reg);
959
+
960
+
if (part_id != BU27008_ID)
961
+
dev_warn(dev, "unknown device 0x%x\n", part_id);
962
+
963
+
ret = devm_iio_init_iio_gts(dev, BU27008_SCALE_1X, 0, bu27008_gains,
964
+
ARRAY_SIZE(bu27008_gains), bu27008_itimes,
965
+
ARRAY_SIZE(bu27008_itimes), &data->gts);
966
+
if (ret)
967
+
return ret;
968
+
969
+
ret = devm_iio_init_iio_gts(dev, BU27008_SCALE_1X, 0, bu27008_gains_ir,
970
+
ARRAY_SIZE(bu27008_gains_ir), bu27008_itimes,
971
+
ARRAY_SIZE(bu27008_itimes), &data->gts_ir);
972
+
if (ret)
973
+
return ret;
974
+
975
+
mutex_init(&data->mutex);
976
+
data->regmap = regmap;
977
+
data->dev = dev;
978
+
data->irq = i2c->irq;
979
+
980
+
idev->channels = bu27008_channels;
981
+
idev->num_channels = ARRAY_SIZE(bu27008_channels);
982
+
idev->name = "bu27008";
983
+
idev->info = &bu27008_info;
984
+
idev->modes = INDIO_DIRECT_MODE;
985
+
idev->available_scan_masks = bu27008_scan_masks;
986
+
987
+
ret = bu27008_chip_init(data);
988
+
if (ret)
989
+
return ret;
990
+
991
+
if (i2c->irq) {
992
+
ret = bu27008_setup_trigger(data, idev);
993
+
if (ret)
994
+
return ret;
995
+
} else {
996
+
dev_info(dev, "No IRQ, buffered mode disabled\n");
997
+
}
998
+
999
+
ret = devm_iio_device_register(dev, idev);
1000
+
if (ret)
1001
+
return dev_err_probe(dev, ret,
1002
+
"Unable to register iio device\n");
1003
+
1004
+
return 0;
1005
+
}
1006
+
1007
+
static const struct of_device_id bu27008_of_match[] = {
1008
+
{ .compatible = "rohm,bu27008" },
1009
+
{ }
1010
+
};
1011
+
MODULE_DEVICE_TABLE(of, bu27008_of_match);
1012
+
1013
+
static struct i2c_driver bu27008_i2c_driver = {
1014
+
.driver = {
1015
+
.name = "bu27008",
1016
+
.of_match_table = bu27008_of_match,
1017
+
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
1018
+
},
1019
+
.probe = bu27008_probe,
1020
+
};
1021
+
module_i2c_driver(bu27008_i2c_driver);
1022
+
1023
+
MODULE_DESCRIPTION("ROHM BU27008 colour sensor driver");
1024
+
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
1025
+
MODULE_LICENSE("GPL");
1026
+
MODULE_IMPORT_NS(IIO_GTS_HELPER);
+2
-1
drivers/iio/light/rohm-bu27034.c
+2
-1
drivers/iio/light/rohm-bu27034.c
···
1500
1500
.driver = {
1501
1501
.name = "bu27034-als",
1502
1502
.of_match_table = bu27034_of_match,
1503
+
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
1503
1504
},
1504
-
.probe_new = bu27034_probe,
1505
+
.probe = bu27034_probe,
1505
1506
};
1506
1507
module_i2c_driver(bu27034_i2c_driver);
1507
1508
+1
-1
drivers/iio/light/rpr0521.c
+1
-1
drivers/iio/light/rpr0521.c
+1
-1
drivers/iio/light/si1133.c
+1
-1
drivers/iio/light/si1133.c
+1
-1
drivers/iio/light/si1145.c
+1
-1
drivers/iio/light/si1145.c
+1
-1
drivers/iio/light/st_uvis25_i2c.c
+1
-1
drivers/iio/light/st_uvis25_i2c.c
+1
-1
drivers/iio/light/stk3310.c
+1
-1
drivers/iio/light/stk3310.c
+1
-1
drivers/iio/light/tcs3414.c
+1
-1
drivers/iio/light/tcs3414.c
+1
-1
drivers/iio/light/tcs3472.c
+1
-1
drivers/iio/light/tcs3472.c
+1
-1
drivers/iio/light/tsl2563.c
+1
-1
drivers/iio/light/tsl2563.c
+1
-1
drivers/iio/light/tsl2583.c
+1
-1
drivers/iio/light/tsl2583.c
+1
-1
drivers/iio/light/tsl2591.c
+1
-1
drivers/iio/light/tsl2591.c
+1
-1
drivers/iio/light/tsl2772.c
+1
-1
drivers/iio/light/tsl2772.c
+1
-1
drivers/iio/light/tsl4531.c
+1
-1
drivers/iio/light/tsl4531.c
+1
-1
drivers/iio/light/us5182d.c
+1
-1
drivers/iio/light/us5182d.c
+1
-1
drivers/iio/light/vcnl4000.c
+1
-1
drivers/iio/light/vcnl4000.c
+1
-1
drivers/iio/light/vcnl4035.c
+1
-1
drivers/iio/light/vcnl4035.c
+1
-1
drivers/iio/light/veml6030.c
+1
-1
drivers/iio/light/veml6030.c
+1
-1
drivers/iio/light/veml6070.c
+1
-1
drivers/iio/light/veml6070.c
+1
-1
drivers/iio/light/vl6180.c
+1
-1
drivers/iio/light/vl6180.c
+1
-1
drivers/iio/light/zopt2201.c
+1
-1
drivers/iio/light/zopt2201.c
+1
-1
drivers/iio/magnetometer/ak8974.c
+1
-1
drivers/iio/magnetometer/ak8974.c
+1
-1
drivers/iio/magnetometer/ak8975.c
+1
-1
drivers/iio/magnetometer/ak8975.c
+1
-1
drivers/iio/magnetometer/bmc150_magn_i2c.c
+1
-1
drivers/iio/magnetometer/bmc150_magn_i2c.c
+1
-1
drivers/iio/magnetometer/hmc5843_i2c.c
+1
-1
drivers/iio/magnetometer/hmc5843_i2c.c
+1
-1
drivers/iio/magnetometer/mag3110.c
+1
-1
drivers/iio/magnetometer/mag3110.c
+1
-1
drivers/iio/magnetometer/mmc35240.c
+1
-1
drivers/iio/magnetometer/mmc35240.c
+1
-1
drivers/iio/magnetometer/rm3100-i2c.c
+1
-1
drivers/iio/magnetometer/rm3100-i2c.c
+1
drivers/iio/magnetometer/st_magn_core.c
+1
drivers/iio/magnetometer/st_magn_core.c
+1
-1
drivers/iio/magnetometer/st_magn_i2c.c
+1
-1
drivers/iio/magnetometer/st_magn_i2c.c
+1
-1
drivers/iio/magnetometer/tmag5273.c
+1
-1
drivers/iio/magnetometer/tmag5273.c
+1
-1
drivers/iio/magnetometer/yamaha-yas530.c
+1
-1
drivers/iio/magnetometer/yamaha-yas530.c
+10
drivers/iio/potentiometer/Kconfig
+10
drivers/iio/potentiometer/Kconfig
···
136
136
To compile this driver as a module, choose M here: the
137
137
module will be called tpl0102.
138
138
139
+
config X9250
140
+
tristate "Renesas X9250 quad controlled potentiometers"
141
+
depends on SPI
142
+
help
143
+
Enable support for the Renesas X9250 quad controlled
144
+
potentiometers.
145
+
146
+
To compile this driver as a module, choose M here: the module
147
+
will be called x9250.
148
+
139
149
endmenu
+1
drivers/iio/potentiometer/Makefile
+1
drivers/iio/potentiometer/Makefile
+1
-1
drivers/iio/potentiometer/ad5110.c
+1
-1
drivers/iio/potentiometer/ad5110.c
+1
-1
drivers/iio/potentiometer/ad5272.c
+1
-1
drivers/iio/potentiometer/ad5272.c
+1
-1
drivers/iio/potentiometer/ds1803.c
+1
-1
drivers/iio/potentiometer/ds1803.c
+1
-1
drivers/iio/potentiometer/max5432.c
+1
-1
drivers/iio/potentiometer/max5432.c
+1
-1
drivers/iio/potentiometer/mcp4018.c
+1
-1
drivers/iio/potentiometer/mcp4018.c
+1
-1
drivers/iio/potentiometer/mcp4531.c
+1
-1
drivers/iio/potentiometer/mcp4531.c
+1
-1
drivers/iio/potentiometer/tpl0102.c
+1
-1
drivers/iio/potentiometer/tpl0102.c
+220
drivers/iio/potentiometer/x9250.c
+220
drivers/iio/potentiometer/x9250.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
*
4
+
* x9250.c -- Renesas X9250 potentiometers IIO driver
5
+
*
6
+
* Copyright 2023 CS GROUP France
7
+
*
8
+
* Author: Herve Codina <herve.codina@bootlin.com>
9
+
*/
10
+
11
+
#include <linux/delay.h>
12
+
#include <linux/gpio/consumer.h>
13
+
#include <linux/iio/iio.h>
14
+
#include <linux/limits.h>
15
+
#include <linux/module.h>
16
+
#include <linux/regulator/consumer.h>
17
+
#include <linux/slab.h>
18
+
#include <linux/spi/spi.h>
19
+
20
+
struct x9250_cfg {
21
+
const char *name;
22
+
int kohms;
23
+
};
24
+
25
+
struct x9250 {
26
+
struct spi_device *spi;
27
+
const struct x9250_cfg *cfg;
28
+
struct gpio_desc *wp_gpio;
29
+
};
30
+
31
+
#define X9250_ID 0x50
32
+
#define X9250_CMD_RD_WCR(_p) (0x90 | (_p))
33
+
#define X9250_CMD_WR_WCR(_p) (0xa0 | (_p))
34
+
35
+
static int x9250_write8(struct x9250 *x9250, u8 cmd, u8 val)
36
+
{
37
+
u8 txbuf[3];
38
+
39
+
txbuf[0] = X9250_ID;
40
+
txbuf[1] = cmd;
41
+
txbuf[2] = val;
42
+
43
+
return spi_write_then_read(x9250->spi, txbuf, ARRAY_SIZE(txbuf), NULL, 0);
44
+
}
45
+
46
+
static int x9250_read8(struct x9250 *x9250, u8 cmd, u8 *val)
47
+
{
48
+
u8 txbuf[2];
49
+
50
+
txbuf[0] = X9250_ID;
51
+
txbuf[1] = cmd;
52
+
53
+
return spi_write_then_read(x9250->spi, txbuf, ARRAY_SIZE(txbuf), val, 1);
54
+
}
55
+
56
+
#define X9250_CHANNEL(ch) { \
57
+
.type = IIO_RESISTANCE, \
58
+
.indexed = 1, \
59
+
.output = 1, \
60
+
.channel = (ch), \
61
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
62
+
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
63
+
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_RAW), \
64
+
}
65
+
66
+
static const struct iio_chan_spec x9250_channels[] = {
67
+
X9250_CHANNEL(0),
68
+
X9250_CHANNEL(1),
69
+
X9250_CHANNEL(2),
70
+
X9250_CHANNEL(3),
71
+
};
72
+
73
+
static int x9250_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
74
+
int *val, int *val2, long mask)
75
+
{
76
+
struct x9250 *x9250 = iio_priv(indio_dev);
77
+
int ch = chan->channel;
78
+
int ret;
79
+
u8 v;
80
+
81
+
switch (mask) {
82
+
case IIO_CHAN_INFO_RAW:
83
+
ret = x9250_read8(x9250, X9250_CMD_RD_WCR(ch), &v);
84
+
if (ret)
85
+
return ret;
86
+
*val = v;
87
+
return IIO_VAL_INT;
88
+
89
+
case IIO_CHAN_INFO_SCALE:
90
+
*val = 1000 * x9250->cfg->kohms;
91
+
*val2 = U8_MAX;
92
+
return IIO_VAL_FRACTIONAL;
93
+
}
94
+
95
+
return -EINVAL;
96
+
}
97
+
98
+
static int x9250_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
99
+
const int **vals, int *type, int *length, long mask)
100
+
{
101
+
static const int range[] = {0, 1, 255}; /* min, step, max */
102
+
103
+
switch (mask) {
104
+
case IIO_CHAN_INFO_RAW:
105
+
*length = ARRAY_SIZE(range);
106
+
*vals = range;
107
+
*type = IIO_VAL_INT;
108
+
return IIO_AVAIL_RANGE;
109
+
}
110
+
111
+
return -EINVAL;
112
+
}
113
+
114
+
static int x9250_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
115
+
int val, int val2, long mask)
116
+
{
117
+
struct x9250 *x9250 = iio_priv(indio_dev);
118
+
int ch = chan->channel;
119
+
int ret;
120
+
121
+
if (mask != IIO_CHAN_INFO_RAW)
122
+
return -EINVAL;
123
+
124
+
if (val > U8_MAX || val < 0)
125
+
return -EINVAL;
126
+
127
+
gpiod_set_value_cansleep(x9250->wp_gpio, 0);
128
+
ret = x9250_write8(x9250, X9250_CMD_WR_WCR(ch), val);
129
+
gpiod_set_value_cansleep(x9250->wp_gpio, 1);
130
+
131
+
return ret;
132
+
}
133
+
134
+
static const struct iio_info x9250_info = {
135
+
.read_raw = x9250_read_raw,
136
+
.read_avail = x9250_read_avail,
137
+
.write_raw = x9250_write_raw,
138
+
};
139
+
140
+
enum x9250_type {
141
+
X9250T,
142
+
X9250U,
143
+
};
144
+
145
+
static const struct x9250_cfg x9250_cfg[] = {
146
+
[X9250T] = { .name = "x9250t", .kohms = 100, },
147
+
[X9250U] = { .name = "x9250u", .kohms = 50, },
148
+
};
149
+
150
+
static const char *const x9250_regulator_names[] = {
151
+
"vcc",
152
+
"avp",
153
+
"avn",
154
+
};
155
+
156
+
static int x9250_probe(struct spi_device *spi)
157
+
{
158
+
struct iio_dev *indio_dev;
159
+
struct x9250 *x9250;
160
+
int ret;
161
+
162
+
ret = devm_regulator_bulk_get_enable(&spi->dev, ARRAY_SIZE(x9250_regulator_names),
163
+
x9250_regulator_names);
164
+
if (ret)
165
+
return dev_err_probe(&spi->dev, ret, "Failed to get regulators\n");
166
+
167
+
/*
168
+
* The x9250 needs a 5ms maximum delay after the power-supplies are set
169
+
* before performing the first write (1ms for the first read).
170
+
*/
171
+
usleep_range(5000, 6000);
172
+
173
+
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*x9250));
174
+
if (!indio_dev)
175
+
return -ENOMEM;
176
+
177
+
x9250 = iio_priv(indio_dev);
178
+
x9250->spi = spi;
179
+
x9250->cfg = spi_get_device_match_data(spi);
180
+
x9250->wp_gpio = devm_gpiod_get_optional(&spi->dev, "wp", GPIOD_OUT_LOW);
181
+
if (IS_ERR(x9250->wp_gpio))
182
+
return dev_err_probe(&spi->dev, PTR_ERR(x9250->wp_gpio),
183
+
"failed to get wp gpio\n");
184
+
185
+
indio_dev->info = &x9250_info;
186
+
indio_dev->channels = x9250_channels;
187
+
indio_dev->num_channels = ARRAY_SIZE(x9250_channels);
188
+
indio_dev->name = x9250->cfg->name;
189
+
190
+
return devm_iio_device_register(&spi->dev, indio_dev);
191
+
}
192
+
193
+
static const struct of_device_id x9250_of_match[] = {
194
+
{ .compatible = "renesas,x9250t", .data = &x9250_cfg[X9250T]},
195
+
{ .compatible = "renesas,x9250u", .data = &x9250_cfg[X9250U]},
196
+
{ }
197
+
};
198
+
MODULE_DEVICE_TABLE(of, x9250_of_match);
199
+
200
+
static const struct spi_device_id x9250_id_table[] = {
201
+
{ "x9250t", (kernel_ulong_t)&x9250_cfg[X9250T] },
202
+
{ "x9250u", (kernel_ulong_t)&x9250_cfg[X9250U] },
203
+
{ }
204
+
};
205
+
MODULE_DEVICE_TABLE(spi, x9250_id_table);
206
+
207
+
static struct spi_driver x9250_spi_driver = {
208
+
.driver = {
209
+
.name = "x9250",
210
+
.of_match_table = x9250_of_match,
211
+
},
212
+
.id_table = x9250_id_table,
213
+
.probe = x9250_probe,
214
+
};
215
+
216
+
module_spi_driver(x9250_spi_driver);
217
+
218
+
MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
219
+
MODULE_DESCRIPTION("X9250 ALSA SoC driver");
220
+
MODULE_LICENSE("GPL");
+1
-1
drivers/iio/potentiostat/lmp91000.c
+1
-1
drivers/iio/potentiostat/lmp91000.c
+13
drivers/iio/pressure/Kconfig
+13
drivers/iio/pressure/Kconfig
···
148
148
To compile this driver as a module, choose M here: the module
149
149
will be called mpl3115.
150
150
151
+
config MPRLS0025PA
152
+
tristate "Honeywell MPRLS0025PA (MicroPressure sensors series)"
153
+
depends on I2C
154
+
select IIO_BUFFER
155
+
select IIO_TRIGGERED_BUFFER
156
+
help
157
+
Say Y here to build support for the Honeywell MicroPressure pressure
158
+
sensor series. There are many different types with different pressure
159
+
range. These ranges can be set up in the device tree.
160
+
161
+
To compile this driver as a module, choose M here: the module will be
162
+
called mprls0025pa.
163
+
151
164
config MS5611
152
165
tristate "Measurement Specialties MS5611 pressure sensor driver"
153
166
select IIO_BUFFER
+1
drivers/iio/pressure/Makefile
+1
drivers/iio/pressure/Makefile
···
19
19
obj-$(CONFIG_MPL115_I2C) += mpl115_i2c.o
20
20
obj-$(CONFIG_MPL115_SPI) += mpl115_spi.o
21
21
obj-$(CONFIG_MPL3115) += mpl3115.o
22
+
obj-$(CONFIG_MPRLS0025PA) += mprls0025pa.o
22
23
obj-$(CONFIG_MS5611) += ms5611_core.o
23
24
obj-$(CONFIG_MS5611_I2C) += ms5611_i2c.o
24
25
obj-$(CONFIG_MS5611_SPI) += ms5611_spi.o
+1
-1
drivers/iio/pressure/abp060mg.c
+1
-1
drivers/iio/pressure/abp060mg.c
+1
-1
drivers/iio/pressure/bmp280-i2c.c
+1
-1
drivers/iio/pressure/bmp280-i2c.c
+1
-1
drivers/iio/pressure/dlhl60d.c
+1
-1
drivers/iio/pressure/dlhl60d.c
+1
-1
drivers/iio/pressure/dps310.c
+1
-1
drivers/iio/pressure/dps310.c
+1
-1
drivers/iio/pressure/hp03.c
+1
-1
drivers/iio/pressure/hp03.c
+1
-1
drivers/iio/pressure/hp206c.c
+1
-1
drivers/iio/pressure/hp206c.c
+1
-1
drivers/iio/pressure/icp10100.c
+1
-1
drivers/iio/pressure/icp10100.c
+1
-1
drivers/iio/pressure/mpl115_i2c.c
+1
-1
drivers/iio/pressure/mpl115_i2c.c
+1
-1
drivers/iio/pressure/mpl3115.c
+1
-1
drivers/iio/pressure/mpl3115.c
+450
drivers/iio/pressure/mprls0025pa.c
+450
drivers/iio/pressure/mprls0025pa.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* MPRLS0025PA - Honeywell MicroPressure pressure sensor series driver
4
+
*
5
+
* Copyright (c) Andreas Klinger <ak@it-klinger.de>
6
+
*
7
+
* Data sheet:
8
+
* https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/
9
+
* products/sensors/pressure-sensors/board-mount-pressure-sensors/
10
+
* micropressure-mpr-series/documents/
11
+
* sps-siot-mpr-series-datasheet-32332628-ciid-172626.pdf
12
+
*
13
+
* 7-bit I2C default slave address: 0x18
14
+
*/
15
+
16
+
#include <linux/delay.h>
17
+
#include <linux/device.h>
18
+
#include <linux/i2c.h>
19
+
#include <linux/math64.h>
20
+
#include <linux/mod_devicetable.h>
21
+
#include <linux/module.h>
22
+
#include <linux/property.h>
23
+
#include <linux/units.h>
24
+
25
+
#include <linux/gpio/consumer.h>
26
+
27
+
#include <linux/iio/buffer.h>
28
+
#include <linux/iio/iio.h>
29
+
#include <linux/iio/trigger_consumer.h>
30
+
#include <linux/iio/triggered_buffer.h>
31
+
32
+
#include <linux/regulator/consumer.h>
33
+
34
+
#include <asm/unaligned.h>
35
+
36
+
/* bits in i2c status byte */
37
+
#define MPR_I2C_POWER BIT(6) /* device is powered */
38
+
#define MPR_I2C_BUSY BIT(5) /* device is busy */
39
+
#define MPR_I2C_MEMORY BIT(2) /* integrity test passed */
40
+
#define MPR_I2C_MATH BIT(0) /* internal math saturation */
41
+
42
+
/*
43
+
* support _RAW sysfs interface:
44
+
*
45
+
* Calculation formula from the datasheet:
46
+
* pressure = (press_cnt - outputmin) * scale + pmin
47
+
* with:
48
+
* * pressure - measured pressure in Pascal
49
+
* * press_cnt - raw value read from sensor
50
+
* * pmin - minimum pressure range value of sensor (data->pmin)
51
+
* * pmax - maximum pressure range value of sensor (data->pmax)
52
+
* * outputmin - minimum numerical range raw value delivered by sensor
53
+
* (mpr_func_spec.output_min)
54
+
* * outputmax - maximum numerical range raw value delivered by sensor
55
+
* (mpr_func_spec.output_max)
56
+
* * scale - (pmax - pmin) / (outputmax - outputmin)
57
+
*
58
+
* formula of the userspace:
59
+
* pressure = (raw + offset) * scale
60
+
*
61
+
* Values given to the userspace in sysfs interface:
62
+
* * raw - press_cnt
63
+
* * offset - (-1 * outputmin) - pmin / scale
64
+
* note: With all sensors from the datasheet pmin = 0
65
+
* which reduces the offset to (-1 * outputmin)
66
+
*/
67
+
68
+
/*
69
+
* transfer function A: 10% to 90% of 2^24
70
+
* transfer function B: 2.5% to 22.5% of 2^24
71
+
* transfer function C: 20% to 80% of 2^24
72
+
*/
73
+
enum mpr_func_id {
74
+
MPR_FUNCTION_A,
75
+
MPR_FUNCTION_B,
76
+
MPR_FUNCTION_C,
77
+
};
78
+
79
+
struct mpr_func_spec {
80
+
u32 output_min;
81
+
u32 output_max;
82
+
};
83
+
84
+
static const struct mpr_func_spec mpr_func_spec[] = {
85
+
[MPR_FUNCTION_A] = {.output_min = 1677722, .output_max = 15099494},
86
+
[MPR_FUNCTION_B] = {.output_min = 419430, .output_max = 3774874},
87
+
[MPR_FUNCTION_C] = {.output_min = 3355443, .output_max = 13421773},
88
+
};
89
+
90
+
struct mpr_chan {
91
+
s32 pres; /* pressure value */
92
+
s64 ts; /* timestamp */
93
+
};
94
+
95
+
struct mpr_data {
96
+
struct i2c_client *client;
97
+
struct mutex lock; /*
98
+
* access to device during read
99
+
*/
100
+
u32 pmin; /* minimal pressure in pascal */
101
+
u32 pmax; /* maximal pressure in pascal */
102
+
enum mpr_func_id function; /* transfer function */
103
+
u32 outmin; /*
104
+
* minimal numerical range raw
105
+
* value from sensor
106
+
*/
107
+
u32 outmax; /*
108
+
* maximal numerical range raw
109
+
* value from sensor
110
+
*/
111
+
int scale; /* int part of scale */
112
+
int scale2; /* nano part of scale */
113
+
int offset; /* int part of offset */
114
+
int offset2; /* nano part of offset */
115
+
struct gpio_desc *gpiod_reset; /* reset */
116
+
int irq; /*
117
+
* end of conversion irq;
118
+
* used to distinguish between
119
+
* irq mode and reading in a
120
+
* loop until data is ready
121
+
*/
122
+
struct completion completion; /* handshake from irq to read */
123
+
struct mpr_chan chan; /*
124
+
* channel values for buffered
125
+
* mode
126
+
*/
127
+
};
128
+
129
+
static const struct iio_chan_spec mpr_channels[] = {
130
+
{
131
+
.type = IIO_PRESSURE,
132
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
133
+
BIT(IIO_CHAN_INFO_SCALE) |
134
+
BIT(IIO_CHAN_INFO_OFFSET),
135
+
.scan_index = 0,
136
+
.scan_type = {
137
+
.sign = 's',
138
+
.realbits = 32,
139
+
.storagebits = 32,
140
+
.endianness = IIO_CPU,
141
+
},
142
+
},
143
+
IIO_CHAN_SOFT_TIMESTAMP(1),
144
+
};
145
+
146
+
static void mpr_reset(struct mpr_data *data)
147
+
{
148
+
if (data->gpiod_reset) {
149
+
gpiod_set_value(data->gpiod_reset, 0);
150
+
udelay(10);
151
+
gpiod_set_value(data->gpiod_reset, 1);
152
+
}
153
+
}
154
+
155
+
/**
156
+
* mpr_read_pressure() - Read pressure value from sensor via I2C
157
+
* @data: Pointer to private data struct.
158
+
* @press: Output value read from sensor.
159
+
*
160
+
* Reading from the sensor by sending and receiving I2C telegrams.
161
+
*
162
+
* If there is an end of conversion (EOC) interrupt registered the function
163
+
* waits for a maximum of one second for the interrupt.
164
+
*
165
+
* Context: The function can sleep and data->lock should be held when calling it
166
+
* Return:
167
+
* * 0 - OK, the pressure value could be read
168
+
* * -ETIMEDOUT - Timeout while waiting for the EOC interrupt or busy flag is
169
+
* still set after nloops attempts of reading
170
+
*/
171
+
static int mpr_read_pressure(struct mpr_data *data, s32 *press)
172
+
{
173
+
struct device *dev = &data->client->dev;
174
+
int ret, i;
175
+
u8 wdata[] = {0xAA, 0x00, 0x00};
176
+
s32 status;
177
+
int nloops = 10;
178
+
u8 buf[4];
179
+
180
+
reinit_completion(&data->completion);
181
+
182
+
ret = i2c_master_send(data->client, wdata, sizeof(wdata));
183
+
if (ret < 0) {
184
+
dev_err(dev, "error while writing ret: %d\n", ret);
185
+
return ret;
186
+
}
187
+
if (ret != sizeof(wdata)) {
188
+
dev_err(dev, "received size doesn't fit - ret: %d / %u\n", ret,
189
+
(u32)sizeof(wdata));
190
+
return -EIO;
191
+
}
192
+
193
+
if (data->irq > 0) {
194
+
ret = wait_for_completion_timeout(&data->completion, HZ);
195
+
if (!ret) {
196
+
dev_err(dev, "timeout while waiting for eoc irq\n");
197
+
return -ETIMEDOUT;
198
+
}
199
+
} else {
200
+
/* wait until status indicates data is ready */
201
+
for (i = 0; i < nloops; i++) {
202
+
/*
203
+
* datasheet only says to wait at least 5 ms for the
204
+
* data but leave the maximum response time open
205
+
* --> let's try it nloops (10) times which seems to be
206
+
* quite long
207
+
*/
208
+
usleep_range(5000, 10000);
209
+
status = i2c_smbus_read_byte(data->client);
210
+
if (status < 0) {
211
+
dev_err(dev,
212
+
"error while reading, status: %d\n",
213
+
status);
214
+
return status;
215
+
}
216
+
if (!(status & MPR_I2C_BUSY))
217
+
break;
218
+
}
219
+
if (i == nloops) {
220
+
dev_err(dev, "timeout while reading\n");
221
+
return -ETIMEDOUT;
222
+
}
223
+
}
224
+
225
+
ret = i2c_master_recv(data->client, buf, sizeof(buf));
226
+
if (ret < 0) {
227
+
dev_err(dev, "error in i2c_master_recv ret: %d\n", ret);
228
+
return ret;
229
+
}
230
+
if (ret != sizeof(buf)) {
231
+
dev_err(dev, "received size doesn't fit - ret: %d / %u\n", ret,
232
+
(u32)sizeof(buf));
233
+
return -EIO;
234
+
}
235
+
236
+
if (buf[0] & MPR_I2C_BUSY) {
237
+
/*
238
+
* it should never be the case that status still indicates
239
+
* business
240
+
*/
241
+
dev_err(dev, "data still not ready: %08x\n", buf[0]);
242
+
return -ETIMEDOUT;
243
+
}
244
+
245
+
*press = get_unaligned_be24(&buf[1]);
246
+
247
+
dev_dbg(dev, "received: %*ph cnt: %d\n", ret, buf, *press);
248
+
249
+
return 0;
250
+
}
251
+
252
+
static irqreturn_t mpr_eoc_handler(int irq, void *p)
253
+
{
254
+
struct mpr_data *data = p;
255
+
256
+
complete(&data->completion);
257
+
258
+
return IRQ_HANDLED;
259
+
}
260
+
261
+
static irqreturn_t mpr_trigger_handler(int irq, void *p)
262
+
{
263
+
int ret;
264
+
struct iio_poll_func *pf = p;
265
+
struct iio_dev *indio_dev = pf->indio_dev;
266
+
struct mpr_data *data = iio_priv(indio_dev);
267
+
268
+
mutex_lock(&data->lock);
269
+
ret = mpr_read_pressure(data, &data->chan.pres);
270
+
if (ret < 0)
271
+
goto err;
272
+
273
+
iio_push_to_buffers_with_timestamp(indio_dev, &data->chan,
274
+
iio_get_time_ns(indio_dev));
275
+
276
+
err:
277
+
mutex_unlock(&data->lock);
278
+
iio_trigger_notify_done(indio_dev->trig);
279
+
280
+
return IRQ_HANDLED;
281
+
}
282
+
283
+
static int mpr_read_raw(struct iio_dev *indio_dev,
284
+
struct iio_chan_spec const *chan, int *val, int *val2, long mask)
285
+
{
286
+
int ret;
287
+
s32 pressure;
288
+
struct mpr_data *data = iio_priv(indio_dev);
289
+
290
+
if (chan->type != IIO_PRESSURE)
291
+
return -EINVAL;
292
+
293
+
switch (mask) {
294
+
case IIO_CHAN_INFO_RAW:
295
+
mutex_lock(&data->lock);
296
+
ret = mpr_read_pressure(data, &pressure);
297
+
mutex_unlock(&data->lock);
298
+
if (ret < 0)
299
+
return ret;
300
+
*val = pressure;
301
+
return IIO_VAL_INT;
302
+
case IIO_CHAN_INFO_SCALE:
303
+
*val = data->scale;
304
+
*val2 = data->scale2;
305
+
return IIO_VAL_INT_PLUS_NANO;
306
+
case IIO_CHAN_INFO_OFFSET:
307
+
*val = data->offset;
308
+
*val2 = data->offset2;
309
+
return IIO_VAL_INT_PLUS_NANO;
310
+
default:
311
+
return -EINVAL;
312
+
}
313
+
}
314
+
315
+
static const struct iio_info mpr_info = {
316
+
.read_raw = &mpr_read_raw,
317
+
};
318
+
319
+
static int mpr_probe(struct i2c_client *client)
320
+
{
321
+
int ret;
322
+
struct mpr_data *data;
323
+
struct iio_dev *indio_dev;
324
+
struct device *dev = &client->dev;
325
+
s64 scale, offset;
326
+
327
+
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_BYTE))
328
+
return dev_err_probe(dev, -EOPNOTSUPP,
329
+
"I2C functionality not supported\n");
330
+
331
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
332
+
if (!indio_dev)
333
+
return dev_err_probe(dev, -ENOMEM, "couldn't get iio_dev\n");
334
+
335
+
data = iio_priv(indio_dev);
336
+
data->client = client;
337
+
data->irq = client->irq;
338
+
339
+
mutex_init(&data->lock);
340
+
init_completion(&data->completion);
341
+
342
+
indio_dev->name = "mprls0025pa";
343
+
indio_dev->info = &mpr_info;
344
+
indio_dev->channels = mpr_channels;
345
+
indio_dev->num_channels = ARRAY_SIZE(mpr_channels);
346
+
indio_dev->modes = INDIO_DIRECT_MODE;
347
+
348
+
ret = devm_regulator_get_enable(dev, "vdd");
349
+
if (ret)
350
+
return dev_err_probe(dev, ret,
351
+
"can't get and enable vdd supply\n");
352
+
353
+
if (dev_fwnode(dev)) {
354
+
ret = device_property_read_u32(dev, "honeywell,pmin-pascal",
355
+
&data->pmin);
356
+
if (ret)
357
+
return dev_err_probe(dev, ret,
358
+
"honeywell,pmin-pascal could not be read\n");
359
+
ret = device_property_read_u32(dev, "honeywell,pmax-pascal",
360
+
&data->pmax);
361
+
if (ret)
362
+
return dev_err_probe(dev, ret,
363
+
"honeywell,pmax-pascal could not be read\n");
364
+
ret = device_property_read_u32(dev,
365
+
"honeywell,transfer-function", &data->function);
366
+
if (ret)
367
+
return dev_err_probe(dev, ret,
368
+
"honeywell,transfer-function could not be read\n");
369
+
if (data->function > MPR_FUNCTION_C)
370
+
return dev_err_probe(dev, -EINVAL,
371
+
"honeywell,transfer-function %d invalid\n",
372
+
data->function);
373
+
} else {
374
+
/* when loaded as i2c device we need to use default values */
375
+
dev_notice(dev, "firmware node not found; using defaults\n");
376
+
data->pmin = 0;
377
+
data->pmax = 172369; /* 25 psi */
378
+
data->function = MPR_FUNCTION_A;
379
+
}
380
+
381
+
data->outmin = mpr_func_spec[data->function].output_min;
382
+
data->outmax = mpr_func_spec[data->function].output_max;
383
+
384
+
/* use 64 bit calculation for preserving a reasonable precision */
385
+
scale = div_s64(((s64)(data->pmax - data->pmin)) * NANO,
386
+
data->outmax - data->outmin);
387
+
data->scale = div_s64_rem(scale, NANO, &data->scale2);
388
+
/*
389
+
* multiply with NANO before dividing by scale and later divide by NANO
390
+
* again.
391
+
*/
392
+
offset = ((-1LL) * (s64)data->outmin) * NANO -
393
+
div_s64(div_s64((s64)data->pmin * NANO, scale), NANO);
394
+
data->offset = div_s64_rem(offset, NANO, &data->offset2);
395
+
396
+
if (data->irq > 0) {
397
+
ret = devm_request_irq(dev, data->irq, mpr_eoc_handler,
398
+
IRQF_TRIGGER_RISING, client->name, data);
399
+
if (ret)
400
+
return dev_err_probe(dev, ret,
401
+
"request irq %d failed\n", data->irq);
402
+
}
403
+
404
+
data->gpiod_reset = devm_gpiod_get_optional(dev, "reset",
405
+
GPIOD_OUT_HIGH);
406
+
if (IS_ERR(data->gpiod_reset))
407
+
return dev_err_probe(dev, PTR_ERR(data->gpiod_reset),
408
+
"request reset-gpio failed\n");
409
+
410
+
mpr_reset(data);
411
+
412
+
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
413
+
mpr_trigger_handler, NULL);
414
+
if (ret)
415
+
return dev_err_probe(dev, ret,
416
+
"iio triggered buffer setup failed\n");
417
+
418
+
ret = devm_iio_device_register(dev, indio_dev);
419
+
if (ret)
420
+
return dev_err_probe(dev, ret,
421
+
"unable to register iio device\n");
422
+
423
+
return 0;
424
+
}
425
+
426
+
static const struct of_device_id mpr_matches[] = {
427
+
{ .compatible = "honeywell,mprls0025pa" },
428
+
{ }
429
+
};
430
+
MODULE_DEVICE_TABLE(of, mpr_matches);
431
+
432
+
static const struct i2c_device_id mpr_id[] = {
433
+
{ "mprls0025pa" },
434
+
{ }
435
+
};
436
+
MODULE_DEVICE_TABLE(i2c, mpr_id);
437
+
438
+
static struct i2c_driver mpr_driver = {
439
+
.probe = mpr_probe,
440
+
.id_table = mpr_id,
441
+
.driver = {
442
+
.name = "mprls0025pa",
443
+
.of_match_table = mpr_matches,
444
+
},
445
+
};
446
+
module_i2c_driver(mpr_driver);
447
+
448
+
MODULE_AUTHOR("Andreas Klinger <ak@it-klinger.de>");
449
+
MODULE_DESCRIPTION("Honeywell MPRLS0025PA I2C driver");
450
+
MODULE_LICENSE("GPL");
+1
-1
drivers/iio/pressure/ms5611_i2c.c
+1
-1
drivers/iio/pressure/ms5611_i2c.c
+1
-1
drivers/iio/pressure/ms5637.c
+1
-1
drivers/iio/pressure/ms5637.c
+1
-1
drivers/iio/pressure/st_pressure_i2c.c
+1
-1
drivers/iio/pressure/st_pressure_i2c.c
+1
-1
drivers/iio/pressure/t5403.c
+1
-1
drivers/iio/pressure/t5403.c
+1
-1
drivers/iio/pressure/zpa2326_i2c.c
+1
-1
drivers/iio/pressure/zpa2326_i2c.c
+1
-1
drivers/iio/proximity/isl29501.c
+1
-1
drivers/iio/proximity/isl29501.c
+1
-1
drivers/iio/proximity/mb1232.c
+1
-1
drivers/iio/proximity/mb1232.c
+1
-1
drivers/iio/proximity/pulsedlight-lidar-lite-v2.c
+1
-1
drivers/iio/proximity/pulsedlight-lidar-lite-v2.c
+1
-1
drivers/iio/proximity/rfd77402.c
+1
-1
drivers/iio/proximity/rfd77402.c
+1
-1
drivers/iio/proximity/srf08.c
+1
-1
drivers/iio/proximity/srf08.c
+1
-1
drivers/iio/proximity/sx9310.c
+1
-1
drivers/iio/proximity/sx9310.c
+1
-1
drivers/iio/proximity/sx9324.c
+1
-1
drivers/iio/proximity/sx9324.c
+1
-1
drivers/iio/proximity/sx9360.c
+1
-1
drivers/iio/proximity/sx9360.c
+1
-1
drivers/iio/proximity/sx9500.c
+1
-1
drivers/iio/proximity/sx9500.c
+1
-1
drivers/iio/proximity/vcnl3020.c
+1
-1
drivers/iio/proximity/vcnl3020.c
+1
-1
drivers/iio/proximity/vl53l0x-i2c.c
+1
-1
drivers/iio/proximity/vl53l0x-i2c.c
+1
-1
drivers/iio/temperature/max30208.c
+1
-1
drivers/iio/temperature/max30208.c
+170
-71
drivers/iio/temperature/mlx90614.c
+170
-71
drivers/iio/temperature/mlx90614.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* mlx90614.c - Support for Melexis MLX90614 contactless IR temperature sensor
3
+
* mlx90614.c - Support for Melexis MLX90614/MLX90615 contactless IR temperature sensor
4
4
*
5
5
* Copyright (c) 2014 Peter Meerwald <pmeerw@pmeerw.net>
6
6
* Copyright (c) 2015 Essensium NV
7
7
* Copyright (c) 2015 Melexis
8
8
*
9
-
* Driver for the Melexis MLX90614 I2C 16-bit IR thermopile sensor
9
+
* Driver for the Melexis MLX90614/MLX90615 I2C 16-bit IR thermopile sensor
10
+
*
11
+
* MLX90614 - 17-bit ADC + MLX90302 DSP
12
+
* MLX90615 - 16-bit ADC + MLX90325 DSP
10
13
*
11
14
* (7-bit I2C slave address 0x5a, 100KHz bus speed only!)
12
15
*
···
22
19
* the "wakeup" GPIO is not given, power management will be disabled.
23
20
*/
24
21
25
-
#include <linux/err.h>
26
-
#include <linux/i2c.h>
27
-
#include <linux/module.h>
28
22
#include <linux/delay.h>
29
-
#include <linux/jiffies.h>
23
+
#include <linux/err.h>
30
24
#include <linux/gpio/consumer.h>
25
+
#include <linux/i2c.h>
26
+
#include <linux/jiffies.h>
27
+
#include <linux/module.h>
28
+
#include <linux/of_device.h>
31
29
#include <linux/pm_runtime.h>
32
30
33
31
#include <linux/iio/iio.h>
···
38
34
#define MLX90614_OP_EEPROM 0x20
39
35
#define MLX90614_OP_SLEEP 0xff
40
36
41
-
/* RAM offsets with 16-bit data, MSB first */
42
-
#define MLX90614_RAW1 (MLX90614_OP_RAM | 0x04) /* raw data IR channel 1 */
43
-
#define MLX90614_RAW2 (MLX90614_OP_RAM | 0x05) /* raw data IR channel 2 */
44
-
#define MLX90614_TA (MLX90614_OP_RAM | 0x06) /* ambient temperature */
45
-
#define MLX90614_TOBJ1 (MLX90614_OP_RAM | 0x07) /* object 1 temperature */
46
-
#define MLX90614_TOBJ2 (MLX90614_OP_RAM | 0x08) /* object 2 temperature */
47
-
48
-
/* EEPROM offsets with 16-bit data, MSB first */
49
-
#define MLX90614_EMISSIVITY (MLX90614_OP_EEPROM | 0x04) /* emissivity correction coefficient */
50
-
#define MLX90614_CONFIG (MLX90614_OP_EEPROM | 0x05) /* configuration register */
37
+
#define MLX90615_OP_EEPROM 0x10
38
+
#define MLX90615_OP_RAM 0x20
39
+
#define MLX90615_OP_SLEEP 0xc6
51
40
52
41
/* Control bits in configuration register */
53
42
#define MLX90614_CONFIG_IIR_SHIFT 0 /* IIR coefficient */
···
49
52
#define MLX90614_CONFIG_DUAL_MASK (1 << MLX90614_CONFIG_DUAL_SHIFT)
50
53
#define MLX90614_CONFIG_FIR_SHIFT 8 /* FIR coefficient */
51
54
#define MLX90614_CONFIG_FIR_MASK (0x7 << MLX90614_CONFIG_FIR_SHIFT)
52
-
#define MLX90614_CONFIG_GAIN_SHIFT 11 /* gain */
53
-
#define MLX90614_CONFIG_GAIN_MASK (0x7 << MLX90614_CONFIG_GAIN_SHIFT)
55
+
56
+
#define MLX90615_CONFIG_IIR_SHIFT 12 /* IIR coefficient */
57
+
#define MLX90615_CONFIG_IIR_MASK (0x7 << MLX90615_CONFIG_IIR_SHIFT)
54
58
55
59
/* Timings (in ms) */
56
60
#define MLX90614_TIMING_EEPROM 20 /* time for EEPROM write/erase to complete */
57
61
#define MLX90614_TIMING_WAKEUP 34 /* time to hold SDA low for wake-up */
58
62
#define MLX90614_TIMING_STARTUP 250 /* time before first data after wake-up */
63
+
64
+
#define MLX90615_TIMING_WAKEUP 22 /* time to hold SCL low for wake-up */
59
65
60
66
#define MLX90614_AUTOSLEEP_DELAY 5000 /* default autosleep delay */
61
67
···
66
66
#define MLX90614_CONST_OFFSET_DEC -13657 /* decimal part of the Kelvin offset */
67
67
#define MLX90614_CONST_OFFSET_REM 500000 /* remainder of offset (273.15*50) */
68
68
#define MLX90614_CONST_SCALE 20 /* Scale in milliKelvin (0.02 * 1000) */
69
-
#define MLX90614_CONST_RAW_EMISSIVITY_MAX 65535 /* max value for emissivity */
70
-
#define MLX90614_CONST_EMISSIVITY_RESOLUTION 15259 /* 1/65535 ~ 0.000015259 */
71
69
#define MLX90614_CONST_FIR 0x7 /* Fixed value for FIR part of low pass filter */
70
+
71
+
/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
72
+
#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
73
+
#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
74
+
75
+
struct mlx_chip_info {
76
+
/* EEPROM offsets with 16-bit data, MSB first */
77
+
/* emissivity correction coefficient */
78
+
u8 op_eeprom_emissivity;
79
+
u8 op_eeprom_config1;
80
+
/* RAM offsets with 16-bit data, MSB first */
81
+
/* ambient temperature */
82
+
u8 op_ram_ta;
83
+
/* object 1 temperature */
84
+
u8 op_ram_tobj1;
85
+
/* object 2 temperature */
86
+
u8 op_ram_tobj2;
87
+
u8 op_sleep;
88
+
/* support for two input channels (MLX90614 only) */
89
+
u8 dual_channel;
90
+
u8 wakeup_delay_ms;
91
+
u16 emissivity_max;
92
+
u16 fir_config_mask;
93
+
u16 iir_config_mask;
94
+
int iir_valid_offset;
95
+
u16 iir_values[8];
96
+
int iir_freqs[8][2];
97
+
};
72
98
73
99
struct mlx90614_data {
74
100
struct i2c_client *client;
75
101
struct mutex lock; /* for EEPROM access only */
76
102
struct gpio_desc *wakeup_gpio; /* NULL to disable sleep/wake-up */
103
+
const struct mlx_chip_info *chip_info; /* Chip hardware details */
77
104
unsigned long ready_timestamp; /* in jiffies */
78
-
};
79
-
80
-
/* Bandwidth values for IIR filtering */
81
-
static const int mlx90614_iir_values[] = {77, 31, 20, 15, 723, 153, 110, 86};
82
-
static const int mlx90614_freqs[][2] = {
83
-
{0, 150000},
84
-
{0, 200000},
85
-
{0, 310000},
86
-
{0, 770000},
87
-
{0, 860000},
88
-
{1, 100000},
89
-
{1, 530000},
90
-
{7, 230000}
91
105
};
92
106
93
107
/*
···
143
129
}
144
130
145
131
/*
146
-
* Find the IIR value inside mlx90614_iir_values array and return its position
132
+
* Find the IIR value inside iir_values array and return its position
147
133
* which is equivalent to the bit value in sensor register
148
134
*/
149
135
static inline s32 mlx90614_iir_search(const struct i2c_client *client,
150
136
int value)
151
137
{
138
+
struct iio_dev *indio_dev = i2c_get_clientdata(client);
139
+
struct mlx90614_data *data = iio_priv(indio_dev);
140
+
const struct mlx_chip_info *chip_info = data->chip_info;
152
141
int i;
153
142
s32 ret;
154
143
155
-
for (i = 0; i < ARRAY_SIZE(mlx90614_iir_values); ++i) {
156
-
if (value == mlx90614_iir_values[i])
144
+
for (i = chip_info->iir_valid_offset;
145
+
i < ARRAY_SIZE(chip_info->iir_values);
146
+
i++) {
147
+
if (value == chip_info->iir_values[i])
157
148
break;
158
149
}
159
150
160
-
if (i == ARRAY_SIZE(mlx90614_iir_values))
151
+
if (i == ARRAY_SIZE(chip_info->iir_values))
161
152
return -EINVAL;
162
153
163
154
/*
···
170
151
* we must read them before we actually write
171
152
* changes
172
153
*/
173
-
ret = i2c_smbus_read_word_data(client, MLX90614_CONFIG);
154
+
ret = i2c_smbus_read_word_data(client, chip_info->op_eeprom_config1);
174
155
if (ret < 0)
175
156
return ret;
176
157
177
-
ret &= ~MLX90614_CONFIG_FIR_MASK;
178
-
ret |= MLX90614_CONST_FIR << MLX90614_CONFIG_FIR_SHIFT;
179
-
ret &= ~MLX90614_CONFIG_IIR_MASK;
180
-
ret |= i << MLX90614_CONFIG_IIR_SHIFT;
158
+
/* Modify FIR on parts which have configurable FIR filter */
159
+
if (chip_info->fir_config_mask) {
160
+
ret &= ~chip_info->fir_config_mask;
161
+
ret |= field_prep(chip_info->fir_config_mask, MLX90614_CONST_FIR);
162
+
}
163
+
164
+
ret &= ~chip_info->iir_config_mask;
165
+
ret |= field_prep(chip_info->iir_config_mask, i);
181
166
182
167
/* Write changed values */
183
-
ret = mlx90614_write_word(client, MLX90614_CONFIG, ret);
168
+
ret = mlx90614_write_word(client, chip_info->op_eeprom_config1, ret);
184
169
return ret;
185
170
}
186
171
···
244
221
int *val2, long mask)
245
222
{
246
223
struct mlx90614_data *data = iio_priv(indio_dev);
247
-
u8 cmd;
224
+
const struct mlx_chip_info *chip_info = data->chip_info;
225
+
u8 cmd, idx;
248
226
s32 ret;
249
227
250
228
switch (mask) {
251
229
case IIO_CHAN_INFO_RAW: /* 0.02K / LSB */
252
230
switch (channel->channel2) {
253
231
case IIO_MOD_TEMP_AMBIENT:
254
-
cmd = MLX90614_TA;
232
+
cmd = chip_info->op_ram_ta;
255
233
break;
256
234
case IIO_MOD_TEMP_OBJECT:
235
+
if (chip_info->dual_channel && channel->channel)
236
+
return -EINVAL;
237
+
257
238
switch (channel->channel) {
258
239
case 0:
259
-
cmd = MLX90614_TOBJ1;
240
+
cmd = chip_info->op_ram_tobj1;
260
241
break;
261
242
case 1:
262
-
cmd = MLX90614_TOBJ2;
243
+
cmd = chip_info->op_ram_tobj2;
263
244
break;
264
245
default:
265
246
return -EINVAL;
···
295
268
case IIO_CHAN_INFO_SCALE:
296
269
*val = MLX90614_CONST_SCALE;
297
270
return IIO_VAL_INT;
298
-
case IIO_CHAN_INFO_CALIBEMISSIVITY: /* 1/65535 / LSB */
271
+
case IIO_CHAN_INFO_CALIBEMISSIVITY: /* 1/emissivity_max / LSB */
299
272
ret = mlx90614_power_get(data, false);
300
273
if (ret < 0)
301
274
return ret;
302
275
303
276
mutex_lock(&data->lock);
304
277
ret = i2c_smbus_read_word_data(data->client,
305
-
MLX90614_EMISSIVITY);
278
+
chip_info->op_eeprom_emissivity);
306
279
mutex_unlock(&data->lock);
307
280
mlx90614_power_put(data);
308
281
309
282
if (ret < 0)
310
283
return ret;
311
284
312
-
if (ret == MLX90614_CONST_RAW_EMISSIVITY_MAX) {
285
+
if (ret == chip_info->emissivity_max) {
313
286
*val = 1;
314
287
*val2 = 0;
315
288
} else {
316
289
*val = 0;
317
-
*val2 = ret * MLX90614_CONST_EMISSIVITY_RESOLUTION;
290
+
*val2 = ret * NSEC_PER_SEC / chip_info->emissivity_max;
318
291
}
319
292
return IIO_VAL_INT_PLUS_NANO;
320
-
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: /* IIR setting with
321
-
FIR = 1024 */
293
+
/* IIR setting with FIR=1024 (MLX90614) or FIR=65536 (MLX90615) */
294
+
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
322
295
ret = mlx90614_power_get(data, false);
323
296
if (ret < 0)
324
297
return ret;
325
298
326
299
mutex_lock(&data->lock);
327
-
ret = i2c_smbus_read_word_data(data->client, MLX90614_CONFIG);
300
+
ret = i2c_smbus_read_word_data(data->client,
301
+
chip_info->op_eeprom_config1);
328
302
mutex_unlock(&data->lock);
329
303
mlx90614_power_put(data);
330
304
331
305
if (ret < 0)
332
306
return ret;
333
307
334
-
*val = mlx90614_iir_values[ret & MLX90614_CONFIG_IIR_MASK] / 100;
335
-
*val2 = (mlx90614_iir_values[ret & MLX90614_CONFIG_IIR_MASK] % 100) *
336
-
10000;
308
+
idx = field_get(chip_info->iir_config_mask, ret) -
309
+
chip_info->iir_valid_offset;
310
+
311
+
*val = chip_info->iir_values[idx] / 100;
312
+
*val2 = (chip_info->iir_values[idx] % 100) * 10000;
337
313
return IIO_VAL_INT_PLUS_MICRO;
338
314
default:
339
315
return -EINVAL;
···
348
318
int val2, long mask)
349
319
{
350
320
struct mlx90614_data *data = iio_priv(indio_dev);
321
+
const struct mlx_chip_info *chip_info = data->chip_info;
351
322
s32 ret;
352
323
353
324
switch (mask) {
354
-
case IIO_CHAN_INFO_CALIBEMISSIVITY: /* 1/65535 / LSB */
325
+
case IIO_CHAN_INFO_CALIBEMISSIVITY: /* 1/emissivity_max / LSB */
355
326
if (val < 0 || val2 < 0 || val > 1 || (val == 1 && val2 != 0))
356
327
return -EINVAL;
357
-
val = val * MLX90614_CONST_RAW_EMISSIVITY_MAX +
358
-
val2 / MLX90614_CONST_EMISSIVITY_RESOLUTION;
328
+
val = val * chip_info->emissivity_max +
329
+
val2 * chip_info->emissivity_max / NSEC_PER_SEC;
359
330
360
331
ret = mlx90614_power_get(data, false);
361
332
if (ret < 0)
362
333
return ret;
363
334
364
335
mutex_lock(&data->lock);
365
-
ret = mlx90614_write_word(data->client, MLX90614_EMISSIVITY,
366
-
val);
336
+
ret = mlx90614_write_word(data->client,
337
+
chip_info->op_eeprom_emissivity, val);
367
338
mutex_unlock(&data->lock);
368
339
mlx90614_power_put(data);
369
340
···
408
377
const int **vals, int *type, int *length,
409
378
long mask)
410
379
{
380
+
struct mlx90614_data *data = iio_priv(indio_dev);
381
+
const struct mlx_chip_info *chip_info = data->chip_info;
382
+
411
383
switch (mask) {
412
384
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
413
-
*vals = (int *)mlx90614_freqs;
385
+
*vals = (int *)chip_info->iir_freqs;
414
386
*type = IIO_VAL_INT_PLUS_MICRO;
415
-
*length = 2 * ARRAY_SIZE(mlx90614_freqs);
387
+
*length = 2 * (ARRAY_SIZE(chip_info->iir_freqs) -
388
+
chip_info->iir_valid_offset);
416
389
return IIO_AVAIL_LIST;
417
390
default:
418
391
return -EINVAL;
···
470
435
#ifdef CONFIG_PM
471
436
static int mlx90614_sleep(struct mlx90614_data *data)
472
437
{
438
+
const struct mlx_chip_info *chip_info = data->chip_info;
473
439
s32 ret;
474
440
475
441
if (!data->wakeup_gpio) {
···
483
447
mutex_lock(&data->lock);
484
448
ret = i2c_smbus_xfer(data->client->adapter, data->client->addr,
485
449
data->client->flags | I2C_CLIENT_PEC,
486
-
I2C_SMBUS_WRITE, MLX90614_OP_SLEEP,
450
+
I2C_SMBUS_WRITE, chip_info->op_sleep,
487
451
I2C_SMBUS_BYTE, NULL);
488
452
mutex_unlock(&data->lock);
489
453
···
492
456
493
457
static int mlx90614_wakeup(struct mlx90614_data *data)
494
458
{
459
+
const struct mlx_chip_info *chip_info = data->chip_info;
460
+
495
461
if (!data->wakeup_gpio) {
496
462
dev_dbg(&data->client->dev, "Wake-up disabled");
497
463
return -ENOSYS;
···
503
465
504
466
i2c_lock_bus(data->client->adapter, I2C_LOCK_ROOT_ADAPTER);
505
467
gpiod_direction_output(data->wakeup_gpio, 0);
506
-
msleep(MLX90614_TIMING_WAKEUP);
468
+
msleep(chip_info->wakeup_delay_ms);
507
469
gpiod_direction_input(data->wakeup_gpio);
508
470
i2c_unlock_bus(data->client->adapter, I2C_LOCK_ROOT_ADAPTER);
509
471
···
516
478
* If the read fails, the controller will probably be reset so that
517
479
* further reads will work.
518
480
*/
519
-
i2c_smbus_read_word_data(data->client, MLX90614_CONFIG);
481
+
i2c_smbus_read_word_data(data->client, chip_info->op_eeprom_config1);
520
482
521
483
return 0;
522
484
}
···
565
527
/* Return 0 for single sensor, 1 for dual sensor, <0 on error. */
566
528
static int mlx90614_probe_num_ir_sensors(struct i2c_client *client)
567
529
{
530
+
struct iio_dev *indio_dev = i2c_get_clientdata(client);
531
+
struct mlx90614_data *data = iio_priv(indio_dev);
532
+
const struct mlx_chip_info *chip_info = data->chip_info;
568
533
s32 ret;
569
534
570
-
ret = i2c_smbus_read_word_data(client, MLX90614_CONFIG);
535
+
if (chip_info->dual_channel)
536
+
return 0;
537
+
538
+
ret = i2c_smbus_read_word_data(client, chip_info->op_eeprom_config1);
571
539
572
540
if (ret < 0)
573
541
return ret;
···
600
556
data->client = client;
601
557
mutex_init(&data->lock);
602
558
data->wakeup_gpio = mlx90614_probe_wakeup(client);
559
+
data->chip_info = device_get_match_data(&client->dev);
603
560
604
561
mlx90614_wakeup(data);
605
562
···
650
605
}
651
606
}
652
607
608
+
static const struct mlx_chip_info mlx90614_chip_info = {
609
+
.op_eeprom_emissivity = MLX90614_OP_EEPROM | 0x04,
610
+
.op_eeprom_config1 = MLX90614_OP_EEPROM | 0x05,
611
+
.op_ram_ta = MLX90614_OP_RAM | 0x06,
612
+
.op_ram_tobj1 = MLX90614_OP_RAM | 0x07,
613
+
.op_ram_tobj2 = MLX90614_OP_RAM | 0x08,
614
+
.op_sleep = MLX90614_OP_SLEEP,
615
+
.dual_channel = true,
616
+
.wakeup_delay_ms = MLX90614_TIMING_WAKEUP,
617
+
.emissivity_max = 65535,
618
+
.fir_config_mask = MLX90614_CONFIG_FIR_MASK,
619
+
.iir_config_mask = MLX90614_CONFIG_IIR_MASK,
620
+
.iir_valid_offset = 0,
621
+
.iir_values = { 77, 31, 20, 15, 723, 153, 110, 86 },
622
+
.iir_freqs = {
623
+
{ 0, 150000 }, /* 13% ~= 0.15 Hz */
624
+
{ 0, 200000 }, /* 17% ~= 0.20 Hz */
625
+
{ 0, 310000 }, /* 25% ~= 0.31 Hz */
626
+
{ 0, 770000 }, /* 50% ~= 0.77 Hz */
627
+
{ 0, 860000 }, /* 57% ~= 0.86 Hz */
628
+
{ 1, 100000 }, /* 67% ~= 1.10 Hz */
629
+
{ 1, 530000 }, /* 80% ~= 1.53 Hz */
630
+
{ 7, 230000 } /* 100% ~= 7.23 Hz */
631
+
},
632
+
};
633
+
634
+
static const struct mlx_chip_info mlx90615_chip_info = {
635
+
.op_eeprom_emissivity = MLX90615_OP_EEPROM | 0x03,
636
+
.op_eeprom_config1 = MLX90615_OP_EEPROM | 0x02,
637
+
.op_ram_ta = MLX90615_OP_RAM | 0x06,
638
+
.op_ram_tobj1 = MLX90615_OP_RAM | 0x07,
639
+
.op_ram_tobj2 = MLX90615_OP_RAM | 0x08,
640
+
.op_sleep = MLX90615_OP_SLEEP,
641
+
.dual_channel = false,
642
+
.wakeup_delay_ms = MLX90615_TIMING_WAKEUP,
643
+
.emissivity_max = 16383,
644
+
.fir_config_mask = 0, /* MLX90615 FIR is fixed */
645
+
.iir_config_mask = MLX90615_CONFIG_IIR_MASK,
646
+
/* IIR value 0 is FORBIDDEN COMBINATION on MLX90615 */
647
+
.iir_valid_offset = 1,
648
+
.iir_values = { 500, 50, 30, 20, 15, 13, 10 },
649
+
.iir_freqs = {
650
+
{ 0, 100000 }, /* 14% ~= 0.10 Hz */
651
+
{ 0, 130000 }, /* 17% ~= 0.13 Hz */
652
+
{ 0, 150000 }, /* 20% ~= 0.15 Hz */
653
+
{ 0, 200000 }, /* 25% ~= 0.20 Hz */
654
+
{ 0, 300000 }, /* 33% ~= 0.30 Hz */
655
+
{ 0, 500000 }, /* 50% ~= 0.50 Hz */
656
+
{ 5, 000000 }, /* 100% ~= 5.00 Hz */
657
+
},
658
+
};
659
+
653
660
static const struct i2c_device_id mlx90614_id[] = {
654
-
{ "mlx90614", 0 },
661
+
{ "mlx90614", .driver_data = (kernel_ulong_t)&mlx90614_chip_info },
662
+
{ "mlx90615", .driver_data = (kernel_ulong_t)&mlx90615_chip_info },
655
663
{ }
656
664
};
657
665
MODULE_DEVICE_TABLE(i2c, mlx90614_id);
658
666
659
667
static const struct of_device_id mlx90614_of_match[] = {
660
-
{ .compatible = "melexis,mlx90614" },
668
+
{ .compatible = "melexis,mlx90614", .data = &mlx90614_chip_info },
669
+
{ .compatible = "melexis,mlx90615", .data = &mlx90615_chip_info },
661
670
{ }
662
671
};
663
672
MODULE_DEVICE_TABLE(of, mlx90614_of_match);
···
774
675
.of_match_table = mlx90614_of_match,
775
676
.pm = pm_ptr(&mlx90614_pm_ops),
776
677
},
777
-
.probe_new = mlx90614_probe,
678
+
.probe = mlx90614_probe,
778
679
.remove = mlx90614_remove,
779
680
.id_table = mlx90614_id,
780
681
};
+1
-1
drivers/iio/temperature/mlx90632.c
+1
-1
drivers/iio/temperature/mlx90632.c
+9
-1
drivers/iio/temperature/tmp006.c
+9
-1
drivers/iio/temperature/tmp006.c
···
15
15
#include <linux/i2c.h>
16
16
#include <linux/delay.h>
17
17
#include <linux/module.h>
18
+
#include <linux/mod_devicetable.h>
18
19
#include <linux/pm.h>
19
20
#include <linux/bitops.h>
20
21
···
273
272
274
273
static DEFINE_SIMPLE_DEV_PM_OPS(tmp006_pm_ops, tmp006_suspend, tmp006_resume);
275
274
275
+
static const struct of_device_id tmp006_of_match[] = {
276
+
{ .compatible = "ti,tmp006" },
277
+
{ }
278
+
};
279
+
MODULE_DEVICE_TABLE(of, tmp006_of_match);
280
+
276
281
static const struct i2c_device_id tmp006_id[] = {
277
282
{ "tmp006", 0 },
278
283
{ }
···
288
281
static struct i2c_driver tmp006_driver = {
289
282
.driver = {
290
283
.name = "tmp006",
284
+
.of_match_table = tmp006_of_match,
291
285
.pm = pm_sleep_ptr(&tmp006_pm_ops),
292
286
},
293
-
.probe_new = tmp006_probe,
287
+
.probe = tmp006_probe,
294
288
.id_table = tmp006_id,
295
289
};
296
290
module_i2c_driver(tmp006_driver);
+1
-1
drivers/iio/temperature/tmp007.c
+1
-1
drivers/iio/temperature/tmp007.c
+1
-1
drivers/iio/temperature/tmp117.c
+1
-1
drivers/iio/temperature/tmp117.c
+1
-1
drivers/iio/temperature/tsys01.c
+1
-1
drivers/iio/temperature/tsys01.c
+1
-1
drivers/iio/temperature/tsys02d.c
+1
-1
drivers/iio/temperature/tsys02d.c
+6
drivers/interconnect/Kconfig
+6
drivers/interconnect/Kconfig
+2
drivers/interconnect/Makefile
+2
drivers/interconnect/Makefile
+2
-50
drivers/interconnect/core.c
+2
-50
drivers/interconnect/core.c
···
587
587
588
588
/**
589
589
* icc_get_name() - Get name of the icc path
590
-
* @path: reference to the path returned by icc_get()
590
+
* @path: interconnect path
591
591
*
592
592
* This function is used by an interconnect consumer to get the name of the icc
593
593
* path.
···
605
605
606
606
/**
607
607
* icc_set_bw() - set bandwidth constraints on an interconnect path
608
-
* @path: reference to the path returned by icc_get()
608
+
* @path: interconnect path
609
609
* @avg_bw: average bandwidth in kilobytes per second
610
610
* @peak_bw: peak bandwidth in kilobytes per second
611
611
*
···
703
703
return __icc_enable(path, false);
704
704
}
705
705
EXPORT_SYMBOL_GPL(icc_disable);
706
-
707
-
/**
708
-
* icc_get() - return a handle for path between two endpoints
709
-
* @dev: the device requesting the path
710
-
* @src_id: source device port id
711
-
* @dst_id: destination device port id
712
-
*
713
-
* This function will search for a path between two endpoints and return an
714
-
* icc_path handle on success. Use icc_put() to release
715
-
* constraints when they are not needed anymore.
716
-
* If the interconnect API is disabled, NULL is returned and the consumer
717
-
* drivers will still build. Drivers are free to handle this specifically,
718
-
* but they don't have to.
719
-
*
720
-
* Return: icc_path pointer on success, ERR_PTR() on error or NULL if the
721
-
* interconnect API is disabled.
722
-
*/
723
-
struct icc_path *icc_get(struct device *dev, const int src_id, const int dst_id)
724
-
{
725
-
struct icc_node *src, *dst;
726
-
struct icc_path *path = ERR_PTR(-EPROBE_DEFER);
727
-
728
-
mutex_lock(&icc_lock);
729
-
730
-
src = node_find(src_id);
731
-
if (!src)
732
-
goto out;
733
-
734
-
dst = node_find(dst_id);
735
-
if (!dst)
736
-
goto out;
737
-
738
-
path = path_find(dev, src, dst);
739
-
if (IS_ERR(path)) {
740
-
dev_err(dev, "%s: invalid path=%ld\n", __func__, PTR_ERR(path));
741
-
goto out;
742
-
}
743
-
744
-
path->name = kasprintf(GFP_KERNEL, "%s-%s", src->name, dst->name);
745
-
if (!path->name) {
746
-
kfree(path);
747
-
path = ERR_PTR(-ENOMEM);
748
-
}
749
-
out:
750
-
mutex_unlock(&icc_lock);
751
-
return path;
752
-
}
753
-
EXPORT_SYMBOL_GPL(icc_get);
754
706
755
707
/**
756
708
* icc_put() - release the reference to the icc_path
+174
drivers/interconnect/icc-clk.c
+174
drivers/interconnect/icc-clk.c
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Ltd.
4
+
*/
5
+
6
+
#include <linux/clk.h>
7
+
#include <linux/device.h>
8
+
#include <linux/interconnect-clk.h>
9
+
#include <linux/interconnect-provider.h>
10
+
11
+
struct icc_clk_node {
12
+
struct clk *clk;
13
+
bool enabled;
14
+
};
15
+
16
+
struct icc_clk_provider {
17
+
struct icc_provider provider;
18
+
int num_clocks;
19
+
struct icc_clk_node clocks[];
20
+
};
21
+
22
+
#define to_icc_clk_provider(_provider) \
23
+
container_of(_provider, struct icc_clk_provider, provider)
24
+
25
+
static int icc_clk_set(struct icc_node *src, struct icc_node *dst)
26
+
{
27
+
struct icc_clk_node *qn = src->data;
28
+
int ret;
29
+
30
+
if (!qn || !qn->clk)
31
+
return 0;
32
+
33
+
if (!src->peak_bw) {
34
+
if (qn->enabled)
35
+
clk_disable_unprepare(qn->clk);
36
+
qn->enabled = false;
37
+
38
+
return 0;
39
+
}
40
+
41
+
if (!qn->enabled) {
42
+
ret = clk_prepare_enable(qn->clk);
43
+
if (ret)
44
+
return ret;
45
+
qn->enabled = true;
46
+
}
47
+
48
+
return clk_set_rate(qn->clk, icc_units_to_bps(src->peak_bw));
49
+
}
50
+
51
+
static int icc_clk_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
52
+
{
53
+
struct icc_clk_node *qn = node->data;
54
+
55
+
if (!qn || !qn->clk)
56
+
*peak = INT_MAX;
57
+
else
58
+
*peak = Bps_to_icc(clk_get_rate(qn->clk));
59
+
60
+
return 0;
61
+
}
62
+
63
+
/**
64
+
* icc_clk_register() - register a new clk-based interconnect provider
65
+
* @dev: device supporting this provider
66
+
* @first_id: an ID of the first provider's node
67
+
* @num_clocks: number of instances of struct icc_clk_data
68
+
* @data: data for the provider
69
+
*
70
+
* Registers and returns a clk-based interconnect provider. It is a simple
71
+
* wrapper around COMMON_CLK framework, allowing other devices to vote on the
72
+
* clock rate.
73
+
*
74
+
* Return: 0 on success, or an error code otherwise
75
+
*/
76
+
struct icc_provider *icc_clk_register(struct device *dev,
77
+
unsigned int first_id,
78
+
unsigned int num_clocks,
79
+
const struct icc_clk_data *data)
80
+
{
81
+
struct icc_clk_provider *qp;
82
+
struct icc_provider *provider;
83
+
struct icc_onecell_data *onecell;
84
+
struct icc_node *node;
85
+
int ret, i, j;
86
+
87
+
onecell = devm_kzalloc(dev, struct_size(onecell, nodes, 2 * num_clocks), GFP_KERNEL);
88
+
if (!onecell)
89
+
return ERR_PTR(-ENOMEM);
90
+
91
+
qp = devm_kzalloc(dev, struct_size(qp, clocks, num_clocks), GFP_KERNEL);
92
+
if (!qp)
93
+
return ERR_PTR(-ENOMEM);
94
+
95
+
qp->num_clocks = num_clocks;
96
+
97
+
provider = &qp->provider;
98
+
provider->dev = dev;
99
+
provider->get_bw = icc_clk_get_bw;
100
+
provider->set = icc_clk_set;
101
+
provider->aggregate = icc_std_aggregate;
102
+
provider->xlate = of_icc_xlate_onecell;
103
+
INIT_LIST_HEAD(&provider->nodes);
104
+
provider->data = onecell;
105
+
106
+
icc_provider_init(provider);
107
+
108
+
for (i = 0, j = 0; i < num_clocks; i++) {
109
+
qp->clocks[i].clk = data[i].clk;
110
+
111
+
node = icc_node_create(first_id + j);
112
+
if (IS_ERR(node)) {
113
+
ret = PTR_ERR(node);
114
+
goto err;
115
+
}
116
+
117
+
node->name = devm_kasprintf(dev, GFP_KERNEL, "%s_master", data[i].name);
118
+
node->data = &qp->clocks[i];
119
+
icc_node_add(node, provider);
120
+
/* link to the next node, slave */
121
+
icc_link_create(node, first_id + j + 1);
122
+
onecell->nodes[j++] = node;
123
+
124
+
node = icc_node_create(first_id + j);
125
+
if (IS_ERR(node)) {
126
+
ret = PTR_ERR(node);
127
+
goto err;
128
+
}
129
+
130
+
node->name = devm_kasprintf(dev, GFP_KERNEL, "%s_slave", data[i].name);
131
+
/* no data for slave node */
132
+
icc_node_add(node, provider);
133
+
onecell->nodes[j++] = node;
134
+
}
135
+
136
+
onecell->num_nodes = j;
137
+
138
+
ret = icc_provider_register(provider);
139
+
if (ret)
140
+
goto err;
141
+
142
+
return provider;
143
+
144
+
err:
145
+
icc_nodes_remove(provider);
146
+
147
+
return ERR_PTR(ret);
148
+
}
149
+
EXPORT_SYMBOL_GPL(icc_clk_register);
150
+
151
+
/**
152
+
* icc_clk_unregister() - unregister a previously registered clk interconnect provider
153
+
* @provider: provider returned by icc_clk_register()
154
+
*/
155
+
void icc_clk_unregister(struct icc_provider *provider)
156
+
{
157
+
struct icc_clk_provider *qp = container_of(provider, struct icc_clk_provider, provider);
158
+
int i;
159
+
160
+
icc_provider_deregister(&qp->provider);
161
+
icc_nodes_remove(&qp->provider);
162
+
163
+
for (i = 0; i < qp->num_clocks; i++) {
164
+
struct icc_clk_node *qn = &qp->clocks[i];
165
+
166
+
if (qn->enabled)
167
+
clk_disable_unprepare(qn->clk);
168
+
}
169
+
}
170
+
EXPORT_SYMBOL_GPL(icc_clk_unregister);
171
+
172
+
MODULE_LICENSE("GPL");
173
+
MODULE_DESCRIPTION("Interconnect wrapper for clocks");
174
+
MODULE_AUTHOR("Dmitry Baryshkov <dmitry.baryshkov@linaro.org>");
+59
-53
drivers/interconnect/qcom/icc-rpm.c
+59
-53
drivers/interconnect/qcom/icc-rpm.c
···
50
50
#define NOC_QOS_MODE_FIXED_VAL 0x0
51
51
#define NOC_QOS_MODE_BYPASS_VAL 0x2
52
52
53
-
static int qcom_icc_set_qnoc_qos(struct icc_node *src, u64 max_bw)
53
+
static int qcom_icc_set_qnoc_qos(struct icc_node *src)
54
54
{
55
55
struct icc_provider *provider = src->provider;
56
56
struct qcom_icc_provider *qp = to_qcom_provider(provider);
···
95
95
mask, val);
96
96
}
97
97
98
-
static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw)
98
+
static int qcom_icc_set_bimc_qos(struct icc_node *src)
99
99
{
100
100
struct qcom_icc_provider *qp;
101
101
struct qcom_icc_node *qn;
···
150
150
NOC_QOS_PRIORITY_P0_MASK, qos->prio_level);
151
151
}
152
152
153
-
static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw)
153
+
static int qcom_icc_set_noc_qos(struct icc_node *src)
154
154
{
155
155
struct qcom_icc_provider *qp;
156
156
struct qcom_icc_node *qn;
···
187
187
NOC_QOS_MODEn_MASK, mode);
188
188
}
189
189
190
-
static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw)
190
+
static int qcom_icc_qos_set(struct icc_node *node)
191
191
{
192
192
struct qcom_icc_provider *qp = to_qcom_provider(node->provider);
193
193
struct qcom_icc_node *qn = node->data;
···
196
196
197
197
switch (qp->type) {
198
198
case QCOM_ICC_BIMC:
199
-
return qcom_icc_set_bimc_qos(node, sum_bw);
199
+
return qcom_icc_set_bimc_qos(node);
200
200
case QCOM_ICC_QNOC:
201
-
return qcom_icc_set_qnoc_qos(node, sum_bw);
201
+
return qcom_icc_set_qnoc_qos(node);
202
202
default:
203
-
return qcom_icc_set_noc_qos(node, sum_bw);
203
+
return qcom_icc_set_noc_qos(node);
204
204
}
205
205
}
206
206
207
-
static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw)
207
+
static int qcom_icc_rpm_set(struct qcom_icc_node *qn, u64 sum_bw)
208
208
{
209
209
int ret = 0;
210
210
211
-
if (mas_rpm_id != -1) {
211
+
if (qn->qos.ap_owned)
212
+
return 0;
213
+
214
+
if (qn->mas_rpm_id != -1) {
212
215
ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
213
216
RPM_BUS_MASTER_REQ,
214
-
mas_rpm_id,
217
+
qn->mas_rpm_id,
215
218
sum_bw);
216
219
if (ret) {
217
220
pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
218
-
mas_rpm_id, ret);
221
+
qn->mas_rpm_id, ret);
219
222
return ret;
220
223
}
221
224
}
222
225
223
-
if (slv_rpm_id != -1) {
226
+
if (qn->slv_rpm_id != -1) {
224
227
ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
225
228
RPM_BUS_SLAVE_REQ,
226
-
slv_rpm_id,
229
+
qn->slv_rpm_id,
227
230
sum_bw);
228
231
if (ret) {
229
232
pr_err("qcom_icc_rpm_smd_send slv %d error %d\n",
230
-
slv_rpm_id, ret);
233
+
qn->slv_rpm_id, ret);
231
234
return ret;
232
235
}
233
236
}
234
237
235
238
return ret;
236
-
}
237
-
238
-
static int __qcom_icc_set(struct icc_node *n, struct qcom_icc_node *qn,
239
-
u64 sum_bw)
240
-
{
241
-
int ret;
242
-
243
-
if (!qn->qos.ap_owned) {
244
-
/* send bandwidth request message to the RPM processor */
245
-
ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw);
246
-
if (ret)
247
-
return ret;
248
-
} else if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID) {
249
-
/* set bandwidth directly from the AP */
250
-
ret = qcom_icc_qos_set(n, sum_bw);
251
-
if (ret)
252
-
return ret;
253
-
}
254
-
255
-
return 0;
256
239
}
257
240
258
241
/**
···
353
370
354
371
sum_bw = icc_units_to_bps(max_agg_avg);
355
372
356
-
ret = __qcom_icc_set(src, src_qn, sum_bw);
373
+
ret = qcom_icc_rpm_set(src_qn, sum_bw);
357
374
if (ret)
358
375
return ret;
376
+
359
377
if (dst_qn) {
360
-
ret = __qcom_icc_set(dst, dst_qn, sum_bw);
378
+
ret = qcom_icc_rpm_set(dst_qn, sum_bw);
361
379
if (ret)
362
380
return ret;
363
381
}
364
382
365
-
for (i = 0; i < qp->num_clks; i++) {
383
+
for (i = 0; i < qp->num_bus_clks; i++) {
366
384
/*
367
385
* Use WAKE bucket for active clock, otherwise, use SLEEP bucket
368
386
* for other clocks. If a platform doesn't set interconnect
···
409
425
struct qcom_icc_provider *qp;
410
426
struct icc_node *node;
411
427
size_t num_nodes, i;
412
-
const char * const *cds;
428
+
const char * const *cds = NULL;
413
429
int cd_num;
414
430
int ret;
415
431
···
424
440
qnodes = desc->nodes;
425
441
num_nodes = desc->num_nodes;
426
442
427
-
if (desc->num_clocks) {
428
-
cds = desc->clocks;
429
-
cd_num = desc->num_clocks;
443
+
if (desc->num_intf_clocks) {
444
+
cds = desc->intf_clocks;
445
+
cd_num = desc->num_intf_clocks;
430
446
} else {
431
-
cds = bus_clocks;
432
-
cd_num = ARRAY_SIZE(bus_clocks);
447
+
/* 0 intf clocks is perfectly fine */
448
+
cd_num = 0;
433
449
}
434
450
435
-
qp = devm_kzalloc(dev, struct_size(qp, bus_clks, cd_num), GFP_KERNEL);
451
+
qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
436
452
if (!qp)
437
453
return -ENOMEM;
438
454
439
-
qp->bus_clk_rate = devm_kcalloc(dev, cd_num, sizeof(*qp->bus_clk_rate),
440
-
GFP_KERNEL);
441
-
if (!qp->bus_clk_rate)
455
+
qp->intf_clks = devm_kcalloc(dev, cd_num, sizeof(*qp->intf_clks), GFP_KERNEL);
456
+
if (!qp->intf_clks)
442
457
return -ENOMEM;
443
458
444
459
data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
···
445
462
if (!data)
446
463
return -ENOMEM;
447
464
465
+
qp->num_intf_clks = cd_num;
448
466
for (i = 0; i < cd_num; i++)
449
-
qp->bus_clks[i].id = cds[i];
450
-
qp->num_clks = cd_num;
467
+
qp->intf_clks[i].id = cds[i];
468
+
469
+
qp->num_bus_clks = desc->no_clk_scaling ? 0 : NUM_BUS_CLKS;
470
+
for (i = 0; i < qp->num_bus_clks; i++)
471
+
qp->bus_clks[i].id = bus_clocks[i];
451
472
452
473
qp->type = desc->type;
453
474
qp->qos_offset = desc->qos_offset;
···
481
494
}
482
495
483
496
regmap_done:
484
-
ret = devm_clk_bulk_get_optional(dev, qp->num_clks, qp->bus_clks);
497
+
ret = devm_clk_bulk_get(dev, qp->num_bus_clks, qp->bus_clks);
485
498
if (ret)
486
499
return ret;
487
500
488
-
ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
501
+
ret = clk_bulk_prepare_enable(qp->num_bus_clks, qp->bus_clks);
502
+
if (ret)
503
+
return ret;
504
+
505
+
ret = devm_clk_bulk_get(dev, qp->num_intf_clks, qp->intf_clks);
489
506
if (ret)
490
507
return ret;
491
508
···
502
511
provider->data = data;
503
512
504
513
icc_provider_init(provider);
514
+
515
+
/* If this fails, bus accesses will crash the platform! */
516
+
ret = clk_bulk_prepare_enable(qp->num_intf_clks, qp->intf_clks);
517
+
if (ret)
518
+
return ret;
505
519
506
520
for (i = 0; i < num_nodes; i++) {
507
521
size_t j;
···
524
528
for (j = 0; j < qnodes[i]->num_links; j++)
525
529
icc_link_create(node, qnodes[i]->links[j]);
526
530
531
+
/* Set QoS registers (we only need to do it once, generally) */
532
+
if (qnodes[i]->qos.ap_owned &&
533
+
qnodes[i]->qos.qos_mode != NOC_QOS_MODE_INVALID) {
534
+
ret = qcom_icc_qos_set(node);
535
+
if (ret)
536
+
return ret;
537
+
}
538
+
527
539
data->nodes[i] = node;
528
540
}
529
541
data->num_nodes = num_nodes;
542
+
543
+
clk_bulk_disable_unprepare(qp->num_intf_clks, qp->intf_clks);
530
544
531
545
ret = icc_provider_register(provider);
532
546
if (ret)
···
557
551
icc_provider_deregister(provider);
558
552
err_remove_nodes:
559
553
icc_nodes_remove(provider);
560
-
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
554
+
clk_bulk_disable_unprepare(qp->num_bus_clks, qp->bus_clks);
561
555
562
556
return ret;
563
557
}
···
569
563
570
564
icc_provider_deregister(&qp->provider);
571
565
icc_nodes_remove(&qp->provider);
572
-
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
566
+
clk_bulk_disable_unprepare(qp->num_bus_clks, qp->bus_clks);
573
567
574
568
return 0;
575
569
}
+16
-6
drivers/interconnect/qcom/icc-rpm.h
+16
-6
drivers/interconnect/qcom/icc-rpm.h
···
20
20
QCOM_ICC_QNOC,
21
21
};
22
22
23
+
#define NUM_BUS_CLKS 2
24
+
23
25
/**
24
26
* struct qcom_icc_provider - Qualcomm specific interconnect provider
25
27
* @provider: generic interconnect provider
26
-
* @num_clks: the total number of clk_bulk_data entries
28
+
* @num_bus_clks: the total number of bus_clks clk_bulk_data entries (0 or 2)
29
+
* @num_intf_clks: the total number of intf_clks clk_bulk_data entries
27
30
* @type: the ICC provider type
28
31
* @regmap: regmap for QoS registers read/write access
29
32
* @qos_offset: offset to QoS registers
30
33
* @bus_clk_rate: bus clock rate in Hz
31
34
* @bus_clks: the clk_bulk_data table of bus clocks
35
+
* @intf_clks: a clk_bulk_data array of interface clocks
36
+
* @is_on: whether the bus is powered on
32
37
*/
33
38
struct qcom_icc_provider {
34
39
struct icc_provider provider;
35
-
int num_clks;
40
+
int num_bus_clks;
41
+
int num_intf_clks;
36
42
enum qcom_icc_type type;
37
43
struct regmap *regmap;
38
44
unsigned int qos_offset;
39
-
u64 *bus_clk_rate;
40
-
struct clk_bulk_data bus_clks[];
45
+
u64 bus_clk_rate[NUM_BUS_CLKS];
46
+
struct clk_bulk_data bus_clks[NUM_BUS_CLKS];
47
+
struct clk_bulk_data *intf_clks;
48
+
bool is_on;
41
49
};
42
50
43
51
/**
···
99
91
struct qcom_icc_desc {
100
92
struct qcom_icc_node * const *nodes;
101
93
size_t num_nodes;
102
-
const char * const *clocks;
103
-
size_t num_clocks;
94
+
const char * const *bus_clocks;
95
+
const char * const *intf_clocks;
96
+
size_t num_intf_clocks;
97
+
bool no_clk_scaling;
104
98
enum qcom_icc_type type;
105
99
const struct regmap_config *regmap_cfg;
106
100
unsigned int qos_offset;
+21
-14
drivers/interconnect/qcom/msm8996.c
+21
-14
drivers/interconnect/qcom/msm8996.c
···
21
21
#include "smd-rpm.h"
22
22
#include "msm8996.h"
23
23
24
-
static const char * const bus_mm_clocks[] = {
25
-
"bus",
26
-
"bus_a",
24
+
static const char * const mm_intf_clocks[] = {
27
25
"iface"
28
26
};
29
27
30
-
static const char * const bus_a0noc_clocks[] = {
28
+
static const char * const a0noc_intf_clocks[] = {
31
29
"aggre0_snoc_axi",
32
30
"aggre0_cnoc_ahb",
33
31
"aggre0_noc_mpu_cfg"
34
32
};
35
33
36
-
static const char * const bus_a2noc_clocks[] = {
37
-
"bus",
38
-
"bus_a",
34
+
static const char * const a2noc_intf_clocks[] = {
39
35
"aggre2_ufs_axi",
40
36
"ufs_axi"
41
37
};
···
1817
1821
.type = QCOM_ICC_NOC,
1818
1822
.nodes = a0noc_nodes,
1819
1823
.num_nodes = ARRAY_SIZE(a0noc_nodes),
1820
-
.clocks = bus_a0noc_clocks,
1821
-
.num_clocks = ARRAY_SIZE(bus_a0noc_clocks),
1824
+
.intf_clocks = a0noc_intf_clocks,
1825
+
.num_intf_clocks = ARRAY_SIZE(a0noc_intf_clocks),
1826
+
.no_clk_scaling = true,
1822
1827
.regmap_cfg = &msm8996_a0noc_regmap_config
1823
1828
};
1824
1829
···
1862
1865
.type = QCOM_ICC_NOC,
1863
1866
.nodes = a2noc_nodes,
1864
1867
.num_nodes = ARRAY_SIZE(a2noc_nodes),
1865
-
.clocks = bus_a2noc_clocks,
1866
-
.num_clocks = ARRAY_SIZE(bus_a2noc_clocks),
1868
+
.intf_clocks = a2noc_intf_clocks,
1869
+
.num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
1867
1870
.regmap_cfg = &msm8996_a2noc_regmap_config
1868
1871
};
1869
1872
···
2001
2004
.type = QCOM_ICC_NOC,
2002
2005
.nodes = mnoc_nodes,
2003
2006
.num_nodes = ARRAY_SIZE(mnoc_nodes),
2004
-
.clocks = bus_mm_clocks,
2005
-
.num_clocks = ARRAY_SIZE(bus_mm_clocks),
2007
+
.intf_clocks = mm_intf_clocks,
2008
+
.num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
2006
2009
.regmap_cfg = &msm8996_mnoc_regmap_config
2007
2010
};
2008
2011
···
2108
2111
.sync_state = icc_sync_state,
2109
2112
}
2110
2113
};
2111
-
module_platform_driver(qnoc_driver);
2114
+
static int __init qnoc_driver_init(void)
2115
+
{
2116
+
return platform_driver_register(&qnoc_driver);
2117
+
}
2118
+
core_initcall(qnoc_driver_init);
2119
+
2120
+
static void __exit qnoc_driver_exit(void)
2121
+
{
2122
+
platform_driver_unregister(&qnoc_driver);
2123
+
}
2124
+
module_exit(qnoc_driver_exit);
2112
2125
2113
2126
MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
2114
2127
MODULE_DESCRIPTION("Qualcomm MSM8996 NoC driver");
+7
-10
drivers/interconnect/qcom/sdm660.c
+7
-10
drivers/interconnect/qcom/sdm660.c
···
127
127
SDM660_SNOC,
128
128
};
129
129
130
-
static const char * const bus_mm_clocks[] = {
131
-
"bus",
132
-
"bus_a",
130
+
static const char * const mm_intf_clocks[] = {
133
131
"iface",
134
132
};
135
133
136
-
static const char * const bus_a2noc_clocks[] = {
137
-
"bus",
138
-
"bus_a",
134
+
static const char * const a2noc_intf_clocks[] = {
139
135
"ipa",
140
136
"ufs_axi",
141
137
"aggre2_ufs_axi",
···
1512
1516
.type = QCOM_ICC_NOC,
1513
1517
.nodes = sdm660_a2noc_nodes,
1514
1518
.num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
1515
-
.clocks = bus_a2noc_clocks,
1516
-
.num_clocks = ARRAY_SIZE(bus_a2noc_clocks),
1519
+
.intf_clocks = a2noc_intf_clocks,
1520
+
.num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
1517
1521
.regmap_cfg = &sdm660_a2noc_regmap_config,
1518
1522
};
1519
1523
···
1616
1620
.nodes = sdm660_gnoc_nodes,
1617
1621
.num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
1618
1622
.regmap_cfg = &sdm660_gnoc_regmap_config,
1623
+
.no_clk_scaling = true,
1619
1624
};
1620
1625
1621
1626
static struct qcom_icc_node * const sdm660_mnoc_nodes[] = {
···
1656
1659
.type = QCOM_ICC_NOC,
1657
1660
.nodes = sdm660_mnoc_nodes,
1658
1661
.num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
1659
-
.clocks = bus_mm_clocks,
1660
-
.num_clocks = ARRAY_SIZE(bus_mm_clocks),
1662
+
.intf_clocks = mm_intf_clocks,
1663
+
.num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
1661
1664
.regmap_cfg = &sdm660_mnoc_regmap_config,
1662
1665
};
1663
1666
-1
drivers/isdn/Kconfig
-1
drivers/isdn/Kconfig
+6
-6
drivers/isdn/hardware/mISDN/Kconfig
+6
-6
drivers/isdn/hardware/mISDN/Kconfig
···
14
14
15
15
config MISDN_HFCMULTI
16
16
tristate "Support for HFC multiport cards (HFC-4S/8S/E1)"
17
-
depends on PCI || CPM1
17
+
depends on (PCI || CPM1) && HAS_IOPORT
18
18
depends on MISDN
19
19
help
20
20
Enable support for cards with Cologne Chip AG's HFC multiport
···
43
43
config MISDN_AVMFRITZ
44
44
tristate "Support for AVM FRITZ!CARD PCI"
45
45
depends on MISDN
46
-
depends on PCI
46
+
depends on PCI && HAS_IOPORT
47
47
select MISDN_IPAC
48
48
help
49
49
Enable support for AVMs FRITZ!CARD PCI cards
···
51
51
config MISDN_SPEEDFAX
52
52
tristate "Support for Sedlbauer Speedfax+"
53
53
depends on MISDN
54
-
depends on PCI
54
+
depends on PCI && HAS_IOPORT
55
55
select MISDN_IPAC
56
56
select MISDN_ISAR
57
57
help
···
60
60
config MISDN_INFINEON
61
61
tristate "Support for cards with Infineon chipset"
62
62
depends on MISDN
63
-
depends on PCI
63
+
depends on PCI && HAS_IOPORT
64
64
select MISDN_IPAC
65
65
help
66
66
Enable support for cards with ISAC + HSCX, IPAC or IPAC-SX
···
69
69
config MISDN_W6692
70
70
tristate "Support for cards with Winbond 6692"
71
71
depends on MISDN
72
-
depends on PCI
72
+
depends on PCI && HAS_IOPORT
73
73
help
74
74
Enable support for Winbond 6692 PCI chip based cards.
75
75
76
76
config MISDN_NETJET
77
77
tristate "Support for NETJet cards"
78
78
depends on MISDN
79
-
depends on PCI
79
+
depends on PCI && HAS_IOPORT
80
80
depends on TTY
81
81
select MISDN_IPAC
82
82
select MISDN_HDLC
+23
drivers/misc/Kconfig
+23
drivers/misc/Kconfig
···
538
538
539
539
Say N here unless you know what you are doing.
540
540
541
+
config TPS6594_ESM
542
+
tristate "TI TPS6594 Error Signal Monitor support"
543
+
depends on MFD_TPS6594
544
+
default MFD_TPS6594
545
+
help
546
+
Support ESM (Error Signal Monitor) on TPS6594 PMIC devices.
547
+
ESM is used typically to reboot the board in error condition.
548
+
549
+
This driver can also be built as a module. If so, the module
550
+
will be called tps6594-esm.
551
+
552
+
config TPS6594_PFSM
553
+
tristate "TI TPS6594 Pre-configurable Finite State Machine support"
554
+
depends on MFD_TPS6594
555
+
default MFD_TPS6594
556
+
help
557
+
Support PFSM (Pre-configurable Finite State Machine) on TPS6594 PMIC devices.
558
+
These devices integrate a finite state machine engine, which manages the state
559
+
of the device during operating state transition.
560
+
561
+
This driver can also be built as a module. If so, the module
562
+
will be called tps6594-pfsm.
563
+
541
564
source "drivers/misc/c2port/Kconfig"
542
565
source "drivers/misc/eeprom/Kconfig"
543
566
source "drivers/misc/cb710/Kconfig"
+2
drivers/misc/Makefile
+2
drivers/misc/Makefile
+1
-1
drivers/misc/ad525x_dpot-i2c.c
+1
-1
drivers/misc/ad525x_dpot-i2c.c
+2
-1
drivers/misc/altera-stapl/Makefile
+2
-1
drivers/misc/altera-stapl/Makefile
+5
-1
drivers/misc/altera-stapl/altera.c
+5
-1
drivers/misc/altera-stapl/altera.c
···
2407
2407
2408
2408
astate->config = config;
2409
2409
if (!astate->config->jtag_io) {
2410
+
if (!IS_ENABLED(CONFIG_HAS_IOPORT)) {
2411
+
retval = -ENODEV;
2412
+
goto free_state;
2413
+
}
2410
2414
dprintk("%s: using byteblaster!\n", __func__);
2411
2415
astate->config->jtag_io = netup_jtag_io_lpt;
2412
2416
}
···
2485
2481
2486
2482
} else if (exec_result)
2487
2483
printk(KERN_ERR "%s: error %d\n", __func__, exec_result);
2488
-
2484
+
free_state:
2489
2485
kfree(astate);
2490
2486
free_value:
2491
2487
kfree(value);
+1
-1
drivers/misc/apds9802als.c
+1
-1
drivers/misc/apds9802als.c
+2
-2
drivers/misc/apds990x.c
+2
-2
drivers/misc/apds990x.c
···
1267
1267
};
1268
1268
1269
1269
static struct i2c_driver apds990x_driver = {
1270
-
.driver = {
1270
+
.driver = {
1271
1271
.name = "apds990x",
1272
1272
.pm = &apds990x_pm_ops,
1273
1273
},
1274
-
.probe_new = apds990x_probe,
1274
+
.probe = apds990x_probe,
1275
1275
.remove = apds990x_remove,
1276
1276
.id_table = apds990x_id,
1277
1277
};
+2
-2
drivers/misc/bh1770glc.c
+2
-2
drivers/misc/bh1770glc.c
···
1374
1374
};
1375
1375
1376
1376
static struct i2c_driver bh1770_driver = {
1377
-
.driver = {
1377
+
.driver = {
1378
1378
.name = "bh1770glc",
1379
1379
.pm = &bh1770_pm_ops,
1380
1380
},
1381
-
.probe_new = bh1770_probe,
1381
+
.probe = bh1770_probe,
1382
1382
.remove = bh1770_remove,
1383
1383
.id_table = bh1770_id,
1384
1384
};
+1
-1
drivers/misc/ds1682.c
+1
-1
drivers/misc/ds1682.c
+1
-1
drivers/misc/eeprom/at24.c
+1
-1
drivers/misc/eeprom/at24.c
+1
-1
drivers/misc/eeprom/ee1004.c
+1
-1
drivers/misc/eeprom/ee1004.c
+1
-1
drivers/misc/eeprom/eeprom.c
+1
-1
drivers/misc/eeprom/eeprom.c
+1
-1
drivers/misc/eeprom/idt_89hpesx.c
+1
-1
drivers/misc/eeprom/idt_89hpesx.c
+1
-1
drivers/misc/eeprom/max6875.c
+1
-1
drivers/misc/eeprom/max6875.c
+4
-1
drivers/misc/fastrpc.c
+4
-1
drivers/misc/fastrpc.c
···
1437
1437
1438
1438
sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE, 4, 0);
1439
1439
if (init.attrs)
1440
-
sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE_ATTR, 6, 0);
1440
+
sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE_ATTR, 4, 0);
1441
1441
1442
1442
err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE,
1443
1443
sc, args);
···
2225
2225
fdev->miscdev.fops = &fastrpc_fops;
2226
2226
fdev->miscdev.name = devm_kasprintf(dev, GFP_KERNEL, "fastrpc-%s%s",
2227
2227
domain, is_secured ? "-secure" : "");
2228
+
if (!fdev->miscdev.name)
2229
+
return -ENOMEM;
2230
+
2228
2231
err = misc_register(&fdev->miscdev);
2229
2232
if (!err) {
2230
2233
if (is_secured)
+1
-1
drivers/misc/hmc6352.c
+1
-1
drivers/misc/hmc6352.c
+1
-1
drivers/misc/ics932s401.c
+1
-1
drivers/misc/ics932s401.c
+1
-1
drivers/misc/isl29003.c
+1
-1
drivers/misc/isl29003.c
+1
-1
drivers/misc/isl29020.c
+1
-1
drivers/misc/isl29020.c
+1
-1
drivers/misc/lis3lv02d/lis3lv02d_i2c.c
+1
-1
drivers/misc/lis3lv02d/lis3lv02d_i2c.c
+1
-1
drivers/misc/lkdtm/core.c
+1
-1
drivers/misc/lkdtm/core.c
···
79
79
CRASHPOINT("INT_HARDWARE_ENTRY", "do_IRQ"),
80
80
CRASHPOINT("INT_HW_IRQ_EN", "handle_irq_event"),
81
81
CRASHPOINT("INT_TASKLET_ENTRY", "tasklet_action"),
82
-
CRASHPOINT("FS_DEVRW", "ll_rw_block"),
82
+
CRASHPOINT("FS_SUBMIT_BH", "submit_bh"),
83
83
CRASHPOINT("MEM_SWAPOUT", "shrink_inactive_list"),
84
84
CRASHPOINT("TIMERADD", "hrtimer_start"),
85
85
CRASHPOINT("SCSI_QUEUE_RQ", "scsi_queue_rq"),
+2
-2
drivers/misc/mei/bus-fixup.c
+2
-2
drivers/misc/mei/bus-fixup.c
···
108
108
static int mei_osver(struct mei_cl_device *cldev)
109
109
{
110
110
const size_t size = MKHI_OSVER_BUF_LEN;
111
-
char buf[MKHI_OSVER_BUF_LEN];
111
+
u8 buf[MKHI_OSVER_BUF_LEN];
112
112
struct mkhi_msg *req;
113
113
struct mkhi_fwcaps *fwcaps;
114
114
struct mei_os_ver *os_ver;
···
137
137
sizeof(struct mkhi_fw_ver_block) * (__num))
138
138
static int mei_fwver(struct mei_cl_device *cldev)
139
139
{
140
-
char buf[MKHI_FWVER_BUF_LEN];
140
+
u8 buf[MKHI_FWVER_BUF_LEN];
141
141
struct mkhi_msg req;
142
142
struct mkhi_msg *rsp;
143
143
struct mkhi_fw_ver *fwver;
-9
drivers/misc/mei/bus.c
-9
drivers/misc/mei/bus.c
···
1046
1046
const struct mei_cl_driver *cldrv = to_mei_cl_driver(drv);
1047
1047
const struct mei_cl_device_id *found_id;
1048
1048
1049
-
if (!cldev)
1050
-
return 0;
1051
-
1052
1049
if (!cldev->do_match)
1053
1050
return 0;
1054
1051
···
1075
1078
1076
1079
cldev = to_mei_cl_device(dev);
1077
1080
cldrv = to_mei_cl_driver(dev->driver);
1078
-
1079
-
if (!cldev)
1080
-
return 0;
1081
1081
1082
1082
if (!cldrv || !cldrv->probe)
1083
1083
return -ENODEV;
···
1269
1275
static void mei_cl_bus_dev_release(struct device *dev)
1270
1276
{
1271
1277
struct mei_cl_device *cldev = to_mei_cl_device(dev);
1272
-
1273
-
if (!cldev)
1274
-
return;
1275
1278
1276
1279
mei_cl_flush_queues(cldev->cl, NULL);
1277
1280
mei_me_cl_put(cldev->me_cl);
-1
drivers/misc/smpro-errmon.c
-1
drivers/misc/smpro-errmon.c
+132
drivers/misc/tps6594-esm.c
+132
drivers/misc/tps6594-esm.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* ESM (Error Signal Monitor) driver for TI TPS6594/TPS6593/LP8764 PMICs
4
+
*
5
+
* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
6
+
*/
7
+
8
+
#include <linux/interrupt.h>
9
+
#include <linux/module.h>
10
+
#include <linux/platform_device.h>
11
+
#include <linux/pm_runtime.h>
12
+
#include <linux/regmap.h>
13
+
14
+
#include <linux/mfd/tps6594.h>
15
+
16
+
static irqreturn_t tps6594_esm_isr(int irq, void *dev_id)
17
+
{
18
+
struct platform_device *pdev = dev_id;
19
+
int i;
20
+
21
+
for (i = 0 ; i < pdev->num_resources ; i++) {
22
+
if (irq == platform_get_irq_byname(pdev, pdev->resource[i].name)) {
23
+
dev_err(pdev->dev.parent, "%s error detected\n", pdev->resource[i].name);
24
+
return IRQ_HANDLED;
25
+
}
26
+
}
27
+
28
+
return IRQ_NONE;
29
+
}
30
+
31
+
static int tps6594_esm_probe(struct platform_device *pdev)
32
+
{
33
+
struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent);
34
+
struct device *dev = &pdev->dev;
35
+
int irq;
36
+
int ret;
37
+
int i;
38
+
39
+
for (i = 0 ; i < pdev->num_resources ; i++) {
40
+
irq = platform_get_irq_byname(pdev, pdev->resource[i].name);
41
+
if (irq < 0)
42
+
return dev_err_probe(dev, irq, "Failed to get %s irq\n",
43
+
pdev->resource[i].name);
44
+
45
+
ret = devm_request_threaded_irq(dev, irq, NULL,
46
+
tps6594_esm_isr, IRQF_ONESHOT,
47
+
pdev->resource[i].name, pdev);
48
+
if (ret)
49
+
return dev_err_probe(dev, ret, "Failed to request irq\n");
50
+
}
51
+
52
+
ret = regmap_set_bits(tps->regmap, TPS6594_REG_ESM_SOC_MODE_CFG,
53
+
TPS6594_BIT_ESM_SOC_EN | TPS6594_BIT_ESM_SOC_ENDRV);
54
+
if (ret)
55
+
return dev_err_probe(dev, ret, "Failed to configure ESM\n");
56
+
57
+
ret = regmap_set_bits(tps->regmap, TPS6594_REG_ESM_SOC_START_REG,
58
+
TPS6594_BIT_ESM_SOC_START);
59
+
if (ret)
60
+
return dev_err_probe(dev, ret, "Failed to start ESM\n");
61
+
62
+
pm_runtime_enable(dev);
63
+
pm_runtime_get_sync(dev);
64
+
65
+
return 0;
66
+
}
67
+
68
+
static int tps6594_esm_remove(struct platform_device *pdev)
69
+
{
70
+
struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent);
71
+
struct device *dev = &pdev->dev;
72
+
int ret;
73
+
74
+
ret = regmap_clear_bits(tps->regmap, TPS6594_REG_ESM_SOC_START_REG,
75
+
TPS6594_BIT_ESM_SOC_START);
76
+
if (ret) {
77
+
dev_err(dev, "Failed to stop ESM\n");
78
+
goto out;
79
+
}
80
+
81
+
ret = regmap_clear_bits(tps->regmap, TPS6594_REG_ESM_SOC_MODE_CFG,
82
+
TPS6594_BIT_ESM_SOC_EN | TPS6594_BIT_ESM_SOC_ENDRV);
83
+
if (ret)
84
+
dev_err(dev, "Failed to unconfigure ESM\n");
85
+
86
+
out:
87
+
pm_runtime_put_sync(dev);
88
+
pm_runtime_disable(dev);
89
+
90
+
return ret;
91
+
}
92
+
93
+
static int tps6594_esm_suspend(struct device *dev)
94
+
{
95
+
struct tps6594 *tps = dev_get_drvdata(dev->parent);
96
+
int ret;
97
+
98
+
ret = regmap_clear_bits(tps->regmap, TPS6594_REG_ESM_SOC_START_REG,
99
+
TPS6594_BIT_ESM_SOC_START);
100
+
101
+
pm_runtime_put_sync(dev);
102
+
103
+
return ret;
104
+
}
105
+
106
+
static int tps6594_esm_resume(struct device *dev)
107
+
{
108
+
struct tps6594 *tps = dev_get_drvdata(dev->parent);
109
+
110
+
pm_runtime_get_sync(dev);
111
+
112
+
return regmap_set_bits(tps->regmap, TPS6594_REG_ESM_SOC_START_REG,
113
+
TPS6594_BIT_ESM_SOC_START);
114
+
}
115
+
116
+
static DEFINE_SIMPLE_DEV_PM_OPS(tps6594_esm_pm_ops, tps6594_esm_suspend, tps6594_esm_resume);
117
+
118
+
static struct platform_driver tps6594_esm_driver = {
119
+
.driver = {
120
+
.name = "tps6594-esm",
121
+
.pm = pm_sleep_ptr(&tps6594_esm_pm_ops),
122
+
},
123
+
.probe = tps6594_esm_probe,
124
+
.remove = tps6594_esm_remove,
125
+
};
126
+
127
+
module_platform_driver(tps6594_esm_driver);
128
+
129
+
MODULE_ALIAS("platform:tps6594-esm");
130
+
MODULE_AUTHOR("Julien Panis <jpanis@baylibre.com>");
131
+
MODULE_DESCRIPTION("TPS6594 Error Signal Monitor Driver");
132
+
MODULE_LICENSE("GPL");
+306
drivers/misc/tps6594-pfsm.c
+306
drivers/misc/tps6594-pfsm.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* PFSM (Pre-configurable Finite State Machine) driver for TI TPS6594/TPS6593/LP8764 PMICs
4
+
*
5
+
* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
6
+
*/
7
+
8
+
#include <linux/errno.h>
9
+
#include <linux/fs.h>
10
+
#include <linux/interrupt.h>
11
+
#include <linux/ioctl.h>
12
+
#include <linux/miscdevice.h>
13
+
#include <linux/module.h>
14
+
#include <linux/platform_device.h>
15
+
#include <linux/regmap.h>
16
+
17
+
#include <linux/mfd/tps6594.h>
18
+
19
+
#include <linux/tps6594_pfsm.h>
20
+
21
+
#define TPS6594_STARTUP_DEST_MCU_ONLY_VAL 2
22
+
#define TPS6594_STARTUP_DEST_ACTIVE_VAL 3
23
+
#define TPS6594_STARTUP_DEST_SHIFT 5
24
+
#define TPS6594_STARTUP_DEST_MCU_ONLY (TPS6594_STARTUP_DEST_MCU_ONLY_VAL \
25
+
<< TPS6594_STARTUP_DEST_SHIFT)
26
+
#define TPS6594_STARTUP_DEST_ACTIVE (TPS6594_STARTUP_DEST_ACTIVE_VAL \
27
+
<< TPS6594_STARTUP_DEST_SHIFT)
28
+
29
+
/*
30
+
* To update the PMIC firmware, the user must be able to access
31
+
* page 0 (user registers) and page 1 (NVM control and configuration).
32
+
*/
33
+
#define TPS6594_PMIC_MAX_POS 0x200
34
+
35
+
#define TPS6594_FILE_TO_PFSM(f) container_of((f)->private_data, struct tps6594_pfsm, miscdev)
36
+
37
+
/**
38
+
* struct tps6594_pfsm - device private data structure
39
+
*
40
+
* @miscdev: misc device infos
41
+
* @regmap: regmap for accessing the device registers
42
+
*/
43
+
struct tps6594_pfsm {
44
+
struct miscdevice miscdev;
45
+
struct regmap *regmap;
46
+
};
47
+
48
+
static ssize_t tps6594_pfsm_read(struct file *f, char __user *buf,
49
+
size_t count, loff_t *ppos)
50
+
{
51
+
struct tps6594_pfsm *pfsm = TPS6594_FILE_TO_PFSM(f);
52
+
loff_t pos = *ppos;
53
+
unsigned int val;
54
+
int ret;
55
+
int i;
56
+
57
+
if (pos < 0)
58
+
return -EINVAL;
59
+
if (pos >= TPS6594_PMIC_MAX_POS)
60
+
return 0;
61
+
if (count > TPS6594_PMIC_MAX_POS - pos)
62
+
count = TPS6594_PMIC_MAX_POS - pos;
63
+
64
+
for (i = 0 ; i < count ; i++) {
65
+
ret = regmap_read(pfsm->regmap, pos + i, &val);
66
+
if (ret)
67
+
return ret;
68
+
69
+
if (put_user(val, buf + i))
70
+
return -EFAULT;
71
+
}
72
+
73
+
*ppos = pos + count;
74
+
75
+
return count;
76
+
}
77
+
78
+
static ssize_t tps6594_pfsm_write(struct file *f, const char __user *buf,
79
+
size_t count, loff_t *ppos)
80
+
{
81
+
struct tps6594_pfsm *pfsm = TPS6594_FILE_TO_PFSM(f);
82
+
loff_t pos = *ppos;
83
+
char val;
84
+
int ret;
85
+
int i;
86
+
87
+
if (pos < 0)
88
+
return -EINVAL;
89
+
if (pos >= TPS6594_PMIC_MAX_POS || !count)
90
+
return 0;
91
+
if (count > TPS6594_PMIC_MAX_POS - pos)
92
+
count = TPS6594_PMIC_MAX_POS - pos;
93
+
94
+
for (i = 0 ; i < count ; i++) {
95
+
if (get_user(val, buf + i))
96
+
return -EFAULT;
97
+
98
+
ret = regmap_write(pfsm->regmap, pos + i, val);
99
+
if (ret)
100
+
return ret;
101
+
}
102
+
103
+
*ppos = pos + count;
104
+
105
+
return count;
106
+
}
107
+
108
+
static int tps6594_pfsm_configure_ret_trig(struct regmap *regmap, u8 gpio_ret, u8 ddr_ret)
109
+
{
110
+
int ret;
111
+
112
+
if (gpio_ret)
113
+
ret = regmap_set_bits(regmap, TPS6594_REG_FSM_I2C_TRIGGERS,
114
+
TPS6594_BIT_TRIGGER_I2C(5) | TPS6594_BIT_TRIGGER_I2C(6));
115
+
else
116
+
ret = regmap_clear_bits(regmap, TPS6594_REG_FSM_I2C_TRIGGERS,
117
+
TPS6594_BIT_TRIGGER_I2C(5) | TPS6594_BIT_TRIGGER_I2C(6));
118
+
if (ret)
119
+
return ret;
120
+
121
+
if (ddr_ret)
122
+
ret = regmap_set_bits(regmap, TPS6594_REG_FSM_I2C_TRIGGERS,
123
+
TPS6594_BIT_TRIGGER_I2C(7));
124
+
else
125
+
ret = regmap_clear_bits(regmap, TPS6594_REG_FSM_I2C_TRIGGERS,
126
+
TPS6594_BIT_TRIGGER_I2C(7));
127
+
128
+
return ret;
129
+
}
130
+
131
+
static long tps6594_pfsm_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
132
+
{
133
+
struct tps6594_pfsm *pfsm = TPS6594_FILE_TO_PFSM(f);
134
+
struct pmic_state_opt state_opt;
135
+
void __user *argp = (void __user *)arg;
136
+
int ret = -ENOIOCTLCMD;
137
+
138
+
switch (cmd) {
139
+
case PMIC_GOTO_STANDBY:
140
+
/* Disable LP mode */
141
+
ret = regmap_clear_bits(pfsm->regmap, TPS6594_REG_RTC_CTRL_2,
142
+
TPS6594_BIT_LP_STANDBY_SEL);
143
+
if (ret)
144
+
return ret;
145
+
146
+
/* Force trigger */
147
+
ret = regmap_write_bits(pfsm->regmap, TPS6594_REG_FSM_I2C_TRIGGERS,
148
+
TPS6594_BIT_TRIGGER_I2C(0), TPS6594_BIT_TRIGGER_I2C(0));
149
+
break;
150
+
case PMIC_GOTO_LP_STANDBY:
151
+
/* Enable LP mode */
152
+
ret = regmap_set_bits(pfsm->regmap, TPS6594_REG_RTC_CTRL_2,
153
+
TPS6594_BIT_LP_STANDBY_SEL);
154
+
if (ret)
155
+
return ret;
156
+
157
+
/* Force trigger */
158
+
ret = regmap_write_bits(pfsm->regmap, TPS6594_REG_FSM_I2C_TRIGGERS,
159
+
TPS6594_BIT_TRIGGER_I2C(0), TPS6594_BIT_TRIGGER_I2C(0));
160
+
break;
161
+
case PMIC_UPDATE_PGM:
162
+
/* Force trigger */
163
+
ret = regmap_write_bits(pfsm->regmap, TPS6594_REG_FSM_I2C_TRIGGERS,
164
+
TPS6594_BIT_TRIGGER_I2C(3), TPS6594_BIT_TRIGGER_I2C(3));
165
+
break;
166
+
case PMIC_SET_ACTIVE_STATE:
167
+
/* Modify NSLEEP1-2 bits */
168
+
ret = regmap_set_bits(pfsm->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS,
169
+
TPS6594_BIT_NSLEEP1B | TPS6594_BIT_NSLEEP2B);
170
+
break;
171
+
case PMIC_SET_MCU_ONLY_STATE:
172
+
if (copy_from_user(&state_opt, argp, sizeof(state_opt)))
173
+
return -EFAULT;
174
+
175
+
/* Configure retention triggers */
176
+
ret = tps6594_pfsm_configure_ret_trig(pfsm->regmap, state_opt.gpio_retention,
177
+
state_opt.ddr_retention);
178
+
if (ret)
179
+
return ret;
180
+
181
+
/* Modify NSLEEP1-2 bits */
182
+
ret = regmap_clear_bits(pfsm->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS,
183
+
TPS6594_BIT_NSLEEP1B);
184
+
if (ret)
185
+
return ret;
186
+
187
+
ret = regmap_set_bits(pfsm->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS,
188
+
TPS6594_BIT_NSLEEP2B);
189
+
break;
190
+
case PMIC_SET_RETENTION_STATE:
191
+
if (copy_from_user(&state_opt, argp, sizeof(state_opt)))
192
+
return -EFAULT;
193
+
194
+
/* Configure wake-up destination */
195
+
if (state_opt.mcu_only_startup_dest)
196
+
ret = regmap_write_bits(pfsm->regmap, TPS6594_REG_RTC_CTRL_2,
197
+
TPS6594_MASK_STARTUP_DEST,
198
+
TPS6594_STARTUP_DEST_MCU_ONLY);
199
+
else
200
+
ret = regmap_write_bits(pfsm->regmap, TPS6594_REG_RTC_CTRL_2,
201
+
TPS6594_MASK_STARTUP_DEST,
202
+
TPS6594_STARTUP_DEST_ACTIVE);
203
+
if (ret)
204
+
return ret;
205
+
206
+
/* Configure retention triggers */
207
+
ret = tps6594_pfsm_configure_ret_trig(pfsm->regmap, state_opt.gpio_retention,
208
+
state_opt.ddr_retention);
209
+
if (ret)
210
+
return ret;
211
+
212
+
/* Modify NSLEEP1-2 bits */
213
+
ret = regmap_clear_bits(pfsm->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS,
214
+
TPS6594_BIT_NSLEEP2B);
215
+
break;
216
+
}
217
+
218
+
return ret;
219
+
}
220
+
221
+
static const struct file_operations tps6594_pfsm_fops = {
222
+
.owner = THIS_MODULE,
223
+
.llseek = generic_file_llseek,
224
+
.read = tps6594_pfsm_read,
225
+
.write = tps6594_pfsm_write,
226
+
.unlocked_ioctl = tps6594_pfsm_ioctl,
227
+
.compat_ioctl = compat_ptr_ioctl,
228
+
};
229
+
230
+
static irqreturn_t tps6594_pfsm_isr(int irq, void *dev_id)
231
+
{
232
+
struct platform_device *pdev = dev_id;
233
+
int i;
234
+
235
+
for (i = 0 ; i < pdev->num_resources ; i++) {
236
+
if (irq == platform_get_irq_byname(pdev, pdev->resource[i].name)) {
237
+
dev_err(pdev->dev.parent, "%s event detected\n", pdev->resource[i].name);
238
+
return IRQ_HANDLED;
239
+
}
240
+
}
241
+
242
+
return IRQ_NONE;
243
+
}
244
+
245
+
static int tps6594_pfsm_probe(struct platform_device *pdev)
246
+
{
247
+
struct tps6594_pfsm *pfsm;
248
+
struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent);
249
+
struct device *dev = &pdev->dev;
250
+
int irq;
251
+
int ret;
252
+
int i;
253
+
254
+
pfsm = devm_kzalloc(dev, sizeof(struct tps6594_pfsm), GFP_KERNEL);
255
+
if (!pfsm)
256
+
return -ENOMEM;
257
+
258
+
pfsm->regmap = tps->regmap;
259
+
260
+
pfsm->miscdev.minor = MISC_DYNAMIC_MINOR;
261
+
pfsm->miscdev.name = devm_kasprintf(dev, GFP_KERNEL, "pfsm-%ld-0x%02x",
262
+
tps->chip_id, tps->reg);
263
+
pfsm->miscdev.fops = &tps6594_pfsm_fops;
264
+
pfsm->miscdev.parent = dev->parent;
265
+
266
+
for (i = 0 ; i < pdev->num_resources ; i++) {
267
+
irq = platform_get_irq_byname(pdev, pdev->resource[i].name);
268
+
if (irq < 0)
269
+
return dev_err_probe(dev, irq, "Failed to get %s irq\n",
270
+
pdev->resource[i].name);
271
+
272
+
ret = devm_request_threaded_irq(dev, irq, NULL,
273
+
tps6594_pfsm_isr, IRQF_ONESHOT,
274
+
pdev->resource[i].name, pdev);
275
+
if (ret)
276
+
return dev_err_probe(dev, ret, "Failed to request irq\n");
277
+
}
278
+
279
+
platform_set_drvdata(pdev, pfsm);
280
+
281
+
return misc_register(&pfsm->miscdev);
282
+
}
283
+
284
+
static int tps6594_pfsm_remove(struct platform_device *pdev)
285
+
{
286
+
struct tps6594_pfsm *pfsm = platform_get_drvdata(pdev);
287
+
288
+
misc_deregister(&pfsm->miscdev);
289
+
290
+
return 0;
291
+
}
292
+
293
+
static struct platform_driver tps6594_pfsm_driver = {
294
+
.driver = {
295
+
.name = "tps6594-pfsm",
296
+
},
297
+
.probe = tps6594_pfsm_probe,
298
+
.remove = tps6594_pfsm_remove,
299
+
};
300
+
301
+
module_platform_driver(tps6594_pfsm_driver);
302
+
303
+
MODULE_ALIAS("platform:tps6594-pfsm");
304
+
MODULE_AUTHOR("Julien Panis <jpanis@baylibre.com>");
305
+
MODULE_DESCRIPTION("TPS6594 Pre-configurable Finite State Machine Driver");
306
+
MODULE_LICENSE("GPL");
+1
-1
drivers/misc/tsl2550.c
+1
-1
drivers/misc/tsl2550.c
+14
-11
drivers/misc/uacce/uacce.c
+14
-11
drivers/misc/uacce/uacce.c
···
166
166
167
167
init_waitqueue_head(&q->wait);
168
168
filep->private_data = q;
169
-
uacce->inode = inode;
170
169
q->state = UACCE_Q_INIT;
170
+
q->mapping = filep->f_mapping;
171
171
mutex_init(&q->mutex);
172
172
list_add(&q->list, &uacce->queues);
173
173
mutex_unlock(&uacce->mutex);
···
200
200
static void uacce_vma_close(struct vm_area_struct *vma)
201
201
{
202
202
struct uacce_queue *q = vma->vm_private_data;
203
-
struct uacce_qfile_region *qfr = NULL;
204
203
205
-
if (vma->vm_pgoff < UACCE_MAX_REGION)
206
-
qfr = q->qfrs[vma->vm_pgoff];
204
+
if (vma->vm_pgoff < UACCE_MAX_REGION) {
205
+
struct uacce_qfile_region *qfr = q->qfrs[vma->vm_pgoff];
207
206
208
-
kfree(qfr);
207
+
mutex_lock(&q->mutex);
208
+
q->qfrs[vma->vm_pgoff] = NULL;
209
+
mutex_unlock(&q->mutex);
210
+
kfree(qfr);
211
+
}
209
212
}
210
213
211
214
static const struct vm_operations_struct uacce_vm_ops = {
···
577
574
578
575
if (!uacce)
579
576
return;
580
-
/*
581
-
* unmap remaining mapping from user space, preventing user still
582
-
* access the mmaped area while parent device is already removed
583
-
*/
584
-
if (uacce->inode)
585
-
unmap_mapping_range(uacce->inode->i_mapping, 0, 0, 1);
586
577
587
578
/*
588
579
* uacce_fops_open() may be running concurrently, even after we remove
···
594
597
uacce_put_queue(q);
595
598
mutex_unlock(&q->mutex);
596
599
uacce_unbind_queue(q);
600
+
601
+
/*
602
+
* unmap remaining mapping from user space, preventing user still
603
+
* access the mmaped area while parent device is already removed
604
+
*/
605
+
unmap_mapping_range(q->mapping, 0, 0, 1);
597
606
}
598
607
599
608
/* disable sva now since no opened queues */
-12
drivers/misc/xilinx_sdfec.c
-12
drivers/misc/xilinx_sdfec.c
···
855
855
return 0;
856
856
}
857
857
858
-
static int xsdfec_dev_open(struct inode *iptr, struct file *fptr)
859
-
{
860
-
return 0;
861
-
}
862
-
863
-
static int xsdfec_dev_release(struct inode *iptr, struct file *fptr)
864
-
{
865
-
return 0;
866
-
}
867
-
868
858
static int xsdfec_start(struct xsdfec_dev *xsdfec)
869
859
{
870
860
u32 regread;
···
1020
1030
1021
1031
static const struct file_operations xsdfec_fops = {
1022
1032
.owner = THIS_MODULE,
1023
-
.open = xsdfec_dev_open,
1024
-
.release = xsdfec_dev_release,
1025
1033
.unlocked_ioctl = xsdfec_dev_ioctl,
1026
1034
.poll = xsdfec_poll,
1027
1035
.compat_ioctl = compat_ptr_ioctl,
+1
-1
drivers/mux/Kconfig
+1
-1
drivers/mux/Kconfig
+1
-1
drivers/mux/adg792a.c
+1
-1
drivers/mux/adg792a.c
+1
-1
drivers/mux/mmio.c
+1
-1
drivers/mux/mmio.c
+10
drivers/nvmem/Kconfig
+10
drivers/nvmem/Kconfig
···
55
55
tristate "Broadcom's NVRAM support"
56
56
depends on ARCH_BCM_5301X || COMPILE_TEST
57
57
depends on HAS_IOMEM
58
+
select GENERIC_NET_UTILS
58
59
help
59
60
This driver provides support for Broadcom's NVRAM that can be accessed
60
61
using I/O mapping.
···
82
81
83
82
This driver can also be built as a module. If so, the module
84
83
will be called nvmem-imx-ocotp.
84
+
85
+
config NVMEM_IMX_OCOTP_ELE
86
+
tristate "i.MX On-Chip OTP Controller support"
87
+
depends on ARCH_MXC || COMPILE_TEST
88
+
depends on HAS_IOMEM
89
+
depends on OF
90
+
help
91
+
This is a driver for the On-Chip OTP Controller (OCOTP)
92
+
available on i.MX SoCs which has ELE.
85
93
86
94
config NVMEM_IMX_OCOTP_SCU
87
95
tristate "i.MX8 SCU On-Chip OTP Controller support"
+2
drivers/nvmem/Makefile
+2
drivers/nvmem/Makefile
···
18
18
nvmem-imx-iim-y := imx-iim.o
19
19
obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o
20
20
nvmem-imx-ocotp-y := imx-ocotp.o
21
+
obj-$(CONFIG_NVMEM_IMX_OCOTP_ELE) += nvmem-imx-ocotp-ele.o
22
+
nvmem-imx-ocotp-ele-y := imx-ocotp-ele.o
21
23
obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o
22
24
nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o
23
25
obj-$(CONFIG_NVMEM_JZ4780_EFUSE) += nvmem_jz4780_efuse.o
+28
drivers/nvmem/brcm_nvram.c
+28
drivers/nvmem/brcm_nvram.c
···
4
4
*/
5
5
6
6
#include <linux/bcm47xx_nvram.h>
7
+
#include <linux/etherdevice.h>
8
+
#include <linux/if_ether.h>
7
9
#include <linux/io.h>
8
10
#include <linux/mod_devicetable.h>
9
11
#include <linux/module.h>
···
44
42
return 0;
45
43
}
46
44
45
+
static int brcm_nvram_read_post_process_macaddr(void *context, const char *id, int index,
46
+
unsigned int offset, void *buf, size_t bytes)
47
+
{
48
+
u8 mac[ETH_ALEN];
49
+
50
+
if (bytes != 3 * ETH_ALEN - 1)
51
+
return -EINVAL;
52
+
53
+
if (!mac_pton(buf, mac))
54
+
return -EINVAL;
55
+
56
+
if (index)
57
+
eth_addr_add(mac, index);
58
+
59
+
ether_addr_copy(buf, mac);
60
+
61
+
return 0;
62
+
}
63
+
47
64
static int brcm_nvram_add_cells(struct brcm_nvram *priv, uint8_t *data,
48
65
size_t len)
49
66
{
···
96
75
priv->cells[idx].offset = value - (char *)data;
97
76
priv->cells[idx].bytes = strlen(value);
98
77
priv->cells[idx].np = of_get_child_by_name(dev->of_node, priv->cells[idx].name);
78
+
if (!strcmp(var, "et0macaddr") ||
79
+
!strcmp(var, "et1macaddr") ||
80
+
!strcmp(var, "et2macaddr")) {
81
+
priv->cells[idx].raw_len = strlen(value);
82
+
priv->cells[idx].bytes = ETH_ALEN;
83
+
priv->cells[idx].read_post_process = brcm_nvram_read_post_process_macaddr;
84
+
}
99
85
}
100
86
101
87
return 0;
+29
-3
drivers/nvmem/core.c
+29
-3
drivers/nvmem/core.c
···
696
696
return 0;
697
697
}
698
698
699
-
static int nvmem_add_cells_from_of(struct nvmem_device *nvmem)
699
+
static int nvmem_add_cells_from_dt(struct nvmem_device *nvmem, struct device_node *np)
700
700
{
701
701
struct nvmem_layout *layout = nvmem->layout;
702
702
struct device *dev = &nvmem->dev;
···
704
704
const __be32 *addr;
705
705
int len, ret;
706
706
707
-
for_each_child_of_node(dev->of_node, child) {
707
+
for_each_child_of_node(np, child) {
708
708
struct nvmem_cell_info info = {0};
709
709
710
710
addr = of_get_property(child, "reg", &len);
···
740
740
}
741
741
742
742
return 0;
743
+
}
744
+
745
+
static int nvmem_add_cells_from_legacy_of(struct nvmem_device *nvmem)
746
+
{
747
+
return nvmem_add_cells_from_dt(nvmem, nvmem->dev.of_node);
748
+
}
749
+
750
+
static int nvmem_add_cells_from_fixed_layout(struct nvmem_device *nvmem)
751
+
{
752
+
struct device_node *layout_np;
753
+
int err = 0;
754
+
755
+
layout_np = of_nvmem_layout_get_container(nvmem);
756
+
if (!layout_np)
757
+
return 0;
758
+
759
+
if (of_device_is_compatible(layout_np, "fixed-layout"))
760
+
err = nvmem_add_cells_from_dt(nvmem, layout_np);
761
+
762
+
of_node_put(layout_np);
763
+
764
+
return err;
743
765
}
744
766
745
767
int __nvmem_layout_register(struct nvmem_layout *layout, struct module *owner)
···
994
972
if (rval)
995
973
goto err_remove_cells;
996
974
997
-
rval = nvmem_add_cells_from_of(nvmem);
975
+
rval = nvmem_add_cells_from_legacy_of(nvmem);
998
976
if (rval)
999
977
goto err_remove_cells;
1000
978
1001
979
dev_dbg(&nvmem->dev, "Registering nvmem device %s\n", config->name);
1002
980
1003
981
rval = device_add(&nvmem->dev);
982
+
if (rval)
983
+
goto err_remove_cells;
984
+
985
+
rval = nvmem_add_cells_from_fixed_layout(nvmem);
1004
986
if (rval)
1005
987
goto err_remove_cells;
1006
988
+175
drivers/nvmem/imx-ocotp-ele.c
+175
drivers/nvmem/imx-ocotp-ele.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* i.MX9 OCOTP fusebox driver
4
+
*
5
+
* Copyright 2023 NXP
6
+
*/
7
+
8
+
#include <linux/device.h>
9
+
#include <linux/io.h>
10
+
#include <linux/module.h>
11
+
#include <linux/nvmem-provider.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/platform_device.h>
14
+
#include <linux/slab.h>
15
+
16
+
enum fuse_type {
17
+
FUSE_FSB = 1,
18
+
FUSE_ELE = 2,
19
+
FUSE_INVALID = -1
20
+
};
21
+
22
+
struct ocotp_map_entry {
23
+
u32 start; /* start word */
24
+
u32 num; /* num words */
25
+
enum fuse_type type;
26
+
};
27
+
28
+
struct ocotp_devtype_data {
29
+
u32 reg_off;
30
+
char *name;
31
+
u32 size;
32
+
u32 num_entry;
33
+
u32 flag;
34
+
nvmem_reg_read_t reg_read;
35
+
struct ocotp_map_entry entry[];
36
+
};
37
+
38
+
struct imx_ocotp_priv {
39
+
struct device *dev;
40
+
void __iomem *base;
41
+
struct nvmem_config config;
42
+
struct mutex lock;
43
+
const struct ocotp_devtype_data *data;
44
+
};
45
+
46
+
static enum fuse_type imx_ocotp_fuse_type(void *context, u32 index)
47
+
{
48
+
struct imx_ocotp_priv *priv = context;
49
+
const struct ocotp_devtype_data *data = priv->data;
50
+
u32 start, end;
51
+
int i;
52
+
53
+
for (i = 0; i < data->num_entry; i++) {
54
+
start = data->entry[i].start;
55
+
end = data->entry[i].start + data->entry[i].num;
56
+
57
+
if (index >= start && index < end)
58
+
return data->entry[i].type;
59
+
}
60
+
61
+
return FUSE_INVALID;
62
+
}
63
+
64
+
static int imx_ocotp_reg_read(void *context, unsigned int offset, void *val, size_t bytes)
65
+
{
66
+
struct imx_ocotp_priv *priv = context;
67
+
void __iomem *reg = priv->base + priv->data->reg_off;
68
+
u32 count, index, num_bytes;
69
+
enum fuse_type type;
70
+
u32 *buf;
71
+
void *p;
72
+
int i;
73
+
74
+
index = offset;
75
+
num_bytes = round_up(bytes, 4);
76
+
count = num_bytes >> 2;
77
+
78
+
if (count > ((priv->data->size >> 2) - index))
79
+
count = (priv->data->size >> 2) - index;
80
+
81
+
p = kzalloc(num_bytes, GFP_KERNEL);
82
+
if (!p)
83
+
return -ENOMEM;
84
+
85
+
mutex_lock(&priv->lock);
86
+
87
+
buf = p;
88
+
89
+
for (i = index; i < (index + count); i++) {
90
+
type = imx_ocotp_fuse_type(context, i);
91
+
if (type == FUSE_INVALID || type == FUSE_ELE) {
92
+
*buf++ = 0;
93
+
continue;
94
+
}
95
+
96
+
*buf++ = readl_relaxed(reg + (i << 2));
97
+
}
98
+
99
+
memcpy(val, (u8 *)p, bytes);
100
+
101
+
mutex_unlock(&priv->lock);
102
+
103
+
kfree(p);
104
+
105
+
return 0;
106
+
};
107
+
108
+
static int imx_ele_ocotp_probe(struct platform_device *pdev)
109
+
{
110
+
struct device *dev = &pdev->dev;
111
+
struct imx_ocotp_priv *priv;
112
+
struct nvmem_device *nvmem;
113
+
114
+
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
115
+
if (!priv)
116
+
return -ENOMEM;
117
+
118
+
priv->data = of_device_get_match_data(dev);
119
+
120
+
priv->base = devm_platform_ioremap_resource(pdev, 0);
121
+
if (IS_ERR(priv->base))
122
+
return PTR_ERR(priv->base);
123
+
124
+
priv->config.dev = dev;
125
+
priv->config.name = "ELE-OCOTP";
126
+
priv->config.id = NVMEM_DEVID_AUTO;
127
+
priv->config.owner = THIS_MODULE;
128
+
priv->config.size = priv->data->size;
129
+
priv->config.reg_read = priv->data->reg_read;
130
+
priv->config.word_size = 4;
131
+
priv->config.stride = 1;
132
+
priv->config.priv = priv;
133
+
priv->config.read_only = true;
134
+
mutex_init(&priv->lock);
135
+
136
+
nvmem = devm_nvmem_register(dev, &priv->config);
137
+
if (IS_ERR(nvmem))
138
+
return PTR_ERR(nvmem);
139
+
140
+
return 0;
141
+
}
142
+
143
+
static const struct ocotp_devtype_data imx93_ocotp_data = {
144
+
.reg_off = 0x8000,
145
+
.reg_read = imx_ocotp_reg_read,
146
+
.size = 2048,
147
+
.num_entry = 6,
148
+
.entry = {
149
+
{ 0, 52, FUSE_FSB },
150
+
{ 63, 1, FUSE_ELE},
151
+
{ 128, 16, FUSE_ELE },
152
+
{ 182, 1, FUSE_ELE },
153
+
{ 188, 1, FUSE_ELE },
154
+
{ 312, 200, FUSE_FSB }
155
+
},
156
+
};
157
+
158
+
static const struct of_device_id imx_ele_ocotp_dt_ids[] = {
159
+
{ .compatible = "fsl,imx93-ocotp", .data = &imx93_ocotp_data, },
160
+
{},
161
+
};
162
+
MODULE_DEVICE_TABLE(of, imx_ele_ocotp_dt_ids);
163
+
164
+
static struct platform_driver imx_ele_ocotp_driver = {
165
+
.driver = {
166
+
.name = "imx_ele_ocotp",
167
+
.of_match_table = imx_ele_ocotp_dt_ids,
168
+
},
169
+
.probe = imx_ele_ocotp_probe,
170
+
};
171
+
module_platform_driver(imx_ele_ocotp_driver);
172
+
173
+
MODULE_DESCRIPTION("i.MX OCOTP/ELE driver");
174
+
MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
175
+
MODULE_LICENSE("GPL");
+2
-8
drivers/nvmem/imx-ocotp.c
+2
-8
drivers/nvmem/imx-ocotp.c
···
97
97
unsigned int bank_address_words;
98
98
void (*set_timing)(struct ocotp_priv *priv);
99
99
struct ocotp_ctrl_reg ctrl;
100
-
bool reverse_mac_address;
101
100
};
102
101
103
102
static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
···
544
545
.bank_address_words = 0,
545
546
.set_timing = imx_ocotp_set_imx6_timing,
546
547
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
547
-
.reverse_mac_address = true,
548
548
};
549
549
550
550
static const struct ocotp_params imx8mm_params = {
···
551
553
.bank_address_words = 0,
552
554
.set_timing = imx_ocotp_set_imx6_timing,
553
555
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
554
-
.reverse_mac_address = true,
555
556
};
556
557
557
558
static const struct ocotp_params imx8mn_params = {
···
558
561
.bank_address_words = 0,
559
562
.set_timing = imx_ocotp_set_imx6_timing,
560
563
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
561
-
.reverse_mac_address = true,
562
564
};
563
565
564
566
static const struct ocotp_params imx8mp_params = {
···
565
569
.bank_address_words = 0,
566
570
.set_timing = imx_ocotp_set_imx6_timing,
567
571
.ctrl = IMX_OCOTP_BM_CTRL_8MP,
568
-
.reverse_mac_address = true,
569
572
};
570
573
571
574
static const struct of_device_id imx_ocotp_dt_ids[] = {
···
591
596
cell->read_post_process = imx_ocotp_cell_pp;
592
597
}
593
598
594
-
struct nvmem_layout imx_ocotp_layout = {
599
+
static struct nvmem_layout imx_ocotp_layout = {
595
600
.fixup_cell_info = imx_ocotp_fixup_cell_info,
596
601
};
597
602
···
619
624
imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
620
625
imx_ocotp_nvmem_config.dev = dev;
621
626
imx_ocotp_nvmem_config.priv = priv;
622
-
if (priv->params->reverse_mac_address)
623
-
imx_ocotp_nvmem_config.layout = &imx_ocotp_layout;
627
+
imx_ocotp_nvmem_config.layout = &imx_ocotp_layout;
624
628
625
629
priv->config = &imx_ocotp_nvmem_config;
626
630
+1
drivers/nvmem/rmem.c
+1
drivers/nvmem/rmem.c
+145
-48
drivers/nvmem/rockchip-otp.c
+145
-48
drivers/nvmem/rockchip-otp.c
···
54
54
55
55
#define OTPC_TIMEOUT 10000
56
56
57
-
struct rockchip_otp {
58
-
struct device *dev;
59
-
void __iomem *base;
60
-
struct clk_bulk_data *clks;
61
-
int num_clks;
62
-
struct reset_control *rst;
63
-
};
64
-
65
-
/* list of required clocks */
66
-
static const char * const rockchip_otp_clocks[] = {
67
-
"otp", "apb_pclk", "phy",
68
-
};
57
+
/* RK3588 Register */
58
+
#define RK3588_OTPC_AUTO_CTRL 0x04
59
+
#define RK3588_OTPC_AUTO_EN 0x08
60
+
#define RK3588_OTPC_INT_ST 0x84
61
+
#define RK3588_OTPC_DOUT0 0x20
62
+
#define RK3588_NO_SECURE_OFFSET 0x300
63
+
#define RK3588_NBYTES 4
64
+
#define RK3588_BURST_NUM 1
65
+
#define RK3588_BURST_SHIFT 8
66
+
#define RK3588_ADDR_SHIFT 16
67
+
#define RK3588_AUTO_EN BIT(0)
68
+
#define RK3588_RD_DONE BIT(1)
69
69
70
70
struct rockchip_data {
71
71
int size;
72
+
const char * const *clks;
73
+
int num_clks;
74
+
nvmem_reg_read_t reg_read;
75
+
};
76
+
77
+
struct rockchip_otp {
78
+
struct device *dev;
79
+
void __iomem *base;
80
+
struct clk_bulk_data *clks;
81
+
struct reset_control *rst;
82
+
const struct rockchip_data *data;
72
83
};
73
84
74
85
static int rockchip_otp_reset(struct rockchip_otp *otp)
···
103
92
return 0;
104
93
}
105
94
106
-
static int rockchip_otp_wait_status(struct rockchip_otp *otp, u32 flag)
95
+
static int rockchip_otp_wait_status(struct rockchip_otp *otp,
96
+
unsigned int reg, u32 flag)
107
97
{
108
98
u32 status = 0;
109
99
int ret;
110
100
111
-
ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status,
101
+
ret = readl_poll_timeout_atomic(otp->base + reg, status,
112
102
(status & flag), 1, OTPC_TIMEOUT);
113
103
if (ret)
114
104
return ret;
115
105
116
106
/* clean int status */
117
-
writel(flag, otp->base + OTPC_INT_STATUS);
107
+
writel(flag, otp->base + reg);
118
108
119
109
return 0;
120
110
}
···
137
125
138
126
writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL);
139
127
140
-
ret = rockchip_otp_wait_status(otp, OTPC_SBPI_DONE);
128
+
ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_SBPI_DONE);
141
129
if (ret < 0)
142
130
dev_err(otp->dev, "timeout during ecc_enable\n");
143
131
144
132
return ret;
145
133
}
146
134
147
-
static int rockchip_otp_read(void *context, unsigned int offset,
148
-
void *val, size_t bytes)
135
+
static int px30_otp_read(void *context, unsigned int offset,
136
+
void *val, size_t bytes)
149
137
{
150
138
struct rockchip_otp *otp = context;
151
139
u8 *buf = val;
152
-
int ret = 0;
153
-
154
-
ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
155
-
if (ret < 0) {
156
-
dev_err(otp->dev, "failed to prepare/enable clks\n");
157
-
return ret;
158
-
}
140
+
int ret;
159
141
160
142
ret = rockchip_otp_reset(otp);
161
143
if (ret) {
162
144
dev_err(otp->dev, "failed to reset otp phy\n");
163
-
goto disable_clks;
145
+
return ret;
164
146
}
165
147
166
148
ret = rockchip_otp_ecc_enable(otp, false);
167
149
if (ret < 0) {
168
150
dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
169
-
goto disable_clks;
151
+
return ret;
170
152
}
171
153
172
154
writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
···
170
164
otp->base + OTPC_USER_ADDR);
171
165
writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
172
166
otp->base + OTPC_USER_ENABLE);
173
-
ret = rockchip_otp_wait_status(otp, OTPC_USER_DONE);
167
+
ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE);
174
168
if (ret < 0) {
175
169
dev_err(otp->dev, "timeout during read setup\n");
176
170
goto read_end;
···
180
174
181
175
read_end:
182
176
writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
183
-
disable_clks:
184
-
clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
177
+
178
+
return ret;
179
+
}
180
+
181
+
static int rk3588_otp_read(void *context, unsigned int offset,
182
+
void *val, size_t bytes)
183
+
{
184
+
struct rockchip_otp *otp = context;
185
+
unsigned int addr_start, addr_end, addr_len;
186
+
int ret, i = 0;
187
+
u32 data;
188
+
u8 *buf;
189
+
190
+
addr_start = round_down(offset, RK3588_NBYTES) / RK3588_NBYTES;
191
+
addr_end = round_up(offset + bytes, RK3588_NBYTES) / RK3588_NBYTES;
192
+
addr_len = addr_end - addr_start;
193
+
addr_start += RK3588_NO_SECURE_OFFSET;
194
+
195
+
buf = kzalloc(array_size(addr_len, RK3588_NBYTES), GFP_KERNEL);
196
+
if (!buf)
197
+
return -ENOMEM;
198
+
199
+
while (addr_len--) {
200
+
writel((addr_start << RK3588_ADDR_SHIFT) |
201
+
(RK3588_BURST_NUM << RK3588_BURST_SHIFT),
202
+
otp->base + RK3588_OTPC_AUTO_CTRL);
203
+
writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN);
204
+
205
+
ret = rockchip_otp_wait_status(otp, RK3588_OTPC_INT_ST,
206
+
RK3588_RD_DONE);
207
+
if (ret < 0) {
208
+
dev_err(otp->dev, "timeout during read setup\n");
209
+
goto read_end;
210
+
}
211
+
212
+
data = readl(otp->base + RK3588_OTPC_DOUT0);
213
+
memcpy(&buf[i], &data, RK3588_NBYTES);
214
+
215
+
i += RK3588_NBYTES;
216
+
addr_start++;
217
+
}
218
+
219
+
memcpy(val, buf + offset % RK3588_NBYTES, bytes);
220
+
221
+
read_end:
222
+
kfree(buf);
223
+
224
+
return ret;
225
+
}
226
+
227
+
static int rockchip_otp_read(void *context, unsigned int offset,
228
+
void *val, size_t bytes)
229
+
{
230
+
struct rockchip_otp *otp = context;
231
+
int ret;
232
+
233
+
if (!otp->data || !otp->data->reg_read)
234
+
return -EINVAL;
235
+
236
+
ret = clk_bulk_prepare_enable(otp->data->num_clks, otp->clks);
237
+
if (ret < 0) {
238
+
dev_err(otp->dev, "failed to prepare/enable clks\n");
239
+
return ret;
240
+
}
241
+
242
+
ret = otp->data->reg_read(context, offset, val, bytes);
243
+
244
+
clk_bulk_disable_unprepare(otp->data->num_clks, otp->clks);
185
245
186
246
return ret;
187
247
}
···
261
189
.reg_read = rockchip_otp_read,
262
190
};
263
191
192
+
static const char * const px30_otp_clocks[] = {
193
+
"otp", "apb_pclk", "phy",
194
+
};
195
+
264
196
static const struct rockchip_data px30_data = {
265
197
.size = 0x40,
198
+
.clks = px30_otp_clocks,
199
+
.num_clks = ARRAY_SIZE(px30_otp_clocks),
200
+
.reg_read = px30_otp_read,
201
+
};
202
+
203
+
static const char * const rk3588_otp_clocks[] = {
204
+
"otp", "apb_pclk", "phy", "arb",
205
+
};
206
+
207
+
static const struct rockchip_data rk3588_data = {
208
+
.size = 0x400,
209
+
.clks = rk3588_otp_clocks,
210
+
.num_clks = ARRAY_SIZE(rk3588_otp_clocks),
211
+
.reg_read = rk3588_otp_read,
266
212
};
267
213
268
214
static const struct of_device_id rockchip_otp_match[] = {
269
215
{
270
216
.compatible = "rockchip,px30-otp",
271
-
.data = (void *)&px30_data,
217
+
.data = &px30_data,
272
218
},
273
219
{
274
220
.compatible = "rockchip,rk3308-otp",
275
-
.data = (void *)&px30_data,
221
+
.data = &px30_data,
222
+
},
223
+
{
224
+
.compatible = "rockchip,rk3588-otp",
225
+
.data = &rk3588_data,
276
226
},
277
227
{ /* sentinel */ },
278
228
};
···
309
215
int ret, i;
310
216
311
217
data = of_device_get_match_data(dev);
312
-
if (!data) {
313
-
dev_err(dev, "failed to get match data\n");
314
-
return -EINVAL;
315
-
}
218
+
if (!data)
219
+
return dev_err_probe(dev, -EINVAL, "failed to get match data\n");
316
220
317
221
otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp),
318
222
GFP_KERNEL);
319
223
if (!otp)
320
224
return -ENOMEM;
321
225
226
+
otp->data = data;
322
227
otp->dev = dev;
323
228
otp->base = devm_platform_ioremap_resource(pdev, 0);
324
229
if (IS_ERR(otp->base))
325
-
return PTR_ERR(otp->base);
230
+
return dev_err_probe(dev, PTR_ERR(otp->base),
231
+
"failed to ioremap resource\n");
326
232
327
-
otp->num_clks = ARRAY_SIZE(rockchip_otp_clocks);
328
-
otp->clks = devm_kcalloc(dev, otp->num_clks,
329
-
sizeof(*otp->clks), GFP_KERNEL);
233
+
otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks),
234
+
GFP_KERNEL);
330
235
if (!otp->clks)
331
236
return -ENOMEM;
332
237
333
-
for (i = 0; i < otp->num_clks; ++i)
334
-
otp->clks[i].id = rockchip_otp_clocks[i];
238
+
for (i = 0; i < data->num_clks; ++i)
239
+
otp->clks[i].id = data->clks[i];
335
240
336
-
ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks);
241
+
ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks);
337
242
if (ret)
338
-
return ret;
243
+
return dev_err_probe(dev, ret, "failed to get clocks\n");
339
244
340
-
otp->rst = devm_reset_control_get(dev, "phy");
245
+
otp->rst = devm_reset_control_array_get_exclusive(dev);
341
246
if (IS_ERR(otp->rst))
342
-
return PTR_ERR(otp->rst);
247
+
return dev_err_probe(dev, PTR_ERR(otp->rst),
248
+
"failed to get resets\n");
343
249
344
250
otp_config.size = data->size;
345
251
otp_config.priv = otp;
346
252
otp_config.dev = dev;
347
-
nvmem = devm_nvmem_register(dev, &otp_config);
348
253
349
-
return PTR_ERR_OR_ZERO(nvmem);
254
+
nvmem = devm_nvmem_register(dev, &otp_config);
255
+
if (IS_ERR(nvmem))
256
+
return dev_err_probe(dev, PTR_ERR(nvmem),
257
+
"failed to register nvmem device\n");
258
+
return 0;
350
259
}
351
260
352
261
static struct platform_driver rockchip_otp_driver = {
+7
-2
drivers/nvmem/sunplus-ocotp.c
+7
-2
drivers/nvmem/sunplus-ocotp.c
···
192
192
sp_ocotp_nvmem_config.dev = dev;
193
193
194
194
nvmem = devm_nvmem_register(dev, &sp_ocotp_nvmem_config);
195
-
if (IS_ERR(nvmem))
196
-
return dev_err_probe(&pdev->dev, PTR_ERR(nvmem),
195
+
if (IS_ERR(nvmem)) {
196
+
ret = dev_err_probe(&pdev->dev, PTR_ERR(nvmem),
197
197
"register nvmem device fail\n");
198
+
goto err;
199
+
}
198
200
199
201
platform_set_drvdata(pdev, nvmem);
200
202
···
205
203
(int)OTP_WORD_SIZE, (int)QAC628_OTP_SIZE);
206
204
207
205
return 0;
206
+
err:
207
+
clk_unprepare(otp->clk);
208
+
return ret;
208
209
}
209
210
210
211
static const struct of_device_id sp_ocotp_dt_ids[] = {
+1
-1
drivers/nvmem/zynqmp_nvmem.c
+1
-1
drivers/nvmem/zynqmp_nvmem.c
···
76
76
77
77
module_platform_driver(zynqmp_nvmem_driver);
78
78
79
-
MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>, Nava kishore Manne <navam@xilinx.com>");
79
+
MODULE_AUTHOR("Michal Simek <michal.simek@amd.com>, Nava kishore Manne <nava.kishore.manne@amd.com>");
80
80
MODULE_DESCRIPTION("ZynqMP NVMEM driver");
81
81
MODULE_LICENSE("GPL");
+2
-1
drivers/parport/Kconfig
+2
-1
drivers/parport/Kconfig
···
42
42
43
43
config PARPORT_PC
44
44
tristate "PC-style hardware"
45
-
depends on ARCH_MIGHT_HAVE_PC_PARPORT || (PCI && !S390)
45
+
depends on ARCH_MIGHT_HAVE_PC_PARPORT || PCI
46
+
depends on HAS_IOPORT
46
47
help
47
48
You should say Y here if you have a PC-style parallel port. All
48
49
IBM PC compatible computers and some Alphas have PC-style
+2
-3
drivers/pcmcia/Kconfig
+2
-3
drivers/pcmcia/Kconfig
···
5
5
6
6
menuconfig PCCARD
7
7
tristate "PCCard (PCMCIA/CardBus) support"
8
-
depends on !UML
9
8
help
10
9
Say Y here if you want to attach PCMCIA- or PC-cards to your Linux
11
10
computer. These are credit-card size devices such as network cards,
···
112
113
113
114
config PD6729
114
115
tristate "Cirrus PD6729 compatible bridge support"
115
-
depends on PCMCIA && PCI
116
+
depends on PCMCIA && PCI && HAS_IOPORT
116
117
select PCCARD_NONSTATIC
117
118
help
118
119
This provides support for the Cirrus PD6729 PCI-to-PCMCIA bridge
···
120
121
121
122
config I82092
122
123
tristate "i82092 compatible bridge support"
123
-
depends on PCMCIA && PCI
124
+
depends on PCMCIA && PCI && HAS_IOPORT
124
125
select PCCARD_NONSTATIC
125
126
help
126
127
This provides support for the Intel I82092AA PCI-to-PCMCIA bridge device,
+2
drivers/pcmcia/rsrc_nonstatic.c
+2
drivers/pcmcia/rsrc_nonstatic.c
+10
-11
drivers/sbus/char/oradax.c
+10
-11
drivers/sbus/char/oradax.c
···
226
226
static int dax_ccb_kill(u64 ca, u16 *kill_res);
227
227
228
228
static struct cdev c_dev;
229
-
static struct class *cl;
230
229
static dev_t first;
230
+
static const struct class cl = {
231
+
.name = DAX_NAME,
232
+
};
231
233
232
234
static int max_ccb_version;
233
235
static int dax_debug;
···
325
323
goto done;
326
324
}
327
325
328
-
cl = class_create(DAX_NAME);
329
-
if (IS_ERR(cl)) {
330
-
dax_err("class_create failed");
331
-
ret = PTR_ERR(cl);
326
+
ret = class_register(&cl);
327
+
if (ret)
332
328
goto class_error;
333
-
}
334
329
335
-
if (device_create(cl, NULL, first, NULL, dax_name) == NULL) {
330
+
if (device_create(&cl, NULL, first, NULL, dax_name) == NULL) {
336
331
dax_err("device_create failed");
337
332
ret = -ENXIO;
338
333
goto device_error;
···
346
347
goto done;
347
348
348
349
cdev_error:
349
-
device_destroy(cl, first);
350
+
device_destroy(&cl, first);
350
351
device_error:
351
-
class_destroy(cl);
352
+
class_unregister(&cl);
352
353
class_error:
353
354
unregister_chrdev_region(first, 1);
354
355
done:
···
361
362
{
362
363
pr_info("Cleaning up DAX module\n");
363
364
cdev_del(&c_dev);
364
-
device_destroy(cl, first);
365
-
class_destroy(cl);
365
+
device_destroy(&cl, first);
366
+
class_unregister(&cl);
366
367
unregister_chrdev_region(first, 1);
367
368
}
368
369
module_exit(dax_detach);
+1
-1
drivers/staging/iio/addac/adt7316-i2c.c
+1
-1
drivers/staging/iio/addac/adt7316-i2c.c
+1
-1
drivers/staging/iio/impedance-analyzer/ad5933.c
+1
-1
drivers/staging/iio/impedance-analyzer/ad5933.c
+2
drivers/uio/uio_dfl.c
+2
drivers/uio/uio_dfl.c
···
46
46
47
47
#define FME_FEATURE_ID_ETH_GROUP 0x10
48
48
#define FME_FEATURE_ID_HSSI_SUBSYS 0x15
49
+
#define FME_FEATURE_ID_VENDOR_SPECIFIC 0x23
49
50
#define PORT_FEATURE_ID_IOPLL_USRCLK 0x14
50
51
51
52
static const struct dfl_device_id uio_dfl_ids[] = {
52
53
{ FME_ID, FME_FEATURE_ID_ETH_GROUP },
53
54
{ FME_ID, FME_FEATURE_ID_HSSI_SUBSYS },
55
+
{ FME_ID, FME_FEATURE_ID_VENDOR_SPECIFIC },
54
56
{ PORT_ID, PORT_FEATURE_ID_IOPLL_USRCLK },
55
57
{ }
56
58
};
+1
-1
drivers/w1/masters/sgi_w1.c
+1
-1
drivers/w1/masters/sgi_w1.c
+2
-2
drivers/w1/slaves/Kconfig
+2
-2
drivers/w1/slaves/Kconfig
···
71
71
help
72
72
Say Y here if you want to use a 1-wire
73
73
is a 112-byte user-programmable EEPROM is
74
-
organized as 7 pages of 16 bytes each with 64bit
75
-
unique number. Requires OverDrive Speed to talk to.
74
+
organized as 7 pages of 16 bytes each with 64bit
75
+
unique number. Requires OverDrive Speed to talk to.
76
76
77
77
config W1_SLAVE_DS2430
78
78
tristate "256b EEPROM family support (DS2430)"
-2
drivers/w1/slaves/w1_ds2438.c
-2
drivers/w1/slaves/w1_ds2438.c
+17
-20
drivers/w1/slaves/w1_therm.c
+17
-20
drivers/w1/slaves/w1_therm.c
···
284
284
* trigger_bulk_read() - function to trigger a bulk read on the bus
285
285
* @dev_master: the device master of the bus
286
286
*
287
-
* Send a SKIP ROM follow by a CONVERT T commmand on the bus.
287
+
* Send a SKIP ROM follow by a CONVERT T command on the bus.
288
288
* It also set the status flag in each slave &struct w1_therm_family_data
289
289
* to signal that a conversion is in progress.
290
290
*
···
454
454
.config = w1_temp_config,
455
455
};
456
456
457
-
static const struct hwmon_channel_info *w1_info[] = {
457
+
static const struct hwmon_channel_info * const w1_info[] = {
458
458
&w1_temp,
459
459
NULL
460
460
};
···
1159
1159
1160
1160
w1_write_8(dev_master, W1_CONVERT_TEMP);
1161
1161
1162
-
if (strong_pullup) { /*some device need pullup */
1162
+
if (SLAVE_FEATURES(sl) & W1_THERM_POLL_COMPLETION) {
1163
+
ret = w1_poll_completion(dev_master, W1_POLL_CONVERT_TEMP);
1164
+
if (ret) {
1165
+
dev_dbg(&sl->dev, "%s: Timeout\n", __func__);
1166
+
goto mt_unlock;
1167
+
}
1168
+
mutex_unlock(&dev_master->bus_mutex);
1169
+
} else if (!strong_pullup) { /*no device need pullup */
1163
1170
sleep_rem = msleep_interruptible(t_conv);
1164
1171
if (sleep_rem != 0) {
1165
1172
ret = -EINTR;
1166
1173
goto mt_unlock;
1167
1174
}
1168
1175
mutex_unlock(&dev_master->bus_mutex);
1169
-
} else { /*no device need pullup */
1170
-
if (SLAVE_FEATURES(sl) & W1_THERM_POLL_COMPLETION) {
1171
-
ret = w1_poll_completion(dev_master, W1_POLL_CONVERT_TEMP);
1172
-
if (ret) {
1173
-
dev_dbg(&sl->dev, "%s: Timeout\n", __func__);
1174
-
goto mt_unlock;
1175
-
}
1176
-
mutex_unlock(&dev_master->bus_mutex);
1177
-
} else {
1178
-
/* Fixed delay */
1179
-
mutex_unlock(&dev_master->bus_mutex);
1180
-
sleep_rem = msleep_interruptible(t_conv);
1181
-
if (sleep_rem != 0) {
1182
-
ret = -EINTR;
1183
-
goto dec_refcnt;
1184
-
}
1176
+
} else { /*some device need pullup */
1177
+
mutex_unlock(&dev_master->bus_mutex);
1178
+
sleep_rem = msleep_interruptible(t_conv);
1179
+
if (sleep_rem != 0) {
1180
+
ret = -EINTR;
1181
+
goto dec_refcnt;
1185
1182
}
1186
1183
}
1187
1184
ret = read_scratchpad(sl, info);
···
1512
1515
if (bulk_read_support(sl)) {
1513
1516
int t_cur = conversion_time(sl);
1514
1517
1515
-
t_conv = t_cur > t_conv ? t_cur : t_conv;
1518
+
t_conv = max(t_cur, t_conv);
1516
1519
strong_pullup = strong_pullup ||
1517
1520
(w1_strong_pullup == 2 ||
1518
1521
(!SLAVE_POWERMODE(sl) &&
+22
-33
drivers/w1/w1.c
+22
-33
drivers/w1/w1.c
···
32
32
module_param_named(timeout, w1_timeout, int, 0);
33
33
MODULE_PARM_DESC(timeout, "time in seconds between automatic slave searches");
34
34
35
-
static int w1_timeout_us = 0;
35
+
static int w1_timeout_us;
36
36
module_param_named(timeout_us, w1_timeout_us, int, 0);
37
37
MODULE_PARM_DESC(timeout_us,
38
38
"time in microseconds between automatic slave searches");
···
57
57
58
58
DEFINE_MUTEX(w1_mlock);
59
59
LIST_HEAD(w1_masters);
60
-
61
-
static int w1_master_match(struct device *dev, struct device_driver *drv)
62
-
{
63
-
return 1;
64
-
}
65
60
66
61
static int w1_master_probe(struct device *dev)
67
62
{
···
169
174
170
175
static struct bus_type w1_bus_type = {
171
176
.name = "w1",
172
-
.match = w1_master_match,
173
177
.uevent = w1_uevent,
174
178
};
175
179
···
295
301
296
302
static ssize_t w1_master_attribute_show_timeout(struct device *dev, struct device_attribute *attr, char *buf)
297
303
{
298
-
ssize_t count;
299
-
count = sprintf(buf, "%d\n", w1_timeout);
300
-
return count;
304
+
return sprintf(buf, "%d\n", w1_timeout);
301
305
}
302
306
303
307
static ssize_t w1_master_attribute_show_timeout_us(struct device *dev,
304
308
struct device_attribute *attr, char *buf)
305
309
{
306
-
ssize_t count;
307
-
count = sprintf(buf, "%d\n", w1_timeout_us);
308
-
return count;
310
+
return sprintf(buf, "%d\n", w1_timeout_us);
309
311
}
310
312
311
313
static ssize_t w1_master_attribute_store_max_slave_count(struct device *dev,
···
491
501
struct w1_master *md = dev_to_w1_master(dev);
492
502
struct w1_reg_num rn;
493
503
struct w1_slave *sl;
494
-
ssize_t result = count;
504
+
ssize_t result;
495
505
496
506
if (w1_atoreg_num(dev, buf, count, &rn))
497
507
return -EINVAL;
···
692
702
dev_err(&sl->dev,
693
703
"Device registration [%s] failed. err=%d\n",
694
704
dev_name(&sl->dev), err);
705
+
of_node_put(sl->dev.of_node);
695
706
put_device(&sl->dev);
696
707
return err;
697
708
}
···
821
830
822
831
struct w1_master *w1_search_master_id(u32 id)
823
832
{
824
-
struct w1_master *dev;
825
-
int found = 0;
833
+
struct w1_master *dev = NULL, *iter;
826
834
827
835
mutex_lock(&w1_mlock);
828
-
list_for_each_entry(dev, &w1_masters, w1_master_entry) {
829
-
if (dev->id == id) {
830
-
found = 1;
831
-
atomic_inc(&dev->refcnt);
836
+
list_for_each_entry(iter, &w1_masters, w1_master_entry) {
837
+
if (iter->id == id) {
838
+
dev = iter;
839
+
atomic_inc(&iter->refcnt);
832
840
break;
833
841
}
834
842
}
835
843
mutex_unlock(&w1_mlock);
836
844
837
-
return (found)?dev:NULL;
845
+
return dev;
838
846
}
839
847
840
848
struct w1_slave *w1_search_slave(struct w1_reg_num *id)
841
849
{
842
850
struct w1_master *dev;
843
-
struct w1_slave *sl = NULL;
844
-
int found = 0;
851
+
struct w1_slave *sl = NULL, *iter;
845
852
846
853
mutex_lock(&w1_mlock);
847
854
list_for_each_entry(dev, &w1_masters, w1_master_entry) {
848
855
mutex_lock(&dev->list_mutex);
849
-
list_for_each_entry(sl, &dev->slist, w1_slave_entry) {
850
-
if (sl->reg_num.family == id->family &&
851
-
sl->reg_num.id == id->id &&
852
-
sl->reg_num.crc == id->crc) {
853
-
found = 1;
856
+
list_for_each_entry(iter, &dev->slist, w1_slave_entry) {
857
+
if (iter->reg_num.family == id->family &&
858
+
iter->reg_num.id == id->id &&
859
+
iter->reg_num.crc == id->crc) {
860
+
sl = iter;
854
861
atomic_inc(&dev->refcnt);
855
-
atomic_inc(&sl->refcnt);
862
+
atomic_inc(&iter->refcnt);
856
863
break;
857
864
}
858
865
}
859
866
mutex_unlock(&dev->list_mutex);
860
867
861
-
if (found)
868
+
if (sl)
862
869
break;
863
870
}
864
871
mutex_unlock(&w1_mlock);
865
872
866
-
return (found)?sl:NULL;
873
+
return sl;
867
874
}
868
875
869
876
void w1_reconnect_slaves(struct w1_family *f, int attach)
···
1252
1263
1253
1264
static void __exit w1_fini(void)
1254
1265
{
1255
-
struct w1_master *dev;
1266
+
struct w1_master *dev, *n;
1256
1267
1257
1268
/* Set netlink removal messages and some cleanup */
1258
-
list_for_each_entry(dev, &w1_masters, w1_master_entry)
1269
+
list_for_each_entry_safe(dev, n, &w1_masters, w1_master_entry)
1259
1270
__w1_remove_master_device(dev);
1260
1271
1261
1272
w1_fini_netlink();
+12
include/dt-bindings/interconnect/qcom,msm8996-cbf.h
+12
include/dt-bindings/interconnect/qcom,msm8996-cbf.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (C) 2023 Linaro Ltd. All rights reserved.
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H
7
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H
8
+
9
+
#define MASTER_CBF_M4M 0
10
+
#define SLAVE_CBF_M4M 1
11
+
12
+
#endif
+62
include/dt-bindings/mux/ti-serdes.h
+62
include/dt-bindings/mux/ti-serdes.h
···
117
117
#define J721S2_SERDES0_LANE3_USB 0x2
118
118
#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3
119
119
120
+
/* J784S4 */
121
+
122
+
#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0
123
+
#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1
124
+
#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2
125
+
#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3
126
+
127
+
#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0
128
+
#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1
129
+
#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2
130
+
#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3
131
+
132
+
#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0
133
+
#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1
134
+
#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2
135
+
#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3
136
+
137
+
#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0
138
+
#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1
139
+
#define J784S4_SERDES0_LANE3_USB 0x2
140
+
#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3
141
+
142
+
#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0
143
+
#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1
144
+
#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2
145
+
#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3
146
+
147
+
#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0
148
+
#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1
149
+
#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2
150
+
#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3
151
+
152
+
#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0
153
+
#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1
154
+
#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2
155
+
#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3
156
+
157
+
#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0
158
+
#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1
159
+
#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2
160
+
#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3
161
+
162
+
#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0
163
+
#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1
164
+
#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2
165
+
#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3
166
+
167
+
#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0
168
+
#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1
169
+
#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2
170
+
#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3
171
+
172
+
#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0
173
+
#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1
174
+
#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2
175
+
#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3
176
+
177
+
#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0
178
+
#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1
179
+
#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2
180
+
#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3
181
+
120
182
#endif /* _DT_BINDINGS_MUX_TI_SERDES */
+1
-1
include/linux/amba/bus.h
+1
-1
include/linux/amba/bus.h
···
107
107
108
108
extern struct bus_type amba_bustype;
109
109
110
-
#define to_amba_device(d) container_of(d, struct amba_device, dev)
110
+
#define to_amba_device(d) container_of_const(d, struct amba_device, dev)
111
111
112
112
#define amba_get_drvdata(d) dev_get_drvdata(&d->dev)
113
113
#define amba_set_drvdata(d,p) dev_set_drvdata(&d->dev, p)
+78
-49
include/linux/coresight.h
+78
-49
include/linux/coresight.h
···
41
41
CORESIGHT_DEV_TYPE_LINKSINK,
42
42
CORESIGHT_DEV_TYPE_SOURCE,
43
43
CORESIGHT_DEV_TYPE_HELPER,
44
-
CORESIGHT_DEV_TYPE_ECT,
44
+
CORESIGHT_DEV_TYPE_MAX
45
45
};
46
46
47
47
enum coresight_dev_subtype_sink {
48
+
CORESIGHT_DEV_SUBTYPE_SINK_DUMMY,
48
49
CORESIGHT_DEV_SUBTYPE_SINK_PORT,
49
50
CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
50
51
CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
···
67
66
68
67
enum coresight_dev_subtype_helper {
69
68
CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
70
-
};
71
-
72
-
/* Embedded Cross Trigger (ECT) sub-types */
73
-
enum coresight_dev_subtype_ect {
74
-
CORESIGHT_DEV_SUBTYPE_ECT_NONE,
75
-
CORESIGHT_DEV_SUBTYPE_ECT_CTI,
69
+
CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI
76
70
};
77
71
78
72
/**
···
80
84
* by @coresight_dev_subtype_source.
81
85
* @helper_subtype: type of helper this component is, as defined
82
86
* by @coresight_dev_subtype_helper.
83
-
* @ect_subtype: type of cross trigger this component is, as
84
-
* defined by @coresight_dev_subtype_ect
85
87
*/
86
88
union coresight_dev_subtype {
87
89
/* We have some devices which acts as LINK and SINK */
···
89
95
};
90
96
enum coresight_dev_subtype_source source_subtype;
91
97
enum coresight_dev_subtype_helper helper_subtype;
92
-
enum coresight_dev_subtype_ect ect_subtype;
93
98
};
94
99
95
100
/**
96
101
* struct coresight_platform_data - data harvested from the firmware
97
102
* specification.
98
103
*
99
-
* @nr_inport: Number of elements for the input connections.
100
-
* @nr_outport: Number of elements for the output connections.
101
-
* @conns: Sparse array of nr_outport connections from this component.
104
+
* @nr_inconns: Number of elements for the input connections.
105
+
* @nr_outconns: Number of elements for the output connections.
106
+
* @out_conns: Array of nr_outconns pointers to connections from this
107
+
* component.
108
+
* @in_conns: Sparse array of pointers to input connections. Sparse
109
+
* because the source device owns the connection so when it's
110
+
* unloaded the connection leaves an empty slot.
102
111
*/
103
112
struct coresight_platform_data {
104
-
int nr_inport;
105
-
int nr_outport;
106
-
struct coresight_connection *conns;
113
+
int nr_inconns;
114
+
int nr_outconns;
115
+
struct coresight_connection **out_conns;
116
+
struct coresight_connection **in_conns;
107
117
};
108
118
109
119
/**
···
162
164
163
165
/**
164
166
* struct coresight_connection - representation of a single connection
165
-
* @outport: a connection's output port number.
166
-
* @child_port: remote component's port number @output is connected to.
167
-
* @chid_fwnode: remote component's fwnode handle.
168
-
* @child_dev: a @coresight_device representation of the component
169
-
connected to @outport.
167
+
* @src_port: a connection's output port number.
168
+
* @dest_port: destination's input port number @src_port is connected to.
169
+
* @dest_fwnode: destination component's fwnode handle.
170
+
* @dest_dev: a @coresight_device representation of the component
171
+
connected to @src_port. NULL until the device is created
170
172
* @link: Representation of the connection as a sysfs link.
173
+
*
174
+
* The full connection structure looks like this, where in_conns store
175
+
* references to same connection as the source device's out_conns.
176
+
*
177
+
* +-----------------------------+ +-----------------------------+
178
+
* |coresight_device | |coresight_connection |
179
+
* |-----------------------------| |-----------------------------|
180
+
* | | | |
181
+
* | | | dest_dev*|<--
182
+
* |pdata->out_conns[nr_outconns]|<->|src_dev* | |
183
+
* | | | | |
184
+
* +-----------------------------+ +-----------------------------+ |
185
+
* |
186
+
* +-----------------------------+ |
187
+
* |coresight_device | |
188
+
* |------------------------------ |
189
+
* | | |
190
+
* | pdata->in_conns[nr_inconns]|<--
191
+
* | |
192
+
* +-----------------------------+
171
193
*/
172
194
struct coresight_connection {
173
-
int outport;
174
-
int child_port;
175
-
struct fwnode_handle *child_fwnode;
176
-
struct coresight_device *child_dev;
195
+
int src_port;
196
+
int dest_port;
197
+
struct fwnode_handle *dest_fwnode;
198
+
struct coresight_device *dest_dev;
177
199
struct coresight_sysfs_link *link;
200
+
struct coresight_device *src_dev;
201
+
atomic_t src_refcnt;
202
+
atomic_t dest_refcnt;
178
203
};
179
204
180
205
/**
···
232
211
* from source to that sink.
233
212
* @ea: Device attribute for sink representation under PMU directory.
234
213
* @def_sink: cached reference to default sink found for this device.
235
-
* @ect_dev: Associated cross trigger device. Not part of the trace data
236
-
* path or connections.
237
214
* @nr_links: number of sysfs links created to other components from this
238
215
* device. These will appear in the "connections" group.
239
216
* @has_conns_grp: Have added a "connections" group for sysfs links.
···
247
228
const struct coresight_ops *ops;
248
229
struct csdev_access access;
249
230
struct device dev;
250
-
atomic_t *refcnt;
231
+
atomic_t refcnt;
251
232
bool orphan;
252
233
bool enable; /* true only if configured as part of a path */
253
234
/* sink specific fields */
254
235
bool activated; /* true only if a sink is part of a path */
255
236
struct dev_ext_attribute *ea;
256
237
struct coresight_device *def_sink;
257
-
/* cross trigger handling */
258
-
struct coresight_device *ect_dev;
259
238
/* sysfs links between components */
260
239
int nr_links;
261
240
bool has_conns_grp;
262
-
bool ect_enabled; /* true only if associated ect device is enabled */
263
241
/* system configuration and feature lists */
264
242
struct list_head feature_csdev_list;
265
243
struct list_head config_csdev_list;
···
288
272
289
273
#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
290
274
275
+
enum cs_mode {
276
+
CS_MODE_DISABLED,
277
+
CS_MODE_SYSFS,
278
+
CS_MODE_PERF,
279
+
};
280
+
291
281
#define source_ops(csdev) csdev->ops->source_ops
292
282
#define sink_ops(csdev) csdev->ops->sink_ops
293
283
#define link_ops(csdev) csdev->ops->link_ops
···
310
288
* @update_buffer: update buffer pointers after a trace session.
311
289
*/
312
290
struct coresight_ops_sink {
313
-
int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
291
+
int (*enable)(struct coresight_device *csdev, enum cs_mode mode,
292
+
void *data);
314
293
int (*disable)(struct coresight_device *csdev);
315
294
void *(*alloc_buffer)(struct coresight_device *csdev,
316
295
struct perf_event *event, void **pages,
···
329
306
* @disable: disables flow between iport and oport.
330
307
*/
331
308
struct coresight_ops_link {
332
-
int (*enable)(struct coresight_device *csdev, int iport, int oport);
333
-
void (*disable)(struct coresight_device *csdev, int iport, int oport);
309
+
int (*enable)(struct coresight_device *csdev,
310
+
struct coresight_connection *in,
311
+
struct coresight_connection *out);
312
+
void (*disable)(struct coresight_device *csdev,
313
+
struct coresight_connection *in,
314
+
struct coresight_connection *out);
334
315
};
335
316
336
317
/**
···
347
320
*/
348
321
struct coresight_ops_source {
349
322
int (*cpu_id)(struct coresight_device *csdev);
350
-
int (*enable)(struct coresight_device *csdev,
351
-
struct perf_event *event, u32 mode);
323
+
int (*enable)(struct coresight_device *csdev, struct perf_event *event,
324
+
enum cs_mode mode);
352
325
void (*disable)(struct coresight_device *csdev,
353
326
struct perf_event *event);
354
327
};
···
363
336
* @disable : Disable the device
364
337
*/
365
338
struct coresight_ops_helper {
366
-
int (*enable)(struct coresight_device *csdev, void *data);
339
+
int (*enable)(struct coresight_device *csdev, enum cs_mode mode,
340
+
void *data);
367
341
int (*disable)(struct coresight_device *csdev, void *data);
368
-
};
369
-
370
-
/**
371
-
* struct coresight_ops_ect - Ops for an embedded cross trigger device
372
-
*
373
-
* @enable : Enable the device
374
-
* @disable : Disable the device
375
-
*/
376
-
struct coresight_ops_ect {
377
-
int (*enable)(struct coresight_device *csdev);
378
-
int (*disable)(struct coresight_device *csdev);
379
342
};
380
343
381
344
struct coresight_ops {
···
373
356
const struct coresight_ops_link *link_ops;
374
357
const struct coresight_ops_source *source_ops;
375
358
const struct coresight_ops_helper *helper_ops;
376
-
const struct coresight_ops_ect *ect_ops;
377
359
};
378
360
379
361
#if IS_ENABLED(CONFIG_CORESIGHT)
···
618
602
extern int coresight_get_cpu(struct device *dev);
619
603
620
604
struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
605
+
struct coresight_connection *
606
+
coresight_add_out_conn(struct device *dev,
607
+
struct coresight_platform_data *pdata,
608
+
const struct coresight_connection *new_conn);
609
+
int coresight_add_in_conn(struct coresight_connection *conn);
610
+
struct coresight_device *
611
+
coresight_find_input_type(struct coresight_platform_data *pdata,
612
+
enum coresight_dev_type type,
613
+
union coresight_dev_subtype subtype);
614
+
struct coresight_device *
615
+
coresight_find_output_type(struct coresight_platform_data *pdata,
616
+
enum coresight_dev_type type,
617
+
union coresight_dev_subtype subtype);
621
618
622
619
#endif /* _LINUX_COREISGHT_H */
+11
include/linux/device.h
+11
include/linux/device.h
···
223
223
{
224
224
return devm_kmalloc_array(dev, n, size, flags | __GFP_ZERO);
225
225
}
226
+
static inline __realloc_size(3, 4) void * __must_check
227
+
devm_krealloc_array(struct device *dev, void *p, size_t new_n, size_t new_size, gfp_t flags)
228
+
{
229
+
size_t bytes;
230
+
231
+
if (unlikely(check_mul_overflow(new_n, new_size, &bytes)))
232
+
return NULL;
233
+
234
+
return devm_krealloc(dev, p, bytes, flags);
235
+
}
236
+
226
237
void devm_kfree(struct device *dev, const void *p);
227
238
char *devm_kstrdup(struct device *dev, const char *s, gfp_t gfp) __malloc;
228
239
const char *devm_kstrdup_const(struct device *dev, const char *s, gfp_t gfp);
+1
-1
include/linux/firmware/xlnx-zynqmp.h
+1
-1
include/linux/firmware/xlnx-zynqmp.h
+21
include/linux/i8254.h
+21
include/linux/i8254.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/* Copyright (C) William Breathitt Gray */
3
+
#ifndef _I8254_H_
4
+
#define _I8254_H_
5
+
6
+
struct device;
7
+
struct regmap;
8
+
9
+
/**
10
+
* struct i8254_regmap_config - Configuration for the register map of an i8254
11
+
* @parent: parent device
12
+
* @map: regmap for the i8254
13
+
*/
14
+
struct i8254_regmap_config {
15
+
struct device *parent;
16
+
struct regmap *map;
17
+
};
18
+
19
+
int devm_i8254_regmap_register(struct device *dev, const struct i8254_regmap_config *config);
20
+
21
+
#endif /* _I8254_H_ */
+1
include/linux/iio/common/st_sensors.h
+1
include/linux/iio/common/st_sensors.h
+3
include/linux/iio/iio.h
+3
include/linux/iio/iio.h
···
221
221
* @extend_name: Allows labeling of channel attributes with an
222
222
* informative name. Note this has no effect codes etc,
223
223
* unlike modifiers.
224
+
* This field is deprecated in favour of providing
225
+
* iio_info->read_label() to override the label, which
226
+
* unlike @extend_name does not affect sysfs filenames.
224
227
* @datasheet_name: A name used in in-kernel mapping of channels. It should
225
228
* correspond to the first name that the channel is referred
226
229
* to by in the datasheet (e.g. IND), or the nearest
+1
include/linux/iio/trigger.h
+1
include/linux/iio/trigger.h
+22
include/linux/interconnect-clk.h
+22
include/linux/interconnect-clk.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Ltd.
4
+
*/
5
+
6
+
#ifndef __LINUX_INTERCONNECT_CLK_H
7
+
#define __LINUX_INTERCONNECT_CLK_H
8
+
9
+
struct device;
10
+
11
+
struct icc_clk_data {
12
+
struct clk *clk;
13
+
const char *name;
14
+
};
15
+
16
+
struct icc_provider *icc_clk_register(struct device *dev,
17
+
unsigned int first_id,
18
+
unsigned int num_clocks,
19
+
const struct icc_clk_data *data);
20
+
void icc_clk_unregister(struct icc_provider *provider);
21
+
22
+
#endif
-8
include/linux/interconnect.h
-8
include/linux/interconnect.h
···
40
40
41
41
#if IS_ENABLED(CONFIG_INTERCONNECT)
42
42
43
-
struct icc_path *icc_get(struct device *dev, const int src_id,
44
-
const int dst_id);
45
43
struct icc_path *of_icc_get(struct device *dev, const char *name);
46
44
struct icc_path *devm_of_icc_get(struct device *dev, const char *name);
47
45
int devm_of_icc_bulk_get(struct device *dev, int num_paths, struct icc_bulk_data *paths);
···
58
60
void icc_bulk_disable(int num_paths, const struct icc_bulk_data *paths);
59
61
60
62
#else
61
-
62
-
static inline struct icc_path *icc_get(struct device *dev, const int src_id,
63
-
const int dst_id)
64
-
{
65
-
return NULL;
66
-
}
67
63
68
64
static inline struct icc_path *of_icc_get(struct device *dev,
69
65
const char *name)
+1
-1
include/linux/parport.h
+1
-1
include/linux/parport.h
···
516
516
extern int parport_device_proc_unregister(struct pardevice *device);
517
517
518
518
/* If PC hardware is the only type supported, we can optimise a bit. */
519
-
#if !defined(CONFIG_PARPORT_NOT_PC)
519
+
#if !defined(CONFIG_PARPORT_NOT_PC) && defined(CONFIG_PARPORT_PC)
520
520
521
521
#include <linux/parport_pc.h>
522
522
#define parport_write_data(p,x) parport_pc_write_data(p,x)
+1
-1
include/linux/platform_data/st_sensors_pdata.h
+1
-1
include/linux/platform_data/st_sensors_pdata.h
···
15
15
* @drdy_int_pin: Redirect DRDY on pin 1 (1) or pin 2 (2).
16
16
* Available only for accelerometer, magnetometer and pressure sensors.
17
17
* Accelerometer DRDY on LSM330 available only on pin 1 (see datasheet).
18
-
* Magnetometer DRDY is supported only on LSM9DS0.
18
+
* Magnetometer DRDY is supported only on LSM9DS0 and LSM303D.
19
19
* @open_drain: set the interrupt line to be open drain if possible.
20
20
* @spi_3wire: enable spi-3wire mode.
21
21
* @pullups: enable/disable i2c controller pullup resistors.
+2
-2
include/linux/uacce.h
+2
-2
include/linux/uacce.h
···
86
86
* @state: queue state machine
87
87
* @pasid: pasid associated to the mm
88
88
* @handle: iommu_sva handle returned by iommu_sva_bind_device()
89
+
* @mapping: user space mapping of the queue
89
90
*/
90
91
struct uacce_queue {
91
92
struct uacce_device *uacce;
···
98
97
enum uacce_q_state state;
99
98
u32 pasid;
100
99
struct iommu_sva *handle;
100
+
struct address_space *mapping;
101
101
};
102
102
103
103
/**
···
116
114
* @mutex: protects uacce operation
117
115
* @priv: private pointer of the uacce
118
116
* @queues: list of queues
119
-
* @inode: core vfs
120
117
*/
121
118
struct uacce_device {
122
119
const char *algs;
···
131
130
struct mutex mutex;
132
131
void *priv;
133
132
struct list_head queues;
134
-
struct inode *inode;
135
133
};
136
134
137
135
#if IS_ENABLED(CONFIG_UACCE)
+6
include/uapi/linux/counter.h
+6
include/uapi/linux/counter.h
···
127
127
COUNTER_COUNT_MODE_RANGE_LIMIT,
128
128
COUNTER_COUNT_MODE_NON_RECYCLE,
129
129
COUNTER_COUNT_MODE_MODULO_N,
130
+
COUNTER_COUNT_MODE_INTERRUPT_ON_TERMINAL_COUNT,
131
+
COUNTER_COUNT_MODE_HARDWARE_RETRIGGERABLE_ONESHOT,
132
+
COUNTER_COUNT_MODE_RATE_GENERATOR,
133
+
COUNTER_COUNT_MODE_SQUARE_WAVE_MODE,
134
+
COUNTER_COUNT_MODE_SOFTWARE_TRIGGERED_STROBE,
135
+
COUNTER_COUNT_MODE_HARDWARE_TRIGGERED_STROBE,
130
136
};
131
137
132
138
/* Count function values */
+37
include/uapi/linux/tps6594_pfsm.h
+37
include/uapi/linux/tps6594_pfsm.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2
+
/*
3
+
* Userspace ABI for TPS6594 PMIC Pre-configurable Finite State Machine
4
+
*
5
+
* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
6
+
*/
7
+
8
+
#ifndef __TPS6594_PFSM_H
9
+
#define __TPS6594_PFSM_H
10
+
11
+
#include <linux/const.h>
12
+
#include <linux/ioctl.h>
13
+
#include <linux/types.h>
14
+
15
+
/**
16
+
* struct pmic_state_opt - PMIC state options
17
+
* @gpio_retention: if enabled, power rails associated with GPIO retention remain active
18
+
* @ddr_retention: if enabled, power rails associated with DDR retention remain active
19
+
* @mcu_only_startup_dest: if enabled, startup destination state is MCU_ONLY
20
+
*/
21
+
struct pmic_state_opt {
22
+
__u8 gpio_retention;
23
+
__u8 ddr_retention;
24
+
__u8 mcu_only_startup_dest;
25
+
};
26
+
27
+
/* Commands */
28
+
#define PMIC_BASE 'P'
29
+
30
+
#define PMIC_GOTO_STANDBY _IO(PMIC_BASE, 0)
31
+
#define PMIC_GOTO_LP_STANDBY _IO(PMIC_BASE, 1)
32
+
#define PMIC_UPDATE_PGM _IO(PMIC_BASE, 2)
33
+
#define PMIC_SET_ACTIVE_STATE _IO(PMIC_BASE, 3)
34
+
#define PMIC_SET_MCU_ONLY_STATE _IOW(PMIC_BASE, 4, struct pmic_state_opt)
35
+
#define PMIC_SET_RETENTION_STATE _IOW(PMIC_BASE, 5, struct pmic_state_opt)
36
+
37
+
#endif /* __TPS6594_PFSM_H */
+6
-6
lib/test_firmware.c
+6
-6
lib/test_firmware.c
···
214
214
{
215
215
*dst = kstrndup(name, count, gfp);
216
216
if (!*dst)
217
-
return -ENOSPC;
217
+
return -ENOMEM;
218
218
return count;
219
219
}
220
220
···
671
671
672
672
name = kstrndup(buf, count, GFP_KERNEL);
673
673
if (!name)
674
-
return -ENOSPC;
674
+
return -ENOMEM;
675
675
676
676
pr_info("loading '%s'\n", name);
677
677
···
719
719
720
720
name = kstrndup(buf, count, GFP_KERNEL);
721
721
if (!name)
722
-
return -ENOSPC;
722
+
return -ENOMEM;
723
723
724
724
pr_info("inserting test platform fw '%s'\n", name);
725
725
efi_embedded_fw.name = name;
···
772
772
773
773
name = kstrndup(buf, count, GFP_KERNEL);
774
774
if (!name)
775
-
return -ENOSPC;
775
+
return -ENOMEM;
776
776
777
777
pr_info("loading '%s'\n", name);
778
778
···
817
817
818
818
name = kstrndup(buf, count, GFP_KERNEL);
819
819
if (!name)
820
-
return -ENOSPC;
820
+
return -ENOMEM;
821
821
822
822
pr_info("loading '%s' using custom fallback mechanism\n", name);
823
823
···
868
868
869
869
test_buf = kzalloc(TEST_FIRMWARE_BUF_SIZE, GFP_KERNEL);
870
870
if (!test_buf)
871
-
return -ENOSPC;
871
+
return -ENOMEM;
872
872
873
873
if (test_fw_config->partial)
874
874
req->rc = request_partial_firmware_into_buf
+7
samples/Kconfig
+7
samples/Kconfig
···
253
253
help
254
254
Build a sample program to work with mei device.
255
255
256
+
config SAMPLE_TPS6594_PFSM
257
+
bool "Build example program working with TPS6594 PFSM driver"
258
+
depends on HEADERS_INSTALL
259
+
depends on CC_CAN_LINK
260
+
help
261
+
Build a sample program to work with PFSM devices.
262
+
256
263
config SAMPLE_WATCHDOG
257
264
bool "watchdog sample"
258
265
depends on CC_CAN_LINK
+1
samples/Makefile
+1
samples/Makefile
···
31
31
obj-y += vfio-mdev/
32
32
subdir-$(CONFIG_SAMPLE_VFS) += vfs
33
33
obj-$(CONFIG_SAMPLE_INTEL_MEI) += mei/
34
+
obj-$(CONFIG_SAMPLE_TPS6594_PFSM) += pfsm/
34
35
subdir-$(CONFIG_SAMPLE_WATCHDOG) += watchdog
35
36
subdir-$(CONFIG_SAMPLE_WATCH_QUEUE) += watch_queue
36
37
obj-$(CONFIG_SAMPLE_KMEMLEAK) += kmemleak/
+4
samples/pfsm/Makefile
+4
samples/pfsm/Makefile
+125
samples/pfsm/pfsm-wakeup.c
+125
samples/pfsm/pfsm-wakeup.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* TPS6594 PFSM userspace example
4
+
*
5
+
* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
6
+
*
7
+
* This example shows how to use PFSMs from a userspace application,
8
+
* on TI j721s2 platform. The PMIC is armed to be triggered by a RTC
9
+
* alarm to execute state transition (RETENTION to ACTIVE).
10
+
*/
11
+
12
+
#include <fcntl.h>
13
+
#include <stdio.h>
14
+
#include <sys/ioctl.h>
15
+
#include <unistd.h>
16
+
17
+
#include <linux/rtc.h>
18
+
#include <linux/tps6594_pfsm.h>
19
+
20
+
#define ALARM_DELTA_SEC 30
21
+
22
+
#define RTC_A "/dev/rtc0"
23
+
24
+
#define PMIC_NB 3
25
+
#define PMIC_A "/dev/pfsm-0-0x48"
26
+
#define PMIC_B "/dev/pfsm-0-0x4c"
27
+
#define PMIC_C "/dev/pfsm-2-0x58"
28
+
29
+
static const char * const dev_pfsm[] = {PMIC_A, PMIC_B, PMIC_C};
30
+
31
+
int main(int argc, char *argv[])
32
+
{
33
+
int i, ret, fd_rtc, fd_pfsm[PMIC_NB] = { 0 };
34
+
struct rtc_time rtc_tm;
35
+
struct pmic_state_opt pmic_opt = { 0 };
36
+
unsigned long data;
37
+
38
+
fd_rtc = open(RTC_A, O_RDONLY);
39
+
if (fd_rtc < 0) {
40
+
perror("Failed to open RTC device.");
41
+
goto out;
42
+
}
43
+
44
+
for (i = 0 ; i < PMIC_NB ; i++) {
45
+
fd_pfsm[i] = open(dev_pfsm[i], O_RDWR);
46
+
if (fd_pfsm[i] < 0) {
47
+
perror("Failed to open PFSM device.");
48
+
goto out;
49
+
}
50
+
}
51
+
52
+
/* Read RTC date/time */
53
+
ret = ioctl(fd_rtc, RTC_RD_TIME, &rtc_tm);
54
+
if (ret < 0) {
55
+
perror("Failed to read RTC date/time.");
56
+
goto out;
57
+
}
58
+
printf("Current RTC date/time is %d-%d-%d, %02d:%02d:%02d.\n",
59
+
rtc_tm.tm_mday, rtc_tm.tm_mon + 1, rtc_tm.tm_year + 1900,
60
+
rtc_tm.tm_hour, rtc_tm.tm_min, rtc_tm.tm_sec);
61
+
62
+
/* Set RTC alarm to ALARM_DELTA_SEC sec in the future, and check for rollover */
63
+
rtc_tm.tm_sec += ALARM_DELTA_SEC;
64
+
if (rtc_tm.tm_sec >= 60) {
65
+
rtc_tm.tm_sec %= 60;
66
+
rtc_tm.tm_min++;
67
+
}
68
+
if (rtc_tm.tm_min == 60) {
69
+
rtc_tm.tm_min = 0;
70
+
rtc_tm.tm_hour++;
71
+
}
72
+
if (rtc_tm.tm_hour == 24)
73
+
rtc_tm.tm_hour = 0;
74
+
ret = ioctl(fd_rtc, RTC_ALM_SET, &rtc_tm);
75
+
if (ret < 0) {
76
+
perror("Failed to set RTC alarm.");
77
+
goto out;
78
+
}
79
+
80
+
/* Enable alarm interrupts */
81
+
ret = ioctl(fd_rtc, RTC_AIE_ON, 0);
82
+
if (ret < 0) {
83
+
perror("Failed to enable alarm interrupts.");
84
+
goto out;
85
+
}
86
+
printf("Waiting %d seconds for alarm...\n", ALARM_DELTA_SEC);
87
+
88
+
/*
89
+
* Set RETENTION state with options for PMIC_C/B/A respectively.
90
+
* Since PMIC_A is master, it should be the last one to be configured.
91
+
*/
92
+
pmic_opt.ddr_retention = 1;
93
+
for (i = PMIC_NB - 1 ; i >= 0 ; i--) {
94
+
printf("Set RETENTION state for PMIC_%d.\n", i);
95
+
sleep(1);
96
+
ret = ioctl(fd_pfsm[i], PMIC_SET_RETENTION_STATE, &pmic_opt);
97
+
if (ret < 0) {
98
+
perror("Failed to set RETENTION state.");
99
+
goto out_reset;
100
+
}
101
+
}
102
+
103
+
/* This blocks until the alarm ring causes an interrupt */
104
+
ret = read(fd_rtc, &data, sizeof(unsigned long));
105
+
if (ret < 0)
106
+
perror("Failed to get RTC alarm.");
107
+
else
108
+
puts("Alarm rang.\n");
109
+
110
+
out_reset:
111
+
ioctl(fd_rtc, RTC_AIE_OFF, 0);
112
+
113
+
/* Set ACTIVE state for PMIC_A */
114
+
ioctl(fd_pfsm[0], PMIC_SET_ACTIVE_STATE, 0);
115
+
116
+
out:
117
+
for (i = 0 ; i < PMIC_NB ; i++)
118
+
if (fd_pfsm[i])
119
+
close(fd_pfsm[i]);
120
+
121
+
if (fd_rtc)
122
+
close(fd_rtc);
123
+
124
+
return 0;
125
+
}