drm/amd/display: Move commit_planes_to_stream to amdgpu_dm

+103 -5

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 3977 3977 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 3978 3978 } 3979 3979 3980 + /* 3981 + * TODO this whole function needs to go 3982 + * 3983 + * dc_surface_update is needlessly complex. See if we can just replace this 3984 + * with a dc_plane_state and follow the atomic model a bit more closely here. 3985 + */ 3986 + static bool commit_planes_to_stream( 3987 + struct dc *dc, 3988 + struct dc_plane_state **plane_states, 3989 + uint8_t new_plane_count, 3990 + struct dm_crtc_state *dm_new_crtc_state, 3991 + struct dm_crtc_state *dm_old_crtc_state, 3992 + struct dc_state *state) 3993 + { 3994 + /* no need to dynamically allocate this. it's pretty small */ 3995 + struct dc_surface_update updates[MAX_SURFACES]; 3996 + struct dc_flip_addrs *flip_addr; 3997 + struct dc_plane_info *plane_info; 3998 + struct dc_scaling_info *scaling_info; 3999 + int i; 4000 + struct dc_stream_state *dc_stream = dm_new_crtc_state->stream; 4001 + struct dc_stream_update *stream_update = 4002 + kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL); 4003 + 4004 + if (!stream_update) { 4005 + BREAK_TO_DEBUGGER(); 4006 + return false; 4007 + } 4008 + 4009 + flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs), 4010 + GFP_KERNEL); 4011 + plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info), 4012 + GFP_KERNEL); 4013 + scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info), 4014 + GFP_KERNEL); 4015 + 4016 + if (!flip_addr || !plane_info || !scaling_info) { 4017 + kfree(flip_addr); 4018 + kfree(plane_info); 4019 + kfree(scaling_info); 4020 + kfree(stream_update); 4021 + return false; 4022 + } 4023 + 4024 + memset(updates, 0, sizeof(updates)); 4025 + 4026 + stream_update->src = dc_stream->src; 4027 + stream_update->dst = dc_stream->dst; 4028 + stream_update->out_transfer_func = dc_stream->out_transfer_func; 4029 + 4030 + for (i = 0; i < new_plane_count; i++) { 4031 + updates[i].surface = plane_states[i]; 4032 + updates[i].gamma = 4033 + (struct dc_gamma *)plane_states[i]->gamma_correction; 4034 + updates[i].in_transfer_func = plane_states[i]->in_transfer_func; 4035 + flip_addr[i].address = plane_states[i]->address; 4036 + flip_addr[i].flip_immediate = plane_states[i]->flip_immediate; 4037 + plane_info[i].color_space = plane_states[i]->color_space; 4038 + plane_info[i].input_tf = plane_states[i]->input_tf; 4039 + plane_info[i].format = plane_states[i]->format; 4040 + plane_info[i].plane_size = plane_states[i]->plane_size; 4041 + plane_info[i].rotation = plane_states[i]->rotation; 4042 + plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror; 4043 + plane_info[i].stereo_format = plane_states[i]->stereo_format; 4044 + plane_info[i].tiling_info = plane_states[i]->tiling_info; 4045 + plane_info[i].visible = plane_states[i]->visible; 4046 + plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha; 4047 + plane_info[i].dcc = plane_states[i]->dcc; 4048 + scaling_info[i].scaling_quality = plane_states[i]->scaling_quality; 4049 + scaling_info[i].src_rect = plane_states[i]->src_rect; 4050 + scaling_info[i].dst_rect = plane_states[i]->dst_rect; 4051 + scaling_info[i].clip_rect = plane_states[i]->clip_rect; 4052 + 4053 + updates[i].flip_addr = &flip_addr[i]; 4054 + updates[i].plane_info = &plane_info[i]; 4055 + updates[i].scaling_info = &scaling_info[i]; 4056 + } 4057 + 4058 + dc_commit_updates_for_stream( 4059 + dc, 4060 + updates, 4061 + new_plane_count, 4062 + dc_stream, stream_update, plane_states, state); 4063 + 4064 + kfree(flip_addr); 4065 + kfree(plane_info); 4066 + kfree(scaling_info); 4067 + kfree(stream_update); 4068 + return true; 4069 + } 4070 + 3980 4071 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 3981 4072 struct drm_device *dev, 3982 4073 struct amdgpu_display_manager *dm, ··· 4083 3992 struct drm_crtc_state *new_pcrtc_state = 4084 3993 drm_atomic_get_new_crtc_state(state, pcrtc); 4085 3994 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 3995 + struct dm_crtc_state *dm_old_crtc_state = 3996 + to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 4086 3997 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 4087 3998 int planes_count = 0; 4088 3999 unsigned long flags; ··· 4163 4070 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4164 4071 } 4165 4072 4166 - if (false == dc_commit_planes_to_stream(dm->dc, 4073 + 4074 + if (false == commit_planes_to_stream(dm->dc, 4167 4075 plane_states_constructed, 4168 4076 planes_count, 4169 - dc_stream_attach, 4077 + acrtc_state, 4078 + dm_old_crtc_state, 4170 4079 dm_state->context)) 4171 4080 dm_error("%s: Failed to attach plane!\n", __func__); 4172 4081 } else { ··· 4393 4298 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 4394 4299 struct dc_stream_status *status = NULL; 4395 4300 4396 - if (acrtc) 4301 + if (acrtc) { 4397 4302 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 4303 + old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4304 + } 4398 4305 4399 4306 /* Skip any modesets/resets */ 4400 4307 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) ··· 4419 4322 WARN_ON(!status->plane_count); 4420 4323 4421 4324 /*TODO How it works with MPO ?*/ 4422 - if (!dc_commit_planes_to_stream( 4325 + if (!commit_planes_to_stream( 4423 4326 dm->dc, 4424 4327 status->plane_states, 4425 4328 status->plane_count, 4426 - dm_new_crtc_state->stream, 4329 + dm_new_crtc_state, 4330 + to_dm_crtc_state(old_crtc_state), 4427 4331 dm_state->context)) 4428 4332 dm_error("%s: Failed to update stream scaling!\n", __func__); 4429 4333 }

-89

drivers/gpu/drm/amd/display/dc/core/dc.c

··· 936 936 return true; 937 937 } 938 938 939 - /* 940 - * TODO this whole function needs to go 941 - * 942 - * dc_surface_update is needlessly complex. See if we can just replace this 943 - * with a dc_plane_state and follow the atomic model a bit more closely here. 944 - */ 945 - bool dc_commit_planes_to_stream( 946 - struct dc *dc, 947 - struct dc_plane_state **plane_states, 948 - uint8_t new_plane_count, 949 - struct dc_stream_state *dc_stream, 950 - struct dc_state *state) 951 - { 952 - /* no need to dynamically allocate this. it's pretty small */ 953 - struct dc_surface_update updates[MAX_SURFACES]; 954 - struct dc_flip_addrs *flip_addr; 955 - struct dc_plane_info *plane_info; 956 - struct dc_scaling_info *scaling_info; 957 - int i; 958 - struct dc_stream_update *stream_update = 959 - kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL); 960 - 961 - if (!stream_update) { 962 - BREAK_TO_DEBUGGER(); 963 - return false; 964 - } 965 - 966 - flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs), 967 - GFP_KERNEL); 968 - plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info), 969 - GFP_KERNEL); 970 - scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info), 971 - GFP_KERNEL); 972 - 973 - if (!flip_addr || !plane_info || !scaling_info) { 974 - kfree(flip_addr); 975 - kfree(plane_info); 976 - kfree(scaling_info); 977 - kfree(stream_update); 978 - return false; 979 - } 980 - 981 - memset(updates, 0, sizeof(updates)); 982 - 983 - stream_update->src = dc_stream->src; 984 - stream_update->dst = dc_stream->dst; 985 - stream_update->out_transfer_func = dc_stream->out_transfer_func; 986 - 987 - for (i = 0; i < new_plane_count; i++) { 988 - updates[i].surface = plane_states[i]; 989 - updates[i].gamma = 990 - (struct dc_gamma *)plane_states[i]->gamma_correction; 991 - updates[i].in_transfer_func = plane_states[i]->in_transfer_func; 992 - flip_addr[i].address = plane_states[i]->address; 993 - flip_addr[i].flip_immediate = plane_states[i]->flip_immediate; 994 - plane_info[i].color_space = plane_states[i]->color_space; 995 - plane_info[i].input_tf = plane_states[i]->input_tf; 996 - plane_info[i].format = plane_states[i]->format; 997 - plane_info[i].plane_size = plane_states[i]->plane_size; 998 - plane_info[i].rotation = plane_states[i]->rotation; 999 - plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror; 1000 - plane_info[i].stereo_format = plane_states[i]->stereo_format; 1001 - plane_info[i].tiling_info = plane_states[i]->tiling_info; 1002 - plane_info[i].visible = plane_states[i]->visible; 1003 - plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha; 1004 - plane_info[i].dcc = plane_states[i]->dcc; 1005 - scaling_info[i].scaling_quality = plane_states[i]->scaling_quality; 1006 - scaling_info[i].src_rect = plane_states[i]->src_rect; 1007 - scaling_info[i].dst_rect = plane_states[i]->dst_rect; 1008 - scaling_info[i].clip_rect = plane_states[i]->clip_rect; 1009 - 1010 - updates[i].flip_addr = &flip_addr[i]; 1011 - updates[i].plane_info = &plane_info[i]; 1012 - updates[i].scaling_info = &scaling_info[i]; 1013 - } 1014 - 1015 - dc_commit_updates_for_stream( 1016 - dc, 1017 - updates, 1018 - new_plane_count, 1019 - dc_stream, stream_update, plane_states, state); 1020 - 1021 - kfree(flip_addr); 1022 - kfree(plane_info); 1023 - kfree(scaling_info); 1024 - kfree(stream_update); 1025 - return true; 1026 - } 1027 - 1028 939 struct dc_state *dc_create_state(void) 1029 940 { 1030 941 struct dc_state *context = kzalloc(sizeof(struct dc_state),

-7

drivers/gpu/drm/amd/display/dc/dc_stream.h

··· 135 135 * This does not trigger a flip. No surface address is programmed. 136 136 */ 137 137 138 - bool dc_commit_planes_to_stream( 139 - struct dc *dc, 140 - struct dc_plane_state **plane_states, 141 - uint8_t new_plane_count, 142 - struct dc_stream_state *dc_stream, 143 - struct dc_state *state); 144 - 145 138 void dc_commit_updates_for_stream(struct dc *dc, 146 139 struct dc_surface_update *srf_updates, 147 140 int surface_count,

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