Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann:
"This is the final small set of ARM SoC bug fixes for linux-4.4, almost
all regressions:
OMAP:
- data corruption on the Nokia N900 flash
Allwinner:
- Two defconfig change to get USB working again
ARM Versatile:
- Interrupt numbers gone bad after an older bug fix
Nomadik:
- Crashes from incorrect L2 cache settings
VIA vt8500:
- SD/MMC support on WM8650 never worked"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
dts: vt8500: Add SDHC node to DTS file for WM8650
ARM: Fix broken USB support in multi_v7_defconfig for sunxi devices
ARM: versatile: fix MMC/SD interrupt assignment
ARM: nomadik: set latencies to 8 cycles
ARM: OMAP2+: Fix onenand rate detection to avoid filesystem corruption
ARM: Fix broken USB support in sunxi_defconfig
+49
-12
+3
-3
arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+3
-3
arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
···
25
25
cache-sets = <512>;
26
26
cache-line-size = <32>;
27
27
/* At full speed latency must be >=2 */
28
-
arm,tag-latency = <2>;
29
-
arm,data-latency = <2 2>;
30
-
arm,dirty-latency = <2>;
28
+
arm,tag-latency = <8>;
29
+
arm,data-latency = <8 8>;
30
+
arm,dirty-latency = <8>;
31
31
};
32
32
33
33
mtu0: mtu@101e2000 {
+7
-3
arch/arm/boot/dts/versatile-ab.dts
+7
-3
arch/arm/boot/dts/versatile-ab.dts
···
110
110
interrupt-parent = <&vic>;
111
111
interrupts = <31>; /* Cascaded to vic */
112
112
clear-mask = <0xffffffff>;
113
-
valid-mask = <0xffc203f8>;
113
+
/*
114
+
* Valid interrupt lines mask according to
115
+
* table 4-36 page 4-50 of ARM DUI 0225D
116
+
*/
117
+
valid-mask = <0x0760031b>;
114
118
};
115
119
116
120
dma@10130000 {
···
270
266
};
271
267
mmc@5000 {
272
268
compatible = "arm,pl180", "arm,primecell";
273
-
reg = < 0x5000 0x1000>;
274
-
interrupts-extended = <&vic 22 &sic 2>;
269
+
reg = <0x5000 0x1000>;
270
+
interrupts-extended = <&vic 22 &sic 1>;
275
271
clocks = <&xtal24mhz>, <&pclk>;
276
272
clock-names = "mclk", "apb_pclk";
277
273
};
+19
-1
arch/arm/boot/dts/versatile-pb.dts
+19
-1
arch/arm/boot/dts/versatile-pb.dts
···
5
5
compatible = "arm,versatile-pb";
6
6
7
7
amba {
8
+
/* The Versatile PB is using more SIC IRQ lines than the AB */
9
+
sic: intc@10003000 {
10
+
clear-mask = <0xffffffff>;
11
+
/*
12
+
* Valid interrupt lines mask according to
13
+
* figure 3-30 page 3-74 of ARM DUI 0224B
14
+
*/
15
+
valid-mask = <0x7fe003ff>;
16
+
};
17
+
8
18
gpio2: gpio@101e6000 {
9
19
compatible = "arm,pl061", "arm,primecell";
10
20
reg = <0x101e6000 0x1000>;
···
77
67
};
78
68
79
69
fpga {
70
+
mmc@5000 {
71
+
/*
72
+
* Overrides the interrupt assignment from
73
+
* the Versatile AB board file.
74
+
*/
75
+
interrupts-extended = <&sic 22 &sic 23>;
76
+
};
80
77
uart@9000 {
81
78
compatible = "arm,pl011", "arm,primecell";
82
79
reg = <0x9000 0x1000>;
···
103
86
mmc@b000 {
104
87
compatible = "arm,pl180", "arm,primecell";
105
88
reg = <0xb000 0x1000>;
106
-
interrupts-extended = <&vic 23 &sic 2>;
89
+
interrupt-parent = <&sic>;
90
+
interrupts = <1>, <2>;
107
91
clocks = <&xtal24mhz>, <&pclk>;
108
92
clock-names = "mclk", "apb_pclk";
109
93
};
+9
arch/arm/boot/dts/wm8650.dtsi
+9
arch/arm/boot/dts/wm8650.dtsi
···
187
187
interrupts = <43>;
188
188
};
189
189
190
+
sdhc@d800a000 {
191
+
compatible = "wm,wm8505-sdhc";
192
+
reg = <0xd800a000 0x400>;
193
+
interrupts = <20>, <21>;
194
+
clocks = <&clksdhc>;
195
+
bus-width = <4>;
196
+
sdon-inverted;
197
+
};
198
+
190
199
fb: fb@d8050800 {
191
200
compatible = "wm,wm8505-fb";
192
201
reg = <0xd8050800 0x200>;
+1
arch/arm/configs/multi_v7_defconfig
+1
arch/arm/configs/multi_v7_defconfig
+1
arch/arm/configs/sunxi_defconfig
+1
arch/arm/configs/sunxi_defconfig
+9
-5
arch/arm/mach-omap2/gpmc-onenand.c
+9
-5
arch/arm/mach-omap2/gpmc-onenand.c
···
149
149
freq = 104;
150
150
break;
151
151
default:
152
-
freq = 54;
153
-
break;
152
+
pr_err("onenand rate not detected, bad GPMC async timings?\n");
153
+
freq = 0;
154
154
}
155
155
156
156
return freq;
···
271
271
struct gpmc_timings t;
272
272
int ret;
273
273
274
+
/*
275
+
* Note that we need to keep sync_write set for the call to
276
+
* omap2_onenand_set_async_mode() to work to detect the onenand
277
+
* supported clock rate for the sync timings.
278
+
*/
274
279
if (gpmc_onenand_data->of_node) {
275
280
gpmc_read_settings_dt(gpmc_onenand_data->of_node,
276
281
&onenand_async);
···
286
281
else
287
282
gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
288
283
onenand_async.sync_read = false;
289
-
onenand_async.sync_write = false;
290
284
}
291
285
}
292
-
293
-
omap2_onenand_set_async_mode(onenand_base);
294
286
295
287
omap2_onenand_calc_async_timings(&t);
296
288
···
312
310
if (!freq) {
313
311
/* Very first call freq is not known */
314
312
freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
313
+
if (!freq)
314
+
return -ENODEV;
315
315
set_onenand_cfg(onenand_base);
316
316
}
317
317