Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'char-misc-5.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver fixes from Greg KH:
"Here are some small char and misc driver fixes for 5.3-rc5.
These are two different subsystems needing some fixes, the habanalabs
driver which is has some more big endian fixes for problems found. The
other are some small soundwire fixes, including some Kconfig
dependencies needed to resolve reported build errors.
All of these have been in linux-next this week with no reported
issues"
* tag 'char-misc-5.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
misc: xilinx-sdfec: fix dependency and build error
habanalabs: fix device IRQ unmasking for BE host
habanalabs: fix endianness handling for internal QMAN submission
habanalabs: fix completion queue handling when host is BE
habanalabs: fix endianness handling for packets from user
habanalabs: fix DRAM usage accounting on context tear down
habanalabs: Avoid double free in error flow
soundwire: fix regmap dependencies and align with other serial links
soundwire: cadence_master: fix definitions for INTSTAT0/1
soundwire: cadence_master: fix register definition for SLAVE_STATE
+98
-66
+1
-1
drivers/base/regmap/Kconfig
+1
-1
drivers/base/regmap/Kconfig
+1
drivers/misc/Kconfig
+1
drivers/misc/Kconfig
+2
-3
drivers/misc/habanalabs/device.c
+2
-3
drivers/misc/habanalabs/device.c
···
970
970
rc = hl_ctx_init(hdev, hdev->kernel_ctx, true);
971
971
if (rc) {
972
972
dev_err(hdev->dev, "failed to initialize kernel context\n");
973
-
goto free_ctx;
973
+
kfree(hdev->kernel_ctx);
974
+
goto mmu_fini;
974
975
}
975
976
976
977
rc = hl_cb_pool_init(hdev);
···
1054
1053
if (hl_ctx_put(hdev->kernel_ctx) != 1)
1055
1054
dev_err(hdev->dev,
1056
1055
"kernel ctx is still alive on initialization failure\n");
1057
-
free_ctx:
1058
-
kfree(hdev->kernel_ctx);
1059
1056
mmu_fini:
1060
1057
hl_mmu_fini(hdev);
1061
1058
eq_fini:
+47
-25
drivers/misc/habanalabs/goya/goya.c
+47
-25
drivers/misc/habanalabs/goya/goya.c
···
2729
2729
GOYA_ASYNC_EVENT_ID_PI_UPDATE);
2730
2730
}
2731
2731
2732
-
void goya_flush_pq_write(struct hl_device *hdev, u64 *pq, u64 exp_val)
2732
+
void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd)
2733
2733
{
2734
-
/* Not needed in Goya */
2734
+
/* The QMANs are on the SRAM so need to copy to IO space */
2735
+
memcpy_toio((void __iomem *) pqe, bd, sizeof(struct hl_bd));
2735
2736
}
2736
2737
2737
2738
static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
···
3314
3313
int rc;
3315
3314
3316
3315
dev_dbg(hdev->dev, "DMA packet details:\n");
3317
-
dev_dbg(hdev->dev, "source == 0x%llx\n", user_dma_pkt->src_addr);
3318
-
dev_dbg(hdev->dev, "destination == 0x%llx\n", user_dma_pkt->dst_addr);
3319
-
dev_dbg(hdev->dev, "size == %u\n", user_dma_pkt->tsize);
3316
+
dev_dbg(hdev->dev, "source == 0x%llx\n",
3317
+
le64_to_cpu(user_dma_pkt->src_addr));
3318
+
dev_dbg(hdev->dev, "destination == 0x%llx\n",
3319
+
le64_to_cpu(user_dma_pkt->dst_addr));
3320
+
dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3320
3321
3321
3322
ctl = le32_to_cpu(user_dma_pkt->ctl);
3322
3323
user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
···
3347
3344
struct packet_lin_dma *user_dma_pkt)
3348
3345
{
3349
3346
dev_dbg(hdev->dev, "DMA packet details:\n");
3350
-
dev_dbg(hdev->dev, "source == 0x%llx\n", user_dma_pkt->src_addr);
3351
-
dev_dbg(hdev->dev, "destination == 0x%llx\n", user_dma_pkt->dst_addr);
3352
-
dev_dbg(hdev->dev, "size == %u\n", user_dma_pkt->tsize);
3347
+
dev_dbg(hdev->dev, "source == 0x%llx\n",
3348
+
le64_to_cpu(user_dma_pkt->src_addr));
3349
+
dev_dbg(hdev->dev, "destination == 0x%llx\n",
3350
+
le64_to_cpu(user_dma_pkt->dst_addr));
3351
+
dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3353
3352
3354
3353
/*
3355
3354
* WA for HW-23.
···
3391
3386
3392
3387
dev_dbg(hdev->dev, "WREG32 packet details:\n");
3393
3388
dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3394
-
dev_dbg(hdev->dev, "value == 0x%x\n", wreg_pkt->value);
3389
+
dev_dbg(hdev->dev, "value == 0x%x\n",
3390
+
le32_to_cpu(wreg_pkt->value));
3395
3391
3396
3392
if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {
3397
3393
dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
···
3434
3428
while (cb_parsed_length < parser->user_cb_size) {
3435
3429
enum packet_id pkt_id;
3436
3430
u16 pkt_size;
3437
-
void *user_pkt;
3431
+
struct goya_packet *user_pkt;
3438
3432
3439
-
user_pkt = (void *) (uintptr_t)
3433
+
user_pkt = (struct goya_packet *) (uintptr_t)
3440
3434
(parser->user_cb->kernel_address + cb_parsed_length);
3441
3435
3442
-
pkt_id = (enum packet_id) (((*(u64 *) user_pkt) &
3436
+
pkt_id = (enum packet_id) (
3437
+
(le64_to_cpu(user_pkt->header) &
3443
3438
PACKET_HEADER_PACKET_ID_MASK) >>
3444
3439
PACKET_HEADER_PACKET_ID_SHIFT);
3445
3440
···
3460
3453
* need to validate here as well because patch_cb() is
3461
3454
* not called in MMU path while this function is called
3462
3455
*/
3463
-
rc = goya_validate_wreg32(hdev, parser, user_pkt);
3456
+
rc = goya_validate_wreg32(hdev,
3457
+
parser, (struct packet_wreg32 *) user_pkt);
3464
3458
break;
3465
3459
3466
3460
case PACKET_WREG_BULK:
···
3489
3481
case PACKET_LIN_DMA:
3490
3482
if (is_mmu)
3491
3483
rc = goya_validate_dma_pkt_mmu(hdev, parser,
3492
-
user_pkt);
3484
+
(struct packet_lin_dma *) user_pkt);
3493
3485
else
3494
3486
rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3495
-
user_pkt);
3487
+
(struct packet_lin_dma *) user_pkt);
3496
3488
break;
3497
3489
3498
3490
case PACKET_MSG_LONG:
···
3665
3657
enum packet_id pkt_id;
3666
3658
u16 pkt_size;
3667
3659
u32 new_pkt_size = 0;
3668
-
void *user_pkt, *kernel_pkt;
3660
+
struct goya_packet *user_pkt, *kernel_pkt;
3669
3661
3670
-
user_pkt = (void *) (uintptr_t)
3662
+
user_pkt = (struct goya_packet *) (uintptr_t)
3671
3663
(parser->user_cb->kernel_address + cb_parsed_length);
3672
-
kernel_pkt = (void *) (uintptr_t)
3664
+
kernel_pkt = (struct goya_packet *) (uintptr_t)
3673
3665
(parser->patched_cb->kernel_address +
3674
3666
cb_patched_cur_length);
3675
3667
3676
-
pkt_id = (enum packet_id) (((*(u64 *) user_pkt) &
3668
+
pkt_id = (enum packet_id) (
3669
+
(le64_to_cpu(user_pkt->header) &
3677
3670
PACKET_HEADER_PACKET_ID_MASK) >>
3678
3671
PACKET_HEADER_PACKET_ID_SHIFT);
3679
3672
···
3689
3680
3690
3681
switch (pkt_id) {
3691
3682
case PACKET_LIN_DMA:
3692
-
rc = goya_patch_dma_packet(hdev, parser, user_pkt,
3693
-
kernel_pkt, &new_pkt_size);
3683
+
rc = goya_patch_dma_packet(hdev, parser,
3684
+
(struct packet_lin_dma *) user_pkt,
3685
+
(struct packet_lin_dma *) kernel_pkt,
3686
+
&new_pkt_size);
3694
3687
cb_patched_cur_length += new_pkt_size;
3695
3688
break;
3696
3689
3697
3690
case PACKET_WREG_32:
3698
3691
memcpy(kernel_pkt, user_pkt, pkt_size);
3699
3692
cb_patched_cur_length += pkt_size;
3700
-
rc = goya_validate_wreg32(hdev, parser, kernel_pkt);
3693
+
rc = goya_validate_wreg32(hdev, parser,
3694
+
(struct packet_wreg32 *) kernel_pkt);
3701
3695
break;
3702
3696
3703
3697
case PACKET_WREG_BULK:
···
4364
4352
size_t total_pkt_size;
4365
4353
long result;
4366
4354
int rc;
4355
+
int irq_num_entries, irq_arr_index;
4356
+
__le32 *goya_irq_arr;
4367
4357
4368
4358
total_pkt_size = sizeof(struct armcp_unmask_irq_arr_packet) +
4369
4359
irq_arr_size;
···
4383
4369
if (!pkt)
4384
4370
return -ENOMEM;
4385
4371
4386
-
pkt->length = cpu_to_le32(irq_arr_size / sizeof(irq_arr[0]));
4387
-
memcpy(&pkt->irqs, irq_arr, irq_arr_size);
4372
+
irq_num_entries = irq_arr_size / sizeof(irq_arr[0]);
4373
+
pkt->length = cpu_to_le32(irq_num_entries);
4374
+
4375
+
/* We must perform any necessary endianness conversation on the irq
4376
+
* array being passed to the goya hardware
4377
+
*/
4378
+
for (irq_arr_index = 0, goya_irq_arr = (__le32 *) &pkt->irqs;
4379
+
irq_arr_index < irq_num_entries ; irq_arr_index++)
4380
+
goya_irq_arr[irq_arr_index] =
4381
+
cpu_to_le32(irq_arr[irq_arr_index]);
4388
4382
4389
4383
pkt->armcp_pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
4390
4384
ARMCP_PKT_CTL_OPCODE_SHIFT);
···
5064
5042
.resume = goya_resume,
5065
5043
.cb_mmap = goya_cb_mmap,
5066
5044
.ring_doorbell = goya_ring_doorbell,
5067
-
.flush_pq_write = goya_flush_pq_write,
5045
+
.pqe_write = goya_pqe_write,
5068
5046
.asic_dma_alloc_coherent = goya_dma_alloc_coherent,
5069
5047
.asic_dma_free_coherent = goya_dma_free_coherent,
5070
5048
.get_int_queue_base = goya_get_int_queue_base,
+1
-1
drivers/misc/habanalabs/goya/goyaP.h
+1
-1
drivers/misc/habanalabs/goya/goyaP.h
···
177
177
void goya_late_fini(struct hl_device *hdev);
178
178
179
179
void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
180
-
void goya_flush_pq_write(struct hl_device *hdev, u64 *pq, u64 exp_val);
180
+
void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd);
181
181
void goya_update_eq_ci(struct hl_device *hdev, u32 val);
182
182
void goya_restore_phase_topology(struct hl_device *hdev);
183
183
int goya_context_switch(struct hl_device *hdev, u32 asid);
+7
-2
drivers/misc/habanalabs/habanalabs.h
+7
-2
drivers/misc/habanalabs/habanalabs.h
···
441
441
* @resume: handles IP specific H/W or SW changes for resume.
442
442
* @cb_mmap: maps a CB.
443
443
* @ring_doorbell: increment PI on a given QMAN.
444
-
* @flush_pq_write: flush PQ entry write if necessary, WARN if flushing failed.
444
+
* @pqe_write: Write the PQ entry to the PQ. This is ASIC-specific
445
+
* function because the PQs are located in different memory areas
446
+
* per ASIC (SRAM, DRAM, Host memory) and therefore, the method of
447
+
* writing the PQE must match the destination memory area
448
+
* properties.
445
449
* @asic_dma_alloc_coherent: Allocate coherent DMA memory by calling
446
450
* dma_alloc_coherent(). This is ASIC function because
447
451
* its implementation is not trivial when the driver
···
514
510
int (*cb_mmap)(struct hl_device *hdev, struct vm_area_struct *vma,
515
511
u64 kaddress, phys_addr_t paddress, u32 size);
516
512
void (*ring_doorbell)(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
517
-
void (*flush_pq_write)(struct hl_device *hdev, u64 *pq, u64 exp_val);
513
+
void (*pqe_write)(struct hl_device *hdev, __le64 *pqe,
514
+
struct hl_bd *bd);
518
515
void* (*asic_dma_alloc_coherent)(struct hl_device *hdev, size_t size,
519
516
dma_addr_t *dma_handle, gfp_t flag);
520
517
void (*asic_dma_free_coherent)(struct hl_device *hdev, size_t size,
+5
-9
drivers/misc/habanalabs/hw_queue.c
+5
-9
drivers/misc/habanalabs/hw_queue.c
···
290
290
struct hl_device *hdev = job->cs->ctx->hdev;
291
291
struct hl_hw_queue *q = &hdev->kernel_queues[job->hw_queue_id];
292
292
struct hl_bd bd;
293
-
u64 *pi, *pbd = (u64 *) &bd;
293
+
__le64 *pi;
294
294
295
295
bd.ctl = 0;
296
-
bd.len = __cpu_to_le32(job->job_cb_size);
297
-
bd.ptr = __cpu_to_le64((u64) (uintptr_t) job->user_cb);
296
+
bd.len = cpu_to_le32(job->job_cb_size);
297
+
bd.ptr = cpu_to_le64((u64) (uintptr_t) job->user_cb);
298
298
299
-
pi = (u64 *) (uintptr_t) (q->kernel_address +
299
+
pi = (__le64 *) (uintptr_t) (q->kernel_address +
300
300
((q->pi & (q->int_queue_len - 1)) * sizeof(bd)));
301
-
302
-
pi[0] = pbd[0];
303
-
pi[1] = pbd[1];
304
301
305
302
q->pi++;
306
303
q->pi &= ((q->int_queue_len << 1) - 1);
307
304
308
-
/* Flush PQ entry write. Relevant only for specific ASICs */
309
-
hdev->asic_funcs->flush_pq_write(hdev, pi, pbd[0]);
305
+
hdev->asic_funcs->pqe_write(hdev, pi, &bd);
310
306
311
307
hdev->asic_funcs->ring_doorbell(hdev, q->hw_queue_id, q->pi);
312
308
}
+13
drivers/misc/habanalabs/include/goya/goya_packets.h
+13
drivers/misc/habanalabs/include/goya/goya_packets.h
···
52
52
#define GOYA_PKT_CTL_MB_SHIFT 31
53
53
#define GOYA_PKT_CTL_MB_MASK 0x80000000
54
54
55
+
/* All packets have, at least, an 8-byte header, which contains
56
+
* the packet type. The kernel driver uses the packet header for packet
57
+
* validation and to perform any necessary required preparation before
58
+
* sending them off to the hardware.
59
+
*/
60
+
struct goya_packet {
61
+
__le64 header;
62
+
/* The rest of the packet data follows. Use the corresponding
63
+
* packet_XXX struct to deference the data, based on packet type
64
+
*/
65
+
u8 contents[0];
66
+
};
67
+
55
68
struct packet_nop {
56
69
__le32 reserved;
57
70
__le32 ctl;
+13
-14
drivers/misc/habanalabs/irq.c
+13
-14
drivers/misc/habanalabs/irq.c
···
80
80
struct hl_cs_job *job;
81
81
bool shadow_index_valid;
82
82
u16 shadow_index;
83
-
u32 *cq_entry;
84
-
u32 *cq_base;
83
+
struct hl_cq_entry *cq_entry, *cq_base;
85
84
86
85
if (hdev->disabled) {
87
86
dev_dbg(hdev->dev,
···
89
90
return IRQ_HANDLED;
90
91
}
91
92
92
-
cq_base = (u32 *) (uintptr_t) cq->kernel_address;
93
+
cq_base = (struct hl_cq_entry *) (uintptr_t) cq->kernel_address;
93
94
94
95
while (1) {
95
-
bool entry_ready = ((cq_base[cq->ci] & CQ_ENTRY_READY_MASK)
96
+
bool entry_ready = ((le32_to_cpu(cq_base[cq->ci].data) &
97
+
CQ_ENTRY_READY_MASK)
96
98
>> CQ_ENTRY_READY_SHIFT);
97
99
98
100
if (!entry_ready)
99
101
break;
100
102
101
-
cq_entry = (u32 *) &cq_base[cq->ci];
103
+
cq_entry = (struct hl_cq_entry *) &cq_base[cq->ci];
102
104
103
-
/*
104
-
* Make sure we read CQ entry contents after we've
105
+
/* Make sure we read CQ entry contents after we've
105
106
* checked the ownership bit.
106
107
*/
107
108
dma_rmb();
108
109
109
-
shadow_index_valid =
110
-
((*cq_entry & CQ_ENTRY_SHADOW_INDEX_VALID_MASK)
110
+
shadow_index_valid = ((le32_to_cpu(cq_entry->data) &
111
+
CQ_ENTRY_SHADOW_INDEX_VALID_MASK)
111
112
>> CQ_ENTRY_SHADOW_INDEX_VALID_SHIFT);
112
113
113
-
shadow_index = (u16)
114
-
((*cq_entry & CQ_ENTRY_SHADOW_INDEX_MASK)
114
+
shadow_index = (u16) ((le32_to_cpu(cq_entry->data) &
115
+
CQ_ENTRY_SHADOW_INDEX_MASK)
115
116
>> CQ_ENTRY_SHADOW_INDEX_SHIFT);
116
117
117
118
queue = &hdev->kernel_queues[cq->hw_queue_id];
···
121
122
queue_work(hdev->cq_wq, &job->finish_work);
122
123
}
123
124
124
-
/*
125
-
* Update ci of the context's queue. There is no
125
+
/* Update ci of the context's queue. There is no
126
126
* need to protect it with spinlock because this update is
127
127
* done only inside IRQ and there is a different IRQ per
128
128
* queue
···
129
131
queue->ci = hl_queue_inc_ptr(queue->ci);
130
132
131
133
/* Clear CQ entry ready bit */
132
-
cq_base[cq->ci] &= ~CQ_ENTRY_READY_MASK;
134
+
cq_entry->data = cpu_to_le32(le32_to_cpu(cq_entry->data) &
135
+
~CQ_ENTRY_READY_MASK);
133
136
134
137
cq->ci = hl_cq_inc_ptr(cq->ci);
135
138
+2
drivers/misc/habanalabs/memory.c
+2
drivers/misc/habanalabs/memory.c
···
1629
1629
dev_dbg(hdev->dev,
1630
1630
"page list 0x%p of asid %d is still alive\n",
1631
1631
phys_pg_list, ctx->asid);
1632
+
atomic64_sub(phys_pg_list->total_size,
1633
+
&hdev->dram_used_mem);
1632
1634
free_phys_pg_pack(hdev, phys_pg_list);
1633
1635
idr_remove(&vm->phys_pg_pack_handles, i);
1634
1636
}
+1
-6
drivers/soundwire/Kconfig
+1
-6
drivers/soundwire/Kconfig
···
4
4
#
5
5
6
6
menuconfig SOUNDWIRE
7
-
bool "SoundWire support"
7
+
tristate "SoundWire support"
8
8
help
9
9
SoundWire is a 2-Pin interface with data and clock line ratified
10
10
by the MIPI Alliance. SoundWire is used for transporting data
···
17
17
18
18
comment "SoundWire Devices"
19
19
20
-
config SOUNDWIRE_BUS
21
-
tristate
22
-
select REGMAP_SOUNDWIRE
23
-
24
20
config SOUNDWIRE_CADENCE
25
21
tristate
26
22
27
23
config SOUNDWIRE_INTEL
28
24
tristate "Intel SoundWire Master driver"
29
25
select SOUNDWIRE_CADENCE
30
-
select SOUNDWIRE_BUS
31
26
depends on X86 && ACPI && SND_SOC
32
27
help
33
28
SoundWire Intel Master driver.
+1
-1
drivers/soundwire/Makefile
+1
-1
drivers/soundwire/Makefile
+4
-4
drivers/soundwire/cadence_master.c
+4
-4
drivers/soundwire/cadence_master.c
···
81
81
82
82
#define CDNS_MCP_INTSET 0x4C
83
83
84
-
#define CDNS_SDW_SLAVE_STAT 0x50
85
-
#define CDNS_MCP_SLAVE_STAT_MASK BIT(1, 0)
84
+
#define CDNS_MCP_SLAVE_STAT 0x50
85
+
#define CDNS_MCP_SLAVE_STAT_MASK GENMASK(1, 0)
86
86
87
87
#define CDNS_MCP_SLAVE_INTSTAT0 0x54
88
88
#define CDNS_MCP_SLAVE_INTSTAT1 0x58
···
96
96
#define CDNS_MCP_SLAVE_INTMASK0 0x5C
97
97
#define CDNS_MCP_SLAVE_INTMASK1 0x60
98
98
99
-
#define CDNS_MCP_SLAVE_INTMASK0_MASK GENMASK(30, 0)
100
-
#define CDNS_MCP_SLAVE_INTMASK1_MASK GENMASK(16, 0)
99
+
#define CDNS_MCP_SLAVE_INTMASK0_MASK GENMASK(31, 0)
100
+
#define CDNS_MCP_SLAVE_INTMASK1_MASK GENMASK(15, 0)
101
101
102
102
#define CDNS_MCP_PORT_INTSTAT 0x64
103
103
#define CDNS_MCP_PDI_STAT 0x6C