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dt-bindings: phy: add qcom,msm8996-qmp-pcie-phy schema
The QMP PHY DT schema is getting unwieldy. Break out the odd-bird
msm8996-qmp-pcie-phy which is the only QMP PHY that uses separate
"per-lane" nodes.
Add an example node based on a cleaned up version of msm8996.dtsi.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20220830112923.3725-9-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Johan Hovold
and committed by
Vinod Koul
4506dc82
6fcebb29
+146
-26
+146
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
+146
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
···
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm QMP PHY controller (MSM8996 PCIe)
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maintainers:
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- Vinod Koul <vkoul@kernel.org>
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description:
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QMP PHY controller supports physical layer functionality for a number of
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controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
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properties:
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compatible:
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const: qcom,msm8996-qmp-pcie-phy
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reg:
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items:
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- description: serdes
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"#address-cells":
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enum: [ 1, 2 ]
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+
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"#size-cells":
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enum: [ 1, 2 ]
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ranges: true
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: aux
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- const: cfg_ahb
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- const: ref
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+
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resets:
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maxItems: 3
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reset-names:
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items:
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- const: phy
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- const: common
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- const: cfg
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vdda-phy-supply: true
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vdda-pll-supply: true
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+
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vddp-ref-clk-supply: true
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patternProperties:
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"^phy@[0-9a-f]+$":
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type: object
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description: one child node per PHY provided by this block
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- ranges
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- clocks
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- clock-names
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- resets
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- reset-names
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- vdda-phy-supply
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- vdda-pll-supply
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8996.h>
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pcie_phy: phy-wrapper@34000 {
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compatible = "qcom,msm8996-qmp-pcie-phy";
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reg = <0x34000 0x488>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x34000 0x4000>;
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+
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clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_CLKREF_CLK>;
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clock-names = "aux", "cfg_ahb", "ref";
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resets = <&gcc GCC_PCIE_PHY_BCR>,
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<&gcc GCC_PCIE_PHY_COM_BCR>,
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<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
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reset-names = "phy", "common", "cfg";
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vdda-phy-supply = <&vreg_l28a_0p925>;
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vdda-pll-supply = <&vreg_l12a_1p8>;
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pciephy_0: phy@1000 {
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reg = <0x1000 0x130>,
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<0x1200 0x200>,
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<0x1400 0x1dc>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
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clock-names = "pipe0";
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "lane0";
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#clock-cells = <0>;
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clock-output-names = "pcie_0_pipe_clk_src";
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#phy-cells = <0>;
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};
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pciephy_1: phy@2000 {
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reg = <0x2000 0x130>,
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<0x2200 0x200>,
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<0x2400 0x1dc>;
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
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clock-names = "pipe1";
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resets = <&gcc GCC_PCIE_1_PHY_BCR>;
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reset-names = "lane1";
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#clock-cells = <0>;
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clock-output-names = "pcie_1_pipe_clk_src";
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#phy-cells = <0>;
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};
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pciephy_2: phy@3000 {
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reg = <0x3000 0x130>,
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<0x3200 0x200>,
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<0x3400 0x1dc>;
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clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
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clock-names = "pipe2";
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resets = <&gcc GCC_PCIE_2_PHY_BCR>;
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reset-names = "lane2";
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#clock-cells = <0>;
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clock-output-names = "pcie_2_pipe_clk_src";
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#phy-cells = <0>;
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};
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};
-26
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
-26
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
···
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- qcom,ipq8074-qmp-gen3-pcie-phy
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- qcom,ipq8074-qmp-pcie-phy
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- qcom,ipq8074-qmp-usb3-phy
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- qcom,msm8996-qmp-pcie-phy
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- qcom,msm8996-qmp-ufs-phy
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- qcom,msm8996-qmp-usb3-phy
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- qcom,msm8998-qmp-pcie-phy
···
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items:
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- const: phy
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- const: common
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-
required:
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-
- vdda-phy-supply
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-
- vdda-pll-supply
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-
- if:
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properties:
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-
compatible:
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contains:
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enum:
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- qcom,msm8996-qmp-pcie-phy
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then:
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properties:
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-
clocks:
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-
maxItems: 3
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clock-names:
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-
items:
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-
- const: aux
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- const: cfg_ahb
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-
- const: ref
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resets:
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-
maxItems: 3
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reset-names:
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-
items:
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-
- const: phy
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-
- const: common
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-
- const: cfg
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required:
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- vdda-phy-supply
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- vdda-pll-supply