Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: rockchip: samsung-hdptx: Optimize internal rate handling
Drop the rate parameter from a bunch of internal helpers and, instead,
make better use of the newly introduced ->hdmi_cfg.tmds_char_rate driver
data.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-13-8cb1678e7663@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Cristian Ciocaltea
and committed by
Vinod Koul
45b14bdc
37f335db
+23
-24
+23
-24
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+23
-24
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
···
968
968
return true;
969
969
}
970
970
971
-
static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
972
-
unsigned long long rate)
971
+
static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
973
972
{
974
973
const struct ropll_config *cfg = NULL;
975
974
struct ropll_config rc = {0};
976
975
int ret, i;
977
976
977
+
if (!hdptx->hdmi_cfg.tmds_char_rate)
978
+
return 0;
979
+
978
980
for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
979
-
if (rate == ropll_tmds_cfg[i].rate) {
981
+
if (hdptx->hdmi_cfg.tmds_char_rate == ropll_tmds_cfg[i].rate) {
980
982
cfg = &ropll_tmds_cfg[i];
981
983
break;
982
984
}
983
985
984
986
if (!cfg) {
985
-
if (rk_hdptx_phy_clk_pll_calc(rate, &rc)) {
986
-
cfg = &rc;
987
-
} else {
988
-
dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__);
987
+
if (!rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.tmds_char_rate, &rc)) {
988
+
dev_err(hdptx->dev, "%s cannot find pll cfg for rate=%llu\n",
989
+
__func__, hdptx->hdmi_cfg.tmds_char_rate);
989
990
return -EINVAL;
990
991
}
992
+
993
+
cfg = &rc;
991
994
}
992
995
993
996
dev_dbg(hdptx->dev, "%s rate=%llu mdiv=%u sdiv=%u sdm_en=%u k_sign=%u k=%u lc=%u\n",
994
-
__func__, rate, cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en,
995
-
cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
997
+
__func__, hdptx->hdmi_cfg.tmds_char_rate, cfg->pms_mdiv, cfg->pms_sdiv + 1,
998
+
cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
996
999
997
1000
rk_hdptx_pre_power_up(hdptx);
998
1001
···
1033
1030
1034
1031
ret = rk_hdptx_post_enable_pll(hdptx);
1035
1032
if (!ret)
1036
-
hdptx->hw_rate = rate;
1033
+
hdptx->hw_rate = hdptx->hdmi_cfg.tmds_char_rate;
1037
1034
1038
1035
return ret;
1039
1036
}
1040
1037
1041
-
static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
1042
-
unsigned long long rate)
1038
+
static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx)
1043
1039
{
1044
1040
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
1045
1041
1046
1042
regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
1047
1043
1048
-
if (rate > HDMI14_MAX_RATE) {
1044
+
if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) {
1049
1045
/* For 1/40 bitrate clk */
1050
1046
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
1051
1047
} else {
···
1096
1094
HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x0));
1097
1095
}
1098
1096
1099
-
static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
1100
-
unsigned long long rate)
1097
+
static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx)
1101
1098
{
1102
1099
enum phy_mode mode = phy_get_mode(hdptx->phy);
1103
1100
u32 status;
···
1115
1114
if (mode == PHY_MODE_DP) {
1116
1115
rk_hdptx_dp_reset(hdptx);
1117
1116
} else {
1118
-
if (rate) {
1119
-
ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
1120
-
if (ret)
1121
-
goto dec_usage;
1122
-
}
1117
+
ret = rk_hdptx_ropll_tmds_cmn_config(hdptx);
1118
+
if (ret)
1119
+
goto dec_usage;
1123
1120
}
1124
1121
1125
1122
return 0;
···
1430
1431
dev_dbg(hdptx->dev, "%s rate=%llu\n", __func__, hdptx->hdmi_cfg.tmds_char_rate);
1431
1432
}
1432
1433
1433
-
ret = rk_hdptx_phy_consumer_get(hdptx, hdptx->hdmi_cfg.tmds_char_rate);
1434
+
ret = rk_hdptx_phy_consumer_get(hdptx);
1434
1435
if (ret)
1435
1436
return ret;
1436
1437
···
1461
1462
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1462
1463
HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0));
1463
1464
1464
-
ret = rk_hdptx_ropll_tmds_mode_config(hdptx, hdptx->hdmi_cfg.tmds_char_rate);
1465
+
ret = rk_hdptx_ropll_tmds_mode_config(hdptx);
1465
1466
if (ret)
1466
1467
rk_hdptx_phy_consumer_put(hdptx, true);
1467
1468
}
···
1829
1830
{
1830
1831
struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1831
1832
1832
-
return rk_hdptx_phy_consumer_get(hdptx, hdptx->hw_rate);
1833
+
return rk_hdptx_phy_consumer_get(hdptx);
1833
1834
}
1834
1835
1835
1836
static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
···
1896
1897
* while the latter being executed only once, i.e. when clock remains
1897
1898
* in the prepared state during rate changes.
1898
1899
*/
1899
-
return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
1900
+
return rk_hdptx_ropll_tmds_cmn_config(hdptx);
1900
1901
}
1901
1902
1902
1903
static const struct clk_ops hdptx_phy_clk_ops = {