Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung
* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S5PV310: Fix on Secondary CPU startup
ARM: S5PV310: Bug fix on uclk1 and sclk_pwm
ARM: S5PV310: Fix missed uart clocks
ARM: S5PV310: Should be clk_sclk_apll not clk_mout_apll
ARM: S5PV310: Fix on PLL setting for S5PV310
ARM: S5PV310: Add CMU block for S5PV310 Clock
ARM: S5PV310: Fix on typo irqs.h of S5PV310
ARM: S5PV310: Fix on default ZRELADDR of ARCH_S5PV310
ARM: S5PV310: Fix on GPIO base addresses
ARM: SAMSUNG: Fix on build warning regarding VMALLOC_END type
ARM: S5P: VMALLOC_END should be unsigned long
+135
-62
+2
-1
arch/arm/Kconfig
+2
-1
arch/arm/Kconfig
+1
-1
arch/arm/mach-s3c2410/include/mach/vmalloc.h
+1
-1
arch/arm/mach-s3c2410/include/mach/vmalloc.h
+1
-1
arch/arm/mach-s3c64xx/include/mach/vmalloc.h
+1
-1
arch/arm/mach-s3c64xx/include/mach/vmalloc.h
+1
-1
arch/arm/mach-s5p6440/include/mach/vmalloc.h
+1
-1
arch/arm/mach-s5p6440/include/mach/vmalloc.h
+1
-1
arch/arm/mach-s5p6442/include/mach/vmalloc.h
+1
-1
arch/arm/mach-s5p6442/include/mach/vmalloc.h
+1
-1
arch/arm/mach-s5pv210/include/mach/vmalloc.h
+1
-1
arch/arm/mach-s5pv210/include/mach/vmalloc.h
+63
-19
arch/arm/mach-s5pv310/clock.c
+63
-19
arch/arm/mach-s5pv310/clock.c
···
30
30
.rate = 27000000,
31
31
};
32
32
33
+
static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
34
+
{
35
+
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
36
+
}
37
+
38
+
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
39
+
{
40
+
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
41
+
}
42
+
33
43
/* Core list of CMU_CPU side */
34
44
35
45
static struct clksrc_clk clk_mout_apll = {
···
49
39
},
50
40
.sources = &clk_src_apll,
51
41
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
42
+
};
43
+
44
+
static struct clksrc_clk clk_sclk_apll = {
45
+
.clk = {
46
+
.name = "sclk_apll",
47
+
.id = -1,
48
+
.parent = &clk_mout_apll.clk,
49
+
},
52
50
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
53
51
};
54
52
···
79
61
};
80
62
81
63
static struct clk *clkset_moutcore_list[] = {
82
-
[0] = &clk_mout_apll.clk,
64
+
[0] = &clk_sclk_apll.clk,
83
65
[1] = &clk_mout_mpll.clk,
84
66
};
85
67
···
172
154
173
155
static struct clk *clkset_corebus_list[] = {
174
156
[0] = &clk_mout_mpll.clk,
175
-
[1] = &clk_mout_apll.clk,
157
+
[1] = &clk_sclk_apll.clk,
176
158
};
177
159
178
160
static struct clksrc_sources clkset_mout_corebus = {
···
238
220
239
221
static struct clk *clkset_aclk_top_list[] = {
240
222
[0] = &clk_mout_mpll.clk,
241
-
[1] = &clk_mout_apll.clk,
223
+
[1] = &clk_sclk_apll.clk,
242
224
};
243
225
244
226
static struct clksrc_sources clkset_aclk_200 = {
···
339
321
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
340
322
};
341
323
342
-
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
343
-
{
344
-
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
345
-
}
346
-
347
324
static struct clk init_clocks_disable[] = {
348
325
{
349
326
.name = "timers",
···
350
337
};
351
338
352
339
static struct clk init_clocks[] = {
353
-
/* Nothing here yet */
340
+
{
341
+
.name = "uart",
342
+
.id = 0,
343
+
.enable = s5pv310_clk_ip_peril_ctrl,
344
+
.ctrlbit = (1 << 0),
345
+
}, {
346
+
.name = "uart",
347
+
.id = 1,
348
+
.enable = s5pv310_clk_ip_peril_ctrl,
349
+
.ctrlbit = (1 << 1),
350
+
}, {
351
+
.name = "uart",
352
+
.id = 2,
353
+
.enable = s5pv310_clk_ip_peril_ctrl,
354
+
.ctrlbit = (1 << 2),
355
+
}, {
356
+
.name = "uart",
357
+
.id = 3,
358
+
.enable = s5pv310_clk_ip_peril_ctrl,
359
+
.ctrlbit = (1 << 3),
360
+
}, {
361
+
.name = "uart",
362
+
.id = 4,
363
+
.enable = s5pv310_clk_ip_peril_ctrl,
364
+
.ctrlbit = (1 << 4),
365
+
}, {
366
+
.name = "uart",
367
+
.id = 5,
368
+
.enable = s5pv310_clk_ip_peril_ctrl,
369
+
.ctrlbit = (1 << 5),
370
+
}
354
371
};
355
372
356
373
static struct clk *clkset_group_list[] = {
···
402
359
.clk = {
403
360
.name = "uclk1",
404
361
.id = 0,
362
+
.enable = s5pv310_clksrc_mask_peril0_ctrl,
405
363
.ctrlbit = (1 << 0),
406
-
.enable = s5pv310_clk_ip_peril_ctrl,
407
364
},
408
365
.sources = &clkset_group,
409
366
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
···
412
369
.clk = {
413
370
.name = "uclk1",
414
371
.id = 1,
415
-
.enable = s5pv310_clk_ip_peril_ctrl,
416
-
.ctrlbit = (1 << 1),
372
+
.enable = s5pv310_clksrc_mask_peril0_ctrl,
373
+
.ctrlbit = (1 << 4),
417
374
},
418
375
.sources = &clkset_group,
419
376
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
···
422
379
.clk = {
423
380
.name = "uclk1",
424
381
.id = 2,
425
-
.enable = s5pv310_clk_ip_peril_ctrl,
426
-
.ctrlbit = (1 << 2),
382
+
.enable = s5pv310_clksrc_mask_peril0_ctrl,
383
+
.ctrlbit = (1 << 8),
427
384
},
428
385
.sources = &clkset_group,
429
386
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
···
432
389
.clk = {
433
390
.name = "uclk1",
434
391
.id = 3,
435
-
.enable = s5pv310_clk_ip_peril_ctrl,
436
-
.ctrlbit = (1 << 3),
392
+
.enable = s5pv310_clksrc_mask_peril0_ctrl,
393
+
.ctrlbit = (1 << 12),
437
394
},
438
395
.sources = &clkset_group,
439
396
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
···
442
399
.clk = {
443
400
.name = "sclk_pwm",
444
401
.id = -1,
445
-
.enable = s5pv310_clk_ip_peril_ctrl,
402
+
.enable = s5pv310_clksrc_mask_peril0_ctrl,
446
403
.ctrlbit = (1 << 24),
447
404
},
448
405
.sources = &clkset_group,
···
454
411
/* Clock initialization code */
455
412
static struct clksrc_clk *sysclks[] = {
456
413
&clk_mout_apll,
414
+
&clk_sclk_apll,
457
415
&clk_mout_epll,
458
416
&clk_mout_mpll,
459
417
&clk_moutcore,
···
514
470
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
515
471
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
516
472
epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
517
-
__raw_readl(S5P_EPLL_CON1), pll_4500);
473
+
__raw_readl(S5P_EPLL_CON1), pll_4600);
518
474
519
475
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
520
476
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
521
-
__raw_readl(S5P_VPLL_CON1), pll_4502);
477
+
__raw_readl(S5P_VPLL_CON1), pll_4650);
522
478
523
479
clk_fout_apll.rate = apll;
524
480
clk_fout_mpll.rate = mpll;
+10
arch/arm/mach-s5pv310/cpu.c
+10
arch/arm/mach-s5pv310/cpu.c
···
45
45
.pfn = __phys_to_pfn(S5PV310_PA_L2CC),
46
46
.length = SZ_4K,
47
47
.type = MT_DEVICE,
48
+
}, {
49
+
.virtual = (unsigned long)S5P_VA_SYSRAM,
50
+
.pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
51
+
.length = SZ_4K,
52
+
.type = MT_DEVICE,
53
+
}, {
54
+
.virtual = (unsigned long)S5P_VA_CMU,
55
+
.pfn = __phys_to_pfn(S5PV310_PA_CMU),
56
+
.length = SZ_128K,
57
+
.type = MT_DEVICE,
48
58
},
49
59
};
50
60
+7
-4
arch/arm/mach-s5pv310/include/mach/irqs.h
+7
-4
arch/arm/mach-s5pv310/include/mach/irqs.h
···
15
15
16
16
#include <plat/irqs.h>
17
17
18
-
/* Private Peripheral Interrupt */
18
+
/* PPI: Private Peripheral Interrupt */
19
+
19
20
#define IRQ_PPI(x) S5P_IRQ(x+16)
20
21
21
22
#define IRQ_LOCALTIMER IRQ_PPI(13)
22
23
23
-
/* Shared Peripheral Interrupt */
24
+
/* SPI: Shared Peripheral Interrupt */
25
+
24
26
#define IRQ_SPI(x) S5P_IRQ(x+32)
25
27
26
28
#define IRQ_EINT0 IRQ_SPI(40)
···
38
36
#define IRQ_PCIE IRQ_SPI(50)
39
37
#define IRQ_SYSTEM_TIMER IRQ_SPI(51)
40
38
#define IRQ_MFC IRQ_SPI(52)
41
-
#define IRQ_WTD IRQ_SPI(53)
39
+
#define IRQ_WDT IRQ_SPI(53)
42
40
#define IRQ_AUDIO_SS IRQ_SPI(54)
43
41
#define IRQ_AC97 IRQ_SPI(55)
44
42
#define IRQ_SPDIF IRQ_SPI(56)
···
69
67
#define IRQ_IIC COMBINER_IRQ(27, 0)
70
68
71
69
/* Set the default NR_IRQS */
70
+
72
71
#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0)
73
72
74
73
#define MAX_COMBINER_NR 39
75
74
76
-
#endif /* ASM_ARCH_IRQS_H */
75
+
#endif /* __ASM_ARCH_IRQS_H */
+14
-2
arch/arm/mach-s5pv310/include/mach/map.h
+14
-2
arch/arm/mach-s5pv310/include/mach/map.h
···
23
23
24
24
#include <plat/map-s5p.h>
25
25
26
+
#define S5PV310_PA_SYSRAM (0x02025000)
27
+
26
28
#define S5PV310_PA_CHIPID (0x10000000)
27
29
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
28
30
29
31
#define S5PV310_PA_SYSCON (0x10020000)
30
32
#define S5P_PA_SYSCON S5PV310_PA_SYSCON
33
+
34
+
#define S5PV310_PA_CMU (0x10030000)
31
35
32
36
#define S5PV310_PA_WATCHDOG (0x10060000)
33
37
···
43
39
#define S5PV310_PA_GIC_DIST (0x10501000)
44
40
#define S5PV310_PA_L2CC (0x10502000)
45
41
46
-
#define S5PV310_PA_GPIO (0x11000000)
47
-
#define S5P_PA_GPIO S5PV310_PA_GPIO
42
+
#define S5PV310_PA_GPIO1 (0x11400000)
43
+
#define S5PV310_PA_GPIO2 (0x11000000)
44
+
#define S5PV310_PA_GPIO3 (0x03860000)
45
+
#define S5P_PA_GPIO S5PV310_PA_GPIO1
46
+
47
+
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
48
48
49
49
#define S5PV310_PA_UART (0x13800000)
50
50
···
71
63
72
64
/* compatibiltiy defines. */
73
65
#define S3C_PA_UART S5PV310_PA_UART
66
+
#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
67
+
#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
68
+
#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
69
+
#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
74
70
#define S3C_PA_IIC S5PV310_PA_IIC0
75
71
#define S3C_PA_WDT S5PV310_PA_WATCHDOG
76
72
+30
-29
arch/arm/mach-s5pv310/include/mach/regs-clock.h
+30
-29
arch/arm/mach-s5pv310/include/mach/regs-clock.h
···
15
15
16
16
#include <mach/map.h>
17
17
18
-
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
18
+
#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
19
19
20
20
#define S5P_INFORM0 S5P_CLKREG(0x800)
21
21
22
-
#define S5P_EPLL_CON0 S5P_CLKREG(0x1C110)
23
-
#define S5P_EPLL_CON1 S5P_CLKREG(0x1C114)
24
-
#define S5P_VPLL_CON0 S5P_CLKREG(0x1C120)
25
-
#define S5P_VPLL_CON1 S5P_CLKREG(0x1C124)
22
+
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
23
+
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
24
+
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
25
+
#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
26
26
27
-
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x1C210)
28
-
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x1C214)
27
+
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
28
+
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
29
29
30
-
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x1C250)
30
+
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
31
31
32
-
#define S5P_CLKDIV_TOP S5P_CLKREG(0x1C510)
32
+
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
33
33
34
-
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x1C550)
35
-
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x1C554)
36
-
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x1C558)
37
-
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x1C55C)
38
-
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x1C560)
39
-
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x1C564)
34
+
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
35
+
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
36
+
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
37
+
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
38
+
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
39
+
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
40
40
41
-
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x1C950)
41
+
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
42
42
43
-
#define S5P_CLKSRC_CORE S5P_CLKREG(0x20200)
43
+
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
44
44
45
-
#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x20500)
45
+
#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
46
+
#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500)
46
47
47
-
#define S5P_APLL_LOCK S5P_CLKREG(0x24000)
48
-
#define S5P_MPLL_LOCK S5P_CLKREG(0x24004)
49
-
#define S5P_APLL_CON0 S5P_CLKREG(0x24100)
50
-
#define S5P_APLL_CON1 S5P_CLKREG(0x24104)
51
-
#define S5P_MPLL_CON0 S5P_CLKREG(0x24108)
52
-
#define S5P_MPLL_CON1 S5P_CLKREG(0x2410C)
48
+
#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
49
+
#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
50
+
#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
51
+
#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
52
+
#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
53
+
#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
53
54
54
-
#define S5P_CLKSRC_CPU S5P_CLKREG(0x24200)
55
-
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x24400)
55
+
#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
56
+
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
56
57
57
-
#define S5P_CLKDIV_CPU S5P_CLKREG(0x24500)
58
-
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x24600)
58
+
#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
59
+
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
59
60
60
-
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x24800)
61
+
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
61
62
62
63
#endif /* __ASM_ARCH_REGS_CLOCK_H */
+1
-1
arch/arm/mach-s5pv310/include/mach/vmalloc.h
+1
-1
arch/arm/mach-s5pv310/include/mach/vmalloc.h
+1
-1
arch/arm/mach-s5pv310/platsmp.c
+1
-1
arch/arm/mach-s5pv310/platsmp.c
···
187
187
* until it receives a soft interrupt, and then the
188
188
* secondary CPU branches to this address.
189
189
*/
190
-
__raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_INFORM0);
190
+
__raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
191
191
}
192
192
}
+2
arch/arm/plat-s5p/include/plat/map-s5p.h
+2
arch/arm/plat-s5p/include/plat/map-s5p.h
···
17
17
#define S5P_VA_GPIO S3C_ADDR(0x00500000)
18
18
#define S5P_VA_SYSTIMER S3C_ADDR(0x01200000)
19
19
#define S5P_VA_SROMC S3C_ADDR(0x01100000)
20
+
#define S5P_VA_SYSRAM S3C_ADDR(0x01180000)
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#define S5P_VA_COMBINER_BASE S3C_ADDR(0x00600000)
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#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
···
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#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
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#define S5P_VA_L2CC S3C_ADDR(0x00900000)
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+
#define S5P_VA_CMU S3C_ADDR(0x00920000)
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#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
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#define S5P_VA_UART0 S5P_VA_UART(0)