Merge tag 'drm-fixes-2020-02-28' of git://anongit.freedesktop.org/drm/drm

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

··· 1389 1389 1390 1390 static struct drm_driver kms_driver = { 1391 1391 .driver_features = 1392 - DRIVER_USE_AGP | DRIVER_ATOMIC | 1392 + DRIVER_ATOMIC | 1393 1393 DRIVER_GEM | 1394 1394 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1395 1395 DRIVER_SYNCOBJ_TIMELINE,

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

··· 195 195 uint32_t srbm_soft_reset; 196 196 bool prt_warning; 197 197 uint64_t stolen_size; 198 + uint32_t sdpif_register; 198 199 /* apertures */ 199 200 u64 shared_aperture_start; 200 201 u64 shared_aperture_end;

+36 -1

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

··· 1272 1272 } 1273 1273 1274 1274 /** 1275 + * gmc_v9_0_restore_registers - restores regs 1276 + * 1277 + * @adev: amdgpu_device pointer 1278 + * 1279 + * This restores register values, saved at suspend. 1280 + */ 1281 + static void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 1282 + { 1283 + if (adev->asic_type == CHIP_RAVEN) 1284 + WREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 1285 + } 1286 + 1287 + /** 1275 1288 * gmc_v9_0_gart_enable - gart enable 1276 1289 * 1277 1290 * @adev: amdgpu_device pointer ··· 1390 1377 } 1391 1378 1392 1379 /** 1380 + * gmc_v9_0_save_registers - saves regs 1381 + * 1382 + * @adev: amdgpu_device pointer 1383 + * 1384 + * This saves potential register values that should be 1385 + * restored upon resume 1386 + */ 1387 + static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1388 + { 1389 + if (adev->asic_type == CHIP_RAVEN) 1390 + adev->gmc.sdpif_register = RREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1391 + } 1392 + 1393 + /** 1393 1394 * gmc_v9_0_gart_disable - gart disable 1394 1395 * 1395 1396 * @adev: amdgpu_device pointer ··· 1439 1412 1440 1413 static int gmc_v9_0_suspend(void *handle) 1441 1414 { 1415 + int r; 1442 1416 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1443 1417 1444 - return gmc_v9_0_hw_fini(adev); 1418 + r = gmc_v9_0_hw_fini(adev); 1419 + if (r) 1420 + return r; 1421 + 1422 + gmc_v9_0_save_registers(adev); 1423 + 1424 + return 0; 1445 1425 } 1446 1426 1447 1427 static int gmc_v9_0_resume(void *handle) ··· 1456 1422 int r; 1457 1423 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1458 1424 1425 + gmc_v9_0_restore_registers(adev); 1459 1426 r = gmc_v9_0_hw_init(adev); 1460 1427 if (r) 1461 1428 return r;

+2

drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h

··· 7376 7376 #define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e 7377 7377 #define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2 7378 7378 7379 + #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x395d 7380 + #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 7379 7381 7380 7382 // addressBlock: dce_dc_fmt4_dispdec 7381 7383 // base address: 0x2000

+5 -1

drivers/gpu/drm/amd/powerplay/smu_v11_0.c

··· 978 978 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks; 979 979 int ret = 0; 980 980 981 - max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), 981 + if (!smu->smu_table.max_sustainable_clocks) 982 + max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), 982 983 GFP_KERNEL); 984 + else 985 + max_sustainable_clocks = smu->smu_table.max_sustainable_clocks; 986 + 983 987 smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks; 984 988 985 989 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;

+1 -1

drivers/gpu/drm/i915/Makefile

··· 294 294 $(shell cd $(srctree)/$(src) && find * -name '*.h'))) 295 295 296 296 quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@) 297 - cmd_hdrtest = $(CC) $(c_flags) -S -o /dev/null -x c /dev/null -include $<; touch $@ 297 + cmd_hdrtest = $(CC) $(filter-out $(CFLAGS_GCOV), $(c_flags)) -S -o /dev/null -x c /dev/null -include $<; touch $@ 298 298 299 299 $(obj)/%.hdrtest: $(src)/%.h FORCE 300 300 $(call if_changed_dep,hdrtest)

+1 -3

drivers/gpu/drm/i915/gem/i915_gem_shrinker.c

··· 256 256 with_intel_runtime_pm(&i915->runtime_pm, wakeref) { 257 257 freed = i915_gem_shrink(i915, -1UL, NULL, 258 258 I915_SHRINK_BOUND | 259 - I915_SHRINK_UNBOUND | 260 - I915_SHRINK_ACTIVE); 259 + I915_SHRINK_UNBOUND); 261 260 } 262 261 263 262 return freed; ··· 335 336 freed_pages = 0; 336 337 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 337 338 freed_pages += i915_gem_shrink(i915, -1UL, NULL, 338 - I915_SHRINK_ACTIVE | 339 339 I915_SHRINK_BOUND | 340 340 I915_SHRINK_UNBOUND | 341 341 I915_SHRINK_WRITEBACK);

+1 -1

drivers/gpu/drm/i915/gvt/dmabuf.c

··· 151 151 dmabuf_obj = container_of(pos, 152 152 struct intel_vgpu_dmabuf_obj, list); 153 153 if (dmabuf_obj == obj) { 154 + list_del(pos); 154 155 intel_gvt_hypervisor_put_vfio_device(vgpu); 155 156 idr_remove(&vgpu->object_idr, 156 157 dmabuf_obj->dmabuf_id); 157 158 kfree(dmabuf_obj->info); 158 159 kfree(dmabuf_obj); 159 - list_del(pos); 160 160 break; 161 161 } 162 162 }

+1 -1

drivers/gpu/drm/i915/gvt/vgpu.c

··· 560 560 561 561 intel_vgpu_reset_mmio(vgpu, dmlr); 562 562 populate_pvinfo_page(vgpu); 563 - intel_vgpu_reset_display(vgpu); 564 563 565 564 if (dmlr) { 565 + intel_vgpu_reset_display(vgpu); 566 566 intel_vgpu_reset_cfg_space(vgpu); 567 567 /* only reset the failsafe mode when dmlr reset */ 568 568 vgpu->failsafe = false;

+2 -2

drivers/gpu/drm/i915/i915_pci.c

··· 437 437 .has_rc6 = 1, \ 438 438 .has_rc6p = 1, \ 439 439 .has_rps = true, \ 440 - .ppgtt_type = INTEL_PPGTT_FULL, \ 440 + .ppgtt_type = INTEL_PPGTT_ALIASING, \ 441 441 .ppgtt_size = 31, \ 442 442 IVB_PIPE_OFFSETS, \ 443 443 IVB_CURSOR_OFFSETS, \ ··· 494 494 .has_rps = true, 495 495 .display.has_gmch = 1, 496 496 .display.has_hotplug = 1, 497 - .ppgtt_type = INTEL_PPGTT_FULL, 497 + .ppgtt_type = INTEL_PPGTT_ALIASING, 498 498 .ppgtt_size = 31, 499 499 .has_snoop = true, 500 500 .has_coherent_ggtt = false,

+31 -28

drivers/gpu/drm/i915/i915_pmu.c

··· 822 822 return sprintf(buf, "config=0x%lx\n", eattr->val); 823 823 } 824 824 825 - static struct attribute_group i915_pmu_events_attr_group = { 826 - .name = "events", 827 - /* Patch in attrs at runtime. */ 828 - }; 829 - 830 825 static ssize_t 831 826 i915_pmu_get_attr_cpumask(struct device *dev, 832 827 struct device_attribute *attr, ··· 839 844 840 845 static const struct attribute_group i915_pmu_cpumask_attr_group = { 841 846 .attrs = i915_cpumask_attrs, 842 - }; 843 - 844 - static const struct attribute_group *i915_pmu_attr_groups[] = { 845 - &i915_pmu_format_attr_group, 846 - &i915_pmu_events_attr_group, 847 - &i915_pmu_cpumask_attr_group, 848 - NULL 849 847 }; 850 848 851 849 #define __event(__config, __name, __unit) \ ··· 1014 1026 1015 1027 static void free_event_attributes(struct i915_pmu *pmu) 1016 1028 { 1017 - struct attribute **attr_iter = i915_pmu_events_attr_group.attrs; 1029 + struct attribute **attr_iter = pmu->events_attr_group.attrs; 1018 1030 1019 1031 for (; *attr_iter; attr_iter++) 1020 1032 kfree((*attr_iter)->name); 1021 1033 1022 - kfree(i915_pmu_events_attr_group.attrs); 1034 + kfree(pmu->events_attr_group.attrs); 1023 1035 kfree(pmu->i915_attr); 1024 1036 kfree(pmu->pmu_attr); 1025 1037 1026 - i915_pmu_events_attr_group.attrs = NULL; 1038 + pmu->events_attr_group.attrs = NULL; 1027 1039 pmu->i915_attr = NULL; 1028 1040 pmu->pmu_attr = NULL; 1029 1041 } 1030 1042 1031 1043 static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node) 1032 1044 { 1033 - struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node); 1045 + struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node); 1034 1046 1035 1047 GEM_BUG_ON(!pmu->base.event_init); 1036 1048 ··· 1043 1055 1044 1056 static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node) 1045 1057 { 1046 - struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node); 1058 + struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node); 1047 1059 unsigned int target; 1048 1060 1049 1061 GEM_BUG_ON(!pmu->base.event_init); ··· 1060 1072 return 0; 1061 1073 } 1062 1074 1063 - static enum cpuhp_state cpuhp_slot = CPUHP_INVALID; 1064 - 1065 1075 static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu) 1066 1076 { 1067 1077 enum cpuhp_state slot; ··· 1073 1087 return ret; 1074 1088 1075 1089 slot = ret; 1076 - ret = cpuhp_state_add_instance(slot, &pmu->node); 1090 + ret = cpuhp_state_add_instance(slot, &pmu->cpuhp.node); 1077 1091 if (ret) { 1078 1092 cpuhp_remove_multi_state(slot); 1079 1093 return ret; 1080 1094 } 1081 1095 1082 - cpuhp_slot = slot; 1096 + pmu->cpuhp.slot = slot; 1083 1097 return 0; 1084 1098 } 1085 1099 1086 1100 static void i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu) 1087 1101 { 1088 - WARN_ON(cpuhp_slot == CPUHP_INVALID); 1089 - WARN_ON(cpuhp_state_remove_instance(cpuhp_slot, &pmu->node)); 1090 - cpuhp_remove_multi_state(cpuhp_slot); 1102 + WARN_ON(pmu->cpuhp.slot == CPUHP_INVALID); 1103 + WARN_ON(cpuhp_state_remove_instance(pmu->cpuhp.slot, &pmu->cpuhp.node)); 1104 + cpuhp_remove_multi_state(pmu->cpuhp.slot); 1105 + pmu->cpuhp.slot = CPUHP_INVALID; 1091 1106 } 1092 1107 1093 1108 static bool is_igp(struct drm_i915_private *i915) ··· 1105 1118 void i915_pmu_register(struct drm_i915_private *i915) 1106 1119 { 1107 1120 struct i915_pmu *pmu = &i915->pmu; 1121 + const struct attribute_group *attr_groups[] = { 1122 + &i915_pmu_format_attr_group, 1123 + &pmu->events_attr_group, 1124 + &i915_pmu_cpumask_attr_group, 1125 + NULL 1126 + }; 1127 + 1108 1128 int ret = -ENOMEM; 1109 1129 1110 1130 if (INTEL_GEN(i915) <= 2) { ··· 1122 1128 spin_lock_init(&pmu->lock); 1123 1129 hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1124 1130 pmu->timer.function = i915_sample; 1131 + pmu->cpuhp.slot = CPUHP_INVALID; 1125 1132 1126 1133 if (!is_igp(i915)) { 1127 1134 pmu->name = kasprintf(GFP_KERNEL, ··· 1138 1143 if (!pmu->name) 1139 1144 goto err; 1140 1145 1141 - i915_pmu_events_attr_group.attrs = create_event_attributes(pmu); 1142 - if (!i915_pmu_events_attr_group.attrs) 1146 + pmu->events_attr_group.name = "events"; 1147 + pmu->events_attr_group.attrs = create_event_attributes(pmu); 1148 + if (!pmu->events_attr_group.attrs) 1143 1149 goto err_name; 1144 1150 1145 - pmu->base.attr_groups = i915_pmu_attr_groups; 1151 + pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups), 1152 + GFP_KERNEL); 1153 + if (!pmu->base.attr_groups) 1154 + goto err_attr; 1155 + 1146 1156 pmu->base.task_ctx_nr = perf_invalid_context; 1147 1157 pmu->base.event_init = i915_pmu_event_init; 1148 1158 pmu->base.add = i915_pmu_event_add; ··· 1159 1159 1160 1160 ret = perf_pmu_register(&pmu->base, pmu->name, -1); 1161 1161 if (ret) 1162 - goto err_attr; 1162 + goto err_groups; 1163 1163 1164 1164 ret = i915_pmu_register_cpuhp_state(pmu); 1165 1165 if (ret) ··· 1169 1169 1170 1170 err_unreg: 1171 1171 perf_pmu_unregister(&pmu->base); 1172 + err_groups: 1173 + kfree(pmu->base.attr_groups); 1172 1174 err_attr: 1173 1175 pmu->base.event_init = NULL; 1174 1176 free_event_attributes(pmu); ··· 1196 1194 1197 1195 perf_pmu_unregister(&pmu->base); 1198 1196 pmu->base.event_init = NULL; 1197 + kfree(pmu->base.attr_groups); 1199 1198 if (!is_igp(i915)) 1200 1199 kfree(pmu->name); 1201 1200 free_event_attributes(pmu);

+9 -2

drivers/gpu/drm/i915/i915_pmu.h

··· 39 39 40 40 struct i915_pmu { 41 41 /** 42 - * @node: List node for CPU hotplug handling. 42 + * @cpuhp: Struct used for CPU hotplug handling. 43 43 */ 44 - struct hlist_node node; 44 + struct { 45 + struct hlist_node node; 46 + enum cpuhp_state slot; 47 + } cpuhp; 45 48 /** 46 49 * @base: PMU base. 47 50 */ ··· 107 104 * @sleep_last: Last time GT parked for RC6 estimation. 108 105 */ 109 106 ktime_t sleep_last; 107 + /** 108 + * @events_attr_group: Device events attribute group. 109 + */ 110 + struct attribute_group events_attr_group; 110 111 /** 111 112 * @i915_attr: Memory block holding device attributes. 112 113 */

+41 -2

drivers/gpu/drm/radeon/radeon_drv.c

··· 37 37 #include <linux/vga_switcheroo.h> 38 38 #include <linux/mmu_notifier.h> 39 39 40 + #include <drm/drm_agpsupport.h> 40 41 #include <drm/drm_crtc_helper.h> 41 42 #include <drm/drm_drv.h> 42 43 #include <drm/drm_fb_helper.h> ··· 326 325 const struct pci_device_id *ent) 327 326 { 328 327 unsigned long flags = 0; 328 + struct drm_device *dev; 329 329 int ret; 330 330 331 331 if (!ent) ··· 367 365 if (ret) 368 366 return ret; 369 367 370 - return drm_get_pci_dev(pdev, ent, &kms_driver); 368 + dev = drm_dev_alloc(&kms_driver, &pdev->dev); 369 + if (IS_ERR(dev)) 370 + return PTR_ERR(dev); 371 + 372 + ret = pci_enable_device(pdev); 373 + if (ret) 374 + goto err_free; 375 + 376 + dev->pdev = pdev; 377 + #ifdef __alpha__ 378 + dev->hose = pdev->sysdata; 379 + #endif 380 + 381 + pci_set_drvdata(pdev, dev); 382 + 383 + if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) 384 + dev->agp = drm_agp_init(dev); 385 + if (dev->agp) { 386 + dev->agp->agp_mtrr = arch_phys_wc_add( 387 + dev->agp->agp_info.aper_base, 388 + dev->agp->agp_info.aper_size * 389 + 1024 * 1024); 390 + } 391 + 392 + ret = drm_dev_register(dev, ent->driver_data); 393 + if (ret) 394 + goto err_agp; 395 + 396 + return 0; 397 + 398 + err_agp: 399 + if (dev->agp) 400 + arch_phys_wc_del(dev->agp->agp_mtrr); 401 + kfree(dev->agp); 402 + pci_disable_device(pdev); 403 + err_free: 404 + drm_dev_put(dev); 405 + return ret; 371 406 } 372 407 373 408 static void ··· 614 575 615 576 static struct drm_driver kms_driver = { 616 577 .driver_features = 617 - DRIVER_USE_AGP | DRIVER_GEM | DRIVER_RENDER, 578 + DRIVER_GEM | DRIVER_RENDER, 618 579 .load = radeon_driver_load_kms, 619 580 .open = radeon_driver_open_kms, 620 581 .postclose = radeon_driver_postclose_kms,

+6

drivers/gpu/drm/radeon/radeon_kms.c

··· 32 32 #include <linux/uaccess.h> 33 33 #include <linux/vga_switcheroo.h> 34 34 35 + #include <drm/drm_agpsupport.h> 35 36 #include <drm/drm_fb_helper.h> 36 37 #include <drm/drm_file.h> 37 38 #include <drm/drm_ioctl.h> ··· 77 76 78 77 radeon_modeset_fini(rdev); 79 78 radeon_device_fini(rdev); 79 + 80 + if (dev->agp) 81 + arch_phys_wc_del(dev->agp->agp_mtrr); 82 + kfree(dev->agp); 83 + dev->agp = NULL; 80 84 81 85 done_free: 82 86 kfree(rdev);

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