Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2024-09-13' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Regular fixes pull, the amdgpu JPEG engine fixes are probably the
biggest, they look to block some register accessing, otherwise there
are just minor fixes and regression fixes all over.
nouveau had a regression report going back a few kernels that finally
got fixed, Not entirely happy with so many changes so late, but they
all seem quite benign apart from the jpeg one.
dma-buf/heaps:
- fix off by one in CMA heap fault handler
syncobj:
- fix syncobj leak in drm_syncobj_eventfd_ioctl
amdgpu:
- Avoid races between set_drr() functions and dc_state_destruct()
- Fix regerssion related to zpos
- Fix regression related to overlay cursor
- SMU 14.x updates
- JPEG fixes
- Silence an UBSAN warning
amdkfd:
- Fetch cacheline size from IP discovery
i915:
- Prevent a possible int overflow in wq offsets
xe:
- Remove a double include
- Fix null checks and UAF
- Fix access_ok check in user_fence_create
- Fix compat IS_DISPLAY_STEP() range
- OA fix
- Fixes in show_meminfo
nouveau:
- fix GP10x regression on boot
stm:
- add COMMON_CLK dep
rockchip:
- iommu api change
tegra:
- iommu api change"
* tag 'drm-fixes-2024-09-13' of https://gitlab.freedesktop.org/drm/kernel: (25 commits)
drm/xe/client: add missing bo locking in show_meminfo()
drm/xe/client: fix deadlock in show_meminfo()
drm/xe/oa: Enable Xe2+ PES disaggregation
drm/xe/display: fix compat IS_DISPLAY_STEP() range end
drm/xe: Fix access_ok check in user_fence_create
drm/xe: Fix possible UAF in guc_exec_queue_process_msg
drm/xe: Remove fence check from send_tlb_invalidation
drm/xe/gt: Remove double include
drm/amd/display: Add all planes on CRTC to state for overlay cursor
drm/amdgpu/atomfirmware: Silence UBSAN warning
drm/amd/amdgpu: apply command submission parser for JPEG v1
drm/amd/amdgpu: apply command submission parser for JPEG v2+
drm/amd/pm: fix the pp_dpm_pcie issue on smu v14.0.2/3
drm/amd/pm: update the features set on smu v14.0.2/3
drm/amd/display: Do not reset planes based on crtc zpos_changed
drm/amd/display: Avoid race between dcn35_set_drr() and dc_state_destruct()
drm/amd/display: Avoid race between dcn10_set_drr() and dc_state_destruct()
drm/amdkfd: Add cache line size info
drm/tegra: Use iommu_paging_domain_alloc()
drm/rockchip: Use iommu_paging_domain_alloc()
...
+315
-109
+1
-1
drivers/dma-buf/heaps/cma_heap.c
+1
-1
drivers/dma-buf/heaps/cma_heap.c
···
165
165
struct vm_area_struct *vma = vmf->vma;
166
166
struct cma_heap_buffer *buffer = vma->vm_private_data;
167
167
168
-
if (vmf->pgoff > buffer->pagecount)
168
+
if (vmf->pgoff >= buffer->pagecount)
169
169
return VM_FAULT_SIGBUS;
170
170
171
171
return vmf_insert_pfn(vma, vmf->address, page_to_pfn(buffer->pages[vmf->pgoff]));
+75
-1
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+75
-1
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
···
23
23
24
24
#include "amdgpu.h"
25
25
#include "amdgpu_jpeg.h"
26
+
#include "amdgpu_cs.h"
26
27
#include "soc15.h"
27
28
#include "soc15d.h"
28
29
#include "vcn_v1_0.h"
···
35
34
static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
36
35
static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev);
37
36
static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring);
37
+
static int jpeg_v1_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
38
+
struct amdgpu_job *job,
39
+
struct amdgpu_ib *ib);
38
40
39
41
static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
40
42
{
···
304
300
305
301
amdgpu_ring_write(ring,
306
302
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
307
-
amdgpu_ring_write(ring, (vmid | (vmid << 4)));
303
+
if (ring->funcs->parse_cs)
304
+
amdgpu_ring_write(ring, 0);
305
+
else
306
+
amdgpu_ring_write(ring, (vmid | (vmid << 4)));
308
307
309
308
amdgpu_ring_write(ring,
310
309
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
···
561
554
.get_rptr = jpeg_v1_0_decode_ring_get_rptr,
562
555
.get_wptr = jpeg_v1_0_decode_ring_get_wptr,
563
556
.set_wptr = jpeg_v1_0_decode_ring_set_wptr,
557
+
.parse_cs = jpeg_v1_dec_ring_parse_cs,
564
558
.emit_frame_size =
565
559
6 + 6 + /* hdp invalidate / flush */
566
560
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
···
618
610
}
619
611
620
612
vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
613
+
}
614
+
615
+
/**
616
+
* jpeg_v1_dec_ring_parse_cs - command submission parser
617
+
*
618
+
* @parser: Command submission parser context
619
+
* @job: the job to parse
620
+
* @ib: the IB to parse
621
+
*
622
+
* Parse the command stream, return -EINVAL for invalid packet,
623
+
* 0 otherwise
624
+
*/
625
+
static int jpeg_v1_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
626
+
struct amdgpu_job *job,
627
+
struct amdgpu_ib *ib)
628
+
{
629
+
u32 i, reg, res, cond, type;
630
+
int ret = 0;
631
+
struct amdgpu_device *adev = parser->adev;
632
+
633
+
for (i = 0; i < ib->length_dw ; i += 2) {
634
+
reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
635
+
res = CP_PACKETJ_GET_RES(ib->ptr[i]);
636
+
cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
637
+
type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
638
+
639
+
if (res || cond != PACKETJ_CONDITION_CHECK0) /* only allow 0 for now */
640
+
return -EINVAL;
641
+
642
+
if (reg >= JPEG_V1_REG_RANGE_START && reg <= JPEG_V1_REG_RANGE_END)
643
+
continue;
644
+
645
+
switch (type) {
646
+
case PACKETJ_TYPE0:
647
+
if (reg != JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_HIGH &&
648
+
reg != JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_LOW &&
649
+
reg != JPEG_V1_LMI_JPEG_READ_64BIT_BAR_HIGH &&
650
+
reg != JPEG_V1_LMI_JPEG_READ_64BIT_BAR_LOW &&
651
+
reg != JPEG_V1_REG_CTX_INDEX &&
652
+
reg != JPEG_V1_REG_CTX_DATA) {
653
+
ret = -EINVAL;
654
+
}
655
+
break;
656
+
case PACKETJ_TYPE1:
657
+
if (reg != JPEG_V1_REG_CTX_DATA)
658
+
ret = -EINVAL;
659
+
break;
660
+
case PACKETJ_TYPE3:
661
+
if (reg != JPEG_V1_REG_SOFT_RESET)
662
+
ret = -EINVAL;
663
+
break;
664
+
case PACKETJ_TYPE6:
665
+
if (ib->ptr[i] != CP_PACKETJ_NOP)
666
+
ret = -EINVAL;
667
+
break;
668
+
default:
669
+
ret = -EINVAL;
670
+
}
671
+
672
+
if (ret) {
673
+
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
674
+
break;
675
+
}
676
+
}
677
+
678
+
return ret;
621
679
}
+11
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h
+11
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h
···
29
29
void jpeg_v1_0_sw_fini(void *handle);
30
30
void jpeg_v1_0_start(struct amdgpu_device *adev, int mode);
31
31
32
+
#define JPEG_V1_REG_RANGE_START 0x8000
33
+
#define JPEG_V1_REG_RANGE_END 0x803f
34
+
35
+
#define JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x8238
36
+
#define JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x8239
37
+
#define JPEG_V1_LMI_JPEG_READ_64BIT_BAR_HIGH 0x825a
38
+
#define JPEG_V1_LMI_JPEG_READ_64BIT_BAR_LOW 0x825b
39
+
#define JPEG_V1_REG_CTX_INDEX 0x8328
40
+
#define JPEG_V1_REG_CTX_DATA 0x8329
41
+
#define JPEG_V1_REG_SOFT_RESET 0x83a0
42
+
32
43
#endif /*__JPEG_V1_0_H__*/
+62
-1
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+62
-1
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
···
23
23
24
24
#include "amdgpu.h"
25
25
#include "amdgpu_jpeg.h"
26
+
#include "amdgpu_cs.h"
26
27
#include "amdgpu_pm.h"
27
28
#include "soc15.h"
28
29
#include "soc15d.h"
···
539
538
540
539
amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
541
540
0, 0, PACKETJ_TYPE0));
542
-
amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
541
+
542
+
if (ring->funcs->parse_cs)
543
+
amdgpu_ring_write(ring, 0);
544
+
else
545
+
amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
543
546
544
547
amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
545
548
0, 0, PACKETJ_TYPE0));
···
769
764
.get_rptr = jpeg_v2_0_dec_ring_get_rptr,
770
765
.get_wptr = jpeg_v2_0_dec_ring_get_wptr,
771
766
.set_wptr = jpeg_v2_0_dec_ring_set_wptr,
767
+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
772
768
.emit_frame_size =
773
769
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
774
770
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
···
816
810
.rev = 0,
817
811
.funcs = &jpeg_v2_0_ip_funcs,
818
812
};
813
+
814
+
/**
815
+
* jpeg_v2_dec_ring_parse_cs - command submission parser
816
+
*
817
+
* @parser: Command submission parser context
818
+
* @job: the job to parse
819
+
* @ib: the IB to parse
820
+
*
821
+
* Parse the command stream, return -EINVAL for invalid packet,
822
+
* 0 otherwise
823
+
*/
824
+
int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
825
+
struct amdgpu_job *job,
826
+
struct amdgpu_ib *ib)
827
+
{
828
+
u32 i, reg, res, cond, type;
829
+
struct amdgpu_device *adev = parser->adev;
830
+
831
+
for (i = 0; i < ib->length_dw ; i += 2) {
832
+
reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
833
+
res = CP_PACKETJ_GET_RES(ib->ptr[i]);
834
+
cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
835
+
type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
836
+
837
+
if (res) /* only support 0 at the moment */
838
+
return -EINVAL;
839
+
840
+
switch (type) {
841
+
case PACKETJ_TYPE0:
842
+
if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START ||
843
+
reg > JPEG_REG_RANGE_END) {
844
+
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
845
+
return -EINVAL;
846
+
}
847
+
break;
848
+
case PACKETJ_TYPE3:
849
+
if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START ||
850
+
reg > JPEG_REG_RANGE_END) {
851
+
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
852
+
return -EINVAL;
853
+
}
854
+
break;
855
+
case PACKETJ_TYPE6:
856
+
if (ib->ptr[i] == CP_PACKETJ_NOP)
857
+
continue;
858
+
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
859
+
return -EINVAL;
860
+
default:
861
+
dev_err(adev->dev, "Unknown packet type %d !\n", type);
862
+
return -EINVAL;
863
+
}
864
+
}
865
+
866
+
return 0;
867
+
}
+6
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
+6
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
···
45
45
46
46
#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
47
47
48
+
#define JPEG_REG_RANGE_START 0x4000
49
+
#define JPEG_REG_RANGE_END 0x41c2
50
+
48
51
void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
49
52
void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
50
53
void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
···
60
57
unsigned vmid, uint64_t pd_addr);
61
58
void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
62
59
void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);
60
+
int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
61
+
struct amdgpu_job *job,
62
+
struct amdgpu_ib *ib);
63
63
64
64
extern const struct amdgpu_ip_block_version jpeg_v2_0_ip_block;
65
65
+2
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+2
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
···
662
662
.get_rptr = jpeg_v2_5_dec_ring_get_rptr,
663
663
.get_wptr = jpeg_v2_5_dec_ring_get_wptr,
664
664
.set_wptr = jpeg_v2_5_dec_ring_set_wptr,
665
+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
665
666
.emit_frame_size =
666
667
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
667
668
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
···
692
691
.get_rptr = jpeg_v2_5_dec_ring_get_rptr,
693
692
.get_wptr = jpeg_v2_5_dec_ring_get_wptr,
694
693
.set_wptr = jpeg_v2_5_dec_ring_set_wptr,
694
+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
695
695
.emit_frame_size =
696
696
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
697
697
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+1
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+1
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
···
560
560
.get_rptr = jpeg_v3_0_dec_ring_get_rptr,
561
561
.get_wptr = jpeg_v3_0_dec_ring_get_wptr,
562
562
.set_wptr = jpeg_v3_0_dec_ring_set_wptr,
563
+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
563
564
.emit_frame_size =
564
565
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
565
566
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+1
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
+1
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
···
727
727
.get_rptr = jpeg_v4_0_dec_ring_get_rptr,
728
728
.get_wptr = jpeg_v4_0_dec_ring_get_wptr,
729
729
.set_wptr = jpeg_v4_0_dec_ring_set_wptr,
730
+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
730
731
.emit_frame_size =
731
732
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
732
733
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
-1
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h
-1
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h
+2
-55
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+2
-55
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
···
23
23
24
24
#include "amdgpu.h"
25
25
#include "amdgpu_jpeg.h"
26
-
#include "amdgpu_cs.h"
27
26
#include "soc15.h"
28
27
#include "soc15d.h"
28
+
#include "jpeg_v2_0.h"
29
29
#include "jpeg_v4_0_3.h"
30
30
#include "mmsch_v4_0_3.h"
31
31
···
1089
1089
.get_rptr = jpeg_v4_0_3_dec_ring_get_rptr,
1090
1090
.get_wptr = jpeg_v4_0_3_dec_ring_get_wptr,
1091
1091
.set_wptr = jpeg_v4_0_3_dec_ring_set_wptr,
1092
-
.parse_cs = jpeg_v4_0_3_dec_ring_parse_cs,
1092
+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
1093
1093
.emit_frame_size =
1094
1094
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1095
1095
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
···
1253
1253
static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev)
1254
1254
{
1255
1255
adev->jpeg.ras = &jpeg_v4_0_3_ras;
1256
-
}
1257
-
1258
-
/**
1259
-
* jpeg_v4_0_3_dec_ring_parse_cs - command submission parser
1260
-
*
1261
-
* @parser: Command submission parser context
1262
-
* @job: the job to parse
1263
-
* @ib: the IB to parse
1264
-
*
1265
-
* Parse the command stream, return -EINVAL for invalid packet,
1266
-
* 0 otherwise
1267
-
*/
1268
-
int jpeg_v4_0_3_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
1269
-
struct amdgpu_job *job,
1270
-
struct amdgpu_ib *ib)
1271
-
{
1272
-
uint32_t i, reg, res, cond, type;
1273
-
struct amdgpu_device *adev = parser->adev;
1274
-
1275
-
for (i = 0; i < ib->length_dw ; i += 2) {
1276
-
reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
1277
-
res = CP_PACKETJ_GET_RES(ib->ptr[i]);
1278
-
cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
1279
-
type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
1280
-
1281
-
if (res) /* only support 0 at the moment */
1282
-
return -EINVAL;
1283
-
1284
-
switch (type) {
1285
-
case PACKETJ_TYPE0:
1286
-
if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END) {
1287
-
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
1288
-
return -EINVAL;
1289
-
}
1290
-
break;
1291
-
case PACKETJ_TYPE3:
1292
-
if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END) {
1293
-
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
1294
-
return -EINVAL;
1295
-
}
1296
-
break;
1297
-
case PACKETJ_TYPE6:
1298
-
if (ib->ptr[i] == CP_PACKETJ_NOP)
1299
-
continue;
1300
-
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
1301
-
return -EINVAL;
1302
-
default:
1303
-
dev_err(adev->dev, "Unknown packet type %d !\n", type);
1304
-
return -EINVAL;
1305
-
}
1306
-
}
1307
-
1308
-
return 0;
1309
1256
}
+1
-6
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h
+1
-6
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h
···
46
46
47
47
#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
48
48
49
-
#define JPEG_REG_RANGE_START 0x4000
50
-
#define JPEG_REG_RANGE_END 0x41c2
51
-
52
49
extern const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block;
53
50
54
51
void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,
···
62
65
void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
63
66
void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
64
67
uint32_t val, uint32_t mask);
65
-
int jpeg_v4_0_3_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
66
-
struct amdgpu_job *job,
67
-
struct amdgpu_ib *ib);
68
+
68
69
#endif /* __JPEG_V4_0_3_H__ */
+1
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
+1
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
···
768
768
.get_rptr = jpeg_v4_0_5_dec_ring_get_rptr,
769
769
.get_wptr = jpeg_v4_0_5_dec_ring_get_wptr,
770
770
.set_wptr = jpeg_v4_0_5_dec_ring_set_wptr,
771
+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
771
772
.emit_frame_size =
772
773
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
773
774
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+2
-1
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+2
-1
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
···
26
26
#include "amdgpu_pm.h"
27
27
#include "soc15.h"
28
28
#include "soc15d.h"
29
+
#include "jpeg_v2_0.h"
29
30
#include "jpeg_v4_0_3.h"
30
31
31
32
#include "vcn/vcn_5_0_0_offset.h"
···
647
646
.get_rptr = jpeg_v5_0_0_dec_ring_get_rptr,
648
647
.get_wptr = jpeg_v5_0_0_dec_ring_get_wptr,
649
648
.set_wptr = jpeg_v5_0_0_dec_ring_set_wptr,
650
-
.parse_cs = jpeg_v4_0_3_dec_ring_parse_cs,
649
+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
651
650
.emit_frame_size =
652
651
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
653
652
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+7
-1
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+7
-1
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
···
1434
1434
pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1435
1435
CRAT_CACHE_FLAGS_DATA_CACHE |
1436
1436
CRAT_CACHE_FLAGS_SIMD_CACHE);
1437
-
pcache_info[0].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;
1437
+
pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;
1438
+
pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size;
1438
1439
i++;
1439
1440
}
1440
1441
/* Scalar L1 Instruction Cache per SQC */
···
1447
1446
CRAT_CACHE_FLAGS_INST_CACHE |
1448
1447
CRAT_CACHE_FLAGS_SIMD_CACHE);
1449
1448
pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
1449
+
pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size;
1450
1450
i++;
1451
1451
}
1452
1452
/* Scalar L1 Data Cache per SQC */
···
1458
1456
CRAT_CACHE_FLAGS_DATA_CACHE |
1459
1457
CRAT_CACHE_FLAGS_SIMD_CACHE);
1460
1458
pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
1459
+
pcache_info[i].cache_line_size = adev->gfx.config.gc_scalar_data_cache_line_size;
1461
1460
i++;
1462
1461
}
1463
1462
/* GL1 Data Cache per SA */
···
1471
1468
CRAT_CACHE_FLAGS_DATA_CACHE |
1472
1469
CRAT_CACHE_FLAGS_SIMD_CACHE);
1473
1470
pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1471
+
pcache_info[i].cache_line_size = 0;
1474
1472
i++;
1475
1473
}
1476
1474
/* L2 Data Cache per GPU (Total Tex Cache) */
···
1482
1478
CRAT_CACHE_FLAGS_DATA_CACHE |
1483
1479
CRAT_CACHE_FLAGS_SIMD_CACHE);
1484
1480
pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1481
+
pcache_info[i].cache_line_size = adev->gfx.config.gc_tcc_cache_line_size;
1485
1482
i++;
1486
1483
}
1487
1484
/* L3 Data Cache per GPU */
···
1493
1488
CRAT_CACHE_FLAGS_DATA_CACHE |
1494
1489
CRAT_CACHE_FLAGS_SIMD_CACHE);
1495
1490
pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1491
+
pcache_info[i].cache_line_size = 0;
1496
1492
i++;
1497
1493
}
1498
1494
return i;
+12
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+12
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
10571
10571
* TODO: We can likely skip bandwidth validation if the only thing that
10572
10572
* changed about the plane was it'z z-ordering.
10573
10573
*/
10574
-
if (new_crtc_state->zpos_changed)
10574
+
if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos)
10575
10575
return true;
10576
10576
10577
10577
if (drm_atomic_crtc_needs_modeset(new_crtc_state))
···
11418
11418
if (ret) {
11419
11419
drm_dbg(dev, "Failed to determine cursor mode\n");
11420
11420
goto fail;
11421
+
}
11422
+
11423
+
/*
11424
+
* If overlay cursor is needed, DC cannot go through the
11425
+
* native cursor update path. All enabled planes on the CRTC
11426
+
* need to be added for DC to not disable a plane by mistake
11427
+
*/
11428
+
if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) {
11429
+
ret = drm_atomic_add_affected_planes(state, crtc);
11430
+
if (ret)
11431
+
goto fail;
11421
11432
}
11422
11433
}
11423
11434
+12
-8
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+12
-8
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
···
3207
3207
* as well.
3208
3208
*/
3209
3209
for (i = 0; i < num_pipes; i++) {
3210
-
if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs) {
3211
-
if (pipe_ctx[i]->stream_res.tg->funcs->set_drr)
3212
-
pipe_ctx[i]->stream_res.tg->funcs->set_drr(
3213
-
pipe_ctx[i]->stream_res.tg, ¶ms);
3210
+
/* dc_state_destruct() might null the stream resources, so fetch tg
3211
+
* here first to avoid a race condition. The lifetime of the pointee
3212
+
* itself (the timing_generator object) is not a problem here.
3213
+
*/
3214
+
struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;
3215
+
3216
+
if ((tg != NULL) && tg->funcs) {
3217
+
if (tg->funcs->set_drr)
3218
+
tg->funcs->set_drr(tg, ¶ms);
3214
3219
if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
3215
-
if (pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control)
3216
-
pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
3217
-
pipe_ctx[i]->stream_res.tg,
3218
-
event_triggers, num_frames);
3220
+
if (tg->funcs->set_static_screen_control)
3221
+
tg->funcs->set_static_screen_control(
3222
+
tg, event_triggers, num_frames);
3219
3223
}
3220
3224
}
3221
3225
}
+12
-8
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+12
-8
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
···
1462
1462
params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num;
1463
1463
1464
1464
for (i = 0; i < num_pipes; i++) {
1465
-
if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs) {
1465
+
/* dc_state_destruct() might null the stream resources, so fetch tg
1466
+
* here first to avoid a race condition. The lifetime of the pointee
1467
+
* itself (the timing_generator object) is not a problem here.
1468
+
*/
1469
+
struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;
1470
+
1471
+
if ((tg != NULL) && tg->funcs) {
1466
1472
struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;
1467
1473
struct dc *dc = pipe_ctx[i]->stream->ctx->dc;
1468
1474
···
1481
1475
num_frames = 2 * (frame_rate % 60);
1482
1476
}
1483
1477
}
1484
-
if (pipe_ctx[i]->stream_res.tg->funcs->set_drr)
1485
-
pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1486
-
pipe_ctx[i]->stream_res.tg, ¶ms);
1478
+
if (tg->funcs->set_drr)
1479
+
tg->funcs->set_drr(tg, ¶ms);
1487
1480
if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
1488
-
if (pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control)
1489
-
pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1490
-
pipe_ctx[i]->stream_res.tg,
1491
-
event_triggers, num_frames);
1481
+
if (tg->funcs->set_static_screen_control)
1482
+
tg->funcs->set_static_screen_control(
1483
+
tg, event_triggers, num_frames);
1492
1484
}
1493
1485
}
1494
1486
}
+2
-2
drivers/gpu/drm/amd/include/atomfirmware.h
+2
-2
drivers/gpu/drm/amd/include/atomfirmware.h
···
1038
1038
uint16_t supporteddevices;
1039
1039
uint8_t number_of_path;
1040
1040
uint8_t reserved;
1041
-
struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
1041
+
struct atom_display_object_path_v2 display_path[]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
1042
1042
};
1043
1043
1044
1044
struct display_object_info_table_v1_5 {
···
1048
1048
uint8_t reserved;
1049
1049
// the real number of this included in the structure is calculated by using the
1050
1050
// (whole structure size - the header size- number_of_path)/size of atom_display_object_path
1051
-
struct atom_display_object_path_v3 display_path[8];
1051
+
struct atom_display_object_path_v3 display_path[];
1052
1052
};
1053
1053
1054
1054
/*
+10
-1
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+10
-1
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
···
439
439
__SMU_DUMMY_MAP(BACO_CG), \
440
440
__SMU_DUMMY_MAP(SOC_CG), \
441
441
__SMU_DUMMY_MAP(LOW_POWER_DCNCLKS), \
442
-
__SMU_DUMMY_MAP(WHISPER_MODE),
442
+
__SMU_DUMMY_MAP(WHISPER_MODE), \
443
+
__SMU_DUMMY_MAP(EDC_PWRBRK), \
444
+
__SMU_DUMMY_MAP(SOC_EDC_XVMIN), \
445
+
__SMU_DUMMY_MAP(GFX_PSM_DIDT), \
446
+
__SMU_DUMMY_MAP(APT_ALL_ENABLE), \
447
+
__SMU_DUMMY_MAP(APT_SQ_THROTTLE), \
448
+
__SMU_DUMMY_MAP(APT_PF_DCS), \
449
+
__SMU_DUMMY_MAP(GFX_EDC_XVMIN), \
450
+
__SMU_DUMMY_MAP(GFX_DIDT_XVMIN), \
451
+
__SMU_DUMMY_MAP(FAN_ABNORMAL),
443
452
444
453
#undef __SMU_DUMMY_MAP
445
454
#define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT
+12
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+12
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
···
187
187
FEA_MAP(MEM_TEMP_READ),
188
188
FEA_MAP(ATHUB_MMHUB_PG),
189
189
FEA_MAP(SOC_PCC),
190
+
FEA_MAP(EDC_PWRBRK),
191
+
FEA_MAP(SOC_EDC_XVMIN),
192
+
FEA_MAP(GFX_PSM_DIDT),
193
+
FEA_MAP(APT_ALL_ENABLE),
194
+
FEA_MAP(APT_SQ_THROTTLE),
195
+
FEA_MAP(APT_PF_DCS),
196
+
FEA_MAP(GFX_EDC_XVMIN),
197
+
FEA_MAP(GFX_DIDT_XVMIN),
198
+
FEA_MAP(FAN_ABNORMAL),
190
199
[SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
191
200
[SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
192
201
[SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
···
683
674
pcie_table->clk_freq[pcie_table->num_of_link_levels] =
684
675
skutable->LclkFreq[link_level];
685
676
pcie_table->num_of_link_levels++;
677
+
678
+
if (link_level == 0)
679
+
link_level++;
686
680
}
687
681
688
682
/* dcefclk dpm table setup */
+13
-4
drivers/gpu/drm/drm_syncobj.c
+13
-4
drivers/gpu/drm/drm_syncobj.c
···
1464
1464
struct drm_syncobj *syncobj;
1465
1465
struct eventfd_ctx *ev_fd_ctx;
1466
1466
struct syncobj_eventfd_entry *entry;
1467
+
int ret;
1467
1468
1468
1469
if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ_TIMELINE))
1469
1470
return -EOPNOTSUPP;
···
1480
1479
return -ENOENT;
1481
1480
1482
1481
ev_fd_ctx = eventfd_ctx_fdget(args->fd);
1483
-
if (IS_ERR(ev_fd_ctx))
1484
-
return PTR_ERR(ev_fd_ctx);
1482
+
if (IS_ERR(ev_fd_ctx)) {
1483
+
ret = PTR_ERR(ev_fd_ctx);
1484
+
goto err_fdget;
1485
+
}
1485
1486
1486
1487
entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1487
1488
if (!entry) {
1488
-
eventfd_ctx_put(ev_fd_ctx);
1489
-
return -ENOMEM;
1489
+
ret = -ENOMEM;
1490
+
goto err_kzalloc;
1490
1491
}
1491
1492
entry->syncobj = syncobj;
1492
1493
entry->ev_fd_ctx = ev_fd_ctx;
···
1499
1496
drm_syncobj_put(syncobj);
1500
1497
1501
1498
return 0;
1499
+
1500
+
err_kzalloc:
1501
+
eventfd_ctx_put(ev_fd_ctx);
1502
+
err_fdget:
1503
+
drm_syncobj_put(syncobj);
1504
+
return ret;
1502
1505
}
1503
1506
1504
1507
int
+2
-2
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+2
-2
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
···
2842
2842
ce->parallel.guc.wqi_tail = 0;
2843
2843
ce->parallel.guc.wqi_head = 0;
2844
2844
2845
-
wq_desc_offset = i915_ggtt_offset(ce->state) +
2845
+
wq_desc_offset = (u64)i915_ggtt_offset(ce->state) +
2846
2846
__get_parent_scratch_offset(ce);
2847
-
wq_base_offset = i915_ggtt_offset(ce->state) +
2847
+
wq_base_offset = (u64)i915_ggtt_offset(ce->state) +
2848
2848
__get_wq_offset(ce);
2849
2849
info->wq_desc_lo = lower_32_bits(wq_desc_offset);
2850
2850
info->wq_desc_hi = upper_32_bits(wq_desc_offset);
+2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h
+2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h
···
46
46
u32 gm200_ram_probe_fbp_amount(const struct nvkm_ram_func *, u32,
47
47
struct nvkm_device *, int, int *);
48
48
49
+
int gp100_ram_init(struct nvkm_ram *);
50
+
49
51
/* RAM type-specific MR calculation routines */
50
52
int nvkm_sddr2_calc(struct nvkm_ram *);
51
53
int nvkm_sddr3_calc(struct nvkm_ram *);
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c
+1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp102.c
+1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp102.c
+7
-3
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+7
-3
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
···
103
103
struct rockchip_drm_private *private = drm_dev->dev_private;
104
104
struct iommu_domain_geometry *geometry;
105
105
u64 start, end;
106
+
int ret;
106
107
107
108
if (IS_ERR_OR_NULL(private->iommu_dev))
108
109
return 0;
109
110
110
-
private->domain = iommu_domain_alloc(private->iommu_dev->bus);
111
-
if (!private->domain)
112
-
return -ENOMEM;
111
+
private->domain = iommu_paging_domain_alloc(private->iommu_dev);
112
+
if (IS_ERR(private->domain)) {
113
+
ret = PTR_ERR(private->domain);
114
+
private->domain = NULL;
115
+
return ret;
116
+
}
113
117
114
118
geometry = &private->domain->geometry;
115
119
start = geometry->aperture_start;
+1
drivers/gpu/drm/stm/Kconfig
+1
drivers/gpu/drm/stm/Kconfig
+3
-2
drivers/gpu/drm/tegra/drm.c
+3
-2
drivers/gpu/drm/tegra/drm.c
···
1135
1135
1136
1136
static int host1x_drm_probe(struct host1x_device *dev)
1137
1137
{
1138
+
struct device *dma_dev = dev->dev.parent;
1138
1139
struct tegra_drm *tegra;
1139
1140
struct drm_device *drm;
1140
1141
int err;
···
1150
1149
goto put;
1151
1150
}
1152
1151
1153
-
if (host1x_drm_wants_iommu(dev) && iommu_present(&platform_bus_type)) {
1154
-
tegra->domain = iommu_domain_alloc(&platform_bus_type);
1152
+
if (host1x_drm_wants_iommu(dev) && device_iommu_mapped(dma_dev)) {
1153
+
tegra->domain = iommu_paging_domain_alloc(dma_dev);
1155
1154
if (!tegra->domain) {
1156
1155
err = -ENOMEM;
1157
1156
goto free;
+1
-1
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+1
-1
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
···
83
83
#define HAS_GMD_ID(xe) GRAPHICS_VERx100(xe) >= 1270
84
84
85
85
/* Workarounds not handled yet */
86
-
#define IS_DISPLAY_STEP(xe, first, last) ({u8 __step = (xe)->info.step.display; first <= __step && __step <= last; })
86
+
#define IS_DISPLAY_STEP(xe, first, last) ({u8 __step = (xe)->info.step.display; first <= __step && __step < last; })
87
87
88
88
#define IS_LP(xe) (0)
89
89
#define IS_GEN9_LP(xe) (0)
+1
drivers/gpu/drm/xe/regs/xe_oa_regs.h
+1
drivers/gpu/drm/xe/regs/xe_oa_regs.h
···
52
52
#define OAG_OABUFFER_MEMORY_SELECT REG_BIT(0) /* 0: PPGTT, 1: GGTT */
53
53
54
54
#define OAG_OACONTROL XE_REG(0xdaf4)
55
+
#define OAG_OACONTROL_OA_PES_DISAG_EN REG_GENMASK(27, 22)
55
56
#define OAG_OACONTROL_OA_CCS_SELECT_MASK REG_GENMASK(18, 16)
56
57
#define OAG_OACONTROL_OA_COUNTER_SEL_MASK REG_GENMASK(4, 2)
57
58
#define OAG_OACONTROL_OA_COUNTER_ENABLE REG_BIT(0)
+41
-4
drivers/gpu/drm/xe/xe_drm_client.c
+41
-4
drivers/gpu/drm/xe/xe_drm_client.c
···
10
10
#include <linux/slab.h>
11
11
#include <linux/types.h>
12
12
13
+
#include "xe_assert.h"
13
14
#include "xe_bo.h"
14
15
#include "xe_bo_types.h"
15
16
#include "xe_device_types.h"
···
152
151
*/
153
152
void xe_drm_client_remove_bo(struct xe_bo *bo)
154
153
{
154
+
struct xe_device *xe = ttm_to_xe_device(bo->ttm.bdev);
155
155
struct xe_drm_client *client = bo->client;
156
156
157
+
xe_assert(xe, !kref_read(&bo->ttm.base.refcount));
158
+
157
159
spin_lock(&client->bos_lock);
158
-
list_del(&bo->client_link);
160
+
list_del_init(&bo->client_link);
159
161
spin_unlock(&client->bos_lock);
160
162
161
163
xe_drm_client_put(client);
···
169
165
{
170
166
u64 sz = bo->size;
171
167
u32 mem_type;
168
+
169
+
xe_bo_assert_held(bo);
172
170
173
171
if (bo->placement.placement)
174
172
mem_type = bo->placement.placement->mem_type;
···
202
196
struct xe_drm_client *client;
203
197
struct drm_gem_object *obj;
204
198
struct xe_bo *bo;
199
+
LLIST_HEAD(deferred);
205
200
unsigned int id;
206
201
u32 mem_type;
207
202
···
213
206
idr_for_each_entry(&file->object_idr, obj, id) {
214
207
struct xe_bo *bo = gem_to_xe_bo(obj);
215
208
216
-
bo_meminfo(bo, stats);
209
+
if (dma_resv_trylock(bo->ttm.base.resv)) {
210
+
bo_meminfo(bo, stats);
211
+
xe_bo_unlock(bo);
212
+
} else {
213
+
xe_bo_get(bo);
214
+
spin_unlock(&file->table_lock);
215
+
216
+
xe_bo_lock(bo, false);
217
+
bo_meminfo(bo, stats);
218
+
xe_bo_unlock(bo);
219
+
220
+
xe_bo_put(bo);
221
+
spin_lock(&file->table_lock);
222
+
}
217
223
}
218
224
spin_unlock(&file->table_lock);
219
225
···
235
215
list_for_each_entry(bo, &client->bos_list, client_link) {
236
216
if (!kref_get_unless_zero(&bo->ttm.base.refcount))
237
217
continue;
238
-
bo_meminfo(bo, stats);
239
-
xe_bo_put(bo);
218
+
219
+
if (dma_resv_trylock(bo->ttm.base.resv)) {
220
+
bo_meminfo(bo, stats);
221
+
xe_bo_unlock(bo);
222
+
} else {
223
+
spin_unlock(&client->bos_lock);
224
+
225
+
xe_bo_lock(bo, false);
226
+
bo_meminfo(bo, stats);
227
+
xe_bo_unlock(bo);
228
+
229
+
spin_lock(&client->bos_lock);
230
+
/* The bo ref will prevent this bo from being removed from the list */
231
+
xe_assert(xef->xe, !list_empty(&bo->client_link));
232
+
}
233
+
234
+
xe_bo_put_deferred(bo, &deferred);
240
235
}
241
236
spin_unlock(&client->bos_lock);
237
+
238
+
xe_bo_put_commit(&deferred);
242
239
243
240
for (mem_type = XE_PL_SYSTEM; mem_type < TTM_NUM_MEM_TYPES; ++mem_type) {
244
241
if (!xe_mem_type_to_name[mem_type])
-1
drivers/gpu/drm/xe/xe_gt.c
-1
drivers/gpu/drm/xe/xe_gt.c
+2
-2
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
+2
-2
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
···
182
182
action[1] = seqno;
183
183
ret = xe_guc_ct_send_locked(&guc->ct, action, len,
184
184
G2H_LEN_DW_TLB_INVALIDATE, 1);
185
-
if (!ret && fence) {
185
+
if (!ret) {
186
186
spin_lock_irq(>->tlb_invalidation.pending_lock);
187
187
/*
188
188
* We haven't actually published the TLB fence as per
···
203
203
tlb_timeout_jiffies(gt));
204
204
}
205
205
spin_unlock_irq(>->tlb_invalidation.pending_lock);
206
-
} else if (ret < 0 && fence) {
206
+
} else if (ret < 0) {
207
207
__invalidation_fence_signal(xe, fence);
208
208
}
209
209
if (!ret) {
+3
-1
drivers/gpu/drm/xe/xe_guc_submit.c
+3
-1
drivers/gpu/drm/xe/xe_guc_submit.c
···
1375
1375
1376
1376
static void guc_exec_queue_process_msg(struct xe_sched_msg *msg)
1377
1377
{
1378
+
struct xe_device *xe = guc_to_xe(exec_queue_to_guc(msg->private_data));
1379
+
1378
1380
trace_xe_sched_msg_recv(msg);
1379
1381
1380
1382
switch (msg->opcode) {
···
1396
1394
XE_WARN_ON("Unknown message type");
1397
1395
}
1398
1396
1399
-
xe_pm_runtime_put(guc_to_xe(exec_queue_to_guc(msg->private_data)));
1397
+
xe_pm_runtime_put(xe);
1400
1398
}
1401
1399
1402
1400
static const struct drm_sched_backend_ops drm_sched_ops = {
+4
drivers/gpu/drm/xe/xe_oa.c
+4
drivers/gpu/drm/xe/xe_oa.c
···
440
440
val = __format_to_oactrl(format, regs->oa_ctrl_counter_select_mask) |
441
441
__oa_ccs_select(stream) | OAG_OACONTROL_OA_COUNTER_ENABLE;
442
442
443
+
if (GRAPHICS_VER(stream->oa->xe) >= 20 &&
444
+
stream->hwe->oa_unit->type == DRM_XE_OA_UNIT_TYPE_OAG)
445
+
val |= OAG_OACONTROL_OA_PES_DISAG_EN;
446
+
443
447
xe_mmio_write32(stream->gt, regs->oa_ctrl, val);
444
448
}
445
449