Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: qat - add wireless mode support for QAT GEN6
Add wireless mode support for QAT GEN6 devices.
When the WCP_WAT fuse bit is clear, the device operates in wireless
cipher mode (wcy_mode). In this mode all accelerator engines load the
wireless firmware and service configuration via 'cfg_services' sysfs
attribute is restricted to 'sym' only.
The get_accel_cap() function is extended to report wireless-specific
capabilities (ZUC, ZUC-256, 5G, extended algorithm chaining) gated by
their respective slice-disable fuse bits. The set_ssm_wdtimer() function
is updated to configure WCP (wireless cipher) and WAT (wireless
authentication) watchdog timers. The adf_gen6_cfg_dev_init() function is
updated to use adf_6xxx_is_wcy() to enforce sym-only service selection
for WCY devices during initialization.
Co-developed-by: Aviraj Cj <aviraj.cj@intel.com>
Signed-off-by: Aviraj Cj <aviraj.cj@intel.com>
Signed-off-by: George Abraham P <george.abraham.p@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
George Abraham P
and committed by
Herbert Xu
464da0bf
3fcfff4e
+137
-18
+90
-7
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
+90
-7
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
···
82
82
0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00
83
83
};
84
84
85
+
static const unsigned long thrd_mask_wcy[ADF_6XXX_MAX_ACCELENGINES] = {
86
+
0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x00
87
+
};
88
+
85
89
static const char *const adf_6xxx_fw_objs[] = {
86
90
[ADF_FW_CY_OBJ] = ADF_6XXX_CY_OBJ,
87
91
[ADF_FW_DC_OBJ] = ADF_6XXX_DC_OBJ,
88
92
[ADF_FW_ADMIN_OBJ] = ADF_6XXX_ADMIN_OBJ,
93
+
[ADF_FW_WCY_OBJ] = ADF_6XXX_WCY_OBJ,
89
94
};
90
95
91
96
static const struct adf_fw_config adf_default_fw_config[] = {
92
97
{ ADF_AE_GROUP_1, ADF_FW_DC_OBJ },
93
98
{ ADF_AE_GROUP_0, ADF_FW_CY_OBJ },
99
+
{ ADF_AE_GROUP_2, ADF_FW_ADMIN_OBJ },
100
+
};
101
+
102
+
static const struct adf_fw_config adf_wcy_fw_config[] = {
103
+
{ ADF_AE_GROUP_1, ADF_FW_WCY_OBJ },
104
+
{ ADF_AE_GROUP_0, ADF_FW_WCY_OBJ },
94
105
{ ADF_AE_GROUP_2, ADF_FW_ADMIN_OBJ },
95
106
};
96
107
···
127
116
default:
128
117
return false;
129
118
}
119
+
}
120
+
121
+
static bool wcy_services_supported(unsigned long mask)
122
+
{
123
+
/* The wireless SKU supports only the symmetric crypto service */
124
+
return mask == BIT(SVC_SYM);
130
125
}
131
126
132
127
static int get_service(unsigned long *mask)
···
172
155
}
173
156
}
174
157
175
-
static const unsigned long *get_thrd_mask(unsigned int service)
158
+
static const unsigned long *get_thrd_mask(struct adf_accel_dev *accel_dev,
159
+
unsigned int service)
176
160
{
161
+
if (adf_6xxx_is_wcy(GET_HW_DATA(accel_dev)))
162
+
return (service == SVC_SYM) ? thrd_mask_wcy : NULL;
163
+
177
164
switch (service) {
178
165
case SVC_SYM:
179
166
return thrd_mask_sym;
···
215
194
return service;
216
195
217
196
rp_config[i].ring_type = get_ring_type(service);
218
-
rp_config[i].thrd_mask = get_thrd_mask(service);
197
+
rp_config[i].thrd_mask = get_thrd_mask(accel_dev, service);
219
198
220
199
/*
221
200
* If there is only one service enabled, use all ring pairs for
···
407
386
ADF_CSR_WR64_LO_HI(addr, ADF_SSMWDTCNVL_OFFSET, ADF_SSMWDTCNVH_OFFSET, val);
408
387
ADF_CSR_WR64_LO_HI(addr, ADF_SSMWDTUCSL_OFFSET, ADF_SSMWDTUCSH_OFFSET, val);
409
388
ADF_CSR_WR64_LO_HI(addr, ADF_SSMWDTDCPRL_OFFSET, ADF_SSMWDTDCPRH_OFFSET, val);
389
+
ADF_CSR_WR64_LO_HI(addr, ADF_SSMWDTWCPL_OFFSET, ADF_SSMWDTWCPH_OFFSET, val);
390
+
ADF_CSR_WR64_LO_HI(addr, ADF_SSMWDTWATL_OFFSET, ADF_SSMWDTWATH_OFFSET, val);
410
391
411
392
/* Enable watchdog timer for pke */
412
393
ADF_CSR_WR64_LO_HI(addr, ADF_SSMWDTPKEL_OFFSET, ADF_SSMWDTPKEH_OFFSET, val_pke);
···
654
631
return set_vc_config(accel_dev);
655
632
}
656
633
634
+
static const struct adf_fw_config *get_fw_config(struct adf_accel_dev *accel_dev)
635
+
{
636
+
return adf_6xxx_is_wcy(GET_HW_DATA(accel_dev)) ? adf_wcy_fw_config :
637
+
adf_default_fw_config;
638
+
}
639
+
657
640
static u32 get_ae_mask(struct adf_hw_device_data *self)
658
641
{
659
642
unsigned long fuses = self->fuses[ADF_FUSECTL4];
···
682
653
return mask;
683
654
}
684
655
656
+
static u32 get_accel_cap_wcy(struct adf_accel_dev *accel_dev)
657
+
{
658
+
u32 capabilities_sym;
659
+
u32 fuse;
660
+
661
+
fuse = GET_HW_DATA(accel_dev)->fuses[ADF_FUSECTL1];
662
+
663
+
capabilities_sym = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
664
+
ICP_ACCEL_CAPABILITIES_CIPHER |
665
+
ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
666
+
ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT |
667
+
ICP_ACCEL_CAPABILITIES_5G |
668
+
ICP_ACCEL_CAPABILITIES_ZUC |
669
+
ICP_ACCEL_CAPABILITIES_ZUC_256 |
670
+
ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN;
671
+
672
+
if (fuse & ICP_ACCEL_GEN6_MASK_EIA3_SLICE) {
673
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC;
674
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC_256;
675
+
}
676
+
if (fuse & ICP_ACCEL_GEN6_MASK_ZUC_256_SLICE)
677
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC_256;
678
+
679
+
if (fuse & ICP_ACCEL_GEN6_MASK_5G_SLICE)
680
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_5G;
681
+
682
+
if (adf_get_service_enabled(accel_dev) == SVC_SYM)
683
+
return capabilities_sym;
684
+
685
+
return 0;
686
+
}
687
+
685
688
static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
686
689
{
687
690
u32 capabilities_sym, capabilities_asym;
···
721
660
unsigned long mask;
722
661
u32 caps = 0;
723
662
u32 fusectl1;
663
+
664
+
if (adf_6xxx_is_wcy(GET_HW_DATA(accel_dev)))
665
+
return get_accel_cap_wcy(accel_dev);
724
666
725
667
fusectl1 = GET_HW_DATA(accel_dev)->fuses[ADF_FUSECTL1];
726
668
···
797
733
798
734
static u32 uof_get_num_objs(struct adf_accel_dev *accel_dev)
799
735
{
800
-
return ARRAY_SIZE(adf_default_fw_config);
736
+
return adf_6xxx_is_wcy(GET_HW_DATA(accel_dev)) ?
737
+
ARRAY_SIZE(adf_wcy_fw_config) :
738
+
ARRAY_SIZE(adf_default_fw_config);
801
739
}
802
740
803
741
static const char *uof_get_name(struct adf_accel_dev *accel_dev, u32 obj_num)
804
742
{
805
743
int num_fw_objs = ARRAY_SIZE(adf_6xxx_fw_objs);
744
+
const struct adf_fw_config *fw_config;
806
745
int id;
807
746
808
-
id = adf_default_fw_config[obj_num].obj;
747
+
fw_config = get_fw_config(accel_dev);
748
+
id = fw_config[obj_num].obj;
809
749
if (id >= num_fw_objs)
810
750
return NULL;
811
751
···
823
755
824
756
static int uof_get_obj_type(struct adf_accel_dev *accel_dev, u32 obj_num)
825
757
{
758
+
const struct adf_fw_config *fw_config;
759
+
826
760
if (obj_num >= uof_get_num_objs(accel_dev))
827
761
return -EINVAL;
828
762
829
-
return adf_default_fw_config[obj_num].obj;
763
+
fw_config = get_fw_config(accel_dev);
764
+
765
+
return fw_config[obj_num].obj;
830
766
}
831
767
832
768
static u32 uof_get_ae_mask(struct adf_accel_dev *accel_dev, u32 obj_num)
833
769
{
834
-
return adf_default_fw_config[obj_num].ae_mask;
770
+
const struct adf_fw_config *fw_config;
771
+
772
+
fw_config = get_fw_config(accel_dev);
773
+
return fw_config[obj_num].ae_mask;
835
774
}
836
775
837
776
static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)
···
948
873
init_num_svc_aes(rl_data);
949
874
}
950
875
876
+
static void adf_gen6_init_services_supported(struct adf_hw_device_data *hw_data)
877
+
{
878
+
if (adf_6xxx_is_wcy(hw_data))
879
+
hw_data->services_supported = wcy_services_supported;
880
+
else
881
+
hw_data->services_supported = services_supported;
882
+
}
883
+
951
884
void adf_init_hw_data_6xxx(struct adf_hw_device_data *hw_data)
952
885
{
953
886
hw_data->dev_class = &adf_6xxx_class;
···
1012
929
hw_data->stop_timer = adf_timer_stop;
1013
930
hw_data->init_device = adf_init_device;
1014
931
hw_data->enable_pm = enable_pm;
1015
-
hw_data->services_supported = services_supported;
1016
932
hw_data->num_rps = ADF_GEN6_ETR_MAX_BANKS;
1017
933
hw_data->clock_frequency = ADF_6XXX_AE_FREQ;
1018
934
hw_data->get_svc_slice_cnt = adf_gen6_get_svc_slice_cnt;
1019
935
936
+
adf_gen6_init_services_supported(hw_data);
1020
937
adf_gen6_init_hw_csr_ops(&hw_data->csr_ops);
1021
938
adf_gen6_init_pf_pfvf_ops(&hw_data->pfvf_ops);
1022
939
adf_gen6_init_dc_ops(&hw_data->dc_ops);
+14
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h
+14
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h
···
64
64
#define ADF_SSMWDTATHH_OFFSET 0x520C
65
65
#define ADF_SSMWDTCNVL_OFFSET 0x5408
66
66
#define ADF_SSMWDTCNVH_OFFSET 0x540C
67
+
#define ADF_SSMWDTWCPL_OFFSET 0x5608
68
+
#define ADF_SSMWDTWCPH_OFFSET 0x560C
67
69
#define ADF_SSMWDTUCSL_OFFSET 0x5808
68
70
#define ADF_SSMWDTUCSH_OFFSET 0x580C
69
71
#define ADF_SSMWDTDCPRL_OFFSET 0x5A08
70
72
#define ADF_SSMWDTDCPRH_OFFSET 0x5A0C
73
+
#define ADF_SSMWDTWATL_OFFSET 0x5C08
74
+
#define ADF_SSMWDTWATH_OFFSET 0x5C0C
71
75
#define ADF_SSMWDTPKEL_OFFSET 0x5E08
72
76
#define ADF_SSMWDTPKEH_OFFSET 0x5E0C
73
77
···
143
139
#define ADF_6XXX_CY_OBJ "qat_6xxx_cy.bin"
144
140
#define ADF_6XXX_DC_OBJ "qat_6xxx_dc.bin"
145
141
#define ADF_6XXX_ADMIN_OBJ "qat_6xxx_admin.bin"
142
+
#define ADF_6XXX_WCY_OBJ "qat_6xxx_wcy.bin"
146
143
147
144
/* RL constants */
148
145
#define ADF_6XXX_RL_PCIE_SCALE_FACTOR_DIV 100
···
164
159
ICP_ACCEL_GEN6_MASK_PKE_SLICE = BIT(2),
165
160
ICP_ACCEL_GEN6_MASK_CPR_SLICE = BIT(3),
166
161
ICP_ACCEL_GEN6_MASK_DCPRZ_SLICE = BIT(4),
162
+
ICP_ACCEL_GEN6_MASK_EIA3_SLICE = BIT(5),
167
163
ICP_ACCEL_GEN6_MASK_WCP_WAT_SLICE = BIT(6),
164
+
ICP_ACCEL_GEN6_MASK_ZUC_256_SLICE = BIT(7),
165
+
ICP_ACCEL_GEN6_MASK_5G_SLICE = BIT(8),
168
166
};
167
+
168
+
/* Return true if the device is a wireless crypto (WCY) SKU */
169
+
static inline bool adf_6xxx_is_wcy(struct adf_hw_device_data *hw_data)
170
+
{
171
+
return !(hw_data->fuses[ADF_FUSECTL1] & ICP_ACCEL_GEN6_MASK_WCP_WAT_SLICE);
172
+
}
169
173
170
174
void adf_init_hw_data_6xxx(struct adf_hw_device_data *hw_data);
171
175
void adf_clean_hw_data_6xxx(struct adf_hw_device_data *hw_data);
+30
-3
drivers/crypto/intel/qat/qat_6xxx/adf_drv.c
+30
-3
drivers/crypto/intel/qat/qat_6xxx/adf_drv.c
···
16
16
17
17
#include "adf_gen6_shared.h"
18
18
#include "adf_6xxx_hw_data.h"
19
+
#include "adf_heartbeat.h"
19
20
20
21
static int bar_map[] = {
21
22
0, /* SRAM */
···
52
51
static void adf_devmgr_remove(void *accel_dev)
53
52
{
54
53
adf_devmgr_rm_dev(accel_dev, NULL);
54
+
}
55
+
56
+
static int adf_gen6_cfg_dev_init(struct adf_accel_dev *accel_dev)
57
+
{
58
+
const char *config;
59
+
int ret;
60
+
61
+
/*
62
+
* Wireless SKU - symmetric crypto service only
63
+
* Non-wireless SKU - crypto service for even devices and compression for odd devices
64
+
*/
65
+
if (adf_6xxx_is_wcy(GET_HW_DATA(accel_dev)))
66
+
config = ADF_CFG_SYM;
67
+
else
68
+
config = accel_dev->accel_id % 2 ? ADF_CFG_DC : ADF_CFG_CY;
69
+
70
+
ret = adf_cfg_section_add(accel_dev, ADF_GENERAL_SEC);
71
+
if (ret)
72
+
return ret;
73
+
74
+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_GENERAL_SEC,
75
+
ADF_SERVICES_ENABLED, config,
76
+
ADF_STR);
77
+
if (ret)
78
+
return ret;
79
+
80
+
adf_heartbeat_save_cfg_param(accel_dev, ADF_CFG_HB_TIMER_MIN_MS);
81
+
82
+
return 0;
55
83
}
56
84
57
85
static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
···
120
90
pci_read_config_dword(pdev, ADF_GEN6_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]);
121
91
pci_read_config_dword(pdev, ADF_GEN6_FUSECTL0_OFFSET, &hw_data->fuses[ADF_FUSECTL0]);
122
92
pci_read_config_dword(pdev, ADF_GEN6_FUSECTL1_OFFSET, &hw_data->fuses[ADF_FUSECTL1]);
123
-
124
-
if (!(hw_data->fuses[ADF_FUSECTL1] & ICP_ACCEL_GEN6_MASK_WCP_WAT_SLICE))
125
-
return dev_err_probe(dev, -EFAULT, "Wireless mode is not supported.\n");
126
93
127
94
/* Enable PCI device */
128
95
ret = pcim_enable_device(pdev);
+1
drivers/crypto/intel/qat/qat_common/adf_fw_config.h
+1
drivers/crypto/intel/qat/qat_common/adf_fw_config.h
+2
-1
drivers/crypto/intel/qat/qat_common/icp_qat_hw.h
+2
-1
drivers/crypto/intel/qat/qat_common/icp_qat_hw.h
···
94
94
ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3),
95
95
ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4),
96
96
ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5),
97
-
/* Bits 6-7 are currently reserved */
97
+
/* Bit 6 is currently reserved */
98
+
ICP_ACCEL_CAPABILITIES_5G = BIT(7),
98
99
ICP_ACCEL_CAPABILITIES_ZUC = BIT(8),
99
100
ICP_ACCEL_CAPABILITIES_SHA3 = BIT(9),
100
101
/* Bits 10-11 are currently reserved */