Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] SB1: Check for -mno-sched-prolog if building corelis debug kernel.
[MIPS] Sibyte: Fix race in sb1250_gettimeoffset().
[MIPS] Sibyte: Fix interrupt timer off by one bug.
[MIPS] Sibyte: Fix M_SCD_TIMER_INIT and M_SCD_TIMER_CNT wrong field width.
[MIPS] Protect more of timer_interrupt() by xtime_lock.
[MIPS] Work around bad code generation for <asm/io.h>.
[MIPS] Simple patch to power off DBAU1200
[MIPS] Fix DBAu1550 software power off.
[MIPS] local_r4k_flush_cache_page fix
[MIPS] SB1: Fix interrupt disable hazard.
[MIPS] Get rid of the IP22-specific code in arclib.
Update MAINTAINERS entry for MIPS.
+220
-137
+2
-1
MAINTAINERS
+2
-1
MAINTAINERS
+2
-1
arch/mips/Makefile
+2
-1
arch/mips/Makefile
···
108
108
cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB)
109
109
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL)
110
110
111
-
cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer
111
+
cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
112
+
-fno-omit-frame-pointer
112
113
113
114
#
114
115
# Use: $(call set_gccflags,<cpu0>,<isa0>,<cpu1>,<isa1>,<isa2>)
-19
arch/mips/arc/misc.c
-19
arch/mips/arc/misc.c
···
9
9
* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
10
10
* Copyright (C) 1999 Silicon Graphics, Inc.
11
11
*/
12
-
#include <linux/config.h>
13
12
#include <linux/init.h>
14
13
#include <linux/kernel.h>
15
14
···
19
20
#include <asm/bootinfo.h>
20
21
#include <asm/system.h>
21
22
22
-
extern void *sgiwd93_host;
23
-
extern void reset_wd33c93(void *instance);
24
-
25
23
VOID
26
24
ArcHalt(VOID)
27
25
{
28
26
bc_disable();
29
27
local_irq_disable();
30
-
#ifdef CONFIG_SCSI_SGIWD93
31
-
reset_wd33c93(sgiwd93_host);
32
-
#endif
33
28
ARC_CALL0(halt);
34
29
never: goto never;
35
30
}
···
33
40
{
34
41
bc_disable();
35
42
local_irq_disable();
36
-
#ifdef CONFIG_SCSI_SGIWD93
37
-
reset_wd33c93(sgiwd93_host);
38
-
#endif
39
43
ARC_CALL0(pdown);
40
44
never: goto never;
41
45
}
···
43
53
{
44
54
bc_disable();
45
55
local_irq_disable();
46
-
#ifdef CONFIG_SCSI_SGIWD93
47
-
reset_wd33c93(sgiwd93_host);
48
-
#endif
49
56
ARC_CALL0(restart);
50
57
never: goto never;
51
58
}
···
52
65
{
53
66
bc_disable();
54
67
local_irq_disable();
55
-
#ifdef CONFIG_SCSI_SGIWD93
56
-
reset_wd33c93(sgiwd93_host);
57
-
#endif
58
68
ARC_CALL0(reboot);
59
69
never: goto never;
60
70
}
···
61
77
{
62
78
bc_disable();
63
79
local_irq_disable();
64
-
#ifdef CONFIG_SCSI_SGIWD93
65
-
reset_wd33c93(sgiwd93_host);
66
-
#endif
67
80
ARC_CALL0(imode);
68
81
never: goto never;
69
82
}
+7
-3
arch/mips/au1000/common/reset.c
+7
-3
arch/mips/au1000/common/reset.c
···
164
164
165
165
void au1000_halt(void)
166
166
{
167
-
#if defined(CONFIG_MIPS_PB1550)
167
+
#if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
168
168
/* power off system */
169
-
printk("\n** Powering off Pb1550\n");
169
+
printk("\n** Powering off...\n");
170
170
au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C);
171
171
au_sync();
172
172
while(1); /* should not get here */
173
-
#endif
173
+
#else
174
174
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
175
175
#ifdef CONFIG_MIPS_MIRAGE
176
176
au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
177
+
#endif
178
+
#ifdef CONFIG_MIPS_DB1200
179
+
au_writew(au_readw(0xB980001C) | (1<<14), 0xB980001C);
177
180
#endif
178
181
#ifdef CONFIG_PM
179
182
au_sleep();
···
190
187
"wait\n\t"
191
188
".set\tmips0");
192
189
#endif
190
+
#endif /* defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) */
193
191
}
194
192
195
193
void au1000_power_off(void)
+4
-2
arch/mips/kernel/time.c
+4
-2
arch/mips/kernel/time.c
···
424
424
unsigned long j;
425
425
unsigned int count;
426
426
427
+
write_seqlock(&xtime_lock);
428
+
427
429
count = mips_hpt_read();
428
430
mips_timer_ack();
429
431
···
443
441
* CMOS clock accordingly every ~11 minutes. rtc_set_time() has to be
444
442
* called as close as possible to 500 ms before the new second starts.
445
443
*/
446
-
write_seqlock(&xtime_lock);
447
444
if (ntp_synced() &&
448
445
xtime.tv_sec > last_rtc_update + 660 &&
449
446
(xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
···
454
453
last_rtc_update = xtime.tv_sec - 600;
455
454
}
456
455
}
457
-
write_sequnlock(&xtime_lock);
458
456
459
457
/*
460
458
* If jiffies has overflown in this timer_interrupt, we must
···
495
495
break;
496
496
}
497
497
}
498
+
499
+
write_sequnlock(&xtime_lock);
498
500
499
501
/*
500
502
* In UP mode, we call local_timer_interrupt() to do profiling
+9
-4
arch/mips/mm/c-r4k.c
+9
-4
arch/mips/mm/c-r4k.c
···
375
375
struct flush_cache_page_args {
376
376
struct vm_area_struct *vma;
377
377
unsigned long addr;
378
+
unsigned long pfn;
378
379
};
379
380
380
381
static inline void local_r4k_flush_cache_page(void *args)
···
383
382
struct flush_cache_page_args *fcp_args = args;
384
383
struct vm_area_struct *vma = fcp_args->vma;
385
384
unsigned long addr = fcp_args->addr;
385
+
unsigned long paddr = fcp_args->pfn << PAGE_SHIFT;
386
386
int exec = vma->vm_flags & VM_EXEC;
387
387
struct mm_struct *mm = vma->vm_mm;
388
388
pgd_t *pgdp;
···
433
431
* Do indexed flush, too much work to get the (possible) TLB refills
434
432
* to work correctly.
435
433
*/
436
-
addr = INDEX_BASE + (addr & (dcache_size - 1));
437
434
if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
438
-
r4k_blast_dcache_page_indexed(addr);
439
-
if (exec && !cpu_icache_snoops_remote_store)
440
-
r4k_blast_scache_page_indexed(addr);
435
+
r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ?
436
+
paddr : addr);
437
+
if (exec && !cpu_icache_snoops_remote_store) {
438
+
r4k_blast_scache_page_indexed(paddr);
439
+
}
441
440
}
442
441
if (exec) {
443
442
if (cpu_has_vtag_icache) {
···
458
455
459
456
args.vma = vma;
460
457
args.addr = addr;
458
+
args.pfn = pfn;
461
459
462
460
on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
463
461
}
···
960
956
switch (c->cputype) {
961
957
case CPU_20KC:
962
958
case CPU_25KF:
959
+
c->dcache.flags |= MIPS_CACHE_PINDEX;
963
960
case CPU_R10000:
964
961
case CPU_R12000:
965
962
case CPU_SB1:
-1
arch/mips/mm/c-tx39.c
-1
arch/mips/mm/c-tx39.c
+58
-19
arch/mips/sibyte/sb1250/time.c
+58
-19
arch/mips/sibyte/sb1250/time.c
···
47
47
#define IMR_IP3_VAL K_INT_MAP_I1
48
48
#define IMR_IP4_VAL K_INT_MAP_I2
49
49
50
+
#define SB1250_HPT_NUM 3
51
+
#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
52
+
#define SB1250_HPT_SHIFT ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH)
53
+
54
+
50
55
extern int sb1250_steal_irq(int irq);
56
+
57
+
static unsigned int sb1250_hpt_read(void);
58
+
static void sb1250_hpt_init(unsigned int);
59
+
60
+
static unsigned int hpt_offset;
61
+
62
+
void __init sb1250_hpt_setup(void)
63
+
{
64
+
int cpu = smp_processor_id();
65
+
66
+
if (!cpu) {
67
+
/* Setup hpt using timer #3 but do not enable irq for it */
68
+
__raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
69
+
__raw_writeq(SB1250_HPT_VALUE,
70
+
IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT)));
71
+
__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
72
+
IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
73
+
74
+
/*
75
+
* we need to fill 32 bits, so just use the upper 23 bits and pretend
76
+
* the timer is going 512Mhz instead of 1Mhz
77
+
*/
78
+
mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT;
79
+
mips_hpt_init = sb1250_hpt_init;
80
+
mips_hpt_read = sb1250_hpt_read;
81
+
}
82
+
}
83
+
51
84
52
85
void sb1250_time_init(void)
53
86
{
54
87
int cpu = smp_processor_id();
55
88
int irq = K_INT_TIMER_0+cpu;
56
89
57
-
/* Only have 4 general purpose timers */
58
-
if (cpu > 3) {
90
+
/* Only have 4 general purpose timers, and we use last one as hpt */
91
+
if (cpu > 2) {
59
92
BUG();
60
-
}
61
-
62
-
if (!cpu) {
63
-
/* Use our own gettimeoffset() routine */
64
-
do_gettimeoffset = sb1250_gettimeoffset;
65
93
}
66
94
67
95
sb1250_mask_irq(cpu, irq);
···
103
75
/* Disable the timer and set up the count */
104
76
__raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
105
77
#ifdef CONFIG_SIMULATION
106
-
__raw_writeq(50000 / HZ,
78
+
__raw_writeq((50000 / HZ) - 1,
107
79
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
108
80
#else
109
-
__raw_writeq(1000000 / HZ,
81
+
__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
110
82
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
111
83
#endif
112
84
···
131
103
int cpu = smp_processor_id();
132
104
int irq = K_INT_TIMER_0 + cpu;
133
105
134
-
/* Reset the timer */
106
+
/* ACK interrupt */
135
107
____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
136
108
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
137
109
···
150
122
}
151
123
152
124
/*
153
-
* We use our own do_gettimeoffset() instead of the generic one,
154
-
* because the generic one does not work for SMP case.
155
-
* In addition, since we use general timer 0 for system time,
156
-
* we can get accurate intra-jiffy offset without calibration.
125
+
* The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
126
+
* again. There's no easy way to set to a specific value so store init value
127
+
* in hpt_offset and subtract each time.
128
+
*
129
+
* Note: Timer isn't full 32bits so shift it into the upper part making
130
+
* it appear to run at a higher frequency.
157
131
*/
158
-
unsigned long sb1250_gettimeoffset(void)
132
+
static unsigned int sb1250_hpt_read(void)
159
133
{
160
-
unsigned long count =
161
-
__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
134
+
unsigned int count;
162
135
163
-
return 1000000/HZ - count;
164
-
}
136
+
count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
137
+
138
+
count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT;
139
+
140
+
return count - hpt_offset;
141
+
}
142
+
143
+
static void sb1250_hpt_init(unsigned int count)
144
+
{
145
+
hpt_offset = count;
146
+
return;
147
+
}
+7
arch/mips/sibyte/swarm/setup.c
+7
arch/mips/sibyte/swarm/setup.c
···
70
70
return "SiByte " SIBYTE_BOARD_NAME;
71
71
}
72
72
73
+
void __init swarm_time_init(void)
74
+
{
75
+
/* Setup HPT */
76
+
sb1250_hpt_setup();
77
+
}
78
+
73
79
void __init swarm_timer_setup(struct irqaction *irq)
74
80
{
75
81
/*
···
115
109
116
110
panic_timeout = 5; /* For debug. */
117
111
112
+
board_time_init = swarm_time_init;
118
113
board_timer_setup = swarm_timer_setup;
119
114
board_be_handler = swarm_be_handler;
120
115
+3
include/asm-mips/cpu-features.h
+3
include/asm-mips/cpu-features.h
···
96
96
#ifndef cpu_has_ic_fills_f_dc
97
97
#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
98
98
#endif
99
+
#ifndef cpu_has_pindexed_dcache
100
+
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
101
+
#endif
99
102
100
103
/*
101
104
* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
+1
include/asm-mips/cpu-info.h
+1
include/asm-mips/cpu-info.h
···
39
39
#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
40
40
#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
41
41
#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
42
+
#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
42
43
43
44
struct cpuinfo_mips {
44
45
unsigned long udelay_val;
+106
-80
include/asm-mips/hazards.h
+106
-80
include/asm-mips/hazards.h
···
3
3
* License. See the file "COPYING" in the main directory of this archive
4
4
* for more details.
5
5
*
6
-
* Copyright (C) 2003, 2004 Ralf Baechle
6
+
* Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
7
+
* Copyright (C) MIPS Technologies, Inc.
8
+
* written by Ralf Baechle <ralf@linux-mips.org>
7
9
*/
8
10
#ifndef _ASM_HAZARDS_H
9
11
#define _ASM_HAZARDS_H
···
76
74
#define irq_disable_hazard
77
75
_ehb
78
76
79
-
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
80
-
defined(CONFIG_CPU_SB1)
77
+
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
81
78
82
79
/*
83
80
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
···
100
99
#else /* __ASSEMBLY__ */
101
100
102
101
__asm__(
103
-
" .macro _ssnop \n\t"
104
-
" sll $0, $0, 1 \n\t"
105
-
" .endm \n\t"
106
-
" \n\t"
107
-
" .macro _ehb \n\t"
108
-
" sll $0, $0, 3 \n\t"
109
-
" .endm \n\t");
102
+
" .macro _ssnop \n"
103
+
" sll $0, $0, 1 \n"
104
+
" .endm \n"
105
+
" \n"
106
+
" .macro _ehb \n"
107
+
" sll $0, $0, 3 \n"
108
+
" .endm \n");
110
109
111
110
#ifdef CONFIG_CPU_RM9000
112
111
···
118
117
119
118
#define mtc0_tlbw_hazard() \
120
119
__asm__ __volatile__( \
121
-
".set\tmips32\n\t" \
122
-
"_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
123
-
".set\tmips0")
120
+
" .set mips32 \n" \
121
+
" _ssnop \n" \
122
+
" _ssnop \n" \
123
+
" _ssnop \n" \
124
+
" _ssnop \n" \
125
+
" .set mips0 \n")
124
126
125
127
#define tlbw_use_hazard() \
126
128
__asm__ __volatile__( \
127
-
".set\tmips32\n\t" \
128
-
"_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
129
-
".set\tmips0")
130
-
131
-
#define back_to_back_c0_hazard() do { } while (0)
129
+
" .set mips32 \n" \
130
+
" _ssnop \n" \
131
+
" _ssnop \n" \
132
+
" _ssnop \n" \
133
+
" _ssnop \n" \
134
+
" .set mips0 \n")
132
135
133
136
#else
134
137
···
141
136
*/
142
137
#define mtc0_tlbw_hazard() \
143
138
__asm__ __volatile__( \
144
-
".set noreorder\n\t" \
145
-
"nop; nop; nop; nop; nop; nop;\n\t" \
146
-
".set reorder\n\t")
139
+
" .set noreorder \n" \
140
+
" nop \n" \
141
+
" nop \n" \
142
+
" nop \n" \
143
+
" nop \n" \
144
+
" nop \n" \
145
+
" nop \n" \
146
+
" .set reorder \n")
147
147
148
148
#define tlbw_use_hazard() \
149
149
__asm__ __volatile__( \
150
-
".set noreorder\n\t" \
151
-
"nop; nop; nop; nop; nop; nop;\n\t" \
152
-
".set reorder\n\t")
150
+
" .set noreorder \n" \
151
+
" nop \n" \
152
+
" nop \n" \
153
+
" nop \n" \
154
+
" nop \n" \
155
+
" nop \n" \
156
+
" nop \n" \
157
+
" .set reorder \n")
153
158
154
159
#endif
155
160
···
171
156
172
157
#ifdef CONFIG_CPU_MIPSR2
173
158
174
-
__asm__(
175
-
" .macro\tirq_enable_hazard \n\t"
176
-
" _ehb \n\t"
177
-
" .endm \n\t"
178
-
" \n\t"
179
-
" .macro\tirq_disable_hazard \n\t"
180
-
" _ehb \n\t"
181
-
" .endm \n\t"
182
-
" \n\t"
183
-
" .macro\tback_to_back_c0_hazard \n\t"
184
-
" _ehb \n\t"
185
-
" .endm");
159
+
__asm__(" .macro irq_enable_hazard \n"
160
+
" _ehb \n"
161
+
" .endm \n"
162
+
" \n"
163
+
" .macro irq_disable_hazard \n"
164
+
" _ehb \n"
165
+
" .endm \n");
186
166
187
-
#define irq_enable_hazard() \
188
-
__asm__ __volatile__( \
189
-
"irq_enable_hazard")
190
-
191
-
#define irq_disable_hazard() \
192
-
__asm__ __volatile__( \
193
-
"irq_disable_hazard")
194
-
195
-
#define back_to_back_c0_hazard() \
196
-
__asm__ __volatile__( \
197
-
"back_to_back_c0_hazard")
198
-
199
-
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
200
-
defined(CONFIG_CPU_SB1)
167
+
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
201
168
202
169
/*
203
170
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
204
171
*/
205
172
206
173
__asm__(
207
-
" .macro\tirq_enable_hazard \n\t"
208
-
" .endm \n\t"
209
-
" \n\t"
210
-
" .macro\tirq_disable_hazard \n\t"
211
-
" .endm");
212
-
213
-
#define irq_enable_hazard() do { } while (0)
214
-
#define irq_disable_hazard() do { } while (0)
215
-
216
-
#define back_to_back_c0_hazard() do { } while (0)
174
+
" .macro irq_enable_hazard \n"
175
+
" .endm \n"
176
+
" \n"
177
+
" .macro irq_disable_hazard \n"
178
+
" .endm \n");
217
179
218
180
#else
219
181
···
201
209
*/
202
210
203
211
__asm__(
204
-
" # \n\t"
205
-
" # There is a hazard but we do not care \n\t"
206
-
" # \n\t"
207
-
" .macro\tirq_enable_hazard \n\t"
208
-
" .endm \n\t"
209
-
" \n\t"
210
-
" .macro\tirq_disable_hazard \n\t"
211
-
" _ssnop; _ssnop; _ssnop \n\t"
212
-
" .endm");
213
-
214
-
#define irq_enable_hazard() do { } while (0)
215
-
#define irq_disable_hazard() \
216
-
__asm__ __volatile__( \
217
-
"irq_disable_hazard")
218
-
219
-
#define back_to_back_c0_hazard() \
220
-
__asm__ __volatile__( \
221
-
" .set noreorder \n" \
222
-
" nop; nop; nop \n" \
223
-
" .set reorder \n")
212
+
" # \n"
213
+
" # There is a hazard but we do not care \n"
214
+
" # \n"
215
+
" .macro\tirq_enable_hazard \n"
216
+
" .endm \n"
217
+
" \n"
218
+
" .macro\tirq_disable_hazard \n"
219
+
" _ssnop \n"
220
+
" _ssnop \n"
221
+
" _ssnop \n"
222
+
" .endm \n");
224
223
225
224
#endif
226
225
226
+
#define irq_enable_hazard() \
227
+
__asm__ __volatile__("irq_enable_hazard")
228
+
#define irq_disable_hazard() \
229
+
__asm__ __volatile__("irq_disable_hazard")
230
+
231
+
232
+
/*
233
+
* Back-to-back hazards -
234
+
*
235
+
* What is needed to separate a move to cp0 from a subsequent read from the
236
+
* same cp0 register?
237
+
*/
238
+
#ifdef CONFIG_CPU_MIPSR2
239
+
240
+
__asm__(" .macro back_to_back_c0_hazard \n"
241
+
" _ehb \n"
242
+
" .endm \n");
243
+
244
+
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
245
+
defined(CONFIG_CPU_SB1)
246
+
247
+
__asm__(" .macro back_to_back_c0_hazard \n"
248
+
" .endm \n");
249
+
250
+
#else
251
+
252
+
__asm__(" .macro back_to_back_c0_hazard \n"
253
+
" .set noreorder \n"
254
+
" _ssnop \n"
255
+
" _ssnop \n"
256
+
" _ssnop \n"
257
+
" .set reorder \n"
258
+
" .endm");
259
+
260
+
#endif
261
+
262
+
#define back_to_back_c0_hazard() \
263
+
__asm__ __volatile__("back_to_back_c0_hazard")
264
+
265
+
266
+
/*
267
+
* Instruction execution hazard
268
+
*/
227
269
#ifdef CONFIG_CPU_MIPSR2
228
270
/*
229
271
* gcc has a tradition of misscompiling the previous construct using the
+15
-3
include/asm-mips/io.h
+15
-3
include/asm-mips/io.h
···
4
4
* for more details.
5
5
*
6
6
* Copyright (C) 1994, 1995 Waldorf GmbH
7
-
* Copyright (C) 1994 - 2000 Ralf Baechle
7
+
* Copyright (C) 1994 - 2000, 06 Ralf Baechle
8
8
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9
9
* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10
10
* Author: Maciej W. Rozycki <macro@mips.com>
···
103
103
*/
104
104
extern const unsigned long mips_io_port_base;
105
105
106
-
#define set_io_port_base(base) \
107
-
do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
106
+
/*
107
+
* Gcc will generate code to load the value of mips_io_port_base after each
108
+
* function call which may be fairly wasteful in some cases. So we don't
109
+
* play quite by the book. We tell gcc mips_io_port_base is a long variable
110
+
* which solves the code generation issue. Now we need to violate the
111
+
* aliasing rules a little to make initialization possible and finally we
112
+
* will need the barrier() to fight side effects of the aliasing chat.
113
+
* This trickery will eventually collapse under gcc's optimizer. Oh well.
114
+
*/
115
+
static inline void set_io_port_base(unsigned long base)
116
+
{
117
+
* (unsigned long *) &mips_io_port_base = base;
118
+
barrier();
119
+
}
108
120
109
121
/*
110
122
* Thanks to James van Artsdalen for a better timing-fix than
+2
-1
include/asm-mips/r4kcache.h
+2
-1
include/asm-mips/r4kcache.h
···
257
257
\
258
258
static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
259
259
{ \
260
-
unsigned long start = page; \
260
+
unsigned long indexmask = current_cpu_data.desc.waysize - 1; \
261
+
unsigned long start = INDEX_BASE + (page & indexmask); \
261
262
unsigned long end = start + PAGE_SIZE; \
262
263
unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
263
264
unsigned long ws_end = current_cpu_data.desc.ways << \
+1
-1
include/asm-mips/sibyte/sb1250.h
+1
-1
include/asm-mips/sibyte/sb1250.h
···
45
45
extern unsigned int periph_rev;
46
46
extern unsigned int zbbus_mhz;
47
47
48
+
extern void sb1250_hpt_setup(void);
48
49
extern void sb1250_time_init(void);
49
-
extern unsigned long sb1250_gettimeoffset(void);
50
50
extern void sb1250_mask_irq(int cpu, int irq);
51
51
extern void sb1250_unmask_irq(int cpu, int irq);
52
52
extern void sb1250_smp_finish(void);
+3
-2
include/asm-mips/sibyte/sb1250_scd.h
+3
-2
include/asm-mips/sibyte/sb1250_scd.h
···
359
359
*/
360
360
361
361
#define V_SCD_TIMER_FREQ 1000000
362
+
#define V_SCD_TIMER_WIDTH 23
362
363
363
364
#define S_SCD_TIMER_INIT 0
364
-
#define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT)
365
+
#define M_SCD_TIMER_INIT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_INIT)
365
366
#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
366
367
#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
367
368
368
369
#define S_SCD_TIMER_CNT 0
369
-
#define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT)
370
+
#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT)
370
371
#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
371
372
#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)
372
373