tjh.dev / kernel
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Merge tag 'drm-fixes-2018-08-31' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Regular fixes pull:

- Mediatek has a bunch of fixes to their RDMA and Overlay engines.

- i915 has some Cannonlake/Geminilake watermark workarounds, LSPCON
fix, HDCP free fix, audio fix and a ppgtt reference counting fix.

- amdgpu has some SRIOV, Kasan, memory leaks and other misc fixes"

* tag 'drm-fixes-2018-08-31' of git://anongit.freedesktop.org/drm/drm: (35 commits)
drm/i915/audio: Hook up component bindings even if displays are disabled
drm/i915: Increase LSPCON timeout
drm/i915: Stop holding a ref to the ppgtt from each vma
drm/i915: Free write_buf that we allocated with kzalloc.
drm/i915: Fix glk/cnl display w/a #1175
drm/amdgpu: Need to set moved to true when evict bo
drm/amdgpu: Remove duplicated power source update
drm/amd/display: Fix memory leak caused by missed dc_sink_release
drm/amdgpu: fix holding mn_lock while allocating memory
drm/amdgpu: Power on uvd block when hw_fini
drm/amdgpu: Update power state at the end of smu hw_init.
drm/amdgpu: Fix vce initialize failed on Kaveri/Mullins
drm/amdgpu: Enable/disable gfx PG feature in rlc safe mode
drm/amdgpu: Adjust the VM size based on system memory size v2
drm/mediatek: fix connection from RDMA2 to DSI1
drm/mediatek: update some variable name from ovl to comp
drm/mediatek: use layer_nr function to get layer number to init plane
drm/mediatek: add function to return RDMA layer number
drm/mediatek: add function to return OVL layer number
drm/mediatek: add function to get layer number for component
...

Linus Torvalds 4658aff6 217c3e01

+303 -161
+28 -19
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
··· 1012 1012 if (r) 1013 1013 return r; 1014 1014 1015 - if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) { 1016 - parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT; 1017 - if (!parser->ctx->preamble_presented) { 1018 - parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST; 1019 - parser->ctx->preamble_presented = true; 1020 - } 1021 - } 1015 + if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) 1016 + parser->job->preamble_status |= 1017 + AMDGPU_PREAMBLE_IB_PRESENT; 1022 1018 1023 1019 if (parser->ring && parser->ring != ring) 1024 1020 return -EINVAL; ··· 1203 1207 1204 1208 int r; 1205 1209 1210 + job = p->job; 1211 + p->job = NULL; 1212 + 1213 + r = drm_sched_job_init(&job->base, entity, p->filp); 1214 + if (r) 1215 + goto error_unlock; 1216 + 1217 + /* No memory allocation is allowed while holding the mn lock */ 1206 1218 amdgpu_mn_lock(p->mn); 1207 1219 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { 1208 1220 struct amdgpu_bo *bo = e->robj; 1209 1221 1210 1222 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { 1211 - amdgpu_mn_unlock(p->mn); 1212 - return -ERESTARTSYS; 1223 + r = -ERESTARTSYS; 1224 + goto error_abort; 1213 1225 } 1214 - } 1215 - 1216 - job = p->job; 1217 - p->job = NULL; 1218 - 1219 - r = drm_sched_job_init(&job->base, entity, p->filp); 1220 - if (r) { 1221 - amdgpu_job_free(job); 1222 - amdgpu_mn_unlock(p->mn); 1223 - return r; 1224 1226 } 1225 1227 1226 1228 job->owner = p->filp; ··· 1234 1240 } 1235 1241 1236 1242 amdgpu_cs_post_dependencies(p); 1243 + 1244 + if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) && 1245 + !p->ctx->preamble_presented) { 1246 + job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST; 1247 + p->ctx->preamble_presented = true; 1248 + } 1237 1249 1238 1250 cs->out.handle = seq; 1239 1251 job->uf_sequence = seq; ··· 1258 1258 amdgpu_mn_unlock(p->mn); 1259 1259 1260 1260 return 0; 1261 + 1262 + error_abort: 1263 + dma_fence_put(&job->base.s_fence->finished); 1264 + job->base.s_fence = NULL; 1265 + 1266 + error_unlock: 1267 + amdgpu_job_free(job); 1268 + amdgpu_mn_unlock(p->mn); 1269 + return r; 1261 1270 } 1262 1271 1263 1272 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+2 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
··· 164 164 return r; 165 165 } 166 166 167 + need_ctx_switch = ring->current_ctx != fence_ctx; 167 168 if (ring->funcs->emit_pipeline_sync && job && 168 169 ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) || 170 + (amdgpu_sriov_vf(adev) && need_ctx_switch) || 169 171 amdgpu_vm_need_pipeline_sync(ring, job))) { 170 172 need_pipe_sync = true; 171 173 dma_fence_put(tmp); ··· 198 196 } 199 197 200 198 skip_preamble = ring->current_ctx == fence_ctx; 201 - need_ctx_switch = ring->current_ctx != fence_ctx; 202 199 if (job && ring->funcs->emit_cntxcntl) { 203 200 if (need_ctx_switch) 204 201 status |= AMDGPU_HAVE_CTX_SWITCH;
-8
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
··· 1932 1932 amdgpu_fence_wait_empty(ring); 1933 1933 } 1934 1934 1935 - mutex_lock(&adev->pm.mutex); 1936 - /* update battery/ac status */ 1937 - if (power_supply_is_system_supplied() > 0) 1938 - adev->pm.ac_power = true; 1939 - else 1940 - adev->pm.ac_power = false; 1941 - mutex_unlock(&adev->pm.mutex); 1942 - 1943 1935 if (adev->powerplay.pp_funcs->dispatch_tasks) { 1944 1936 if (!amdgpu_device_has_dc_support(adev)) { 1945 1937 mutex_lock(&adev->pm.mutex);
+30 -5
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
··· 172 172 * is validated on next vm use to avoid fault. 173 173 * */ 174 174 list_move_tail(&base->vm_status, &vm->evicted); 175 + base->moved = true; 175 176 } 176 177 177 178 /** ··· 370 369 uint64_t addr; 371 370 int r; 372 371 373 - addr = amdgpu_bo_gpu_offset(bo); 374 372 entries = amdgpu_bo_size(bo) / 8; 375 373 376 374 if (pte_support_ats) { ··· 401 401 if (r) 402 402 goto error; 403 403 404 + addr = amdgpu_bo_gpu_offset(bo); 404 405 if (ats_entries) { 405 406 uint64_t ats_value; 406 407 ··· 2484 2483 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size 2485 2484 * 2486 2485 * @adev: amdgpu_device pointer 2487 - * @vm_size: the default vm size if it's set auto 2486 + * @min_vm_size: the minimum vm size in GB if it's set auto 2488 2487 * @fragment_size_default: Default PTE fragment size 2489 2488 * @max_level: max VMPT level 2490 2489 * @max_bits: max address space size in bits 2491 2490 * 2492 2491 */ 2493 - void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, 2492 + void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 2494 2493 uint32_t fragment_size_default, unsigned max_level, 2495 2494 unsigned max_bits) 2496 2495 { 2496 + unsigned int max_size = 1 << (max_bits - 30); 2497 + unsigned int vm_size; 2497 2498 uint64_t tmp; 2498 2499 2499 2500 /* adjust vm size first */ 2500 2501 if (amdgpu_vm_size != -1) { 2501 - unsigned max_size = 1 << (max_bits - 30); 2502 - 2503 2502 vm_size = amdgpu_vm_size; 2504 2503 if (vm_size > max_size) { 2505 2504 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", 2506 2505 amdgpu_vm_size, max_size); 2507 2506 vm_size = max_size; 2508 2507 } 2508 + } else { 2509 + struct sysinfo si; 2510 + unsigned int phys_ram_gb; 2511 + 2512 + /* Optimal VM size depends on the amount of physical 2513 + * RAM available. Underlying requirements and 2514 + * assumptions: 2515 + * 2516 + * - Need to map system memory and VRAM from all GPUs 2517 + * - VRAM from other GPUs not known here 2518 + * - Assume VRAM <= system memory 2519 + * - On GFX8 and older, VM space can be segmented for 2520 + * different MTYPEs 2521 + * - Need to allow room for fragmentation, guard pages etc. 2522 + * 2523 + * This adds up to a rough guess of system memory x3. 2524 + * Round up to power of two to maximize the available 2525 + * VM size with the given page table size. 2526 + */ 2527 + si_meminfo(&si); 2528 + phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit + 2529 + (1 << 30) - 1) >> 30; 2530 + vm_size = roundup_pow_of_two( 2531 + min(max(phys_ram_gb * 3, min_vm_size), max_size)); 2509 2532 } 2510 2533 2511 2534 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
··· 321 321 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 322 322 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 323 323 struct amdgpu_bo_va *bo_va); 324 - void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, 324 + void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 325 325 uint32_t fragment_size_default, unsigned max_level, 326 326 unsigned max_bits); 327 327 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+10 -1
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
··· 5664 5664 if (amdgpu_sriov_vf(adev)) 5665 5665 return 0; 5666 5666 5667 + if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG | 5668 + AMD_PG_SUPPORT_RLC_SMU_HS | 5669 + AMD_PG_SUPPORT_CP | 5670 + AMD_PG_SUPPORT_GFX_DMG)) 5671 + adev->gfx.rlc.funcs->enter_safe_mode(adev); 5667 5672 switch (adev->asic_type) { 5668 5673 case CHIP_CARRIZO: 5669 5674 case CHIP_STONEY: ··· 5718 5713 default: 5719 5714 break; 5720 5715 } 5721 - 5716 + if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG | 5717 + AMD_PG_SUPPORT_RLC_SMU_HS | 5718 + AMD_PG_SUPPORT_CP | 5719 + AMD_PG_SUPPORT_GFX_DMG)) 5720 + adev->gfx.rlc.funcs->exit_safe_mode(adev); 5722 5721 return 0; 5723 5722 } 5724 5723
+2 -7
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
··· 632 632 amdgpu_gart_table_vram_unpin(adev); 633 633 } 634 634 635 - static void gmc_v6_0_gart_fini(struct amdgpu_device *adev) 636 - { 637 - amdgpu_gart_table_vram_free(adev); 638 - amdgpu_gart_fini(adev); 639 - } 640 - 641 635 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, 642 636 u32 status, u32 addr, u32 mc_client) 643 637 { ··· 929 935 930 936 amdgpu_gem_force_release(adev); 931 937 amdgpu_vm_manager_fini(adev); 932 - gmc_v6_0_gart_fini(adev); 938 + amdgpu_gart_table_vram_free(adev); 933 939 amdgpu_bo_fini(adev); 940 + amdgpu_gart_fini(adev); 934 941 release_firmware(adev->gmc.fw); 935 942 adev->gmc.fw = NULL; 936 943
+2 -14
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
··· 747 747 } 748 748 749 749 /** 750 - * gmc_v7_0_gart_fini - vm fini callback 751 - * 752 - * @adev: amdgpu_device pointer 753 - * 754 - * Tears down the driver GART/VM setup (CIK). 755 - */ 756 - static void gmc_v7_0_gart_fini(struct amdgpu_device *adev) 757 - { 758 - amdgpu_gart_table_vram_free(adev); 759 - amdgpu_gart_fini(adev); 760 - } 761 - 762 - /** 763 750 * gmc_v7_0_vm_decode_fault - print human readable fault info 764 751 * 765 752 * @adev: amdgpu_device pointer ··· 1082 1095 amdgpu_gem_force_release(adev); 1083 1096 amdgpu_vm_manager_fini(adev); 1084 1097 kfree(adev->gmc.vm_fault_info); 1085 - gmc_v7_0_gart_fini(adev); 1098 + amdgpu_gart_table_vram_free(adev); 1086 1099 amdgpu_bo_fini(adev); 1100 + amdgpu_gart_fini(adev); 1087 1101 release_firmware(adev->gmc.fw); 1088 1102 adev->gmc.fw = NULL; 1089 1103
+2 -14
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
··· 969 969 } 970 970 971 971 /** 972 - * gmc_v8_0_gart_fini - vm fini callback 973 - * 974 - * @adev: amdgpu_device pointer 975 - * 976 - * Tears down the driver GART/VM setup (CIK). 977 - */ 978 - static void gmc_v8_0_gart_fini(struct amdgpu_device *adev) 979 - { 980 - amdgpu_gart_table_vram_free(adev); 981 - amdgpu_gart_fini(adev); 982 - } 983 - 984 - /** 985 972 * gmc_v8_0_vm_decode_fault - print human readable fault info 986 973 * 987 974 * @adev: amdgpu_device pointer ··· 1186 1199 amdgpu_gem_force_release(adev); 1187 1200 amdgpu_vm_manager_fini(adev); 1188 1201 kfree(adev->gmc.vm_fault_info); 1189 - gmc_v8_0_gart_fini(adev); 1202 + amdgpu_gart_table_vram_free(adev); 1190 1203 amdgpu_bo_fini(adev); 1204 + amdgpu_gart_fini(adev); 1191 1205 release_firmware(adev->gmc.fw); 1192 1206 adev->gmc.fw = NULL; 1193 1207
+2 -14
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
··· 942 942 return 0; 943 943 } 944 944 945 - /** 946 - * gmc_v9_0_gart_fini - vm fini callback 947 - * 948 - * @adev: amdgpu_device pointer 949 - * 950 - * Tears down the driver GART/VM setup (CIK). 951 - */ 952 - static void gmc_v9_0_gart_fini(struct amdgpu_device *adev) 953 - { 954 - amdgpu_gart_table_vram_free(adev); 955 - amdgpu_gart_fini(adev); 956 - } 957 - 958 945 static int gmc_v9_0_sw_fini(void *handle) 959 946 { 960 947 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 961 948 962 949 amdgpu_gem_force_release(adev); 963 950 amdgpu_vm_manager_fini(adev); 964 - gmc_v9_0_gart_fini(adev); 965 951 966 952 /* 967 953 * TODO: ··· 960 974 */ 961 975 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); 962 976 977 + amdgpu_gart_table_vram_free(adev); 963 978 amdgpu_bo_fini(adev); 979 + amdgpu_gart_fini(adev); 964 980 965 981 return 0; 966 982 }
+29 -20
drivers/gpu/drm/amd/amdgpu/kv_dpm.c
··· 65 65 int min_temp, int max_temp); 66 66 static int kv_init_fps_limits(struct amdgpu_device *adev); 67 67 68 - static void kv_dpm_powergate_uvd(void *handle, bool gate); 69 - static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate); 70 68 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate); 71 69 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate); 72 70 ··· 1352 1354 return ret; 1353 1355 } 1354 1356 1355 - kv_update_current_ps(adev, adev->pm.dpm.boot_ps); 1356 - 1357 1357 if (adev->irq.installed && 1358 1358 amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) { 1359 1359 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX); ··· 1370 1374 1371 1375 static void kv_dpm_disable(struct amdgpu_device *adev) 1372 1376 { 1377 + struct kv_power_info *pi = kv_get_pi(adev); 1378 + 1373 1379 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, 1374 1380 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH); 1375 1381 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, ··· 1385 1387 /* powerup blocks */ 1386 1388 kv_dpm_powergate_acp(adev, false); 1387 1389 kv_dpm_powergate_samu(adev, false); 1388 - kv_dpm_powergate_vce(adev, false); 1389 - kv_dpm_powergate_uvd(adev, false); 1390 + if (pi->caps_vce_pg) /* power on the VCE block */ 1391 + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); 1392 + if (pi->caps_uvd_pg) /* power on the UVD block */ 1393 + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); 1390 1394 1391 1395 kv_enable_smc_cac(adev, false); 1392 1396 kv_enable_didt(adev, false); ··· 1551 1551 int ret; 1552 1552 1553 1553 if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) { 1554 - kv_dpm_powergate_vce(adev, false); 1555 1554 if (pi->caps_stable_p_state) 1556 1555 pi->vce_boot_level = table->count - 1; 1557 1556 else ··· 1572 1573 kv_enable_vce_dpm(adev, true); 1573 1574 } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) { 1574 1575 kv_enable_vce_dpm(adev, false); 1575 - kv_dpm_powergate_vce(adev, true); 1576 1576 } 1577 1577 1578 1578 return 0; ··· 1700 1702 } 1701 1703 } 1702 1704 1703 - static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate) 1705 + static void kv_dpm_powergate_vce(void *handle, bool gate) 1704 1706 { 1707 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1705 1708 struct kv_power_info *pi = kv_get_pi(adev); 1706 - 1707 - if (pi->vce_power_gated == gate) 1708 - return; 1709 + int ret; 1709 1710 1710 1711 pi->vce_power_gated = gate; 1711 1712 1712 - if (!pi->caps_vce_pg) 1713 - return; 1714 - 1715 - if (gate) 1716 - amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF); 1717 - else 1718 - amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); 1713 + if (gate) { 1714 + /* stop the VCE block */ 1715 + ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1716 + AMD_PG_STATE_GATE); 1717 + kv_enable_vce_dpm(adev, false); 1718 + if (pi->caps_vce_pg) /* power off the VCE block */ 1719 + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF); 1720 + } else { 1721 + if (pi->caps_vce_pg) /* power on the VCE block */ 1722 + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); 1723 + kv_enable_vce_dpm(adev, true); 1724 + /* re-init the VCE block */ 1725 + ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1726 + AMD_PG_STATE_UNGATE); 1727 + } 1719 1728 } 1729 + 1720 1730 1721 1731 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate) 1722 1732 { ··· 3067 3061 else 3068 3062 adev->pm.dpm_enabled = true; 3069 3063 mutex_unlock(&adev->pm.mutex); 3070 - 3064 + amdgpu_pm_compute_clocks(adev); 3071 3065 return ret; 3072 3066 } 3073 3067 ··· 3318 3312 switch (block_type) { 3319 3313 case AMD_IP_BLOCK_TYPE_UVD: 3320 3314 kv_dpm_powergate_uvd(handle, gate); 3315 + break; 3316 + case AMD_IP_BLOCK_TYPE_VCE: 3317 + kv_dpm_powergate_vce(handle, gate); 3321 3318 break; 3322 3319 default: 3323 3320 break;
+1 -2
drivers/gpu/drm/amd/amdgpu/si_dpm.c
··· 6887 6887 6888 6888 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6889 6889 si_thermal_start_thermal_controller(adev); 6890 - ni_update_current_ps(adev, boot_ps); 6891 6890 6892 6891 return 0; 6893 6892 } ··· 7762 7763 else 7763 7764 adev->pm.dpm_enabled = true; 7764 7765 mutex_unlock(&adev->pm.mutex); 7765 - 7766 + amdgpu_pm_compute_clocks(adev); 7766 7767 return ret; 7767 7768 } 7768 7769
+10 -2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
··· 480 480 { 481 481 struct dc_context *ctx = pp->ctx; 482 482 struct amdgpu_device *adev = ctx->driver_context; 483 + void *pp_handle = adev->powerplay.pp_handle; 483 484 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 485 + struct pp_display_clock_request clock = {0}; 484 486 485 - if (!pp_funcs || !pp_funcs->display_configuration_changed) 487 + if (!pp_funcs || !pp_funcs->display_clock_voltage_request) 486 488 return; 487 489 488 - amdgpu_dpm_display_configuration_changed(adev); 490 + clock.clock_type = amd_pp_dcf_clock; 491 + clock.clock_freq_in_khz = req->hard_min_dcefclk_khz; 492 + pp_funcs->display_clock_voltage_request(pp_handle, &clock); 493 + 494 + clock.clock_type = amd_pp_f_clock; 495 + clock.clock_freq_in_khz = req->hard_min_fclk_khz; 496 + pp_funcs->display_clock_voltage_request(pp_handle, &clock); 489 497 } 490 498 491 499 void pp_rv_set_wm_ranges(struct pp_smu *pp,
+5 -1
drivers/gpu/drm/amd/display/dc/core/dc_link.c
··· 754 754 * fail-safe mode 755 755 */ 756 756 if (dc_is_hdmi_signal(link->connector_signal) || 757 - dc_is_dvi_signal(link->connector_signal)) 757 + dc_is_dvi_signal(link->connector_signal)) { 758 + if (prev_sink != NULL) 759 + dc_sink_release(prev_sink); 760 + 758 761 return false; 762 + } 759 763 default: 760 764 break; 761 765 }
-4
drivers/gpu/drm/i915/i915_vma.c
··· 199 199 vma->flags |= I915_VMA_GGTT; 200 200 list_add(&vma->obj_link, &obj->vma_list); 201 201 } else { 202 - i915_ppgtt_get(i915_vm_to_ppgtt(vm)); 203 202 list_add_tail(&vma->obj_link, &obj->vma_list); 204 203 } 205 204 ··· 805 806 list_del(&vma->vm_link); 806 807 if (vma->obj) 807 808 rb_erase(&vma->obj_node, &vma->obj->vma_tree); 808 - 809 - if (!i915_vma_is_ggtt(vma)) 810 - i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); 811 809 812 810 rbtree_postorder_for_each_entry_safe(iter, n, &vma->active, node) { 813 811 GEM_BUG_ON(i915_gem_active_isset(&iter->base));
-3
drivers/gpu/drm/i915/intel_audio.c
··· 962 962 { 963 963 int ret; 964 964 965 - if (INTEL_INFO(dev_priv)->num_pipes == 0) 966 - return; 967 - 968 965 ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops); 969 966 if (ret < 0) { 970 967 DRM_ERROR("failed to add audio component (%d)\n", ret);
+4 -3
drivers/gpu/drm/i915/intel_display.c
··· 2988 2988 int w = drm_rect_width(&plane_state->base.src) >> 16; 2989 2989 int h = drm_rect_height(&plane_state->base.src) >> 16; 2990 2990 int dst_x = plane_state->base.dst.x1; 2991 + int dst_w = drm_rect_width(&plane_state->base.dst); 2991 2992 int pipe_src_w = crtc_state->pipe_src_w; 2992 2993 int max_width = skl_max_plane_width(fb, 0, rotation); 2993 2994 int max_height = 4096; ··· 3010 3009 * screen may cause FIFO underflow and display corruption. 3011 3010 */ 3012 3011 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && 3013 - (dst_x + w < 4 || dst_x > pipe_src_w - 4)) { 3012 + (dst_x + dst_w < 4 || dst_x > pipe_src_w - 4)) { 3014 3013 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n", 3015 - dst_x + w < 4 ? "end" : "start", 3016 - dst_x + w < 4 ? dst_x + w : dst_x, 3014 + dst_x + dst_w < 4 ? "end" : "start", 3015 + dst_x + dst_w < 4 ? dst_x + dst_w : dst_x, 3017 3016 4, pipe_src_w - 4); 3018 3017 return -ERANGE; 3019 3018 }
+6 -2
drivers/gpu/drm/i915/intel_hdmi.c
··· 943 943 944 944 ret = i2c_transfer(adapter, &msg, 1); 945 945 if (ret == 1) 946 - return 0; 947 - return ret >= 0 ? -EIO : ret; 946 + ret = 0; 947 + else if (ret >= 0) 948 + ret = -EIO; 949 + 950 + kfree(write_buf); 951 + return ret; 948 952 } 949 953 950 954 static
+1 -1
drivers/gpu/drm/i915/intel_lspcon.c
··· 74 74 DRM_DEBUG_KMS("Waiting for LSPCON mode %s to settle\n", 75 75 lspcon_mode_name(mode)); 76 76 77 - wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 100); 77 + wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400); 78 78 if (current_mode != mode) 79 79 DRM_ERROR("LSPCON mode hasn't settled\n"); 80 80
+11
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
··· 132 132 writel(0x0, comp->regs + DISP_REG_OVL_RST); 133 133 } 134 134 135 + static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp) 136 + { 137 + return 4; 138 + } 139 + 135 140 static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) 136 141 { 137 142 unsigned int reg; ··· 162 157 163 158 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) 164 159 { 160 + /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" 161 + * is defined in mediatek HW data sheet. 162 + * The alphabet order in XXX is no relation to data 163 + * arrangement in memory. 164 + */ 165 165 switch (fmt) { 166 166 default: 167 167 case DRM_FORMAT_RGB565: ··· 231 221 .stop = mtk_ovl_stop, 232 222 .enable_vblank = mtk_ovl_enable_vblank, 233 223 .disable_vblank = mtk_ovl_disable_vblank, 224 + .layer_nr = mtk_ovl_layer_nr, 234 225 .layer_on = mtk_ovl_layer_on, 235 226 .layer_off = mtk_ovl_layer_off, 236 227 .layer_config = mtk_ovl_layer_config,
+92
drivers/gpu/drm/mediatek/mtk_disp_rdma.c
··· 31 31 #define RDMA_REG_UPDATE_INT BIT(0) 32 32 #define DISP_REG_RDMA_GLOBAL_CON 0x0010 33 33 #define RDMA_ENGINE_EN BIT(0) 34 + #define RDMA_MODE_MEMORY BIT(1) 34 35 #define DISP_REG_RDMA_SIZE_CON_0 0x0014 36 + #define RDMA_MATRIX_ENABLE BIT(17) 37 + #define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20) 38 + #define RDMA_MATRIX_INT_MTX_BT601_to_RGB (6 << 20) 35 39 #define DISP_REG_RDMA_SIZE_CON_1 0x0018 36 40 #define DISP_REG_RDMA_TARGET_LINE 0x001c 41 + #define DISP_RDMA_MEM_CON 0x0024 42 + #define MEM_MODE_INPUT_FORMAT_RGB565 (0x000 << 4) 43 + #define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4) 44 + #define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4) 45 + #define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4) 46 + #define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4) 47 + #define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4) 48 + #define MEM_MODE_INPUT_SWAP BIT(8) 49 + #define DISP_RDMA_MEM_SRC_PITCH 0x002c 50 + #define DISP_RDMA_MEM_GMC_SETTING_0 0x0030 37 51 #define DISP_REG_RDMA_FIFO_CON 0x0040 38 52 #define RDMA_FIFO_UNDERFLOW_EN BIT(31) 39 53 #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) 40 54 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) 41 55 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size) 56 + #define DISP_RDMA_MEM_START_ADDR 0x0f00 57 + 58 + #define RDMA_MEM_GMC 0x40402020 42 59 43 60 struct mtk_disp_rdma_data { 44 61 unsigned int fifo_size; ··· 155 138 writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); 156 139 } 157 140 141 + static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, 142 + unsigned int fmt) 143 + { 144 + /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" 145 + * is defined in mediatek HW data sheet. 146 + * The alphabet order in XXX is no relation to data 147 + * arrangement in memory. 148 + */ 149 + switch (fmt) { 150 + default: 151 + case DRM_FORMAT_RGB565: 152 + return MEM_MODE_INPUT_FORMAT_RGB565; 153 + case DRM_FORMAT_BGR565: 154 + return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP; 155 + case DRM_FORMAT_RGB888: 156 + return MEM_MODE_INPUT_FORMAT_RGB888; 157 + case DRM_FORMAT_BGR888: 158 + return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP; 159 + case DRM_FORMAT_RGBX8888: 160 + case DRM_FORMAT_RGBA8888: 161 + return MEM_MODE_INPUT_FORMAT_ARGB8888; 162 + case DRM_FORMAT_BGRX8888: 163 + case DRM_FORMAT_BGRA8888: 164 + return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP; 165 + case DRM_FORMAT_XRGB8888: 166 + case DRM_FORMAT_ARGB8888: 167 + return MEM_MODE_INPUT_FORMAT_RGBA8888; 168 + case DRM_FORMAT_XBGR8888: 169 + case DRM_FORMAT_ABGR8888: 170 + return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP; 171 + case DRM_FORMAT_UYVY: 172 + return MEM_MODE_INPUT_FORMAT_UYVY; 173 + case DRM_FORMAT_YUYV: 174 + return MEM_MODE_INPUT_FORMAT_YUYV; 175 + } 176 + } 177 + 178 + static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp) 179 + { 180 + return 1; 181 + } 182 + 183 + static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, 184 + struct mtk_plane_state *state) 185 + { 186 + struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 187 + struct mtk_plane_pending_state *pending = &state->pending; 188 + unsigned int addr = pending->addr; 189 + unsigned int pitch = pending->pitch & 0xffff; 190 + unsigned int fmt = pending->format; 191 + unsigned int con; 192 + 193 + con = rdma_fmt_convert(rdma, fmt); 194 + writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON); 195 + 196 + if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) { 197 + rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 198 + RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE); 199 + rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 200 + RDMA_MATRIX_INT_MTX_SEL, 201 + RDMA_MATRIX_INT_MTX_BT601_to_RGB); 202 + } else { 203 + rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 204 + RDMA_MATRIX_ENABLE, 0); 205 + } 206 + 207 + writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR); 208 + writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH); 209 + writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0); 210 + rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, 211 + RDMA_MODE_MEMORY, RDMA_MODE_MEMORY); 212 + } 213 + 158 214 static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = { 159 215 .config = mtk_rdma_config, 160 216 .start = mtk_rdma_start, 161 217 .stop = mtk_rdma_stop, 162 218 .enable_vblank = mtk_rdma_enable_vblank, 163 219 .disable_vblank = mtk_rdma_disable_vblank, 220 + .layer_nr = mtk_rdma_layer_nr, 221 + .layer_config = mtk_rdma_layer_config, 164 222 }; 165 223 166 224 static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
+27 -20
drivers/gpu/drm/mediatek/mtk_drm_crtc.c
··· 45 45 bool pending_needs_vblank; 46 46 struct drm_pending_vblank_event *event; 47 47 48 - struct drm_plane planes[OVL_LAYER_NR]; 48 + struct drm_plane *planes; 49 + unsigned int layer_nr; 49 50 bool pending_planes; 50 51 51 52 void __iomem *config_regs; ··· 172 171 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 173 172 { 174 173 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 175 - struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; 174 + struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 176 175 177 - mtk_ddp_comp_enable_vblank(ovl, &mtk_crtc->base); 176 + mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); 178 177 179 178 return 0; 180 179 } ··· 182 181 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 183 182 { 184 183 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 185 - struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; 184 + struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 186 185 187 - mtk_ddp_comp_disable_vblank(ovl); 186 + mtk_ddp_comp_disable_vblank(comp); 188 187 } 189 188 190 189 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) ··· 287 286 } 288 287 289 288 /* Initially configure all planes */ 290 - for (i = 0; i < OVL_LAYER_NR; i++) { 289 + for (i = 0; i < mtk_crtc->layer_nr; i++) { 291 290 struct drm_plane *plane = &mtk_crtc->planes[i]; 292 291 struct mtk_plane_state *plane_state; 293 292 ··· 335 334 { 336 335 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 337 336 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 338 - struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; 337 + struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 339 338 unsigned int i; 340 339 341 340 /* ··· 344 343 * queue update module registers on vblank. 345 344 */ 346 345 if (state->pending_config) { 347 - mtk_ddp_comp_config(ovl, state->pending_width, 346 + mtk_ddp_comp_config(comp, state->pending_width, 348 347 state->pending_height, 349 348 state->pending_vrefresh, 0); 350 349 ··· 352 351 } 353 352 354 353 if (mtk_crtc->pending_planes) { 355 - for (i = 0; i < OVL_LAYER_NR; i++) { 354 + for (i = 0; i < mtk_crtc->layer_nr; i++) { 356 355 struct drm_plane *plane = &mtk_crtc->planes[i]; 357 356 struct mtk_plane_state *plane_state; 358 357 359 358 plane_state = to_mtk_plane_state(plane->state); 360 359 361 360 if (plane_state->pending.config) { 362 - mtk_ddp_comp_layer_config(ovl, i, plane_state); 361 + mtk_ddp_comp_layer_config(comp, i, plane_state); 363 362 plane_state->pending.config = false; 364 363 } 365 364 } ··· 371 370 struct drm_crtc_state *old_state) 372 371 { 373 372 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 374 - struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; 373 + struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 375 374 int ret; 376 375 377 376 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 378 377 379 - ret = mtk_smi_larb_get(ovl->larb_dev); 378 + ret = mtk_smi_larb_get(comp->larb_dev); 380 379 if (ret) { 381 380 DRM_ERROR("Failed to get larb: %d\n", ret); 382 381 return; ··· 384 383 385 384 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 386 385 if (ret) { 387 - mtk_smi_larb_put(ovl->larb_dev); 386 + mtk_smi_larb_put(comp->larb_dev); 388 387 return; 389 388 } 390 389 ··· 396 395 struct drm_crtc_state *old_state) 397 396 { 398 397 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 399 - struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; 398 + struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 400 399 int i; 401 400 402 401 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); ··· 404 403 return; 405 404 406 405 /* Set all pending plane state to disabled */ 407 - for (i = 0; i < OVL_LAYER_NR; i++) { 406 + for (i = 0; i < mtk_crtc->layer_nr; i++) { 408 407 struct drm_plane *plane = &mtk_crtc->planes[i]; 409 408 struct mtk_plane_state *plane_state; 410 409 ··· 419 418 420 419 drm_crtc_vblank_off(crtc); 421 420 mtk_crtc_ddp_hw_fini(mtk_crtc); 422 - mtk_smi_larb_put(ovl->larb_dev); 421 + mtk_smi_larb_put(comp->larb_dev); 423 422 424 423 mtk_crtc->enabled = false; 425 424 } ··· 451 450 452 451 if (mtk_crtc->event) 453 452 mtk_crtc->pending_needs_vblank = true; 454 - for (i = 0; i < OVL_LAYER_NR; i++) { 453 + for (i = 0; i < mtk_crtc->layer_nr; i++) { 455 454 struct drm_plane *plane = &mtk_crtc->planes[i]; 456 455 struct mtk_plane_state *plane_state; 457 456 ··· 517 516 return ret; 518 517 } 519 518 520 - void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl) 519 + void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 521 520 { 522 521 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 523 522 struct mtk_drm_private *priv = crtc->dev->dev_private; ··· 599 598 mtk_crtc->ddp_comp[i] = comp; 600 599 } 601 600 602 - for (zpos = 0; zpos < OVL_LAYER_NR; zpos++) { 601 + mtk_crtc->layer_nr = mtk_ddp_comp_layer_nr(mtk_crtc->ddp_comp[0]); 602 + mtk_crtc->planes = devm_kzalloc(dev, mtk_crtc->layer_nr * 603 + sizeof(struct drm_plane), 604 + GFP_KERNEL); 605 + 606 + for (zpos = 0; zpos < mtk_crtc->layer_nr; zpos++) { 603 607 type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY : 604 608 (zpos == 1) ? DRM_PLANE_TYPE_CURSOR : 605 609 DRM_PLANE_TYPE_OVERLAY; ··· 615 609 } 616 610 617 611 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0], 618 - &mtk_crtc->planes[1], pipe); 612 + mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] : 613 + NULL, pipe); 619 614 if (ret < 0) 620 615 goto unprepare; 621 616 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
+1 -2
drivers/gpu/drm/mediatek/mtk_drm_crtc.h
··· 18 18 #include "mtk_drm_ddp_comp.h" 19 19 #include "mtk_drm_plane.h" 20 20 21 - #define OVL_LAYER_NR 4 22 21 #define MTK_LUT_SIZE 512 23 22 #define MTK_MAX_BPC 10 24 23 #define MTK_MIN_BPC 3 25 24 26 25 void mtk_drm_crtc_commit(struct drm_crtc *crtc); 27 - void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl); 26 + void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp); 28 27 int mtk_drm_crtc_create(struct drm_device *drm_dev, 29 28 const enum mtk_ddp_comp_id *path, 30 29 unsigned int path_len);
+17 -1
drivers/gpu/drm/mediatek/mtk_drm_ddp.c
··· 106 106 #define OVL1_MOUT_EN_COLOR1 0x1 107 107 #define GAMMA_MOUT_EN_RDMA1 0x1 108 108 #define RDMA0_SOUT_DPI0 0x2 109 + #define RDMA0_SOUT_DPI1 0x3 110 + #define RDMA0_SOUT_DSI1 0x1 109 111 #define RDMA0_SOUT_DSI2 0x4 110 112 #define RDMA0_SOUT_DSI3 0x5 111 113 #define RDMA1_SOUT_DPI0 0x2 ··· 124 122 #define DPI0_SEL_IN_RDMA2 0x3 125 123 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) 126 124 #define DPI1_SEL_IN_RDMA2 (0x3 << 8) 125 + #define DSI0_SEL_IN_RDMA1 0x1 126 + #define DSI0_SEL_IN_RDMA2 0x4 127 127 #define DSI1_SEL_IN_RDMA1 0x1 128 128 #define DSI1_SEL_IN_RDMA2 0x4 129 129 #define DSI2_SEL_IN_RDMA1 (0x1 << 16) ··· 228 224 } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { 229 225 *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; 230 226 value = RDMA0_SOUT_DPI0; 227 + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { 228 + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; 229 + value = RDMA0_SOUT_DPI1; 230 + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { 231 + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; 232 + value = RDMA0_SOUT_DSI1; 231 233 } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { 232 234 *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; 233 235 value = RDMA0_SOUT_DSI2; ··· 292 282 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { 293 283 *addr = DISP_REG_CONFIG_DPI_SEL_IN; 294 284 value = DPI1_SEL_IN_RDMA1; 285 + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { 286 + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; 287 + value = DSI0_SEL_IN_RDMA1; 295 288 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { 296 289 *addr = DISP_REG_CONFIG_DSIO_SEL_IN; 297 290 value = DSI1_SEL_IN_RDMA1; ··· 310 297 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { 311 298 *addr = DISP_REG_CONFIG_DPI_SEL_IN; 312 299 value = DPI1_SEL_IN_RDMA2; 313 - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { 300 + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { 314 301 *addr = DISP_REG_CONFIG_DSIE_SEL_IN; 302 + value = DSI0_SEL_IN_RDMA2; 303 + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { 304 + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; 315 305 value = DSI1_SEL_IN_RDMA2; 316 306 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { 317 307 *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+9
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
··· 78 78 void (*stop)(struct mtk_ddp_comp *comp); 79 79 void (*enable_vblank)(struct mtk_ddp_comp *comp, struct drm_crtc *crtc); 80 80 void (*disable_vblank)(struct mtk_ddp_comp *comp); 81 + unsigned int (*layer_nr)(struct mtk_ddp_comp *comp); 81 82 void (*layer_on)(struct mtk_ddp_comp *comp, unsigned int idx); 82 83 void (*layer_off)(struct mtk_ddp_comp *comp, unsigned int idx); 83 84 void (*layer_config)(struct mtk_ddp_comp *comp, unsigned int idx, ··· 127 126 { 128 127 if (comp->funcs && comp->funcs->disable_vblank) 129 128 comp->funcs->disable_vblank(comp); 129 + } 130 + 131 + static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp) 132 + { 133 + if (comp->funcs && comp->funcs->layer_nr) 134 + return comp->funcs->layer_nr(comp); 135 + 136 + return 0; 130 137 } 131 138 132 139 static inline void mtk_ddp_comp_layer_on(struct mtk_ddp_comp *comp,
+11 -16
drivers/gpu/drm/mediatek/mtk_drm_drv.c
··· 381 381 err_deinit: 382 382 mtk_drm_kms_deinit(drm); 383 383 err_free: 384 - drm_dev_unref(drm); 384 + drm_dev_put(drm); 385 385 return ret; 386 386 } 387 387 ··· 390 390 struct mtk_drm_private *private = dev_get_drvdata(dev); 391 391 392 392 drm_dev_unregister(private->drm); 393 - drm_dev_unref(private->drm); 393 + drm_dev_put(private->drm); 394 394 private->drm = NULL; 395 395 } 396 396 ··· 564 564 565 565 drm_dev_unregister(drm); 566 566 mtk_drm_kms_deinit(drm); 567 - drm_dev_unref(drm); 567 + drm_dev_put(drm); 568 568 569 569 component_master_del(&pdev->dev, &mtk_drm_ops); 570 570 pm_runtime_disable(&pdev->dev); ··· 580 580 { 581 581 struct mtk_drm_private *private = dev_get_drvdata(dev); 582 582 struct drm_device *drm = private->drm; 583 + int ret; 583 584 584 - drm_kms_helper_poll_disable(drm); 585 - 586 - private->suspend_state = drm_atomic_helper_suspend(drm); 587 - if (IS_ERR(private->suspend_state)) { 588 - drm_kms_helper_poll_enable(drm); 589 - return PTR_ERR(private->suspend_state); 590 - } 591 - 585 + ret = drm_mode_config_helper_suspend(drm); 592 586 DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n"); 593 - return 0; 587 + 588 + return ret; 594 589 } 595 590 596 591 static int mtk_drm_sys_resume(struct device *dev) 597 592 { 598 593 struct mtk_drm_private *private = dev_get_drvdata(dev); 599 594 struct drm_device *drm = private->drm; 595 + int ret; 600 596 601 - drm_atomic_helper_resume(drm, private->suspend_state); 602 - drm_kms_helper_poll_enable(drm); 603 - 597 + ret = drm_mode_config_helper_resume(drm); 604 598 DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n"); 605 - return 0; 599 + 600 + return ret; 606 601 } 607 602 #endif 608 603