tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/panel: himax-hx8394: transition to mipi_dsi wrapped functions

Changes the himax-hx8394 panel to use multi style functions for
improved error handling.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Tejas Vipin <tejasvipin76@gmail.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20250325094707.961349-1-tejasvipin76@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Tejas Vipin and committed by
Dmitry Baryshkov 4658f363 20e82192

+210 -231
+210 -231
drivers/gpu/drm/panel/panel-himax-hx8394.c
··· 80 80 unsigned int lanes; 81 81 unsigned long mode_flags; 82 82 enum mipi_dsi_pixel_format format; 83 - int (*init_sequence)(struct hx8394 *ctx); 83 + void (*init_sequence)(struct mipi_dsi_multi_context *dsi_ctx); 84 84 }; 85 85 86 86 static inline struct hx8394 *panel_to_hx8394(struct drm_panel *panel) ··· 88 88 return container_of(panel, struct hx8394, panel); 89 89 } 90 90 91 - static int hsd060bhw4_init_sequence(struct hx8394 *ctx) 91 + static void hsd060bhw4_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) 92 92 { 93 - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 94 - 95 93 /* 5.19.8 SETEXTC: Set extension command (B9h) */ 96 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC, 97 - 0xff, 0x83, 0x94); 94 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC, 95 + 0xff, 0x83, 0x94); 98 96 99 97 /* 5.19.2 SETPOWER: Set power (B1h) */ 100 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, 101 - 0x48, 0x11, 0x71, 0x09, 0x32, 0x24, 0x71, 0x31, 0x55, 0x30); 98 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER, 99 + 0x48, 0x11, 0x71, 0x09, 0x32, 0x24, 0x71, 0x31, 0x55, 0x30); 102 100 103 101 /* 5.19.9 SETMIPI: Set MIPI control (BAh) */ 104 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI, 105 - 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0); 102 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETMIPI, 103 + 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0); 106 104 107 105 /* 5.19.3 SETDISP: Set display related register (B2h) */ 108 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP, 109 - 0x00, 0x80, 0x78, 0x0c, 0x07); 106 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP, 107 + 0x00, 0x80, 0x78, 0x0c, 0x07); 110 108 111 109 /* 5.19.4 SETCYC: Set display waveform cycles (B4h) */ 112 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC, 113 - 0x12, 0x63, 0x12, 0x63, 0x12, 0x63, 0x01, 0x0c, 0x7c, 0x55, 114 - 0x00, 0x3f, 0x12, 0x6b, 0x12, 0x6b, 0x12, 0x6b, 0x01, 0x0c, 115 - 0x7c); 110 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC, 111 + 0x12, 0x63, 0x12, 0x63, 0x12, 0x63, 0x01, 0x0c, 0x7c, 0x55, 112 + 0x00, 0x3f, 0x12, 0x6b, 0x12, 0x6b, 0x12, 0x6b, 0x01, 0x0c, 113 + 0x7c); 116 114 117 115 /* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */ 118 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0, 119 - 0x00, 0x00, 0x00, 0x00, 0x3c, 0x1c, 0x00, 0x00, 0x32, 0x10, 120 - 0x09, 0x00, 0x09, 0x32, 0x15, 0xad, 0x05, 0xad, 0x32, 0x00, 121 - 0x00, 0x00, 0x00, 0x37, 0x03, 0x0b, 0x0b, 0x37, 0x00, 0x00, 122 - 0x00, 0x0c, 0x40); 116 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0, 117 + 0x00, 0x00, 0x00, 0x00, 0x3c, 0x1c, 0x00, 0x00, 0x32, 0x10, 118 + 0x09, 0x00, 0x09, 0x32, 0x15, 0xad, 0x05, 0xad, 0x32, 0x00, 119 + 0x00, 0x00, 0x00, 0x37, 0x03, 0x0b, 0x0b, 0x37, 0x00, 0x00, 120 + 0x00, 0x0c, 0x40); 123 121 124 122 /* 5.19.20 Set GIP Option1 (D5h) */ 125 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1, 126 - 0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b, 0x1a, 0x1a, 0x00, 0x01, 127 - 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 0x18, 0x18, 128 - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 129 - 0x24, 0x25, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 130 - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18); 123 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1, 124 + 0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b, 0x1a, 0x1a, 0x00, 0x01, 125 + 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 0x18, 0x18, 126 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 127 + 0x24, 0x25, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 128 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18); 131 129 132 130 /* 5.19.21 Set GIP Option2 (D6h) */ 133 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2, 134 - 0x18, 0x18, 0x19, 0x19, 0x1b, 0x1b, 0x1a, 0x1a, 0x07, 0x06, 135 - 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x25, 0x24, 0x18, 0x18, 136 - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 137 - 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 138 - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18); 131 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2, 132 + 0x18, 0x18, 0x19, 0x19, 0x1b, 0x1b, 0x1a, 0x1a, 0x07, 0x06, 133 + 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x25, 0x24, 0x18, 0x18, 134 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 135 + 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 136 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18); 139 137 140 138 /* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */ 141 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA, 142 - 0x00, 0x04, 0x0c, 0x12, 0x14, 0x18, 0x1a, 0x18, 0x31, 0x3f, 143 - 0x4d, 0x4c, 0x54, 0x65, 0x6b, 0x70, 0x7f, 0x82, 0x7e, 0x8a, 144 - 0x99, 0x4a, 0x48, 0x49, 0x4b, 0x4a, 0x4c, 0x4b, 0x7f, 0x00, 145 - 0x04, 0x0c, 0x11, 0x13, 0x17, 0x1a, 0x18, 0x31, 146 - 0x3f, 0x4d, 0x4c, 0x54, 0x65, 0x6b, 0x70, 0x7f, 147 - 0x82, 0x7e, 0x8a, 0x99, 0x4a, 0x48, 0x49, 0x4b, 148 - 0x4a, 0x4c, 0x4b, 0x7f); 139 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGAMMA, 140 + 0x00, 0x04, 0x0c, 0x12, 0x14, 0x18, 0x1a, 0x18, 0x31, 0x3f, 141 + 0x4d, 0x4c, 0x54, 0x65, 0x6b, 0x70, 0x7f, 0x82, 0x7e, 0x8a, 142 + 0x99, 0x4a, 0x48, 0x49, 0x4b, 0x4a, 0x4c, 0x4b, 0x7f, 0x00, 143 + 0x04, 0x0c, 0x11, 0x13, 0x17, 0x1a, 0x18, 0x31, 144 + 0x3f, 0x4d, 0x4c, 0x54, 0x65, 0x6b, 0x70, 0x7f, 145 + 0x82, 0x7e, 0x8a, 0x99, 0x4a, 0x48, 0x49, 0x4b, 146 + 0x4a, 0x4c, 0x4b, 0x7f); 149 147 150 148 /* 5.19.17 SETPANEL (CCh) */ 151 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL, 152 - 0x0b); 149 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPANEL, 150 + 0x0b); 153 151 154 152 /* Unknown command, not listed in the HX8394-F datasheet */ 155 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1, 156 - 0x1f, 0x31); 153 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN1, 154 + 0x1f, 0x31); 157 155 158 156 /* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */ 159 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM, 160 - 0x7d, 0x7d); 157 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETVCOM, 158 + 0x7d, 0x7d); 161 159 162 160 /* Unknown command, not listed in the HX8394-F datasheet */ 163 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3, 164 - 0x02); 161 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN3, 162 + 0x02); 165 163 166 164 /* 5.19.11 Set register bank (BDh) */ 167 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, 168 - 0x01); 165 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK, 166 + 0x01); 169 167 170 168 /* 5.19.2 SETPOWER: Set power (B1h) */ 171 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, 172 - 0x00); 169 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER, 170 + 0x00); 173 171 174 172 /* 5.19.11 Set register bank (BDh) */ 175 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, 176 - 0x00); 173 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK, 174 + 0x00); 177 175 178 176 /* Unknown command, not listed in the HX8394-F datasheet */ 179 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3, 180 - 0xed); 181 - 182 - return 0; 177 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN3, 178 + 0xed); 183 179 } 184 180 185 181 static const struct drm_display_mode hsd060bhw4_mode = { ··· 201 205 .init_sequence = hsd060bhw4_init_sequence, 202 206 }; 203 207 204 - static int powkiddy_x55_init_sequence(struct hx8394 *ctx) 208 + static void powkiddy_x55_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) 205 209 { 206 - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 207 - 208 210 /* 5.19.8 SETEXTC: Set extension command (B9h) */ 209 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC, 210 - 0xff, 0x83, 0x94); 211 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC, 212 + 0xff, 0x83, 0x94); 211 213 212 214 /* 5.19.9 SETMIPI: Set MIPI control (BAh) */ 213 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI, 214 - 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0); 215 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETMIPI, 216 + 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0); 215 217 216 218 /* 5.19.2 SETPOWER: Set power (B1h) */ 217 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, 218 - 0x48, 0x12, 0x72, 0x09, 0x32, 0x54, 0x71, 0x71, 0x57, 0x47); 219 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER, 220 + 0x48, 0x12, 0x72, 0x09, 0x32, 0x54, 0x71, 0x71, 0x57, 0x47); 219 221 220 222 /* 5.19.3 SETDISP: Set display related register (B2h) */ 221 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP, 222 - 0x00, 0x80, 0x64, 0x2c, 0x16, 0x2f); 223 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP, 224 + 0x00, 0x80, 0x64, 0x2c, 0x16, 0x2f); 223 225 224 226 /* 5.19.4 SETCYC: Set display waveform cycles (B4h) */ 225 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC, 226 - 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0c, 0x86, 0x75, 227 - 0x00, 0x3f, 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0c, 228 - 0x86); 227 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC, 228 + 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0c, 0x86, 0x75, 229 + 0x00, 0x3f, 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0c, 230 + 0x86); 229 231 230 232 /* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */ 231 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM, 232 - 0x6e, 0x6e); 233 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETVCOM, 234 + 0x6e, 0x6e); 233 235 234 236 /* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */ 235 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0, 236 - 0x00, 0x00, 0x07, 0x07, 0x40, 0x07, 0x0c, 0x00, 0x08, 0x10, 237 - 0x08, 0x00, 0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a, 0x02, 0x15, 238 - 0x06, 0x05, 0x06, 0x47, 0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07, 239 - 0x07, 0x0c, 0x40); 237 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0, 238 + 0x00, 0x00, 0x07, 0x07, 0x40, 0x07, 0x0c, 0x00, 0x08, 0x10, 239 + 0x08, 0x00, 0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a, 0x02, 0x15, 240 + 0x06, 0x05, 0x06, 0x47, 0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07, 241 + 0x07, 0x0c, 0x40); 240 242 241 243 /* 5.19.20 Set GIP Option1 (D5h) */ 242 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1, 243 - 0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 244 - 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25, 0x18, 0x18, 245 - 0x26, 0x27, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 246 - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21, 247 - 0x18, 0x18, 0x18, 0x18); 244 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1, 245 + 0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 246 + 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25, 0x18, 0x18, 247 + 0x26, 0x27, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 248 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21, 249 + 0x18, 0x18, 0x18, 0x18); 248 250 249 251 /* 5.19.21 Set GIP Option2 (D6h) */ 250 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2, 251 - 0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 252 - 0x01, 0x00, 0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20, 0x18, 0x18, 253 - 0x27, 0x26, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 254 - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x25, 0x24, 255 - 0x18, 0x18, 0x18, 0x18); 252 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2, 253 + 0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 254 + 0x01, 0x00, 0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20, 0x18, 0x18, 255 + 0x27, 0x26, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 256 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x25, 0x24, 257 + 0x18, 0x18, 0x18, 0x18); 256 258 257 259 /* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */ 258 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA, 259 - 0x00, 0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24, 0x22, 0x47, 0x56, 260 - 0x65, 0x66, 0x6e, 0x82, 0x88, 0x8b, 0x9a, 0x9d, 0x98, 0xa8, 261 - 0xb9, 0x5d, 0x5c, 0x61, 0x66, 0x6a, 0x6f, 0x7f, 0x7f, 0x00, 262 - 0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24, 0x22, 0x47, 0x56, 0x65, 263 - 0x65, 0x6e, 0x81, 0x87, 0x8b, 0x98, 0x9d, 0x99, 0xa8, 0xba, 264 - 0x5d, 0x5d, 0x62, 0x67, 0x6b, 0x72, 0x7f, 0x7f); 260 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGAMMA, 261 + 0x00, 0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24, 0x22, 0x47, 0x56, 262 + 0x65, 0x66, 0x6e, 0x82, 0x88, 0x8b, 0x9a, 0x9d, 0x98, 0xa8, 263 + 0xb9, 0x5d, 0x5c, 0x61, 0x66, 0x6a, 0x6f, 0x7f, 0x7f, 0x00, 264 + 0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24, 0x22, 0x47, 0x56, 0x65, 265 + 0x65, 0x6e, 0x81, 0x87, 0x8b, 0x98, 0x9d, 0x99, 0xa8, 0xba, 266 + 0x5d, 0x5d, 0x62, 0x67, 0x6b, 0x72, 0x7f, 0x7f); 265 267 266 268 /* Unknown command, not listed in the HX8394-F datasheet */ 267 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1, 268 - 0x1f, 0x31); 269 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN1, 270 + 0x1f, 0x31); 269 271 270 272 /* 5.19.17 SETPANEL (CCh) */ 271 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL, 272 - 0x0b); 273 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPANEL, 274 + 0x0b); 273 275 274 276 /* Unknown command, not listed in the HX8394-F datasheet */ 275 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3, 276 - 0x02); 277 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN3, 278 + 0x02); 277 279 278 280 /* 5.19.11 Set register bank (BDh) */ 279 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, 280 - 0x02); 281 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK, 282 + 0x02); 281 283 282 284 /* Unknown command, not listed in the HX8394-F datasheet */ 283 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN4, 284 - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 285 - 0xff, 0xff); 285 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN4, 286 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 287 + 0xff, 0xff); 286 288 287 289 /* 5.19.11 Set register bank (BDh) */ 288 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, 289 - 0x00); 290 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK, 291 + 0x00); 290 292 291 293 /* 5.19.11 Set register bank (BDh) */ 292 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, 293 - 0x01); 294 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK, 295 + 0x01); 294 296 295 297 /* 5.19.2 SETPOWER: Set power (B1h) */ 296 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, 297 - 0x00); 298 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER, 299 + 0x00); 298 300 299 301 /* 5.19.11 Set register bank (BDh) */ 300 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, 301 - 0x00); 302 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK, 303 + 0x00); 302 304 303 305 /* Unknown command, not listed in the HX8394-F datasheet */ 304 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN5, 305 - 0x40, 0x81, 0x50, 0x00, 0x1a, 0xfc, 0x01); 306 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN5, 307 + 0x40, 0x81, 0x50, 0x00, 0x1a, 0xfc, 0x01); 306 308 307 309 /* Unknown command, not listed in the HX8394-F datasheet */ 308 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN2, 309 - 0xed); 310 - 311 - return 0; 310 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN2, 311 + 0xed); 312 312 } 313 313 314 314 static const struct drm_display_mode powkiddy_x55_mode = { ··· 331 339 .init_sequence = powkiddy_x55_init_sequence, 332 340 }; 333 341 334 - static int mchp_ac40t08a_init_sequence(struct hx8394 *ctx) 342 + static void mchp_ac40t08a_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) 335 343 { 336 - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 337 - 338 344 /* DCS commands do not seem to be sent correclty without this delay */ 339 - msleep(20); 345 + mipi_dsi_msleep(dsi_ctx, 20); 340 346 341 347 /* 5.19.8 SETEXTC: Set extension command (B9h) */ 342 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC, 343 - 0xff, 0x83, 0x94); 348 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC, 349 + 0xff, 0x83, 0x94); 344 350 345 351 /* 5.19.9 SETMIPI: Set MIPI control (BAh) */ 346 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI, 347 - 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0); 352 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETMIPI, 353 + 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0); 348 354 349 355 /* 5.19.2 SETPOWER: Set power (B1h) */ 350 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, 351 - 0x48, 0x12, 0x72, 0x09, 0x32, 0x54, 352 - 0x71, 0x71, 0x57, 0x47); 356 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER, 357 + 0x48, 0x12, 0x72, 0x09, 0x32, 0x54, 358 + 0x71, 0x71, 0x57, 0x47); 353 359 354 360 /* 5.19.3 SETDISP: Set display related register (B2h) */ 355 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP, 356 - 0x00, 0x80, 0x64, 0x0c, 0x0d, 0x2f); 361 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP, 362 + 0x00, 0x80, 0x64, 0x0c, 0x0d, 0x2f); 357 363 358 364 /* 5.19.4 SETCYC: Set display waveform cycles (B4h) */ 359 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC, 360 - 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 361 - 0x01, 0x0c, 0x86, 0x75, 0x00, 0x3f, 362 - 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 363 - 0x01, 0x0c, 0x86); 365 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC, 366 + 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 367 + 0x01, 0x0c, 0x86, 0x75, 0x00, 0x3f, 368 + 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 369 + 0x01, 0x0c, 0x86); 364 370 365 371 /* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */ 366 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM, 367 - 0x6e, 0x6e); 372 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETVCOM, 373 + 0x6e, 0x6e); 368 374 369 375 /* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */ 370 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0, 371 - 0x00, 0x00, 0x07, 0x07, 0x40, 0x07, 372 - 0x0c, 0x00, 0x08, 0x10, 0x08, 0x00, 373 - 0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a, 374 - 0x02, 0x15, 0x06, 0x05, 0x06, 0x47, 375 - 0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07, 376 - 0x07, 0x0c, 0x40); 376 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0, 377 + 0x00, 0x00, 0x07, 0x07, 0x40, 0x07, 378 + 0x0c, 0x00, 0x08, 0x10, 0x08, 0x00, 379 + 0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a, 380 + 0x02, 0x15, 0x06, 0x05, 0x06, 0x47, 381 + 0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07, 382 + 0x07, 0x0c, 0x40); 377 383 378 384 /* 5.19.20 Set GIP Option1 (D5h) */ 379 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1, 380 - 0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01, 381 - 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 382 - 0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25, 383 - 0x18, 0x18, 0x26, 0x27, 0x18, 0x18, 384 - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 385 - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 386 - 0x18, 0x18, 0x20, 0x21, 0x18, 0x18, 387 - 0x18, 0x18); 385 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1, 386 + 0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01, 387 + 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 388 + 0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25, 389 + 0x18, 0x18, 0x26, 0x27, 0x18, 0x18, 390 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 391 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 392 + 0x18, 0x18, 0x20, 0x21, 0x18, 0x18, 393 + 0x18, 0x18); 388 394 389 395 /* 5.19.21 Set GIP Option2 (D6h) */ 390 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2, 391 - 0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06, 392 - 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 393 - 0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20, 394 - 0x18, 0x18, 0x27, 0x26, 0x18, 0x18, 395 - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 396 - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 397 - 0x18, 0x18, 0x25, 0x24, 0x18, 0x18, 398 - 0x18, 0x18); 396 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2, 397 + 0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06, 398 + 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 399 + 0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20, 400 + 0x18, 0x18, 0x27, 0x26, 0x18, 0x18, 401 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 402 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 403 + 0x18, 0x18, 0x25, 0x24, 0x18, 0x18, 404 + 0x18, 0x18); 399 405 400 406 /* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */ 401 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA, 402 - 0x00, 0x0a, 0x15, 0x1b, 0x1e, 0x21, 403 - 0x24, 0x22, 0x47, 0x56, 0x65, 0x66, 404 - 0x6e, 0x82, 0x88, 0x8b, 0x9a, 0x9d, 405 - 0x98, 0xa8, 0xb9, 0x5d, 0x5c, 0x61, 406 - 0x66, 0x6a, 0x6f, 0x7f, 0x7f, 0x00, 407 - 0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24, 408 - 0x22, 0x47, 0x56, 0x65, 0x65, 0x6e, 409 - 0x81, 0x87, 0x8b, 0x98, 0x9d, 0x99, 410 - 0xa8, 0xba, 0x5d, 0x5d, 0x62, 0x67, 411 - 0x6b, 0x72, 0x7f, 0x7f); 407 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGAMMA, 408 + 0x00, 0x0a, 0x15, 0x1b, 0x1e, 0x21, 409 + 0x24, 0x22, 0x47, 0x56, 0x65, 0x66, 410 + 0x6e, 0x82, 0x88, 0x8b, 0x9a, 0x9d, 411 + 0x98, 0xa8, 0xb9, 0x5d, 0x5c, 0x61, 412 + 0x66, 0x6a, 0x6f, 0x7f, 0x7f, 0x00, 413 + 0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24, 414 + 0x22, 0x47, 0x56, 0x65, 0x65, 0x6e, 415 + 0x81, 0x87, 0x8b, 0x98, 0x9d, 0x99, 416 + 0xa8, 0xba, 0x5d, 0x5d, 0x62, 0x67, 417 + 0x6b, 0x72, 0x7f, 0x7f); 412 418 413 419 /* Unknown command, not listed in the HX8394-F datasheet (C0H) */ 414 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1, 415 - 0x1f, 0x73); 420 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN1, 421 + 0x1f, 0x73); 416 422 417 423 /* Set CABC control (C9h)*/ 418 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCABC, 419 - 0x76, 0x00, 0x30); 424 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCABC, 425 + 0x76, 0x00, 0x30); 420 426 421 427 /* 5.19.17 SETPANEL (CCh) */ 422 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL, 423 - 0x0b); 428 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPANEL, 429 + 0x0b); 424 430 425 431 /* Unknown command, not listed in the HX8394-F datasheet (D4h) */ 426 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3, 427 - 0x02); 432 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN3, 433 + 0x02); 428 434 429 435 /* 5.19.11 Set register bank (BDh) */ 430 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, 431 - 0x02); 436 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK, 437 + 0x02); 432 438 433 439 /* 5.19.11 Set register bank (D8h) */ 434 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN4, 435 - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 436 - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff); 440 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN4, 441 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 442 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff); 437 443 438 444 /* 5.19.11 Set register bank (BDh) */ 439 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, 440 - 0x00); 445 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK, 446 + 0x00); 441 447 442 448 /* 5.19.11 Set register bank (BDh) */ 443 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, 444 - 0x01); 449 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK, 450 + 0x01); 445 451 446 452 /* 5.19.2 SETPOWER: Set power (B1h) */ 447 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, 448 - 0x00); 453 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER, 454 + 0x00); 449 455 450 456 /* 5.19.11 Set register bank (BDh) */ 451 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, 452 - 0x00); 457 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK, 458 + 0x00); 453 459 454 460 /* Unknown command, not listed in the HX8394-F datasheet (C6h) */ 455 - mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN2, 456 - 0xed); 457 - 458 - return 0; 461 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN2, 462 + 0xed); 459 463 } 460 464 461 465 static const struct drm_display_mode mchp_ac40t08a_mode = { ··· 481 493 { 482 494 struct hx8394 *ctx = panel_to_hx8394(panel); 483 495 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 496 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 484 497 int ret; 485 498 486 - ret = ctx->desc->init_sequence(ctx); 487 - if (ret) { 488 - dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret); 489 - return ret; 490 - } 499 + ctx->desc->init_sequence(&dsi_ctx); 491 500 492 - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); 493 - if (ret) { 494 - dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret); 495 - return ret; 496 - } 501 + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); 497 502 503 + if (dsi_ctx.accum_err) 504 + return dsi_ctx.accum_err; 498 505 /* Panel is operational 120 msec after reset */ 499 506 msleep(120); 500 507 501 - ret = mipi_dsi_dcs_set_display_on(dsi); 502 - if (ret) { 503 - dev_err(ctx->dev, "Failed to turn on the display: %d\n", ret); 508 + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); 509 + if (dsi_ctx.accum_err) 504 510 goto sleep_in; 505 - } 506 511 507 512 return 0; 508 513 509 514 sleep_in: 515 + ret = dsi_ctx.accum_err; 516 + dsi_ctx.accum_err = 0; 517 + 510 518 /* This will probably fail, but let's try orderly power off anyway. */ 511 - if (!mipi_dsi_dcs_enter_sleep_mode(dsi)) 512 - msleep(50); 519 + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); 520 + mipi_dsi_msleep(&dsi_ctx, 50); 513 521 514 522 return ret; 515 523 } ··· 514 530 { 515 531 struct hx8394 *ctx = panel_to_hx8394(panel); 516 532 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 517 - int ret; 533 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 518 534 519 - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 520 - if (ret) { 521 - dev_err(ctx->dev, "Failed to enter sleep mode: %d\n", ret); 522 - return ret; 523 - } 535 + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); 536 + mipi_dsi_msleep(&dsi_ctx, 50); /* about 3 frames */ 524 537 525 - msleep(50); /* about 3 frames */ 526 - 527 - return 0; 538 + return dsi_ctx.accum_err; 528 539 } 529 540 530 541 static int hx8394_unprepare(struct drm_panel *panel)