tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge tag 'soc-fixes-6.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC fixes from Arnd Bergmann:
"There are 18 devicetree fixes for three arm64 plaforms: Qualcomm
Snapdragon, Rockchips and NXP i.MX. These get updated to more
correctly describe the hardware, fixing issues with:

- real-time clock on Snapdragon based laptops

- SD card detection, PCI probing and HDMI/DDC communication on
Rockchips

- ethernet and SPI probing on certain i.MX based boards

- a regression with the i.MX watchdog

Aside from the devicetree fixes, there are two additional fixes for
the merged ASPEED LPC snoop driver that saw some changes in 6.16, and
one additional driver enabled in arm64 defconfig to fix CPU frequency
scaling"

* tag 'soc-fixes-6.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (21 commits)
arm64: dts: freescale: imx8mm-verdin: Keep LDO5 always on
soc: aspeed: lpc-snoop: Don't disable channels that aren't enabled
soc: aspeed: lpc-snoop: Cleanup resources in stack-order
arm64: dts: imx95: Correct the DMA interrupter number of pcie0_ep
arm64: dts: rockchip: Add missing fan-supply to rk3566-quartz64-a
arm64: dts: rockchip: use cs-gpios for spi1 on ringneck
arm64: dts: add big-endian property back into watchdog node
arm64: dts: imx95-15x15-evk: fix the overshoot issue of NETC
arm64: dts: imx95-19x19-evk: fix the overshoot issue of NETC
arm64: dts: rockchip: list all CPU supplies on ArmSoM Sige5
arm64: dts: imx8mp-venice-gw74xx: fix TPM SPI frequency
arm64: dts: imx8mp-venice-gw73xx: fix TPM SPI frequency
arm64: dts: imx8mp-venice-gw72xx: fix TPM SPI frequency
arm64: dts: imx8mp-venice-gw71xx: fix TPM SPI frequency
arm64: dts: qcom: x1e80100: describe uefi rtc offset
arm64: dts: qcom: sc8280xp-x13s: describe uefi rtc offset
arm64: defconfig: Enable Qualcomm CPUCP mailbox driver
arm64: dts: rockchip: Add cd-gpios for sdcard detect on Cool Pi 4B
arm64: dts: rockchip: Add cd-gpios for sdcard detect on Cool Pi CM5
arm64: dts: rockchip: Adjust the HDMI DDC IO driver strength for rk3588
...

Linus Torvalds 4664a4dd e003ef2c

+143 -36
+2 -1
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
··· 687 687 }; 688 688 689 689 wdog0: watchdog@2ad0000 { 690 - compatible = "fsl,imx21-wdt"; 690 + compatible = "fsl,ls1046a-wdt", "fsl,imx21-wdt"; 691 691 reg = <0x0 0x2ad0000 0x0 0x10000>; 692 692 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 693 693 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 694 694 QORIQ_CLK_PLL_DIV(2)>; 695 + big-endian; 695 696 }; 696 697 697 698 edma0: dma-controller@2c00000 {
+1
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
··· 464 464 }; 465 465 466 466 reg_nvcc_sd: LDO5 { 467 + regulator-always-on; 467 468 regulator-max-microvolt = <3300000>; 468 469 regulator-min-microvolt = <1800000>; 469 470 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
··· 70 70 tpm@1 { 71 71 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 72 72 reg = <0x1>; 73 - spi-max-frequency = <36000000>; 73 + spi-max-frequency = <25000000>; 74 74 }; 75 75 }; 76 76
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
··· 110 110 tpm@1 { 111 111 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 112 112 reg = <0x1>; 113 - spi-max-frequency = <36000000>; 113 + spi-max-frequency = <25000000>; 114 114 }; 115 115 }; 116 116
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
··· 122 122 tpm@1 { 123 123 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 124 124 reg = <0x1>; 125 - spi-max-frequency = <36000000>; 125 + spi-max-frequency = <25000000>; 126 126 }; 127 127 }; 128 128
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
··· 201 201 tpm@0 { 202 202 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 203 203 reg = <0x0>; 204 - spi-max-frequency = <36000000>; 204 + spi-max-frequency = <25000000>; 205 205 }; 206 206 }; 207 207
+10 -10
arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
··· 574 574 &scmi_iomuxc { 575 575 pinctrl_emdio: emdiogrp { 576 576 fsl,pins = < 577 - IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e 578 - IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e 577 + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e 578 + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e 579 579 >; 580 580 }; 581 581 582 582 pinctrl_enetc0: enetc0grp { 583 583 fsl,pins = < 584 - IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e 585 - IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e 586 - IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e 587 - IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e 584 + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e 585 + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e 586 + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e 587 + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e 588 588 IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e 589 589 IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e 590 590 IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e ··· 598 598 599 599 pinctrl_enetc1: enetc1grp { 600 600 fsl,pins = < 601 - IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e 602 - IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e 603 - IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e 604 - IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e 601 + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e 602 + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e 603 + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e 604 + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e 605 605 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e 606 606 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e 607 607 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e
+6 -6
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
··· 566 566 &scmi_iomuxc { 567 567 pinctrl_emdio: emdiogrp{ 568 568 fsl,pins = < 569 - IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e 570 - IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e 569 + IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e 570 + IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e 571 571 >; 572 572 }; 573 573 574 574 pinctrl_enetc0: enetc0grp { 575 575 fsl,pins = < 576 - IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e 577 - IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e 578 - IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e 579 - IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e 576 + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e 577 + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e 578 + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e 579 + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e 580 580 IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e 581 581 IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e 582 582 IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e
+1 -1
arch/arm64/boot/dts/freescale/imx95.dtsi
··· 1708 1708 <0x9 0 1 0>; 1709 1709 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; 1710 1710 num-lanes = <1>; 1711 - interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1711 + interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1712 1712 interrupt-names = "dma"; 1713 1713 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1714 1714 <&scmi_clk IMX95_CLK_HSIOPLL>,
+2
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
··· 1090 1090 }; 1091 1091 1092 1092 &pmk8280_rtc { 1093 + qcom,uefi-rtc-info; 1094 + 1093 1095 status = "okay"; 1094 1096 }; 1095 1097
+1
arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi
··· 224 224 reg-names = "rtc", "alarm"; 225 225 interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; 226 226 qcom,no-alarm; /* alarm owned by ADSP */ 227 + qcom,uefi-rtc-info; 227 228 }; 228 229 229 230 pmk8550_sdam_2: nvram@7100 {
+23
arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
··· 379 379 <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 380 380 }; 381 381 }; 382 + 383 + spi1 { 384 + spi1_csn0_gpio_pin: spi1-csn0-gpio-pin { 385 + rockchip,pins = 386 + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 387 + }; 388 + 389 + spi1_csn1_gpio_pin: spi1-csn1-gpio-pin { 390 + rockchip,pins = 391 + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 392 + }; 393 + }; 382 394 }; 383 395 384 396 &pmu_io_domains { ··· 406 394 407 395 &sdmmc { 408 396 vqmmc-supply = <&vccio_sd>; 397 + }; 398 + 399 + &spi1 { 400 + /* 401 + * Hardware CS has a very slow rise time of about 6us, 402 + * causing transmission errors. 403 + * With cs-gpios we have a rise time of about 20ns. 404 + */ 405 + cs-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>, <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; 406 + pinctrl-names = "default"; 407 + pinctrl-0 = <&spi1_clk &spi1_csn0_gpio_pin &spi1_csn1_gpio_pin &spi1_miso &spi1_mosi>; 409 408 }; 410 409 411 410 &tsadc {
+1
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
··· 30 30 31 31 fan: gpio_fan { 32 32 compatible = "gpio-fan"; 33 + fan-supply = <&vcc12v_dcin>; 33 34 gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; 34 35 gpio-fan,speed-map = 35 36 < 0 0>,
+28
arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts
··· 211 211 status = "okay"; 212 212 }; 213 213 214 + &cpu_b0 { 215 + cpu-supply = <&vdd_cpu_big_s0>; 216 + }; 217 + 218 + &cpu_b1 { 219 + cpu-supply = <&vdd_cpu_big_s0>; 220 + }; 221 + 222 + &cpu_b2 { 223 + cpu-supply = <&vdd_cpu_big_s0>; 224 + }; 225 + 226 + &cpu_b3 { 227 + cpu-supply = <&vdd_cpu_big_s0>; 228 + }; 229 + 214 230 &cpu_l0 { 231 + cpu-supply = <&vdd_cpu_lit_s0>; 232 + }; 233 + 234 + &cpu_l1 { 235 + cpu-supply = <&vdd_cpu_lit_s0>; 236 + }; 237 + 238 + &cpu_l2 { 239 + cpu-supply = <&vdd_cpu_lit_s0>; 240 + }; 241 + 242 + &cpu_l3 { 215 243 cpu-supply = <&vdd_cpu_lit_s0>; 216 244 }; 217 245
+1 -1
arch/arm64/boot/dts/rockchip/rk3576.dtsi
··· 615 615 <0 0 0 2 &pcie1_intc 1>, 616 616 <0 0 0 3 &pcie1_intc 2>, 617 617 <0 0 0 4 &pcie1_intc 3>; 618 - linux,pci-domain = <0>; 618 + linux,pci-domain = <1>; 619 619 max-link-speed = <2>; 620 620 num-ib-windows = <8>; 621 621 num-viewport = <8>;
+10 -10
arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
··· 578 578 hdmim0_tx0_scl: hdmim0-tx0-scl { 579 579 rockchip,pins = 580 580 /* hdmim0_tx0_scl */ 581 - <4 RK_PB7 5 &pcfg_pull_none>; 581 + <4 RK_PB7 5 &pcfg_pull_none_drv_level_5_smt>; 582 582 }; 583 583 584 584 /omit-if-no-ref/ 585 585 hdmim0_tx0_sda: hdmim0-tx0-sda { 586 586 rockchip,pins = 587 587 /* hdmim0_tx0_sda */ 588 - <4 RK_PC0 5 &pcfg_pull_none>; 588 + <4 RK_PC0 5 &pcfg_pull_none_drv_level_1_smt>; 589 589 }; 590 590 591 591 /omit-if-no-ref/ ··· 640 640 hdmim1_tx0_scl: hdmim1-tx0-scl { 641 641 rockchip,pins = 642 642 /* hdmim1_tx0_scl */ 643 - <0 RK_PD5 11 &pcfg_pull_none>; 643 + <0 RK_PD5 11 &pcfg_pull_none_drv_level_5_smt>; 644 644 }; 645 645 646 646 /omit-if-no-ref/ 647 647 hdmim1_tx0_sda: hdmim1-tx0-sda { 648 648 rockchip,pins = 649 649 /* hdmim1_tx0_sda */ 650 - <0 RK_PD4 11 &pcfg_pull_none>; 650 + <0 RK_PD4 11 &pcfg_pull_none_drv_level_1_smt>; 651 651 }; 652 652 653 653 /omit-if-no-ref/ ··· 668 668 hdmim1_tx1_scl: hdmim1-tx1-scl { 669 669 rockchip,pins = 670 670 /* hdmim1_tx1_scl */ 671 - <3 RK_PC6 5 &pcfg_pull_none>; 671 + <3 RK_PC6 5 &pcfg_pull_none_drv_level_5_smt>; 672 672 }; 673 673 674 674 /omit-if-no-ref/ 675 675 hdmim1_tx1_sda: hdmim1-tx1-sda { 676 676 rockchip,pins = 677 677 /* hdmim1_tx1_sda */ 678 - <3 RK_PC5 5 &pcfg_pull_none>; 678 + <3 RK_PC5 5 &pcfg_pull_none_drv_level_1_smt>; 679 679 }; 680 680 /omit-if-no-ref/ 681 681 hdmim2_rx_cec: hdmim2-rx-cec { ··· 709 709 hdmim2_tx0_scl: hdmim2-tx0-scl { 710 710 rockchip,pins = 711 711 /* hdmim2_tx0_scl */ 712 - <3 RK_PC7 5 &pcfg_pull_none>; 712 + <3 RK_PC7 5 &pcfg_pull_none_drv_level_5_smt>; 713 713 }; 714 714 715 715 /omit-if-no-ref/ 716 716 hdmim2_tx0_sda: hdmim2-tx0-sda { 717 717 rockchip,pins = 718 718 /* hdmim2_tx0_sda */ 719 - <3 RK_PD0 5 &pcfg_pull_none>; 719 + <3 RK_PD0 5 &pcfg_pull_none_drv_level_1_smt>; 720 720 }; 721 721 722 722 /omit-if-no-ref/ ··· 730 730 hdmim2_tx1_scl: hdmim2-tx1-scl { 731 731 rockchip,pins = 732 732 /* hdmim2_tx1_scl */ 733 - <1 RK_PA4 5 &pcfg_pull_none>; 733 + <1 RK_PA4 5 &pcfg_pull_none_drv_level_5_smt>; 734 734 }; 735 735 736 736 /omit-if-no-ref/ 737 737 hdmim2_tx1_sda: hdmim2-tx1-sda { 738 738 rockchip,pins = 739 739 /* hdmim2_tx1_sda */ 740 - <1 RK_PA3 5 &pcfg_pull_none>; 740 + <1 RK_PA3 5 &pcfg_pull_none_drv_level_1_smt>; 741 741 }; 742 742 743 743 /omit-if-no-ref/
+1
arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi
··· 321 321 bus-width = <4>; 322 322 cap-mmc-highspeed; 323 323 cap-sd-highspeed; 324 + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 324 325 disable-wp; 325 326 max-frequency = <150000000>; 326 327 no-sdio;
+3 -2
arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi
··· 160 160 hdmim0_tx1_scl: hdmim0-tx1-scl { 161 161 rockchip,pins = 162 162 /* hdmim0_tx1_scl */ 163 - <2 RK_PB5 4 &pcfg_pull_none>; 163 + <2 RK_PB5 4 &pcfg_pull_none_drv_level_3_smt>; 164 164 }; 165 165 166 166 /omit-if-no-ref/ 167 167 hdmim0_tx1_sda: hdmim0-tx1-sda { 168 168 rockchip,pins = 169 169 /* hdmim0_tx1_sda */ 170 - <2 RK_PB4 4 &pcfg_pull_none>; 170 + <2 RK_PB4 4 &pcfg_pull_none_drv_level_1_smt>; 171 + 171 172 }; 172 173 }; 173 174
+1
arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
··· 474 474 bus-width = <4>; 475 475 cap-mmc-highspeed; 476 476 cap-sd-highspeed; 477 + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 477 478 disable-wp; 478 479 max-frequency = <150000000>; 479 480 no-sdio;
+35
arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi
··· 333 333 }; 334 334 335 335 /omit-if-no-ref/ 336 + pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt { 337 + bias-disable; 338 + drive-strength = <1>; 339 + input-schmitt-enable; 340 + }; 341 + 342 + /omit-if-no-ref/ 343 + pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt { 344 + bias-disable; 345 + drive-strength = <2>; 346 + input-schmitt-enable; 347 + }; 348 + 349 + /omit-if-no-ref/ 350 + pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt { 351 + bias-disable; 352 + drive-strength = <3>; 353 + input-schmitt-enable; 354 + }; 355 + 356 + /omit-if-no-ref/ 357 + pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt { 358 + bias-disable; 359 + drive-strength = <4>; 360 + input-schmitt-enable; 361 + }; 362 + 363 + /omit-if-no-ref/ 364 + pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt { 365 + bias-disable; 366 + drive-strength = <5>; 367 + input-schmitt-enable; 368 + }; 369 + 370 + /omit-if-no-ref/ 336 371 pcfg_output_high: pcfg-output-high { 337 372 output-high; 338 373 };
+1
arch/arm64/configs/defconfig
··· 1444 1444 CONFIG_BCM2835_MBOX=y 1445 1445 CONFIG_QCOM_APCS_IPC=y 1446 1446 CONFIG_MTK_ADSP_MBOX=m 1447 + CONFIG_QCOM_CPUCP_MBOX=m 1447 1448 CONFIG_QCOM_IPCC=y 1448 1449 CONFIG_ROCKCHIP_IOMMU=y 1449 1450 CONFIG_TEGRA_IOMMU_SMMU=y
+12 -1
drivers/soc/aspeed/aspeed-lpc-snoop.c
··· 58 58 }; 59 59 60 60 struct aspeed_lpc_snoop_channel { 61 + bool enabled; 61 62 struct kfifo fifo; 62 63 wait_queue_head_t wq; 63 64 struct miscdevice miscdev; ··· 191 190 const struct aspeed_lpc_snoop_model_data *model_data = 192 191 of_device_get_match_data(dev); 193 192 193 + if (WARN_ON(lpc_snoop->chan[channel].enabled)) 194 + return -EBUSY; 195 + 194 196 init_waitqueue_head(&lpc_snoop->chan[channel].wq); 195 197 /* Create FIFO datastructure */ 196 198 rc = kfifo_alloc(&lpc_snoop->chan[channel].fifo, ··· 240 236 regmap_update_bits(lpc_snoop->regmap, HICRB, 241 237 hicrb_en, hicrb_en); 242 238 239 + lpc_snoop->chan[channel].enabled = true; 240 + 243 241 return 0; 244 242 245 243 err_misc_deregister: ··· 254 248 static void aspeed_lpc_disable_snoop(struct aspeed_lpc_snoop *lpc_snoop, 255 249 int channel) 256 250 { 251 + if (!lpc_snoop->chan[channel].enabled) 252 + return; 253 + 257 254 switch (channel) { 258 255 case 0: 259 256 regmap_update_bits(lpc_snoop->regmap, HICR5, ··· 272 263 return; 273 264 } 274 265 275 - kfifo_free(&lpc_snoop->chan[channel].fifo); 266 + lpc_snoop->chan[channel].enabled = false; 267 + /* Consider improving safety wrt concurrent reader(s) */ 276 268 misc_deregister(&lpc_snoop->chan[channel].miscdev); 269 + kfifo_free(&lpc_snoop->chan[channel].fifo); 277 270 } 278 271 279 272 static int aspeed_lpc_snoop_probe(struct platform_device *pdev)