Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-next-2025-01-07' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
Driver Changes:
- Some DG2 refactor to fix DG2 bugs when operating with certain CPUs (Raag)
- Use hw support for min/interim ddb allocation for async flip (Vinod)
- More general code refactor to allow full display separation (Jani)
- Expose dsc sink max slice count via debugfs (Swati)
- Fix C10 pll programming sequence (Suraj)
- Fix DG1 power gate sequence (Rodrigo)
- Use preemption timeout on selftest cleanup (Janusz)
- DP DSC related fixes (Ankit)
- Fix HDCP compliance test (Suraj)
- Clean and Optimise mtl_ddi_prepare_link_retrain (Suraj)
- Adjust Added Wake Time with PKG_C_LATENCY (Animesh)
- Enabling uncompressed 128b/132b UHBR SST (Jani)
- Handle hdmi connector init failures, and no HDMI/DP cases (Jani)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Z31_WPbBoHkwgEA9@intel.com
+1988
-1481
+2
-8
drivers/gpu/drm/display/drm_dp_mst_topology.c
+2
-8
drivers/gpu/drm/display/drm_dp_mst_topology.c
···
3572
3572
}
3573
3573
3574
3574
/**
3575
-
* drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link
3576
-
* @mgr: The &drm_dp_mst_topology_mgr to use
3575
+
* drm_dp_get_vc_payload_bw - get the VC payload BW for an MTP link
3577
3576
* @link_rate: link rate in 10kbits/s units
3578
3577
* @link_lane_count: lane count
3579
3578
*
···
3583
3584
*
3584
3585
* Returns the BW / timeslot value in 20.12 fixed point format.
3585
3586
*/
3586
-
fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
3587
-
int link_rate, int link_lane_count)
3587
+
fixed20_12 drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count)
3588
3588
{
3589
3589
int ch_coding_efficiency =
3590
3590
drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(link_rate));
3591
3591
fixed20_12 ret;
3592
-
3593
-
if (link_rate == 0 || link_lane_count == 0)
3594
-
drm_dbg_kms(mgr->dev, "invalid link rate/lane count: (%d / %d)\n",
3595
-
link_rate, link_lane_count);
3596
3592
3597
3593
/* See DP v2.0 2.6.4.2, 2.7.6.3 VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
3598
3594
ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count,
+3
drivers/gpu/drm/i915/Makefile
+3
drivers/gpu/drm/i915/Makefile
···
34
34
i915_sysfs.o \
35
35
i915_utils.o \
36
36
intel_clock_gating.o \
37
+
intel_cpu_info.o \
37
38
intel_device_info.o \
38
39
intel_memory_region.o \
39
40
intel_pcode.o \
···
43
42
intel_sbi.o \
44
43
intel_step.o \
45
44
intel_uncore.o \
45
+
intel_uncore_trace.o \
46
46
intel_wakeref.o \
47
47
vlv_sideband.o \
48
48
vlv_suspend.o
···
238
236
display/intel_crtc_state_dump.o \
239
237
display/intel_cursor.o \
240
238
display/intel_display.o \
239
+
display/intel_display_conversion.o \
241
240
display/intel_display_driver.o \
242
241
display/intel_display_irq.o \
243
242
display/intel_display_params.o \
-1
drivers/gpu/drm/i915/display/dvo_ns2501.c
-1
drivers/gpu/drm/i915/display/dvo_ns2501.c
+1
drivers/gpu/drm/i915/display/g4x_dp.c
+1
drivers/gpu/drm/i915/display/g4x_dp.c
+24
-12
drivers/gpu/drm/i915/display/g4x_hdmi.c
+24
-12
drivers/gpu/drm/i915/display/g4x_hdmi.c
···
6
6
*/
7
7
8
8
#include "g4x_hdmi.h"
9
+
#include "i915_drv.h"
9
10
#include "i915_reg.h"
10
11
#include "intel_atomic.h"
11
12
#include "intel_audio.h"
···
683
682
"Platform does not support HDMI %c\n", port_name(port));
684
683
}
685
684
686
-
void g4x_hdmi_init(struct drm_i915_private *dev_priv,
685
+
bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
687
686
i915_reg_t hdmi_reg, enum port port)
688
687
{
689
688
struct intel_display *display = &dev_priv->display;
···
693
692
struct intel_connector *intel_connector;
694
693
695
694
if (!assert_port_valid(dev_priv, port))
696
-
return;
695
+
return false;
697
696
698
697
if (!assert_hdmi_port_valid(dev_priv, port))
699
-
return;
698
+
return false;
700
699
701
700
devdata = intel_bios_encoder_data_lookup(display, port);
702
701
···
707
706
708
707
dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
709
708
if (!dig_port)
710
-
return;
709
+
return false;
711
710
712
711
dig_port->aux_ch = AUX_CH_NONE;
713
712
714
713
intel_connector = intel_connector_alloc();
715
-
if (!intel_connector) {
716
-
kfree(dig_port);
717
-
return;
718
-
}
714
+
if (!intel_connector)
715
+
goto err_connector_alloc;
719
716
720
717
intel_encoder = &dig_port->base;
721
718
···
721
722
722
723
mutex_init(&dig_port->hdcp_mutex);
723
724
724
-
drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
725
-
&intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
726
-
"HDMI %c", port_name(port));
725
+
if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
726
+
&intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
727
+
"HDMI %c", port_name(port)))
728
+
goto err_encoder_init;
727
729
728
730
intel_encoder->hotplug = intel_hdmi_hotplug;
729
731
intel_encoder->compute_config = g4x_hdmi_compute_config;
···
787
787
788
788
intel_infoframe_init(dig_port);
789
789
790
-
intel_hdmi_init_connector(dig_port, intel_connector);
790
+
if (!intel_hdmi_init_connector(dig_port, intel_connector))
791
+
goto err_init_connector;
792
+
793
+
return true;
794
+
795
+
err_init_connector:
796
+
drm_encoder_cleanup(&intel_encoder->base);
797
+
err_encoder_init:
798
+
kfree(intel_connector);
799
+
err_connector_alloc:
800
+
kfree(dig_port);
801
+
802
+
return false;
791
803
}
+3
-2
drivers/gpu/drm/i915/display/g4x_hdmi.h
+3
-2
drivers/gpu/drm/i915/display/g4x_hdmi.h
···
16
16
struct drm_i915_private;
17
17
18
18
#ifdef I915
19
-
void g4x_hdmi_init(struct drm_i915_private *dev_priv,
19
+
bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
20
20
i915_reg_t hdmi_reg, enum port port);
21
21
int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
22
22
struct drm_atomic_state *state);
23
23
#else
24
-
static inline void g4x_hdmi_init(struct drm_i915_private *dev_priv,
24
+
static inline bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
25
25
i915_reg_t hdmi_reg, int port)
26
26
{
27
+
return false;
27
28
}
28
29
static inline int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
29
30
struct drm_atomic_state *state)
+3
-1
drivers/gpu/drm/i915/display/i9xx_display_sr.c
+3
-1
drivers/gpu/drm/i915/display/i9xx_display_sr.c
···
3
3
* Copyright © 2024 Intel Corporation
4
4
*/
5
5
6
-
#include "i915_drv.h"
6
+
#include <drm/drm_device.h>
7
+
7
8
#include "i915_reg.h"
8
9
#include "i9xx_display_sr.h"
10
+
#include "i9xx_wm_regs.h"
9
11
#include "intel_de.h"
10
12
#include "intel_gmbus.h"
11
13
#include "intel_pci_config.h"
+1
drivers/gpu/drm/i915/display/i9xx_plane.c
+1
drivers/gpu/drm/i915/display/i9xx_plane.c
+1
drivers/gpu/drm/i915/display/i9xx_wm.c
+1
drivers/gpu/drm/i915/display/i9xx_wm.c
+257
drivers/gpu/drm/i915/display/i9xx_wm_regs.h
+257
drivers/gpu/drm/i915/display/i9xx_wm_regs.h
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/* Copyright © 2024 Intel Corporation */
3
+
4
+
#ifndef __I9XX_WM_REGS_H__
5
+
#define __I9XX_WM_REGS_H__
6
+
7
+
#include "intel_display_reg_defs.h"
8
+
9
+
#define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
10
+
#define DSPARB_CSTART_MASK (0x7f << 7)
11
+
#define DSPARB_CSTART_SHIFT 7
12
+
#define DSPARB_BSTART_MASK (0x7f)
13
+
#define DSPARB_BSTART_SHIFT 0
14
+
#define DSPARB_BEND_SHIFT 9 /* on 855 */
15
+
#define DSPARB_AEND_SHIFT 0
16
+
#define DSPARB_SPRITEA_SHIFT_VLV 0
17
+
#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
18
+
#define DSPARB_SPRITEB_SHIFT_VLV 8
19
+
#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
20
+
#define DSPARB_SPRITEC_SHIFT_VLV 16
21
+
#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
22
+
#define DSPARB_SPRITED_SHIFT_VLV 24
23
+
#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
24
+
#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
25
+
#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
26
+
#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
27
+
#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
28
+
#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
29
+
#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
30
+
#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
31
+
#define DSPARB_SPRITED_HI_SHIFT_VLV 12
32
+
#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
33
+
#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
34
+
#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
35
+
#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
36
+
#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
37
+
#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
38
+
#define DSPARB_SPRITEE_SHIFT_VLV 0
39
+
#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
40
+
#define DSPARB_SPRITEF_SHIFT_VLV 8
41
+
#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
42
+
43
+
/* pnv/gen4/g4x/vlv/chv */
44
+
#define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
45
+
#define DSPFW_SR_SHIFT 23
46
+
#define DSPFW_SR_MASK (0x1ff << 23)
47
+
#define DSPFW_CURSORB_SHIFT 16
48
+
#define DSPFW_CURSORB_MASK (0x3f << 16)
49
+
#define DSPFW_PLANEB_SHIFT 8
50
+
#define DSPFW_PLANEB_MASK (0x7f << 8)
51
+
#define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
52
+
#define DSPFW_PLANEA_SHIFT 0
53
+
#define DSPFW_PLANEA_MASK (0x7f << 0)
54
+
#define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
55
+
#define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
56
+
#define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
57
+
#define DSPFW_FBC_SR_SHIFT 28
58
+
#define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
59
+
#define DSPFW_FBC_HPLL_SR_SHIFT 24
60
+
#define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
61
+
#define DSPFW_SPRITEB_SHIFT (16)
62
+
#define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
63
+
#define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
64
+
#define DSPFW_CURSORA_SHIFT 8
65
+
#define DSPFW_CURSORA_MASK (0x3f << 8)
66
+
#define DSPFW_PLANEC_OLD_SHIFT 0
67
+
#define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
68
+
#define DSPFW_SPRITEA_SHIFT 0
69
+
#define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
70
+
#define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
71
+
#define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
72
+
#define DSPFW_HPLL_SR_EN (1 << 31)
73
+
#define PINEVIEW_SELF_REFRESH_EN (1 << 30)
74
+
#define DSPFW_CURSOR_SR_SHIFT 24
75
+
#define DSPFW_CURSOR_SR_MASK (0x3f << 24)
76
+
#define DSPFW_HPLL_CURSOR_SHIFT 16
77
+
#define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
78
+
#define DSPFW_HPLL_SR_SHIFT 0
79
+
#define DSPFW_HPLL_SR_MASK (0x1ff << 0)
80
+
81
+
/* vlv/chv */
82
+
#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
83
+
#define DSPFW_SPRITEB_WM1_SHIFT 16
84
+
#define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
85
+
#define DSPFW_CURSORA_WM1_SHIFT 8
86
+
#define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
87
+
#define DSPFW_SPRITEA_WM1_SHIFT 0
88
+
#define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
89
+
#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
90
+
#define DSPFW_PLANEB_WM1_SHIFT 24
91
+
#define DSPFW_PLANEB_WM1_MASK (0xff << 24)
92
+
#define DSPFW_PLANEA_WM1_SHIFT 16
93
+
#define DSPFW_PLANEA_WM1_MASK (0xff << 16)
94
+
#define DSPFW_CURSORB_WM1_SHIFT 8
95
+
#define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
96
+
#define DSPFW_CURSOR_SR_WM1_SHIFT 0
97
+
#define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
98
+
#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
99
+
#define DSPFW_SR_WM1_SHIFT 0
100
+
#define DSPFW_SR_WM1_MASK (0x1ff << 0)
101
+
#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
102
+
#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
103
+
#define DSPFW_SPRITED_WM1_SHIFT 24
104
+
#define DSPFW_SPRITED_WM1_MASK (0xff << 24)
105
+
#define DSPFW_SPRITED_SHIFT 16
106
+
#define DSPFW_SPRITED_MASK_VLV (0xff << 16)
107
+
#define DSPFW_SPRITEC_WM1_SHIFT 8
108
+
#define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
109
+
#define DSPFW_SPRITEC_SHIFT 0
110
+
#define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
111
+
#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
112
+
#define DSPFW_SPRITEF_WM1_SHIFT 24
113
+
#define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
114
+
#define DSPFW_SPRITEF_SHIFT 16
115
+
#define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
116
+
#define DSPFW_SPRITEE_WM1_SHIFT 8
117
+
#define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
118
+
#define DSPFW_SPRITEE_SHIFT 0
119
+
#define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
120
+
#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
121
+
#define DSPFW_PLANEC_WM1_SHIFT 24
122
+
#define DSPFW_PLANEC_WM1_MASK (0xff << 24)
123
+
#define DSPFW_PLANEC_SHIFT 16
124
+
#define DSPFW_PLANEC_MASK_VLV (0xff << 16)
125
+
#define DSPFW_CURSORC_WM1_SHIFT 8
126
+
#define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
127
+
#define DSPFW_CURSORC_SHIFT 0
128
+
#define DSPFW_CURSORC_MASK (0x3f << 0)
129
+
130
+
/* vlv/chv high order bits */
131
+
#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
132
+
#define DSPFW_SR_HI_SHIFT 24
133
+
#define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
134
+
#define DSPFW_SPRITEF_HI_SHIFT 23
135
+
#define DSPFW_SPRITEF_HI_MASK (1 << 23)
136
+
#define DSPFW_SPRITEE_HI_SHIFT 22
137
+
#define DSPFW_SPRITEE_HI_MASK (1 << 22)
138
+
#define DSPFW_PLANEC_HI_SHIFT 21
139
+
#define DSPFW_PLANEC_HI_MASK (1 << 21)
140
+
#define DSPFW_SPRITED_HI_SHIFT 20
141
+
#define DSPFW_SPRITED_HI_MASK (1 << 20)
142
+
#define DSPFW_SPRITEC_HI_SHIFT 16
143
+
#define DSPFW_SPRITEC_HI_MASK (1 << 16)
144
+
#define DSPFW_PLANEB_HI_SHIFT 12
145
+
#define DSPFW_PLANEB_HI_MASK (1 << 12)
146
+
#define DSPFW_SPRITEB_HI_SHIFT 8
147
+
#define DSPFW_SPRITEB_HI_MASK (1 << 8)
148
+
#define DSPFW_SPRITEA_HI_SHIFT 4
149
+
#define DSPFW_SPRITEA_HI_MASK (1 << 4)
150
+
#define DSPFW_PLANEA_HI_SHIFT 0
151
+
#define DSPFW_PLANEA_HI_MASK (1 << 0)
152
+
#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
153
+
#define DSPFW_SR_WM1_HI_SHIFT 24
154
+
#define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
155
+
#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
156
+
#define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
157
+
#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
158
+
#define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
159
+
#define DSPFW_PLANEC_WM1_HI_SHIFT 21
160
+
#define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
161
+
#define DSPFW_SPRITED_WM1_HI_SHIFT 20
162
+
#define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
163
+
#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
164
+
#define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
165
+
#define DSPFW_PLANEB_WM1_HI_SHIFT 12
166
+
#define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
167
+
#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
168
+
#define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
169
+
#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
170
+
#define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
171
+
#define DSPFW_PLANEA_WM1_HI_SHIFT 0
172
+
#define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
173
+
174
+
/* drain latency register values*/
175
+
#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
176
+
#define DDL_CURSOR_SHIFT 24
177
+
#define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
178
+
#define DDL_PLANE_SHIFT 0
179
+
#define DDL_PRECISION_HIGH (1 << 7)
180
+
#define DDL_PRECISION_LOW (0 << 7)
181
+
#define DRAIN_LATENCY_MASK 0x7f
182
+
183
+
/* FIFO watermark sizes etc */
184
+
#define G4X_FIFO_LINE_SIZE 64
185
+
#define I915_FIFO_LINE_SIZE 64
186
+
#define I830_FIFO_LINE_SIZE 32
187
+
188
+
#define VALLEYVIEW_FIFO_SIZE 255
189
+
#define G4X_FIFO_SIZE 127
190
+
#define I965_FIFO_SIZE 512
191
+
#define I945_FIFO_SIZE 127
192
+
#define I915_FIFO_SIZE 95
193
+
#define I855GM_FIFO_SIZE 127 /* In cachelines */
194
+
#define I830_FIFO_SIZE 95
195
+
196
+
#define VALLEYVIEW_MAX_WM 0xff
197
+
#define G4X_MAX_WM 0x3f
198
+
#define I915_MAX_WM 0x3f
199
+
200
+
#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
201
+
#define PINEVIEW_FIFO_LINE_SIZE 64
202
+
#define PINEVIEW_MAX_WM 0x1ff
203
+
#define PINEVIEW_DFT_WM 0x3f
204
+
#define PINEVIEW_DFT_HPLLOFF_WM 0
205
+
#define PINEVIEW_GUARD_WM 10
206
+
#define PINEVIEW_CURSOR_FIFO 64
207
+
#define PINEVIEW_CURSOR_MAX_WM 0x3f
208
+
#define PINEVIEW_CURSOR_DFT_WM 0
209
+
#define PINEVIEW_CURSOR_GUARD_WM 5
210
+
211
+
#define VALLEYVIEW_CURSOR_MAX_WM 64
212
+
#define I965_CURSOR_FIFO 64
213
+
#define I965_CURSOR_MAX_WM 32
214
+
#define I965_CURSOR_DFT_WM 8
215
+
216
+
/* define the Watermark register on Ironlake */
217
+
#define _WM0_PIPEA_ILK 0x45100
218
+
#define _WM0_PIPEB_ILK 0x45104
219
+
#define _WM0_PIPEC_IVB 0x45200
220
+
#define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \
221
+
_WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
222
+
#define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16)
223
+
#define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
224
+
#define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
225
+
#define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
226
+
#define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
227
+
#define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
228
+
#define WM1_LP_ILK _MMIO(0x45108)
229
+
#define WM2_LP_ILK _MMIO(0x4510c)
230
+
#define WM3_LP_ILK _MMIO(0x45110)
231
+
#define WM_LP_ENABLE REG_BIT(31)
232
+
#define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
233
+
#define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
234
+
#define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
235
+
#define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
236
+
#define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
237
+
#define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
238
+
#define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
239
+
#define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
240
+
#define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
241
+
#define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
242
+
#define WM1S_LP_ILK _MMIO(0x45120)
243
+
#define WM2S_LP_IVB _MMIO(0x45124)
244
+
#define WM3S_LP_IVB _MMIO(0x45128)
245
+
#define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
246
+
#define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
247
+
#define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
248
+
249
+
#define WM_MISC _MMIO(0x45260)
250
+
#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
251
+
252
+
#define WM_DBG _MMIO(0x45280)
253
+
#define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
254
+
#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
255
+
#define WM_DBG_DISALLOW_SPRITE (1 << 2)
256
+
257
+
#endif /* __I9XX_WM_REGS_H__ */
+1
drivers/gpu/drm/i915/display/icl_dsi.c
+1
drivers/gpu/drm/i915/display/icl_dsi.c
+2
-1
drivers/gpu/drm/i915/display/intel_acpi.c
+2
-1
drivers/gpu/drm/i915/display/intel_acpi.c
···
9
9
#include <linux/acpi.h>
10
10
#include <acpi/video.h>
11
11
12
-
#include "i915_drv.h"
12
+
#include "i915_utils.h"
13
13
#include "intel_acpi.h"
14
+
#include "intel_display_core.h"
14
15
#include "intel_display_types.h"
15
16
16
17
#define INTEL_DSM_REVISION_ID 1 /* For Calpella anyway... */
+7
-21
drivers/gpu/drm/i915/display/intel_atomic_plane.c
+7
-21
drivers/gpu/drm/i915/display/intel_atomic_plane.c
···
40
40
#include <drm/drm_gem.h>
41
41
#include <drm/drm_gem_atomic_helper.h>
42
42
43
+
#include "i915_drv.h"
43
44
#include "i915_config.h"
44
45
#include "i9xx_plane_regs.h"
45
46
#include "intel_atomic_plane.h"
···
208
207
fb->format->cpp[color_plane];
209
208
}
210
209
211
-
static bool
212
-
use_min_ddb(const struct intel_crtc_state *crtc_state,
213
-
struct intel_plane *plane)
214
-
{
215
-
struct drm_i915_private *i915 = to_i915(plane->base.dev);
216
-
217
-
return DISPLAY_VER(i915) >= 13 &&
218
-
crtc_state->uapi.async_flip &&
219
-
plane->async_flip;
220
-
}
221
-
222
210
static unsigned int
223
211
intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
224
212
const struct intel_plane_state *plane_state,
···
215
225
{
216
226
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
217
227
const struct drm_framebuffer *fb = plane_state->hw.fb;
218
-
int width, height;
219
228
unsigned int rel_data_rate;
229
+
int width, height;
220
230
221
231
if (plane->id == PLANE_CURSOR)
222
232
return 0;
223
233
224
234
if (!plane_state->uapi.visible)
225
-
return 0;
226
-
227
-
/*
228
-
* We calculate extra ddb based on ratio plane rate/total data rate
229
-
* in case, in some cases we should not allocate extra ddb for the plane,
230
-
* so do not count its data rate, if this is the case.
231
-
*/
232
-
if (use_min_ddb(crtc_state, plane))
233
235
return 0;
234
236
235
237
/*
···
238
256
height /= 2;
239
257
}
240
258
241
-
rel_data_rate = width * height * fb->format->cpp[color_plane];
259
+
rel_data_rate =
260
+
skl_plane_relative_data_rate(crtc_state, plane, width, height,
261
+
fb->format->cpp[color_plane]);
262
+
if (!rel_data_rate)
263
+
return 0;
242
264
243
265
return intel_adjusted_rate(&plane_state->uapi.src,
244
266
&plane_state->uapi.dst,
+1
drivers/gpu/drm/i915/display/intel_backlight.c
+1
drivers/gpu/drm/i915/display/intel_backlight.c
+2
-1
drivers/gpu/drm/i915/display/intel_bw.c
+2
-1
drivers/gpu/drm/i915/display/intel_bw.c
···
1447
1447
1448
1448
int intel_bw_init(struct drm_i915_private *i915)
1449
1449
{
1450
+
struct intel_display *display = &i915->display;
1450
1451
struct intel_bw_state *state;
1451
1452
1452
1453
state = kzalloc(sizeof(*state), GFP_KERNEL);
1453
1454
if (!state)
1454
1455
return -ENOMEM;
1455
1456
1456
-
intel_atomic_global_obj_init(i915, &i915->display.bw.obj,
1457
+
intel_atomic_global_obj_init(display, &display->bw.obj,
1457
1458
&state->base, &intel_bw_funcs);
1458
1459
1459
1460
/*
+2
-2
drivers/gpu/drm/i915/display/intel_cdclk.c
+2
-2
drivers/gpu/drm/i915/display/intel_cdclk.c
···
29
29
#include "soc/intel_dram.h"
30
30
31
31
#include "hsw_ips.h"
32
+
#include "i915_drv.h"
32
33
#include "i915_reg.h"
33
34
#include "intel_atomic.h"
34
35
#include "intel_atomic_plane.h"
···
3217
3216
3218
3217
int intel_cdclk_init(struct intel_display *display)
3219
3218
{
3220
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
3221
3219
struct intel_cdclk_state *cdclk_state;
3222
3220
3223
3221
cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
3224
3222
if (!cdclk_state)
3225
3223
return -ENOMEM;
3226
3224
3227
-
intel_atomic_global_obj_init(dev_priv, &display->cdclk.obj,
3225
+
intel_atomic_global_obj_init(display, &display->cdclk.obj,
3228
3226
&cdclk_state->base, &intel_cdclk_funcs);
3229
3227
3230
3228
return 0;
+1
drivers/gpu/drm/i915/display/intel_color.c
+1
drivers/gpu/drm/i915/display/intel_color.c
+1
drivers/gpu/drm/i915/display/intel_combo_phy.c
+1
drivers/gpu/drm/i915/display/intel_combo_phy.c
+2
drivers/gpu/drm/i915/display/intel_crt_regs.h
+2
drivers/gpu/drm/i915/display/intel_crt_regs.h
+1
drivers/gpu/drm/i915/display/intel_crtc.c
+1
drivers/gpu/drm/i915/display/intel_crtc.c
+1
drivers/gpu/drm/i915/display/intel_cursor.c
+1
drivers/gpu/drm/i915/display/intel_cursor.c
+6
-8
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+6
-8
drivers/gpu/drm/i915/display/intel_cx0_phy.c
···
5
5
6
6
#include <linux/log2.h>
7
7
#include <linux/math64.h>
8
+
9
+
#include "i915_drv.h"
8
10
#include "i915_reg.h"
9
11
#include "intel_cx0_phy.h"
10
12
#include "intel_cx0_phy_regs.h"
···
2117
2115
0, C10_VDR_CTRL_MSGBUS_ACCESS,
2118
2116
MB_WRITE_COMMITTED);
2119
2117
2120
-
/* Custom width needs to be programmed to 0 for both the phy lanes */
2121
-
intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH,
2122
-
C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10,
2123
-
MB_WRITE_COMMITTED);
2124
-
intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
2125
-
0, C10_VDR_CTRL_UPDATE_CFG,
2126
-
MB_WRITE_COMMITTED);
2127
-
2128
2118
/* Program the pll values only for the master lane */
2129
2119
for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
2130
2120
intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i),
···
2126
2132
intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);
2127
2133
intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED);
2128
2134
2135
+
/* Custom width needs to be programmed to 0 for both the phy lanes */
2136
+
intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH,
2137
+
C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10,
2138
+
MB_WRITE_COMMITTED);
2129
2139
intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),
2130
2140
0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,
2131
2141
MB_WRITE_COMMITTED);
+5
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+5
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
···
9
9
#include "i915_reg_defs.h"
10
10
#include "intel_display_limits.h"
11
11
12
+
/* DDI Buffer Control */
13
+
#define _DDI_CLK_VALFREQ_A 0x64030
14
+
#define _DDI_CLK_VALFREQ_B 0x64130
15
+
#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
16
+
12
17
/*
13
18
* Wrapper macro to convert from port number to the index used in some of the
14
19
* registers. For Display version 20 and above it converts the port number to a
+145
-40
drivers/gpu/drm/i915/display/intel_ddi.c
+145
-40
drivers/gpu/drm/i915/display/intel_ddi.c
···
28
28
#include <linux/iopoll.h>
29
29
#include <linux/string_helpers.h>
30
30
31
+
#include <drm/display/drm_dp_helper.h>
31
32
#include <drm/display/drm_scdc_helper.h>
32
33
#include <drm/drm_privacy_screen_consumer.h>
33
34
···
562
561
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
563
562
temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
564
563
temp |= (crtc_state->fdi_lanes - 1) << 1;
565
-
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
564
+
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
565
+
intel_dp_is_uhbr(crtc_state)) {
566
566
if (intel_dp_is_uhbr(crtc_state))
567
567
temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
568
568
else
···
658
656
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
659
657
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
660
658
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
659
+
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
661
660
u32 ctl;
662
661
663
662
if (DISPLAY_VER(dev_priv) >= 11)
···
678
675
TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
679
676
680
677
if (DISPLAY_VER(dev_priv) >= 12) {
681
-
if (!intel_dp_mst_is_master_trans(crtc_state)) {
678
+
if (!intel_dp_mst_is_master_trans(crtc_state) ||
679
+
(!is_mst && intel_dp_is_uhbr(crtc_state))) {
682
680
ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
683
681
TRANS_DDI_MODE_SELECT_MASK);
684
682
}
···
789
785
intel_wakeref_t wakeref;
790
786
enum pipe p;
791
787
u32 tmp;
792
-
u8 mst_pipe_mask;
788
+
u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0;
793
789
794
790
*pipe_mask = 0;
795
791
*is_dp_mst = false;
···
826
822
goto out;
827
823
}
828
824
829
-
mst_pipe_mask = 0;
830
825
for_each_pipe(dev_priv, p) {
831
826
enum transcoder cpu_transcoder = (enum transcoder)p;
832
827
u32 port_mask, ddi_select, ddi_mode;
···
854
851
855
852
ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK;
856
853
857
-
if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST ||
858
-
(ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)))
854
+
if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)
859
855
mst_pipe_mask |= BIT(p);
856
+
else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))
857
+
dp128b132b_pipe_mask |= BIT(p);
860
858
861
859
*pipe_mask |= BIT(p);
862
860
}
···
866
862
drm_dbg_kms(&dev_priv->drm,
867
863
"No pipe for [ENCODER:%d:%s] found\n",
868
864
encoder->base.base.id, encoder->base.name);
865
+
866
+
if (!mst_pipe_mask && dp128b132b_pipe_mask) {
867
+
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
868
+
869
+
/*
870
+
* If we don't have 8b/10b MST, but have more than one
871
+
* transcoder in 128b/132b mode, we know it must be 128b/132b
872
+
* MST.
873
+
*
874
+
* Otherwise, we fall back to checking the current MST
875
+
* state. It's not accurate for hardware takeover at probe, but
876
+
* we don't expect MST to have been enabled at that point, and
877
+
* can assume it's SST.
878
+
*/
879
+
if (hweight8(dp128b132b_pipe_mask) > 1 || intel_dp->is_mst)
880
+
mst_pipe_mask = dp128b132b_pipe_mask;
881
+
}
869
882
870
883
if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
871
884
drm_dbg_kms(&dev_priv->drm,
···
894
873
895
874
if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
896
875
drm_dbg_kms(&dev_priv->drm,
897
-
"Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
876
+
"Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n",
898
877
encoder->base.base.id, encoder->base.name,
899
-
*pipe_mask, mst_pipe_mask);
878
+
*pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask);
900
879
else
901
880
*is_dp_mst = mst_pipe_mask;
902
881
···
2555
2534
static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
2556
2535
const struct intel_crtc_state *crtc_state)
2557
2536
{
2558
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2537
+
struct intel_display *display = to_intel_display(encoder);
2559
2538
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2560
2539
enum port port = encoder->port;
2561
-
u32 val;
2540
+
u32 val = 0;
2562
2541
2563
-
val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port));
2564
-
val &= ~XELPDP_PORT_WIDTH_MASK;
2565
2542
val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
2566
2543
2567
-
val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK;
2568
2544
if (intel_dp_is_uhbr(crtc_state))
2569
2545
val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
2570
2546
else
···
2570
2552
if (dig_port->lane_reversal)
2571
2553
val |= XELPDP_PORT_REVERSAL;
2572
2554
2573
-
intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val);
2555
+
intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
2556
+
XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK,
2557
+
val);
2574
2558
}
2575
2559
2576
2560
static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
···
2594
2574
{
2595
2575
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2596
2576
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2577
+
int ret;
2597
2578
2598
2579
intel_dp_set_link_params(intel_dp,
2599
2580
crtc_state->port_clock,
···
2689
2668
/* 6.o Configure and enable FEC if needed */
2690
2669
intel_ddi_enable_fec(encoder, crtc_state);
2691
2670
2671
+
/* 7.a 128b/132b SST. */
2672
+
if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
2673
+
/* VCPID 1, start slot 0 for 128b/132b, tu slots */
2674
+
ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
2675
+
if (ret < 0)
2676
+
intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
2677
+
}
2678
+
2692
2679
if (!is_mst)
2693
2680
intel_dsc_dp_pps_write(encoder, crtc_state);
2694
2681
}
···
2710
2681
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2711
2682
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2712
2683
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2684
+
int ret;
2713
2685
2714
2686
intel_dp_set_link_params(intel_dp,
2715
2687
crtc_state->port_clock,
···
2836
2806
2837
2807
/* 7.l Configure and enable FEC if needed */
2838
2808
intel_ddi_enable_fec(encoder, crtc_state);
2809
+
2810
+
if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
2811
+
/* VCPID 1, start slot 0 for 128b/132b, tu slots */
2812
+
ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
2813
+
if (ret < 0)
2814
+
intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
2815
+
}
2839
2816
2840
2817
if (!is_mst)
2841
2818
intel_dsc_dp_pps_write(encoder, crtc_state);
···
3218
3181
{
3219
3182
struct intel_display *display = to_intel_display(encoder);
3220
3183
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3184
+
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3221
3185
struct intel_crtc *pipe_crtc;
3186
+
bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI);
3222
3187
int i;
3223
3188
3224
3189
for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
···
3231
3192
}
3232
3193
3233
3194
intel_disable_transcoder(old_crtc_state);
3195
+
3196
+
/* 128b/132b SST */
3197
+
if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) {
3198
+
/* VCPID 1, start slot 0 for 128b/132b, clear */
3199
+
drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0);
3200
+
3201
+
intel_ddi_clear_act_sent(encoder, old_crtc_state);
3202
+
3203
+
intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder),
3204
+
TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
3205
+
3206
+
intel_ddi_wait_for_act_sent(encoder, old_crtc_state);
3207
+
drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);
3208
+
}
3234
3209
3235
3210
intel_ddi_disable_transcoder_func(old_crtc_state);
3236
3211
···
3508
3455
{
3509
3456
struct intel_display *display = to_intel_display(encoder);
3510
3457
struct intel_crtc *pipe_crtc;
3458
+
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3459
+
bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
3511
3460
int i;
3461
+
3462
+
/* 128b/132b SST */
3463
+
if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
3464
+
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
3465
+
u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
3466
+
3467
+
intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
3468
+
TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
3469
+
intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
3470
+
TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
3471
+
}
3512
3472
3513
3473
intel_ddi_enable_transcoder_func(encoder, crtc_state);
3514
3474
3515
3475
/* Enable/Disable DP2.0 SDP split config before transcoder */
3516
3476
intel_audio_sdp_split_update(crtc_state);
3477
+
3478
+
/* 128b/132b SST */
3479
+
if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
3480
+
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3481
+
3482
+
intel_ddi_clear_act_sent(encoder, crtc_state);
3483
+
3484
+
intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0,
3485
+
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
3486
+
3487
+
intel_ddi_wait_for_act_sent(encoder, crtc_state);
3488
+
drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);
3489
+
}
3517
3490
3518
3491
intel_enable_transcoder(crtc_state);
3519
3492
···
3552
3473
intel_crtc_vblank_on(pipe_crtc_state);
3553
3474
}
3554
3475
3555
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3476
+
if (is_hdmi)
3556
3477
intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state);
3557
3478
else
3558
3479
intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);
···
3718
3639
static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3719
3640
const struct intel_crtc_state *crtc_state)
3720
3641
{
3642
+
struct intel_display *display = to_intel_display(crtc_state);
3721
3643
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3722
3644
struct intel_encoder *encoder = &dig_port->base;
3723
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3724
3645
enum port port = encoder->port;
3725
3646
u32 dp_tp_ctl;
3726
3647
···
3728
3649
* TODO: To train with only a different voltage swing entry is not
3729
3650
* necessary disable and enable port
3730
3651
*/
3731
-
dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3652
+
dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
3732
3653
if (dp_tp_ctl & DP_TP_CTL_ENABLE)
3733
3654
mtl_disable_ddi_buf(encoder, crtc_state);
3734
3655
3735
3656
/* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */
3736
3657
dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3737
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3658
+
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
3659
+
intel_dp_is_uhbr(crtc_state)) {
3738
3660
dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3739
3661
} else {
3740
3662
dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3741
3663
if (crtc_state->enhanced_framing)
3742
3664
dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3743
3665
}
3744
-
intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3745
-
intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3666
+
intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3667
+
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
3746
3668
3747
3669
/* 6.f Enable D2D Link */
3748
3670
mtl_ddi_enable_d2d(encoder);
···
3756
3676
3757
3677
/* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
3758
3678
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3759
-
if (DISPLAY_VER(dev_priv) >= 20)
3679
+
if (DISPLAY_VER(display) >= 20)
3760
3680
intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
3761
3681
3762
-
intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3763
-
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3682
+
intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP);
3683
+
intel_de_posting_read(display, DDI_BUF_CTL(port));
3764
3684
3765
3685
/* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
3766
3686
intel_wait_ddi_buf_active(encoder);
···
3795
3715
}
3796
3716
3797
3717
dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3798
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3718
+
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
3719
+
intel_dp_is_uhbr(crtc_state)) {
3799
3720
dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3800
3721
} else {
3801
3722
dp_tp_ctl |= DP_TP_CTL_MODE_SST;
···
4051
3970
crtc_state->lane_count =
4052
3971
((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4053
3972
3973
+
if (DISPLAY_VER(display) >= 12 &&
3974
+
(ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)
3975
+
crtc_state->mst_master_transcoder =
3976
+
REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
3977
+
4054
3978
intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
4055
3979
intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);
4056
3980
···
4150
4064
intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl);
4151
4065
} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) {
4152
4066
intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl);
4153
-
} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST ||
4154
-
(ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))) {
4067
+
} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) {
4155
4068
intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl);
4069
+
} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {
4070
+
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4071
+
4072
+
/*
4073
+
* If this is true, we know we're being called from mst stream
4074
+
* encoder's ->get_config().
4075
+
*/
4076
+
if (intel_dp->is_mst)
4077
+
intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl);
4078
+
else
4079
+
intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl);
4156
4080
}
4157
4081
}
4158
4082
···
4638
4542
.late_register = intel_ddi_encoder_late_register,
4639
4543
};
4640
4544
4641
-
static struct intel_connector *
4642
-
intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4545
+
static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4643
4546
{
4644
4547
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
4645
4548
struct intel_connector *connector;
···
4646
4551
4647
4552
connector = intel_connector_alloc();
4648
4553
if (!connector)
4649
-
return NULL;
4554
+
return -ENOMEM;
4650
4555
4651
4556
dig_port->dp.output_reg = DDI_BUF_CTL(port);
4652
4557
if (DISPLAY_VER(i915) >= 14)
···
4661
4566
4662
4567
if (!intel_dp_init_connector(dig_port, connector)) {
4663
4568
kfree(connector);
4664
-
return NULL;
4569
+
return -EINVAL;
4665
4570
}
4666
4571
4667
4572
if (dig_port->base.type == INTEL_OUTPUT_EDP) {
···
4677
4582
}
4678
4583
}
4679
4584
4680
-
return connector;
4585
+
return 0;
4681
4586
}
4682
4587
4683
4588
static int intel_hdmi_reset_link(struct intel_encoder *encoder,
···
4843
4748
return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4844
4749
}
4845
4750
4846
-
static struct intel_connector *
4847
-
intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4751
+
static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4848
4752
{
4849
4753
struct intel_connector *connector;
4850
4754
enum port port = dig_port->base.port;
4851
4755
4852
4756
connector = intel_connector_alloc();
4853
4757
if (!connector)
4854
-
return NULL;
4758
+
return -ENOMEM;
4855
4759
4856
4760
dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4857
-
intel_hdmi_init_connector(dig_port, connector);
4858
4761
4859
-
return connector;
4762
+
if (!intel_hdmi_init_connector(dig_port, connector)) {
4763
+
/*
4764
+
* HDMI connector init failures may just mean conflicting DDC
4765
+
* pins or not having enough lanes. Handle them gracefully, but
4766
+
* don't fail the entire DDI init.
4767
+
*/
4768
+
dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG;
4769
+
kfree(connector);
4770
+
}
4771
+
4772
+
return 0;
4860
4773
}
4861
4774
4862
4775
static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
···
5019
4916
5020
4917
static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
5021
4918
{
5022
-
intel_dp_encoder_shutdown(encoder);
5023
-
intel_hdmi_encoder_shutdown(encoder);
4919
+
if (intel_encoder_is_dp(encoder))
4920
+
intel_dp_encoder_shutdown(encoder);
4921
+
if (intel_encoder_is_hdmi(encoder))
4922
+
intel_hdmi_encoder_shutdown(encoder);
5024
4923
}
5025
4924
5026
4925
static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder)
···
5411
5306
intel_infoframe_init(dig_port);
5412
5307
5413
5308
if (init_dp) {
5414
-
if (!intel_ddi_init_dp_connector(dig_port))
5309
+
if (intel_ddi_init_dp_connector(dig_port))
5415
5310
goto err;
5416
5311
5417
5312
dig_port->hpd_pulse = intel_dp_hpd_pulse;
···
5425
5320
* but leave it just in case we have some really bad VBTs...
5426
5321
*/
5427
5322
if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
5428
-
if (!intel_ddi_init_hdmi_connector(dig_port))
5323
+
if (intel_ddi_init_hdmi_connector(dig_port))
5429
5324
goto err;
5430
5325
}
5431
5326
+5
-3
drivers/gpu/drm/i915/display/intel_de.h
+5
-3
drivers/gpu/drm/i915/display/intel_de.h
···
6
6
#ifndef __INTEL_DE_H__
7
7
#define __INTEL_DE_H__
8
8
9
-
#include "i915_drv.h"
10
-
#include "i915_trace.h"
9
+
#include "intel_display_conversion.h"
10
+
#include "intel_display_core.h"
11
+
#include "intel_dmc_wl.h"
11
12
#include "intel_dsb.h"
12
13
#include "intel_uncore.h"
14
+
#include "intel_uncore_trace.h"
13
15
14
16
static inline struct intel_uncore *__to_uncore(struct intel_display *display)
15
17
{
16
-
return &to_i915(display->drm)->uncore;
18
+
return to_intel_uncore(display->drm);
17
19
}
18
20
19
21
static inline u32
+3
-3
drivers/gpu/drm/i915/display/intel_display.c
+3
-3
drivers/gpu/drm/i915/display/intel_display.c
···
8156
8156
intel_lvds_init(dev_priv);
8157
8157
intel_crt_init(display);
8158
8158
8159
-
dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
8159
+
dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);
8160
8160
8161
8161
if (ilk_has_edp_a(dev_priv))
8162
8162
g4x_dp_init(dev_priv, DP_A, PORT_A);
···
8202
8202
* trust the port type the VBT declares as we've seen at least
8203
8203
* HDMI ports that the VBT claim are DP or eDP.
8204
8204
*/
8205
-
has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
8205
+
has_edp = intel_dp_is_port_edp(display, PORT_B);
8206
8206
has_port = intel_bios_is_port_present(display, PORT_B);
8207
8207
if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
8208
8208
has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
8209
8209
if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
8210
8210
g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
8211
8211
8212
-
has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
8212
+
has_edp = intel_dp_is_port_edp(display, PORT_C);
8213
8213
has_port = intel_bios_is_port_present(display, PORT_C);
8214
8214
if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
8215
8215
has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
+14
drivers/gpu/drm/i915/display/intel_display_conversion.c
+14
drivers/gpu/drm/i915/display/intel_display_conversion.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/* Copyright © 2024 Intel Corporation */
3
+
4
+
#include "i915_drv.h"
5
+
6
+
struct intel_display *__i915_to_display(struct drm_i915_private *i915)
7
+
{
8
+
return &i915->display;
9
+
}
10
+
11
+
struct intel_display *__drm_to_display(struct drm_device *drm)
12
+
{
13
+
return __i915_to_display(to_i915(drm));
14
+
}
+8
-2
drivers/gpu/drm/i915/display/intel_display_conversion.h
+8
-2
drivers/gpu/drm/i915/display/intel_display_conversion.h
···
8
8
#ifndef __INTEL_DISPLAY_CONVERSION__
9
9
#define __INTEL_DISPLAY_CONVERSION__
10
10
11
+
struct drm_device;
12
+
struct drm_i915_private;
13
+
struct intel_display;
14
+
15
+
struct intel_display *__i915_to_display(struct drm_i915_private *i915);
16
+
struct intel_display *__drm_to_display(struct drm_device *drm);
11
17
/*
12
18
* Transitional macro to optionally convert struct drm_i915_private * to struct
13
19
* intel_display *, also accepting the latter.
14
20
*/
15
21
#define __to_intel_display(p) \
16
22
_Generic(p, \
17
-
const struct drm_i915_private *: (&((const struct drm_i915_private *)(p))->display), \
18
-
struct drm_i915_private *: (&((struct drm_i915_private *)(p))->display), \
23
+
const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(p)), \
24
+
struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(p)), \
19
25
const struct intel_display *: (p), \
20
26
struct intel_display *: (p))
21
27
+4
drivers/gpu/drm/i915/display/intel_display_debugfs.c
+4
drivers/gpu/drm/i915/display/intel_display_debugfs.c
···
11
11
#include <drm/drm_fourcc.h>
12
12
13
13
#include "hsw_ips.h"
14
+
#include "i915_drv.h"
14
15
#include "i915_irq.h"
15
16
#include "i915_reg.h"
17
+
#include "i9xx_wm_regs.h"
16
18
#include "intel_alpm.h"
17
19
#include "intel_bo.h"
18
20
#include "intel_crtc.h"
···
1015
1013
DP_DSC_YCbCr444)));
1016
1014
seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
1017
1015
drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd));
1016
+
seq_printf(m, "DSC_Sink_Max_Slice_Count: %d\n",
1017
+
drm_dp_dsc_sink_max_slice_count((connector->dp.dsc_dpcd), intel_dp_is_edp(intel_dp)));
1018
1018
seq_printf(m, "Force_DSC_Enable: %s\n",
1019
1019
str_yes_no(intel_dp->force_dsc_en));
1020
1020
if (!intel_dp_is_edp(intel_dp))
+2
-1
drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
+2
-1
drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
+6
-11
drivers/gpu/drm/i915/display/intel_display_driver.c
+6
-11
drivers/gpu/drm/i915/display/intel_display_driver.c
···
163
163
164
164
static void intel_mode_config_cleanup(struct intel_display *display)
165
165
{
166
-
struct drm_i915_private *i915 = to_i915(display->drm);
167
-
168
-
intel_atomic_global_obj_cleanup(i915);
166
+
intel_atomic_global_obj_cleanup(display);
169
167
drm_mode_config_cleanup(display->drm);
170
168
}
171
169
···
231
233
if (ret < 0)
232
234
goto cleanup_vga;
233
235
234
-
intel_pmdemand_init_early(i915);
236
+
intel_pmdemand_init_early(display);
235
237
236
238
intel_power_domains_init_hw(display, false);
237
239
···
263
265
if (ret)
264
266
goto cleanup_vga_client_pw_domain_dmc;
265
267
266
-
ret = intel_pmdemand_init(i915);
268
+
ret = intel_pmdemand_init(display);
267
269
if (ret)
268
270
goto cleanup_vga_client_pw_domain_dmc;
269
271
···
571
573
/* part #1: call before irq uninstall */
572
574
void intel_display_driver_remove(struct intel_display *display)
573
575
{
574
-
struct drm_i915_private *i915 = to_i915(display->drm);
575
-
576
576
if (!HAS_DISPLAY(display))
577
577
return;
578
578
···
583
587
* fbdev after it's finalized. MST will be destroyed later as part of
584
588
* drm_mode_config_cleanup()
585
589
*/
586
-
intel_dp_mst_suspend(i915);
590
+
intel_dp_mst_suspend(display);
587
591
}
588
592
589
593
/* part #2: call after irq uninstall */
···
668
672
*/
669
673
int intel_display_driver_suspend(struct intel_display *display)
670
674
{
671
-
struct drm_i915_private *i915 = to_i915(display->drm);
672
675
struct drm_atomic_state *state;
673
676
int ret;
674
677
···
685
690
/* ensure all DPT VMAs have been unpinned for intel_dpt_suspend() */
686
691
flush_workqueue(display->wq.cleanup);
687
692
688
-
intel_dp_mst_suspend(i915);
693
+
intel_dp_mst_suspend(display);
689
694
690
695
return ret;
691
696
}
···
742
747
return;
743
748
744
749
/* MST sideband requires HPD interrupts enabled */
745
-
intel_dp_mst_resume(i915);
750
+
intel_dp_mst_resume(display);
746
751
747
752
display->restore.modeset_state = NULL;
748
753
if (state)
+6
-1
drivers/gpu/drm/i915/display/intel_display_params.c
+6
-1
drivers/gpu/drm/i915/display/intel_display_params.c
···
3
3
* Copyright © 2023 Intel Corporation
4
4
*/
5
5
6
+
#include <linux/moduleparam.h>
7
+
#include <linux/slab.h>
8
+
#include <linux/string_choices.h>
9
+
10
+
#include <drm/drm_print.h>
11
+
6
12
#include "intel_display_params.h"
7
-
#include "i915_drv.h"
8
13
9
14
#define intel_display_param_named(name, T, perm, desc) \
10
15
module_param_named(name, intel_display_modparams.name, T, perm); \
+2
-2
drivers/gpu/drm/i915/display/intel_display_power.c
+2
-2
drivers/gpu/drm/i915/display/intel_display_power.c
···
1103
1103
slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices;
1104
1104
1105
1105
if (DISPLAY_VER(display) >= 14)
1106
-
intel_pmdemand_program_dbuf(dev_priv, slices_mask);
1106
+
intel_pmdemand_program_dbuf(display, slices_mask);
1107
1107
1108
1108
/*
1109
1109
* Just power up at least 1 slice, we will
···
1119
1119
gen9_dbuf_slices_update(dev_priv, 0);
1120
1120
1121
1121
if (DISPLAY_VER(display) >= 14)
1122
-
intel_pmdemand_program_dbuf(dev_priv, 0);
1122
+
intel_pmdemand_program_dbuf(display, 0);
1123
1123
}
1124
1124
1125
1125
static void gen12_dbuf_slices_config(struct intel_display *display)
+2
-4
drivers/gpu/drm/i915/display/intel_display_power_map.c
+2
-4
drivers/gpu/drm/i915/display/intel_display_power_map.c
···
3
3
* Copyright © 2022 Intel Corporation
4
4
*/
5
5
6
-
#include "i915_drv.h"
7
6
#include "i915_reg.h"
8
-
9
-
#include "vlv_sideband_reg.h"
10
-
7
+
#include "intel_display_core.h"
11
8
#include "intel_display_power_map.h"
12
9
#include "intel_display_power_well.h"
13
10
#include "intel_display_types.h"
11
+
#include "vlv_sideband_reg.h"
14
12
15
13
#define __LIST_INLINE_ELEMS(__elem_type, ...) \
16
14
((__elem_type[]) { __VA_ARGS__ })
+3
-1
drivers/gpu/drm/i915/display/intel_display_snapshot.c
+3
-1
drivers/gpu/drm/i915/display/intel_display_snapshot.c
+1
-1
drivers/gpu/drm/i915/display/intel_display_trace.h
+1
-1
drivers/gpu/drm/i915/display/intel_display_trace.h
+23
-3
drivers/gpu/drm/i915/display/intel_display_types.h
+23
-3
drivers/gpu/drm/i915/display/intel_display_types.h
···
45
45
#include "i915_vma_types.h"
46
46
#include "intel_bios.h"
47
47
#include "intel_display.h"
48
+
#include "intel_display_conversion.h"
48
49
#include "intel_display_limits.h"
49
50
#include "intel_display_power.h"
50
51
#include "intel_dpll_mgr.h"
···
781
780
u8 lines;
782
781
bool enable;
783
782
bool ignore_lines;
783
+
bool auto_min_alloc_wm_enable;
784
784
bool can_sagv;
785
785
};
786
786
···
876
874
struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
877
875
/* pre-icl: for planar Y */
878
876
struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
877
+
878
+
/*
879
+
* xe3: Minimum amount of display blocks and minimum
880
+
* sagv allocation required for async flip
881
+
*/
882
+
u16 plane_min_ddb[I915_MAX_PLANES];
883
+
u16 plane_interim_ddb[I915_MAX_PLANES];
879
884
} skl;
880
885
881
886
struct {
···
1159
1150
bool crc_enabled;
1160
1151
1161
1152
bool double_wide;
1162
-
1163
-
int pbn;
1164
1153
1165
1154
struct intel_crtc_scaler_state scaler_state;
1166
1155
···
1966
1959
}
1967
1960
}
1968
1961
1962
+
static inline bool intel_encoder_is_hdmi(struct intel_encoder *encoder)
1963
+
{
1964
+
switch (encoder->type) {
1965
+
case INTEL_OUTPUT_HDMI:
1966
+
return true;
1967
+
case INTEL_OUTPUT_DDI:
1968
+
/* See if the HDMI encoder is valid. */
1969
+
return i915_mmio_reg_valid(enc_to_intel_hdmi(encoder)->hdmi_reg);
1970
+
default:
1971
+
return false;
1972
+
}
1973
+
}
1974
+
1969
1975
static inline struct intel_lspcon *
1970
1976
enc_to_intel_lspcon(struct intel_encoder *encoder)
1971
1977
{
···
2119
2099
* intel_display pointer.
2120
2100
*/
2121
2101
#define __drm_device_to_intel_display(p) \
2122
-
((p) ? &to_i915(p)->display : NULL)
2102
+
((p) ? __drm_to_display(p) : NULL)
2123
2103
#define __device_to_intel_display(p) \
2124
2104
__drm_device_to_intel_display(dev_get_drvdata(p))
2125
2105
#define __pci_dev_to_intel_display(p) \
+4
-3
drivers/gpu/drm/i915/display/intel_dmc_wl.c
+4
-3
drivers/gpu/drm/i915/display/intel_dmc_wl.c
···
7
7
8
8
#include <drm/drm_print.h>
9
9
10
+
#include "i915_drv.h"
10
11
#include "i915_reg.h"
11
12
#include "intel_de.h"
12
13
#include "intel_dmc.h"
···
55
54
u32 end;
56
55
};
57
56
58
-
static struct intel_dmc_wl_range powered_off_ranges[] = {
57
+
static const struct intel_dmc_wl_range powered_off_ranges[] = {
59
58
{ .start = 0x60000, .end = 0x7ffff },
60
59
{},
61
60
};
62
61
63
-
static struct intel_dmc_wl_range xe3lpd_dc5_dc6_dmc_ranges[] = {
62
+
static const struct intel_dmc_wl_range xe3lpd_dc5_dc6_dmc_ranges[] = {
64
63
{ .start = 0x45500 }, /* DC_STATE_SEL */
65
64
{ .start = 0x457a0, .end = 0x457b0 }, /* DC*_RESIDENCY_COUNTER */
66
65
{ .start = 0x45504 }, /* DC_STATE_EN */
···
94
93
{},
95
94
};
96
95
97
-
static struct intel_dmc_wl_range xe3lpd_dc3co_dmc_ranges[] = {
96
+
static const struct intel_dmc_wl_range xe3lpd_dc3co_dmc_ranges[] = {
98
97
{ .start = 0x454a0 }, /* CHICKEN_DCPR_4 */
99
98
100
99
{ .start = 0x45504 }, /* DC_STATE_EN */
+601
-556
drivers/gpu/drm/i915/display/intel_dp.c
+601
-556
drivers/gpu/drm/i915/display/intel_dp.c
···
94
94
#include "intel_vrr.h"
95
95
#include "intel_crtc_state_dump.h"
96
96
97
-
#define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
98
-
99
97
/* DP DSC throughput values used for slice count calculations KPixels/s */
100
98
#define DP_DSC_PEAK_PIXEL_RATE 2720000
101
99
#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
···
265
267
266
268
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
267
269
{
270
+
struct intel_display *display = to_intel_display(intel_dp);
268
271
struct intel_connector *connector = intel_dp->attached_connector;
269
272
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
270
273
struct intel_encoder *encoder = &intel_dig_port->base;
···
275
276
if (intel_dp->num_sink_rates)
276
277
return;
277
278
278
-
drm_err(&dp_to_i915(intel_dp)->drm,
279
+
drm_err(display->drm,
279
280
"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
280
281
connector->base.base.id, connector->base.name,
281
282
encoder->base.base.id, encoder->base.name);
···
290
291
291
292
static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
292
293
{
294
+
struct intel_display *display = to_intel_display(intel_dp);
293
295
struct intel_connector *connector = intel_dp->attached_connector;
294
296
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295
297
struct intel_encoder *encoder = &intel_dig_port->base;
···
304
304
return;
305
305
}
306
306
307
-
drm_err(&dp_to_i915(intel_dp)->drm,
307
+
drm_err(display->drm,
308
308
"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
309
309
connector->base.base.id, connector->base.name,
310
310
encoder->base.base.id, encoder->base.name,
···
337
337
338
338
int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
339
339
{
340
-
if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
340
+
struct intel_display *display = to_intel_display(intel_dp);
341
+
342
+
if (drm_WARN_ON(display->drm,
341
343
index < 0 || index >= intel_dp->num_common_rates))
342
344
return 162000;
343
345
···
466
464
467
465
bool intel_dp_has_joiner(struct intel_dp *intel_dp)
468
466
{
467
+
struct intel_display *display = to_intel_display(intel_dp);
469
468
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
470
469
struct intel_encoder *encoder = &intel_dig_port->base;
471
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
472
470
473
471
/* eDP MSO is not compatible with joiner */
474
472
if (intel_dp->mso_link_count)
475
473
return false;
476
474
477
-
return DISPLAY_VER(dev_priv) >= 12 ||
478
-
(DISPLAY_VER(dev_priv) == 11 &&
475
+
return DISPLAY_VER(display) >= 12 ||
476
+
(DISPLAY_VER(display) == 11 &&
479
477
encoder->port != PORT_A);
480
478
}
481
479
···
504
502
505
503
static int mtl_max_source_rate(struct intel_dp *intel_dp)
506
504
{
505
+
struct intel_display *display = to_intel_display(intel_dp);
507
506
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
508
507
509
508
if (intel_encoder_is_c10phy(encoder))
510
509
return 810000;
511
510
512
-
if (DISPLAY_VERx100(to_i915(encoder->base.dev)) == 1401)
511
+
if (DISPLAY_VERx100(display) == 1401)
513
512
return 1350000;
514
513
515
514
return 2000000;
···
564
561
static const int g4x_rates[] = {
565
562
162000, 270000
566
563
};
567
-
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
568
-
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
564
+
struct intel_display *display = to_intel_display(intel_dp);
569
565
const int *source_rates;
570
566
int size, max_rate = 0, vbt_max_rate;
571
567
572
568
/* This should only be done once */
573
-
drm_WARN_ON(&dev_priv->drm,
569
+
drm_WARN_ON(display->drm,
574
570
intel_dp->source_rates || intel_dp->num_source_rates);
575
571
576
-
if (DISPLAY_VER(dev_priv) >= 14) {
577
-
if (IS_BATTLEMAGE(dev_priv)) {
572
+
if (DISPLAY_VER(display) >= 14) {
573
+
if (display->platform.battlemage) {
578
574
source_rates = bmg_rates;
579
575
size = ARRAY_SIZE(bmg_rates);
580
576
} else {
···
581
579
size = ARRAY_SIZE(mtl_rates);
582
580
}
583
581
max_rate = mtl_max_source_rate(intel_dp);
584
-
} else if (DISPLAY_VER(dev_priv) >= 11) {
582
+
} else if (DISPLAY_VER(display) >= 11) {
585
583
source_rates = icl_rates;
586
584
size = ARRAY_SIZE(icl_rates);
587
-
if (IS_DG2(dev_priv))
585
+
if (display->platform.dg2)
588
586
max_rate = dg2_max_source_rate(intel_dp);
589
-
else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
590
-
IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
587
+
else if (display->platform.alderlake_p || display->platform.alderlake_s ||
588
+
display->platform.dg1 || display->platform.rocketlake)
591
589
max_rate = 810000;
592
-
else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
590
+
else if (display->platform.jasperlake || display->platform.elkhartlake)
593
591
max_rate = ehl_max_source_rate(intel_dp);
594
592
else
595
593
max_rate = icl_max_source_rate(intel_dp);
596
-
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
594
+
} else if (display->platform.geminilake || display->platform.broxton) {
597
595
source_rates = bxt_rates;
598
596
size = ARRAY_SIZE(bxt_rates);
599
-
} else if (DISPLAY_VER(dev_priv) == 9) {
597
+
} else if (DISPLAY_VER(display) == 9) {
600
598
source_rates = skl_rates;
601
599
size = ARRAY_SIZE(skl_rates);
602
-
} else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
603
-
IS_BROADWELL(dev_priv)) {
600
+
} else if ((display->platform.haswell && !display->platform.haswell_ulx) ||
601
+
display->platform.broadwell) {
604
602
source_rates = hsw_rates;
605
603
size = ARRAY_SIZE(hsw_rates);
606
604
} else {
···
691
689
692
690
static void intel_dp_link_config_init(struct intel_dp *intel_dp)
693
691
{
694
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
692
+
struct intel_display *display = to_intel_display(intel_dp);
695
693
struct intel_dp_link_config *lc;
696
694
int num_common_lane_configs;
697
695
int i;
698
696
int j;
699
697
700
-
if (drm_WARN_ON(&i915->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))
698
+
if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))
701
699
return;
702
700
703
701
num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;
704
702
705
-
if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates * num_common_lane_configs >
703
+
if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >
706
704
ARRAY_SIZE(intel_dp->link.configs)))
707
705
return;
708
706
···
726
724
727
725
void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)
728
726
{
729
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
727
+
struct intel_display *display = to_intel_display(intel_dp);
730
728
const struct intel_dp_link_config *lc;
731
729
732
-
if (drm_WARN_ON(&i915->drm, idx < 0 || idx >= intel_dp->link.num_configs))
730
+
if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))
733
731
idx = 0;
734
732
735
733
lc = &intel_dp->link.configs[idx];
···
758
756
759
757
static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
760
758
{
761
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
759
+
struct intel_display *display = to_intel_display(intel_dp);
762
760
763
-
drm_WARN_ON(&i915->drm,
761
+
drm_WARN_ON(display->drm,
764
762
!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
765
763
766
764
intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
···
770
768
intel_dp->common_rates);
771
769
772
770
/* Paranoia, there should always be something in common. */
773
-
if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
771
+
if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {
774
772
intel_dp->common_rates[0] = 162000;
775
773
intel_dp->num_common_rates = 1;
776
774
}
···
818
816
}
819
817
820
818
static int
821
-
small_joiner_ram_size_bits(struct drm_i915_private *i915)
819
+
small_joiner_ram_size_bits(struct intel_display *display)
822
820
{
823
-
if (DISPLAY_VER(i915) >= 13)
821
+
if (DISPLAY_VER(display) >= 13)
824
822
return 17280 * 8;
825
-
else if (DISPLAY_VER(i915) >= 11)
823
+
else if (DISPLAY_VER(display) >= 11)
826
824
return 7680 * 8;
827
825
else
828
826
return 6144 * 8;
829
827
}
830
828
831
-
u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
829
+
u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp)
832
830
{
833
831
u32 bits_per_pixel = bpp;
834
832
int i;
835
833
836
834
/* Error out if the max bpp is less than smallest allowed valid bpp */
837
835
if (bits_per_pixel < valid_dsc_bpp[0]) {
838
-
drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
836
+
drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n",
839
837
bits_per_pixel, valid_dsc_bpp[0]);
840
838
return 0;
841
839
}
842
840
843
841
/* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
844
-
if (DISPLAY_VER(i915) >= 13) {
842
+
if (DISPLAY_VER(display) >= 13) {
845
843
bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
846
844
847
845
/*
···
853
851
* DSC enabled.
854
852
*/
855
853
if (bits_per_pixel < 8) {
856
-
drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
854
+
drm_dbg_kms(display->drm,
855
+
"Unsupported BPP %u, min 8\n",
857
856
bits_per_pixel);
858
857
return 0;
859
858
}
···
865
862
if (bits_per_pixel < valid_dsc_bpp[i + 1])
866
863
break;
867
864
}
868
-
drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
865
+
drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n",
869
866
bits_per_pixel, valid_dsc_bpp[i]);
870
867
871
868
bits_per_pixel = valid_dsc_bpp[i];
···
900
897
u32 mode_hdisplay,
901
898
int num_joined_pipes)
902
899
{
903
-
struct drm_i915_private *i915 = to_i915(display->drm);
904
900
u32 max_bpp;
905
901
906
902
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
907
-
max_bpp = small_joiner_ram_size_bits(i915) / mode_hdisplay;
903
+
max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay;
908
904
909
905
max_bpp *= num_joined_pipes;
910
906
···
921
919
}
922
920
923
921
static
924
-
u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
922
+
u32 get_max_compressed_bpp_with_joiner(struct intel_display *display,
925
923
u32 mode_clock, u32 mode_hdisplay,
926
924
int num_joined_pipes)
927
925
{
928
-
struct intel_display *display = to_intel_display(&i915->drm);
929
926
u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);
930
927
931
928
if (num_joined_pipes > 1)
···
936
935
return max_bpp;
937
936
}
938
937
939
-
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
938
+
u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
940
939
u32 link_clock, u32 lane_count,
941
940
u32 mode_clock, u32 mode_hdisplay,
942
941
int num_joined_pipes,
···
978
977
if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
979
978
bits_per_pixel = min_t(u32, bits_per_pixel, 31);
980
979
981
-
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
980
+
drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots "
982
981
"total bw %u pixel clock %u\n",
983
982
bits_per_pixel, timeslots,
984
983
(link_clock * lane_count * 8),
985
984
intel_dp_mode_to_fec_clock(mode_clock));
986
985
987
-
joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
986
+
joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock,
988
987
mode_hdisplay, num_joined_pipes);
989
988
bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
990
989
991
-
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
990
+
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp);
992
991
993
992
return bits_per_pixel;
994
993
}
···
997
996
int mode_clock, int mode_hdisplay,
998
997
int num_joined_pipes)
999
998
{
1000
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
999
+
struct intel_display *display = to_intel_display(connector);
1001
1000
u8 min_slice_count, i;
1002
1001
int max_slice_width;
1003
1002
···
1012
1011
* Due to some DSC engine BW limitations, we need to enable second
1013
1012
* slice and VDSC engine, whenever we approach close enough to max CDCLK
1014
1013
*/
1015
-
if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
1014
+
if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100))
1016
1015
min_slice_count = max_t(u8, min_slice_count, 2);
1017
1016
1018
1017
max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
1019
1018
if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
1020
-
drm_dbg_kms(&i915->drm,
1019
+
drm_dbg_kms(display->drm,
1021
1020
"Unsupported slice width %d by DP DSC Sink device\n",
1022
1021
max_slice_width);
1023
1022
return 0;
···
1057
1056
return test_slice_count;
1058
1057
}
1059
1058
1060
-
drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
1059
+
drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n",
1061
1060
min_slice_count);
1062
1061
return 0;
1063
1062
}
···
1065
1064
static bool source_can_output(struct intel_dp *intel_dp,
1066
1065
enum intel_output_format format)
1067
1066
{
1068
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1067
+
struct intel_display *display = to_intel_display(intel_dp);
1069
1068
1070
1069
switch (format) {
1071
1070
case INTEL_OUTPUT_FORMAT_RGB:
···
1077
1076
* Also, ILK doesn't seem capable of DP YCbCr output.
1078
1077
* The displayed image is severly corrupted. SNB+ is fine.
1079
1078
*/
1080
-
return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
1079
+
return !HAS_GMCH(display) && !display->platform.ironlake;
1081
1080
1082
1081
case INTEL_OUTPUT_FORMAT_YCBCR420:
1083
1082
/* Platform < Gen 11 cannot output YCbCr420 format */
1084
-
return DISPLAY_VER(i915) >= 11;
1083
+
return DISPLAY_VER(display) >= 11;
1085
1084
1086
1085
default:
1087
1086
MISSING_CASE(format);
···
1141
1140
intel_dp_output_format(struct intel_connector *connector,
1142
1141
enum intel_output_format sink_format)
1143
1142
{
1143
+
struct intel_display *display = to_intel_display(connector);
1144
1144
struct intel_dp *intel_dp = intel_attached_dp(connector);
1145
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1146
1145
enum intel_output_format force_dsc_output_format =
1147
1146
intel_dp->force_dsc_output_format;
1148
1147
enum intel_output_format output_format;
···
1153
1152
dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1154
1153
return force_dsc_output_format;
1155
1154
1156
-
drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
1155
+
drm_dbg_kms(display->drm, "Cannot force DSC output format\n");
1157
1156
}
1158
1157
1159
1158
if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
···
1167
1166
else
1168
1167
output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1169
1168
1170
-
drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
1169
+
drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));
1171
1170
1172
1171
return output_format;
1173
1172
}
···
1218
1217
return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1219
1218
}
1220
1219
1221
-
static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1220
+
static bool intel_dp_hdisplay_bad(struct intel_display *display,
1222
1221
int hdisplay)
1223
1222
{
1224
1223
/*
···
1234
1233
*
1235
1234
* TODO: confirm the behaviour on HSW+
1236
1235
*/
1237
-
return hdisplay == 4096 && !HAS_DDI(dev_priv);
1236
+
return hdisplay == 4096 && !HAS_DDI(display);
1238
1237
}
1239
1238
1240
1239
static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
···
1335
1334
int hdisplay, int clock,
1336
1335
int num_joined_pipes)
1337
1336
{
1338
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1337
+
struct intel_display *display = to_intel_display(intel_dp);
1339
1338
int hdisplay_limit;
1340
1339
1341
1340
if (!intel_dp_has_joiner(intel_dp))
···
1343
1342
1344
1343
num_joined_pipes /= 2;
1345
1344
1346
-
hdisplay_limit = DISPLAY_VER(i915) >= 30 ? 6144 : 5120;
1345
+
hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120;
1347
1346
1348
-
return clock > num_joined_pipes * i915->display.cdclk.max_dotclk_freq ||
1347
+
return clock > num_joined_pipes * display->cdclk.max_dotclk_freq ||
1349
1348
hdisplay > num_joined_pipes * hdisplay_limit;
1350
1349
}
1351
1350
···
1371
1370
1372
1371
bool intel_dp_has_dsc(const struct intel_connector *connector)
1373
1372
{
1374
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1373
+
struct intel_display *display = to_intel_display(connector);
1375
1374
1376
-
if (!HAS_DSC(i915))
1375
+
if (!HAS_DSC(display))
1377
1376
return false;
1378
1377
1379
-
if (connector->mst_port && !HAS_DSC_MST(i915))
1378
+
if (connector->mst_port && !HAS_DSC_MST(display))
1380
1379
return false;
1381
1380
1382
1381
if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
···
1393
1392
intel_dp_mode_valid(struct drm_connector *_connector,
1394
1393
struct drm_display_mode *mode)
1395
1394
{
1395
+
struct intel_display *display = to_intel_display(_connector->dev);
1396
1396
struct intel_connector *connector = to_intel_connector(_connector);
1397
1397
struct intel_dp *intel_dp = intel_attached_dp(connector);
1398
1398
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1399
1399
const struct drm_display_mode *fixed_mode;
1400
1400
int target_clock = mode->clock;
1401
1401
int max_rate, mode_rate, max_lanes, max_link_clock;
1402
-
int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
1402
+
int max_dotclk = display->cdclk.max_dotclk_freq;
1403
1403
u16 dsc_max_compressed_bpp = 0;
1404
1404
u8 dsc_slice_count = 0;
1405
1405
enum drm_mode_status status;
···
1433
1431
if (target_clock > max_dotclk)
1434
1432
return MODE_CLOCK_HIGH;
1435
1433
1436
-
if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1434
+
if (intel_dp_hdisplay_bad(display, mode->hdisplay))
1437
1435
return MODE_H_ILLEGAL;
1438
1436
1439
1437
max_link_clock = intel_dp_max_link_rate(intel_dp);
···
1468
1466
true);
1469
1467
} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1470
1468
dsc_max_compressed_bpp =
1471
-
intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1469
+
intel_dp_dsc_get_max_compressed_bpp(display,
1472
1470
max_link_clock,
1473
1471
max_lanes,
1474
1472
target_clock,
···
1486
1484
dsc = dsc_max_compressed_bpp && dsc_slice_count;
1487
1485
}
1488
1486
1489
-
if (intel_dp_joiner_needs_dsc(dev_priv, num_joined_pipes) && !dsc)
1487
+
if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
1490
1488
return MODE_CLOCK_HIGH;
1491
1489
1492
1490
if (mode_rate > max_rate && !dsc)
···
1499
1497
return intel_mode_valid_max_plane_size(dev_priv, mode, num_joined_pipes);
1500
1498
}
1501
1499
1502
-
bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1500
+
bool intel_dp_source_supports_tps3(struct intel_display *display)
1503
1501
{
1504
-
return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1502
+
return DISPLAY_VER(display) >= 9 ||
1503
+
display->platform.broadwell || display->platform.haswell;
1505
1504
}
1506
1505
1507
-
bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1506
+
bool intel_dp_source_supports_tps4(struct intel_display *display)
1508
1507
{
1509
-
return DISPLAY_VER(i915) >= 10;
1508
+
return DISPLAY_VER(display) >= 10;
1510
1509
}
1511
1510
1512
1511
static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem)
···
1572
1569
1573
1570
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1574
1571
{
1575
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1572
+
struct intel_display *display = to_intel_display(intel_dp);
1576
1573
int i = intel_dp_rate_index(intel_dp->sink_rates,
1577
1574
intel_dp->num_sink_rates, rate);
1578
1575
1579
-
if (drm_WARN_ON(&i915->drm, i < 0))
1576
+
if (drm_WARN_ON(display->drm, i < 0))
1580
1577
i = 0;
1581
1578
1582
1579
return i;
···
1606
1603
static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1607
1604
const struct intel_crtc_state *pipe_config)
1608
1605
{
1606
+
struct intel_display *display = to_intel_display(intel_dp);
1609
1607
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1610
-
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1611
1608
1612
-
if (DISPLAY_VER(dev_priv) >= 12)
1609
+
if (DISPLAY_VER(display) >= 12)
1613
1610
return true;
1614
1611
1615
-
if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&
1612
+
if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A &&
1616
1613
!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
1617
1614
return true;
1618
1615
···
1627
1624
drm_dp_sink_supports_fec(connector->dp.fec_capability);
1628
1625
}
1629
1626
1630
-
bool intel_dp_supports_dsc(const struct intel_connector *connector,
1627
+
bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1628
+
const struct intel_connector *connector,
1631
1629
const struct intel_crtc_state *crtc_state)
1632
1630
{
1633
1631
if (!intel_dp_has_dsc(connector))
1634
1632
return false;
1635
1633
1636
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1634
+
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) &&
1635
+
!intel_dp_supports_fec(intel_dp, connector, crtc_state))
1637
1636
return false;
1638
1637
1639
1638
return intel_dsc_source_support(crtc_state);
···
1677
1672
const struct intel_crtc_state *crtc_state,
1678
1673
bool respect_downstream_limits)
1679
1674
{
1680
-
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1681
-
struct intel_connector *intel_connector = intel_dp->attached_connector;
1675
+
struct intel_display *display = to_intel_display(intel_dp);
1676
+
struct intel_connector *connector = intel_dp->attached_connector;
1682
1677
int bpp, bpc;
1683
1678
1684
1679
bpc = crtc_state->pipe_bpp / 3;
···
1700
1695
bpp = bpc * 3;
1701
1696
if (intel_dp_is_edp(intel_dp)) {
1702
1697
/* Get bpp from vbt only for panels that dont have bpp in edid */
1703
-
if (intel_connector->base.display_info.bpc == 0 &&
1704
-
intel_connector->panel.vbt.edp.bpp &&
1705
-
intel_connector->panel.vbt.edp.bpp < bpp) {
1706
-
drm_dbg_kms(&dev_priv->drm,
1698
+
if (connector->base.display_info.bpc == 0 &&
1699
+
connector->panel.vbt.edp.bpp &&
1700
+
connector->panel.vbt.edp.bpp < bpp) {
1701
+
drm_dbg_kms(display->drm,
1707
1702
"clamping bpp for eDP panel to BIOS-provided %i\n",
1708
-
intel_connector->panel.vbt.edp.bpp);
1709
-
bpp = intel_connector->panel.vbt.edp.bpp;
1703
+
connector->panel.vbt.edp.bpp);
1704
+
bpp = connector->panel.vbt.edp.bpp;
1710
1705
}
1711
1706
}
1712
1707
···
1783
1778
return -EINVAL;
1784
1779
}
1785
1780
1786
-
static
1787
-
u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1781
+
int intel_dp_dsc_max_src_input_bpc(struct intel_display *display)
1788
1782
{
1789
1783
/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1790
-
if (DISPLAY_VER(i915) >= 12)
1784
+
if (DISPLAY_VER(display) >= 12)
1791
1785
return 12;
1792
-
if (DISPLAY_VER(i915) == 11)
1786
+
if (DISPLAY_VER(display) == 11)
1793
1787
return 10;
1794
1788
1795
1789
return 0;
···
1797
1793
int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1798
1794
u8 max_req_bpc)
1799
1795
{
1800
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1796
+
struct intel_display *display = to_intel_display(connector);
1801
1797
int i, num_bpc;
1802
1798
u8 dsc_bpc[3] = {};
1803
-
u8 dsc_max_bpc;
1799
+
int dsc_max_bpc;
1804
1800
1805
-
dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1801
+
dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
1806
1802
1807
1803
if (!dsc_max_bpc)
1808
1804
return dsc_max_bpc;
1809
1805
1810
-
dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
1806
+
dsc_max_bpc = min(dsc_max_bpc, max_req_bpc);
1811
1807
1812
1808
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1813
1809
dsc_bpc);
···
1819
1815
return 0;
1820
1816
}
1821
1817
1822
-
static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
1818
+
static int intel_dp_source_dsc_version_minor(struct intel_display *display)
1823
1819
{
1824
-
return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1820
+
return DISPLAY_VER(display) >= 14 ? 2 : 1;
1825
1821
}
1826
1822
1827
1823
static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
···
1855
1851
static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1856
1852
struct intel_crtc_state *crtc_state)
1857
1853
{
1858
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1854
+
struct intel_display *display = to_intel_display(connector);
1859
1855
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1860
1856
int ret;
1861
1857
···
1878
1874
(connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1879
1875
DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1880
1876
vdsc_cfg->dsc_version_minor =
1881
-
min(intel_dp_source_dsc_version_minor(i915),
1877
+
min(intel_dp_source_dsc_version_minor(display),
1882
1878
intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1883
1879
if (vdsc_cfg->convert_rgb)
1884
1880
vdsc_cfg->convert_rgb =
···
1888
1884
vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,
1889
1885
drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));
1890
1886
if (!vdsc_cfg->line_buf_depth) {
1891
-
drm_dbg_kms(&i915->drm,
1887
+
drm_dbg_kms(display->drm,
1892
1888
"DSC Sink Line Buffer Depth invalid\n");
1893
1889
return -EINVAL;
1894
1890
}
···
1903
1899
static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1904
1900
enum intel_output_format output_format)
1905
1901
{
1906
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1902
+
struct intel_display *display = to_intel_display(connector);
1907
1903
u8 sink_dsc_format;
1908
1904
1909
1905
switch (output_format) {
···
1914
1910
sink_dsc_format = DP_DSC_YCbCr444;
1915
1911
break;
1916
1912
case INTEL_OUTPUT_FORMAT_YCBCR420:
1917
-
if (min(intel_dp_source_dsc_version_minor(i915),
1913
+
if (min(intel_dp_source_dsc_version_minor(display),
1918
1914
intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1919
1915
return false;
1920
1916
sink_dsc_format = DP_DSC_YCbCr420_Native;
···
1975
1971
1976
1972
static
1977
1973
u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
1978
-
struct intel_crtc_state *pipe_config,
1974
+
const struct intel_crtc_state *pipe_config,
1979
1975
int bpc)
1980
1976
{
1981
1977
u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
···
2000
1996
return 0;
2001
1997
}
2002
1998
2003
-
int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
1999
+
int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config)
2004
2000
{
2005
2001
/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
2006
2002
switch (pipe_config->output_format) {
···
2018
2014
}
2019
2015
2020
2016
int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
2021
-
struct intel_crtc_state *pipe_config,
2017
+
const struct intel_crtc_state *pipe_config,
2022
2018
int bpc)
2023
2019
{
2024
2020
return intel_dp_dsc_max_sink_compressed_bppx16(connector,
···
2033
2029
2034
2030
static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
2035
2031
{
2036
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2032
+
struct intel_display *display = to_intel_display(intel_dp);
2037
2033
2038
2034
/*
2039
2035
* Forcing DSC and using the platform's max compressed bpp is seen to cause
···
2048
2044
* Max Compressed bpp for Gen 13+ is 27bpp.
2049
2045
* For earlier platform is 23bpp. (Bspec:49259).
2050
2046
*/
2051
-
if (DISPLAY_VER(i915) < 13)
2047
+
if (DISPLAY_VER(display) < 13)
2052
2048
return 23;
2053
2049
else
2054
2050
return 27;
···
2109
2105
int pipe_bpp,
2110
2106
int timeslots)
2111
2107
{
2108
+
struct intel_display *display = to_intel_display(intel_dp);
2112
2109
u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
2113
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2114
2110
u16 compressed_bppx16;
2115
2111
u8 bppx16_step;
2116
2112
int ret;
2117
2113
2118
-
if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
2114
+
if (DISPLAY_VER(display) < 14 || bppx16_incr <= 1)
2119
2115
bppx16_step = 16;
2120
2116
else
2121
2117
bppx16_step = 16 / bppx16_incr;
···
2139
2135
pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
2140
2136
if (intel_dp->force_dsc_fractional_bpp_en &&
2141
2137
fxp_q4_to_frac(compressed_bppx16))
2142
-
drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
2138
+
drm_dbg_kms(display->drm,
2139
+
"Forcing DSC fractional bpp\n");
2143
2140
2144
2141
return 0;
2145
2142
}
···
2155
2150
int pipe_bpp,
2156
2151
int timeslots)
2157
2152
{
2153
+
struct intel_display *display = to_intel_display(intel_dp);
2158
2154
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2159
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2160
-
int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2161
-
int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2155
+
int dsc_min_bpp;
2156
+
int dsc_max_bpp;
2162
2157
int dsc_joiner_max_bpp;
2163
2158
int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
2164
2159
2165
-
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2166
-
dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2167
-
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2168
-
dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
2160
+
dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
2169
2161
2170
-
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2171
-
dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2172
-
pipe_config,
2173
-
pipe_bpp / 3);
2174
-
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2175
-
2176
-
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
2162
+
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock,
2177
2163
adjusted_mode->hdisplay,
2178
2164
num_joined_pipes);
2179
-
dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
2180
-
dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
2165
+
dsc_max_bpp = min(dsc_joiner_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
2181
2166
2182
-
if (DISPLAY_VER(i915) >= 13)
2167
+
if (DISPLAY_VER(display) >= 13)
2183
2168
return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
2184
2169
dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2185
2170
return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
2186
2171
dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2187
2172
}
2188
2173
2189
-
static
2190
-
u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
2174
+
int intel_dp_dsc_min_src_input_bpc(void)
2191
2175
{
2192
2176
/* Min DSC Input BPC for ICL+ is 8 */
2193
-
return HAS_DSC(i915) ? 8 : 0;
2177
+
return 8;
2194
2178
}
2195
2179
2196
2180
static
2197
-
bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
2198
-
struct drm_connector_state *conn_state,
2199
-
struct link_config_limits *limits,
2181
+
bool is_dsc_pipe_bpp_sufficient(struct link_config_limits *limits,
2200
2182
int pipe_bpp)
2201
2183
{
2202
-
u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
2203
-
2204
-
dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
2205
-
dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2206
-
2207
-
dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2208
-
dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2209
-
2210
-
return pipe_bpp >= dsc_min_pipe_bpp &&
2211
-
pipe_bpp <= dsc_max_pipe_bpp;
2184
+
return pipe_bpp >= limits->pipe.min_bpp &&
2185
+
pipe_bpp <= limits->pipe.max_bpp;
2212
2186
}
2213
2187
2214
2188
static
2215
2189
int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2216
-
struct drm_connector_state *conn_state,
2217
2190
struct link_config_limits *limits)
2218
2191
{
2219
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2192
+
struct intel_display *display = to_intel_display(intel_dp);
2220
2193
int forced_bpp;
2221
2194
2222
2195
if (!intel_dp->force_dsc_bpc)
···
2202
2219
2203
2220
forced_bpp = intel_dp->force_dsc_bpc * 3;
2204
2221
2205
-
if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
2206
-
drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
2222
+
if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) {
2223
+
drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n",
2224
+
intel_dp->force_dsc_bpc);
2207
2225
return forced_bpp;
2208
2226
}
2209
2227
2210
-
drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2228
+
drm_dbg_kms(display->drm,
2229
+
"Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2211
2230
intel_dp->force_dsc_bpc);
2212
2231
2213
2232
return 0;
···
2221
2236
struct link_config_limits *limits,
2222
2237
int timeslots)
2223
2238
{
2224
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2225
2239
const struct intel_connector *connector =
2226
2240
to_intel_connector(conn_state->connector);
2227
-
u8 max_req_bpc = conn_state->max_requested_bpc;
2228
-
u8 dsc_max_bpc, dsc_max_bpp;
2229
-
u8 dsc_min_bpc, dsc_min_bpp;
2241
+
int dsc_max_bpp;
2242
+
int dsc_min_bpp;
2230
2243
u8 dsc_bpc[3] = {};
2231
2244
int forced_bpp, pipe_bpp;
2232
2245
int num_bpc, i, ret;
2233
2246
2234
-
forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2247
+
forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
2235
2248
2236
2249
if (forced_bpp) {
2237
2250
ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
···
2240
2257
}
2241
2258
}
2242
2259
2243
-
dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
2244
-
if (!dsc_max_bpc)
2245
-
return -EINVAL;
2246
-
2247
-
dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2248
-
dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2249
-
2250
-
dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2251
-
dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2260
+
dsc_max_bpp = limits->pipe.max_bpp;
2261
+
dsc_min_bpp = limits->pipe.min_bpp;
2252
2262
2253
2263
/*
2254
2264
* Get the maximum DSC bpc that will be supported by any valid
···
2270
2294
struct drm_connector_state *conn_state,
2271
2295
struct link_config_limits *limits)
2272
2296
{
2273
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2297
+
struct intel_display *display = to_intel_display(intel_dp);
2274
2298
struct intel_connector *connector =
2275
2299
to_intel_connector(conn_state->connector);
2276
2300
int pipe_bpp, forced_bpp;
2277
-
int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2278
-
int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2301
+
int dsc_min_bpp;
2302
+
int dsc_max_bpp;
2279
2303
2280
-
forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2304
+
forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
2281
2305
2282
2306
if (forced_bpp) {
2283
2307
pipe_bpp = forced_bpp;
2284
2308
} else {
2285
-
int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
2309
+
int max_bpc = limits->pipe.max_bpp / 3;
2286
2310
2287
2311
/* For eDP use max bpp that can be supported with DSC. */
2288
2312
pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2289
-
if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2290
-
drm_dbg_kms(&i915->drm,
2313
+
if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) {
2314
+
drm_dbg_kms(display->drm,
2291
2315
"Computed BPC is not in DSC BPC limits\n");
2292
2316
return -EINVAL;
2293
2317
}
···
2295
2319
pipe_config->port_clock = limits->max_rate;
2296
2320
pipe_config->lane_count = limits->max_lane_count;
2297
2321
2298
-
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2299
-
dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2300
-
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2301
-
dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
2322
+
dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
2302
2323
2303
-
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2304
-
dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2305
-
pipe_config,
2306
-
pipe_bpp / 3);
2307
-
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2308
-
dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
2324
+
dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
2309
2325
2310
2326
/* Compressed BPP should be less than the Input DSC bpp */
2311
2327
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
···
2310
2342
return 0;
2311
2343
}
2312
2344
2345
+
static void intel_dp_fec_compute_config(struct intel_dp *intel_dp,
2346
+
struct intel_crtc_state *crtc_state)
2347
+
{
2348
+
if (crtc_state->fec_enable)
2349
+
return;
2350
+
2351
+
/*
2352
+
* Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional.
2353
+
* Since, FEC is a bandwidth overhead, continue to not enable it for
2354
+
* eDP. Until, there is a good reason to do so.
2355
+
*/
2356
+
if (intel_dp_is_edp(intel_dp))
2357
+
return;
2358
+
2359
+
if (intel_dp_is_uhbr(crtc_state))
2360
+
return;
2361
+
2362
+
crtc_state->fec_enable = true;
2363
+
}
2364
+
2313
2365
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2314
2366
struct intel_crtc_state *pipe_config,
2315
2367
struct drm_connector_state *conn_state,
···
2337
2349
int timeslots,
2338
2350
bool compute_pipe_bpp)
2339
2351
{
2340
-
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2341
-
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2352
+
struct intel_display *display = to_intel_display(intel_dp);
2342
2353
const struct intel_connector *connector =
2343
2354
to_intel_connector(conn_state->connector);
2344
2355
const struct drm_display_mode *adjusted_mode =
···
2345
2358
int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
2346
2359
int ret;
2347
2360
2348
-
/*
2349
-
* Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional.
2350
-
* Since, FEC is a bandwidth overhead, continue to not enable it for
2351
-
* eDP. Until, there is a good reason to do so.
2352
-
*/
2353
-
pipe_config->fec_enable = pipe_config->fec_enable ||
2354
-
(!intel_dp_is_edp(intel_dp) &&
2355
-
intel_dp_supports_fec(intel_dp, connector, pipe_config) &&
2356
-
!intel_dp_is_uhbr(pipe_config));
2357
-
2358
-
if (!intel_dp_supports_dsc(connector, pipe_config))
2359
-
return -EINVAL;
2361
+
intel_dp_fec_compute_config(intel_dp, pipe_config);
2360
2362
2361
2363
if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2362
2364
return -EINVAL;
···
2364
2388
ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2365
2389
conn_state, limits, timeslots);
2366
2390
if (ret) {
2367
-
drm_dbg_kms(&dev_priv->drm,
2391
+
drm_dbg_kms(display->drm,
2368
2392
"No Valid pipe bpp for given mode ret = %d\n", ret);
2369
2393
return ret;
2370
2394
}
···
2376
2400
drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2377
2401
true);
2378
2402
if (!pipe_config->dsc.slice_count) {
2379
-
drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2403
+
drm_dbg_kms(display->drm,
2404
+
"Unsupported Slice Count %d\n",
2380
2405
pipe_config->dsc.slice_count);
2381
2406
return -EINVAL;
2382
2407
}
···
2390
2413
adjusted_mode->crtc_hdisplay,
2391
2414
num_joined_pipes);
2392
2415
if (!dsc_dp_slice_count) {
2393
-
drm_dbg_kms(&dev_priv->drm,
2416
+
drm_dbg_kms(display->drm,
2394
2417
"Compressed Slice Count not supported\n");
2395
2418
return -EINVAL;
2396
2419
}
···
2414
2437
2415
2438
ret = intel_dp_dsc_compute_params(connector, pipe_config);
2416
2439
if (ret < 0) {
2417
-
drm_dbg_kms(&dev_priv->drm,
2440
+
drm_dbg_kms(display->drm,
2418
2441
"Cannot compute valid DSC parameters for Input Bpp = %d"
2419
2442
"Compressed BPP = " FXP_Q4_FMT "\n",
2420
2443
pipe_config->pipe_bpp,
···
2423
2446
}
2424
2447
2425
2448
pipe_config->dsc.compression_enable = true;
2426
-
drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2449
+
drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "
2427
2450
"Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
2428
2451
pipe_config->pipe_bpp,
2429
2452
FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
···
2432
2455
return 0;
2433
2456
}
2434
2457
2435
-
/**
2436
-
* intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2437
-
* @intel_dp: intel DP
2438
-
* @crtc_state: crtc state
2439
-
* @dsc: DSC compression mode
2440
-
* @limits: link configuration limits
2441
-
*
2442
-
* Calculates the output link min, max bpp values in @limits based on the
2443
-
* pipe bpp range, @crtc_state and @dsc mode.
2444
-
*
2445
-
* Returns %true in case of success.
2458
+
/*
2459
+
* Calculate the output link min, max bpp values in limits based on the pipe bpp
2460
+
* range, crtc_state and dsc mode. Return true on success.
2446
2461
*/
2447
-
bool
2462
+
static bool
2448
2463
intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2464
+
const struct intel_connector *connector,
2449
2465
const struct intel_crtc_state *crtc_state,
2450
2466
bool dsc,
2451
2467
struct link_config_limits *limits)
2452
2468
{
2453
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2469
+
struct intel_display *display = to_intel_display(intel_dp);
2454
2470
const struct drm_display_mode *adjusted_mode =
2455
2471
&crtc_state->hw.adjusted_mode;
2456
2472
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
···
2461
2491
2462
2492
limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);
2463
2493
} else {
2464
-
/*
2465
-
* TODO: set the DSC link limits already here, atm these are
2466
-
* initialized only later in intel_edp_dsc_compute_pipe_bpp() /
2467
-
* intel_dp_dsc_compute_pipe_bpp()
2468
-
*/
2469
-
limits->link.min_bpp_x16 = 0;
2494
+
int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2495
+
int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2496
+
2497
+
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2498
+
dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
2499
+
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2500
+
limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);
2501
+
2502
+
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2503
+
dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2504
+
crtc_state,
2505
+
limits->pipe.max_bpp / 3);
2506
+
dsc_max_bpp = dsc_sink_max_bpp ?
2507
+
min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2508
+
2509
+
max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
2470
2510
}
2471
2511
2472
2512
limits->link.max_bpp_x16 = max_link_bpp_x16;
2473
2513
2474
-
drm_dbg_kms(&i915->drm,
2514
+
drm_dbg_kms(display->drm,
2475
2515
"[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
2476
2516
encoder->base.base.id, encoder->base.name,
2477
2517
crtc->base.base.id, crtc->base.name,
···
2495
2515
return true;
2496
2516
}
2497
2517
2498
-
static bool
2518
+
static void
2519
+
intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp *intel_dp,
2520
+
struct link_config_limits *limits)
2521
+
{
2522
+
struct intel_display *display = to_intel_display(intel_dp);
2523
+
int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc();
2524
+
int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
2525
+
2526
+
limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);
2527
+
limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);
2528
+
}
2529
+
2530
+
bool
2499
2531
intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2500
2532
struct intel_crtc_state *crtc_state,
2501
2533
bool respect_downstream_limits,
2502
2534
bool dsc,
2503
2535
struct link_config_limits *limits)
2504
2536
{
2537
+
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2538
+
2505
2539
limits->min_rate = intel_dp_min_link_rate(intel_dp);
2506
2540
limits->max_rate = intel_dp_max_link_rate(intel_dp);
2507
2541
2508
-
/* FIXME 128b/132b SST support missing */
2509
-
limits->max_rate = min(limits->max_rate, 810000);
2542
+
/* FIXME 128b/132b SST+DSC support missing */
2543
+
if (!is_mst && dsc)
2544
+
limits->max_rate = min(limits->max_rate, 810000);
2510
2545
limits->min_rate = min(limits->min_rate, limits->max_rate);
2511
2546
2512
2547
limits->min_lane_count = intel_dp_min_lane_count(intel_dp);
2513
2548
limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2514
2549
2515
2550
limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2516
-
limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2517
-
respect_downstream_limits);
2518
-
2519
-
if (intel_dp->use_max_params) {
2551
+
if (is_mst) {
2520
2552
/*
2553
+
* FIXME: If all the streams can't fit into the link with their
2554
+
* current pipe_bpp we should reduce pipe_bpp across the board
2555
+
* until things start to fit. Until then we limit to <= 8bpc
2556
+
* since that's what was hardcoded for all MST streams
2557
+
* previously. This hack should be removed once we have the
2558
+
* proper retry logic in place.
2559
+
*/
2560
+
limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
2561
+
} else {
2562
+
limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2563
+
respect_downstream_limits);
2564
+
}
2565
+
2566
+
if (dsc)
2567
+
intel_dp_dsc_compute_pipe_bpp_limits(intel_dp, limits);
2568
+
2569
+
if (is_mst || intel_dp->use_max_params) {
2570
+
/*
2571
+
* For MST we always configure max link bw - the spec doesn't
2572
+
* seem to suggest we should do otherwise.
2573
+
*
2521
2574
* Use the maximum clock and number of lanes the eDP panel
2522
2575
* advertizes being capable of in case the initial fast
2523
2576
* optimal params failed us. The panels are generally
···
2565
2552
intel_dp_test_compute_config(intel_dp, crtc_state, limits);
2566
2553
2567
2554
return intel_dp_compute_config_link_bpp_limits(intel_dp,
2555
+
intel_dp->attached_connector,
2568
2556
crtc_state,
2569
2557
dsc,
2570
2558
limits);
···
2582
2568
return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
2583
2569
}
2584
2570
2585
-
bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915,
2571
+
bool intel_dp_joiner_needs_dsc(struct intel_display *display,
2586
2572
int num_joined_pipes)
2587
2573
{
2588
2574
/*
···
2591
2577
* compression.
2592
2578
* Ultrajoiner always needs compression.
2593
2579
*/
2594
-
return (!HAS_UNCOMPRESSED_JOINER(i915) && num_joined_pipes == 2) ||
2580
+
return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) ||
2595
2581
num_joined_pipes == 4;
2596
2582
}
2597
2583
···
2601
2587
struct drm_connector_state *conn_state,
2602
2588
bool respect_downstream_limits)
2603
2589
{
2604
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2590
+
struct intel_display *display = to_intel_display(encoder);
2605
2591
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2606
2592
struct intel_connector *connector =
2607
2593
to_intel_connector(conn_state->connector);
···
2623
2609
if (num_joined_pipes > 1)
2624
2610
pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
2625
2611
2626
-
joiner_needs_dsc = intel_dp_joiner_needs_dsc(i915, num_joined_pipes);
2612
+
joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
2627
2613
2628
2614
dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2629
2615
!intel_dp_compute_config_limits(intel_dp, pipe_config,
···
2638
2624
*/
2639
2625
ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2640
2626
conn_state, &limits);
2627
+
if (!ret && intel_dp_is_uhbr(pipe_config))
2628
+
ret = intel_dp_mtp_tu_compute_config(intel_dp,
2629
+
pipe_config,
2630
+
pipe_config->pipe_bpp,
2631
+
pipe_config->pipe_bpp,
2632
+
conn_state,
2633
+
0, false);
2641
2634
if (ret)
2642
2635
dsc_needed = true;
2643
2636
}
2644
2637
2638
+
if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) {
2639
+
drm_dbg_kms(display->drm, "DSC required but not available\n");
2640
+
return -EINVAL;
2641
+
}
2642
+
2645
2643
if (dsc_needed) {
2646
-
drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2644
+
drm_dbg_kms(display->drm,
2645
+
"Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2647
2646
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2648
2647
str_yes_no(intel_dp->force_dsc_en));
2649
2648
···
2672
2645
return ret;
2673
2646
}
2674
2647
2675
-
drm_dbg_kms(&i915->drm,
2648
+
drm_dbg_kms(display->drm,
2676
2649
"DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
2677
2650
pipe_config->lane_count, pipe_config->port_clock,
2678
2651
pipe_config->pipe_bpp,
···
2718
2691
}
2719
2692
}
2720
2693
2721
-
static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2722
-
enum port port)
2694
+
static bool intel_dp_port_has_audio(struct intel_display *display, enum port port)
2723
2695
{
2724
-
if (IS_G4X(dev_priv))
2696
+
if (display->platform.g4x)
2725
2697
return false;
2726
-
if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2698
+
if (DISPLAY_VER(display) < 12 && port == PORT_A)
2727
2699
return false;
2728
2700
2729
2701
return true;
···
2732
2706
const struct drm_connector_state *conn_state,
2733
2707
struct drm_dp_vsc_sdp *vsc)
2734
2708
{
2735
-
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2736
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2709
+
struct intel_display *display = to_intel_display(crtc_state);
2737
2710
2738
2711
if (crtc_state->has_panel_replay) {
2739
2712
/*
···
2809
2784
vsc->bpc = crtc_state->pipe_bpp / 3;
2810
2785
2811
2786
/* only RGB pixelformat supports 6 bpc */
2812
-
drm_WARN_ON(&dev_priv->drm,
2787
+
drm_WARN_ON(display->drm,
2813
2788
vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2814
2789
2815
2790
/* all YCbCr are always limited range */
···
2899
2874
struct intel_crtc_state *crtc_state,
2900
2875
const struct drm_connector_state *conn_state)
2901
2876
{
2877
+
struct intel_display *display = to_intel_display(intel_dp);
2902
2878
int ret;
2903
-
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2904
2879
struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2905
2880
2906
2881
if (!conn_state->hdr_output_metadata)
···
2909
2884
ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2910
2885
2911
2886
if (ret) {
2912
-
drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2887
+
drm_dbg_kms(display->drm,
2888
+
"couldn't set HDR metadata in infoframe\n");
2913
2889
return;
2914
2890
}
2915
2891
···
2952
2926
struct intel_crtc_state *pipe_config,
2953
2927
int link_bpp_x16)
2954
2928
{
2929
+
struct intel_display *display = to_intel_display(connector);
2955
2930
struct drm_i915_private *i915 = to_i915(connector->base.dev);
2956
2931
const struct drm_display_mode *downclock_mode =
2957
2932
intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
···
2971
2944
return;
2972
2945
}
2973
2946
2974
-
if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2947
+
if (display->platform.ironlake || display->platform.sandybridge ||
2948
+
display->platform.ivybridge)
2975
2949
pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2976
2950
2977
2951
pipe_config->has_drrs = true;
···
2994
2966
static bool intel_dp_has_audio(struct intel_encoder *encoder,
2995
2967
const struct drm_connector_state *conn_state)
2996
2968
{
2997
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2969
+
struct intel_display *display = to_intel_display(encoder);
2998
2970
const struct intel_digital_connector_state *intel_conn_state =
2999
2971
to_intel_digital_connector_state(conn_state);
3000
2972
struct intel_connector *connector =
3001
2973
to_intel_connector(conn_state->connector);
3002
2974
3003
-
if (!intel_dp_port_has_audio(i915, encoder->port))
2975
+
if (!intel_dp_port_has_audio(display, encoder->port))
3004
2976
return false;
3005
2977
3006
2978
if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
···
3015
2987
struct drm_connector_state *conn_state,
3016
2988
bool respect_downstream_limits)
3017
2989
{
3018
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2990
+
struct intel_display *display = to_intel_display(encoder);
3019
2991
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3020
2992
struct intel_connector *connector = intel_dp->attached_connector;
3021
2993
const struct drm_display_info *info = &connector->base.display_info;
···
3026
2998
ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
3027
2999
3028
3000
if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
3029
-
drm_dbg_kms(&i915->drm,
3001
+
drm_dbg_kms(display->drm,
3030
3002
"YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
3031
3003
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
3032
3004
} else {
···
3110
3082
struct intel_crtc_state *pipe_config,
3111
3083
struct drm_connector_state *conn_state)
3112
3084
{
3113
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3085
+
struct intel_display *display = to_intel_display(encoder);
3114
3086
struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
3115
3087
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
3116
3088
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
···
3135
3107
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
3136
3108
return -EINVAL;
3137
3109
3138
-
if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
3110
+
if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay))
3139
3111
return -EINVAL;
3140
3112
3141
3113
/*
···
3158
3130
pipe_config->limited_color_range =
3159
3131
intel_dp_limited_color_range(pipe_config, conn_state);
3160
3132
3161
-
pipe_config->enhanced_framing =
3162
-
drm_dp_enhanced_frame_cap(intel_dp->dpcd);
3133
+
if (intel_dp_is_uhbr(pipe_config)) {
3134
+
/* 128b/132b SST also needs this */
3135
+
pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;
3136
+
} else {
3137
+
pipe_config->enhanced_framing =
3138
+
drm_dp_enhanced_frame_cap(intel_dp->dpcd);
3139
+
}
3163
3140
3164
3141
if (pipe_config->dsc.compression_enable)
3165
3142
link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
···
3180
3147
pipe_config->splitter.link_count = n;
3181
3148
pipe_config->splitter.pixel_overlap = overlap;
3182
3149
3183
-
drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
3150
+
drm_dbg_kms(display->drm,
3151
+
"MSO link count %d, pixel overlap %d\n",
3184
3152
n, overlap);
3185
3153
3186
3154
adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
···
3195
3161
3196
3162
intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
3197
3163
3198
-
intel_link_compute_m_n(link_bpp_x16,
3199
-
pipe_config->lane_count,
3200
-
adjusted_mode->crtc_clock,
3201
-
pipe_config->port_clock,
3202
-
intel_dp_bw_fec_overhead(pipe_config->fec_enable),
3203
-
&pipe_config->dp_m_n);
3164
+
if (!intel_dp_is_uhbr(pipe_config)) {
3165
+
intel_link_compute_m_n(link_bpp_x16,
3166
+
pipe_config->lane_count,
3167
+
adjusted_mode->crtc_clock,
3168
+
pipe_config->port_clock,
3169
+
intel_dp_bw_fec_overhead(pipe_config->fec_enable),
3170
+
&pipe_config->dp_m_n);
3171
+
}
3204
3172
3205
3173
/* FIXME: abstract this better */
3206
3174
if (pipe_config->splitter.enable)
···
3244
3208
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3245
3209
const struct drm_connector_state *conn_state)
3246
3210
{
3211
+
struct intel_display *display = to_intel_display(crtc_state);
3247
3212
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3248
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3249
3213
3250
3214
if (!intel_dp_is_edp(intel_dp))
3251
3215
return;
3252
3216
3253
-
drm_dbg_kms(&i915->drm, "\n");
3217
+
drm_dbg_kms(display->drm, "\n");
3254
3218
3255
3219
intel_backlight_enable(crtc_state, conn_state);
3256
3220
intel_pps_backlight_on(intel_dp);
···
3260
3224
void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3261
3225
{
3262
3226
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3263
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3227
+
struct intel_display *display = to_intel_display(intel_dp);
3264
3228
3265
3229
if (!intel_dp_is_edp(intel_dp))
3266
3230
return;
3267
3231
3268
-
drm_dbg_kms(&i915->drm, "\n");
3232
+
drm_dbg_kms(display->drm, "\n");
3269
3233
3270
3234
intel_pps_backlight_off(intel_dp);
3271
3235
intel_backlight_disable(old_conn_state);
···
3308
3272
intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3309
3273
bool enable)
3310
3274
{
3311
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
3275
+
struct intel_display *display = to_intel_display(connector);
3312
3276
3313
3277
if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3314
3278
DP_DECOMPRESSION_EN, enable) < 0)
3315
-
drm_dbg_kms(&i915->drm,
3279
+
drm_dbg_kms(display->drm,
3316
3280
"Failed to %s sink decompression state\n",
3317
3281
str_enable_disable(enable));
3318
3282
}
···
3321
3285
intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3322
3286
bool enable)
3323
3287
{
3324
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
3288
+
struct intel_display *display = to_intel_display(connector);
3325
3289
struct drm_dp_aux *aux = connector->port ?
3326
3290
connector->port->passthrough_aux : NULL;
3327
3291
···
3330
3294
3331
3295
if (write_dsc_decompression_flag(aux,
3332
3296
DP_DSC_PASSTHROUGH_EN, enable) < 0)
3333
-
drm_dbg_kms(&i915->drm,
3297
+
drm_dbg_kms(display->drm,
3334
3298
"Failed to %s sink compression passthrough state\n",
3335
3299
str_enable_disable(enable));
3336
3300
}
···
3339
3303
const struct intel_connector *connector,
3340
3304
bool for_get_ref)
3341
3305
{
3342
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
3306
+
struct intel_display *display = to_intel_display(state);
3343
3307
struct drm_connector *_connector_iter;
3344
3308
struct drm_connector_state *old_conn_state;
3345
3309
struct drm_connector_state *new_conn_state;
···
3364
3328
if (!connector_iter->dp.dsc_decompression_enabled)
3365
3329
continue;
3366
3330
3367
-
drm_WARN_ON(&i915->drm,
3331
+
drm_WARN_ON(display->drm,
3368
3332
(for_get_ref && !new_conn_state->crtc) ||
3369
3333
(!for_get_ref && !old_conn_state->crtc));
3370
3334
···
3411
3375
struct intel_connector *connector,
3412
3376
const struct intel_crtc_state *new_crtc_state)
3413
3377
{
3414
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
3378
+
struct intel_display *display = to_intel_display(state);
3415
3379
3416
3380
if (!new_crtc_state->dsc.compression_enable)
3417
3381
return;
3418
3382
3419
-
if (drm_WARN_ON(&i915->drm,
3383
+
if (drm_WARN_ON(display->drm,
3420
3384
!connector->dp.dsc_decompression_aux ||
3421
3385
connector->dp.dsc_decompression_enabled))
3422
3386
return;
···
3442
3406
struct intel_connector *connector,
3443
3407
const struct intel_crtc_state *old_crtc_state)
3444
3408
{
3445
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
3409
+
struct intel_display *display = to_intel_display(state);
3446
3410
3447
3411
if (!old_crtc_state->dsc.compression_enable)
3448
3412
return;
3449
3413
3450
-
if (drm_WARN_ON(&i915->drm,
3414
+
if (drm_WARN_ON(display->drm,
3451
3415
!connector->dp.dsc_decompression_aux ||
3452
3416
!connector->dp.dsc_decompression_enabled))
3453
3417
return;
···
3499
3463
3500
3464
void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3501
3465
{
3466
+
struct intel_display *display = to_intel_display(intel_dp);
3502
3467
struct intel_connector *connector = intel_dp->attached_connector;
3503
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3504
3468
3505
-
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3469
+
drm_dbg_kms(display->drm,
3470
+
"[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3506
3471
connector->base.base.id, connector->base.name,
3507
3472
connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3508
3473
···
3514
3477
/* If the device supports it, try to set the power state appropriately */
3515
3478
void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3516
3479
{
3480
+
struct intel_display *display = to_intel_display(intel_dp);
3517
3481
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3518
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3519
3482
int ret, i;
3520
3483
3521
3484
/* Should have a valid DPCD by this point */
···
3551
3514
}
3552
3515
3553
3516
if (ret != 1)
3554
-
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3517
+
drm_dbg_kms(display->drm,
3518
+
"[ENCODER:%d:%s] Set power to %s failed\n",
3555
3519
encoder->base.base.id, encoder->base.name,
3556
3520
mode == DP_SET_POWER_D0 ? "D0" : "D3");
3557
3521
}
···
3595
3557
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3596
3558
struct intel_crtc_state *crtc_state)
3597
3559
{
3598
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3560
+
struct intel_display *display = to_intel_display(encoder);
3599
3561
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3600
3562
bool fastset = true;
3601
3563
···
3605
3567
*/
3606
3568
if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3607
3569
crtc_state->port_clock) < 0) {
3608
-
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3570
+
drm_dbg_kms(display->drm,
3571
+
"[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3609
3572
encoder->base.base.id, encoder->base.name);
3610
3573
crtc_state->uapi.connectors_changed = true;
3611
3574
fastset = false;
···
3620
3581
* Remove once we have readout for DSC.
3621
3582
*/
3622
3583
if (crtc_state->dsc.compression_enable) {
3623
-
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3584
+
drm_dbg_kms(display->drm,
3585
+
"[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3624
3586
encoder->base.base.id, encoder->base.name);
3625
3587
crtc_state->uapi.mode_changed = true;
3626
3588
fastset = false;
3627
3589
}
3628
3590
3629
3591
if (CAN_PANEL_REPLAY(intel_dp)) {
3630
-
drm_dbg_kms(&i915->drm,
3592
+
drm_dbg_kms(display->drm,
3631
3593
"[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
3632
3594
encoder->base.base.id, encoder->base.name);
3633
3595
crtc_state->uapi.mode_changed = true;
···
3640
3600
3641
3601
static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3642
3602
{
3643
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3603
+
struct intel_display *display = to_intel_display(intel_dp);
3644
3604
3645
3605
/* Clear the cached register set to avoid using stale values */
3646
3606
···
3649
3609
if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3650
3610
intel_dp->pcon_dsc_dpcd,
3651
3611
sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3652
-
drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3612
+
drm_err(display->drm, "Failed to read DPCD register 0x%x\n",
3653
3613
DP_PCON_DSC_ENCODER);
3654
3614
3655
-
drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3615
+
drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3656
3616
(int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3657
3617
}
3658
3618
···
3690
3650
3691
3651
static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3692
3652
{
3693
-
struct intel_connector *intel_connector = intel_dp->attached_connector;
3694
-
struct drm_connector *connector = &intel_connector->base;
3653
+
struct intel_connector *connector = intel_dp->attached_connector;
3654
+
const struct drm_display_info *info = &connector->base.display_info;
3695
3655
int max_frl_rate;
3696
3656
int max_lanes, rate_per_lane;
3697
3657
int max_dsc_lanes, dsc_rate_per_lane;
3698
3658
3699
-
max_lanes = connector->display_info.hdmi.max_lanes;
3700
-
rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
3659
+
max_lanes = info->hdmi.max_lanes;
3660
+
rate_per_lane = info->hdmi.max_frl_rate_per_lane;
3701
3661
max_frl_rate = max_lanes * rate_per_lane;
3702
3662
3703
-
if (connector->display_info.hdmi.dsc_cap.v_1p2) {
3704
-
max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
3705
-
dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
3663
+
if (info->hdmi.dsc_cap.v_1p2) {
3664
+
max_dsc_lanes = info->hdmi.dsc_cap.max_lanes;
3665
+
dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane;
3706
3666
if (max_dsc_lanes && dsc_rate_per_lane)
3707
3667
max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3708
3668
}
···
3724
3684
3725
3685
static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3726
3686
{
3687
+
struct intel_display *display = to_intel_display(intel_dp);
3727
3688
#define TIMEOUT_FRL_READY_MS 500
3728
3689
#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3729
-
3730
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3731
3690
int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3732
3691
u8 max_frl_bw_mask = 0, frl_trained_mask;
3733
3692
bool is_active;
3734
3693
3735
3694
max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3736
-
drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3695
+
drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3737
3696
3738
3697
max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3739
-
drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
3698
+
drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n",
3699
+
max_edid_frl_bw);
3740
3700
3741
3701
max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3742
3702
···
3744
3704
return -EINVAL;
3745
3705
3746
3706
max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3747
-
drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3707
+
drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3748
3708
3749
3709
if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3750
3710
goto frl_trained;
···
3781
3741
return -ETIMEDOUT;
3782
3742
3783
3743
frl_trained:
3784
-
drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3744
+
drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3785
3745
intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3786
3746
intel_dp->frl.is_trained = true;
3787
-
drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
3747
+
drm_dbg(display->drm, "FRL trained with : %d Gbps\n",
3748
+
intel_dp->frl.trained_rate_gbps);
3788
3749
3789
3750
return 0;
3790
3751
}
···
3824
3783
3825
3784
void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3826
3785
{
3827
-
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3786
+
struct intel_display *display = to_intel_display(intel_dp);
3828
3787
3829
3788
/*
3830
3789
* Always go for FRL training if:
···
3839
3798
if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3840
3799
int ret, mode;
3841
3800
3842
-
drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3801
+
drm_dbg(display->drm,
3802
+
"Couldn't set FRL mode, continuing with TMDS mode\n");
3843
3803
ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3844
3804
mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3845
3805
3846
3806
if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3847
-
drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3807
+
drm_dbg(display->drm,
3808
+
"Issue with PCON, cannot set TMDS mode\n");
3848
3809
} else {
3849
-
drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3810
+
drm_dbg(display->drm, "FRL training Completed\n");
3850
3811
}
3851
3812
}
3852
3813
···
3864
3821
intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3865
3822
const struct intel_crtc_state *crtc_state)
3866
3823
{
3867
-
struct intel_connector *intel_connector = intel_dp->attached_connector;
3868
-
struct drm_connector *connector = &intel_connector->base;
3869
-
int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
3870
-
int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
3824
+
struct intel_connector *connector = intel_dp->attached_connector;
3825
+
const struct drm_display_info *info = &connector->base.display_info;
3826
+
int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice;
3827
+
int hdmi_max_slices = info->hdmi.dsc_cap.max_slices;
3871
3828
int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3872
3829
int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3873
3830
···
3881
3838
const struct intel_crtc_state *crtc_state,
3882
3839
int num_slices, int slice_width)
3883
3840
{
3884
-
struct intel_connector *intel_connector = intel_dp->attached_connector;
3885
-
struct drm_connector *connector = &intel_connector->base;
3841
+
struct intel_connector *connector = intel_dp->attached_connector;
3842
+
const struct drm_display_info *info = &connector->base.display_info;
3886
3843
int output_format = crtc_state->output_format;
3887
-
bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
3844
+
bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp;
3888
3845
int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3889
3846
int hdmi_max_chunk_bytes =
3890
-
connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
3847
+
info->hdmi.dsc_cap.total_chunk_kbytes * 1024;
3891
3848
3892
3849
return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3893
3850
num_slices, output_format, hdmi_all_bpp,
···
3898
3855
intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3899
3856
const struct intel_crtc_state *crtc_state)
3900
3857
{
3858
+
struct intel_display *display = to_intel_display(intel_dp);
3859
+
struct intel_connector *connector = intel_dp->attached_connector;
3860
+
const struct drm_display_info *info;
3901
3861
u8 pps_param[6];
3902
3862
int slice_height;
3903
3863
int slice_width;
3904
3864
int num_slices;
3905
3865
int bits_per_pixel;
3906
3866
int ret;
3907
-
struct intel_connector *intel_connector = intel_dp->attached_connector;
3908
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3909
-
struct drm_connector *connector;
3910
3867
bool hdmi_is_dsc_1_2;
3911
3868
3912
3869
if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3913
3870
return;
3914
3871
3915
-
if (!intel_connector)
3872
+
if (!connector)
3916
3873
return;
3917
-
connector = &intel_connector->base;
3918
-
hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
3874
+
3875
+
info = &connector->base.display_info;
3876
+
3877
+
hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2;
3919
3878
3920
3879
if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3921
3880
!hdmi_is_dsc_1_2)
···
3948
3903
3949
3904
ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3950
3905
if (ret < 0)
3951
-
drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
3906
+
drm_dbg_kms(display->drm, "Failed to set pcon DSC\n");
3952
3907
}
3953
3908
3954
3909
void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3955
3910
const struct intel_crtc_state *crtc_state)
3956
3911
{
3957
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3912
+
struct intel_display *display = to_intel_display(intel_dp);
3958
3913
bool ycbcr444_to_420 = false;
3959
3914
bool rgb_to_ycbcr = false;
3960
3915
u8 tmp;
···
3969
3924
3970
3925
if (drm_dp_dpcd_writeb(&intel_dp->aux,
3971
3926
DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3972
-
drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3927
+
drm_dbg_kms(display->drm,
3928
+
"Failed to %s protocol converter HDMI mode\n",
3973
3929
str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3974
3930
3975
3931
if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
···
4005
3959
4006
3960
if (drm_dp_dpcd_writeb(&intel_dp->aux,
4007
3961
DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
4008
-
drm_dbg_kms(&i915->drm,
3962
+
drm_dbg_kms(display->drm,
4009
3963
"Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
4010
3964
str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
4011
3965
4012
3966
tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
4013
3967
4014
3968
if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
4015
-
drm_dbg_kms(&i915->drm,
3969
+
drm_dbg_kms(display->drm,
4016
3970
"Failed to %s protocol converter RGB->YCbCr conversion mode\n",
4017
3971
str_enable_disable(tmp));
4018
3972
}
···
4045
3999
4046
4000
void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
4047
4001
{
4048
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
4002
+
struct intel_display *display = to_intel_display(connector);
4049
4003
4050
4004
/*
4051
4005
* Clear the cached register set to avoid using stale values
···
4064
4018
4065
4019
if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
4066
4020
&connector->dp.fec_capability) < 0) {
4067
-
drm_err(&i915->drm, "Failed to read FEC DPCD register\n");
4021
+
drm_err(display->drm, "Failed to read FEC DPCD register\n");
4068
4022
return;
4069
4023
}
4070
4024
4071
-
drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4025
+
drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
4072
4026
connector->dp.fec_capability);
4073
4027
}
4074
4028
···
4083
4037
static void
4084
4038
intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
4085
4039
{
4086
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4040
+
struct intel_display *display = to_intel_display(intel_dp);
4087
4041
4088
4042
/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4089
-
if (!HAS_DSC(i915))
4043
+
if (!HAS_DSC(display))
4090
4044
return;
4091
4045
4092
4046
if (intel_dp_is_edp(intel_dp))
···
4100
4054
static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
4101
4055
struct drm_display_mode *mode)
4102
4056
{
4057
+
struct intel_display *display = to_intel_display(connector);
4103
4058
struct intel_dp *intel_dp = intel_attached_dp(connector);
4104
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
4105
4059
int n = intel_dp->mso_link_count;
4106
4060
int overlap = intel_dp->mso_pixel_overlap;
4107
4061
···
4116
4070
4117
4071
drm_mode_set_name(mode);
4118
4072
4119
-
drm_dbg_kms(&i915->drm,
4073
+
drm_dbg_kms(display->drm,
4120
4074
"[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
4121
4075
connector->base.base.id, connector->base.name,
4122
4076
DRM_MODE_ARG(mode));
···
4124
4078
4125
4079
void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
4126
4080
{
4127
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4081
+
struct intel_display *display = to_intel_display(encoder);
4128
4082
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4129
4083
struct intel_connector *connector = intel_dp->attached_connector;
4130
4084
···
4142
4096
* up by the BIOS, and thus we can't get the mode at module
4143
4097
* load.
4144
4098
*/
4145
-
drm_dbg_kms(&dev_priv->drm,
4099
+
drm_dbg_kms(display->drm,
4146
4100
"pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4147
4101
pipe_bpp, connector->panel.vbt.edp.bpp);
4148
4102
connector->panel.vbt.edp.bpp = pipe_bpp;
···
4151
4105
4152
4106
static void intel_edp_mso_init(struct intel_dp *intel_dp)
4153
4107
{
4154
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4108
+
struct intel_display *display = to_intel_display(intel_dp);
4155
4109
struct intel_connector *connector = intel_dp->attached_connector;
4156
4110
struct drm_display_info *info = &connector->base.display_info;
4157
4111
u8 mso;
···
4160
4114
return;
4161
4115
4162
4116
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
4163
-
drm_err(&i915->drm, "Failed to read MSO cap\n");
4117
+
drm_err(display->drm, "Failed to read MSO cap\n");
4164
4118
return;
4165
4119
}
4166
4120
4167
4121
/* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
4168
4122
mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
4169
4123
if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
4170
-
drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
4124
+
drm_err(display->drm, "Invalid MSO link count cap %u\n", mso);
4171
4125
mso = 0;
4172
4126
}
4173
4127
4174
4128
if (mso) {
4175
-
drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
4129
+
drm_dbg_kms(display->drm,
4130
+
"Sink MSO %ux%u configuration, pixel overlap %u\n",
4176
4131
mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
4177
4132
info->mso_pixel_overlap);
4178
-
if (!HAS_MSO(i915)) {
4179
-
drm_err(&i915->drm, "No source MSO support, disabling\n");
4133
+
if (!HAS_MSO(display)) {
4134
+
drm_err(display->drm,
4135
+
"No source MSO support, disabling\n");
4180
4136
mso = 0;
4181
4137
}
4182
4138
}
···
4229
4181
static bool
4230
4182
intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
4231
4183
{
4232
-
struct drm_i915_private *dev_priv =
4233
-
to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4184
+
struct intel_display *display = to_intel_display(intel_dp);
4234
4185
4235
4186
/* this function is meant to be called only once */
4236
-
drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4187
+
drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4237
4188
4238
4189
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
4239
4190
return false;
···
4256
4209
if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4257
4210
intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4258
4211
sizeof(intel_dp->edp_dpcd)) {
4259
-
drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4212
+
drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n",
4260
4213
(int)sizeof(intel_dp->edp_dpcd),
4261
4214
intel_dp->edp_dpcd);
4262
4215
···
4367
4320
intel_dp_mst_mode_choose(struct intel_dp *intel_dp,
4368
4321
enum drm_dp_mst_mode sink_mst_mode)
4369
4322
{
4370
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4323
+
struct intel_display *display = to_intel_display(intel_dp);
4371
4324
4372
-
if (!i915->display.params.enable_dp_mst)
4325
+
if (!display->params.enable_dp_mst)
4373
4326
return DRM_DP_SST;
4374
4327
4375
4328
if (!intel_dp_mst_source_support(intel_dp))
···
4385
4338
static enum drm_dp_mst_mode
4386
4339
intel_dp_mst_detect(struct intel_dp *intel_dp)
4387
4340
{
4388
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4341
+
struct intel_display *display = to_intel_display(intel_dp);
4389
4342
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4390
4343
enum drm_dp_mst_mode sink_mst_mode;
4391
4344
enum drm_dp_mst_mode mst_detect;
···
4394
4347
4395
4348
mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);
4396
4349
4397
-
drm_dbg_kms(&i915->drm,
4350
+
drm_dbg_kms(display->drm,
4398
4351
"[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",
4399
4352
encoder->base.base.id, encoder->base.name,
4400
4353
str_yes_no(intel_dp_mst_source_support(intel_dp)),
4401
4354
intel_dp_mst_mode_str(sink_mst_mode),
4402
-
str_yes_no(i915->display.params.enable_dp_mst),
4355
+
str_yes_no(display->params.enable_dp_mst),
4403
4356
intel_dp_mst_mode_str(mst_detect));
4404
4357
4405
4358
return mst_detect;
···
4425
4378
static void
4426
4379
intel_dp_mst_disconnect(struct intel_dp *intel_dp)
4427
4380
{
4428
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4381
+
struct intel_display *display = to_intel_display(intel_dp);
4429
4382
4430
4383
if (!intel_dp->is_mst)
4431
4384
return;
4432
4385
4433
-
drm_dbg_kms(&i915->drm, "MST device may have disappeared %d vs %d\n",
4386
+
drm_dbg_kms(display->drm,
4387
+
"MST device may have disappeared %d vs %d\n",
4434
4388
intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4435
4389
intel_dp->is_mst = false;
4436
4390
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
···
4512
4464
}
4513
4465
4514
4466
static ssize_t
4515
-
intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
4467
+
intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display,
4516
4468
const struct hdmi_drm_infoframe *drm_infoframe,
4517
4469
struct dp_sdp *sdp,
4518
4470
size_t size)
···
4529
4481
4530
4482
len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4531
4483
if (len < 0) {
4532
-
drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
4484
+
drm_dbg_kms(display->drm,
4485
+
"buffer size is smaller than hdr metadata infoframe\n");
4533
4486
return -ENOSPC;
4534
4487
}
4535
4488
4536
4489
if (len != infoframe_size) {
4537
-
drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
4490
+
drm_dbg_kms(display->drm, "wrong static hdr metadata size\n");
4538
4491
return -ENOSPC;
4539
4492
}
4540
4493
···
4593
4544
const struct intel_crtc_state *crtc_state,
4594
4545
unsigned int type)
4595
4546
{
4547
+
struct intel_display *display = to_intel_display(encoder);
4596
4548
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4597
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4598
4549
struct dp_sdp sdp = {};
4599
4550
ssize_t len;
4600
4551
···
4607
4558
len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);
4608
4559
break;
4609
4560
case HDMI_PACKET_TYPE_GAMUT_METADATA:
4610
-
len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4561
+
len = intel_dp_hdr_metadata_infoframe_sdp_pack(display,
4611
4562
&crtc_state->infoframes.drm.drm,
4612
4563
&sdp, sizeof(sdp));
4613
4564
break;
···
4620
4571
return;
4621
4572
}
4622
4573
4623
-
if (drm_WARN_ON(&dev_priv->drm, len < 0))
4574
+
if (drm_WARN_ON(display->drm, len < 0))
4624
4575
return;
4625
4576
4626
4577
dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
···
4631
4582
const struct intel_crtc_state *crtc_state,
4632
4583
const struct drm_connector_state *conn_state)
4633
4584
{
4634
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4635
-
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(dev_priv,
4636
-
crtc_state->cpu_transcoder);
4585
+
struct intel_display *display = to_intel_display(encoder);
4586
+
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
4637
4587
u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4638
4588
VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4639
4589
VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4640
4590
4641
-
if (HAS_AS_SDP(dev_priv))
4591
+
if (HAS_AS_SDP(display))
4642
4592
dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
4643
4593
4644
-
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4594
+
u32 val = intel_de_read(display, reg) & ~dip_enable;
4645
4595
4646
4596
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4647
-
if (!enable && HAS_DSC(dev_priv))
4597
+
if (!enable && HAS_DSC(display))
4648
4598
val &= ~VDIP_ENABLE_PPS;
4649
4599
4650
4600
/*
···
4653
4605
if (!enable || !crtc_state->has_psr)
4654
4606
val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4655
4607
4656
-
intel_de_write(dev_priv, reg, val);
4657
-
intel_de_posting_read(dev_priv, reg);
4608
+
intel_de_write(display, reg, val);
4609
+
intel_de_posting_read(display, reg);
4658
4610
4659
4611
if (!enable)
4660
4612
return;
···
4775
4727
struct intel_crtc_state *crtc_state,
4776
4728
struct drm_dp_as_sdp *as_sdp)
4777
4729
{
4730
+
struct intel_display *display = to_intel_display(encoder);
4778
4731
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4779
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4780
4732
unsigned int type = DP_SDP_ADAPTIVE_SYNC;
4781
4733
struct dp_sdp sdp = {};
4782
4734
int ret;
···
4790
4742
4791
4743
ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));
4792
4744
if (ret)
4793
-
drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n");
4745
+
drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n");
4794
4746
}
4795
4747
4796
4748
static int
···
4843
4795
struct intel_crtc_state *crtc_state,
4844
4796
struct drm_dp_vsc_sdp *vsc)
4845
4797
{
4798
+
struct intel_display *display = to_intel_display(encoder);
4846
4799
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4847
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4848
4800
unsigned int type = DP_SDP_VSC;
4849
4801
struct dp_sdp sdp = {};
4850
4802
int ret;
···
4858
4810
ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4859
4811
4860
4812
if (ret)
4861
-
drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4813
+
drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n");
4862
4814
}
4863
4815
4864
4816
static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4865
4817
struct intel_crtc_state *crtc_state,
4866
4818
struct hdmi_drm_infoframe *drm_infoframe)
4867
4819
{
4820
+
struct intel_display *display = to_intel_display(encoder);
4868
4821
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4869
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4870
4822
unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4871
4823
struct dp_sdp sdp = {};
4872
4824
int ret;
···
4882
4834
sizeof(sdp));
4883
4835
4884
4836
if (ret)
4885
-
drm_dbg_kms(&dev_priv->drm,
4837
+
drm_dbg_kms(display->drm,
4886
4838
"Failed to unpack DP HDR Metadata Infoframe SDP\n");
4887
4839
}
4888
4840
···
4912
4864
static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4913
4865
u8 link_status[DP_LINK_STATUS_SIZE])
4914
4866
{
4867
+
struct intel_display *display = to_intel_display(intel_dp);
4915
4868
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4916
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4917
4869
bool uhbr = intel_dp->link_rate >= 1000000;
4918
4870
bool ok;
4919
4871
···
4927
4879
return true;
4928
4880
4929
4881
intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4930
-
drm_dbg_kms(&i915->drm,
4882
+
drm_dbg_kms(display->drm,
4931
4883
"[ENCODER:%d:%s] %s link not ok, retraining\n",
4932
4884
encoder->base.base.id, encoder->base.name,
4933
4885
uhbr ? "128b/132b" : "8b/10b");
···
4950
4902
4951
4903
static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4952
4904
{
4905
+
struct intel_display *display = to_intel_display(intel_dp);
4953
4906
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4954
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4955
4907
u8 link_status[DP_LINK_STATUS_SIZE] = {};
4956
4908
const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4957
4909
4958
4910
if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4959
4911
esi_link_status_size) != esi_link_status_size) {
4960
-
drm_err(&i915->drm,
4912
+
drm_err(display->drm,
4961
4913
"[ENCODER:%d:%s] Failed to read link status\n",
4962
4914
encoder->base.base.id, encoder->base.name);
4963
4915
return false;
···
4983
4935
static bool
4984
4936
intel_dp_check_mst_status(struct intel_dp *intel_dp)
4985
4937
{
4986
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4938
+
struct intel_display *display = to_intel_display(intel_dp);
4987
4939
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4988
4940
struct intel_encoder *encoder = &dig_port->base;
4989
4941
bool link_ok = true;
4990
4942
bool reprobe_needed = false;
4991
4943
4992
-
drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4944
+
drm_WARN_ON_ONCE(display->drm, intel_dp->active_mst_links < 0);
4993
4945
4994
4946
for (;;) {
4995
4947
u8 esi[4] = {};
4996
4948
u8 ack[4] = {};
4997
4949
4998
4950
if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4999
-
drm_dbg_kms(&i915->drm,
4951
+
drm_dbg_kms(display->drm,
5000
4952
"failed to get ESI - device may have failed\n");
5001
4953
link_ok = false;
5002
4954
5003
4955
break;
5004
4956
}
5005
4957
5006
-
drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4958
+
drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi);
5007
4959
5008
4960
if (intel_dp->active_mst_links > 0 && link_ok &&
5009
4961
esi[3] & LINK_STATUS_CHANGED) {
···
5015
4967
intel_dp_mst_hpd_irq(intel_dp, esi, ack);
5016
4968
5017
4969
if (esi[3] & DP_TUNNELING_IRQ) {
5018
-
if (drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
4970
+
if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,
5019
4971
&intel_dp->aux))
5020
4972
reprobe_needed = true;
5021
4973
ack[3] |= DP_TUNNELING_IRQ;
···
5025
4977
break;
5026
4978
5027
4979
if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
5028
-
drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4980
+
drm_dbg_kms(display->drm, "Failed to ack ESI\n");
5029
4981
5030
4982
if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
5031
4983
drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
···
5113
5065
bool intel_dp_has_connector(struct intel_dp *intel_dp,
5114
5066
const struct drm_connector_state *conn_state)
5115
5067
{
5116
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5068
+
struct intel_display *display = to_intel_display(intel_dp);
5117
5069
struct intel_encoder *encoder;
5118
5070
enum pipe pipe;
5119
5071
···
5126
5078
return true;
5127
5079
5128
5080
/* MST */
5129
-
for_each_pipe(i915, pipe) {
5081
+
for_each_pipe(display, pipe) {
5130
5082
encoder = &intel_dp->mst_encoders[pipe]->base;
5131
5083
if (conn_state->best_encoder == &encoder->base)
5132
5084
return true;
···
5154
5106
struct drm_modeset_acquire_ctx *ctx,
5155
5107
u8 *pipe_mask)
5156
5108
{
5157
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5109
+
struct intel_display *display = to_intel_display(intel_dp);
5158
5110
struct drm_connector_list_iter conn_iter;
5159
5111
struct intel_connector *connector;
5160
5112
int ret = 0;
5161
5113
5162
5114
*pipe_mask = 0;
5163
5115
5164
-
drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5116
+
drm_connector_list_iter_begin(display->drm, &conn_iter);
5165
5117
for_each_intel_connector_iter(connector, &conn_iter) {
5166
5118
struct drm_connector_state *conn_state =
5167
5119
connector->base.state;
···
5181
5133
5182
5134
crtc_state = to_intel_crtc_state(crtc->base.state);
5183
5135
5184
-
drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5136
+
drm_WARN_ON(display->drm,
5137
+
!intel_crtc_has_dp_encoder(crtc_state));
5185
5138
5186
5139
if (!crtc_state->hw.active)
5187
5140
continue;
···
5212
5163
static int intel_dp_retrain_link(struct intel_encoder *encoder,
5213
5164
struct drm_modeset_acquire_ctx *ctx)
5214
5165
{
5166
+
struct intel_display *display = to_intel_display(encoder);
5215
5167
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5216
5168
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5217
5169
u8 pipe_mask;
···
5221
5171
if (!intel_dp_is_connected(intel_dp))
5222
5172
return 0;
5223
5173
5224
-
ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5174
+
ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
5225
5175
ctx);
5226
5176
if (ret)
5227
5177
return ret;
···
5239
5189
if (!intel_dp_needs_link_retrain(intel_dp))
5240
5190
return 0;
5241
5191
5242
-
drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link (forced %s)\n",
5192
+
drm_dbg_kms(display->drm,
5193
+
"[ENCODER:%d:%s] retraining link (forced %s)\n",
5243
5194
encoder->base.base.id, encoder->base.name,
5244
5195
str_yes_no(intel_dp->link.force_retrain));
5245
5196
···
5251
5200
intel_dp->link.force_retrain = false;
5252
5201
5253
5202
if (ret)
5254
-
drm_dbg_kms(&dev_priv->drm,
5203
+
drm_dbg_kms(display->drm,
5255
5204
"[ENCODER:%d:%s] link retraining failed: %pe\n",
5256
5205
encoder->base.base.id, encoder->base.name,
5257
5206
ERR_PTR(ret));
···
5284
5233
5285
5234
static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5286
5235
{
5287
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5236
+
struct intel_display *display = to_intel_display(intel_dp);
5288
5237
u8 val;
5289
5238
5290
5239
if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
···
5303
5252
intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5304
5253
5305
5254
if (val & DP_SINK_SPECIFIC_IRQ)
5306
-
drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5255
+
drm_dbg_kms(display->drm, "Sink specific irq unhandled\n");
5307
5256
}
5308
5257
5309
5258
static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5310
5259
{
5311
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5260
+
struct intel_display *display = to_intel_display(intel_dp);
5312
5261
bool reprobe_needed = false;
5313
5262
u8 val;
5314
5263
···
5320
5269
return false;
5321
5270
5322
5271
if ((val & DP_TUNNELING_IRQ) &&
5323
-
drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
5272
+
drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,
5324
5273
&intel_dp->aux))
5325
5274
reprobe_needed = true;
5326
5275
···
5389
5338
static enum drm_connector_status
5390
5339
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5391
5340
{
5392
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5341
+
struct intel_display *display = to_intel_display(intel_dp);
5393
5342
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5394
5343
u8 *dpcd = intel_dp->dpcd;
5395
5344
u8 type;
5396
5345
5397
-
if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5346
+
if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))
5398
5347
return connector_status_connected;
5399
5348
5400
5349
lspcon_resume(dig_port);
···
5437
5386
}
5438
5387
5439
5388
/* Anything else is out of spec, warn and ignore */
5440
-
drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5389
+
drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n");
5441
5390
return connector_status_disconnected;
5442
5391
}
5443
5392
···
5532
5481
intel_dp_update_dfp(struct intel_dp *intel_dp,
5533
5482
const struct drm_edid *drm_edid)
5534
5483
{
5535
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5484
+
struct intel_display *display = to_intel_display(intel_dp);
5536
5485
struct intel_connector *connector = intel_dp->attached_connector;
5537
5486
5538
5487
intel_dp->dfp.max_bpc =
···
5556
5505
drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5557
5506
intel_dp->downstream_ports);
5558
5507
5559
-
drm_dbg_kms(&i915->drm,
5508
+
drm_dbg_kms(display->drm,
5560
5509
"[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5561
5510
connector->base.base.id, connector->base.name,
5562
5511
intel_dp->dfp.max_bpc,
···
5589
5538
static void
5590
5539
intel_dp_update_420(struct intel_dp *intel_dp)
5591
5540
{
5592
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5541
+
struct intel_display *display = to_intel_display(intel_dp);
5593
5542
struct intel_connector *connector = intel_dp->attached_connector;
5594
5543
5595
5544
intel_dp->dfp.ycbcr420_passthrough =
···
5607
5556
5608
5557
connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5609
5558
5610
-
drm_dbg_kms(&i915->drm,
5559
+
drm_dbg_kms(display->drm,
5611
5560
"[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5612
5561
connector->base.base.id, connector->base.name,
5613
5562
str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
···
5618
5567
static void
5619
5568
intel_dp_set_edid(struct intel_dp *intel_dp)
5620
5569
{
5621
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5570
+
struct intel_display *display = to_intel_display(intel_dp);
5622
5571
struct intel_connector *connector = intel_dp->attached_connector;
5623
5572
const struct drm_edid *drm_edid;
5624
5573
bool vrr_capable;
···
5631
5580
drm_edid_connector_update(&connector->base, drm_edid);
5632
5581
5633
5582
vrr_capable = intel_vrr_is_capable(connector);
5634
-
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5583
+
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5635
5584
connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5636
5585
drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5637
5586
···
5668
5617
static void
5669
5618
intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
5670
5619
{
5671
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5620
+
struct intel_display *display = to_intel_display(intel_dp);
5672
5621
5673
-
intel_dp->as_sdp_supported = HAS_AS_SDP(i915) &&
5622
+
intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
5674
5623
drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
5675
5624
}
5676
5625
5677
5626
static int
5678
-
intel_dp_detect(struct drm_connector *connector,
5627
+
intel_dp_detect(struct drm_connector *_connector,
5679
5628
struct drm_modeset_acquire_ctx *ctx,
5680
5629
bool force)
5681
5630
{
5682
-
struct intel_display *display = to_intel_display(connector->dev);
5683
-
struct drm_i915_private *dev_priv = to_i915(connector->dev);
5684
-
struct intel_connector *intel_connector =
5685
-
to_intel_connector(connector);
5686
-
struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5631
+
struct intel_display *display = to_intel_display(_connector->dev);
5632
+
struct intel_connector *connector = to_intel_connector(_connector);
5633
+
struct intel_dp *intel_dp = intel_attached_dp(connector);
5687
5634
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5688
5635
struct intel_encoder *encoder = &dig_port->base;
5689
5636
enum drm_connector_status status;
5690
5637
int ret;
5691
5638
5692
-
drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5693
-
connector->base.id, connector->name);
5694
-
drm_WARN_ON(&dev_priv->drm,
5695
-
!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5639
+
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
5640
+
connector->base.base.id, connector->base.name);
5641
+
drm_WARN_ON(display->drm,
5642
+
!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
5696
5643
5697
5644
if (!intel_display_device_enabled(display))
5698
5645
return connector_status_disconnected;
5699
5646
5700
5647
if (!intel_display_driver_check_access(display))
5701
-
return connector->status;
5648
+
return connector->base.status;
5702
5649
5703
-
intel_dp_flush_connector_commits(intel_connector);
5650
+
intel_dp_flush_connector_commits(connector);
5704
5651
5705
5652
intel_pps_vdd_on(intel_dp);
5706
5653
···
5724
5675
5725
5676
if (status == connector_status_disconnected) {
5726
5677
intel_dp_test_reset(intel_dp);
5727
-
memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
5678
+
memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
5728
5679
intel_dp->psr.sink_panel_replay_support = false;
5729
5680
intel_dp->psr.sink_panel_replay_su_support = false;
5730
5681
···
5745
5696
}
5746
5697
5747
5698
if (ret == 1)
5748
-
intel_connector->base.epoch_counter++;
5699
+
connector->base.epoch_counter++;
5749
5700
5750
5701
if (!intel_dp_is_edp(intel_dp))
5751
5702
intel_psr_init_dpcd(intel_dp);
5752
5703
5753
-
intel_dp_detect_dsc_caps(intel_dp, intel_connector);
5704
+
intel_dp_detect_dsc_caps(intel_dp, connector);
5754
5705
5755
5706
intel_dp_detect_sdp_caps(intel_dp);
5756
5707
···
5793
5744
intel_dp->aux.i2c_defer_count = 0;
5794
5745
5795
5746
intel_dp_set_edid(intel_dp);
5796
-
if (intel_dp_is_edp(intel_dp) ||
5797
-
to_intel_connector(connector)->detect_edid)
5747
+
if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
5798
5748
status = connector_status_connected;
5799
5749
5800
5750
intel_dp_check_device_service_irq(intel_dp);
···
5803
5755
intel_dp_unset_edid(intel_dp);
5804
5756
5805
5757
if (!intel_dp_is_edp(intel_dp))
5806
-
drm_dp_set_subconnector_property(connector,
5758
+
drm_dp_set_subconnector_property(&connector->base,
5807
5759
status,
5808
5760
intel_dp->dpcd,
5809
5761
intel_dp->downstream_ports);
···
5818
5770
{
5819
5771
struct intel_display *display = to_intel_display(connector->dev);
5820
5772
struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5821
-
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5822
-
struct intel_encoder *intel_encoder = &dig_port->base;
5823
-
struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5824
5773
5825
-
drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5774
+
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
5826
5775
connector->base.id, connector->name);
5827
5776
5828
5777
if (!intel_display_driver_check_access(display))
···
5833
5788
intel_dp_set_edid(intel_dp);
5834
5789
}
5835
5790
5836
-
static int intel_dp_get_modes(struct drm_connector *connector)
5791
+
static int intel_dp_get_modes(struct drm_connector *_connector)
5837
5792
{
5838
-
struct intel_connector *intel_connector = to_intel_connector(connector);
5793
+
struct intel_display *display = to_intel_display(_connector->dev);
5794
+
struct intel_connector *connector = to_intel_connector(_connector);
5795
+
struct intel_dp *intel_dp = intel_attached_dp(connector);
5839
5796
int num_modes;
5840
5797
5841
5798
/* drm_edid_connector_update() done in ->detect() or ->force() */
5842
-
num_modes = drm_edid_connector_add_modes(connector);
5799
+
num_modes = drm_edid_connector_add_modes(&connector->base);
5843
5800
5844
5801
/* Also add fixed mode, which may or may not be present in EDID */
5845
-
if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5846
-
num_modes += intel_panel_get_modes(intel_connector);
5802
+
if (intel_dp_is_edp(intel_dp))
5803
+
num_modes += intel_panel_get_modes(connector);
5847
5804
5848
5805
if (num_modes)
5849
5806
return num_modes;
5850
5807
5851
-
if (!intel_connector->detect_edid) {
5852
-
struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5808
+
if (!connector->detect_edid) {
5853
5809
struct drm_display_mode *mode;
5854
5810
5855
-
mode = drm_dp_downstream_mode(connector->dev,
5811
+
mode = drm_dp_downstream_mode(display->drm,
5856
5812
intel_dp->dpcd,
5857
5813
intel_dp->downstream_ports);
5858
5814
if (mode) {
5859
-
drm_mode_probed_add(connector, mode);
5815
+
drm_mode_probed_add(&connector->base, mode);
5860
5816
num_modes++;
5861
5817
}
5862
5818
}
···
5868
5822
static int
5869
5823
intel_dp_connector_register(struct drm_connector *connector)
5870
5824
{
5871
-
struct drm_i915_private *i915 = to_i915(connector->dev);
5825
+
struct intel_display *display = to_intel_display(connector->dev);
5872
5826
struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5873
5827
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5874
5828
struct intel_lspcon *lspcon = &dig_port->lspcon;
···
5878
5832
if (ret)
5879
5833
return ret;
5880
5834
5881
-
drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5835
+
drm_dbg_kms(display->drm, "registering %s bus for %s\n",
5882
5836
intel_dp->aux.name, connector->kdev->kobj.name);
5883
5837
5884
5838
intel_dp->aux.dev = connector->kdev;
···
5915
5869
void intel_dp_connector_sync_state(struct intel_connector *connector,
5916
5870
const struct intel_crtc_state *crtc_state)
5917
5871
{
5918
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
5872
+
struct intel_display *display = to_intel_display(connector);
5919
5873
5920
5874
if (crtc_state && crtc_state->dsc.compression_enable) {
5921
-
drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
5875
+
drm_WARN_ON(display->drm,
5876
+
!connector->dp.dsc_decompression_aux);
5922
5877
connector->dp.dsc_decompression_enabled = true;
5923
5878
} else {
5924
5879
connector->dp.dsc_decompression_enabled = false;
···
5949
5902
intel_dp_aux_fini(intel_dp);
5950
5903
}
5951
5904
5952
-
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5905
+
void intel_dp_encoder_suspend(struct intel_encoder *encoder)
5953
5906
{
5954
-
struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5907
+
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5955
5908
5956
5909
intel_pps_vdd_off_sync(intel_dp);
5957
5910
5958
5911
intel_dp_tunnel_suspend(intel_dp);
5959
5912
}
5960
5913
5961
-
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5914
+
void intel_dp_encoder_shutdown(struct intel_encoder *encoder)
5962
5915
{
5963
-
struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5916
+
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5964
5917
5965
5918
intel_pps_wait_power_cycle(intel_dp);
5966
5919
}
···
5968
5921
static int intel_modeset_tile_group(struct intel_atomic_state *state,
5969
5922
int tile_group_id)
5970
5923
{
5971
-
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5924
+
struct intel_display *display = to_intel_display(state);
5972
5925
struct drm_connector_list_iter conn_iter;
5973
5926
struct drm_connector *connector;
5974
5927
int ret = 0;
5975
5928
5976
-
drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5929
+
drm_connector_list_iter_begin(display->drm, &conn_iter);
5977
5930
drm_for_each_connector_iter(connector, &conn_iter) {
5978
5931
struct drm_connector_state *conn_state;
5979
5932
struct intel_crtc_state *crtc_state;
···
6009
5962
6010
5963
static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
6011
5964
{
6012
-
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5965
+
struct intel_display *display = to_intel_display(state);
6013
5966
struct intel_crtc *crtc;
6014
5967
6015
5968
if (transcoders == 0)
6016
5969
return 0;
6017
5970
6018
-
for_each_intel_crtc(&dev_priv->drm, crtc) {
5971
+
for_each_intel_crtc(display->drm, crtc) {
6019
5972
struct intel_crtc_state *crtc_state;
6020
5973
int ret;
6021
5974
···
6042
5995
transcoders &= ~BIT(crtc_state->cpu_transcoder);
6043
5996
}
6044
5997
6045
-
drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5998
+
drm_WARN_ON(display->drm, transcoders != 0);
6046
5999
6047
6000
return 0;
6048
6001
}
···
6076
6029
static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6077
6030
struct drm_atomic_state *_state)
6078
6031
{
6079
-
struct drm_i915_private *dev_priv = to_i915(conn->dev);
6032
+
struct intel_display *display = to_intel_display(conn->dev);
6080
6033
struct intel_atomic_state *state = to_intel_atomic_state(_state);
6081
6034
struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6082
6035
struct intel_connector *intel_conn = to_intel_connector(conn);
···
6106
6059
* We don't enable port sync on BDW due to missing w/as and
6107
6060
* due to not having adjusted the modeset sequence appropriately.
6108
6061
*/
6109
-
if (DISPLAY_VER(dev_priv) < 9)
6062
+
if (DISPLAY_VER(display) < 9)
6110
6063
return 0;
6111
6064
6112
6065
if (conn->has_tile) {
···
6121
6074
static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6122
6075
enum drm_connector_status hpd_state)
6123
6076
{
6077
+
struct intel_display *display = to_intel_display(connector->dev);
6124
6078
struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6125
6079
struct drm_i915_private *i915 = to_i915(connector->dev);
6126
6080
bool hpd_high = hpd_state == connector_status_connected;
···
6129
6081
bool need_work = false;
6130
6082
6131
6083
spin_lock_irq(&i915->irq_lock);
6132
-
if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {
6133
-
i915->display.hotplug.event_bits |= BIT(hpd_pin);
6084
+
if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) {
6085
+
display->hotplug.event_bits |= BIT(hpd_pin);
6134
6086
6135
-
__assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);
6087
+
__assign_bit(hpd_pin,
6088
+
&display->hotplug.oob_hotplug_last_state,
6089
+
hpd_high);
6136
6090
need_work = true;
6137
6091
}
6138
6092
spin_unlock_irq(&i915->irq_lock);
···
6166
6116
enum irqreturn
6167
6117
intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6168
6118
{
6119
+
struct intel_display *display = to_intel_display(dig_port);
6169
6120
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6170
6121
struct intel_dp *intel_dp = &dig_port->dp;
6171
6122
u8 dpcd[DP_RECEIVER_CAP_SIZE];
···
6181
6130
* would end up in an endless cycle of
6182
6131
* "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6183
6132
*/
6184
-
drm_dbg_kms(&i915->drm,
6133
+
drm_dbg_kms(display->drm,
6185
6134
"ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6186
6135
long_hpd ? "long" : "short",
6187
6136
dig_port->base.base.base.id,
···
6189
6138
return IRQ_HANDLED;
6190
6139
}
6191
6140
6192
-
drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6141
+
drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6193
6142
dig_port->base.base.base.id,
6194
6143
dig_port->base.base.name,
6195
6144
long_hpd ? "long" : "short");
···
6222
6171
return IRQ_HANDLED;
6223
6172
}
6224
6173
6225
-
static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
6174
+
static bool _intel_dp_is_port_edp(struct intel_display *display,
6226
6175
const struct intel_bios_encoder_data *devdata,
6227
6176
enum port port)
6228
6177
{
···
6230
6179
* eDP not supported on g4x. so bail out early just
6231
6180
* for a bit extra safety in case the VBT is bonkers.
6232
6181
*/
6233
-
if (DISPLAY_VER(dev_priv) < 5)
6182
+
if (DISPLAY_VER(display) < 5)
6234
6183
return false;
6235
6184
6236
-
if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
6185
+
if (DISPLAY_VER(display) < 9 && port == PORT_A)
6237
6186
return true;
6238
6187
6239
6188
return devdata && intel_bios_encoder_supports_edp(devdata);
6240
6189
}
6241
6190
6242
-
bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
6191
+
bool intel_dp_is_port_edp(struct intel_display *display, enum port port)
6243
6192
{
6244
-
struct intel_display *display = &i915->display;
6245
6193
const struct intel_bios_encoder_data *devdata =
6246
6194
intel_bios_encoder_data_lookup(display, port);
6247
6195
6248
-
return _intel_dp_is_port_edp(i915, devdata, port);
6196
+
return _intel_dp_is_port_edp(display, devdata, port);
6249
6197
}
6250
6198
6251
6199
bool
6252
6200
intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder)
6253
6201
{
6254
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
6202
+
struct intel_display *display = to_intel_display(encoder);
6255
6203
enum port port = encoder->port;
6256
6204
6257
6205
if (intel_bios_encoder_is_lspcon(encoder->devdata))
6258
6206
return false;
6259
6207
6260
-
if (DISPLAY_VER(i915) >= 11)
6208
+
if (DISPLAY_VER(display) >= 11)
6261
6209
return true;
6262
6210
6263
6211
if (port == PORT_A)
6264
6212
return false;
6265
6213
6266
-
if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
6267
-
DISPLAY_VER(i915) >= 9)
6214
+
if (display->platform.haswell || display->platform.broadwell ||
6215
+
DISPLAY_VER(display) >= 9)
6268
6216
return true;
6269
6217
6270
6218
return false;
···
6272
6222
static void
6273
6223
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6274
6224
{
6275
-
struct drm_i915_private *dev_priv = to_i915(connector->dev);
6225
+
struct intel_display *display = to_intel_display(intel_dp);
6276
6226
enum port port = dp_to_dig_port(intel_dp)->base.port;
6277
6227
6278
6228
if (!intel_dp_is_edp(intel_dp))
6279
6229
drm_connector_attach_dp_subconnector_property(connector);
6280
6230
6281
-
if (!IS_G4X(dev_priv) && port != PORT_A)
6231
+
if (!display->platform.g4x && port != PORT_A)
6282
6232
intel_attach_force_audio_property(connector);
6283
6233
6284
6234
intel_attach_broadcast_rgb_property(connector);
6285
-
if (HAS_GMCH(dev_priv))
6235
+
if (HAS_GMCH(display))
6286
6236
drm_connector_attach_max_bpc_property(connector, 6, 10);
6287
-
else if (DISPLAY_VER(dev_priv) >= 5)
6237
+
else if (DISPLAY_VER(display) >= 5)
6288
6238
drm_connector_attach_max_bpc_property(connector, 6, 12);
6289
6239
6290
6240
/* Register HDMI colorspace for case of lspcon */
···
6298
6248
if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6299
6249
drm_connector_attach_hdr_output_metadata_property(connector);
6300
6250
6301
-
if (HAS_VRR(dev_priv))
6251
+
if (HAS_VRR(display))
6302
6252
drm_connector_attach_vrr_capable_property(connector);
6303
6253
}
6304
6254
6305
6255
static void
6306
6256
intel_edp_add_properties(struct intel_dp *intel_dp)
6307
6257
{
6258
+
struct intel_display *display = to_intel_display(intel_dp);
6308
6259
struct intel_connector *connector = intel_dp->attached_connector;
6309
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
6310
6260
const struct drm_display_mode *fixed_mode =
6311
6261
intel_panel_preferred_fixed_mode(connector);
6312
6262
6313
6263
intel_attach_scaling_mode_property(&connector->base);
6314
6264
6315
6265
drm_connector_set_panel_orientation_with_quirk(&connector->base,
6316
-
i915->display.vbt.orientation,
6266
+
display->vbt.orientation,
6317
6267
fixed_mode->hdisplay,
6318
6268
fixed_mode->vdisplay);
6319
6269
}
···
6321
6271
static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6322
6272
struct intel_connector *connector)
6323
6273
{
6324
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6274
+
struct intel_display *display = to_intel_display(intel_dp);
6325
6275
enum pipe pipe = INVALID_PIPE;
6326
6276
6327
-
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
6277
+
if (display->platform.valleyview || display->platform.cherryview)
6328
6278
pipe = vlv_pps_backlight_initial_pipe(intel_dp);
6329
6279
6330
6280
intel_backlight_setup(connector, pipe);
6331
6281
}
6332
6282
6333
6283
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6334
-
struct intel_connector *intel_connector)
6284
+
struct intel_connector *connector)
6335
6285
{
6336
6286
struct intel_display *display = to_intel_display(intel_dp);
6337
-
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6338
-
struct drm_connector *connector = &intel_connector->base;
6287
+
struct drm_i915_private *dev_priv = to_i915(display->drm);
6339
6288
struct drm_display_mode *fixed_mode;
6340
6289
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6341
6290
bool has_dpcd;
···
6350
6301
* with an already powered-on LVDS power sequencer.
6351
6302
*/
6352
6303
if (intel_get_lvds_encoder(dev_priv)) {
6353
-
drm_WARN_ON(&dev_priv->drm,
6304
+
drm_WARN_ON(display->drm,
6354
6305
!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6355
-
drm_info(&dev_priv->drm,
6306
+
drm_info(display->drm,
6356
6307
"LVDS was detected, not registering eDP\n");
6357
6308
6358
6309
return false;
6359
6310
}
6360
6311
6361
-
intel_bios_init_panel_early(display, &intel_connector->panel,
6312
+
intel_bios_init_panel_early(display, &connector->panel,
6362
6313
encoder->devdata);
6363
6314
6364
6315
if (!intel_pps_init(intel_dp)) {
6365
-
drm_info(&dev_priv->drm,
6316
+
drm_info(display->drm,
6366
6317
"[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6367
6318
encoder->base.base.id, encoder->base.name);
6368
6319
/*
···
6385
6336
intel_alpm_init_dpcd(intel_dp);
6386
6337
6387
6338
/* Cache DPCD and EDID for edp. */
6388
-
has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector);
6339
+
has_dpcd = intel_edp_init_dpcd(intel_dp, connector);
6389
6340
6390
6341
if (!has_dpcd) {
6391
6342
/* if this fails, presume the device is a ghost */
6392
-
drm_info(&dev_priv->drm,
6343
+
drm_info(display->drm,
6393
6344
"[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6394
6345
encoder->base.base.id, encoder->base.name);
6395
6346
goto out_vdd_off;
···
6412
6363
* DPCD read? Would need sort out the VDD handling...
6413
6364
*/
6414
6365
if (!intel_digital_port_connected(encoder)) {
6415
-
drm_info(&dev_priv->drm,
6366
+
drm_info(display->drm,
6416
6367
"[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6417
6368
encoder->base.base.id, encoder->base.name);
6418
6369
goto out_vdd_off;
···
6424
6375
* back to checking for a VGA branch device. Only do this
6425
6376
* on known affected platforms to minimize false positives.
6426
6377
*/
6427
-
if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6378
+
if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6428
6379
(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6429
6380
DP_DWN_STRM_PORT_TYPE_ANALOG) {
6430
-
drm_info(&dev_priv->drm,
6381
+
drm_info(display->drm,
6431
6382
"[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6432
6383
encoder->base.base.id, encoder->base.name);
6433
6384
goto out_vdd_off;
6434
6385
}
6435
6386
}
6436
6387
6437
-
mutex_lock(&dev_priv->drm.mode_config.mutex);
6438
-
drm_edid = drm_edid_read_ddc(connector, connector->ddc);
6388
+
mutex_lock(&display->drm->mode_config.mutex);
6389
+
drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);
6439
6390
if (!drm_edid) {
6440
6391
/* Fallback to EDID from ACPI OpRegion, if any */
6441
-
drm_edid = intel_opregion_get_edid(intel_connector);
6392
+
drm_edid = intel_opregion_get_edid(connector);
6442
6393
if (drm_edid)
6443
-
drm_dbg_kms(&dev_priv->drm,
6394
+
drm_dbg_kms(display->drm,
6444
6395
"[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6445
-
connector->base.id, connector->name);
6396
+
connector->base.base.id, connector->base.name);
6446
6397
}
6447
6398
if (drm_edid) {
6448
-
if (drm_edid_connector_update(connector, drm_edid) ||
6449
-
!drm_edid_connector_add_modes(connector)) {
6450
-
drm_edid_connector_update(connector, NULL);
6399
+
if (drm_edid_connector_update(&connector->base, drm_edid) ||
6400
+
!drm_edid_connector_add_modes(&connector->base)) {
6401
+
drm_edid_connector_update(&connector->base, NULL);
6451
6402
drm_edid_free(drm_edid);
6452
6403
drm_edid = ERR_PTR(-EINVAL);
6453
6404
}
···
6455
6406
drm_edid = ERR_PTR(-ENOENT);
6456
6407
}
6457
6408
6458
-
intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata,
6409
+
intel_bios_init_panel_late(display, &connector->panel, encoder->devdata,
6459
6410
IS_ERR(drm_edid) ? NULL : drm_edid);
6460
6411
6461
-
intel_panel_add_edid_fixed_modes(intel_connector, true);
6412
+
intel_panel_add_edid_fixed_modes(connector, true);
6462
6413
6463
6414
/* MSO requires information from the EDID */
6464
6415
intel_edp_mso_init(intel_dp);
6465
6416
6466
6417
/* multiply the mode clock and horizontal timings for MSO */
6467
-
list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
6468
-
intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
6418
+
list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head)
6419
+
intel_edp_mso_mode_fixup(connector, fixed_mode);
6469
6420
6470
6421
/* fallback to VBT if available for eDP */
6471
-
if (!intel_panel_preferred_fixed_mode(intel_connector))
6472
-
intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
6422
+
if (!intel_panel_preferred_fixed_mode(connector))
6423
+
intel_panel_add_vbt_lfp_fixed_mode(connector);
6473
6424
6474
-
mutex_unlock(&dev_priv->drm.mode_config.mutex);
6425
+
mutex_unlock(&display->drm->mode_config.mutex);
6475
6426
6476
-
if (!intel_panel_preferred_fixed_mode(intel_connector)) {
6477
-
drm_info(&dev_priv->drm,
6427
+
if (!intel_panel_preferred_fixed_mode(connector)) {
6428
+
drm_info(display->drm,
6478
6429
"[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6479
6430
encoder->base.base.id, encoder->base.name);
6480
6431
goto out_vdd_off;
6481
6432
}
6482
6433
6483
-
intel_panel_init(intel_connector, drm_edid);
6434
+
intel_panel_init(connector, drm_edid);
6484
6435
6485
-
intel_edp_backlight_setup(intel_dp, intel_connector);
6436
+
intel_edp_backlight_setup(intel_dp, connector);
6486
6437
6487
6438
intel_edp_add_properties(intel_dp);
6488
6439
···
6492
6443
6493
6444
out_vdd_off:
6494
6445
intel_pps_vdd_off_sync(intel_dp);
6495
-
intel_bios_fini_panel(&intel_connector->panel);
6446
+
intel_bios_fini_panel(&connector->panel);
6496
6447
6497
6448
return false;
6498
6449
}
6499
6450
6500
6451
static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6501
6452
{
6502
-
struct intel_connector *intel_connector;
6503
-
struct drm_connector *connector;
6453
+
struct intel_connector *connector = container_of(work, typeof(*connector),
6454
+
modeset_retry_work);
6455
+
struct intel_display *display = to_intel_display(connector);
6504
6456
6505
-
intel_connector = container_of(work, typeof(*intel_connector),
6506
-
modeset_retry_work);
6507
-
connector = &intel_connector->base;
6508
-
drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
6509
-
connector->name);
6457
+
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id,
6458
+
connector->base.name);
6510
6459
6511
6460
/* Grab the locks before changing connector property*/
6512
-
mutex_lock(&connector->dev->mode_config.mutex);
6461
+
mutex_lock(&display->drm->mode_config.mutex);
6513
6462
/* Set connector link status to BAD and send a Uevent to notify
6514
6463
* userspace to do a modeset.
6515
6464
*/
6516
-
drm_connector_set_link_status_property(connector,
6465
+
drm_connector_set_link_status_property(&connector->base,
6517
6466
DRM_MODE_LINK_STATUS_BAD);
6518
-
mutex_unlock(&connector->dev->mode_config.mutex);
6467
+
mutex_unlock(&display->drm->mode_config.mutex);
6519
6468
/* Send Hotplug uevent so userspace can reprobe */
6520
-
drm_kms_helper_connector_hotplug_event(connector);
6469
+
drm_kms_helper_connector_hotplug_event(&connector->base);
6521
6470
6522
-
drm_connector_put(connector);
6471
+
drm_connector_put(&connector->base);
6523
6472
}
6524
6473
6525
6474
void intel_dp_init_modeset_retry_work(struct intel_connector *connector)
···
6528
6481
6529
6482
bool
6530
6483
intel_dp_init_connector(struct intel_digital_port *dig_port,
6531
-
struct intel_connector *intel_connector)
6484
+
struct intel_connector *connector)
6532
6485
{
6533
6486
struct intel_display *display = to_intel_display(dig_port);
6534
-
struct drm_connector *connector = &intel_connector->base;
6535
6487
struct intel_dp *intel_dp = &dig_port->dp;
6536
-
struct intel_encoder *intel_encoder = &dig_port->base;
6537
-
struct drm_device *dev = intel_encoder->base.dev;
6488
+
struct intel_encoder *encoder = &dig_port->base;
6489
+
struct drm_device *dev = encoder->base.dev;
6538
6490
struct drm_i915_private *dev_priv = to_i915(dev);
6539
-
enum port port = intel_encoder->port;
6491
+
enum port port = encoder->port;
6540
6492
int type;
6541
6493
6542
6494
/* Initialize the work for modeset in case of link train failure */
6543
-
intel_dp_init_modeset_retry_work(intel_connector);
6495
+
intel_dp_init_modeset_retry_work(connector);
6544
6496
6545
6497
if (drm_WARN(dev, dig_port->max_lanes < 1,
6546
6498
"Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6547
-
dig_port->max_lanes, intel_encoder->base.base.id,
6548
-
intel_encoder->base.name))
6499
+
dig_port->max_lanes, encoder->base.base.id,
6500
+
encoder->base.name))
6549
6501
return false;
6550
6502
6551
6503
intel_dp->reset_link_params = true;
6552
6504
6553
6505
/* Preserve the current hw state. */
6554
-
intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6555
-
intel_dp->attached_connector = intel_connector;
6506
+
intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
6507
+
intel_dp->attached_connector = connector;
6556
6508
6557
-
if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6509
+
if (_intel_dp_is_port_edp(display, encoder->devdata, port)) {
6558
6510
/*
6559
6511
* Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30,
6560
6512
* although in theory it could work on TypeC legacy ports.
6561
6513
*/
6562
-
drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder) &&
6563
-
DISPLAY_VER(dev_priv) < 30);
6514
+
drm_WARN_ON(dev, intel_encoder_is_tc(encoder) &&
6515
+
DISPLAY_VER(display) < 30);
6564
6516
type = DRM_MODE_CONNECTOR_eDP;
6565
-
intel_encoder->type = INTEL_OUTPUT_EDP;
6517
+
encoder->type = INTEL_OUTPUT_EDP;
6566
6518
6567
6519
/* eDP only on port B and/or C on vlv/chv */
6568
-
if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6569
-
IS_CHERRYVIEW(dev_priv)) &&
6520
+
if (drm_WARN_ON(dev, (display->platform.valleyview ||
6521
+
display->platform.cherryview) &&
6570
6522
port != PORT_B && port != PORT_C))
6571
6523
return false;
6572
6524
} else {
···
6575
6529
intel_dp_set_default_sink_rates(intel_dp);
6576
6530
intel_dp_set_default_max_sink_lane_count(intel_dp);
6577
6531
6578
-
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6532
+
if (display->platform.valleyview || display->platform.cherryview)
6579
6533
vlv_pps_pipe_init(intel_dp);
6580
6534
6581
6535
intel_dp_aux_init(intel_dp);
6582
-
intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
6536
+
connector->dp.dsc_decompression_aux = &intel_dp->aux;
6583
6537
6584
-
drm_dbg_kms(&dev_priv->drm,
6538
+
drm_dbg_kms(display->drm,
6585
6539
"Adding %s connector on [ENCODER:%d:%s]\n",
6586
6540
type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6587
-
intel_encoder->base.base.id, intel_encoder->base.name);
6541
+
encoder->base.base.id, encoder->base.name);
6588
6542
6589
-
drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,
6543
+
drm_connector_init_with_ddc(dev, &connector->base, &intel_dp_connector_funcs,
6590
6544
type, &intel_dp->aux.ddc);
6591
-
drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6545
+
drm_connector_helper_add(&connector->base, &intel_dp_connector_helper_funcs);
6592
6546
6593
-
if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6594
-
connector->interlace_allowed = true;
6547
+
if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12)
6548
+
connector->base.interlace_allowed = true;
6595
6549
6596
6550
if (type != DRM_MODE_CONNECTOR_eDP)
6597
-
intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6598
-
intel_connector->base.polled = intel_connector->polled;
6551
+
connector->polled = DRM_CONNECTOR_POLL_HPD;
6552
+
connector->base.polled = connector->polled;
6599
6553
6600
-
intel_connector_attach_encoder(intel_connector, intel_encoder);
6554
+
intel_connector_attach_encoder(connector, encoder);
6601
6555
6602
-
if (HAS_DDI(dev_priv))
6603
-
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6556
+
if (HAS_DDI(display))
6557
+
connector->get_hw_state = intel_ddi_connector_get_hw_state;
6604
6558
else
6605
-
intel_connector->get_hw_state = intel_connector_get_hw_state;
6606
-
intel_connector->sync_state = intel_dp_connector_sync_state;
6559
+
connector->get_hw_state = intel_connector_get_hw_state;
6560
+
connector->sync_state = intel_dp_connector_sync_state;
6607
6561
6608
-
if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6562
+
if (!intel_edp_init_connector(intel_dp, connector)) {
6609
6563
intel_dp_aux_fini(intel_dp);
6610
6564
goto fail;
6611
6565
}
···
6615
6569
intel_dp_reset_link_params(intel_dp);
6616
6570
6617
6571
/* init MST on ports that can support it */
6618
-
intel_dp_mst_encoder_init(dig_port,
6619
-
intel_connector->base.base.id);
6572
+
intel_dp_mst_encoder_init(dig_port, connector->base.base.id);
6620
6573
6621
-
intel_dp_add_properties(intel_dp, connector);
6574
+
intel_dp_add_properties(intel_dp, &connector->base);
6622
6575
6623
6576
if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
6624
-
int ret = intel_dp_hdcp_init(dig_port, intel_connector);
6577
+
int ret = intel_dp_hdcp_init(dig_port, connector);
6625
6578
if (ret)
6626
-
drm_dbg_kms(&dev_priv->drm,
6579
+
drm_dbg_kms(display->drm,
6627
6580
"HDCP init failed, skipping.\n");
6628
6581
}
6629
6582
···
6635
6590
6636
6591
fail:
6637
6592
intel_display_power_flush_work(dev_priv);
6638
-
drm_connector_cleanup(connector);
6593
+
drm_connector_cleanup(&connector->base);
6639
6594
6640
6595
return false;
6641
6596
}
6642
6597
6643
-
void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6598
+
void intel_dp_mst_suspend(struct intel_display *display)
6644
6599
{
6645
6600
struct intel_encoder *encoder;
6646
6601
6647
-
if (!HAS_DISPLAY(dev_priv))
6602
+
if (!HAS_DISPLAY(display))
6648
6603
return;
6649
6604
6650
-
for_each_intel_encoder(&dev_priv->drm, encoder) {
6605
+
for_each_intel_encoder(display->drm, encoder) {
6651
6606
struct intel_dp *intel_dp;
6652
6607
6653
6608
if (encoder->type != INTEL_OUTPUT_DDI)
···
6663
6618
}
6664
6619
}
6665
6620
6666
-
void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6621
+
void intel_dp_mst_resume(struct intel_display *display)
6667
6622
{
6668
6623
struct intel_encoder *encoder;
6669
6624
6670
-
if (!HAS_DISPLAY(dev_priv))
6625
+
if (!HAS_DISPLAY(display))
6671
6626
return;
6672
6627
6673
-
for_each_intel_encoder(&dev_priv->drm, encoder) {
6628
+
for_each_intel_encoder(display->drm, encoder) {
6674
6629
struct intel_dp *intel_dp;
6675
6630
int ret;
6676
6631
+22
-19
drivers/gpu/drm/i915/display/intel_dp.h
+22
-19
drivers/gpu/drm/i915/display/intel_dp.h
···
12
12
enum pipe;
13
13
enum port;
14
14
struct drm_connector_state;
15
-
struct drm_encoder;
16
-
struct drm_i915_private;
17
-
struct drm_modeset_acquire_ctx;
18
15
struct drm_dp_vsc_sdp;
16
+
struct drm_encoder;
17
+
struct drm_modeset_acquire_ctx;
19
18
struct intel_atomic_state;
20
19
struct intel_connector;
21
20
struct intel_crtc_state;
22
21
struct intel_digital_port;
22
+
struct intel_display;
23
23
struct intel_dp;
24
24
struct intel_encoder;
25
25
···
87
87
bool intel_dp_has_dsc(const struct intel_connector *connector);
88
88
int intel_dp_link_symbol_size(int rate);
89
89
int intel_dp_link_symbol_clock(int rate);
90
-
bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
90
+
bool intel_dp_is_port_edp(struct intel_display *display, enum port port);
91
91
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
92
92
bool long_hpd);
93
93
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
94
94
const struct drm_connector_state *conn_state);
95
95
void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
96
96
void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
97
-
void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
98
-
void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
97
+
void intel_dp_mst_suspend(struct intel_display *display);
98
+
void intel_dp_mst_resume(struct intel_display *display);
99
99
int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port);
100
100
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
101
101
int intel_dp_max_lane_count(struct intel_dp *intel_dp);
···
112
112
113
113
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
114
114
u8 *link_bw, u8 *rate_select);
115
-
bool intel_dp_source_supports_tps3(struct drm_i915_private *i915);
116
-
bool intel_dp_source_supports_tps4(struct drm_i915_private *i915);
115
+
bool intel_dp_source_supports_tps3(struct intel_display *display);
116
+
bool intel_dp_source_supports_tps4(struct intel_display *display);
117
117
118
118
int intel_dp_link_required(int pixel_clock, int bpp);
119
119
int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
120
120
int bw_overhead);
121
121
int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
122
122
int max_dprx_rate, int max_dprx_lanes);
123
-
bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915,
123
+
bool intel_dp_joiner_needs_dsc(struct intel_display *display,
124
124
int num_joined_pipes);
125
125
bool intel_dp_has_joiner(struct intel_dp *intel_dp);
126
126
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
···
137
137
bool intel_digital_port_connected_locked(struct intel_encoder *encoder);
138
138
int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
139
139
u8 dsc_max_bpc);
140
-
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
140
+
u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
141
141
u32 link_clock, u32 lane_count,
142
142
u32 mode_clock, u32 mode_hdisplay,
143
143
int num_joined_pipes,
144
144
enum intel_output_format output_format,
145
145
u32 pipe_bpp,
146
146
u32 timeslots);
147
-
int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
147
+
int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config);
148
148
int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
149
-
struct intel_crtc_state *pipe_config,
149
+
const struct intel_crtc_state *pipe_config,
150
150
int bpc);
151
151
u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
152
152
int mode_clock, int mode_hdisplay,
···
170
170
const struct intel_connector *connector,
171
171
const struct intel_crtc_state *pipe_config);
172
172
173
-
bool intel_dp_supports_dsc(const struct intel_connector *connector,
173
+
bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
174
+
const struct intel_connector *connector,
174
175
const struct intel_crtc_state *crtc_state);
175
176
176
-
u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
177
+
u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp);
177
178
178
179
void intel_ddi_update_pipe(struct intel_atomic_state *state,
179
180
struct intel_encoder *encoder,
···
194
193
void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
195
194
int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
196
195
197
-
bool
198
-
intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
199
-
const struct intel_crtc_state *crtc_state,
200
-
bool dsc,
201
-
struct link_config_limits *limits);
196
+
bool intel_dp_compute_config_limits(struct intel_dp *intel_dp,
197
+
struct intel_crtc_state *crtc_state,
198
+
bool respect_downstream_limits,
199
+
bool dsc,
200
+
struct link_config_limits *limits);
202
201
203
202
void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
204
203
bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder);
···
207
206
u8 lane_count);
208
207
bool intel_dp_has_connector(struct intel_dp *intel_dp,
209
208
const struct drm_connector_state *conn_state);
209
+
int intel_dp_dsc_max_src_input_bpc(struct intel_display *display);
210
+
int intel_dp_dsc_min_src_input_bpc(void);
210
211
211
212
#endif /* __INTEL_DP_H__ */
+1
-1
drivers/gpu/drm/i915/display/intel_dp_aux.c
+1
-1
drivers/gpu/drm/i915/display/intel_dp_aux.c
···
5
5
6
6
#include "i915_drv.h"
7
7
#include "i915_reg.h"
8
-
#include "i915_trace.h"
9
8
#include "intel_de.h"
10
9
#include "intel_display_types.h"
11
10
#include "intel_dp.h"
···
13
14
#include "intel_pps.h"
14
15
#include "intel_quirks.h"
15
16
#include "intel_tc.h"
17
+
#include "intel_uncore_trace.h"
16
18
17
19
#define AUX_CH_NAME_BUFSIZE 6
18
20
+2
-1
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+2
-1
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+7
-10
drivers/gpu/drm/i915/display/intel_dp_link_training.c
+7
-10
drivers/gpu/drm/i915/display/intel_dp_link_training.c
···
25
25
26
26
#include <drm/display/drm_dp_helper.h>
27
27
28
-
#include "i915_drv.h"
28
+
#include "i915_utils.h"
29
+
#include "intel_display_core.h"
29
30
#include "intel_display_types.h"
30
31
#include "intel_dp.h"
31
32
#include "intel_dp_link_training.h"
···
222
221
int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])
223
222
{
224
223
struct intel_display *display = to_intel_display(intel_dp);
225
-
struct drm_i915_private *i915 = to_i915(display->drm);
226
224
227
225
if (intel_dp_is_edp(intel_dp))
228
226
return 0;
···
230
230
* Detecting LTTPRs must be avoided on platforms with an AUX timeout
231
231
* period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
232
232
*/
233
-
if (DISPLAY_VER(display) >= 10 && !IS_GEMINILAKE(i915))
233
+
if (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)
234
234
if (drm_dp_dpcd_probe(&intel_dp->aux,
235
235
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV))
236
236
return -EIO;
···
262
262
int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
263
263
{
264
264
struct intel_display *display = to_intel_display(intel_dp);
265
-
struct drm_i915_private *i915 = to_i915(display->drm);
266
265
int lttpr_count = 0;
267
266
268
267
/*
···
269
270
* period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
270
271
*/
271
272
if (!intel_dp_is_edp(intel_dp) &&
272
-
(DISPLAY_VER(display) >= 10 && !IS_GEMINILAKE(i915))) {
273
+
(DISPLAY_VER(display) >= 10 && !display->platform.geminilake)) {
273
274
u8 dpcd[DP_RECEIVER_CAP_SIZE];
274
275
int err = intel_dp_read_dprx_caps(intel_dp, dpcd);
275
276
···
390
391
enum drm_dp_phy dp_phy)
391
392
{
392
393
struct intel_display *display = to_intel_display(intel_dp);
393
-
struct drm_i915_private *i915 = to_i915(display->drm);
394
394
395
395
return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
396
-
DISPLAY_VER(display) >= 10 || IS_BROXTON(i915);
396
+
DISPLAY_VER(display) >= 10 || display->platform.broxton;
397
397
}
398
398
399
399
/* 128b/132b */
···
957
959
enum drm_dp_phy dp_phy)
958
960
{
959
961
struct intel_display *display = to_intel_display(intel_dp);
960
-
struct drm_i915_private *i915 = to_i915(display->drm);
961
962
bool source_tps3, sink_tps3, source_tps4, sink_tps4;
962
963
963
964
/* UHBR+ use separate 128b/132b TPS2 */
···
969
972
* TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
970
973
* LTTPRs must support TPS4.
971
974
*/
972
-
source_tps4 = intel_dp_source_supports_tps4(i915);
975
+
source_tps4 = intel_dp_source_supports_tps4(display);
973
976
sink_tps4 = dp_phy != DP_PHY_DPRX ||
974
977
drm_dp_tps4_supported(intel_dp->dpcd);
975
978
if (source_tps4 && sink_tps4) {
···
987
990
* TPS3 support is mandatory for downstream devices that
988
991
* support HBR2. However, not all sinks follow the spec.
989
992
*/
990
-
source_tps3 = intel_dp_source_supports_tps3(i915);
993
+
source_tps3 = intel_dp_source_supports_tps3(display);
991
994
sink_tps3 = dp_phy != DP_PHY_DPRX ||
992
995
drm_dp_tps3_supported(intel_dp->dpcd);
993
996
if (source_tps3 && sink_tps3) {
+131
-157
drivers/gpu/drm/i915/display/intel_dp_mst.c
+131
-157
drivers/gpu/drm/i915/display/intel_dp_mst.c
···
139
139
}
140
140
141
141
static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
142
-
const struct intel_connector *connector,
143
142
bool ssc, int dsc_slice_count, int bpp_x16)
144
143
{
145
144
const struct drm_display_mode *adjusted_mode =
···
167
168
}
168
169
169
170
static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
170
-
const struct intel_connector *connector,
171
171
int overhead,
172
172
int bpp_x16,
173
173
struct intel_link_m_n *m_n)
···
209
211
num_joined_pipes);
210
212
}
211
213
212
-
static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
213
-
struct intel_crtc_state *crtc_state,
214
-
int max_bpp, int min_bpp,
215
-
struct link_config_limits *limits,
216
-
struct drm_connector_state *conn_state,
217
-
int step, bool dsc)
214
+
int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
215
+
struct intel_crtc_state *crtc_state,
216
+
int max_bpp, int min_bpp,
217
+
struct drm_connector_state *conn_state,
218
+
int step, bool dsc)
218
219
{
219
220
struct intel_display *display = to_intel_display(intel_dp);
220
221
struct drm_atomic_state *state = crtc_state->uapi.state;
221
-
struct drm_dp_mst_topology_state *mst_state;
222
222
struct intel_connector *connector =
223
223
to_intel_connector(conn_state->connector);
224
224
const struct drm_display_mode *adjusted_mode =
225
225
&crtc_state->hw.adjusted_mode;
226
+
fixed20_12 pbn_div;
226
227
int bpp, slots = -EINVAL;
227
228
int dsc_slice_count = 0;
228
229
int max_dpt_bpp;
229
-
int ret = 0;
230
-
231
-
mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
232
-
if (IS_ERR(mst_state))
233
-
return PTR_ERR(mst_state);
234
-
235
-
crtc_state->lane_count = limits->max_lane_count;
236
-
crtc_state->port_clock = limits->max_rate;
237
230
238
231
if (dsc) {
239
232
if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
···
233
244
crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
234
245
}
235
246
236
-
mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
237
-
crtc_state->port_clock,
238
-
crtc_state->lane_count);
247
+
pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
248
+
crtc_state->lane_count);
239
249
240
250
max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc);
241
251
if (max_bpp > max_dpt_bpp) {
···
257
269
258
270
for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
259
271
int local_bw_overhead;
260
-
int remote_bw_overhead;
261
272
int link_bpp_x16;
262
-
int remote_tu;
263
-
fixed20_12 pbn;
264
273
265
274
drm_dbg_kms(display->drm, "Trying bpp %d\n", bpp);
266
275
267
276
link_bpp_x16 = fxp_q4_from_int(dsc ? bpp :
268
277
intel_dp_output_bpp(crtc_state->output_format, bpp));
269
278
270
-
local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
279
+
local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
271
280
false, dsc_slice_count, link_bpp_x16);
272
-
remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
273
-
true, dsc_slice_count, link_bpp_x16);
274
-
275
-
intel_dp_mst_compute_m_n(crtc_state, connector,
281
+
intel_dp_mst_compute_m_n(crtc_state,
276
282
local_bw_overhead,
277
283
link_bpp_x16,
278
284
&crtc_state->dp_m_n);
279
285
280
-
/*
281
-
* The TU size programmed to the HW determines which slots in
282
-
* an MTP frame are used for this stream, which needs to match
283
-
* the payload size programmed to the first downstream branch
284
-
* device's payload table.
285
-
*
286
-
* Note that atm the payload's PBN value DRM core sends via
287
-
* the ALLOCATE_PAYLOAD side-band message matches the payload
288
-
* size (which it calculates from the PBN value) it programs
289
-
* to the first branch device's payload table. The allocation
290
-
* in the payload table could be reduced though (to
291
-
* crtc_state->dp_m_n.tu), provided that the driver doesn't
292
-
* enable SSC on the corresponding link.
293
-
*/
294
-
pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
295
-
link_bpp_x16,
296
-
remote_bw_overhead));
297
-
remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full);
286
+
if (intel_dp->is_mst) {
287
+
int remote_bw_overhead;
288
+
int remote_tu;
289
+
fixed20_12 pbn;
298
290
299
-
/*
300
-
* Aligning the TUs ensures that symbols consisting of multiple
301
-
* (4) symbol cycles don't get split between two consecutive
302
-
* MTPs, as required by Bspec.
303
-
* TODO: remove the alignment restriction for 128b/132b links
304
-
* on some platforms, where Bspec allows this.
305
-
*/
306
-
remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
291
+
remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
292
+
true, dsc_slice_count, link_bpp_x16);
307
293
308
-
/*
309
-
* Also align PBNs accordingly, since MST core will derive its
310
-
* own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
311
-
* The above comment about the difference between the PBN
312
-
* allocated for the whole path and the TUs allocated for the
313
-
* first branch device's link also applies here.
314
-
*/
315
-
pbn.full = remote_tu * mst_state->pbn_div.full;
316
-
crtc_state->pbn = dfixed_trunc(pbn);
294
+
/*
295
+
* The TU size programmed to the HW determines which slots in
296
+
* an MTP frame are used for this stream, which needs to match
297
+
* the payload size programmed to the first downstream branch
298
+
* device's payload table.
299
+
*
300
+
* Note that atm the payload's PBN value DRM core sends via
301
+
* the ALLOCATE_PAYLOAD side-band message matches the payload
302
+
* size (which it calculates from the PBN value) it programs
303
+
* to the first branch device's payload table. The allocation
304
+
* in the payload table could be reduced though (to
305
+
* crtc_state->dp_m_n.tu), provided that the driver doesn't
306
+
* enable SSC on the corresponding link.
307
+
*/
308
+
pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
309
+
link_bpp_x16,
310
+
remote_bw_overhead));
311
+
remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full);
317
312
318
-
drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
319
-
crtc_state->dp_m_n.tu = remote_tu;
313
+
/*
314
+
* Aligning the TUs ensures that symbols consisting of multiple
315
+
* (4) symbol cycles don't get split between two consecutive
316
+
* MTPs, as required by Bspec.
317
+
* TODO: remove the alignment restriction for 128b/132b links
318
+
* on some platforms, where Bspec allows this.
319
+
*/
320
+
remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
320
321
321
-
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
322
-
connector->port,
323
-
crtc_state->pbn);
322
+
/*
323
+
* Also align PBNs accordingly, since MST core will derive its
324
+
* own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
325
+
* The above comment about the difference between the PBN
326
+
* allocated for the whole path and the TUs allocated for the
327
+
* first branch device's link also applies here.
328
+
*/
329
+
pbn.full = remote_tu * pbn_div.full;
330
+
331
+
drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
332
+
crtc_state->dp_m_n.tu = remote_tu;
333
+
334
+
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
335
+
connector->port,
336
+
dfixed_trunc(pbn));
337
+
} else {
338
+
/* Same as above for remote_tu */
339
+
crtc_state->dp_m_n.tu = ALIGN(crtc_state->dp_m_n.tu,
340
+
4 / crtc_state->lane_count);
341
+
342
+
if (crtc_state->dp_m_n.tu <= 64)
343
+
slots = crtc_state->dp_m_n.tu;
344
+
else
345
+
slots = -EINVAL;
346
+
}
347
+
324
348
if (slots == -EDEADLK)
325
349
return slots;
326
350
···
343
343
}
344
344
}
345
345
346
-
/* We failed to find a proper bpp/timeslots, return error */
347
-
if (ret)
348
-
slots = ret;
349
-
350
346
if (slots < 0) {
351
347
drm_dbg_kms(display->drm, "failed finding vcpi slots:%d\n",
352
348
slots);
353
-
} else {
354
-
if (!dsc)
355
-
crtc_state->pipe_bpp = bpp;
356
-
else
357
-
crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp);
358
-
drm_dbg_kms(display->drm, "Got %d slots for pipe bpp %d dsc %d\n",
359
-
slots, bpp, dsc);
349
+
return slots;
360
350
}
361
351
362
-
return slots;
352
+
if (!dsc)
353
+
crtc_state->pipe_bpp = bpp;
354
+
else
355
+
crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp);
356
+
357
+
drm_dbg_kms(display->drm, "Got %d slots for pipe bpp %d dsc %d\n",
358
+
slots, bpp, dsc);
359
+
360
+
return 0;
361
+
}
362
+
363
+
static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
364
+
struct intel_crtc_state *crtc_state,
365
+
int max_bpp, int min_bpp,
366
+
struct link_config_limits *limits,
367
+
struct drm_connector_state *conn_state,
368
+
int step, bool dsc)
369
+
{
370
+
struct drm_atomic_state *state = crtc_state->uapi.state;
371
+
struct drm_dp_mst_topology_state *mst_state;
372
+
373
+
mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
374
+
if (IS_ERR(mst_state))
375
+
return PTR_ERR(mst_state);
376
+
377
+
crtc_state->lane_count = limits->max_lane_count;
378
+
crtc_state->port_clock = limits->max_rate;
379
+
380
+
mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
381
+
crtc_state->lane_count);
382
+
383
+
return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state,
384
+
max_bpp, min_bpp,
385
+
conn_state, step, dsc);
363
386
}
364
387
365
388
static int mst_stream_compute_link_config(struct intel_dp *intel_dp,
···
390
367
struct drm_connector_state *conn_state,
391
368
struct link_config_limits *limits)
392
369
{
393
-
int slots = -EINVAL;
394
-
395
370
/*
396
371
* FIXME: allocate the BW according to link_bpp, which in the case of
397
372
* YUV420 is only half of the pipe bpp value.
398
373
*/
399
-
slots = mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state,
400
-
fxp_q4_to_int(limits->link.max_bpp_x16),
401
-
fxp_q4_to_int(limits->link.min_bpp_x16),
402
-
limits,
403
-
conn_state, 2 * 3, false);
404
-
405
-
if (slots < 0)
406
-
return slots;
407
-
408
-
return 0;
374
+
return mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state,
375
+
fxp_q4_to_int(limits->link.max_bpp_x16),
376
+
fxp_q4_to_int(limits->link.min_bpp_x16),
377
+
limits,
378
+
conn_state, 2 * 3, false);
409
379
}
410
380
411
381
static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp,
···
408
392
{
409
393
struct intel_display *display = to_intel_display(intel_dp);
410
394
struct intel_connector *connector = to_intel_connector(conn_state->connector);
411
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
412
-
int slots = -EINVAL;
413
395
int i, num_bpc;
414
396
u8 dsc_bpc[3] = {};
415
397
int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
416
-
u8 dsc_max_bpc;
417
398
int min_compressed_bpp, max_compressed_bpp;
418
399
419
-
/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
420
-
if (DISPLAY_VER(display) >= 12)
421
-
dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
422
-
else
423
-
dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
424
-
425
-
max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
400
+
max_bpp = limits->pipe.max_bpp;
426
401
min_bpp = limits->pipe.min_bpp;
427
402
428
403
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
···
443
436
444
437
crtc_state->pipe_bpp = max_bpp;
445
438
446
-
max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
447
-
crtc_state,
448
-
max_bpp / 3);
449
-
max_compressed_bpp = min(max_compressed_bpp,
450
-
fxp_q4_to_int(limits->link.max_bpp_x16));
451
-
452
-
min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
453
-
min_compressed_bpp = max(min_compressed_bpp,
454
-
fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
439
+
max_compressed_bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
440
+
min_compressed_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
455
441
456
442
drm_dbg_kms(display->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",
457
443
min_compressed_bpp, max_compressed_bpp);
458
444
459
445
/* Align compressed bpps according to our own constraints */
460
-
max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,
446
+
max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(display, max_compressed_bpp,
461
447
crtc_state->pipe_bpp);
462
-
min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
448
+
min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(display, min_compressed_bpp,
463
449
crtc_state->pipe_bpp);
464
450
465
-
slots = mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state, max_compressed_bpp,
466
-
min_compressed_bpp, limits,
467
-
conn_state, 1, true);
468
-
469
-
if (slots < 0)
470
-
return slots;
471
-
472
-
return 0;
451
+
return mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state, max_compressed_bpp,
452
+
min_compressed_bpp, limits,
453
+
conn_state, 1, true);
473
454
}
474
455
475
456
static int mst_stream_update_slots(struct intel_dp *intel_dp,
···
515
520
}
516
521
517
522
static bool
518
-
adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *connector,
523
+
adjust_limits_for_dsc_hblank_expansion_quirk(struct intel_dp *intel_dp,
524
+
const struct intel_connector *connector,
519
525
const struct intel_crtc_state *crtc_state,
520
526
struct link_config_limits *limits,
521
527
bool dsc)
···
529
533
return true;
530
534
531
535
if (!dsc) {
532
-
if (intel_dp_supports_dsc(connector, crtc_state)) {
536
+
if (intel_dp_supports_dsc(intel_dp, connector, crtc_state)) {
533
537
drm_dbg_kms(display->drm,
534
538
"[CRTC:%d:%s][CONNECTOR:%d:%s] DSC needed by hblank expansion quirk\n",
535
539
crtc->base.base.id, crtc->base.name,
···
581
585
bool dsc,
582
586
struct link_config_limits *limits)
583
587
{
584
-
/*
585
-
* for MST we always configure max link bw - the spec doesn't
586
-
* seem to suggest we should do otherwise.
587
-
*/
588
-
limits->min_rate = limits->max_rate =
589
-
intel_dp_max_link_rate(intel_dp);
590
-
591
-
limits->min_lane_count = limits->max_lane_count =
592
-
intel_dp_max_lane_count(intel_dp);
593
-
594
-
limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
595
-
/*
596
-
* FIXME: If all the streams can't fit into the link with
597
-
* their current pipe_bpp we should reduce pipe_bpp across
598
-
* the board until things start to fit. Until then we
599
-
* limit to <= 8bpc since that's what was hardcoded for all
600
-
* MST streams previously. This hack should be removed once
601
-
* we have the proper retry logic in place.
602
-
*/
603
-
limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
604
-
605
-
intel_dp_test_compute_config(intel_dp, crtc_state, limits);
606
-
607
-
if (!intel_dp_compute_config_link_bpp_limits(intel_dp,
608
-
crtc_state,
609
-
dsc,
610
-
limits))
588
+
if (!intel_dp_compute_config_limits(intel_dp, crtc_state, false, dsc,
589
+
limits))
611
590
return false;
612
591
613
-
return adjust_limits_for_dsc_hblank_expansion_quirk(connector,
592
+
return adjust_limits_for_dsc_hblank_expansion_quirk(intel_dp,
593
+
connector,
614
594
crtc_state,
615
595
limits,
616
596
dsc);
···
597
625
struct drm_connector_state *conn_state)
598
626
{
599
627
struct intel_display *display = to_intel_display(encoder);
600
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
601
628
struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
602
629
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
603
630
struct intel_dp *intel_dp = to_primary_dp(encoder);
···
626
655
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
627
656
pipe_config->has_pch_encoder = false;
628
657
629
-
joiner_needs_dsc = intel_dp_joiner_needs_dsc(dev_priv, num_joined_pipes);
658
+
joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
630
659
631
660
dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
632
661
!mst_stream_compute_config_limits(intel_dp, connector,
···
643
672
dsc_needed = true;
644
673
}
645
674
675
+
if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) {
676
+
drm_dbg_kms(display->drm, "DSC required but not available\n");
677
+
return -EINVAL;
678
+
}
679
+
646
680
/* enable compression if the mode doesn't fit available BW */
647
681
if (dsc_needed) {
648
682
drm_dbg_kms(display->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
649
683
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
650
684
str_yes_no(intel_dp->force_dsc_en));
651
685
652
-
if (!intel_dp_supports_dsc(connector, pipe_config))
653
-
return -EINVAL;
654
686
655
687
if (!mst_stream_compute_config_limits(intel_dp, connector,
656
688
pipe_config, true,
···
1500
1526
1501
1527
if (drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) {
1502
1528
dsc_max_compressed_bpp =
1503
-
intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1529
+
intel_dp_dsc_get_max_compressed_bpp(display,
1504
1530
max_link_clock,
1505
1531
max_lanes,
1506
1532
target_clock,
···
1518
1544
dsc = dsc_max_compressed_bpp && dsc_slice_count;
1519
1545
}
1520
1546
1521
-
if (intel_dp_joiner_needs_dsc(dev_priv, num_joined_pipes) && !dsc) {
1547
+
if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {
1522
1548
*status = MODE_CLOCK_HIGH;
1523
1549
return 0;
1524
1550
}
+7
drivers/gpu/drm/i915/display/intel_dp_mst.h
+7
drivers/gpu/drm/i915/display/intel_dp_mst.h
···
8
8
9
9
#include <linux/types.h>
10
10
11
+
struct drm_connector_state;
11
12
struct intel_atomic_state;
12
13
struct intel_crtc;
13
14
struct intel_crtc_state;
···
30
29
struct intel_crtc *crtc);
31
30
void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp);
32
31
bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp);
32
+
33
+
int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
34
+
struct intel_crtc_state *crtc_state,
35
+
int max_bpp, int min_bpp,
36
+
struct drm_connector_state *conn_state,
37
+
int step, bool dsc);
33
38
34
39
#endif /* __INTEL_DP_MST_H__ */
-1
drivers/gpu/drm/i915/display/intel_dp_test.c
-1
drivers/gpu/drm/i915/display/intel_dp_test.c
+1
-2
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
+1
-2
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
···
3
3
* Copyright © 2023 Intel Corporation
4
4
*/
5
5
6
-
#include "i915_drv.h"
7
-
8
6
#include <drm/display/drm_dp_tunnel.h>
9
7
10
8
#include "intel_atomic.h"
9
+
#include "intel_display_core.h"
11
10
#include "intel_display_limits.h"
12
11
#include "intel_display_types.h"
13
12
#include "intel_dp.h"
+1
drivers/gpu/drm/i915/display/intel_dpio_phy.c
+1
drivers/gpu/drm/i915/display/intel_dpio_phy.c
+1
drivers/gpu/drm/i915/display/intel_dpll.c
+1
drivers/gpu/drm/i915/display/intel_dpll.c
+1
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+1
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+1
drivers/gpu/drm/i915/display/intel_dpt_common.c
+1
drivers/gpu/drm/i915/display/intel_dpt_common.c
+1
drivers/gpu/drm/i915/display/intel_fdi.c
+1
drivers/gpu/drm/i915/display/intel_fdi.c
+21
-21
drivers/gpu/drm/i915/display/intel_global_state.c
+21
-21
drivers/gpu/drm/i915/display/intel_global_state.c
···
75
75
return obj_state;
76
76
}
77
77
78
-
void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
78
+
void intel_atomic_global_obj_init(struct intel_display *display,
79
79
struct intel_global_obj *obj,
80
80
struct intel_global_state *state,
81
81
const struct intel_global_state_funcs *funcs)
···
88
88
89
89
obj->state = state;
90
90
obj->funcs = funcs;
91
-
list_add_tail(&obj->head, &dev_priv->display.global.obj_list);
91
+
list_add_tail(&obj->head, &display->global.obj_list);
92
92
}
93
93
94
-
void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv)
94
+
void intel_atomic_global_obj_cleanup(struct intel_display *display)
95
95
{
96
96
struct intel_global_obj *obj, *next;
97
97
98
-
list_for_each_entry_safe(obj, next, &dev_priv->display.global.obj_list, head) {
98
+
list_for_each_entry_safe(obj, next, &display->global.obj_list, head) {
99
99
list_del(&obj->head);
100
100
101
-
drm_WARN_ON(&dev_priv->drm, kref_read(&obj->state->ref) != 1);
101
+
drm_WARN_ON(display->drm, kref_read(&obj->state->ref) != 1);
102
102
intel_atomic_global_state_put(obj->state);
103
103
}
104
104
}
105
105
106
-
static void assert_global_state_write_locked(struct drm_i915_private *dev_priv)
106
+
static void assert_global_state_write_locked(struct intel_display *display)
107
107
{
108
108
struct intel_crtc *crtc;
109
109
110
-
for_each_intel_crtc(&dev_priv->drm, crtc)
110
+
for_each_intel_crtc(display->drm, crtc)
111
111
drm_modeset_lock_assert_held(&crtc->base.mutex);
112
112
}
113
113
···
126
126
127
127
static void assert_global_state_read_locked(struct intel_atomic_state *state)
128
128
{
129
+
struct intel_display *display = to_intel_display(state);
129
130
struct drm_modeset_acquire_ctx *ctx = state->base.acquire_ctx;
130
-
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
131
131
struct intel_crtc *crtc;
132
132
133
-
for_each_intel_crtc(&dev_priv->drm, crtc) {
133
+
for_each_intel_crtc(display->drm, crtc) {
134
134
if (modeset_lock_is_held(ctx, &crtc->base.mutex))
135
135
return;
136
136
}
137
137
138
-
drm_WARN(&dev_priv->drm, 1, "Global state not read locked\n");
138
+
drm_WARN(display->drm, 1, "Global state not read locked\n");
139
139
}
140
140
141
141
struct intel_global_state *
142
142
intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
143
143
struct intel_global_obj *obj)
144
144
{
145
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
145
+
struct intel_display *display = to_intel_display(state);
146
146
int index, num_objs, i;
147
147
size_t size;
148
148
struct __intel_global_objs_state *arr;
···
184
184
185
185
state->num_global_objs = num_objs;
186
186
187
-
drm_dbg_atomic(&i915->drm, "Added new global object %p state %p to %p\n",
187
+
drm_dbg_atomic(display->drm, "Added new global object %p state %p to %p\n",
188
188
obj, obj_state, state);
189
189
190
190
return obj_state;
···
218
218
219
219
void intel_atomic_swap_global_state(struct intel_atomic_state *state)
220
220
{
221
-
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
221
+
struct intel_display *display = to_intel_display(state);
222
222
struct intel_global_state *old_obj_state, *new_obj_state;
223
223
struct intel_global_obj *obj;
224
224
int i;
225
225
226
226
for_each_oldnew_global_obj_in_state(state, obj, old_obj_state,
227
227
new_obj_state, i) {
228
-
drm_WARN_ON(&dev_priv->drm, obj->state != old_obj_state);
228
+
drm_WARN_ON(display->drm, obj->state != old_obj_state);
229
229
230
230
/*
231
231
* If the new state wasn't modified (and properly
···
234
234
if (!new_obj_state->changed)
235
235
continue;
236
236
237
-
assert_global_state_write_locked(dev_priv);
237
+
assert_global_state_write_locked(display);
238
238
239
239
old_obj_state->state = state;
240
240
new_obj_state->state = NULL;
···
265
265
int intel_atomic_lock_global_state(struct intel_global_state *obj_state)
266
266
{
267
267
struct intel_atomic_state *state = obj_state->state;
268
-
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
268
+
struct intel_display *display = to_intel_display(state);
269
269
struct intel_crtc *crtc;
270
270
271
-
for_each_intel_crtc(&dev_priv->drm, crtc) {
271
+
for_each_intel_crtc(display->drm, crtc) {
272
272
int ret;
273
273
274
274
ret = drm_modeset_lock(&crtc->base.mutex,
···
298
298
bool
299
299
intel_atomic_global_state_is_serialized(struct intel_atomic_state *state)
300
300
{
301
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
301
+
struct intel_display *display = to_intel_display(state);
302
302
struct intel_crtc *crtc;
303
303
304
-
for_each_intel_crtc(&i915->drm, crtc)
304
+
for_each_intel_crtc(display->drm, crtc)
305
305
if (!intel_atomic_get_new_crtc_state(state, crtc))
306
306
return false;
307
307
return true;
···
344
344
int
345
345
intel_atomic_global_state_wait_for_dependencies(struct intel_atomic_state *state)
346
346
{
347
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
347
+
struct intel_display *display = to_intel_display(state);
348
348
const struct intel_global_state *old_obj_state;
349
349
struct intel_global_obj *obj;
350
350
int i;
···
358
358
359
359
ret = wait_for_completion_timeout(&commit->done, 10 * HZ);
360
360
if (ret == 0) {
361
-
drm_err(&i915->drm, "global state timed out\n");
361
+
drm_err(display->drm, "global state timed out\n");
362
362
return -ETIMEDOUT;
363
363
}
364
364
}
+3
-3
drivers/gpu/drm/i915/display/intel_global_state.h
+3
-3
drivers/gpu/drm/i915/display/intel_global_state.h
···
9
9
#include <linux/kref.h>
10
10
#include <linux/list.h>
11
11
12
-
struct drm_i915_private;
13
12
struct intel_atomic_state;
13
+
struct intel_display;
14
14
struct intel_global_obj;
15
15
struct intel_global_state;
16
16
···
69
69
struct intel_global_state *state, *old_state, *new_state;
70
70
};
71
71
72
-
void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
72
+
void intel_atomic_global_obj_init(struct intel_display *display,
73
73
struct intel_global_obj *obj,
74
74
struct intel_global_state *state,
75
75
const struct intel_global_state_funcs *funcs);
76
-
void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv);
76
+
void intel_atomic_global_obj_cleanup(struct intel_display *display);
77
77
78
78
struct intel_global_state *
79
79
intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
+9
-3
drivers/gpu/drm/i915/display/intel_hdcp.c
+9
-3
drivers/gpu/drm/i915/display/intel_hdcp.c
···
1166
1166
goto out;
1167
1167
}
1168
1168
1169
-
intel_hdcp_update_value(connector,
1170
-
DRM_MODE_CONTENT_PROTECTION_DESIRED,
1171
-
true);
1169
+
ret = intel_hdcp1_enable(connector);
1170
+
if (ret) {
1171
+
drm_err(display->drm, "Failed to enable hdcp (%d)\n", ret);
1172
+
intel_hdcp_update_value(connector,
1173
+
DRM_MODE_CONTENT_PROTECTION_DESIRED,
1174
+
true);
1175
+
goto out;
1176
+
}
1177
+
1172
1178
out:
1173
1179
mutex_unlock(&dig_port->hdcp_mutex);
1174
1180
mutex_unlock(&hdcp->mutex);
+6
-4
drivers/gpu/drm/i915/display/intel_hdmi.c
+6
-4
drivers/gpu/drm/i915/display/intel_hdmi.c
···
3039
3039
}
3040
3040
}
3041
3041
3042
-
void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
3042
+
bool intel_hdmi_init_connector(struct intel_digital_port *dig_port,
3043
3043
struct intel_connector *intel_connector)
3044
3044
{
3045
3045
struct intel_display *display = to_intel_display(dig_port);
···
3056
3056
intel_encoder->base.base.id, intel_encoder->base.name);
3057
3057
3058
3058
if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A))
3059
-
return;
3059
+
return false;
3060
3060
3061
3061
if (drm_WARN(dev, dig_port->max_lanes < 4,
3062
3062
"Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3063
3063
dig_port->max_lanes, intel_encoder->base.base.id,
3064
3064
intel_encoder->base.name))
3065
-
return;
3065
+
return false;
3066
3066
3067
3067
ddc_pin = intel_hdmi_ddc_pin(intel_encoder);
3068
3068
if (!ddc_pin)
3069
-
return;
3069
+
return false;
3070
3070
3071
3071
drm_connector_init_with_ddc(dev, connector,
3072
3072
&intel_hdmi_connector_funcs,
···
3111
3111
&conn_info);
3112
3112
if (!intel_hdmi->cec_notifier)
3113
3113
drm_dbg_kms(display->drm, "CEC notifier get failed\n");
3114
+
3115
+
return true;
3114
3116
}
3115
3117
3116
3118
/*
+1
-1
drivers/gpu/drm/i915/display/intel_hdmi.h
+1
-1
drivers/gpu/drm/i915/display/intel_hdmi.h
···
22
22
struct intel_hdmi;
23
23
union hdmi_infoframe;
24
24
25
-
void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
25
+
bool intel_hdmi_init_connector(struct intel_digital_port *dig_port,
26
26
struct intel_connector *intel_connector);
27
27
bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder,
28
28
const struct intel_crtc_state *crtc_state,
+2
-1
drivers/gpu/drm/i915/display/intel_hti.c
+2
-1
drivers/gpu/drm/i915/display/intel_hti.c
+1
-2
drivers/gpu/drm/i915/display/intel_link_bw.c
+1
-2
drivers/gpu/drm/i915/display/intel_link_bw.c
+1
-1
drivers/gpu/drm/i915/display/intel_load_detect.c
+1
-1
drivers/gpu/drm/i915/display/intel_load_detect.c
+2
-1
drivers/gpu/drm/i915/display/intel_lspcon.c
+2
-1
drivers/gpu/drm/i915/display/intel_lspcon.c
···
29
29
#include <drm/drm_edid.h>
30
30
31
31
#include "i915_reg.h"
32
+
#include "i915_utils.h"
32
33
#include "intel_de.h"
33
34
#include "intel_display_types.h"
34
35
#include "intel_dp.h"
35
-
#include "intel_lspcon.h"
36
36
#include "intel_hdmi.h"
37
+
#include "intel_lspcon.h"
37
38
38
39
/* LSPCON OUI Vendor ID(signatures) */
39
40
#define LSPCON_VENDOR_PARADE_OUI 0x001CF8
+10
-7
drivers/gpu/drm/i915/display/intel_modeset_setup.c
+10
-7
drivers/gpu/drm/i915/display/intel_modeset_setup.c
···
116
116
117
117
static void reset_encoder_connector_state(struct intel_encoder *encoder)
118
118
{
119
+
struct intel_display *display = to_intel_display(encoder);
119
120
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
120
121
struct intel_pmdemand_state *pmdemand_state =
121
122
to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
···
129
128
continue;
130
129
131
130
/* Clear the corresponding bit in pmdemand active phys mask */
132
-
intel_pmdemand_update_phys_mask(i915, encoder,
131
+
intel_pmdemand_update_phys_mask(display, encoder,
133
132
pmdemand_state, false);
134
133
135
134
set_encoder_for_connector(connector, NULL);
···
153
152
154
153
static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
155
154
{
155
+
struct intel_display *display = to_intel_display(crtc);
156
156
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
157
157
struct intel_bw_state *bw_state =
158
158
to_intel_bw_state(i915->display.bw.obj.state);
···
187
185
bw_state->data_rate[pipe] = 0;
188
186
bw_state->num_active_planes[pipe] = 0;
189
187
190
-
intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe, 0);
188
+
intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, 0);
191
189
}
192
190
193
191
/*
···
584
582
585
583
static void intel_sanitize_encoder(struct intel_encoder *encoder)
586
584
{
585
+
struct intel_display *display = to_intel_display(encoder);
587
586
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
588
587
struct intel_connector *connector;
589
588
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
···
616
613
encoder->base.name);
617
614
618
615
/* Clear the corresponding bit in pmdemand active phys mask */
619
-
intel_pmdemand_update_phys_mask(i915, encoder,
616
+
intel_pmdemand_update_phys_mask(display, encoder,
620
617
pmdemand_state, false);
621
618
622
619
/*
···
773
770
}
774
771
}
775
772
776
-
intel_pmdemand_update_phys_mask(i915, encoder,
773
+
intel_pmdemand_update_phys_mask(display, encoder,
777
774
pmdemand_state,
778
775
true);
779
776
} else {
780
-
intel_pmdemand_update_phys_mask(i915, encoder,
777
+
intel_pmdemand_update_phys_mask(display, encoder,
781
778
pmdemand_state,
782
779
false);
783
780
···
902
899
cdclk_state->min_voltage_level[crtc->pipe] =
903
900
crtc_state->min_voltage_level;
904
901
905
-
intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe,
902
+
intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,
906
903
crtc_state->port_clock);
907
904
908
905
intel_bw_crtc_update(bw_state, crtc_state);
909
906
}
910
907
911
-
intel_pmdemand_init_pmdemand_params(i915, pmdemand_state);
908
+
intel_pmdemand_init_pmdemand_params(display, pmdemand_state);
912
909
}
913
910
914
911
static void
-1
drivers/gpu/drm/i915/display/intel_panel.c
-1
drivers/gpu/drm/i915/display/intel_panel.c
+1
drivers/gpu/drm/i915/display/intel_pch_display.c
+1
drivers/gpu/drm/i915/display/intel_pch_display.c
+1
drivers/gpu/drm/i915/display/intel_pch_refclk.c
+1
drivers/gpu/drm/i915/display/intel_pch_refclk.c
+1
-1
drivers/gpu/drm/i915/display/intel_pfit.c
+1
-1
drivers/gpu/drm/i915/display/intel_pfit.c
+1
drivers/gpu/drm/i915/display/intel_pipe_crc.c
+1
drivers/gpu/drm/i915/display/intel_pipe_crc.c
+114
-81
drivers/gpu/drm/i915/display/intel_pmdemand.c
+114
-81
drivers/gpu/drm/i915/display/intel_pmdemand.c
···
5
5
6
6
#include <linux/bitops.h>
7
7
8
-
#include "i915_drv.h"
9
8
#include "i915_reg.h"
9
+
#include "i915_utils.h"
10
10
#include "intel_atomic.h"
11
11
#include "intel_bw.h"
12
12
#include "intel_cdclk.h"
13
13
#include "intel_de.h"
14
14
#include "intel_display_trace.h"
15
15
#include "intel_pmdemand.h"
16
+
#include "intel_step.h"
16
17
#include "skl_watermark.h"
18
+
19
+
struct pmdemand_params {
20
+
u16 qclk_gv_bw;
21
+
u8 voltage_index;
22
+
u8 qclk_gv_index;
23
+
u8 active_pipes;
24
+
u8 active_dbufs; /* pre-Xe3 only */
25
+
/* Total number of non type C active phys from active_phys_mask */
26
+
u8 active_phys;
27
+
u8 plls;
28
+
u16 cdclk_freq_mhz;
29
+
/* max from ddi_clocks[] */
30
+
u16 ddiclk_max;
31
+
u8 scalers; /* pre-Xe3 only */
32
+
};
33
+
34
+
struct intel_pmdemand_state {
35
+
struct intel_global_state base;
36
+
37
+
/* Maintain a persistent list of port clocks across all crtcs */
38
+
int ddi_clocks[I915_MAX_PIPES];
39
+
40
+
/* Maintain a persistent list of non type C phys mask */
41
+
u16 active_combo_phys_mask;
42
+
43
+
/* Parameters to be configured in the pmdemand registers */
44
+
struct pmdemand_params params;
45
+
};
46
+
47
+
struct intel_pmdemand_state *to_intel_pmdemand_state(struct intel_global_state *obj_state)
48
+
{
49
+
return container_of(obj_state, struct intel_pmdemand_state, base);
50
+
}
17
51
18
52
static struct intel_global_state *
19
53
intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
···
75
41
static struct intel_pmdemand_state *
76
42
intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
77
43
{
78
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
44
+
struct intel_display *display = to_intel_display(state);
79
45
struct intel_global_state *pmdemand_state =
80
46
intel_atomic_get_global_obj_state(state,
81
-
&i915->display.pmdemand.obj);
47
+
&display->pmdemand.obj);
82
48
83
49
if (IS_ERR(pmdemand_state))
84
50
return ERR_CAST(pmdemand_state);
···
89
55
static struct intel_pmdemand_state *
90
56
intel_atomic_get_old_pmdemand_state(struct intel_atomic_state *state)
91
57
{
92
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
58
+
struct intel_display *display = to_intel_display(state);
93
59
struct intel_global_state *pmdemand_state =
94
60
intel_atomic_get_old_global_obj_state(state,
95
-
&i915->display.pmdemand.obj);
61
+
&display->pmdemand.obj);
96
62
97
63
if (!pmdemand_state)
98
64
return NULL;
···
103
69
static struct intel_pmdemand_state *
104
70
intel_atomic_get_new_pmdemand_state(struct intel_atomic_state *state)
105
71
{
106
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
72
+
struct intel_display *display = to_intel_display(state);
107
73
struct intel_global_state *pmdemand_state =
108
74
intel_atomic_get_new_global_obj_state(state,
109
-
&i915->display.pmdemand.obj);
75
+
&display->pmdemand.obj);
110
76
111
77
if (!pmdemand_state)
112
78
return NULL;
···
114
80
return to_intel_pmdemand_state(pmdemand_state);
115
81
}
116
82
117
-
int intel_pmdemand_init(struct drm_i915_private *i915)
83
+
int intel_pmdemand_init(struct intel_display *display)
118
84
{
119
85
struct intel_pmdemand_state *pmdemand_state;
120
86
···
122
88
if (!pmdemand_state)
123
89
return -ENOMEM;
124
90
125
-
intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj,
91
+
intel_atomic_global_obj_init(display, &display->pmdemand.obj,
126
92
&pmdemand_state->base,
127
93
&intel_pmdemand_funcs);
128
94
129
-
if (IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_A0, STEP_C0))
95
+
if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0))
130
96
/* Wa_14016740474 */
131
-
intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
97
+
intel_de_rmw(display, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
132
98
133
99
return 0;
134
100
}
135
101
136
-
void intel_pmdemand_init_early(struct drm_i915_private *i915)
102
+
void intel_pmdemand_init_early(struct intel_display *display)
137
103
{
138
-
mutex_init(&i915->display.pmdemand.lock);
139
-
init_waitqueue_head(&i915->display.pmdemand.waitqueue);
104
+
mutex_init(&display->pmdemand.lock);
105
+
init_waitqueue_head(&display->pmdemand.waitqueue);
140
106
}
141
107
142
108
void
143
-
intel_pmdemand_update_phys_mask(struct drm_i915_private *i915,
109
+
intel_pmdemand_update_phys_mask(struct intel_display *display,
144
110
struct intel_encoder *encoder,
145
111
struct intel_pmdemand_state *pmdemand_state,
146
112
bool set_bit)
147
113
{
148
114
enum phy phy;
149
115
150
-
if (DISPLAY_VER(i915) < 14)
116
+
if (DISPLAY_VER(display) < 14)
151
117
return;
152
118
153
119
if (!encoder)
···
165
131
}
166
132
167
133
void
168
-
intel_pmdemand_update_port_clock(struct drm_i915_private *i915,
134
+
intel_pmdemand_update_port_clock(struct intel_display *display,
169
135
struct intel_pmdemand_state *pmdemand_state,
170
136
enum pipe pipe, int port_clock)
171
137
{
172
-
if (DISPLAY_VER(i915) < 14)
138
+
if (DISPLAY_VER(display) < 14)
173
139
return;
174
140
175
141
pmdemand_state->ddi_clocks[pipe] = port_clock;
176
142
}
177
143
178
144
static void
179
-
intel_pmdemand_update_max_ddiclk(struct drm_i915_private *i915,
145
+
intel_pmdemand_update_max_ddiclk(struct intel_display *display,
180
146
struct intel_atomic_state *state,
181
147
struct intel_pmdemand_state *pmdemand_state)
182
148
{
···
186
152
int i;
187
153
188
154
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
189
-
intel_pmdemand_update_port_clock(i915, pmdemand_state,
155
+
intel_pmdemand_update_port_clock(display, pmdemand_state,
190
156
crtc->pipe,
191
157
new_crtc_state->port_clock);
192
158
···
197
163
}
198
164
199
165
static void
200
-
intel_pmdemand_update_connector_phys(struct drm_i915_private *i915,
166
+
intel_pmdemand_update_connector_phys(struct intel_display *display,
201
167
struct intel_atomic_state *state,
202
168
struct drm_connector_state *conn_state,
203
169
bool set_bit,
···
218
184
if (!crtc_state->hw.active)
219
185
return;
220
186
221
-
intel_pmdemand_update_phys_mask(i915, encoder, pmdemand_state,
187
+
intel_pmdemand_update_phys_mask(display, encoder, pmdemand_state,
222
188
set_bit);
223
189
}
224
190
225
191
static void
226
-
intel_pmdemand_update_active_non_tc_phys(struct drm_i915_private *i915,
192
+
intel_pmdemand_update_active_non_tc_phys(struct intel_display *display,
227
193
struct intel_atomic_state *state,
228
194
struct intel_pmdemand_state *pmdemand_state)
229
195
{
···
238
204
continue;
239
205
240
206
/* First clear the active phys in the old connector state */
241
-
intel_pmdemand_update_connector_phys(i915, state,
207
+
intel_pmdemand_update_connector_phys(display, state,
242
208
old_conn_state, false,
243
209
pmdemand_state);
244
210
245
211
/* Then set the active phys in new connector state */
246
-
intel_pmdemand_update_connector_phys(i915, state,
212
+
intel_pmdemand_update_connector_phys(display, state,
247
213
new_conn_state, true,
248
214
pmdemand_state);
249
215
}
···
254
220
}
255
221
256
222
static bool
257
-
intel_pmdemand_encoder_has_tc_phy(struct drm_i915_private *i915,
223
+
intel_pmdemand_encoder_has_tc_phy(struct intel_display *display,
258
224
struct intel_encoder *encoder)
259
225
{
260
226
return encoder && intel_encoder_is_tc(encoder);
···
263
229
static bool
264
230
intel_pmdemand_connector_needs_update(struct intel_atomic_state *state)
265
231
{
266
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
232
+
struct intel_display *display = to_intel_display(state);
267
233
struct drm_connector_state *old_conn_state;
268
234
struct drm_connector_state *new_conn_state;
269
235
struct drm_connector *connector;
···
280
246
continue;
281
247
282
248
if (old_encoder == new_encoder ||
283
-
(intel_pmdemand_encoder_has_tc_phy(i915, old_encoder) &&
284
-
intel_pmdemand_encoder_has_tc_phy(i915, new_encoder)))
249
+
(intel_pmdemand_encoder_has_tc_phy(display, old_encoder) &&
250
+
intel_pmdemand_encoder_has_tc_phy(display, new_encoder)))
285
251
continue;
286
252
287
253
return true;
···
338
304
339
305
int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
340
306
{
341
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
307
+
struct intel_display *display = to_intel_display(state);
342
308
const struct intel_bw_state *new_bw_state;
343
309
const struct intel_cdclk_state *new_cdclk_state;
344
310
const struct intel_dbuf_state *new_dbuf_state;
345
311
struct intel_pmdemand_state *new_pmdemand_state;
346
312
347
-
if (DISPLAY_VER(i915) < 14)
313
+
if (DISPLAY_VER(display) < 14)
348
314
return 0;
349
315
350
316
if (!intel_pmdemand_needs_update(state))
···
366
332
if (IS_ERR(new_dbuf_state))
367
333
return PTR_ERR(new_dbuf_state);
368
334
369
-
if (DISPLAY_VER(i915) < 30) {
335
+
if (DISPLAY_VER(display) < 30) {
370
336
new_pmdemand_state->params.active_dbufs =
371
337
min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3);
372
338
new_pmdemand_state->params.active_pipes =
373
339
min_t(u8, hweight8(new_dbuf_state->active_pipes), 3);
374
340
} else {
375
341
new_pmdemand_state->params.active_pipes =
376
-
min_t(u8, hweight8(new_dbuf_state->active_pipes), INTEL_NUM_PIPES(i915));
342
+
min_t(u8, hweight8(new_dbuf_state->active_pipes), INTEL_NUM_PIPES(display));
377
343
}
378
344
379
345
new_cdclk_state = intel_atomic_get_cdclk_state(state);
···
385
351
new_pmdemand_state->params.cdclk_freq_mhz =
386
352
DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000);
387
353
388
-
intel_pmdemand_update_max_ddiclk(i915, state, new_pmdemand_state);
354
+
intel_pmdemand_update_max_ddiclk(display, state, new_pmdemand_state);
389
355
390
-
intel_pmdemand_update_active_non_tc_phys(i915, state, new_pmdemand_state);
356
+
intel_pmdemand_update_active_non_tc_phys(display, state, new_pmdemand_state);
391
357
392
358
/*
393
359
* Active_PLLs starts with 1 because of CDCLK PLL.
···
408
374
return intel_atomic_lock_global_state(&new_pmdemand_state->base);
409
375
}
410
376
411
-
static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *i915)
377
+
static bool intel_pmdemand_check_prev_transaction(struct intel_display *display)
412
378
{
413
-
return !(intel_de_wait_for_clear(i915,
379
+
return !(intel_de_wait_for_clear(display,
414
380
XELPDP_INITIATE_PMDEMAND_REQUEST(1),
415
381
XELPDP_PMDEMAND_REQ_ENABLE, 10) ||
416
-
intel_de_wait_for_clear(i915,
382
+
intel_de_wait_for_clear(display,
417
383
GEN12_DCPR_STATUS_1,
418
384
XELPDP_PMDEMAND_INFLIGHT_STATUS, 10));
419
385
}
420
386
421
387
void
422
-
intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915,
388
+
intel_pmdemand_init_pmdemand_params(struct intel_display *display,
423
389
struct intel_pmdemand_state *pmdemand_state)
424
390
{
425
391
u32 reg1, reg2;
426
392
427
-
if (DISPLAY_VER(i915) < 14)
393
+
if (DISPLAY_VER(display) < 14)
428
394
return;
429
395
430
-
mutex_lock(&i915->display.pmdemand.lock);
431
-
if (drm_WARN_ON(&i915->drm,
432
-
!intel_pmdemand_check_prev_transaction(i915))) {
396
+
mutex_lock(&display->pmdemand.lock);
397
+
if (drm_WARN_ON(display->drm,
398
+
!intel_pmdemand_check_prev_transaction(display))) {
433
399
memset(&pmdemand_state->params, 0,
434
400
sizeof(pmdemand_state->params));
435
401
goto unlock;
436
402
}
437
403
438
-
reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
404
+
reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
439
405
440
-
reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
406
+
reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
441
407
442
408
pmdemand_state->params.qclk_gv_bw =
443
409
REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1);
···
453
419
pmdemand_state->params.ddiclk_max =
454
420
REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2);
455
421
456
-
if (DISPLAY_VER(i915) >= 30) {
422
+
if (DISPLAY_VER(display) >= 30) {
457
423
pmdemand_state->params.active_pipes =
458
424
REG_FIELD_GET(XE3_PMDEMAND_PIPES_MASK, reg1);
459
425
} else {
···
467
433
}
468
434
469
435
unlock:
470
-
mutex_unlock(&i915->display.pmdemand.lock);
436
+
mutex_unlock(&display->pmdemand.lock);
471
437
}
472
438
473
-
static bool intel_pmdemand_req_complete(struct drm_i915_private *i915)
439
+
static bool intel_pmdemand_req_complete(struct intel_display *display)
474
440
{
475
-
return !(intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
441
+
return !(intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
476
442
XELPDP_PMDEMAND_REQ_ENABLE);
477
443
}
478
444
479
-
static void intel_pmdemand_wait(struct drm_i915_private *i915)
445
+
static void intel_pmdemand_wait(struct intel_display *display)
480
446
{
481
-
if (!wait_event_timeout(i915->display.pmdemand.waitqueue,
482
-
intel_pmdemand_req_complete(i915),
447
+
if (!wait_event_timeout(display->pmdemand.waitqueue,
448
+
intel_pmdemand_req_complete(display),
483
449
msecs_to_jiffies_timeout(10)))
484
-
drm_err(&i915->drm,
450
+
drm_err(display->drm,
485
451
"timed out waiting for Punit PM Demand Response\n");
486
452
}
487
453
488
454
/* Required to be programmed during Display Init Sequences. */
489
-
void intel_pmdemand_program_dbuf(struct drm_i915_private *i915,
455
+
void intel_pmdemand_program_dbuf(struct intel_display *display,
490
456
u8 dbuf_slices)
491
457
{
492
458
u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
493
459
494
460
/* PM Demand only tracks active dbufs on pre-Xe3 platforms */
495
-
if (DISPLAY_VER(i915) >= 30)
461
+
if (DISPLAY_VER(display) >= 30)
496
462
return;
497
463
498
-
mutex_lock(&i915->display.pmdemand.lock);
499
-
if (drm_WARN_ON(&i915->drm,
500
-
!intel_pmdemand_check_prev_transaction(i915)))
464
+
mutex_lock(&display->pmdemand.lock);
465
+
if (drm_WARN_ON(display->drm,
466
+
!intel_pmdemand_check_prev_transaction(display)))
501
467
goto unlock;
502
468
503
-
intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
469
+
intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
504
470
XELPDP_PMDEMAND_DBUFS_MASK,
505
471
REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, dbufs));
506
-
intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
472
+
intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
507
473
XELPDP_PMDEMAND_REQ_ENABLE);
508
474
509
-
intel_pmdemand_wait(i915);
475
+
intel_pmdemand_wait(display);
510
476
511
477
unlock:
512
-
mutex_unlock(&i915->display.pmdemand.lock);
478
+
mutex_unlock(&display->pmdemand.lock);
513
479
}
514
480
515
481
static void
···
569
535
}
570
536
571
537
static void
572
-
intel_pmdemand_program_params(struct drm_i915_private *i915,
538
+
intel_pmdemand_program_params(struct intel_display *display,
573
539
const struct intel_pmdemand_state *new,
574
540
const struct intel_pmdemand_state *old,
575
541
bool serialized)
576
542
{
577
-
struct intel_display *display = &i915->display;
578
543
bool changed = false;
579
544
u32 reg1, mod_reg1;
580
545
u32 reg2, mod_reg2;
581
546
582
-
mutex_lock(&i915->display.pmdemand.lock);
583
-
if (drm_WARN_ON(&i915->drm,
584
-
!intel_pmdemand_check_prev_transaction(i915)))
547
+
mutex_lock(&display->pmdemand.lock);
548
+
if (drm_WARN_ON(display->drm,
549
+
!intel_pmdemand_check_prev_transaction(display)))
585
550
goto unlock;
586
551
587
-
reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
552
+
reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
588
553
mod_reg1 = reg1;
589
554
590
-
reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
555
+
reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
591
556
mod_reg2 = reg2;
592
557
593
558
intel_pmdemand_update_params(display, new, old, &mod_reg1, &mod_reg2,
594
559
serialized);
595
560
596
561
if (reg1 != mod_reg1) {
597
-
intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
562
+
intel_de_write(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
598
563
mod_reg1);
599
564
changed = true;
600
565
}
601
566
602
567
if (reg2 != mod_reg2) {
603
-
intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
568
+
intel_de_write(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
604
569
mod_reg2);
605
570
changed = true;
606
571
}
···
608
575
if (!changed)
609
576
goto unlock;
610
577
611
-
drm_dbg_kms(&i915->drm,
578
+
drm_dbg_kms(display->drm,
612
579
"initate pmdemand request values: (0x%x 0x%x)\n",
613
580
mod_reg1, mod_reg2);
614
581
615
-
intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
582
+
intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
616
583
XELPDP_PMDEMAND_REQ_ENABLE);
617
584
618
-
intel_pmdemand_wait(i915);
585
+
intel_pmdemand_wait(display);
619
586
620
587
unlock:
621
-
mutex_unlock(&i915->display.pmdemand.lock);
588
+
mutex_unlock(&display->pmdemand.lock);
622
589
}
623
590
624
591
static bool
···
630
597
631
598
void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
632
599
{
633
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
600
+
struct intel_display *display = to_intel_display(state);
634
601
const struct intel_pmdemand_state *new_pmdemand_state =
635
602
intel_atomic_get_new_pmdemand_state(state);
636
603
const struct intel_pmdemand_state *old_pmdemand_state =
637
604
intel_atomic_get_old_pmdemand_state(state);
638
605
639
-
if (DISPLAY_VER(i915) < 14)
606
+
if (DISPLAY_VER(display) < 14)
640
607
return;
641
608
642
609
if (!new_pmdemand_state ||
···
646
613
647
614
WARN_ON(!new_pmdemand_state->base.changed);
648
615
649
-
intel_pmdemand_program_params(i915, new_pmdemand_state,
616
+
intel_pmdemand_program_params(display, new_pmdemand_state,
650
617
old_pmdemand_state,
651
618
intel_atomic_global_state_is_serialized(state));
652
619
}
653
620
654
621
void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
655
622
{
656
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
623
+
struct intel_display *display = to_intel_display(state);
657
624
const struct intel_pmdemand_state *new_pmdemand_state =
658
625
intel_atomic_get_new_pmdemand_state(state);
659
626
const struct intel_pmdemand_state *old_pmdemand_state =
660
627
intel_atomic_get_old_pmdemand_state(state);
661
628
662
-
if (DISPLAY_VER(i915) < 14)
629
+
if (DISPLAY_VER(display) < 14)
663
630
return;
664
631
665
632
if (!new_pmdemand_state ||
···
669
636
670
637
WARN_ON(!new_pmdemand_state->base.changed);
671
638
672
-
intel_pmdemand_program_params(i915, new_pmdemand_state, NULL,
639
+
intel_pmdemand_program_params(display, new_pmdemand_state, NULL,
673
640
intel_atomic_global_state_is_serialized(state));
674
641
}
+12
-39
drivers/gpu/drm/i915/display/intel_pmdemand.h
+12
-39
drivers/gpu/drm/i915/display/intel_pmdemand.h
···
6
6
#ifndef __INTEL_PMDEMAND_H__
7
7
#define __INTEL_PMDEMAND_H__
8
8
9
-
#include "intel_display_limits.h"
10
-
#include "intel_global_state.h"
9
+
#include <linux/types.h>
11
10
12
-
struct drm_i915_private;
11
+
enum pipe;
13
12
struct intel_atomic_state;
14
13
struct intel_crtc_state;
14
+
struct intel_display;
15
15
struct intel_encoder;
16
+
struct intel_global_state;
16
17
struct intel_plane_state;
18
+
struct intel_pmdemand_state;
17
19
18
-
struct pmdemand_params {
19
-
u16 qclk_gv_bw;
20
-
u8 voltage_index;
21
-
u8 qclk_gv_index;
22
-
u8 active_pipes;
23
-
u8 active_dbufs; /* pre-Xe3 only */
24
-
/* Total number of non type C active phys from active_phys_mask */
25
-
u8 active_phys;
26
-
u8 plls;
27
-
u16 cdclk_freq_mhz;
28
-
/* max from ddi_clocks[] */
29
-
u16 ddiclk_max;
30
-
u8 scalers; /* pre-Xe3 only */
31
-
};
20
+
struct intel_pmdemand_state *to_intel_pmdemand_state(struct intel_global_state *obj_state);
32
21
33
-
struct intel_pmdemand_state {
34
-
struct intel_global_state base;
35
-
36
-
/* Maintain a persistent list of port clocks across all crtcs */
37
-
int ddi_clocks[I915_MAX_PIPES];
38
-
39
-
/* Maintain a persistent list of non type C phys mask */
40
-
u16 active_combo_phys_mask;
41
-
42
-
/* Parameters to be configured in the pmdemand registers */
43
-
struct pmdemand_params params;
44
-
};
45
-
46
-
#define to_intel_pmdemand_state(global_state) \
47
-
container_of_const((global_state), struct intel_pmdemand_state, base)
48
-
49
-
void intel_pmdemand_init_early(struct drm_i915_private *i915);
50
-
int intel_pmdemand_init(struct drm_i915_private *i915);
51
-
void intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915,
22
+
void intel_pmdemand_init_early(struct intel_display *display);
23
+
int intel_pmdemand_init(struct intel_display *display);
24
+
void intel_pmdemand_init_pmdemand_params(struct intel_display *display,
52
25
struct intel_pmdemand_state *pmdemand_state);
53
-
void intel_pmdemand_update_port_clock(struct drm_i915_private *i915,
26
+
void intel_pmdemand_update_port_clock(struct intel_display *display,
54
27
struct intel_pmdemand_state *pmdemand_state,
55
28
enum pipe pipe, int port_clock);
56
-
void intel_pmdemand_update_phys_mask(struct drm_i915_private *i915,
29
+
void intel_pmdemand_update_phys_mask(struct intel_display *display,
57
30
struct intel_encoder *encoder,
58
31
struct intel_pmdemand_state *pmdemand_state,
59
32
bool clear_bit);
60
-
void intel_pmdemand_program_dbuf(struct drm_i915_private *i915,
33
+
void intel_pmdemand_program_dbuf(struct intel_display *display,
61
34
u8 dbuf_slices);
62
35
void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
63
36
void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
+1
-1
drivers/gpu/drm/i915/display/intel_psr.c
+1
-1
drivers/gpu/drm/i915/display/intel_psr.c
+1
-1
drivers/gpu/drm/i915/display/intel_quirks.c
+1
-1
drivers/gpu/drm/i915/display/intel_quirks.c
+1
drivers/gpu/drm/i915/display/intel_snps_phy.c
+1
drivers/gpu/drm/i915/display/intel_snps_phy.c
-1
drivers/gpu/drm/i915/display/intel_vrr.c
-1
drivers/gpu/drm/i915/display/intel_vrr.c
+1
drivers/gpu/drm/i915/display/skl_scaler.c
+1
drivers/gpu/drm/i915/display/skl_scaler.c
+26
drivers/gpu/drm/i915/display/skl_universal_plane.c
+26
drivers/gpu/drm/i915/display/skl_universal_plane.c
···
717
717
PLANE_BUF_START(entry->start);
718
718
}
719
719
720
+
static u32 xe3_plane_min_ddb_reg_val(const u16 *min_ddb,
721
+
const u16 *interim_ddb)
722
+
{
723
+
u32 val = 0;
724
+
725
+
if (*min_ddb)
726
+
val |= PLANE_MIN_DBUF_BLOCKS(*min_ddb);
727
+
728
+
if (*interim_ddb)
729
+
val |= PLANE_INTERIM_DBUF_BLOCKS(*interim_ddb);
730
+
731
+
val |= val ? PLANE_AUTO_MIN_DBUF_EN : 0;
732
+
733
+
return val;
734
+
}
735
+
720
736
static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
721
737
{
722
738
u32 val = 0;
···
741
725
val |= PLANE_WM_EN;
742
726
if (level->ignore_lines)
743
727
val |= PLANE_WM_IGNORE_LINES;
728
+
if (level->auto_min_alloc_wm_enable)
729
+
val |= PLANE_WM_AUTO_MIN_ALLOC_EN;
730
+
744
731
val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
745
732
val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
746
733
···
762
743
&crtc_state->wm.skl.plane_ddb[plane_id];
763
744
const struct skl_ddb_entry *ddb_y =
764
745
&crtc_state->wm.skl.plane_ddb_y[plane_id];
746
+
const u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id];
747
+
const u16 *interim_ddb =
748
+
&crtc_state->wm.skl.plane_interim_ddb[plane_id];
765
749
int level;
766
750
767
751
for (level = 0; level < display->wm.num_levels; level++)
···
789
767
if (DISPLAY_VER(display) < 11)
790
768
intel_de_write_dsb(display, dsb, PLANE_NV12_BUF_CFG(pipe, plane_id),
791
769
skl_plane_ddb_reg_val(ddb_y));
770
+
771
+
if (DISPLAY_VER(display) >= 30)
772
+
intel_de_write_dsb(display, dsb, PLANE_MIN_BUF_CFG(pipe, plane_id),
773
+
xe3_plane_min_ddb_reg_val(min_ddb, interim_ddb));
792
774
}
793
775
794
776
static void
+15
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+15
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
···
322
322
_PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
323
323
#define PLANE_WM_EN REG_BIT(31)
324
324
#define PLANE_WM_IGNORE_LINES REG_BIT(30)
325
+
#define PLANE_WM_AUTO_MIN_ALLOC_EN REG_BIT(29)
325
326
#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
326
327
#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
327
328
···
374
373
#define PLANE_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
375
374
_PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \
376
375
_PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
376
+
377
377
/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
378
378
#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
379
379
#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
380
380
#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
381
381
#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
382
+
383
+
#define _PLANE_MIN_BUF_CFG_1_A 0x70274
384
+
#define _PLANE_MIN_BUF_CFG_2_A 0x70374
385
+
#define _PLANE_MIN_BUF_CFG_1_B 0x71274
386
+
#define _PLANE_MIN_BUF_CFG_2_B 0x71374
387
+
#define PLANE_MIN_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
388
+
_PLANE_MIN_BUF_CFG_1_A, _PLANE_MIN_BUF_CFG_1_B, \
389
+
_PLANE_MIN_BUF_CFG_2_A, _PLANE_MIN_BUF_CFG_2_B)
390
+
#define PLANE_AUTO_MIN_DBUF_EN REG_BIT(31)
391
+
#define PLANE_MIN_DBUF_BLOCKS_MASK REG_GENMASK(27, 16)
392
+
#define PLANE_MIN_DBUF_BLOCKS(val) REG_FIELD_PREP(PLANE_MIN_DBUF_BLOCKS_MASK, (val))
393
+
#define PLANE_INTERIM_DBUF_BLOCKS_MASK REG_GENMASK(11, 0)
394
+
#define PLANE_INTERIM_DBUF_BLOCKS(val) REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val))
382
395
383
396
/* tgl+ */
384
397
#define _SEL_FETCH_PLANE_CTL_1_A 0x70890
+113
-38
drivers/gpu/drm/i915/display/skl_watermark.c
+113
-38
drivers/gpu/drm/i915/display/skl_watermark.c
···
801
801
const enum pipe pipe,
802
802
const enum plane_id plane_id,
803
803
struct skl_ddb_entry *ddb,
804
-
struct skl_ddb_entry *ddb_y)
804
+
struct skl_ddb_entry *ddb_y,
805
+
u16 *min_ddb, u16 *interim_ddb)
805
806
{
807
+
struct intel_display *display = &i915->display;
806
808
u32 val;
807
809
808
810
/* Cursor doesn't support NV12/planar, so no extra calculation needed */
809
811
if (plane_id == PLANE_CURSOR) {
810
-
val = intel_de_read(i915, CUR_BUF_CFG(pipe));
812
+
val = intel_de_read(display, CUR_BUF_CFG(pipe));
811
813
skl_ddb_entry_init_from_hw(ddb, val);
812
814
return;
813
815
}
814
816
815
-
val = intel_de_read(i915, PLANE_BUF_CFG(pipe, plane_id));
817
+
val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id));
816
818
skl_ddb_entry_init_from_hw(ddb, val);
817
819
818
-
if (DISPLAY_VER(i915) >= 11)
820
+
if (DISPLAY_VER(display) >= 30) {
821
+
val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id));
822
+
823
+
*min_ddb = REG_FIELD_GET(PLANE_MIN_DBUF_BLOCKS_MASK, val);
824
+
*interim_ddb = REG_FIELD_GET(PLANE_INTERIM_DBUF_BLOCKS_MASK, val);
825
+
}
826
+
827
+
if (DISPLAY_VER(display) >= 11)
819
828
return;
820
829
821
-
val = intel_de_read(i915, PLANE_NV12_BUF_CFG(pipe, plane_id));
830
+
val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id));
822
831
skl_ddb_entry_init_from_hw(ddb_y, val);
823
832
}
824
833
825
834
static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
826
835
struct skl_ddb_entry *ddb,
827
-
struct skl_ddb_entry *ddb_y)
836
+
struct skl_ddb_entry *ddb_y,
837
+
u16 *min_ddb, u16 *interim_ddb)
828
838
{
829
839
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
830
840
enum intel_display_power_domain power_domain;
···
851
841
skl_ddb_get_hw_plane_state(i915, pipe,
852
842
plane_id,
853
843
&ddb[plane_id],
854
-
&ddb_y[plane_id]);
844
+
&ddb_y[plane_id],
845
+
&min_ddb[plane_id],
846
+
&interim_ddb[plane_id]);
855
847
856
848
intel_display_power_put(i915, power_domain, wakeref);
857
849
}
···
1388
1376
use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
1389
1377
struct intel_plane *plane)
1390
1378
{
1391
-
struct drm_i915_private *i915 = to_i915(plane->base.dev);
1379
+
struct intel_display *display = to_intel_display(plane);
1392
1380
1393
-
return DISPLAY_VER(i915) >= 13 &&
1381
+
/* Xe3+ are auto minimum DDB capble. So don't force minimal wm0 */
1382
+
return IS_DISPLAY_VER(display, 13, 20) &&
1394
1383
crtc_state->uapi.async_flip &&
1395
1384
plane->async_flip;
1385
+
}
1386
+
1387
+
unsigned int
1388
+
skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
1389
+
struct intel_plane *plane, int width, int height,
1390
+
int cpp)
1391
+
{
1392
+
/*
1393
+
* We calculate extra ddb based on ratio plane rate/total data rate
1394
+
* in case, in some cases we should not allocate extra ddb for the plane,
1395
+
* so do not count its data rate, if this is the case.
1396
+
*/
1397
+
if (use_minimal_wm0_only(crtc_state, plane))
1398
+
return 0;
1399
+
1400
+
return width * height * cpp;
1396
1401
}
1397
1402
1398
1403
static u64
···
1548
1519
const struct intel_dbuf_state *dbuf_state =
1549
1520
intel_atomic_get_new_dbuf_state(state);
1550
1521
const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
1522
+
struct intel_display *display = to_intel_display(state);
1551
1523
int num_active = hweight8(dbuf_state->active_pipes);
1552
1524
struct skl_plane_ddb_iter iter;
1553
1525
enum plane_id plane_id;
···
1559
1529
/* Clear the partitioning for disabled planes. */
1560
1530
memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb));
1561
1531
memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
1532
+
memset(crtc_state->wm.skl.plane_min_ddb, 0,
1533
+
sizeof(crtc_state->wm.skl.plane_min_ddb));
1534
+
memset(crtc_state->wm.skl.plane_interim_ddb, 0,
1535
+
sizeof(crtc_state->wm.skl.plane_interim_ddb));
1562
1536
1563
1537
if (!crtc_state->hw.active)
1564
1538
return 0;
···
1635
1601
&crtc_state->wm.skl.plane_ddb[plane_id];
1636
1602
struct skl_ddb_entry *ddb_y =
1637
1603
&crtc_state->wm.skl.plane_ddb_y[plane_id];
1604
+
u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id];
1605
+
u16 *interim_ddb =
1606
+
&crtc_state->wm.skl.plane_interim_ddb[plane_id];
1638
1607
const struct skl_plane_wm *wm =
1639
1608
&crtc_state->wm.skl.optimal.planes[plane_id];
1640
1609
···
1653
1616
} else {
1654
1617
skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level],
1655
1618
crtc_state->rel_data_rate[plane_id]);
1619
+
}
1620
+
1621
+
if (DISPLAY_VER(display) >= 30) {
1622
+
*min_ddb = wm->wm[0].min_ddb_alloc;
1623
+
*interim_ddb = wm->sagv.wm0.min_ddb_alloc;
1656
1624
}
1657
1625
}
1658
1626
drm_WARN_ON(&i915->drm, iter.size != 0 || iter.data_rate != 0);
···
1702
1660
&crtc_state->wm.skl.plane_ddb[plane_id];
1703
1661
const struct skl_ddb_entry *ddb_y =
1704
1662
&crtc_state->wm.skl.plane_ddb_y[plane_id];
1663
+
u16 *interim_ddb =
1664
+
&crtc_state->wm.skl.plane_interim_ddb[plane_id];
1705
1665
struct skl_plane_wm *wm =
1706
1666
&crtc_state->wm.skl.optimal.planes[plane_id];
1707
1667
···
1717
1673
}
1718
1674
1719
1675
skl_check_wm_level(&wm->sagv.wm0, ddb);
1676
+
if (DISPLAY_VER(display) >= 30)
1677
+
*interim_ddb = wm->sagv.wm0.min_ddb_alloc;
1678
+
1720
1679
skl_check_wm_level(&wm->sagv.trans_wm, ddb);
1721
1680
}
1722
1681
···
1798
1751
int color_plane, unsigned int pan_x)
1799
1752
{
1800
1753
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1754
+
struct intel_display *display = to_intel_display(crtc_state);
1801
1755
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1802
1756
u32 interm_pbpl;
1803
1757
···
1857
1809
wp->y_min_scanlines,
1858
1810
wp->dbuf_block_size);
1859
1811
1860
-
if (DISPLAY_VER(i915) >= 30)
1812
+
if (DISPLAY_VER(display) >= 30)
1861
1813
interm_pbpl += (pan_x != 0);
1862
1814
else if (DISPLAY_VER(i915) >= 10)
1863
1815
interm_pbpl++;
···
1920
1872
return 255;
1921
1873
else
1922
1874
return 31;
1875
+
}
1876
+
1877
+
static bool xe3_auto_min_alloc_capable(struct intel_plane *plane, int level)
1878
+
{
1879
+
struct intel_display *display = to_intel_display(plane);
1880
+
1881
+
return DISPLAY_VER(display) >= 30 && level == 0 && plane->id != PLANE_CURSOR;
1923
1882
}
1924
1883
1925
1884
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
···
2061
2006
/* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
2062
2007
result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;
2063
2008
result->enable = true;
2009
+
result->auto_min_alloc_wm_enable = xe3_auto_min_alloc_capable(plane, level);
2064
2010
2065
2011
if (DISPLAY_VER(i915) < 12 && i915->display.sagv.block_time_us)
2066
2012
result->can_sagv = latency >= i915->display.sagv.block_time_us;
···
2441
2385
return l1->enable == l2->enable &&
2442
2386
l1->ignore_lines == l2->ignore_lines &&
2443
2387
l1->lines == l2->lines &&
2444
-
l1->blocks == l2->blocks;
2388
+
l1->blocks == l2->blocks &&
2389
+
l1->auto_min_alloc_wm_enable == l2->auto_min_alloc_wm_enable;
2445
2390
}
2446
2391
2447
2392
static bool skl_plane_wm_equals(struct drm_i915_private *i915,
2448
2393
const struct skl_plane_wm *wm1,
2449
2394
const struct skl_plane_wm *wm2)
2450
2395
{
2396
+
struct intel_display *display = &i915->display;
2451
2397
int level;
2452
2398
2453
-
for (level = 0; level < i915->display.wm.num_levels; level++) {
2399
+
for (level = 0; level < display->wm.num_levels; level++) {
2454
2400
/*
2455
2401
* We don't check uv_wm as the hardware doesn't actually
2456
2402
* use it. It only gets used for calculating the required
···
2939
2881
}
2940
2882
2941
2883
if (fixed_refresh_rate) {
2884
+
added_wake_time = DSB_EXE_TIME +
2885
+
display->sagv.block_time_us;
2886
+
2942
2887
latency = skl_watermark_max_latency(i915, 1);
2888
+
2889
+
/* Wa_22020432604 */
2890
+
if ((DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30) && !latency) {
2891
+
latency += added_wake_time;
2892
+
added_wake_time = 0;
2893
+
}
2894
+
2943
2895
/* Wa_22020299601 */
2944
2896
if ((latency && max_linetime) &&
2945
2897
(DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30)) {
···
2957
2889
} else if (!latency) {
2958
2890
latency = LNL_PKG_C_LATENCY_MASK;
2959
2891
}
2960
-
2961
-
added_wake_time = DSB_EXE_TIME +
2962
-
display->sagv.block_time_us;
2963
2892
}
2964
2893
2965
2894
clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
···
3003
2938
return 0;
3004
2939
}
3005
2940
3006
-
static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
2941
+
static void skl_wm_level_from_reg_val(struct intel_display *display,
2942
+
u32 val, struct skl_wm_level *level)
3007
2943
{
3008
2944
level->enable = val & PLANE_WM_EN;
3009
2945
level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
3010
2946
level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val);
3011
2947
level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);
2948
+
level->auto_min_alloc_wm_enable = DISPLAY_VER(display) >= 30 ?
2949
+
val & PLANE_WM_AUTO_MIN_ALLOC_EN : 0;
3012
2950
}
3013
2951
3014
2952
static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
3015
2953
struct skl_pipe_wm *out)
3016
2954
{
3017
2955
struct intel_display *display = to_intel_display(crtc);
3018
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3019
2956
enum pipe pipe = crtc->pipe;
3020
2957
enum plane_id plane_id;
3021
2958
int level;
···
3026
2959
for_each_plane_id_on_crtc(crtc, plane_id) {
3027
2960
struct skl_plane_wm *wm = &out->planes[plane_id];
3028
2961
3029
-
for (level = 0; level < i915->display.wm.num_levels; level++) {
2962
+
for (level = 0; level < display->wm.num_levels; level++) {
3030
2963
if (plane_id != PLANE_CURSOR)
3031
-
val = intel_de_read(i915, PLANE_WM(pipe, plane_id, level));
2964
+
val = intel_de_read(display, PLANE_WM(pipe, plane_id, level));
3032
2965
else
3033
-
val = intel_de_read(i915, CUR_WM(pipe, level));
2966
+
val = intel_de_read(display, CUR_WM(pipe, level));
3034
2967
3035
-
skl_wm_level_from_reg_val(val, &wm->wm[level]);
2968
+
skl_wm_level_from_reg_val(display, val, &wm->wm[level]);
3036
2969
}
3037
2970
3038
2971
if (plane_id != PLANE_CURSOR)
3039
-
val = intel_de_read(i915, PLANE_WM_TRANS(pipe, plane_id));
2972
+
val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id));
3040
2973
else
3041
-
val = intel_de_read(i915, CUR_WM_TRANS(pipe));
2974
+
val = intel_de_read(display, CUR_WM_TRANS(pipe));
3042
2975
3043
-
skl_wm_level_from_reg_val(val, &wm->trans_wm);
2976
+
skl_wm_level_from_reg_val(display, val, &wm->trans_wm);
3044
2977
3045
2978
if (HAS_HW_SAGV_WM(display)) {
3046
2979
if (plane_id != PLANE_CURSOR)
3047
-
val = intel_de_read(i915, PLANE_WM_SAGV(pipe, plane_id));
2980
+
val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id));
3048
2981
else
3049
-
val = intel_de_read(i915, CUR_WM_SAGV(pipe));
2982
+
val = intel_de_read(display, CUR_WM_SAGV(pipe));
3050
2983
3051
-
skl_wm_level_from_reg_val(val, &wm->sagv.wm0);
2984
+
skl_wm_level_from_reg_val(display, val, &wm->sagv.wm0);
3052
2985
3053
2986
if (plane_id != PLANE_CURSOR)
3054
-
val = intel_de_read(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id));
2987
+
val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id));
3055
2988
else
3056
-
val = intel_de_read(i915, CUR_WM_SAGV_TRANS(pipe));
2989
+
val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe));
3057
2990
3058
-
skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm);
3059
-
} else if (DISPLAY_VER(i915) >= 12) {
2991
+
skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm);
2992
+
} else if (DISPLAY_VER(display) >= 12) {
3060
2993
wm->sagv.wm0 = wm->wm[0];
3061
2994
wm->sagv.trans_wm = wm->trans_wm;
3062
2995
}
···
3071
3004
struct intel_crtc *crtc;
3072
3005
3073
3006
if (HAS_MBUS_JOINING(display))
3074
-
dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
3007
+
dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
3075
3008
3076
3009
dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw);
3077
3010
3078
-
for_each_intel_crtc(&i915->drm, crtc) {
3011
+
for_each_intel_crtc(display->drm, crtc) {
3079
3012
struct intel_crtc_state *crtc_state =
3080
3013
to_intel_crtc_state(crtc->base.state);
3081
3014
enum pipe pipe = crtc->pipe;
···
3096
3029
&crtc_state->wm.skl.plane_ddb[plane_id];
3097
3030
struct skl_ddb_entry *ddb_y =
3098
3031
&crtc_state->wm.skl.plane_ddb_y[plane_id];
3032
+
u16 *min_ddb =
3033
+
&crtc_state->wm.skl.plane_min_ddb[plane_id];
3034
+
u16 *interim_ddb =
3035
+
&crtc_state->wm.skl.plane_interim_ddb[plane_id];
3099
3036
3100
3037
if (!crtc_state->hw.active)
3101
3038
continue;
3102
3039
3103
3040
skl_ddb_get_hw_plane_state(i915, crtc->pipe,
3104
-
plane_id, ddb, ddb_y);
3041
+
plane_id, ddb, ddb_y,
3042
+
min_ddb, interim_ddb);
3105
3043
3106
3044
skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb);
3107
3045
skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);
···
3128
3056
dbuf_state->slices[pipe] =
3129
3057
skl_ddb_dbuf_slice_mask(i915, &crtc_state->wm.skl.ddb);
3130
3058
3131
-
drm_dbg_kms(&i915->drm,
3059
+
drm_dbg_kms(display->drm,
3132
3060
"[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n",
3133
3061
crtc->base.base.id, crtc->base.name,
3134
3062
dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start,
···
3136
3064
str_yes_no(dbuf_state->joined_mbus));
3137
3065
}
3138
3066
3139
-
dbuf_state->enabled_slices = i915->display.dbuf.enabled_slices;
3067
+
dbuf_state->enabled_slices = display->dbuf.enabled_slices;
3140
3068
}
3141
3069
3142
3070
bool skl_watermark_ipc_enabled(struct drm_i915_private *i915)
···
3333
3261
3334
3262
int intel_dbuf_init(struct drm_i915_private *i915)
3335
3263
{
3264
+
struct intel_display *display = &i915->display;
3336
3265
struct intel_dbuf_state *dbuf_state;
3337
3266
3338
3267
dbuf_state = kzalloc(sizeof(*dbuf_state), GFP_KERNEL);
3339
3268
if (!dbuf_state)
3340
3269
return -ENOMEM;
3341
3270
3342
-
intel_atomic_global_obj_init(i915, &i915->display.dbuf.obj,
3271
+
intel_atomic_global_obj_init(display, &display->dbuf.obj,
3343
3272
&dbuf_state->base, &intel_dbuf_funcs);
3344
3273
3345
3274
return 0;
···
3772
3699
struct skl_hw_state {
3773
3700
struct skl_ddb_entry ddb[I915_MAX_PLANES];
3774
3701
struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
3702
+
u16 min_ddb[I915_MAX_PLANES];
3703
+
u16 interim_ddb[I915_MAX_PLANES];
3775
3704
struct skl_pipe_wm wm;
3776
3705
} *hw;
3777
3706
const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
···
3790
3715
3791
3716
skl_pipe_wm_get_hw_state(crtc, &hw->wm);
3792
3717
3793
-
skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);
3718
+
skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y, hw->min_ddb, hw->interim_ddb);
3794
3719
3795
3720
hw_enabled_slices = intel_enabled_dbuf_slices_mask(i915);
3796
3721
+4
drivers/gpu/drm/i915/display/skl_watermark.h
+4
drivers/gpu/drm/i915/display/skl_watermark.h
···
18
18
struct intel_crtc;
19
19
struct intel_crtc_state;
20
20
struct intel_plane;
21
+
struct intel_plane_state;
21
22
struct skl_pipe_wm;
22
23
struct skl_wm_level;
23
24
···
54
53
int level);
55
54
const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
56
55
enum plane_id plane_id);
56
+
unsigned int skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
57
+
struct intel_plane *plane, int width,
58
+
int height, int cpp);
57
59
58
60
struct intel_dbuf_state {
59
61
struct intel_global_state base;
+1
-1
drivers/gpu/drm/i915/gt/intel_rc6.c
+1
-1
drivers/gpu/drm/i915/gt/intel_rc6.c
···
133
133
GEN9_MEDIA_PG_ENABLE |
134
134
GEN11_MEDIA_SAMPLER_PG_ENABLE;
135
135
136
-
if (GRAPHICS_VER(gt->i915) >= 12) {
136
+
if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) {
137
137
for (i = 0; i < I915_MAX_VCS; i++)
138
138
if (HAS_ENGINE(gt, _VCS(i)))
139
139
pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
+10
-7
drivers/gpu/drm/i915/gvt/cmd_parser.c
+10
-7
drivers/gpu/drm/i915/gvt/cmd_parser.c
···
1286
1286
struct mi_display_flip_command_info *info)
1287
1287
{
1288
1288
struct drm_i915_private *dev_priv = s->engine->i915;
1289
+
struct intel_display *display = &dev_priv->display;
1289
1290
struct plane_code_mapping gen8_plane_code[] = {
1290
1291
[0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1291
1292
[1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
···
1315
1314
info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1316
1315
1317
1316
if (info->plane == PLANE_A) {
1318
-
info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
1319
-
info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
1320
-
info->surf_reg = DSPSURF(dev_priv, info->pipe);
1317
+
info->ctrl_reg = DSPCNTR(display, info->pipe);
1318
+
info->stride_reg = DSPSTRIDE(display, info->pipe);
1319
+
info->surf_reg = DSPSURF(display, info->pipe);
1321
1320
} else if (info->plane == PLANE_B) {
1322
1321
info->ctrl_reg = SPRCTL(info->pipe);
1323
1322
info->stride_reg = SPRSTRIDE(info->pipe);
···
1333
1332
struct mi_display_flip_command_info *info)
1334
1333
{
1335
1334
struct drm_i915_private *dev_priv = s->engine->i915;
1335
+
struct intel_display *display = &dev_priv->display;
1336
1336
struct intel_vgpu *vgpu = s->vgpu;
1337
1337
u32 dword0 = cmd_val(s, 0);
1338
1338
u32 dword1 = cmd_val(s, 1);
···
1382
1380
info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1383
1381
info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1384
1382
1385
-
info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
1386
-
info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
1387
-
info->surf_reg = DSPSURF(dev_priv, info->pipe);
1383
+
info->ctrl_reg = DSPCNTR(display, info->pipe);
1384
+
info->stride_reg = DSPSTRIDE(display, info->pipe);
1385
+
info->surf_reg = DSPSURF(display, info->pipe);
1388
1386
1389
1387
return 0;
1390
1388
}
···
1421
1419
struct mi_display_flip_command_info *info)
1422
1420
{
1423
1421
struct drm_i915_private *dev_priv = s->engine->i915;
1422
+
struct intel_display *display = &dev_priv->display;
1424
1423
struct intel_vgpu *vgpu = s->vgpu;
1425
1424
1426
1425
set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
···
1439
1436
}
1440
1437
1441
1438
if (info->plane == PLANE_PRIMARY)
1442
-
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, info->pipe))++;
1439
+
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++;
1443
1440
1444
1441
if (info->async_flip)
1445
1442
intel_vgpu_trigger_virtual_event(vgpu, info->event);
+43
-37
drivers/gpu/drm/i915/gvt/display.c
+43
-37
drivers/gpu/drm/i915/gvt/display.c
···
69
69
static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
70
70
{
71
71
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
72
+
struct intel_display *display = &dev_priv->display;
72
73
73
-
if (!(vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_EDP)) & TRANSCONF_ENABLE))
74
+
if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE))
74
75
return 0;
75
76
76
77
if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
···
82
81
int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
83
82
{
84
83
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
84
+
struct intel_display *display = &dev_priv->display;
85
85
86
86
if (drm_WARN_ON(&dev_priv->drm,
87
87
pipe < PIPE_A || pipe >= I915_MAX_PIPES))
88
88
return -EINVAL;
89
89
90
-
if (vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) & TRANSCONF_ENABLE)
90
+
if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE)
91
91
return 1;
92
92
93
93
if (edp_pipe_is_enabled(vgpu) &&
···
183
181
static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
184
182
{
185
183
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
184
+
struct intel_display *display = &dev_priv->display;
186
185
int pipe;
187
186
188
187
if (IS_BROXTON(dev_priv)) {
···
196
193
GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
197
194
GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
198
195
199
-
for_each_pipe(dev_priv, pipe) {
200
-
vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) &=
196
+
for_each_pipe(display, pipe) {
197
+
vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &=
201
198
~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE);
202
-
vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE;
199
+
vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;
203
200
vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
204
-
vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK;
205
-
vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE;
201
+
vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;
202
+
vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;
206
203
}
207
204
208
205
for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
209
-
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, trans)) &=
206
+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &=
210
207
~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
211
208
TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
212
209
}
213
-
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=
210
+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
214
211
~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
215
212
TRANS_DDI_PORT_MASK);
216
213
···
258
255
* TRANSCODER_A can be enabled. PORT_x depends on the input of
259
256
* setup_virtual_dp_monitor.
260
257
*/
261
-
vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE;
262
-
vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
258
+
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
259
+
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
263
260
264
261
/*
265
262
* Golden M/N are calculated based on:
···
267
264
* DP link clk 1620 MHz and non-constant_n.
268
265
* TODO: calculate DP link symbol clk and stream clk m/n.
269
266
*/
270
-
vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
271
-
vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
272
-
vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
273
-
vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
274
-
vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000;
267
+
vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);
268
+
vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;
269
+
vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;
270
+
vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;
271
+
vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;
275
272
276
273
/* Enable per-DDI/PORT vreg */
277
274
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
···
294
291
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
295
292
~DDI_BUF_IS_IDLE;
296
293
vgpu_vreg_t(vgpu,
297
-
TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)) |=
294
+
TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)) |=
298
295
(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
299
296
TRANS_DDI_FUNC_ENABLE);
300
297
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
···
324
321
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
325
322
~DDI_BUF_IS_IDLE;
326
323
vgpu_vreg_t(vgpu,
327
-
TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
324
+
TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
328
325
(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
329
326
(PORT_B << TRANS_DDI_PORT_SHIFT) |
330
327
TRANS_DDI_FUNC_ENABLE);
···
355
352
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
356
353
~DDI_BUF_IS_IDLE;
357
354
vgpu_vreg_t(vgpu,
358
-
TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
355
+
TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
359
356
(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
360
357
(PORT_B << TRANS_DDI_PORT_SHIFT) |
361
358
TRANS_DDI_FUNC_ENABLE);
···
404
401
* DP link clk 1620 MHz and non-constant_n.
405
402
* TODO: calculate DP link symbol clk and stream clk m/n.
406
403
*/
407
-
vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
408
-
vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
409
-
vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
410
-
vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
411
-
vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000;
404
+
vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);
405
+
vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;
406
+
vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;
407
+
vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;
408
+
vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;
412
409
}
413
410
414
411
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
···
419
416
vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
420
417
DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
421
418
vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
422
-
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=
419
+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
423
420
~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
424
421
TRANS_DDI_PORT_MASK);
425
-
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
422
+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
426
423
(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
427
424
(PORT_B << TRANS_DDI_PORT_SHIFT) |
428
425
TRANS_DDI_FUNC_ENABLE);
···
445
442
vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
446
443
DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
447
444
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
448
-
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=
445
+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
449
446
~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
450
447
TRANS_DDI_PORT_MASK);
451
-
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
448
+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
452
449
(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
453
450
(PORT_C << TRANS_DDI_PORT_SHIFT) |
454
451
TRANS_DDI_FUNC_ENABLE);
···
471
468
vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
472
469
DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
473
470
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
474
-
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=
471
+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
475
472
~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
476
473
TRANS_DDI_PORT_MASK);
477
-
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
474
+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
478
475
(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
479
476
(PORT_D << TRANS_DDI_PORT_SHIFT) |
480
477
TRANS_DDI_FUNC_ENABLE);
···
512
509
vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
513
510
514
511
/* Disable Primary/Sprite/Cursor plane */
515
-
for_each_pipe(dev_priv, pipe) {
516
-
vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE;
512
+
for_each_pipe(display, pipe) {
513
+
vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;
517
514
vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
518
-
vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK;
519
-
vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE;
515
+
vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;
516
+
vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;
520
517
}
521
518
522
-
vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE;
519
+
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
523
520
}
524
521
525
522
static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
···
635
632
static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
636
633
{
637
634
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
635
+
struct intel_display *display = &dev_priv->display;
638
636
struct intel_vgpu_irq *irq = &vgpu->irq;
639
637
int vblank_event[] = {
640
638
[PIPE_A] = PIPE_A_VBLANK,
···
657
653
}
658
654
659
655
if (pipe_is_enabled(vgpu, pipe)) {
660
-
vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(dev_priv, pipe))++;
656
+
vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++;
661
657
intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
662
658
}
663
659
}
664
660
665
661
void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu)
666
662
{
663
+
struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
664
+
struct intel_display *display = &i915->display;
667
665
int pipe;
668
666
669
667
mutex_lock(&vgpu->vgpu_lock);
670
-
for_each_pipe(vgpu->gvt->gt->i915, pipe)
668
+
for_each_pipe(display, pipe)
671
669
emulate_vblank_on_pipe(vgpu, pipe);
672
670
mutex_unlock(&vgpu->vgpu_lock);
673
671
}
+12
-9
drivers/gpu/drm/i915/gvt/fb_decoder.c
+12
-9
drivers/gpu/drm/i915/gvt/fb_decoder.c
···
154
154
u32 tiled, int stride_mask, int bpp)
155
155
{
156
156
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
157
+
struct intel_display *display = &dev_priv->display;
157
158
158
-
u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(dev_priv, pipe)) & stride_mask;
159
+
u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask;
159
160
u32 stride = stride_reg;
160
161
161
162
if (GRAPHICS_VER(dev_priv) >= 9) {
···
211
210
struct intel_vgpu_primary_plane_format *plane)
212
211
{
213
212
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
213
+
struct intel_display *display = &dev_priv->display;
214
214
u32 val, fmt;
215
215
int pipe;
216
216
···
219
217
if (pipe >= I915_MAX_PIPES)
220
218
return -ENODEV;
221
219
222
-
val = vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe));
220
+
val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe));
223
221
plane->enabled = !!(val & DISP_ENABLE);
224
222
if (!plane->enabled)
225
223
return -ENODEV;
···
253
251
254
252
plane->hw_format = fmt;
255
253
256
-
plane->base = vgpu_vreg_t(vgpu, DSPSURF(dev_priv, pipe)) & I915_GTT_PAGE_MASK;
254
+
plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;
257
255
if (!vgpu_gmadr_is_valid(vgpu, plane->base))
258
256
return -EINVAL;
259
257
···
269
267
(_PRI_PLANE_STRIDE_MASK >> 6) :
270
268
_PRI_PLANE_STRIDE_MASK, plane->bpp);
271
269
272
-
plane->width = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) & _PIPE_H_SRCSZ_MASK) >>
270
+
plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>
273
271
_PIPE_H_SRCSZ_SHIFT;
274
272
plane->width += 1;
275
-
plane->height = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) &
273
+
plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &
276
274
_PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
277
275
plane->height += 1; /* raw height is one minus the real value */
278
276
279
-
val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe));
277
+
val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe));
280
278
plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
281
279
_PRI_PLANE_X_OFF_SHIFT;
282
280
plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
···
342
340
struct intel_vgpu_cursor_plane_format *plane)
343
341
{
344
342
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
343
+
struct intel_display *display = &dev_priv->display;
345
344
u32 val, mode, index;
346
345
u32 alpha_plane, alpha_force;
347
346
int pipe;
···
351
348
if (pipe >= I915_MAX_PIPES)
352
349
return -ENODEV;
353
350
354
-
val = vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe));
351
+
val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe));
355
352
mode = val & MCURSOR_MODE_MASK;
356
353
plane->enabled = (mode != MCURSOR_MODE_DISABLE);
357
354
if (!plane->enabled)
···
377
374
gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
378
375
alpha_plane, alpha_force);
379
376
380
-
plane->base = vgpu_vreg_t(vgpu, CURBASE(dev_priv, pipe)) & I915_GTT_PAGE_MASK;
377
+
plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;
381
378
if (!vgpu_gmadr_is_valid(vgpu, plane->base))
382
379
return -EINVAL;
383
380
···
388
385
return -EINVAL;
389
386
}
390
387
391
-
val = vgpu_vreg_t(vgpu, CURPOS(dev_priv, pipe));
388
+
val = vgpu_vreg_t(vgpu, CURPOS(display, pipe));
392
389
plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
393
390
plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
394
391
plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
+24
-20
drivers/gpu/drm/i915/gvt/handlers.c
+24
-20
drivers/gpu/drm/i915/gvt/handlers.c
···
656
656
static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
657
657
{
658
658
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
659
+
struct intel_display *display = &dev_priv->display;
659
660
enum port port;
660
661
u32 dp_br, link_m, link_n, htotal, vtotal;
661
662
662
663
/* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */
663
-
port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &
664
+
port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &
664
665
TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
665
666
if (port != PORT_B && port != PORT_D) {
666
667
gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port));
···
677
676
dp_br = skl_vgpu_get_dp_bitrate(vgpu, port);
678
677
679
678
/* Get DP link symbol clock M/N */
680
-
link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A));
681
-
link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A));
679
+
link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A));
680
+
link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A));
682
681
683
682
/* Get H/V total from transcoder timing */
684
-
htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
685
-
vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
683
+
htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
684
+
vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
686
685
687
686
if (dp_br && link_n && htotal && vtotal) {
688
687
u64 pixel_clk = 0;
···
1013
1012
return 0;
1014
1013
}
1015
1014
1016
-
#define DSPSURF_TO_PIPE(dev_priv, offset) \
1017
-
calc_index(offset, DSPSURF(dev_priv, PIPE_A), DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C))
1015
+
#define DSPSURF_TO_PIPE(display, offset) \
1016
+
calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C))
1018
1017
1019
1018
static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1020
1019
void *p_data, unsigned int bytes)
1021
1020
{
1022
1021
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1023
-
u32 pipe = DSPSURF_TO_PIPE(dev_priv, offset);
1022
+
struct intel_display *display = &dev_priv->display;
1023
+
u32 pipe = DSPSURF_TO_PIPE(display, offset);
1024
1024
int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
1025
1025
1026
1026
write_vreg(vgpu, offset, p_data, bytes);
1027
-
vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);
1027
+
vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);
1028
1028
1029
-
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++;
1029
+
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;
1030
1030
1031
-
if (vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) & PLANE_CTL_ASYNC_FLIP)
1031
+
if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP)
1032
1032
intel_vgpu_trigger_virtual_event(vgpu, event);
1033
1033
else
1034
1034
set_bit(event, vgpu->irq.flip_done_event[pipe]);
···
1062
1060
unsigned int bytes)
1063
1061
{
1064
1062
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1063
+
struct intel_display *display = &dev_priv->display;
1065
1064
enum pipe pipe = REG_50080_TO_PIPE(offset);
1066
1065
enum plane_id plane = REG_50080_TO_PLANE(offset);
1067
1066
int event = SKL_FLIP_EVENT(pipe, plane);
1068
1067
1069
1068
write_vreg(vgpu, offset, p_data, bytes);
1070
1069
if (plane == PLANE_PRIMARY) {
1071
-
vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);
1072
-
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++;
1070
+
vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);
1071
+
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;
1073
1072
} else {
1074
1073
vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1075
1074
}
···
2196
2193
static int init_generic_mmio_info(struct intel_gvt *gvt)
2197
2194
{
2198
2195
struct drm_i915_private *dev_priv = gvt->gt->i915;
2196
+
struct intel_display *display = &dev_priv->display;
2199
2197
int ret;
2200
2198
2201
2199
MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
···
2285
2281
MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2286
2282
2287
2283
/* display */
2288
-
MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_A), D_ALL, NULL,
2284
+
MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL,
2289
2285
pipeconf_mmio_write);
2290
-
MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_B), D_ALL, NULL,
2286
+
MMIO_DH(TRANSCONF(display, TRANSCODER_B), D_ALL, NULL,
2291
2287
pipeconf_mmio_write);
2292
-
MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_C), D_ALL, NULL,
2288
+
MMIO_DH(TRANSCONF(display, TRANSCODER_C), D_ALL, NULL,
2293
2289
pipeconf_mmio_write);
2294
-
MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_EDP), D_ALL, NULL,
2290
+
MMIO_DH(TRANSCONF(display, TRANSCODER_EDP), D_ALL, NULL,
2295
2291
pipeconf_mmio_write);
2296
-
MMIO_DH(DSPSURF(dev_priv, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
2292
+
MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
2297
2293
MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
2298
2294
reg50080_mmio_write);
2299
-
MMIO_DH(DSPSURF(dev_priv, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
2295
+
MMIO_DH(DSPSURF(display, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
2300
2296
MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
2301
2297
reg50080_mmio_write);
2302
-
MMIO_DH(DSPSURF(dev_priv, PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
2298
+
MMIO_DH(DSPSURF(display, PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
2303
2299
MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
2304
2300
reg50080_mmio_write);
2305
2301
MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
+16
-1
drivers/gpu/drm/i915/i915_driver.c
+16
-1
drivers/gpu/drm/i915/i915_driver.c
···
95
95
#include "i915_memcpy.h"
96
96
#include "i915_perf.h"
97
97
#include "i915_query.h"
98
+
#include "i915_reg.h"
98
99
#include "i915_switcheroo.h"
99
100
#include "i915_sysfs.h"
100
101
#include "i915_utils.h"
101
102
#include "i915_vgpu.h"
102
103
#include "intel_clock_gating.h"
104
+
#include "intel_cpu_info.h"
103
105
#include "intel_gvt.h"
104
106
#include "intel_memory_region.h"
105
107
#include "intel_pci_config.h"
···
426
424
return ret;
427
425
}
428
426
427
+
/* Wa_14022698537:dg2 */
428
+
static void i915_enable_g8(struct drm_i915_private *i915)
429
+
{
430
+
if (IS_DG2(i915)) {
431
+
if (IS_DG2_D(i915) && !intel_match_g8_cpu())
432
+
return;
433
+
434
+
snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP,
435
+
POWER_SETUP_SUBCOMMAND_G8_ENABLE, 0, 0);
436
+
}
437
+
}
438
+
429
439
static int i915_pcode_init(struct drm_i915_private *i915)
430
440
{
431
441
struct intel_gt *gt;
···
451
437
}
452
438
}
453
439
440
+
i915_enable_g8(i915);
454
441
return 0;
455
442
}
456
443
···
981
966
drm_atomic_helper_shutdown(&i915->drm);
982
967
}
983
968
984
-
intel_dp_mst_suspend(i915);
969
+
intel_dp_mst_suspend(display);
985
970
986
971
intel_irq_suspend(i915);
987
972
intel_hpd_cancel_work(i915);
+2
drivers/gpu/drm/i915/i915_drv.h
+2
drivers/gpu/drm/i915/i915_drv.h
···
549
549
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
550
550
#define IS_DG2_G12(i915) \
551
551
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
552
+
#define IS_DG2_D(i915) \
553
+
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_D)
552
554
#define IS_RAPTORLAKE_S(i915) \
553
555
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
554
556
#define IS_ALDERLAKE_P_N(i915) \
+1
-255
drivers/gpu/drm/i915/i915_reg.h
+1
-255
drivers/gpu/drm/i915/i915_reg.h
···
144
144
#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
145
145
#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
146
146
147
-
#define _VGA_MSR_WRITE _MMIO(0x3c2)
148
-
149
147
#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
150
148
#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
151
149
#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
···
1067
1069
#define CLKGATE_DIS_PSL_EXT(pipe) \
1068
1070
_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
1069
1071
1070
-
/* DDI Buffer Control */
1071
-
#define _DDI_CLK_VALFREQ_A 0x64030
1072
-
#define _DDI_CLK_VALFREQ_B 0x64130
1073
-
#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
1074
-
1075
1072
/*
1076
1073
* Display engine regs
1077
1074
*/
···
1732
1739
#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
1733
1740
#define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
1734
1741
1735
-
#define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
1736
-
#define DSPARB_CSTART_MASK (0x7f << 7)
1737
-
#define DSPARB_CSTART_SHIFT 7
1738
-
#define DSPARB_BSTART_MASK (0x7f)
1739
-
#define DSPARB_BSTART_SHIFT 0
1740
-
#define DSPARB_BEND_SHIFT 9 /* on 855 */
1741
-
#define DSPARB_AEND_SHIFT 0
1742
-
#define DSPARB_SPRITEA_SHIFT_VLV 0
1743
-
#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
1744
-
#define DSPARB_SPRITEB_SHIFT_VLV 8
1745
-
#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
1746
-
#define DSPARB_SPRITEC_SHIFT_VLV 16
1747
-
#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
1748
-
#define DSPARB_SPRITED_SHIFT_VLV 24
1749
-
#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
1750
-
#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
1751
-
#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
1752
-
#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
1753
-
#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
1754
-
#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
1755
-
#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
1756
-
#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
1757
-
#define DSPARB_SPRITED_HI_SHIFT_VLV 12
1758
-
#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
1759
-
#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
1760
-
#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
1761
-
#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
1762
-
#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
1763
-
#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
1764
-
#define DSPARB_SPRITEE_SHIFT_VLV 0
1765
-
#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
1766
-
#define DSPARB_SPRITEF_SHIFT_VLV 8
1767
-
#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
1768
-
1769
-
/* pnv/gen4/g4x/vlv/chv */
1770
-
#define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
1771
-
#define DSPFW_SR_SHIFT 23
1772
-
#define DSPFW_SR_MASK (0x1ff << 23)
1773
-
#define DSPFW_CURSORB_SHIFT 16
1774
-
#define DSPFW_CURSORB_MASK (0x3f << 16)
1775
-
#define DSPFW_PLANEB_SHIFT 8
1776
-
#define DSPFW_PLANEB_MASK (0x7f << 8)
1777
-
#define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
1778
-
#define DSPFW_PLANEA_SHIFT 0
1779
-
#define DSPFW_PLANEA_MASK (0x7f << 0)
1780
-
#define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
1781
-
#define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
1782
-
#define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
1783
-
#define DSPFW_FBC_SR_SHIFT 28
1784
-
#define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
1785
-
#define DSPFW_FBC_HPLL_SR_SHIFT 24
1786
-
#define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
1787
-
#define DSPFW_SPRITEB_SHIFT (16)
1788
-
#define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
1789
-
#define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
1790
-
#define DSPFW_CURSORA_SHIFT 8
1791
-
#define DSPFW_CURSORA_MASK (0x3f << 8)
1792
-
#define DSPFW_PLANEC_OLD_SHIFT 0
1793
-
#define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
1794
-
#define DSPFW_SPRITEA_SHIFT 0
1795
-
#define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
1796
-
#define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
1797
-
#define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
1798
-
#define DSPFW_HPLL_SR_EN (1 << 31)
1799
-
#define PINEVIEW_SELF_REFRESH_EN (1 << 30)
1800
-
#define DSPFW_CURSOR_SR_SHIFT 24
1801
-
#define DSPFW_CURSOR_SR_MASK (0x3f << 24)
1802
-
#define DSPFW_HPLL_CURSOR_SHIFT 16
1803
-
#define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
1804
-
#define DSPFW_HPLL_SR_SHIFT 0
1805
-
#define DSPFW_HPLL_SR_MASK (0x1ff << 0)
1806
-
1807
-
/* vlv/chv */
1808
-
#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
1809
-
#define DSPFW_SPRITEB_WM1_SHIFT 16
1810
-
#define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
1811
-
#define DSPFW_CURSORA_WM1_SHIFT 8
1812
-
#define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
1813
-
#define DSPFW_SPRITEA_WM1_SHIFT 0
1814
-
#define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
1815
-
#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
1816
-
#define DSPFW_PLANEB_WM1_SHIFT 24
1817
-
#define DSPFW_PLANEB_WM1_MASK (0xff << 24)
1818
-
#define DSPFW_PLANEA_WM1_SHIFT 16
1819
-
#define DSPFW_PLANEA_WM1_MASK (0xff << 16)
1820
-
#define DSPFW_CURSORB_WM1_SHIFT 8
1821
-
#define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
1822
-
#define DSPFW_CURSOR_SR_WM1_SHIFT 0
1823
-
#define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
1824
-
#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
1825
-
#define DSPFW_SR_WM1_SHIFT 0
1826
-
#define DSPFW_SR_WM1_MASK (0x1ff << 0)
1827
-
#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
1828
-
#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
1829
-
#define DSPFW_SPRITED_WM1_SHIFT 24
1830
-
#define DSPFW_SPRITED_WM1_MASK (0xff << 24)
1831
-
#define DSPFW_SPRITED_SHIFT 16
1832
-
#define DSPFW_SPRITED_MASK_VLV (0xff << 16)
1833
-
#define DSPFW_SPRITEC_WM1_SHIFT 8
1834
-
#define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
1835
-
#define DSPFW_SPRITEC_SHIFT 0
1836
-
#define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
1837
-
#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
1838
-
#define DSPFW_SPRITEF_WM1_SHIFT 24
1839
-
#define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
1840
-
#define DSPFW_SPRITEF_SHIFT 16
1841
-
#define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
1842
-
#define DSPFW_SPRITEE_WM1_SHIFT 8
1843
-
#define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
1844
-
#define DSPFW_SPRITEE_SHIFT 0
1845
-
#define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
1846
-
#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
1847
-
#define DSPFW_PLANEC_WM1_SHIFT 24
1848
-
#define DSPFW_PLANEC_WM1_MASK (0xff << 24)
1849
-
#define DSPFW_PLANEC_SHIFT 16
1850
-
#define DSPFW_PLANEC_MASK_VLV (0xff << 16)
1851
-
#define DSPFW_CURSORC_WM1_SHIFT 8
1852
-
#define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
1853
-
#define DSPFW_CURSORC_SHIFT 0
1854
-
#define DSPFW_CURSORC_MASK (0x3f << 0)
1855
-
1856
-
/* vlv/chv high order bits */
1857
-
#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
1858
-
#define DSPFW_SR_HI_SHIFT 24
1859
-
#define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
1860
-
#define DSPFW_SPRITEF_HI_SHIFT 23
1861
-
#define DSPFW_SPRITEF_HI_MASK (1 << 23)
1862
-
#define DSPFW_SPRITEE_HI_SHIFT 22
1863
-
#define DSPFW_SPRITEE_HI_MASK (1 << 22)
1864
-
#define DSPFW_PLANEC_HI_SHIFT 21
1865
-
#define DSPFW_PLANEC_HI_MASK (1 << 21)
1866
-
#define DSPFW_SPRITED_HI_SHIFT 20
1867
-
#define DSPFW_SPRITED_HI_MASK (1 << 20)
1868
-
#define DSPFW_SPRITEC_HI_SHIFT 16
1869
-
#define DSPFW_SPRITEC_HI_MASK (1 << 16)
1870
-
#define DSPFW_PLANEB_HI_SHIFT 12
1871
-
#define DSPFW_PLANEB_HI_MASK (1 << 12)
1872
-
#define DSPFW_SPRITEB_HI_SHIFT 8
1873
-
#define DSPFW_SPRITEB_HI_MASK (1 << 8)
1874
-
#define DSPFW_SPRITEA_HI_SHIFT 4
1875
-
#define DSPFW_SPRITEA_HI_MASK (1 << 4)
1876
-
#define DSPFW_PLANEA_HI_SHIFT 0
1877
-
#define DSPFW_PLANEA_HI_MASK (1 << 0)
1878
-
#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
1879
-
#define DSPFW_SR_WM1_HI_SHIFT 24
1880
-
#define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
1881
-
#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
1882
-
#define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
1883
-
#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
1884
-
#define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
1885
-
#define DSPFW_PLANEC_WM1_HI_SHIFT 21
1886
-
#define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
1887
-
#define DSPFW_SPRITED_WM1_HI_SHIFT 20
1888
-
#define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
1889
-
#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
1890
-
#define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
1891
-
#define DSPFW_PLANEB_WM1_HI_SHIFT 12
1892
-
#define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
1893
-
#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
1894
-
#define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
1895
-
#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
1896
-
#define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
1897
-
#define DSPFW_PLANEA_WM1_HI_SHIFT 0
1898
-
#define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
1899
-
1900
-
/* drain latency register values*/
1901
-
#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
1902
-
#define DDL_CURSOR_SHIFT 24
1903
-
#define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
1904
-
#define DDL_PLANE_SHIFT 0
1905
-
#define DDL_PRECISION_HIGH (1 << 7)
1906
-
#define DDL_PRECISION_LOW (0 << 7)
1907
-
#define DRAIN_LATENCY_MASK 0x7f
1908
-
1909
1742
#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
1910
1743
#define CBR_PND_DEADLINE_DISABLE (1 << 31)
1911
1744
#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
1912
1745
1913
1746
#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
1914
1747
#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
1915
-
1916
-
/* FIFO watermark sizes etc */
1917
-
#define G4X_FIFO_LINE_SIZE 64
1918
-
#define I915_FIFO_LINE_SIZE 64
1919
-
#define I830_FIFO_LINE_SIZE 32
1920
-
1921
-
#define VALLEYVIEW_FIFO_SIZE 255
1922
-
#define G4X_FIFO_SIZE 127
1923
-
#define I965_FIFO_SIZE 512
1924
-
#define I945_FIFO_SIZE 127
1925
-
#define I915_FIFO_SIZE 95
1926
-
#define I855GM_FIFO_SIZE 127 /* In cachelines */
1927
-
#define I830_FIFO_SIZE 95
1928
-
1929
-
#define VALLEYVIEW_MAX_WM 0xff
1930
-
#define G4X_MAX_WM 0x3f
1931
-
#define I915_MAX_WM 0x3f
1932
-
1933
-
#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
1934
-
#define PINEVIEW_FIFO_LINE_SIZE 64
1935
-
#define PINEVIEW_MAX_WM 0x1ff
1936
-
#define PINEVIEW_DFT_WM 0x3f
1937
-
#define PINEVIEW_DFT_HPLLOFF_WM 0
1938
-
#define PINEVIEW_GUARD_WM 10
1939
-
#define PINEVIEW_CURSOR_FIFO 64
1940
-
#define PINEVIEW_CURSOR_MAX_WM 0x3f
1941
-
#define PINEVIEW_CURSOR_DFT_WM 0
1942
-
#define PINEVIEW_CURSOR_GUARD_WM 5
1943
-
1944
-
#define VALLEYVIEW_CURSOR_MAX_WM 64
1945
-
#define I965_CURSOR_FIFO 64
1946
-
#define I965_CURSOR_MAX_WM 32
1947
-
#define I965_CURSOR_DFT_WM 8
1948
-
1949
-
/* define the Watermark register on Ironlake */
1950
-
#define _WM0_PIPEA_ILK 0x45100
1951
-
#define _WM0_PIPEB_ILK 0x45104
1952
-
#define _WM0_PIPEC_IVB 0x45200
1953
-
#define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \
1954
-
_WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
1955
-
#define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16)
1956
-
#define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
1957
-
#define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
1958
-
#define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
1959
-
#define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
1960
-
#define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
1961
-
#define WM1_LP_ILK _MMIO(0x45108)
1962
-
#define WM2_LP_ILK _MMIO(0x4510c)
1963
-
#define WM3_LP_ILK _MMIO(0x45110)
1964
-
#define WM_LP_ENABLE REG_BIT(31)
1965
-
#define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
1966
-
#define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
1967
-
#define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
1968
-
#define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
1969
-
#define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
1970
-
#define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
1971
-
#define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
1972
-
#define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
1973
-
#define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
1974
-
#define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
1975
-
#define WM1S_LP_ILK _MMIO(0x45120)
1976
-
#define WM2S_LP_IVB _MMIO(0x45124)
1977
-
#define WM3S_LP_IVB _MMIO(0x45128)
1978
-
#define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
1979
-
#define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
1980
-
#define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
1981
1748
1982
1749
/*
1983
1750
* The two pipe frame counter registers are not synchronized, so
···
3331
3578
#define POWER_SETUP_I1_WATTS REG_BIT(31)
3332
3579
#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
3333
3580
#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
3581
+
#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
3334
3582
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
3335
3583
#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
3336
3584
/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
···
4159
4405
#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
4160
4406
#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
4161
4407
#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
4162
-
4163
-
#define WM_MISC _MMIO(0x45260)
4164
-
#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
4165
-
4166
-
#define WM_DBG _MMIO(0x45280)
4167
-
#define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
4168
-
#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
4169
-
#define WM_DBG_DISALLOW_SPRITE (1 << 2)
4170
4408
4171
4409
/* Gen4+ Timestamp and Pipe Frame time stamp registers */
4172
4410
#define GEN4_TIMESTAMP _MMIO(0x2358)
-28
drivers/gpu/drm/i915/i915_trace.h
-28
drivers/gpu/drm/i915/i915_trace.h
···
642
642
TP_ARGS(rq)
643
643
);
644
644
645
-
TRACE_EVENT_CONDITION(i915_reg_rw,
646
-
TP_PROTO(bool write, i915_reg_t reg, u64 val, int len, bool trace),
647
-
648
-
TP_ARGS(write, reg, val, len, trace),
649
-
650
-
TP_CONDITION(trace),
651
-
652
-
TP_STRUCT__entry(
653
-
__field(u64, val)
654
-
__field(u32, reg)
655
-
__field(u16, write)
656
-
__field(u16, len)
657
-
),
658
-
659
-
TP_fast_assign(
660
-
__entry->val = (u64)val;
661
-
__entry->reg = i915_mmio_reg_offset(reg);
662
-
__entry->write = write;
663
-
__entry->len = len;
664
-
),
665
-
666
-
TP_printk("%s reg=0x%x, len=%d, val=(0x%x, 0x%x)",
667
-
__entry->write ? "write" : "read",
668
-
__entry->reg, __entry->len,
669
-
(u32)(__entry->val & 0xffffffff),
670
-
(u32)(__entry->val >> 32))
671
-
);
672
-
673
645
/**
674
646
* DOC: i915_ppgtt_create and i915_ppgtt_release tracepoints
675
647
*
+44
drivers/gpu/drm/i915/intel_cpu_info.c
+44
drivers/gpu/drm/i915/intel_cpu_info.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/*
3
+
* Copyright © 2024 Intel Corporation
4
+
*
5
+
* Avoid INTEL_<PLATFORM> name collisions between asm/intel-family.h and
6
+
* intel_device_info.h by having a separate file.
7
+
*/
8
+
9
+
#include "intel_cpu_info.h"
10
+
11
+
#ifdef CONFIG_X86
12
+
#include <asm/cpu_device_id.h>
13
+
#include <asm/intel-family.h>
14
+
15
+
static const struct x86_cpu_id g8_cpu_ids[] = {
16
+
X86_MATCH_VFM(INTEL_ALDERLAKE, NULL),
17
+
X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL),
18
+
X86_MATCH_VFM(INTEL_COMETLAKE, NULL),
19
+
X86_MATCH_VFM(INTEL_KABYLAKE, NULL),
20
+
X86_MATCH_VFM(INTEL_KABYLAKE_L, NULL),
21
+
X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL),
22
+
X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL),
23
+
X86_MATCH_VFM(INTEL_RAPTORLAKE_S, NULL),
24
+
X86_MATCH_VFM(INTEL_ROCKETLAKE, NULL),
25
+
{}
26
+
};
27
+
28
+
/**
29
+
* intel_match_g8_cpu - match current CPU against g8_cpu_ids
30
+
*
31
+
* This matches current CPU against g8_cpu_ids, which are applicable
32
+
* for G8 workaround.
33
+
*
34
+
* Returns: %true if matches, %false otherwise.
35
+
*/
36
+
bool intel_match_g8_cpu(void)
37
+
{
38
+
return x86_match_cpu(g8_cpu_ids);
39
+
}
40
+
#else /* CONFIG_X86 */
41
+
42
+
bool intel_match_g8_cpu(void) { return false; }
43
+
44
+
#endif /* CONFIG_X86 */
+13
drivers/gpu/drm/i915/intel_cpu_info.h
+13
drivers/gpu/drm/i915/intel_cpu_info.h
+9
drivers/gpu/drm/i915/intel_device_info.c
+9
drivers/gpu/drm/i915/intel_device_info.c
···
200
200
INTEL_DG2_G12_IDS(ID),
201
201
};
202
202
203
+
static const u16 subplatform_dg2_d_ids[] = {
204
+
INTEL_DG2_D_IDS(ID),
205
+
};
206
+
203
207
static const u16 subplatform_arl_h_ids[] = {
204
208
INTEL_ARL_H_IDS(ID),
205
209
};
···
283
279
ARRAY_SIZE(subplatform_arl_s_ids))) {
284
280
mask = BIT(INTEL_SUBPLATFORM_ARL_S);
285
281
}
282
+
283
+
/* DG2_D ids span across multiple DG2 subplatforms */
284
+
if (find_devid(devid, subplatform_dg2_d_ids,
285
+
ARRAY_SIZE(subplatform_dg2_d_ids)))
286
+
mask |= BIT(INTEL_SUBPLATFORM_D);
286
287
287
288
GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
288
289
+4
-1
drivers/gpu/drm/i915/intel_device_info.h
+4
-1
drivers/gpu/drm/i915/intel_device_info.h
···
95
95
/*
96
96
* Subplatform bits share the same namespace per parent platform. In other words
97
97
* it is fine for the same bit to be used on multiple parent platforms.
98
+
* Devices can belong to multiple subplatforms if needed, so it's possible to set
99
+
* multiple bits for same device.
98
100
*/
99
101
100
-
#define INTEL_SUBPLATFORM_BITS (3)
102
+
#define INTEL_SUBPLATFORM_BITS (4)
101
103
#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
102
104
103
105
/* HSW/BDW/SKL/KBL/CFL */
···
116
114
#define INTEL_SUBPLATFORM_G10 0
117
115
#define INTEL_SUBPLATFORM_G11 1
118
116
#define INTEL_SUBPLATFORM_G12 2
117
+
#define INTEL_SUBPLATFORM_D 3
119
118
120
119
/* ADL */
121
120
#define INTEL_SUBPLATFORM_RPL 0
+1
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+1
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+6
-1
drivers/gpu/drm/i915/intel_uncore.c
+6
-1
drivers/gpu/drm/i915/intel_uncore.c
···
31
31
#include "i915_drv.h"
32
32
#include "i915_iosf_mbi.h"
33
33
#include "i915_reg.h"
34
-
#include "i915_trace.h"
35
34
#include "i915_vgpu.h"
35
+
#include "intel_uncore_trace.h"
36
36
37
37
#define FORCEWAKE_ACK_TIMEOUT_MS 50
38
38
#define GT_FIFO_TIMEOUT_MS 10
39
+
40
+
struct intel_uncore *to_intel_uncore(struct drm_device *drm)
41
+
{
42
+
return &to_i915(drm)->uncore;
43
+
}
39
44
40
45
#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
41
46
+2
drivers/gpu/drm/i915/intel_uncore.h
+2
drivers/gpu/drm/i915/intel_uncore.h
+7
drivers/gpu/drm/i915/intel_uncore_trace.c
+7
drivers/gpu/drm/i915/intel_uncore_trace.c
+49
drivers/gpu/drm/i915/intel_uncore_trace.h
+49
drivers/gpu/drm/i915/intel_uncore_trace.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/* Copyright © 2024 Intel Corporation */
3
+
4
+
#undef TRACE_SYSTEM
5
+
#define TRACE_SYSTEM i915
6
+
7
+
#if !defined(__INTEL_UNCORE_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ)
8
+
#define __INTEL_UNCORE_TRACE_H__
9
+
10
+
#include "i915_reg_defs.h"
11
+
12
+
#include <linux/types.h>
13
+
#include <linux/tracepoint.h>
14
+
15
+
TRACE_EVENT_CONDITION(i915_reg_rw,
16
+
TP_PROTO(bool write, i915_reg_t reg, u64 val, int len, bool trace),
17
+
18
+
TP_ARGS(write, reg, val, len, trace),
19
+
20
+
TP_CONDITION(trace),
21
+
22
+
TP_STRUCT__entry(
23
+
__field(u64, val)
24
+
__field(u32, reg)
25
+
__field(u16, write)
26
+
__field(u16, len)
27
+
),
28
+
29
+
TP_fast_assign(
30
+
__entry->val = (u64)val;
31
+
__entry->reg = i915_mmio_reg_offset(reg);
32
+
__entry->write = write;
33
+
__entry->len = len;
34
+
),
35
+
36
+
TP_printk("%s reg=0x%x, len=%d, val=(0x%x, 0x%x)",
37
+
__entry->write ? "write" : "read",
38
+
__entry->reg, __entry->len,
39
+
(u32)(__entry->val & 0xffffffff),
40
+
(u32)(__entry->val >> 32))
41
+
);
42
+
#endif /* __INTEL_UNCORE_TRACE_H__ */
43
+
44
+
/* This part must be outside protection */
45
+
#undef TRACE_INCLUDE_PATH
46
+
#undef TRACE_INCLUDE_FILE
47
+
#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915
48
+
#define TRACE_INCLUDE_FILE intel_uncore_trace
49
+
#include <trace/define_trace.h>
+11
-1
drivers/gpu/drm/i915/selftests/igt_flush_test.c
+11
-1
drivers/gpu/drm/i915/selftests/igt_flush_test.c
···
19
19
int ret = 0;
20
20
21
21
for_each_gt(gt, i915, i) {
22
+
struct intel_engine_cs *engine;
23
+
unsigned long timeout_ms = 0;
24
+
unsigned int id;
25
+
22
26
if (intel_gt_is_wedged(gt))
23
27
ret = -EIO;
24
28
29
+
for_each_engine(engine, gt, id) {
30
+
if (engine->props.preempt_timeout_ms > timeout_ms)
31
+
timeout_ms = engine->props.preempt_timeout_ms;
32
+
}
33
+
25
34
cond_resched();
26
35
27
-
if (intel_gt_wait_for_idle(gt, HZ * 3) == -ETIME) {
36
+
/* 2x longest preempt timeout, experimentally determined */
37
+
if (intel_gt_wait_for_idle(gt, HZ * timeout_ms / 500) == -ETIME) {
28
38
pr_err("%pS timed out, cancelling all further testing.\n",
29
39
__builtin_return_address(0));
30
40
+1
drivers/gpu/drm/i915/vlv_suspend.c
+1
drivers/gpu/drm/i915/vlv_suspend.c
+1
-2
drivers/gpu/drm/nouveau/dispnv50/disp.c
+1
-2
drivers/gpu/drm/nouveau/dispnv50/disp.c
···
992
992
if (!mst_state->pbn_div.full) {
993
993
struct nouveau_encoder *outp = mstc->mstm->outp;
994
994
995
-
mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr,
996
-
outp->dp.link_bw, outp->dp.link_nr);
995
+
mst_state->pbn_div = drm_dp_get_vc_payload_bw(outp->dp.link_bw, outp->dp.link_nr);
997
996
}
998
997
999
998
slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);
+1
-16
drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
+1
-16
drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
···
199
199
static void drm_test_dp_mst_calc_pbn_div(struct kunit *test)
200
200
{
201
201
const struct drm_dp_mst_calc_pbn_div_test *params = test->param_value;
202
-
/* mgr->dev is only needed by drm_dbg_kms(), but it's not called for the test cases. */
203
-
struct drm_dp_mst_topology_mgr *mgr = test->priv;
204
202
205
-
KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(mgr, params->link_rate, params->lane_count).full,
203
+
KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(params->link_rate, params->lane_count).full,
206
204
params->expected.full);
207
205
}
208
206
···
566
568
{ }
567
569
};
568
570
569
-
static int drm_dp_mst_helper_tests_init(struct kunit *test)
570
-
{
571
-
struct drm_dp_mst_topology_mgr *mgr;
572
-
573
-
mgr = kunit_kzalloc(test, sizeof(*mgr), GFP_KERNEL);
574
-
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, mgr);
575
-
576
-
test->priv = mgr;
577
-
578
-
return 0;
579
-
}
580
-
581
571
static struct kunit_suite drm_dp_mst_helper_test_suite = {
582
572
.name = "drm_dp_mst_helper",
583
-
.init = drm_dp_mst_helper_tests_init,
584
573
.test_cases = drm_dp_mst_helper_tests,
585
574
};
586
575
+1
drivers/gpu/drm/xe/Makefile
+1
drivers/gpu/drm/xe/Makefile
···
209
209
i915-display/intel_ddi.o \
210
210
i915-display/intel_ddi_buf_trans.o \
211
211
i915-display/intel_display.o \
212
+
i915-display/intel_display_conversion.o \
212
213
i915-display/intel_display_device.o \
213
214
i915-display/intel_display_driver.o \
214
215
i915-display/intel_display_irq.o \
drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore_trace.h
drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore_trace.h
+5
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
+5
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
···
10
10
#include "xe_device_types.h"
11
11
#include "xe_mmio.h"
12
12
13
+
static inline struct intel_uncore *to_intel_uncore(struct drm_device *drm)
14
+
{
15
+
return &to_xe_device(drm)->uncore;
16
+
}
17
+
13
18
static inline struct xe_mmio *__compat_uncore_to_mmio(struct intel_uncore *uncore)
14
19
{
15
20
struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
+1
-1
drivers/gpu/drm/xe/display/xe_display.c
+1
-1
drivers/gpu/drm/xe/display/xe_display.c
+1
-2
include/drm/display/drm_dp_mst_helper.h
+1
-2
include/drm/display/drm_dp_mst_helper.h
···
867
867
struct drm_dp_mst_topology_mgr *mgr,
868
868
struct drm_dp_mst_port *port);
869
869
870
-
fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
871
-
int link_rate, int link_lane_count);
870
+
fixed20_12 drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count);
872
871
873
872
int drm_dp_calc_pbn_mode(int clock, int bpp);
874
873
+42
-13
include/drm/intel/pciids.h
+42
-13
include/drm/intel/pciids.h
···
717
717
MACRO__(0xA7AB, ## __VA_ARGS__)
718
718
719
719
/* DG2 */
720
-
#define INTEL_DG2_G10_IDS(MACRO__, ...) \
721
-
MACRO__(0x5690, ## __VA_ARGS__), \
722
-
MACRO__(0x5691, ## __VA_ARGS__), \
723
-
MACRO__(0x5692, ## __VA_ARGS__), \
720
+
#define INTEL_DG2_G10_D_IDS(MACRO__, ...) \
724
721
MACRO__(0x56A0, ## __VA_ARGS__), \
725
722
MACRO__(0x56A1, ## __VA_ARGS__), \
726
-
MACRO__(0x56A2, ## __VA_ARGS__), \
723
+
MACRO__(0x56A2, ## __VA_ARGS__)
724
+
725
+
#define INTEL_DG2_G10_E_IDS(MACRO__, ...) \
727
726
MACRO__(0x56BE, ## __VA_ARGS__), \
728
727
MACRO__(0x56BF, ## __VA_ARGS__)
729
728
730
-
#define INTEL_DG2_G11_IDS(MACRO__, ...) \
731
-
MACRO__(0x5693, ## __VA_ARGS__), \
732
-
MACRO__(0x5694, ## __VA_ARGS__), \
733
-
MACRO__(0x5695, ## __VA_ARGS__), \
729
+
#define INTEL_DG2_G10_M_IDS(MACRO__, ...) \
730
+
MACRO__(0x5690, ## __VA_ARGS__), \
731
+
MACRO__(0x5691, ## __VA_ARGS__), \
732
+
MACRO__(0x5692, ## __VA_ARGS__)
733
+
734
+
#define INTEL_DG2_G10_IDS(MACRO__, ...) \
735
+
INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
736
+
INTEL_DG2_G10_E_IDS(MACRO__, ## __VA_ARGS__), \
737
+
INTEL_DG2_G10_M_IDS(MACRO__, ## __VA_ARGS__)
738
+
739
+
#define INTEL_DG2_G11_D_IDS(MACRO__, ...) \
734
740
MACRO__(0x56A5, ## __VA_ARGS__), \
735
741
MACRO__(0x56A6, ## __VA_ARGS__), \
736
742
MACRO__(0x56B0, ## __VA_ARGS__), \
737
-
MACRO__(0x56B1, ## __VA_ARGS__), \
743
+
MACRO__(0x56B1, ## __VA_ARGS__)
744
+
745
+
#define INTEL_DG2_G11_E_IDS(MACRO__, ...) \
738
746
MACRO__(0x56BA, ## __VA_ARGS__), \
739
747
MACRO__(0x56BB, ## __VA_ARGS__), \
740
748
MACRO__(0x56BC, ## __VA_ARGS__), \
741
749
MACRO__(0x56BD, ## __VA_ARGS__)
742
750
743
-
#define INTEL_DG2_G12_IDS(MACRO__, ...) \
744
-
MACRO__(0x5696, ## __VA_ARGS__), \
745
-
MACRO__(0x5697, ## __VA_ARGS__), \
751
+
#define INTEL_DG2_G11_M_IDS(MACRO__, ...) \
752
+
MACRO__(0x5693, ## __VA_ARGS__), \
753
+
MACRO__(0x5694, ## __VA_ARGS__), \
754
+
MACRO__(0x5695, ## __VA_ARGS__)
755
+
756
+
#define INTEL_DG2_G11_IDS(MACRO__, ...) \
757
+
INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
758
+
INTEL_DG2_G11_E_IDS(MACRO__, ## __VA_ARGS__), \
759
+
INTEL_DG2_G11_M_IDS(MACRO__, ## __VA_ARGS__)
760
+
761
+
#define INTEL_DG2_G12_D_IDS(MACRO__, ...) \
746
762
MACRO__(0x56A3, ## __VA_ARGS__), \
747
763
MACRO__(0x56A4, ## __VA_ARGS__), \
748
764
MACRO__(0x56B2, ## __VA_ARGS__), \
749
765
MACRO__(0x56B3, ## __VA_ARGS__)
766
+
767
+
#define INTEL_DG2_G12_M_IDS(MACRO__, ...) \
768
+
MACRO__(0x5696, ## __VA_ARGS__), \
769
+
MACRO__(0x5697, ## __VA_ARGS__)
770
+
771
+
#define INTEL_DG2_G12_IDS(MACRO__, ...) \
772
+
INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__), \
773
+
INTEL_DG2_G12_M_IDS(MACRO__, ## __VA_ARGS__)
774
+
775
+
#define INTEL_DG2_D_IDS(MACRO__, ...) \
776
+
INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
777
+
INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
778
+
INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__)
750
779
751
780
#define INTEL_DG2_IDS(MACRO__, ...) \
752
781
INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \