Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: correct DP MST interface configuration
Due to historical reasons we ended up with dummy values being specified
for MST-related interfaces some of them had INTF_NONE, others had
non-existing DP controller indices. Those workarounds are no longer
necessary. Fix types and indices for all DP-MST related INTF instances.
The only exception is INTF_3 on SC8180X, which has unique design. It can
be used either with INTF_0 / DP0 or with INTF_4 / DP1. This interface is
left with the dummy value until somebody implements necessary bits for
that platform.
Co-developed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/713988/
Link: https://lore.kernel.org/r/20260325-fix-dp-mst-interfaces-v1-1-186d1de3fa1b@oss.qualcomm.com
+28
-31
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
···
377
377
.name = "intf_3", .id = INTF_3,
378
378
.base = 0x37000, .len = 0x280,
379
379
.type = INTF_DP,
380
-
.controller_id = MSM_DP_CONTROLLER_1,
380
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
381
381
.prog_fetch_lines_worst_case = 24,
382
382
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
383
383
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
···
419
419
.name = "intf_3", .id = INTF_3,
420
420
.base = 0x37000, .len = 0x4bc,
421
421
.type = INTF_DP,
422
-
.controller_id = MSM_DP_CONTROLLER_1,
422
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
423
423
.prog_fetch_lines_worst_case = 24,
424
424
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
425
425
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+3
-3
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
+3
-3
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
···
425
425
}, {
426
426
.name = "intf_3", .id = INTF_3,
427
427
.base = 0x37000, .len = 0x400,
428
-
.type = INTF_NONE,
428
+
.type = INTF_DP,
429
429
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
430
430
.prog_fetch_lines_worst_case = 24,
431
431
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
···
457
457
}, {
458
458
.name = "intf_7", .id = INTF_7,
459
459
.base = 0x3b000, .len = 0x400,
460
-
.type = INTF_NONE,
460
+
.type = INTF_DP,
461
461
.controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
462
462
.prog_fetch_lines_worst_case = 24,
463
463
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
···
465
465
}, {
466
466
.name = "intf_8", .id = INTF_8,
467
467
.base = 0x3c000, .len = 0x400,
468
-
.type = INTF_NONE,
468
+
.type = INTF_DP,
469
469
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
470
470
.prog_fetch_lines_worst_case = 24,
471
471
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
···
417
417
.name = "intf_3", .id = INTF_3,
418
418
.base = 0x190000, .len = 0x4bc,
419
419
.type = INTF_DP,
420
-
.controller_id = MSM_DP_CONTROLLER_1,
420
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
421
421
.prog_fetch_lines_worst_case = 24,
422
422
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
423
423
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
···
258
258
.name = "intf_3", .id = INTF_3,
259
259
.base = 0x6b800, .len = 0x280,
260
260
.type = INTF_DP,
261
-
.controller_id = MSM_DP_CONTROLLER_1,
261
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
262
262
.prog_fetch_lines_worst_case = 24,
263
263
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
264
264
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
···
316
316
.name = "intf_3", .id = INTF_3,
317
317
.base = 0x6b800, .len = 0x280,
318
318
.type = INTF_DP,
319
-
.controller_id = MSM_DP_CONTROLLER_1,
319
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
320
320
.prog_fetch_lines_worst_case = 24,
321
321
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
322
322
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
···
230
230
.name = "intf_3", .id = INTF_3,
231
231
.base = 0x6b800, .len = 0x280,
232
232
.type = INTF_DP,
233
-
.controller_id = MSM_DP_CONTROLLER_1,
233
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
234
234
.prog_fetch_lines_worst_case = 24,
235
235
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
236
236
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
···
185
185
.name = "intf_3", .id = INTF_3,
186
186
.base = 0x6b800, .len = 0x280,
187
187
.type = INTF_DP,
188
-
.controller_id = MSM_DP_CONTROLLER_1,
188
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
189
189
.prog_fetch_lines_worst_case = 24,
190
190
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
191
191
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
···
301
301
.name = "intf_3", .id = INTF_3,
302
302
.base = 0x6b800, .len = 0x280,
303
303
.type = INTF_DP,
304
-
.controller_id = MSM_DP_CONTROLLER_1,
304
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
305
305
.prog_fetch_lines_worst_case = 24,
306
306
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
307
307
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
···
326
326
.name = "intf_3", .id = INTF_3,
327
327
.base = 0x37000, .len = 0x280,
328
328
.type = INTF_DP,
329
-
.controller_id = MSM_DP_CONTROLLER_1,
329
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
330
330
.prog_fetch_lines_worst_case = 24,
331
331
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
332
332
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+6
-7
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+6
-7
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
···
288
288
},
289
289
};
290
290
291
-
/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
292
291
static const struct dpu_intf_cfg sc8280xp_intf[] = {
293
292
{
294
293
.name = "intf_0", .id = INTF_0,
···
318
319
}, {
319
320
.name = "intf_3", .id = INTF_3,
320
321
.base = 0x37000, .len = 0x280,
321
-
.type = INTF_NONE,
322
-
.controller_id = MSM_DP_CONTROLLER_0,
322
+
.type = INTF_DP,
323
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
323
324
.prog_fetch_lines_worst_case = 24,
324
325
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
325
326
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
···
350
351
}, {
351
352
.name = "intf_7", .id = INTF_7,
352
353
.base = 0x3b000, .len = 0x280,
353
-
.type = INTF_NONE,
354
-
.controller_id = MSM_DP_CONTROLLER_2,
354
+
.type = INTF_DP,
355
+
.controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
355
356
.prog_fetch_lines_worst_case = 24,
356
357
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
357
358
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
358
359
}, {
359
360
.name = "intf_8", .id = INTF_8,
360
361
.base = 0x3c000, .len = 0x280,
361
-
.type = INTF_NONE,
362
-
.controller_id = MSM_DP_CONTROLLER_1,
362
+
.type = INTF_DP,
363
+
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_8 for DP MST */
363
364
.prog_fetch_lines_worst_case = 24,
364
365
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
365
366
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
···
339
339
.name = "intf_3", .id = INTF_3,
340
340
.base = 0x37000, .len = 0x280,
341
341
.type = INTF_DP,
342
-
.controller_id = MSM_DP_CONTROLLER_1,
342
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
343
343
.prog_fetch_lines_worst_case = 24,
344
344
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
345
345
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+4
-5
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
+4
-5
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
···
315
315
},
316
316
};
317
317
318
-
/* TODO: INTF 3, 6, 7 and 8 are used for MST, marked as INTF_NONE for now */
319
318
static const struct dpu_intf_cfg sa8775p_intf[] = {
320
319
{
321
320
.name = "intf_0", .id = INTF_0,
···
345
346
}, {
346
347
.name = "intf_3", .id = INTF_3,
347
348
.base = 0x37000, .len = 0x280,
348
-
.type = INTF_NONE,
349
+
.type = INTF_DP,
349
350
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
350
351
.prog_fetch_lines_worst_case = 24,
351
352
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
···
361
362
}, {
362
363
.name = "intf_6", .id = INTF_6,
363
364
.base = 0x3A000, .len = 0x280,
364
-
.type = INTF_NONE,
365
+
.type = INTF_DP,
365
366
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
366
367
.prog_fetch_lines_worst_case = 24,
367
368
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
···
369
370
}, {
370
371
.name = "intf_7", .id = INTF_7,
371
372
.base = 0x3b000, .len = 0x280,
372
-
.type = INTF_NONE,
373
+
.type = INTF_DP,
373
374
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
374
375
.prog_fetch_lines_worst_case = 24,
375
376
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
···
377
378
}, {
378
379
.name = "intf_8", .id = INTF_8,
379
380
.base = 0x3c000, .len = 0x280,
380
-
.type = INTF_NONE,
381
+
.type = INTF_DP,
381
382
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
382
383
.prog_fetch_lines_worst_case = 24,
383
384
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
···
334
334
.name = "intf_3", .id = INTF_3,
335
335
.base = 0x37000, .len = 0x280,
336
336
.type = INTF_DP,
337
-
.controller_id = MSM_DP_CONTROLLER_1,
337
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
338
338
.prog_fetch_lines_worst_case = 24,
339
339
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
340
340
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
···
334
334
.name = "intf_3", .id = INTF_3,
335
335
.base = 0x37000, .len = 0x280,
336
336
.type = INTF_DP,
337
-
.controller_id = MSM_DP_CONTROLLER_1,
337
+
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
338
338
.prog_fetch_lines_worst_case = 24,
339
339
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
340
340
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+3
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+3
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
···
303
303
},
304
304
};
305
305
306
-
/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
307
306
static const struct dpu_intf_cfg x1e80100_intf[] = {
308
307
{
309
308
.name = "intf_0", .id = INTF_0,
···
333
334
}, {
334
335
.name = "intf_3", .id = INTF_3,
335
336
.base = 0x37000, .len = 0x280,
336
-
.type = INTF_NONE,
337
+
.type = INTF_DP,
337
338
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
338
339
.prog_fetch_lines_worst_case = 24,
339
340
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
···
365
366
}, {
366
367
.name = "intf_7", .id = INTF_7,
367
368
.base = 0x3b000, .len = 0x280,
368
-
.type = INTF_NONE,
369
+
.type = INTF_DP,
369
370
.controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
370
371
.prog_fetch_lines_worst_case = 24,
371
372
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
···
373
374
}, {
374
375
.name = "intf_8", .id = INTF_8,
375
376
.base = 0x3c000, .len = 0x280,
376
-
.type = INTF_NONE,
377
+
.type = INTF_DP,
377
378
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
378
379
.prog_fetch_lines_worst_case = 24,
379
380
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),