Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Core changes:
- Drop the unused devm_pinctrl_unregister() function
- Move pretended generic pin control functionality out of the core
and into the Amlogic AM4 driver. We have something better coming
(hopefully)
New hardware support:
- Spacemit K3 (RISC-V) pin control support
- Atmel AT91 PIO4 (ARM32) SAMA7D65 pin control support
- Exynos9610 (ARM64) pin control support
- Qualcomm Mahua TLMM (ARM64) pin control support
- Microchip Polarfire MSSIO (RISC-V) pin control support
- Ocelot LAN9645XF (multiplatform) pin control support
Improvements:
- Using a few more guards for locking
- Various nonurgent fixes and tweaks"
* tag 'pinctrl-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (73 commits)
pinctrl: generic: move function to amlogic-am4 driver
pinctrl: intel: Align Copyright note with corporate guidelines
pinctrl: mediatek: remove unused drv_offset field
pinctrl: canaan: k230: Fix NULL pointer dereference when parsing devicetree
pinctrl: single: fix refcount leak in pcs_add_gpio_func()
pinctrl: meson: amlogic-a4: Fix device node reference leak in bank helpers
pinctrl: qcom: sm8250-lpass-lpi: Fix i2s2_data_groups definition
pinctrl: core: Remove duplicate error messages
pinctrl: core: Simplify devm_pinctrl_*()
pinctrl: core: Remove unused devm_pinctrl_unregister()
dt-bindings: pinctrl: spacemit: fix drive-strength check warning
pinctrl: fix kismet issues with GENERIC_PINCTRL
pinctrl: tangier: Join tng_pinctrl_probe() into its wrapper
pinctrl: tangier: Remove duplicate error messages
pinctrl: lynxpoint: Remove duplicate error messages
pinctrl: cherryview: Remove duplicate error messages
pinctrl: baytrail: Remove duplicate error messages
pinctrl: intel: Remove duplicate error messages
pinctrl: equilibrium: Fix device node reference leak in pinbank_init()
dt-bindings: pinctrl: pinctrl-microchip-sgpio: add LAN969x
...
+2671
-497
+1
-1
Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+1
-1
Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
···
106
106
# the pin numbers then,
107
107
# - Finally, the name will end with either -pin or pins.
108
108
109
-
"^([rs]-)?(([a-z0-9]{3,}|[a-oq-z][a-z0-9]*?)?-)+?(p[a-ilm][0-9]*?-)??pins?$":
109
+
"^([rs]-)?(([a-z0-9]{3,}|[a-oq-z0-9][a-z0-9]*?)?-)+?(p[a-ilm][0-9]*?-)??pins?$":
110
110
type: object
111
111
112
112
properties:
+1
-1
Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml
+1
-1
Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml
+109
Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
+109
Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Microchip Polarfire SoC MSSIO pinctrl
8
+
9
+
maintainers:
10
+
- Conor Dooley <conor.dooley@microchip.com>
11
+
12
+
properties:
13
+
compatible:
14
+
oneOf:
15
+
- const: microchip,mpfs-pinctrl-mssio
16
+
- items:
17
+
- const: microchip,pic64gx-pinctrl-mssio
18
+
- const: microchip,mpfs-pinctrl-mssio
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
pinctrl-use-default: true
24
+
25
+
patternProperties:
26
+
'-cfg$':
27
+
type: object
28
+
additionalProperties: false
29
+
30
+
patternProperties:
31
+
'-pins$':
32
+
type: object
33
+
additionalProperties: false
34
+
35
+
allOf:
36
+
- $ref: pincfg-node.yaml#
37
+
- $ref: pinmux-node.yaml#
38
+
39
+
properties:
40
+
pins:
41
+
description:
42
+
The list of IOs that properties in the pincfg node apply to.
43
+
44
+
function:
45
+
description:
46
+
A string containing the name of the function to mux for these
47
+
pins. The "reserved" function tristates a pin.
48
+
enum: [ sd, emmc, qspi, spi, usb, uart, i2c, can, mdio, misc
49
+
reserved, gpio, fabric-test, tied-low, tied-high, tristate ]
50
+
51
+
bias-bus-hold: true
52
+
bias-disable: true
53
+
bias-pull-down: true
54
+
bias-pull-up: true
55
+
input-schmitt-enable: true
56
+
low-power-enable: true
57
+
58
+
drive-strength:
59
+
enum: [ 2, 4, 6, 8, 10, 12, 16, 20 ]
60
+
61
+
power-source:
62
+
description:
63
+
Which bank voltage to use. This cannot differ for pins in a
64
+
given bank, the whole bank uses the same voltage.
65
+
enum: [ 1200000, 1500000, 1800000, 2500000, 3300000 ]
66
+
67
+
microchip,clamp-diode:
68
+
$ref: /schemas/types.yaml#/definitions/flag
69
+
description:
70
+
Reflects the "Clamp Diode" setting in the MSS Configurator for
71
+
this pin. This setting controls whether or not input voltage
72
+
clamping should be enabled.
73
+
74
+
microchip,ibufmd:
75
+
$ref: /schemas/types.yaml#/definitions/uint32
76
+
default: 0
77
+
description:
78
+
Reflects the "IBUFMD" bits in the MSS Configurator output files
79
+
for this pin.
80
+
81
+
required:
82
+
- pins
83
+
- function
84
+
- power-source
85
+
86
+
required:
87
+
- compatible
88
+
- reg
89
+
90
+
additionalProperties: false
91
+
92
+
examples:
93
+
- |
94
+
pinctrl@204 {
95
+
compatible = "microchip,mpfs-pinctrl-mssio";
96
+
reg = <0x204 0x7c>;
97
+
98
+
ikrd-spi1-cfg {
99
+
spi1-pins {
100
+
pins = <30>, <31>, <32>, <33>;
101
+
function = "spi";
102
+
bias-pull-up;
103
+
drive-strength = <8>;
104
+
power-source = <3300000>;
105
+
microchip,ibufmd = <0x1>;
106
+
};
107
+
};
108
+
};
109
+
...
+15
-5
Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
+15
-5
Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
···
21
21
pattern: '^gpio@[0-9a-f]+$'
22
22
23
23
compatible:
24
-
enum:
25
-
- microchip,sparx5-sgpio
26
-
- mscc,ocelot-sgpio
27
-
- mscc,luton-sgpio
24
+
oneOf:
25
+
- enum:
26
+
- microchip,sparx5-sgpio
27
+
- mscc,ocelot-sgpio
28
+
- mscc,luton-sgpio
29
+
- items:
30
+
- enum:
31
+
- microchip,lan9691-sgpio
32
+
- const: microchip,sparx5-sgpio
28
33
29
34
'#address-cells':
30
35
const: 1
···
85
80
type: object
86
81
properties:
87
82
compatible:
88
-
const: microchip,sparx5-sgpio-bank
83
+
oneOf:
84
+
- items:
85
+
- enum:
86
+
- microchip,lan9691-sgpio-bank
87
+
- const: microchip,sparx5-sgpio-bank
88
+
- const: microchip,sparx5-sgpio-bank
89
89
90
90
reg:
91
91
description: |
+6
Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
+6
Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
···
14
14
compatible:
15
15
oneOf:
16
16
- enum:
17
+
- microchip,lan96455f-pinctrl
17
18
- microchip,lan966x-pinctrl
18
19
- microchip,lan9691-pinctrl
19
20
- microchip,sparx5-pinctrl
···
31
30
- microchip,lan9693-pinctrl
32
31
- microchip,lan9692-pinctrl
33
32
- const: microchip,lan9691-pinctrl
33
+
- items:
34
+
- enum:
35
+
- microchip,lan96457f-pinctrl
36
+
- microchip,lan96459f-pinctrl
37
+
- const: microchip,lan96455f-pinctrl
34
38
35
39
reg:
36
40
items:
+4
-2
Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml
+4
-2
Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml
···
10
10
- Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
11
11
12
12
description:
13
-
Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC.
13
+
Top Level Mode Multiplexer pin controller in Qualcomm Glymur and Mahua SoC.
14
14
15
15
allOf:
16
16
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
17
18
18
properties:
19
19
compatible:
20
-
const: qcom,glymur-tlmm
20
+
enum:
21
+
- qcom,glymur-tlmm
22
+
- qcom,mahua-tlmm
21
23
22
24
reg:
23
25
maxItems: 1
+13
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
+13
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
···
49
49
gpio-ranges:
50
50
maxItems: 1
51
51
52
+
interrupt-controller: true
53
+
54
+
'#interrupt-cells':
55
+
const: 2
56
+
description:
57
+
The first cell contains the global GPIO port index, constructed using the
58
+
RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
59
+
and the second cell is used to specify the flag.
60
+
E.g. "interrupts = <RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>;" if P08_6 is
61
+
being used as an interrupt.
62
+
52
63
clocks:
53
64
maxItems: 1
54
65
···
150
139
gpio-controller;
151
140
#gpio-cells = <2>;
152
141
gpio-ranges = <&pinctrl 0 0 288>;
142
+
interrupt-controller;
143
+
#interrupt-cells = <2>;
153
144
power-domains = <&cpg>;
154
145
155
146
serial0-pins {
+1
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
+1
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
+1
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+1
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+22
-5
Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
+22
-5
Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
···
11
11
12
12
properties:
13
13
compatible:
14
-
const: spacemit,k1-pinctrl
14
+
enum:
15
+
- spacemit,k1-pinctrl
16
+
- spacemit,k3-pinctrl
15
17
16
18
reg:
17
19
items:
···
31
29
32
30
resets:
33
31
maxItems: 1
32
+
33
+
spacemit,apbc:
34
+
$ref: /schemas/types.yaml#/definitions/phandle
35
+
description: Phandle to syscon that access the protected register
34
36
35
37
patternProperties:
36
38
'-cfg$':
···
78
72
enum: [ 0, 1 ]
79
73
80
74
drive-strength:
81
-
description: |
82
-
typical current when output high level.
83
-
1.8V output: 11, 21, 32, 42 (mA)
84
-
3.3V output: 7, 10, 13, 16, 19, 23, 26, 29 (mA)
75
+
description:
76
+
typical current (in mA) when the output at high level.
77
+
anyOf:
78
+
- enum: [ 11, 21, 32, 42 ]
79
+
description: For K1 SoC, 1.8V voltage output
80
+
81
+
- enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ]
82
+
description: For K1 SoC, 3.3V voltage output
83
+
84
+
- enum: [ 2, 4, 6, 7, 9, 11, 13, 14, 21, 23, 25, 26, 28, 30, 31, 33 ]
85
+
description: For K3 SoC, 1.8V voltage output
86
+
87
+
- enum: [ 3, 5, 7, 9, 11, 13, 15, 17, 25, 27, 29, 31, 33, 35, 37, 38 ]
88
+
description: For K3 SoC, 3.3V voltage output
85
89
86
90
input-schmitt:
87
91
description: |
···
142
126
clocks = <&syscon_apbc 42>,
143
127
<&syscon_apbc 94>;
144
128
clock-names = "func", "bus";
129
+
spacemit,apbc = <&syscon_apbc>;
145
130
146
131
uart0_2_cfg: uart0-2-cfg {
147
132
uart0-2-pins {
+4
Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
+4
Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
-1
Documentation/driver-api/driver-model/devres.rst
-1
Documentation/driver-api/driver-model/devres.rst
+4
-2
MAINTAINERS
+4
-2
MAINTAINERS
···
22666
22666
F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
22667
22667
F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml
22668
22668
F: Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
22669
+
F: Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
22669
22670
F: Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml
22670
22671
F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
22671
22672
F: Documentation/devicetree/bindings/riscv/microchip.yaml
···
22681
22680
F: drivers/i2c/busses/i2c-microchip-corei2c.c
22682
22681
F: drivers/mailbox/mailbox-mpfs.c
22683
22682
F: drivers/pci/controller/plda/pcie-microchip-host.c
22684
-
F: drivers/pinctrl/pinctrl-mpfs-iomux0.c
22685
-
F: drivers/pinctrl/pinctrl-pic64gx-gpio2.c
22683
+
F: drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c
22684
+
F: drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
22685
+
F: drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c
22686
22686
F: drivers/pwm/pwm-microchip-core.c
22687
22687
F: drivers/reset/reset-mpfs.c
22688
22688
F: drivers/rtc/rtc-mpfs.c
+9
drivers/base/base.h
+9
drivers/base/base.h
···
302
302
303
303
void software_node_notify(struct device *dev);
304
304
void software_node_notify_remove(struct device *dev);
305
+
306
+
#ifdef CONFIG_PINCTRL
307
+
int pinctrl_bind_pins(struct device *dev);
308
+
#else
309
+
static inline int pinctrl_bind_pins(struct device *dev)
310
+
{
311
+
return 0;
312
+
}
313
+
#endif /* CONFIG_PINCTRL */
+2
drivers/base/pinctrl.c
+2
drivers/base/pinctrl.c
+7
-19
drivers/pinctrl/Kconfig
+7
-19
drivers/pinctrl/Kconfig
···
25
25
bool
26
26
select PINCONF
27
27
28
+
config GENERIC_PINCTRL
29
+
bool
30
+
select GENERIC_PINCONF
31
+
select GENERIC_PINCTRL_GROUPS
32
+
select GENERIC_PINMUX_FUNCTIONS
33
+
28
34
config DEBUG_PINCTRL
29
35
bool "Debug PINCTRL calls"
30
36
depends on DEBUG_KERNEL
···
492
486
def_bool y if PIC32MZDA
493
487
select PINCTRL_PIC32
494
488
495
-
config PINCTRL_PIC64GX
496
-
bool "pic64gx gpio2 pinctrl driver"
497
-
depends on ARCH_MICROCHIP || COMPILE_TEST
498
-
depends on OF
499
-
select GENERIC_PINCONF
500
-
select REGMAP_MMIO
501
-
default y
502
-
help
503
-
This selects the pinctrl driver for gpio2 on pic64gx.
504
-
505
489
config PINCTRL_PISTACHIO
506
490
bool "IMG Pistachio SoC pinctrl driver"
507
491
depends on OF && (MIPS || COMPILE_TEST)
···
502
506
select OF_GPIO
503
507
help
504
508
This support pinctrl and GPIO driver for IMG Pistachio SoC.
505
-
506
-
config PINCTRL_POLARFIRE_SOC
507
-
bool "Polarfire SoC pinctrl driver"
508
-
depends on ARCH_MICROCHIP || COMPILE_TEST
509
-
depends on OF
510
-
select GENERIC_PINCONF
511
-
default y
512
-
help
513
-
This selects the pinctrl driver for Microchip Polarfire SoC.
514
509
515
510
config PINCTRL_RK805
516
511
tristate "Pinctrl and GPIO driver for RK805 PMIC"
···
697
710
source "drivers/pinctrl/intel/Kconfig"
698
711
source "drivers/pinctrl/mediatek/Kconfig"
699
712
source "drivers/pinctrl/meson/Kconfig"
713
+
source "drivers/pinctrl/microchip/Kconfig"
700
714
source "drivers/pinctrl/mvebu/Kconfig"
701
715
source "drivers/pinctrl/nomadik/Kconfig"
702
716
source "drivers/pinctrl/nuvoton/Kconfig"
+2
-2
drivers/pinctrl/Makefile
+2
-2
drivers/pinctrl/Makefile
···
7
7
obj-$(CONFIG_PINMUX) += pinmux.o
8
8
obj-$(CONFIG_PINCONF) += pinconf.o
9
9
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
10
+
obj-$(CONFIG_GENERIC_PINCTRL) += pinctrl-generic.o
10
11
obj-$(CONFIG_OF) += devicetree.o
11
12
12
13
obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
···
49
48
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
50
49
obj-$(CONFIG_PINCTRL_PEF2256) += pinctrl-pef2256.o
51
50
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
52
-
obj-$(CONFIG_PINCTRL_PIC64GX) += pinctrl-pic64gx-gpio2.o
53
51
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
54
-
obj-$(CONFIG_PINCTRL_POLARFIRE_SOC) += pinctrl-mpfs-iomux0.o
55
52
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
56
53
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
57
54
obj-$(CONFIG_PINCTRL_RP1) += pinctrl-rp1.o
···
75
76
obj-$(CONFIG_X86) += intel/
76
77
obj-y += mediatek/
77
78
obj-$(CONFIG_PINCTRL_MESON) += meson/
79
+
obj-y += microchip/
78
80
obj-y += mvebu/
79
81
obj-y += nomadik/
80
82
obj-y += nuvoton/
+1
-3
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+1
-3
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
···
6
6
#include <linux/init.h>
7
7
#include <linux/io.h>
8
8
#include <linux/kernel.h>
9
-
#include <linux/mutex.h>
10
-
#include <linux/of.h>
9
+
#include <linux/mod_devicetable.h>
11
10
#include <linux/platform_device.h>
12
11
#include <linux/pinctrl/pinctrl.h>
13
12
#include <linux/pinctrl/pinmux.h>
14
13
#include <linux/pinctrl/pinconf.h>
15
14
#include <linux/pinctrl/pinconf-generic.h>
16
-
#include <linux/string.h>
17
15
#include <linux/types.h>
18
16
19
17
#include "../core.h"
+2
-5
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+2
-5
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
···
7
7
#include <linux/io.h>
8
8
#include <linux/kernel.h>
9
9
#include <linux/mfd/syscon.h>
10
-
#include <linux/mutex.h>
10
+
#include <linux/mod_devicetable.h>
11
11
#include <linux/of.h>
12
12
#include <linux/platform_device.h>
13
13
#include <linux/pinctrl/pinctrl.h>
14
14
#include <linux/pinctrl/pinmux.h>
15
15
#include <linux/pinctrl/pinconf.h>
16
16
#include <linux/pinctrl/pinconf-generic.h>
17
-
#include <linux/string.h>
18
17
#include <linux/types.h>
19
18
20
19
#include "../core.h"
···
2653
2654
np = of_parse_phandle(ctx->dev->of_node,
2654
2655
"aspeed,external-nodes", 1);
2655
2656
if (np) {
2656
-
if (!of_device_is_compatible(np->parent, "aspeed,ast2400-lpc-v2") &&
2657
-
!of_device_is_compatible(np->parent, "aspeed,ast2500-lpc-v2") &&
2658
-
!of_device_is_compatible(np->parent, "aspeed,ast2600-lpc-v2"))
2657
+
if (!of_device_is_compatible(np->parent, "aspeed,ast2500-lpc-v2"))
2659
2658
return ERR_PTR(-ENODEV);
2660
2659
2661
2660
map = syscon_node_to_regmap(np->parent);
+1
-4
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
+1
-4
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
···
4
4
#include <linux/init.h>
5
5
#include <linux/io.h>
6
6
#include <linux/kernel.h>
7
-
#include <linux/mfd/syscon.h>
8
-
#include <linux/mutex.h>
9
-
#include <linux/of.h>
7
+
#include <linux/mod_devicetable.h>
10
8
#include <linux/platform_device.h>
11
9
#include <linux/pinctrl/pinctrl.h>
12
10
#include <linux/pinctrl/pinmux.h>
13
-
#include <linux/string.h>
14
11
#include <linux/types.h>
15
12
16
13
#include "../core.h"
+21
-72
drivers/pinctrl/core.c
+21
-72
drivers/pinctrl/core.c
···
1383
1383
}
1384
1384
EXPORT_SYMBOL_GPL(pinctrl_select_state);
1385
1385
1386
-
static void devm_pinctrl_release(struct device *dev, void *res)
1386
+
static void devm_pinctrl_release(void *p)
1387
1387
{
1388
-
pinctrl_put(*(struct pinctrl **)res);
1388
+
pinctrl_put(p);
1389
1389
}
1390
1390
1391
1391
/**
···
1397
1397
*/
1398
1398
struct pinctrl *devm_pinctrl_get(struct device *dev)
1399
1399
{
1400
-
struct pinctrl **ptr, *p;
1401
-
1402
-
ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL);
1403
-
if (!ptr)
1404
-
return ERR_PTR(-ENOMEM);
1400
+
struct pinctrl *p;
1401
+
int ret;
1405
1402
1406
1403
p = pinctrl_get(dev);
1407
-
if (!IS_ERR(p)) {
1408
-
*ptr = p;
1409
-
devres_add(dev, ptr);
1410
-
} else {
1411
-
devres_free(ptr);
1412
-
}
1404
+
if (IS_ERR(p))
1405
+
return p;
1406
+
1407
+
ret = devm_add_action_or_reset(dev, devm_pinctrl_release, p);
1408
+
if (ret)
1409
+
return ERR_PTR(ret);
1413
1410
1414
1411
return p;
1415
1412
}
1416
1413
EXPORT_SYMBOL_GPL(devm_pinctrl_get);
1417
-
1418
-
static int devm_pinctrl_match(struct device *dev, void *res, void *data)
1419
-
{
1420
-
struct pinctrl **p = res;
1421
-
1422
-
return *p == data;
1423
-
}
1424
1414
1425
1415
/**
1426
1416
* devm_pinctrl_put() - Resource managed pinctrl_put()
···
1422
1432
*/
1423
1433
void devm_pinctrl_put(struct pinctrl *p)
1424
1434
{
1425
-
WARN_ON(devres_release(p->dev, devm_pinctrl_release,
1426
-
devm_pinctrl_match, p));
1435
+
devm_release_action(p->dev, devm_pinctrl_release, p);
1427
1436
}
1428
1437
EXPORT_SYMBOL_GPL(devm_pinctrl_put);
1429
1438
···
2187
2198
int error;
2188
2199
2189
2200
error = pinctrl_claim_hogs(pctldev);
2190
-
if (error) {
2191
-
dev_err(pctldev->dev, "could not claim hogs: %i\n", error);
2201
+
if (error)
2192
2202
return error;
2193
-
}
2194
2203
2195
2204
mutex_lock(&pinctrldev_list_mutex);
2196
2205
list_add_tail(&pctldev->node, &pinctrldev_list);
···
2303
2316
}
2304
2317
EXPORT_SYMBOL_GPL(pinctrl_unregister);
2305
2318
2306
-
static void devm_pinctrl_dev_release(struct device *dev, void *res)
2319
+
static void devm_pinctrl_dev_release(void *pctldev)
2307
2320
{
2308
-
struct pinctrl_dev *pctldev = *(struct pinctrl_dev **)res;
2309
-
2310
2321
pinctrl_unregister(pctldev);
2311
-
}
2312
-
2313
-
static int devm_pinctrl_dev_match(struct device *dev, void *res, void *data)
2314
-
{
2315
-
struct pctldev **r = res;
2316
-
2317
-
if (WARN_ON(!r || !*r))
2318
-
return 0;
2319
-
2320
-
return *r == data;
2321
2322
}
2322
2323
2323
2324
/**
···
2323
2348
const struct pinctrl_desc *pctldesc,
2324
2349
void *driver_data)
2325
2350
{
2326
-
struct pinctrl_dev **ptr, *pctldev;
2327
-
2328
-
ptr = devres_alloc(devm_pinctrl_dev_release, sizeof(*ptr), GFP_KERNEL);
2329
-
if (!ptr)
2330
-
return ERR_PTR(-ENOMEM);
2351
+
struct pinctrl_dev *pctldev;
2352
+
int ret;
2331
2353
2332
2354
pctldev = pinctrl_register(pctldesc, dev, driver_data);
2333
-
if (IS_ERR(pctldev)) {
2334
-
devres_free(ptr);
2355
+
if (IS_ERR(pctldev))
2335
2356
return pctldev;
2336
-
}
2337
2357
2338
-
*ptr = pctldev;
2339
-
devres_add(dev, ptr);
2358
+
ret = devm_add_action_or_reset(dev, devm_pinctrl_dev_release, pctldev);
2359
+
if (ret)
2360
+
return ERR_PTR(ret);
2340
2361
2341
2362
return pctldev;
2342
2363
}
···
2354
2383
void *driver_data,
2355
2384
struct pinctrl_dev **pctldev)
2356
2385
{
2357
-
struct pinctrl_dev **ptr;
2358
2386
int error;
2359
2387
2360
-
ptr = devres_alloc(devm_pinctrl_dev_release, sizeof(*ptr), GFP_KERNEL);
2361
-
if (!ptr)
2362
-
return -ENOMEM;
2363
-
2364
2388
error = pinctrl_register_and_init(pctldesc, dev, driver_data, pctldev);
2365
-
if (error) {
2366
-
devres_free(ptr);
2389
+
if (error)
2367
2390
return error;
2368
-
}
2369
2391
2370
-
*ptr = *pctldev;
2371
-
devres_add(dev, ptr);
2372
-
2373
-
return 0;
2392
+
return devm_add_action_or_reset(dev, devm_pinctrl_dev_release, *pctldev);
2374
2393
}
2375
2394
EXPORT_SYMBOL_GPL(devm_pinctrl_register_and_init);
2376
-
2377
-
/**
2378
-
* devm_pinctrl_unregister() - Resource managed version of pinctrl_unregister().
2379
-
* @dev: device for which resource was allocated
2380
-
* @pctldev: the pinctrl device to unregister.
2381
-
*/
2382
-
void devm_pinctrl_unregister(struct device *dev, struct pinctrl_dev *pctldev)
2383
-
{
2384
-
WARN_ON(devres_release(dev, devm_pinctrl_dev_release,
2385
-
devm_pinctrl_dev_match, pctldev));
2386
-
}
2387
-
EXPORT_SYMBOL_GPL(devm_pinctrl_unregister);
2388
2395
2389
2396
static int __init pinctrl_init(void)
2390
2397
{
+16
-4
drivers/pinctrl/freescale/pinctrl-imx-scmi.c
+16
-4
drivers/pinctrl/freescale/pinctrl-imx-scmi.c
···
38
38
};
39
39
40
40
/* SCMI pin control types, aligned with SCMI firmware */
41
-
#define IMX_SCMI_NUM_CFG 4
41
+
#define IMX_SCMI_NUM_CFG 5
42
42
#define IMX_SCMI_PIN_MUX 192
43
43
#define IMX_SCMI_PIN_CONFIG 193
44
44
#define IMX_SCMI_PIN_DAISY_ID 194
45
45
#define IMX_SCMI_PIN_DAISY_CFG 195
46
+
#define IMX_SCMI_PIN_EXT 196
46
47
47
48
#define IMX_SCMI_NO_PAD_CTL BIT(31)
48
49
#define IMX_SCMI_PAD_SION BIT(30)
···
51
50
52
51
#define IMX_SCMI_PIN_SIZE 24
53
52
54
-
#define IMX95_DAISY_OFF 0x408
55
53
#define IMX94_DAISY_OFF 0x608
54
+
#define IMX95_DAISY_OFF 0x408
55
+
#define IMX952_DAISY_OFF 0x460
56
56
57
57
static int pinctrl_scmi_imx_dt_node_to_map(struct pinctrl_dev *pctldev,
58
58
struct device_node *np,
···
75
73
daisy_off = IMX95_DAISY_OFF;
76
74
} else if (of_machine_is_compatible("fsl,imx94")) {
77
75
daisy_off = IMX94_DAISY_OFF;
76
+
} else if (of_machine_is_compatible("fsl,imx952")) {
77
+
daisy_off = IMX952_DAISY_OFF;
78
78
} else {
79
79
dev_err(pctldev->dev, "platform not support scmi pinctrl\n");
80
80
return -EINVAL;
···
122
118
123
119
pin_id = mux_reg / 4;
124
120
125
-
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_MUX, mux_val);
121
+
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_MUX, (mux_val & 0xFF));
122
+
123
+
if (mux_val & 0xFF00) {
124
+
int ext_val = (mux_val & 0xFF00) >> 8;
125
+
126
+
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_EXT, ext_val);
127
+
} else
128
+
ncfg--;
126
129
127
130
if (!conf_reg || (conf_val & IMX_SCMI_NO_PAD_CTL))
128
131
ncfg--;
···
302
291
}
303
292
304
293
static const char * const scmi_pinctrl_imx_allowlist[] = {
305
-
"fsl,imx95",
306
294
"fsl,imx94",
295
+
"fsl,imx95",
296
+
"fsl,imx952",
307
297
NULL
308
298
};
309
299
+16
-6
drivers/pinctrl/intel/Kconfig
+16
-6
drivers/pinctrl/intel/Kconfig
···
45
45
of Intel PCH pins and using them as GPIOs. Currently the following
46
46
Intel SoCs / platforms require this to be functional:
47
47
- Lunar Lake
48
+
- Nova Lake
48
49
- Panther Lake
49
50
50
51
config PINCTRL_ALDERLAKE
···
53
52
select PINCTRL_INTEL
54
53
help
55
54
This pinctrl driver provides an interface that allows configuring
56
-
of Intel Alder Lake PCH pins and using them as GPIOs.
55
+
PCH pins of the following platforms and using them as GPIOs:
56
+
- Alder Lake HX, N, and S
57
+
- Raptor Lake HX, E, and S
58
+
- Twin Lake
57
59
58
60
config PINCTRL_BROXTON
59
61
tristate "Intel Broxton pinctrl and GPIO driver"
···
140
136
select PINCTRL_INTEL
141
137
help
142
138
This pinctrl driver provides an interface that allows configuring
143
-
of Intel Meteor Lake pins and using them as GPIOs.
139
+
SoC pins of the following platforms and using them as GPIOs:
140
+
- Arrow Lake (all variants)
141
+
- Meteor Lake (all variants)
144
142
145
143
config PINCTRL_METEORPOINT
146
144
tristate "Intel Meteor Point pinctrl and GPIO driver"
147
145
select PINCTRL_INTEL
148
146
help
149
-
Meteor Point is the PCH of Intel Meteor Lake. This pinctrl driver
150
-
provides an interface that allows configuring of PCH pins and
151
-
using them as GPIOs.
147
+
This pinctrl driver provides an interface that allows configuring
148
+
PCH pins of the following platforms and using them as GPIOs:
149
+
- Arrow Lake HX and S
152
150
153
151
config PINCTRL_SUNRISEPOINT
154
152
tristate "Intel Sunrisepoint pinctrl and GPIO driver"
···
165
159
select PINCTRL_INTEL
166
160
help
167
161
This pinctrl driver provides an interface that allows configuring
168
-
of Intel Tiger Lake PCH pins and using them as GPIOs.
162
+
PCH pins of the following platforms and using them as GPIOs:
163
+
- Alder Lake H, P, PS, and U
164
+
- Raptor Lake H, P, PS, PX, and U
165
+
- Rocket Lake S
166
+
- Tiger Lake (all variants)
169
167
170
168
source "drivers/pinctrl/intel/Kconfig.tng"
171
169
endmenu
+1
-1
drivers/pinctrl/intel/pinctrl-alderlake.c
+1
-1
drivers/pinctrl/intel/pinctrl-alderlake.c
+25
-20
drivers/pinctrl/intel/pinctrl-baytrail.c
+25
-20
drivers/pinctrl/intel/pinctrl-baytrail.c
···
2
2
/*
3
3
* Pinctrl GPIO driver for Intel Baytrail
4
4
*
5
-
* Copyright (c) 2012-2013, Intel Corporation
5
+
* Copyright (C) 2012-2013 Intel Corporation
6
6
* Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7
7
*/
8
8
···
101
101
u32 val;
102
102
};
103
103
104
-
#define COMMUNITY(p, n, map) \
104
+
#define BYT_COMMUNITY(p, n, g, map) \
105
105
{ \
106
106
.pin_base = (p), \
107
107
.npins = (n), \
108
+
.gpps = (g), \
109
+
.ngpps = ARRAY_SIZE(g), \
108
110
.pad_map = (map),\
109
111
}
110
112
···
362
360
FUNCTION("gpio", byt_score_gpio_groups),
363
361
};
364
362
363
+
static const struct intel_padgroup byt_score_gpps[] = {
364
+
INTEL_GPP(0, 0, 31, 0),
365
+
INTEL_GPP(1, 32, 63, 32),
366
+
INTEL_GPP(2, 64, 95, 64),
367
+
INTEL_GPP(3, 96, 101, 96),
368
+
};
369
+
365
370
static const struct intel_community byt_score_communities[] = {
366
-
COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
371
+
BYT_COMMUNITY(0, 102, byt_score_gpps, byt_score_pins_map),
367
372
};
368
373
369
374
static const struct intel_pinctrl_soc_data byt_score_soc_data = {
···
492
483
FUNCTION("pmu_clk", byt_sus_pmu_clk_groups),
493
484
};
494
485
486
+
static const struct intel_padgroup byt_sus_gpps[] = {
487
+
INTEL_GPP(0, 0, 31, 0),
488
+
INTEL_GPP(1, 32, 43, 32),
489
+
};
490
+
495
491
static const struct intel_community byt_sus_communities[] = {
496
-
COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
492
+
BYT_COMMUNITY(0, 44, byt_sus_gpps, byt_sus_pins_map),
497
493
};
498
494
499
495
static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
···
550
536
3, 6, 10, 13, 2, 5, 9, 7,
551
537
};
552
538
539
+
static const struct intel_padgroup byt_ncore_gpps[] = {
540
+
INTEL_GPP(0, 0, 27, 0),
541
+
};
542
+
553
543
static const struct intel_community byt_ncore_communities[] = {
554
-
COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
544
+
BYT_COMMUNITY(0, 28, byt_ncore_gpps, byt_ncore_pins_map),
555
545
};
556
546
557
547
static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
···
1508
1490
return 0;
1509
1491
}
1510
1492
1511
-
static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
1512
-
{
1513
-
struct intel_pinctrl *vg = gpiochip_get_data(chip);
1514
-
struct device *dev = vg->dev;
1515
-
int ret;
1516
-
1517
-
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1518
-
if (ret)
1519
-
return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
1520
-
1521
-
return 0;
1522
-
}
1523
-
1524
1493
static int byt_gpio_probe(struct intel_pinctrl *vg)
1525
1494
{
1526
1495
struct platform_device *pdev = to_platform_device(vg->dev);
···
1520
1515
gc->label = dev_name(vg->dev);
1521
1516
gc->base = -1;
1522
1517
gc->can_sleep = false;
1523
-
gc->add_pin_ranges = byt_gpio_add_pin_ranges;
1518
+
gc->add_pin_ranges = intel_gpio_add_pin_ranges;
1524
1519
gc->parent = vg->dev;
1525
1520
gc->ngpio = vg->soc->npins;
1526
1521
···
1616
1611
1617
1612
vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1618
1613
if (IS_ERR(vg->pctldev))
1619
-
return dev_err_probe(dev, PTR_ERR(vg->pctldev), "failed to register pinctrl\n");
1614
+
return PTR_ERR(vg->pctldev);
1620
1615
1621
1616
ret = byt_gpio_probe(vg);
1622
1617
if (ret)
+1
-1
drivers/pinctrl/intel/pinctrl-broxton.c
+1
-1
drivers/pinctrl/intel/pinctrl-broxton.c
+1
-1
drivers/pinctrl/intel/pinctrl-cannonlake.c
+1
-1
drivers/pinctrl/intel/pinctrl-cannonlake.c
+1
-1
drivers/pinctrl/intel/pinctrl-cedarfork.c
+1
-1
drivers/pinctrl/intel/pinctrl-cedarfork.c
+2
-2
drivers/pinctrl/intel/pinctrl-cherryview.c
+2
-2
drivers/pinctrl/intel/pinctrl-cherryview.c
···
2
2
/*
3
3
* Cherryview/Braswell pinctrl driver
4
4
*
5
-
* Copyright (C) 2014, 2020 Intel Corporation
5
+
* Copyright (C) 2014-2020 Intel Corporation
6
6
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7
7
*
8
8
* This driver is based on the original Cherryview GPIO driver by
···
1644
1644
1645
1645
pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1646
1646
if (IS_ERR(pctrl->pctldev))
1647
-
return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), "failed to register pinctrl\n");
1647
+
return PTR_ERR(pctrl->pctldev);
1648
1648
1649
1649
ret = chv_gpio_probe(pctrl, irq);
1650
1650
if (ret)
+1
-1
drivers/pinctrl/intel/pinctrl-denverton.c
+1
-1
drivers/pinctrl/intel/pinctrl-denverton.c
+1
-1
drivers/pinctrl/intel/pinctrl-elkhartlake.c
+1
-1
drivers/pinctrl/intel/pinctrl-elkhartlake.c
+1
-1
drivers/pinctrl/intel/pinctrl-emmitsburg.c
+1
-1
drivers/pinctrl/intel/pinctrl-emmitsburg.c
+1
-1
drivers/pinctrl/intel/pinctrl-icelake.c
+1
-1
drivers/pinctrl/intel/pinctrl-icelake.c
+1
-1
drivers/pinctrl/intel/pinctrl-intel-platform.c
+1
-1
drivers/pinctrl/intel/pinctrl-intel-platform.c
+2
-2
drivers/pinctrl/intel/pinctrl-intel.c
+2
-2
drivers/pinctrl/intel/pinctrl-intel.c
···
2
2
/*
3
3
* Intel pinctrl/GPIO core driver.
4
4
*
5
-
* Copyright (C) 2015, Intel Corporation
5
+
* Copyright (C) 2015 Intel Corporation
6
6
* Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7
7
* Mika Westerberg <mika.westerberg@linux.intel.com>
8
8
*/
···
1673
1673
1674
1674
pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1675
1675
if (IS_ERR(pctrl->pctldev))
1676
-
return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), "failed to register pinctrl\n");
1676
+
return PTR_ERR(pctrl->pctldev);
1677
1677
1678
1678
ret = intel_gpio_probe(pctrl, irq);
1679
1679
if (ret)
+1
-1
drivers/pinctrl/intel/pinctrl-intel.h
+1
-1
drivers/pinctrl/intel/pinctrl-intel.h
+1
-1
drivers/pinctrl/intel/pinctrl-jasperlake.c
+1
-1
drivers/pinctrl/intel/pinctrl-jasperlake.c
+1
-1
drivers/pinctrl/intel/pinctrl-lakefield.c
+1
-1
drivers/pinctrl/intel/pinctrl-lakefield.c
+1
-1
drivers/pinctrl/intel/pinctrl-lewisburg.c
+1
-1
drivers/pinctrl/intel/pinctrl-lewisburg.c
+13
-18
drivers/pinctrl/intel/pinctrl-lynxpoint.c
+13
-18
drivers/pinctrl/intel/pinctrl-lynxpoint.c
···
2
2
/*
3
3
* Intel Lynxpoint PCH pinctrl/GPIO driver
4
4
*
5
-
* Copyright (c) 2012, 2019, Intel Corporation
5
+
* Copyright (C) 2012-2019 Intel Corporation
6
6
* Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7
7
* Andy Shevchenko <andriy.shevchenko@linux.intel.com>
8
8
*/
···
29
29
30
30
#include "pinctrl-intel.h"
31
31
32
-
#define COMMUNITY(p, n) \
32
+
#define LPTLP_COMMUNITY(p, n, g) \
33
33
{ \
34
34
.pin_base = (p), \
35
35
.npins = (n), \
36
+
.gpps = (g), \
37
+
.ngpps = ARRAY_SIZE(g), \
36
38
}
37
39
38
40
static const struct pinctrl_pin_desc lptlp_pins[] = {
···
135
133
PINCTRL_PIN(94, "GP94_UART0_CTSB"),
136
134
};
137
135
136
+
static const struct intel_padgroup lptlp_gpps[] = {
137
+
INTEL_GPP(0, 0, 31, 0),
138
+
INTEL_GPP(1, 32, 63, 32),
139
+
INTEL_GPP(2, 64, 94, 64),
140
+
};
141
+
138
142
static const struct intel_community lptlp_communities[] = {
139
-
COMMUNITY(0, 95),
143
+
LPTLP_COMMUNITY(0, 95, lptlp_gpps),
140
144
};
141
145
142
146
static const struct intel_pinctrl_soc_data lptlp_soc_data = {
···
700
692
return 0;
701
693
}
702
694
703
-
static int lp_gpio_add_pin_ranges(struct gpio_chip *chip)
704
-
{
705
-
struct intel_pinctrl *lg = gpiochip_get_data(chip);
706
-
struct device *dev = lg->dev;
707
-
int ret;
708
-
709
-
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins);
710
-
if (ret)
711
-
return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
712
-
713
-
return 0;
714
-
}
715
-
716
695
static int lp_gpio_probe(struct platform_device *pdev)
717
696
{
718
697
const struct intel_pinctrl_soc_data *soc;
···
735
740
736
741
lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg);
737
742
if (IS_ERR(lg->pctldev))
738
-
return dev_err_probe(dev, PTR_ERR(lg->pctldev), "failed to register pinctrl\n");
743
+
return PTR_ERR(lg->pctldev);
739
744
740
745
platform_set_drvdata(pdev, lg);
741
746
···
772
777
gc->base = -1;
773
778
gc->ngpio = LP_NUM_GPIO;
774
779
gc->can_sleep = false;
775
-
gc->add_pin_ranges = lp_gpio_add_pin_ranges;
780
+
gc->add_pin_ranges = intel_gpio_add_pin_ranges;
776
781
gc->parent = dev;
777
782
778
783
/* set up interrupts */
+1
-1
drivers/pinctrl/intel/pinctrl-merrifield.c
+1
-1
drivers/pinctrl/intel/pinctrl-merrifield.c
+1
-1
drivers/pinctrl/intel/pinctrl-meteorlake.c
+1
-1
drivers/pinctrl/intel/pinctrl-meteorlake.c
+1
-1
drivers/pinctrl/intel/pinctrl-meteorpoint.c
+1
-1
drivers/pinctrl/intel/pinctrl-meteorpoint.c
+1
-1
drivers/pinctrl/intel/pinctrl-moorefield.c
+1
-1
drivers/pinctrl/intel/pinctrl-moorefield.c
+1
-1
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
+1
-1
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
+8
-15
drivers/pinctrl/intel/pinctrl-tangier.c
+8
-15
drivers/pinctrl/intel/pinctrl-tangier.c
···
2
2
/*
3
3
* Intel Tangier pinctrl driver
4
4
*
5
-
* Copyright (C) 2016, 2023 Intel Corporation
5
+
* Copyright (C) 2016-2023 Intel Corporation
6
6
*
7
7
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
8
8
* Raag Jadav <raag.jadav@intel.com>
···
518
518
.owner = THIS_MODULE,
519
519
};
520
520
521
-
static int tng_pinctrl_probe(struct platform_device *pdev,
522
-
const struct tng_pinctrl *data)
521
+
int devm_tng_pinctrl_probe(struct platform_device *pdev)
523
522
{
524
523
struct device *dev = &pdev->dev;
524
+
const struct tng_pinctrl *data;
525
525
struct tng_family *families;
526
526
struct tng_pinctrl *tp;
527
527
void __iomem *regs;
528
528
unsigned int i;
529
+
530
+
data = device_get_match_data(dev);
531
+
if (!data)
532
+
return -ENODATA;
529
533
530
534
tp = devm_kmemdup(dev, data, sizeof(*data), GFP_KERNEL);
531
535
if (!tp)
···
566
562
567
563
tp->pctldev = devm_pinctrl_register(dev, &tp->pctldesc, tp);
568
564
if (IS_ERR(tp->pctldev))
569
-
return dev_err_probe(dev, PTR_ERR(tp->pctldev), "failed to register pinctrl\n");
565
+
return PTR_ERR(tp->pctldev);
570
566
571
567
return 0;
572
-
}
573
-
574
-
int devm_tng_pinctrl_probe(struct platform_device *pdev)
575
-
{
576
-
const struct tng_pinctrl *data;
577
-
578
-
data = device_get_match_data(&pdev->dev);
579
-
if (!data)
580
-
return -ENODATA;
581
-
582
-
return tng_pinctrl_probe(pdev, data);
583
568
}
584
569
EXPORT_SYMBOL_NS_GPL(devm_tng_pinctrl_probe, "PINCTRL_TANGIER");
585
570
+1
-1
drivers/pinctrl/intel/pinctrl-tangier.h
+1
-1
drivers/pinctrl/intel/pinctrl-tangier.h
+1
-1
drivers/pinctrl/intel/pinctrl-tigerlake.c
+1
-1
drivers/pinctrl/intel/pinctrl-tigerlake.c
+17
-12
drivers/pinctrl/mediatek/mtk-eint.c
+17
-12
drivers/pinctrl/mediatek/mtk-eint.c
···
544
544
}
545
545
}
546
546
547
-
eint->pin_list = devm_kmalloc(eint->dev, eint->nbase * sizeof(u16 *), GFP_KERNEL);
547
+
eint->pin_list = devm_kcalloc(eint->dev, eint->nbase,
548
+
sizeof(*eint->pin_list), GFP_KERNEL);
548
549
if (!eint->pin_list)
549
550
goto err_pin_list;
550
551
551
-
eint->wake_mask = devm_kmalloc(eint->dev, eint->nbase * sizeof(u32 *), GFP_KERNEL);
552
+
eint->wake_mask = devm_kcalloc(eint->dev, eint->nbase,
553
+
sizeof(*eint->wake_mask), GFP_KERNEL);
552
554
if (!eint->wake_mask)
553
555
goto err_wake_mask;
554
556
555
-
eint->cur_mask = devm_kmalloc(eint->dev, eint->nbase * sizeof(u32 *), GFP_KERNEL);
557
+
eint->cur_mask = devm_kcalloc(eint->dev, eint->nbase,
558
+
sizeof(*eint->cur_mask), GFP_KERNEL);
556
559
if (!eint->cur_mask)
557
560
goto err_cur_mask;
558
561
559
562
for (i = 0; i < eint->nbase; i++) {
560
-
eint->pin_list[i] = devm_kzalloc(eint->dev, eint->base_pin_num[i] * sizeof(u16),
563
+
eint->pin_list[i] = devm_kzalloc(eint->dev,
564
+
eint->base_pin_num[i] * sizeof(**eint->pin_list),
561
565
GFP_KERNEL);
562
566
port = DIV_ROUND_UP(eint->base_pin_num[i], 32);
563
-
eint->wake_mask[i] = devm_kzalloc(eint->dev, port * sizeof(u32), GFP_KERNEL);
564
-
eint->cur_mask[i] = devm_kzalloc(eint->dev, port * sizeof(u32), GFP_KERNEL);
567
+
eint->wake_mask[i] = devm_kzalloc(eint->dev,
568
+
port * sizeof(**eint->wake_mask),
569
+
GFP_KERNEL);
570
+
eint->cur_mask[i] = devm_kzalloc(eint->dev,
571
+
port * sizeof(**eint->cur_mask),
572
+
GFP_KERNEL);
565
573
if (!eint->pin_list[i] || !eint->wake_mask[i] || !eint->cur_mask[i])
566
574
goto err_eint;
567
575
}
···
605
597
606
598
err_eint:
607
599
for (i = 0; i < eint->nbase; i++) {
608
-
if (eint->cur_mask[i])
609
-
devm_kfree(eint->dev, eint->cur_mask[i]);
610
-
if (eint->wake_mask[i])
611
-
devm_kfree(eint->dev, eint->wake_mask[i]);
612
-
if (eint->pin_list[i])
613
-
devm_kfree(eint->dev, eint->pin_list[i]);
600
+
devm_kfree(eint->dev, eint->cur_mask[i]);
601
+
devm_kfree(eint->dev, eint->wake_mask[i]);
602
+
devm_kfree(eint->dev, eint->pin_list[i]);
614
603
}
615
604
devm_kfree(eint->dev, eint->cur_mask);
616
605
err_cur_mask:
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7981.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7981.c
···
1019
1019
.nfuncs = ARRAY_SIZE(mt7981_functions),
1020
1020
.eint_hw = &mt7981_eint_hw,
1021
1021
.gpio_m = 0,
1022
-
.ies_present = false,
1022
+
.ies_present = true,
1023
1023
.base_names = mt7981_pinctrl_register_base_names,
1024
1024
.nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
1025
1025
.bias_disable_set = mtk_pinconf_bias_disable_set,
+2
-2
drivers/pinctrl/mediatek/pinctrl-mt7986.c
+2
-2
drivers/pinctrl/mediatek/pinctrl-mt7986.c
···
919
919
.nfuncs = ARRAY_SIZE(mt7986_functions),
920
920
.eint_hw = &mt7986a_eint_hw,
921
921
.gpio_m = 0,
922
-
.ies_present = false,
922
+
.ies_present = true,
923
923
.base_names = mt7986_pinctrl_register_base_names,
924
924
.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
925
925
.bias_disable_set = mtk_pinconf_bias_disable_set,
···
945
945
.nfuncs = ARRAY_SIZE(mt7986_functions),
946
946
.eint_hw = &mt7986b_eint_hw,
947
947
.gpio_m = 0,
948
-
.ies_present = false,
948
+
.ies_present = true,
949
949
.base_names = mt7986_pinctrl_register_base_names,
950
950
.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
951
951
.bias_disable_set = mtk_pinconf_bias_disable_set,
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7988.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7988.c
···
1505
1505
.nfuncs = ARRAY_SIZE(mt7988_functions),
1506
1506
.eint_hw = &mt7988_eint_hw,
1507
1507
.gpio_m = 0,
1508
-
.ies_present = false,
1508
+
.ies_present = true,
1509
1509
.base_names = mt7988_pinctrl_register_base_names,
1510
1510
.nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
1511
1511
.bias_disable_set = mtk_pinconf_bias_disable_set,
-1
drivers/pinctrl/mediatek/pinctrl-mt8365.c
-1
drivers/pinctrl/mediatek/pinctrl-mt8365.c
-1
drivers/pinctrl/mediatek/pinctrl-mtk-common.h
-1
drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+11
-11
drivers/pinctrl/meson/Kconfig
+11
-11
drivers/pinctrl/meson/Kconfig
···
15
15
16
16
config PINCTRL_MESON8
17
17
bool "Meson 8 SoC pinctrl driver"
18
-
depends on ARM
18
+
depends on ARM || COMPILE_TEST
19
19
select PINCTRL_MESON8_PMX
20
20
default ARCH_MESON
21
21
22
22
config PINCTRL_MESON8B
23
23
bool "Meson 8b SoC pinctrl driver"
24
-
depends on ARM
24
+
depends on ARM || COMPILE_TEST
25
25
select PINCTRL_MESON8_PMX
26
26
default ARCH_MESON
27
27
28
28
config PINCTRL_MESON_GXBB
29
29
tristate "Meson gxbb SoC pinctrl driver"
30
-
depends on ARM64
30
+
depends on ARM64 || COMPILE_TEST
31
31
select PINCTRL_MESON8_PMX
32
32
default ARCH_MESON
33
33
34
34
config PINCTRL_MESON_GXL
35
35
tristate "Meson gxl SoC pinctrl driver"
36
-
depends on ARM64
36
+
depends on ARM64 || COMPILE_TEST
37
37
select PINCTRL_MESON8_PMX
38
38
default ARCH_MESON
39
39
···
42
42
43
43
config PINCTRL_MESON_AXG
44
44
tristate "Meson axg Soc pinctrl driver"
45
-
depends on ARM64
45
+
depends on ARM64 || COMPILE_TEST
46
46
select PINCTRL_MESON_AXG_PMX
47
47
default ARCH_MESON
48
48
···
51
51
52
52
config PINCTRL_MESON_G12A
53
53
tristate "Meson g12a Soc pinctrl driver"
54
-
depends on ARM64
54
+
depends on ARM64 || COMPILE_TEST
55
55
select PINCTRL_MESON_AXG_PMX
56
56
default ARCH_MESON
57
57
58
58
config PINCTRL_MESON_A1
59
59
tristate "Meson a1 Soc pinctrl driver"
60
-
depends on ARM64
60
+
depends on ARM64 || COMPILE_TEST
61
61
select PINCTRL_MESON_AXG_PMX
62
62
default ARCH_MESON
63
63
64
64
config PINCTRL_MESON_S4
65
65
tristate "Meson s4 Soc pinctrl driver"
66
-
depends on ARM64
66
+
depends on ARM64 || COMPILE_TEST
67
67
select PINCTRL_MESON_AXG_PMX
68
68
default ARCH_MESON
69
69
70
70
config PINCTRL_AMLOGIC_A4
71
71
bool "AMLOGIC pincontrol"
72
-
depends on ARM64
72
+
depends on ARM64 || COMPILE_TEST
73
73
default ARCH_MESON
74
74
help
75
75
This is the driver for the pin controller found on Amlogic SoCs.
···
80
80
81
81
config PINCTRL_AMLOGIC_C3
82
82
tristate "Amlogic C3 SoC pinctrl driver"
83
-
depends on ARM64
83
+
depends on ARM64 || COMPILE_TEST
84
84
select PINCTRL_MESON_AXG_PMX
85
85
default ARCH_MESON
86
86
87
87
config PINCTRL_AMLOGIC_T7
88
88
tristate "Amlogic T7 SoC pinctrl driver"
89
-
depends on ARM64
89
+
depends on ARM64 || COMPILE_TEST
90
90
select PINCTRL_MESON_AXG_PMX
91
91
default ARCH_MESON
92
92
+77
-6
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
+77
-6
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
···
24
24
#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
25
25
26
26
#include "../core.h"
27
+
#include "../pinctrl-utils.h"
27
28
#include "../pinconf.h"
28
29
29
30
#define gpio_chip_to_bank(chip) \
···
673
672
seq_printf(s, " %s", dev_name(pcdev->dev));
674
673
}
675
674
675
+
static int aml_dt_node_to_map_pinmux(struct pinctrl_dev *pctldev,
676
+
struct device_node *np,
677
+
struct pinctrl_map **map,
678
+
unsigned int *num_maps)
679
+
{
680
+
struct device *dev = pctldev->dev;
681
+
struct device_node *pnode;
682
+
unsigned long *configs = NULL;
683
+
unsigned int num_configs = 0;
684
+
struct property *prop;
685
+
unsigned int reserved_maps;
686
+
int reserve;
687
+
int ret;
688
+
689
+
prop = of_find_property(np, "pinmux", NULL);
690
+
if (!prop) {
691
+
dev_info(dev, "Missing pinmux property\n");
692
+
return -ENOENT;
693
+
}
694
+
695
+
pnode = of_get_parent(np);
696
+
if (!pnode) {
697
+
dev_info(dev, "Missing function node\n");
698
+
return -EINVAL;
699
+
}
700
+
701
+
reserved_maps = 0;
702
+
*map = NULL;
703
+
*num_maps = 0;
704
+
705
+
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
706
+
&num_configs);
707
+
if (ret < 0) {
708
+
dev_err(dev, "%pOF: could not parse node property\n", np);
709
+
return ret;
710
+
}
711
+
712
+
reserve = 1;
713
+
if (num_configs)
714
+
reserve++;
715
+
716
+
ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps,
717
+
num_maps, reserve);
718
+
if (ret < 0)
719
+
goto exit;
720
+
721
+
ret = pinctrl_utils_add_map_mux(pctldev, map,
722
+
&reserved_maps, num_maps, np->name,
723
+
pnode->name);
724
+
if (ret < 0)
725
+
goto exit;
726
+
727
+
if (num_configs) {
728
+
ret = pinctrl_utils_add_map_configs(pctldev, map, &reserved_maps,
729
+
num_maps, np->name, configs,
730
+
num_configs, PIN_MAP_TYPE_CONFIGS_GROUP);
731
+
if (ret < 0)
732
+
goto exit;
733
+
}
734
+
735
+
exit:
736
+
kfree(configs);
737
+
if (ret)
738
+
pinctrl_utils_free_map(pctldev, *map, *num_maps);
739
+
740
+
return ret;
741
+
}
742
+
676
743
static const struct pinctrl_ops aml_pctrl_ops = {
677
744
.get_groups_count = aml_get_groups_count,
678
745
.get_group_name = aml_get_group_name,
679
746
.get_group_pins = aml_get_group_pins,
680
-
.dt_node_to_map = pinconf_generic_dt_node_to_map_pinmux,
747
+
.dt_node_to_map = aml_dt_node_to_map_pinmux,
681
748
.dt_free_map = pinconf_generic_dt_free_map,
682
749
.pin_dbg_show = aml_pin_dbg_show,
683
750
};
···
794
725
if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3,
795
726
0, &of_args))
796
727
return 0;
797
-
else
798
-
return of_args.args[2];
728
+
729
+
of_node_put(of_args.np);
730
+
return of_args.args[2];
799
731
}
800
732
801
733
static int aml_bank_number(struct device_node *np)
···
806
736
if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3,
807
737
0, &of_args))
808
738
return -EINVAL;
809
-
else
810
-
return of_args.args[1] >> 8;
739
+
740
+
of_node_put(of_args.np);
741
+
return of_args.args[1] >> 8;
811
742
}
812
743
813
744
static unsigned int aml_count_pins(struct device_node *np)
···
964
893
.direction_input = aml_gpio_direction_input,
965
894
.direction_output = aml_gpio_direction_output,
966
895
.get_direction = aml_gpio_get_direction,
967
-
.can_sleep = false,
896
+
.can_sleep = true,
968
897
};
969
898
970
899
static void init_bank_register_bit(struct aml_pinctrl *info,
+18
drivers/pinctrl/microchip/Kconfig
+18
drivers/pinctrl/microchip/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
config PINCTRL_PIC64GX
4
+
bool "pic64gx gpio2 pinctrl driver"
5
+
depends on ARCH_MICROCHIP || COMPILE_TEST
6
+
depends on OF
7
+
select GENERIC_PINCONF
8
+
select REGMAP_MMIO
9
+
help
10
+
This selects the pinctrl driver for gpio2 on pic64gx.
11
+
12
+
config PINCTRL_POLARFIRE_SOC
13
+
bool "Polarfire SoC pinctrl drivers"
14
+
depends on ARCH_MICROCHIP || COMPILE_TEST
15
+
depends on OF
16
+
select GENERIC_PINCTRL
17
+
help
18
+
This selects the pinctrl drivers for Microchip Polarfire SoC.
+5
drivers/pinctrl/microchip/Makefile
+5
drivers/pinctrl/microchip/Makefile
+737
drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
+737
drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
3
+
#include <linux/bitfield.h>
4
+
#include <linux/module.h>
5
+
#include <linux/mfd/syscon.h>
6
+
#include <linux/mod_devicetable.h>
7
+
#include <linux/of.h>
8
+
#include <linux/platform_device.h>
9
+
#include <linux/regmap.h>
10
+
#include <linux/seq_file.h>
11
+
12
+
#include <linux/pinctrl/pinconf-generic.h>
13
+
#include <linux/pinctrl/pinconf.h>
14
+
#include <linux/pinctrl/pinctrl.h>
15
+
#include <linux/pinctrl/pinmux.h>
16
+
17
+
#include "../core.h"
18
+
#include "../pinctrl-utils.h"
19
+
#include "../pinconf.h"
20
+
#include "../pinmux.h"
21
+
22
+
#define MPFS_PINCTRL_PAD_MUX_MASK GENMASK(3, 0)
23
+
24
+
#define MPFS_PINCTRL_IOCFG_MASK GENMASK(14, 0)
25
+
#define MPFS_PINCTRL_IBUFMD_MASK GENMASK(2, 0)
26
+
#define MPFS_PINCTRL_DRV_MASK GENMASK(6, 3)
27
+
#define MPFS_PINCTRL_CLAMP BIT(7)
28
+
#define MPFS_PINCTRL_ENHYST BIT(8)
29
+
#define MPFS_PINCTRL_LOCKDN BIT(9)
30
+
#define MPFS_PINCTRL_WPD BIT(10)
31
+
#define MPFS_PINCTRL_WPU BIT(11)
32
+
#define MPFS_PINCTRL_PULL_MASK GENMASK(11, 10)
33
+
#define MPFS_PINCTRL_LP_PERSIST_EN BIT(12)
34
+
#define MPFS_PINCTRL_LP_BYPASS_EN BIT(13)
35
+
36
+
#define MPFS_PINCTRL_MSSIO_BANK2_CFG_CR 0x1c4
37
+
#define MPFS_PINCTRL_MSSIO_BANK4_CFG_CR 0x1c8
38
+
#define MPFS_PINCTRL_BANK_VOLTAGE_MASK GENMASK(19, 16)
39
+
40
+
#define MPFS_PINCTRL_IOCFG01_REG 0x234
41
+
42
+
#define MPFS_PINCTRL_INTER_BANK_GAP 0x4
43
+
44
+
#define MPFS_PINCTRL_BANK2_START 14
45
+
46
+
#define MPFS_PINCTRL_LOCKDOWN (PIN_CONFIG_END + 1)
47
+
#define MPFS_PINCTRL_CLAMP_DIODE (PIN_CONFIG_END + 2)
48
+
#define MPFS_PINCTRL_IBUFMD (PIN_CONFIG_END + 3)
49
+
50
+
struct mpfs_pinctrl_mux_config {
51
+
u8 pin;
52
+
u8 function;
53
+
};
54
+
55
+
struct mpfs_pinctrl {
56
+
struct pinctrl_dev *pctrl;
57
+
struct device *dev;
58
+
struct regmap *regmap;
59
+
struct regmap *sysreg_regmap;
60
+
struct mutex mutex;
61
+
struct pinctrl_desc desc;
62
+
};
63
+
64
+
struct mpfs_pinctrl_drive_strength {
65
+
u8 ma;
66
+
u8 val;
67
+
};
68
+
69
+
struct mpfs_pinctrl_bank_voltage {
70
+
u32 uv;
71
+
u8 val;
72
+
};
73
+
74
+
static struct mpfs_pinctrl_drive_strength mpfs_pinctrl_drive_strengths[8] = {
75
+
{ .ma = 2, .val = 2 },
76
+
{ .ma = 4, .val = 3 },
77
+
{ .ma = 6, .val = 4 },
78
+
{ .ma = 8, .val = 5 },
79
+
{ .ma = 10, .val = 6 },
80
+
{ .ma = 12, .val = 7 },
81
+
{ .ma = 16, .val = 10 },
82
+
{ .ma = 20, .val = 12 },
83
+
};
84
+
static struct mpfs_pinctrl_bank_voltage mpfs_pinctrl_bank_voltages[8] = {
85
+
{ .uv = 1200000, .val = 0 },
86
+
{ .uv = 1500000, .val = 2 },
87
+
{ .uv = 1800000, .val = 4 },
88
+
{ .uv = 2500000, .val = 6 },
89
+
{ .uv = 3300000, .val = 8 },
90
+
{ .uv = 0, .val = 0x3f }, // pin unused
91
+
};
92
+
93
+
static int mpfs_pinctrl_get_drive_strength_ma(u32 drive_strength)
94
+
{
95
+
size_t num = ARRAY_SIZE(mpfs_pinctrl_drive_strengths);
96
+
97
+
for (int i = 0; i < num; i++)
98
+
if (drive_strength == mpfs_pinctrl_drive_strengths[i].val)
99
+
return mpfs_pinctrl_drive_strengths[i].ma;
100
+
101
+
return -EINVAL;
102
+
}
103
+
104
+
static int mpfs_pinctrl_get_drive_strength_val(u32 drive_strength_ma)
105
+
{
106
+
size_t num = ARRAY_SIZE(mpfs_pinctrl_drive_strengths);
107
+
108
+
if (!drive_strength_ma)
109
+
return -EINVAL;
110
+
111
+
for (int i = 0; i < num; i++)
112
+
if (drive_strength_ma <= mpfs_pinctrl_drive_strengths[i].ma)
113
+
return mpfs_pinctrl_drive_strengths[i].val;
114
+
115
+
return mpfs_pinctrl_drive_strengths[num - 1].val;
116
+
}
117
+
118
+
static int mpfs_pinctrl_get_bank_voltage_uv(u32 bank_voltage)
119
+
{
120
+
size_t num = ARRAY_SIZE(mpfs_pinctrl_bank_voltages);
121
+
122
+
for (int i = 0; i < num; i++)
123
+
if (bank_voltage == mpfs_pinctrl_bank_voltages[i].val)
124
+
return mpfs_pinctrl_bank_voltages[i].uv;
125
+
126
+
return -EINVAL;
127
+
}
128
+
129
+
static int mpfs_pinctrl_get_bank_voltage_val(u32 bank_voltage_uv)
130
+
{
131
+
size_t num = ARRAY_SIZE(mpfs_pinctrl_bank_voltages);
132
+
133
+
for (int i = 0; i < num; i++)
134
+
if (bank_voltage_uv <= mpfs_pinctrl_bank_voltages[i].uv)
135
+
return mpfs_pinctrl_bank_voltages[i].val;
136
+
137
+
return -EINVAL;
138
+
}
139
+
140
+
static u32 mpfs_pinctrl_pin_to_bank_voltage(struct mpfs_pinctrl *pctrl, unsigned int pin)
141
+
{
142
+
u32 bank_voltage, val;
143
+
144
+
if (pin < MPFS_PINCTRL_BANK2_START)
145
+
regmap_read(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK4_CFG_CR, &val);
146
+
else
147
+
regmap_read(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK2_CFG_CR, &val);
148
+
149
+
bank_voltage = FIELD_GET(MPFS_PINCTRL_BANK_VOLTAGE_MASK, val);
150
+
151
+
return mpfs_pinctrl_get_bank_voltage_uv(bank_voltage);
152
+
}
153
+
154
+
static void mpfs_pinctrl_set_bank_voltage(struct mpfs_pinctrl *pctrl, unsigned int pin,
155
+
u32 bank_voltage)
156
+
{
157
+
u32 val = FIELD_PREP(MPFS_PINCTRL_BANK_VOLTAGE_MASK, bank_voltage);
158
+
159
+
if (pin < MPFS_PINCTRL_BANK2_START)
160
+
regmap_assign_bits(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK4_CFG_CR,
161
+
MPFS_PINCTRL_BANK_VOLTAGE_MASK, val);
162
+
else
163
+
regmap_assign_bits(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK2_CFG_CR,
164
+
MPFS_PINCTRL_BANK_VOLTAGE_MASK, val);
165
+
}
166
+
167
+
static char *mpfs_pinctrl_function_names[] = {
168
+
"sd",
169
+
"emmc",
170
+
"qspi",
171
+
"spi",
172
+
"usb",
173
+
"uart",
174
+
"i2c",
175
+
"can",
176
+
"mdio",
177
+
"misc",
178
+
"reserved",
179
+
"gpio",
180
+
"fabric test",
181
+
"tied-low",
182
+
"tied-high",
183
+
"tristate"
184
+
};
185
+
186
+
static int mpfs_pinctrl_function_map(const char *function)
187
+
{
188
+
size_t num = ARRAY_SIZE(mpfs_pinctrl_function_names);
189
+
190
+
for (int i = 0; i < num; i++)
191
+
if (!strcmp(function, mpfs_pinctrl_function_names[i]))
192
+
return i;
193
+
194
+
return -EINVAL;
195
+
}
196
+
197
+
static const struct pinconf_generic_params mpfs_pinctrl_custom_bindings[] = {
198
+
{ "microchip,clamp-diode", MPFS_PINCTRL_CLAMP_DIODE, 1 },
199
+
{ "microchip,ibufmd", MPFS_PINCTRL_IBUFMD, 0x0 },
200
+
};
201
+
202
+
static int mpfs_pinctrl_pin_to_iomux_offset(unsigned int pin)
203
+
{
204
+
int offset;
205
+
206
+
switch (pin) {
207
+
case 0 ... 7:
208
+
offset = pin * 4;
209
+
break;
210
+
case 8 ... 13:
211
+
offset = (pin - 8) * 4;
212
+
break;
213
+
case 14 ... 21:
214
+
offset = (pin - 14) * 4;
215
+
break;
216
+
case 22 ... 29:
217
+
offset = (pin - 22) * 4;
218
+
break;
219
+
case 30 ... 37:
220
+
offset = (pin - 30) * 4;
221
+
break;
222
+
default:
223
+
offset = -EINVAL;
224
+
}
225
+
226
+
return offset;
227
+
}
228
+
229
+
static int mpfs_pinctrl_pin_to_iomux_reg(unsigned int pin)
230
+
{
231
+
int reg;
232
+
233
+
switch (pin) {
234
+
case 0 ... 7:
235
+
reg = 0x204;
236
+
break;
237
+
case 8 ... 13:
238
+
reg = 0x208;
239
+
break;
240
+
case 14 ... 21:
241
+
reg = 0x20c;
242
+
break;
243
+
case 22 ... 29:
244
+
reg = 0x210;
245
+
break;
246
+
case 30 ... 37:
247
+
reg = 0x214;
248
+
break;
249
+
default:
250
+
reg = -EINVAL;
251
+
}
252
+
253
+
return reg;
254
+
}
255
+
256
+
static int mpfs_pinctrl_pin_to_iocfg_reg(unsigned int pin)
257
+
{
258
+
u32 reg = MPFS_PINCTRL_IOCFG01_REG;
259
+
260
+
if (pin >= MPFS_PINCTRL_BANK2_START)
261
+
reg += MPFS_PINCTRL_INTER_BANK_GAP;
262
+
263
+
// 2 pins per 32-bit register
264
+
reg += (pin / 2) * 0x4;
265
+
266
+
return reg;
267
+
}
268
+
269
+
static int mpfs_pinctrl_pin_to_iocfg_offset(unsigned int pin)
270
+
{
271
+
return 16 * (pin % 2);
272
+
}
273
+
274
+
static void mpfs_pinctrl_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq,
275
+
unsigned int pin)
276
+
{
277
+
struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
278
+
u32 func;
279
+
int reg, offset;
280
+
281
+
reg = mpfs_pinctrl_pin_to_iomux_reg(pin);
282
+
offset = mpfs_pinctrl_pin_to_iomux_offset(pin);
283
+
284
+
seq_printf(seq, "reg: %x, offset: %u ", reg, offset);
285
+
seq_printf(seq, "pin: %u ", pin);
286
+
287
+
if (reg < 0 || offset < 0)
288
+
return;
289
+
290
+
regmap_read(pctrl->regmap, reg, &func);
291
+
func = (func >> offset) & MPFS_PINCTRL_PAD_MUX_MASK;
292
+
seq_printf(seq, "func: %s (%x)\n", mpfs_pinctrl_function_names[func], func);
293
+
}
294
+
295
+
static const struct pinctrl_ops mpfs_pinctrl_ops = {
296
+
.get_groups_count = pinctrl_generic_get_group_count,
297
+
.get_group_name = pinctrl_generic_get_group_name,
298
+
.get_group_pins = pinctrl_generic_get_group_pins,
299
+
.pin_dbg_show = mpfs_pinctrl_dbg_show,
300
+
.dt_node_to_map = pinctrl_generic_pins_function_dt_node_to_map,
301
+
.dt_free_map = pinctrl_utils_free_map,
302
+
};
303
+
304
+
static int mpfs_pinctrl_set_pin_func(struct mpfs_pinctrl *pctrl, u8 pin, u8 function)
305
+
{
306
+
struct device *dev = pctrl->dev;
307
+
int reg, offset;
308
+
u32 func, mask;
309
+
310
+
reg = mpfs_pinctrl_pin_to_iomux_reg(pin);
311
+
offset = mpfs_pinctrl_pin_to_iomux_offset(pin);
312
+
313
+
func = function << offset;
314
+
mask = MPFS_PINCTRL_PAD_MUX_MASK << offset;
315
+
316
+
dev_dbg(dev, "Setting pin %u. reg: %x offset %u func %x\n", pin, reg, offset, func);
317
+
318
+
if (reg < 0 || offset < 0)
319
+
return -EINVAL;
320
+
321
+
regmap_update_bits(pctrl->regmap, reg, mask, func);
322
+
323
+
return 0;
324
+
}
325
+
326
+
static int mpfs_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, unsigned int fsel,
327
+
unsigned int gsel)
328
+
{
329
+
struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
330
+
const struct group_desc *group;
331
+
const char **functions;
332
+
333
+
group = pinctrl_generic_get_group(pctrl_dev, gsel);
334
+
if (!group)
335
+
return -EINVAL;
336
+
337
+
functions = group->data;
338
+
339
+
for (int i = 0; i < group->grp.npins; i++) {
340
+
int function;
341
+
342
+
function = mpfs_pinctrl_function_map(functions[i]);
343
+
if (function < 0) {
344
+
dev_err(pctrl->dev, "invalid function %s\n", functions[i]);
345
+
return function;
346
+
}
347
+
348
+
mpfs_pinctrl_set_pin_func(pctrl, group->grp.pins[i], function);
349
+
}
350
+
351
+
return 0;
352
+
}
353
+
354
+
static const struct pinmux_ops mpfs_pinctrl_pinmux_ops = {
355
+
.get_functions_count = pinmux_generic_get_function_count,
356
+
.get_function_name = pinmux_generic_get_function_name,
357
+
.get_function_groups = pinmux_generic_get_function_groups,
358
+
.set_mux = mpfs_pinctrl_set_mux,
359
+
};
360
+
361
+
static int mpfs_pinctrl_pinconf_get(struct pinctrl_dev *pctrl_dev, unsigned int pin,
362
+
unsigned long *config)
363
+
{
364
+
struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
365
+
int param = pinconf_to_config_param(*config);
366
+
int reg = mpfs_pinctrl_pin_to_iocfg_reg(pin);
367
+
int val;
368
+
u32 arg;
369
+
u8 str;
370
+
371
+
regmap_read(pctrl->regmap, reg, &val);
372
+
373
+
val = val >> mpfs_pinctrl_pin_to_iocfg_offset(pin);
374
+
val = val & MPFS_PINCTRL_IOCFG_MASK;
375
+
376
+
switch (param) {
377
+
case PIN_CONFIG_BIAS_BUS_HOLD:
378
+
if (!(val & MPFS_PINCTRL_WPD))
379
+
return -EINVAL;
380
+
381
+
if (!(val & MPFS_PINCTRL_WPU))
382
+
return -EINVAL;
383
+
384
+
arg = 1;
385
+
break;
386
+
case PIN_CONFIG_BIAS_PULL_DOWN:
387
+
if (!(val & MPFS_PINCTRL_WPD))
388
+
return -EINVAL;
389
+
390
+
if (val & MPFS_PINCTRL_WPU)
391
+
return -EINVAL;
392
+
393
+
arg = 1;
394
+
break;
395
+
case PIN_CONFIG_BIAS_PULL_UP:
396
+
if (!(val & MPFS_PINCTRL_WPU))
397
+
return -EINVAL;
398
+
399
+
if (val & MPFS_PINCTRL_WPD)
400
+
return -EINVAL;
401
+
402
+
arg = 1;
403
+
break;
404
+
case PIN_CONFIG_BIAS_DISABLE:
405
+
if (val & MPFS_PINCTRL_PULL_MASK)
406
+
return -EINVAL;
407
+
408
+
arg = 1;
409
+
break;
410
+
case PIN_CONFIG_DRIVE_STRENGTH:
411
+
str = FIELD_GET(MPFS_PINCTRL_DRV_MASK, val);
412
+
if (!str)
413
+
return -EINVAL;
414
+
415
+
arg = mpfs_pinctrl_get_drive_strength_ma(str);
416
+
break;
417
+
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
418
+
if (!FIELD_GET(MPFS_PINCTRL_ENHYST, val))
419
+
return -EINVAL;
420
+
421
+
arg = 1;
422
+
break;
423
+
case PIN_CONFIG_PERSIST_STATE:
424
+
if (!FIELD_GET(MPFS_PINCTRL_LP_PERSIST_EN, val))
425
+
return -EINVAL;
426
+
427
+
arg = 1;
428
+
break;
429
+
case PIN_CONFIG_MODE_LOW_POWER:
430
+
if (!FIELD_GET(MPFS_PINCTRL_LP_BYPASS_EN, val))
431
+
return -EINVAL;
432
+
433
+
arg = 1;
434
+
break;
435
+
case PIN_CONFIG_POWER_SOURCE:
436
+
arg = mpfs_pinctrl_pin_to_bank_voltage(pctrl, pin);
437
+
break;
438
+
case MPFS_PINCTRL_CLAMP_DIODE:
439
+
if (!FIELD_GET(MPFS_PINCTRL_CLAMP, val))
440
+
return -EINVAL;
441
+
442
+
arg = 1;
443
+
break;
444
+
case MPFS_PINCTRL_LOCKDOWN:
445
+
/*
446
+
* Lockdown is a read-only configuration, it'll get set if the
447
+
* tamper unit triggers global lockdown and lockdown has been
448
+
* set in the MSS Configurator for the bank a pin belongs to.
449
+
*/
450
+
if (!FIELD_GET(MPFS_PINCTRL_LOCKDN, val))
451
+
return -EINVAL;
452
+
453
+
arg = 1;
454
+
break;
455
+
case MPFS_PINCTRL_IBUFMD:
456
+
arg = FIELD_GET(MPFS_PINCTRL_IBUFMD_MASK, val);
457
+
break;
458
+
default:
459
+
return -ENOTSUPP;
460
+
}
461
+
462
+
*config = pinconf_to_config_packed(param, arg);
463
+
464
+
return 0;
465
+
}
466
+
467
+
static int mpfs_pinctrl_pinconf_generate_config(struct mpfs_pinctrl *pctrl, unsigned int pin,
468
+
unsigned long *configs, unsigned int num_configs,
469
+
u32 *value, u32 *bank_voltage)
470
+
{
471
+
u32 val = 0;
472
+
473
+
for (int i = 0; i < num_configs; i++) {
474
+
int param, tmp;
475
+
u32 arg;
476
+
477
+
param = pinconf_to_config_param(configs[i]);
478
+
arg = pinconf_to_config_argument(configs[i]);
479
+
480
+
switch (param) {
481
+
case PIN_CONFIG_BIAS_BUS_HOLD:
482
+
val |= MPFS_PINCTRL_PULL_MASK;
483
+
break;
484
+
case PIN_CONFIG_BIAS_PULL_DOWN:
485
+
val &= ~MPFS_PINCTRL_PULL_MASK;
486
+
val |= MPFS_PINCTRL_WPD;
487
+
break;
488
+
case PIN_CONFIG_BIAS_PULL_UP:
489
+
val &= ~MPFS_PINCTRL_PULL_MASK;
490
+
val |= MPFS_PINCTRL_WPU;
491
+
break;
492
+
case PIN_CONFIG_BIAS_DISABLE:
493
+
val &= ~MPFS_PINCTRL_PULL_MASK;
494
+
break;
495
+
case PIN_CONFIG_DRIVE_STRENGTH:
496
+
tmp = mpfs_pinctrl_get_drive_strength_val(arg);
497
+
if (tmp < 0)
498
+
return tmp;
499
+
500
+
val |= FIELD_PREP(MPFS_PINCTRL_DRV_MASK, tmp);
501
+
break;
502
+
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
503
+
if (!arg)
504
+
break;
505
+
val |= MPFS_PINCTRL_ENHYST;
506
+
break;
507
+
case PIN_CONFIG_PERSIST_STATE:
508
+
val |= MPFS_PINCTRL_LP_PERSIST_EN;
509
+
break;
510
+
case PIN_CONFIG_MODE_LOW_POWER:
511
+
if (arg)
512
+
val |= MPFS_PINCTRL_LP_BYPASS_EN;
513
+
break;
514
+
case PIN_CONFIG_POWER_SOURCE:
515
+
tmp = mpfs_pinctrl_get_bank_voltage_val(arg);
516
+
if (tmp < 0)
517
+
return tmp;
518
+
519
+
*bank_voltage = tmp;
520
+
break;
521
+
case MPFS_PINCTRL_CLAMP_DIODE:
522
+
val |= MPFS_PINCTRL_CLAMP;
523
+
break;
524
+
case MPFS_PINCTRL_IBUFMD:
525
+
val |= FIELD_PREP(MPFS_PINCTRL_IBUFMD_MASK, arg);
526
+
break;
527
+
default:
528
+
dev_err(pctrl->dev, "config %u not supported\n", param);
529
+
return -ENOTSUPP;
530
+
}
531
+
}
532
+
533
+
*value = val;
534
+
return 0;
535
+
}
536
+
537
+
static int mpfs_pinctrl_pin_set_config(struct mpfs_pinctrl *pctrl, unsigned int pin, u32 config)
538
+
{
539
+
int reg = mpfs_pinctrl_pin_to_iocfg_reg(pin);
540
+
int offset = mpfs_pinctrl_pin_to_iocfg_offset(pin);
541
+
u32 val, mask;
542
+
543
+
mask = MPFS_PINCTRL_IOCFG_MASK << offset;
544
+
val = config << offset;
545
+
546
+
regmap_update_bits(pctrl->regmap, reg, mask, val);
547
+
548
+
return 0;
549
+
}
550
+
551
+
static int mpfs_pinctrl_pinconf_set(struct pinctrl_dev *pctrl_dev, unsigned int pin,
552
+
unsigned long *configs, unsigned int num_configs)
553
+
{
554
+
struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
555
+
u32 val, bank_voltage = 0;
556
+
int ret;
557
+
558
+
ret = mpfs_pinctrl_pinconf_generate_config(pctrl, pin, configs, num_configs, &val,
559
+
&bank_voltage);
560
+
if (ret)
561
+
return ret;
562
+
563
+
ret = mpfs_pinctrl_pin_set_config(pctrl, pin, val);
564
+
if (ret)
565
+
return ret;
566
+
567
+
if (bank_voltage)
568
+
mpfs_pinctrl_set_bank_voltage(pctrl, pin, bank_voltage);
569
+
570
+
return 0;
571
+
}
572
+
573
+
static int mpfs_pinctrl_pinconf_group_set(struct pinctrl_dev *pctrl_dev, unsigned int gsel,
574
+
unsigned long *configs, unsigned int num_configs)
575
+
{
576
+
struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
577
+
const struct group_desc *group;
578
+
unsigned int pin;
579
+
u32 val, bank_voltage = 0;
580
+
int ret;
581
+
582
+
group = pinctrl_generic_get_group(pctrl_dev, gsel);
583
+
if (!group)
584
+
return -EINVAL;
585
+
586
+
/*
587
+
* Assume that the first pin in a group is representative, as the mss
588
+
* configurator doesn't allow splitting a function between two banks.
589
+
*/
590
+
pin = group->grp.pins[0];
591
+
592
+
ret = mpfs_pinctrl_pinconf_generate_config(pctrl, pin, configs, num_configs, &val,
593
+
&bank_voltage);
594
+
if (ret)
595
+
return ret;
596
+
597
+
for (int i = 0; i < group->grp.npins; i++)
598
+
mpfs_pinctrl_pin_set_config(pctrl, group->grp.pins[i], val);
599
+
600
+
if (bank_voltage)
601
+
mpfs_pinctrl_set_bank_voltage(pctrl, group->grp.pins[0], bank_voltage);
602
+
603
+
return 0;
604
+
}
605
+
606
+
static void mpfs_pinctrl_pinconf_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq,
607
+
unsigned int pin)
608
+
{
609
+
struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
610
+
u32 val;
611
+
int reg, offset;
612
+
613
+
reg = mpfs_pinctrl_pin_to_iocfg_reg(pin);
614
+
offset = mpfs_pinctrl_pin_to_iocfg_offset(pin);
615
+
616
+
seq_printf(seq, "pin: %u ", pin);
617
+
seq_printf(seq, "reg: %x offset: %u ", reg, offset);
618
+
619
+
if (reg < 0 || offset < 0)
620
+
return;
621
+
622
+
regmap_read(pctrl->regmap, reg, &val);
623
+
val = (val & (MPFS_PINCTRL_IOCFG_MASK << offset)) >> offset;
624
+
seq_printf(seq, "val: %x\n", val);
625
+
}
626
+
627
+
static const struct pinconf_ops mpfs_pinctrl_pinconf_ops = {
628
+
.pin_config_get = mpfs_pinctrl_pinconf_get,
629
+
.pin_config_set = mpfs_pinctrl_pinconf_set,
630
+
.pin_config_group_set = mpfs_pinctrl_pinconf_group_set,
631
+
.pin_config_dbg_show = mpfs_pinctrl_pinconf_dbg_show,
632
+
.is_generic = true,
633
+
};
634
+
635
+
static const struct pinctrl_pin_desc mpfs_pinctrl_pins[] = {
636
+
PINCTRL_PIN(0, "bank 4 0"),
637
+
PINCTRL_PIN(1, "bank 4 1"),
638
+
PINCTRL_PIN(2, "bank 4 2"),
639
+
PINCTRL_PIN(3, "bank 4 3"),
640
+
PINCTRL_PIN(4, "bank 4 4"),
641
+
PINCTRL_PIN(5, "bank 4 5"),
642
+
PINCTRL_PIN(6, "bank 4 6"),
643
+
PINCTRL_PIN(7, "bank 4 7"),
644
+
PINCTRL_PIN(8, "bank 4 8"),
645
+
PINCTRL_PIN(9, "bank 4 9"),
646
+
PINCTRL_PIN(10, "bank 4 10"),
647
+
PINCTRL_PIN(11, "bank 4 11"),
648
+
PINCTRL_PIN(12, "bank 4 12"),
649
+
PINCTRL_PIN(13, "bank 4 13"),
650
+
651
+
PINCTRL_PIN(14, "bank 2 0"),
652
+
PINCTRL_PIN(15, "bank 2 1"),
653
+
PINCTRL_PIN(16, "bank 2 2"),
654
+
PINCTRL_PIN(17, "bank 2 3"),
655
+
PINCTRL_PIN(18, "bank 2 4"),
656
+
PINCTRL_PIN(19, "bank 2 5"),
657
+
PINCTRL_PIN(20, "bank 2 6"),
658
+
PINCTRL_PIN(21, "bank 2 7"),
659
+
PINCTRL_PIN(22, "bank 2 8"),
660
+
PINCTRL_PIN(23, "bank 2 9"),
661
+
PINCTRL_PIN(24, "bank 2 10"),
662
+
PINCTRL_PIN(25, "bank 2 11"),
663
+
PINCTRL_PIN(26, "bank 2 12"),
664
+
PINCTRL_PIN(27, "bank 2 13"),
665
+
PINCTRL_PIN(28, "bank 2 14"),
666
+
PINCTRL_PIN(29, "bank 2 15"),
667
+
PINCTRL_PIN(30, "bank 2 16"),
668
+
PINCTRL_PIN(31, "bank 2 17"),
669
+
PINCTRL_PIN(32, "bank 2 18"),
670
+
PINCTRL_PIN(33, "bank 2 19"),
671
+
PINCTRL_PIN(34, "bank 2 20"),
672
+
PINCTRL_PIN(35, "bank 2 21"),
673
+
PINCTRL_PIN(36, "bank 2 22"),
674
+
PINCTRL_PIN(37, "bank 2 23"),
675
+
};
676
+
677
+
static int mpfs_pinctrl_probe(struct platform_device *pdev)
678
+
{
679
+
struct device *dev = &pdev->dev;
680
+
struct mpfs_pinctrl *pctrl;
681
+
int ret;
682
+
683
+
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
684
+
if (!pctrl)
685
+
return -ENOMEM;
686
+
687
+
pctrl->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
688
+
if (IS_ERR(pctrl->regmap))
689
+
dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n");
690
+
691
+
pctrl->sysreg_regmap = syscon_regmap_lookup_by_compatible("microchip,mpfs-sysreg-scb");
692
+
if (IS_ERR(pctrl->sysreg_regmap))
693
+
return PTR_ERR(pctrl->sysreg_regmap);
694
+
695
+
pctrl->desc.name = dev_name(dev);
696
+
pctrl->desc.pins = mpfs_pinctrl_pins;
697
+
pctrl->desc.npins = ARRAY_SIZE(mpfs_pinctrl_pins);
698
+
pctrl->desc.pctlops = &mpfs_pinctrl_ops;
699
+
pctrl->desc.pmxops = &mpfs_pinctrl_pinmux_ops;
700
+
pctrl->desc.confops = &mpfs_pinctrl_pinconf_ops;
701
+
pctrl->desc.owner = THIS_MODULE;
702
+
pctrl->desc.num_custom_params = ARRAY_SIZE(mpfs_pinctrl_custom_bindings);
703
+
pctrl->desc.custom_params = mpfs_pinctrl_custom_bindings;
704
+
705
+
pctrl->dev = dev;
706
+
707
+
ret = devm_mutex_init(dev, &pctrl->mutex);
708
+
if (ret)
709
+
return ret;
710
+
711
+
platform_set_drvdata(pdev, pctrl);
712
+
713
+
pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
714
+
if (IS_ERR(pctrl->pctrl))
715
+
return PTR_ERR(pctrl->pctrl);
716
+
717
+
return 0;
718
+
}
719
+
720
+
static const struct of_device_id mpfs_pinctrl_of_match[] = {
721
+
{ .compatible = "microchip,mpfs-pinctrl-mssio" },
722
+
{ }
723
+
};
724
+
MODULE_DEVICE_TABLE(of, mpfs_pinctrl_of_match);
725
+
726
+
static struct platform_driver mpfs_pinctrl_driver = {
727
+
.driver = {
728
+
.name = "mpfs-pinctrl",
729
+
.of_match_table = mpfs_pinctrl_of_match,
730
+
},
731
+
.probe = mpfs_pinctrl_probe,
732
+
};
733
+
module_platform_driver(mpfs_pinctrl_driver);
734
+
735
+
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
736
+
MODULE_DESCRIPTION("Polarfire SoC mssio pinctrl driver");
737
+
MODULE_LICENSE("GPL");
-69
drivers/pinctrl/pinconf-generic.c
-69
drivers/pinctrl/pinconf-generic.c
···
385
385
}
386
386
EXPORT_SYMBOL_GPL(pinconf_generic_parse_dt_config);
387
387
388
-
int pinconf_generic_dt_node_to_map_pinmux(struct pinctrl_dev *pctldev,
389
-
struct device_node *np,
390
-
struct pinctrl_map **map,
391
-
unsigned int *num_maps)
392
-
{
393
-
struct device *dev = pctldev->dev;
394
-
struct device_node *pnode;
395
-
unsigned long *configs = NULL;
396
-
unsigned int num_configs = 0;
397
-
struct property *prop;
398
-
unsigned int reserved_maps;
399
-
int reserve;
400
-
int ret;
401
-
402
-
prop = of_find_property(np, "pinmux", NULL);
403
-
if (!prop) {
404
-
dev_info(dev, "Missing pinmux property\n");
405
-
return -ENOENT;
406
-
}
407
-
408
-
pnode = of_get_parent(np);
409
-
if (!pnode) {
410
-
dev_info(dev, "Missing function node\n");
411
-
return -EINVAL;
412
-
}
413
-
414
-
reserved_maps = 0;
415
-
*map = NULL;
416
-
*num_maps = 0;
417
-
418
-
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
419
-
&num_configs);
420
-
if (ret < 0) {
421
-
dev_err(dev, "%pOF: could not parse node property\n", np);
422
-
return ret;
423
-
}
424
-
425
-
reserve = 1;
426
-
if (num_configs)
427
-
reserve++;
428
-
429
-
ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps,
430
-
num_maps, reserve);
431
-
if (ret < 0)
432
-
goto exit;
433
-
434
-
ret = pinctrl_utils_add_map_mux(pctldev, map,
435
-
&reserved_maps, num_maps, np->name,
436
-
pnode->name);
437
-
if (ret < 0)
438
-
goto exit;
439
-
440
-
if (num_configs) {
441
-
ret = pinctrl_utils_add_map_configs(pctldev, map, &reserved_maps,
442
-
num_maps, np->name, configs,
443
-
num_configs, PIN_MAP_TYPE_CONFIGS_GROUP);
444
-
if (ret < 0)
445
-
goto exit;
446
-
}
447
-
448
-
exit:
449
-
kfree(configs);
450
-
if (ret)
451
-
pinctrl_utils_free_map(pctldev, *map, *num_maps);
452
-
453
-
return ret;
454
-
}
455
-
EXPORT_SYMBOL_GPL(pinconf_generic_dt_node_to_map_pinmux);
456
-
457
388
int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
458
389
struct device_node *np, struct pinctrl_map **map,
459
390
unsigned int *reserved_maps, unsigned int *num_maps,
+16
drivers/pinctrl/pinconf.h
+16
drivers/pinctrl/pinconf.h
···
160
160
return -ENOTSUPP;
161
161
}
162
162
#endif
163
+
164
+
#if defined(CONFIG_GENERIC_PINCTRL) && defined (CONFIG_OF)
165
+
int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
166
+
struct device_node *np,
167
+
struct pinctrl_map **maps,
168
+
unsigned int *num_maps);
169
+
#else
170
+
static inline int
171
+
pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
172
+
struct device_node *np,
173
+
struct pinctrl_map **maps,
174
+
unsigned int *num_maps)
175
+
{
176
+
return -ENOTSUPP;
177
+
}
178
+
#endif
-2
drivers/pinctrl/pinctrl-amd.c
-2
drivers/pinctrl/pinctrl-amd.c
···
21
21
#include <linux/gpio/driver.h>
22
22
#include <linux/slab.h>
23
23
#include <linux/platform_device.h>
24
-
#include <linux/mutex.h>
25
24
#include <linux/acpi.h>
26
25
#include <linux/seq_file.h>
27
26
#include <linux/interrupt.h>
28
-
#include <linux/list.h>
29
27
#include <linux/bitops.h>
30
28
#include <linux/pinctrl/pinconf.h>
31
29
#include <linux/pinctrl/pinconf-generic.h>
+13
-5
drivers/pinctrl/pinctrl-apple-gpio.c
+13
-5
drivers/pinctrl/pinctrl-apple-gpio.c
···
102
102
static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
103
103
struct device_node *node,
104
104
struct pinctrl_map **map,
105
-
unsigned *num_maps)
105
+
unsigned int *num_maps)
106
106
{
107
-
unsigned reserved_maps;
107
+
unsigned int reserved_maps;
108
108
struct apple_gpio_pinctrl *pctl;
109
109
u32 pinfunc, pin, func;
110
110
int num_pins, i, ret;
···
170
170
171
171
/* Pin multiplexer functions */
172
172
173
-
static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func,
174
-
unsigned group)
173
+
static bool apple_gpio_pinmux_func_is_gpio(struct pinctrl_dev *pctldev,
174
+
unsigned int selector)
175
+
{
176
+
/* Function selector 0 is always the GPIO mode */
177
+
return (selector == 0);
178
+
}
179
+
180
+
static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned int func,
181
+
unsigned int group)
175
182
{
176
183
struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
177
184
···
193
186
.get_functions_count = pinmux_generic_get_function_count,
194
187
.get_function_name = pinmux_generic_get_function_name,
195
188
.get_function_groups = pinmux_generic_get_function_groups,
189
+
.function_is_gpio = apple_gpio_pinmux_func_is_gpio,
196
190
.set_mux = apple_gpio_pinmux_set,
197
191
.strict = true,
198
192
};
···
210
202
return GPIO_LINE_DIRECTION_IN;
211
203
}
212
204
213
-
static int apple_gpio_get(struct gpio_chip *chip, unsigned offset)
205
+
static int apple_gpio_get(struct gpio_chip *chip, unsigned int offset)
214
206
{
215
207
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
216
208
unsigned int reg = apple_gpio_get_reg(pctl, offset);
+9
drivers/pinctrl/pinctrl-at91-pio4.c
+9
drivers/pinctrl/pinctrl-at91-pio4.c
···
1053
1053
.last_bank_count = ATMEL_PIO_NPINS_PER_BANK,
1054
1054
};
1055
1055
1056
+
static const struct atmel_pioctrl_data microchip_sama7d65_pioctrl_data = {
1057
+
.nbanks = 5,
1058
+
.last_bank_count = 14, /* sama7d65 has only PE0 to PE13 */
1059
+
.slew_rate_support = 1,
1060
+
};
1061
+
1056
1062
static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
1057
1063
.nbanks = 5,
1058
1064
.last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */
···
1069
1063
{
1070
1064
.compatible = "atmel,sama5d2-pinctrl",
1071
1065
.data = &atmel_sama5d2_pioctrl_data,
1066
+
}, {
1067
+
.compatible = "microchip,sama7d65-pinctrl",
1068
+
.data = µchip_sama7d65_pioctrl_data,
1072
1069
}, {
1073
1070
.compatible = "microchip,sama7g5-pinctrl",
1074
1071
.data = µchip_sama7g5_pioctrl_data,
+23
-30
drivers/pinctrl/pinctrl-aw9523.c
+23
-30
drivers/pinctrl/pinctrl-aw9523.c
···
291
291
unsigned int mask, val;
292
292
int i, rc;
293
293
294
-
mutex_lock(&awi->i2c_lock);
294
+
guard(mutex)(&awi->i2c_lock);
295
295
for (i = 0; i < num_configs; i++) {
296
296
param = pinconf_to_config_param(configs[i]);
297
297
arg = pinconf_to_config_argument(configs[i]);
298
298
299
299
rc = aw9523_pcfg_param_to_reg(param, pin, ®);
300
300
if (rc)
301
-
goto end;
301
+
return rc;
302
302
303
303
switch (param) {
304
304
case PIN_CONFIG_LEVEL:
···
307
307
AW9523_REG_CONF_STATE(pin),
308
308
BIT(regbit), 0);
309
309
if (rc)
310
-
goto end;
310
+
return rc;
311
311
312
312
/* Then, fall through to config output level */
313
313
fallthrough;
···
323
323
break;
324
324
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
325
325
/* Open-Drain is supported only on port 0 */
326
-
if (pin >= AW9523_PINS_PER_PORT) {
327
-
rc = -ENOTSUPP;
328
-
goto end;
329
-
}
326
+
if (pin >= AW9523_PINS_PER_PORT)
327
+
return -ENOTSUPP;
328
+
330
329
mask = AW9523_GCR_GPOMD_MASK;
331
330
val = 0;
332
331
break;
···
340
341
val = AW9523_GCR_GPOMD_MASK;
341
342
break;
342
343
default:
343
-
rc = -ENOTSUPP;
344
-
goto end;
344
+
return -ENOTSUPP;
345
345
}
346
346
347
347
rc = regmap_update_bits(awi->regmap, reg, mask, val);
348
348
if (rc)
349
-
goto end;
349
+
return rc;
350
350
}
351
-
end:
352
-
mutex_unlock(&awi->i2c_lock);
353
-
return rc;
351
+
352
+
return 0;
354
353
}
355
354
356
355
static const struct pinconf_ops aw9523_pinconf_ops = {
···
596
599
u8 m, state = 0;
597
600
int ret;
598
601
599
-
mutex_lock(&awi->i2c_lock);
602
+
guard(mutex)(&awi->i2c_lock);
600
603
601
604
/* Port 0 (gpio 0-7) */
602
605
m = *mask;
603
606
if (m) {
604
607
ret = _aw9523_gpio_get_multiple(awi, 0, &state, m);
605
608
if (ret)
606
-
goto out;
609
+
return ret;
607
610
}
608
611
*bits = state;
609
612
···
613
616
ret = _aw9523_gpio_get_multiple(awi, AW9523_PINS_PER_PORT,
614
617
&state, m);
615
618
if (ret)
616
-
goto out;
619
+
return ret;
617
620
618
621
*bits |= (state << 8);
619
622
}
620
-
out:
621
-
mutex_unlock(&awi->i2c_lock);
622
-
return ret;
623
+
624
+
return 0;
623
625
}
624
626
625
627
static int aw9523_gpio_set_multiple(struct gpio_chip *chip,
···
628
632
struct aw9523 *awi = gpiochip_get_data(chip);
629
633
u8 mask_lo, mask_hi, bits_lo, bits_hi;
630
634
unsigned int reg;
631
-
int ret = 0;
635
+
int ret;
632
636
633
637
mask_lo = *mask;
634
638
mask_hi = *mask >> 8;
635
639
bits_lo = *bits;
636
640
bits_hi = *bits >> 8;
637
641
638
-
mutex_lock(&awi->i2c_lock);
642
+
guard(mutex)(&awi->i2c_lock);
639
643
if (mask_hi) {
640
644
reg = AW9523_REG_OUT_STATE(AW9523_PINS_PER_PORT);
641
645
ret = regmap_write_bits(awi->regmap, reg, mask_hi, bits_hi);
642
646
if (ret)
643
-
goto out;
647
+
return ret;
644
648
}
645
649
if (mask_lo) {
646
650
reg = AW9523_REG_OUT_STATE(0);
647
651
ret = regmap_write_bits(awi->regmap, reg, mask_lo, bits_lo);
648
652
if (ret)
649
-
goto out;
653
+
return ret;
650
654
}
651
655
652
-
out:
653
-
mutex_unlock(&awi->i2c_lock);
654
-
return ret;
656
+
return 0;
655
657
}
656
658
657
659
static int aw9523_gpio_set(struct gpio_chip *chip, unsigned int offset,
···
689
695
u8 regbit = offset % AW9523_PINS_PER_PORT;
690
696
int ret;
691
697
692
-
mutex_lock(&awi->i2c_lock);
698
+
guard(mutex)(&awi->i2c_lock);
693
699
ret = regmap_update_bits(awi->regmap, AW9523_REG_OUT_STATE(offset),
694
700
BIT(regbit), value ? BIT(regbit) : 0);
695
701
if (ret)
696
-
goto end;
702
+
return ret;
697
703
698
704
ret = regmap_update_bits(awi->regmap, AW9523_REG_CONF_STATE(offset),
699
705
BIT(regbit), 0);
700
-
end:
701
-
mutex_unlock(&awi->i2c_lock);
706
+
702
707
return ret;
703
708
}
704
709
+1
drivers/pinctrl/pinctrl-equilibrium.c
+1
drivers/pinctrl/pinctrl-equilibrium.c
+189
drivers/pinctrl/pinctrl-generic.c
+189
drivers/pinctrl/pinctrl-generic.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
#define pr_fmt(fmt) "generic pinconfig core: " fmt
4
+
5
+
#include <linux/array_size.h>
6
+
#include <linux/device.h>
7
+
#include <linux/module.h>
8
+
#include <linux/of.h>
9
+
#include <linux/slab.h>
10
+
11
+
#include <linux/pinctrl/pinconf-generic.h>
12
+
#include <linux/pinctrl/pinconf.h>
13
+
#include <linux/pinctrl/pinctrl.h>
14
+
15
+
#include "core.h"
16
+
#include "pinconf.h"
17
+
#include "pinctrl-utils.h"
18
+
#include "pinmux.h"
19
+
20
+
static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *pctldev,
21
+
struct device_node *parent,
22
+
struct device_node *np,
23
+
struct pinctrl_map **maps,
24
+
unsigned int *num_maps,
25
+
unsigned int *num_reserved_maps,
26
+
const char **group_names,
27
+
unsigned int ngroups)
28
+
{
29
+
struct device *dev = pctldev->dev;
30
+
const char **functions;
31
+
const char *group_name;
32
+
unsigned long *configs;
33
+
unsigned int num_configs, pin, *pins;
34
+
int npins, ret, reserve = 1;
35
+
36
+
npins = of_property_count_u32_elems(np, "pins");
37
+
38
+
if (npins < 1) {
39
+
dev_err(dev, "invalid pinctrl group %pOFn.%pOFn %d\n",
40
+
parent, np, npins);
41
+
return npins;
42
+
}
43
+
44
+
group_name = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", parent, np);
45
+
if (!group_name)
46
+
return -ENOMEM;
47
+
48
+
group_names[ngroups] = group_name;
49
+
50
+
pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
51
+
if (!pins)
52
+
return -ENOMEM;
53
+
54
+
functions = devm_kcalloc(dev, npins, sizeof(*functions), GFP_KERNEL);
55
+
if (!functions)
56
+
return -ENOMEM;
57
+
58
+
for (int i = 0; i < npins; i++) {
59
+
ret = of_property_read_u32_index(np, "pins", i, &pin);
60
+
if (ret)
61
+
return ret;
62
+
63
+
pins[i] = pin;
64
+
65
+
ret = of_property_read_string(np, "function", &functions[i]);
66
+
if (ret)
67
+
return ret;
68
+
}
69
+
70
+
ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve);
71
+
if (ret)
72
+
return ret;
73
+
74
+
ret = pinctrl_utils_add_map_mux(pctldev, maps, num_reserved_maps, num_maps, group_name,
75
+
parent->name);
76
+
if (ret < 0)
77
+
return ret;
78
+
79
+
ret = pinctrl_generic_add_group(pctldev, group_name, pins, npins, functions);
80
+
if (ret < 0)
81
+
return dev_err_probe(dev, ret, "failed to add group %s: %d\n",
82
+
group_name, ret);
83
+
84
+
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
85
+
if (ret)
86
+
return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n",
87
+
group_name);
88
+
89
+
if (num_configs == 0)
90
+
return 0;
91
+
92
+
ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve);
93
+
if (ret)
94
+
return ret;
95
+
96
+
ret = pinctrl_utils_add_map_configs(pctldev, maps, num_reserved_maps, num_maps, group_name,
97
+
configs,
98
+
num_configs, PIN_MAP_TYPE_CONFIGS_GROUP);
99
+
kfree(configs);
100
+
if (ret)
101
+
return ret;
102
+
103
+
return 0;
104
+
};
105
+
106
+
/*
107
+
* For platforms that do not define groups or functions in the driver, but
108
+
* instead use the devicetree to describe them. This function will, unlike
109
+
* pinconf_generic_dt_node_to_map() etc which rely on driver defined groups
110
+
* and functions, create them in addition to parsing pinconf properties and
111
+
* adding mappings.
112
+
*/
113
+
int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
114
+
struct device_node *np,
115
+
struct pinctrl_map **maps,
116
+
unsigned int *num_maps)
117
+
{
118
+
struct device *dev = pctldev->dev;
119
+
struct device_node *child_np;
120
+
const char **group_names;
121
+
unsigned int num_reserved_maps = 0;
122
+
int ngroups = 0;
123
+
int ret;
124
+
125
+
*maps = NULL;
126
+
*num_maps = 0;
127
+
128
+
/*
129
+
* Check if this is actually the pins node, or a parent containing
130
+
* multiple pins nodes.
131
+
*/
132
+
if (!of_property_present(np, "pins"))
133
+
goto parent;
134
+
135
+
group_names = devm_kcalloc(dev, 1, sizeof(*group_names), GFP_KERNEL);
136
+
if (!group_names)
137
+
return -ENOMEM;
138
+
139
+
ret = pinctrl_generic_pins_function_dt_subnode_to_map(pctldev, np, np,
140
+
maps, num_maps,
141
+
&num_reserved_maps,
142
+
group_names,
143
+
ngroups);
144
+
if (ret) {
145
+
pinctrl_utils_free_map(pctldev, *maps, *num_maps);
146
+
return dev_err_probe(dev, ret, "error figuring out mappings for %s\n", np->name);
147
+
}
148
+
149
+
ret = pinmux_generic_add_function(pctldev, np->name, group_names, 1, NULL);
150
+
if (ret < 0) {
151
+
pinctrl_utils_free_map(pctldev, *maps, *num_maps);
152
+
return dev_err_probe(dev, ret, "error adding function %s\n", np->name);
153
+
}
154
+
155
+
return 0;
156
+
157
+
parent:
158
+
for_each_available_child_of_node(np, child_np)
159
+
ngroups += 1;
160
+
161
+
group_names = devm_kcalloc(dev, ngroups, sizeof(*group_names), GFP_KERNEL);
162
+
if (!group_names)
163
+
return -ENOMEM;
164
+
165
+
ngroups = 0;
166
+
for_each_available_child_of_node_scoped(np, child_np) {
167
+
ret = pinctrl_generic_pins_function_dt_subnode_to_map(pctldev, np, child_np,
168
+
maps, num_maps,
169
+
&num_reserved_maps,
170
+
group_names,
171
+
ngroups);
172
+
if (ret) {
173
+
pinctrl_utils_free_map(pctldev, *maps, *num_maps);
174
+
return dev_err_probe(dev, ret, "error figuring out mappings for %s\n",
175
+
np->name);
176
+
}
177
+
178
+
ngroups++;
179
+
}
180
+
181
+
ret = pinmux_generic_add_function(pctldev, np->name, group_names, ngroups, NULL);
182
+
if (ret < 0) {
183
+
pinctrl_utils_free_map(pctldev, *maps, *num_maps);
184
+
return dev_err_probe(dev, ret, "error adding function %s\n", np->name);
185
+
}
186
+
187
+
return 0;
188
+
}
189
+
EXPORT_SYMBOL_GPL(pinctrl_generic_pins_function_dt_node_to_map);
+5
-2
drivers/pinctrl/pinctrl-k230.c
+5
-2
drivers/pinctrl/pinctrl-k230.c
···
65
65
};
66
66
67
67
struct k230_pinctrl {
68
+
struct device *dev;
68
69
struct pinctrl_desc pctl;
69
70
struct pinctrl_dev *pctl_dev;
70
71
struct regmap *regmap_base;
···
471
470
struct k230_pinctrl *info,
472
471
unsigned int index)
473
472
{
474
-
struct device *dev = info->pctl_dev->dev;
473
+
struct device *dev = info->dev;
475
474
const __be32 *list;
476
475
int size, i, ret;
477
476
···
512
511
struct k230_pinctrl *info,
513
512
unsigned int index)
514
513
{
515
-
struct device *dev = info->pctl_dev->dev;
514
+
struct device *dev = info->dev;
516
515
struct k230_pmx_func *func;
517
516
struct k230_pin_group *grp;
518
517
static unsigned int idx, i;
···
596
595
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
597
596
if (!info)
598
597
return -ENOMEM;
598
+
599
+
info->dev = dev;
599
600
600
601
pctl = &info->pctl;
601
602
+2
-4
drivers/pinctrl/pinctrl-microchip-sgpio.c
+2
-4
drivers/pinctrl/pinctrl-microchip-sgpio.c
···
264
264
* setting.
265
265
* After the manual burst, reenable the auto repeat mode again.
266
266
*/
267
-
mutex_lock(&priv->poll_lock);
267
+
guard(mutex)(&priv->poll_lock);
268
268
ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat,
269
269
single_shot);
270
270
if (ret)
271
-
goto out;
271
+
return ret;
272
272
273
273
ret = regmap_read_poll_timeout(priv->regs, addr, ctrl,
274
274
!(ctrl & single_shot), 100, 60000);
275
275
276
276
/* reenable auto repeat mode even if there was an error */
277
277
ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat);
278
-
out:
279
-
mutex_unlock(&priv->poll_lock);
280
278
281
279
return ret ?: ret2;
282
280
}
+4
-4
drivers/pinctrl/pinctrl-mpfs-iomux0.c
drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c
+4
-4
drivers/pinctrl/pinctrl-mpfs-iomux0.c
drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c
···
15
15
#include <linux/pinctrl/pinctrl.h>
16
16
#include <linux/pinctrl/pinmux.h>
17
17
18
-
#include "core.h"
19
-
#include "pinctrl-utils.h"
20
-
#include "pinconf.h"
21
-
#include "pinmux.h"
18
+
#include "../core.h"
19
+
#include "../pinctrl-utils.h"
20
+
#include "../pinconf.h"
21
+
#include "../pinmux.h"
22
22
23
23
#define MPFS_IOMUX0_REG 0x200
24
24
+183
-1
drivers/pinctrl/pinctrl-ocelot.c
+183
-1
drivers/pinctrl/pinctrl-ocelot.c
···
97
97
FUNC_FC_SHRD20,
98
98
FUNC_FUSA,
99
99
FUNC_GPIO,
100
+
FUNC_I2C,
101
+
FUNC_I2C_Sa,
100
102
FUNC_IB_TRG_a,
101
103
FUNC_IB_TRG_b,
102
104
FUNC_IB_TRG_c,
···
114
112
FUNC_IRQ1,
115
113
FUNC_IRQ1_IN,
116
114
FUNC_IRQ1_OUT,
115
+
FUNC_IRQ2,
117
116
FUNC_IRQ3,
118
117
FUNC_IRQ4,
119
118
FUNC_EXT_IRQ,
119
+
FUNC_MACLED,
120
120
FUNC_MIIM,
121
121
FUNC_MIIM_a,
122
122
FUNC_MIIM_b,
···
130
126
FUNC_OB_TRG_a,
131
127
FUNC_OB_TRG_b,
132
128
FUNC_PHY_LED,
129
+
FUNC_PHY_DBG,
133
130
FUNC_PCI_WAKE,
134
131
FUNC_MD,
135
132
FUNC_PCIE_PERST,
···
161
156
FUNC_SG0,
162
157
FUNC_SG1,
163
158
FUNC_SG2,
159
+
FUNC_SPI,
164
160
FUNC_SGPIO_a,
165
161
FUNC_SGPIO_b,
166
162
FUNC_SI,
167
163
FUNC_SI2,
164
+
FUNC_SI_Sa,
168
165
FUNC_SYNCE,
169
166
FUNC_TACHO,
170
167
FUNC_TACHO_a,
···
195
188
FUNC_EMMC_SD,
196
189
FUNC_REF_CLK,
197
190
FUNC_RCVRD_CLK,
191
+
FUNC_RGMII,
198
192
FUNC_MAX
199
193
};
200
194
···
245
237
[FUNC_FC_SHRD20] = "fc_shrd20",
246
238
[FUNC_FUSA] = "fusa",
247
239
[FUNC_GPIO] = "gpio",
240
+
[FUNC_I2C] = "i2c",
241
+
[FUNC_I2C_Sa] = "i2c_slave_a",
248
242
[FUNC_IB_TRG_a] = "ib_trig_a",
249
243
[FUNC_IB_TRG_b] = "ib_trig_b",
250
244
[FUNC_IB_TRG_c] = "ib_trig_c",
···
262
252
[FUNC_IRQ1] = "irq1",
263
253
[FUNC_IRQ1_IN] = "irq1_in",
264
254
[FUNC_IRQ1_OUT] = "irq1_out",
255
+
[FUNC_IRQ2] = "irq2",
265
256
[FUNC_IRQ3] = "irq3",
266
257
[FUNC_IRQ4] = "irq4",
267
258
[FUNC_EXT_IRQ] = "ext_irq",
259
+
[FUNC_MACLED] = "mac_led",
268
260
[FUNC_MIIM] = "miim",
269
261
[FUNC_MIIM_a] = "miim_a",
270
262
[FUNC_MIIM_b] = "miim_b",
···
275
263
[FUNC_MIIM_Sb] = "miim_slave_b",
276
264
[FUNC_MIIM_IRQ] = "miim_irq",
277
265
[FUNC_PHY_LED] = "phy_led",
266
+
[FUNC_PHY_DBG] = "phy_dbg",
278
267
[FUNC_PCI_WAKE] = "pci_wake",
279
268
[FUNC_PCIE_PERST] = "pcie_perst",
280
269
[FUNC_MD] = "md",
···
313
300
[FUNC_SGPIO_b] = "sgpio_b",
314
301
[FUNC_SI] = "si",
315
302
[FUNC_SI2] = "si2",
303
+
[FUNC_SI_Sa] = "si_slave_a",
304
+
[FUNC_SPI] = "spi",
316
305
[FUNC_SYNCE] = "synce",
317
306
[FUNC_TACHO] = "tacho",
318
307
[FUNC_TACHO_a] = "tacho_a",
···
343
328
[FUNC_EMMC_SD] = "emmc_sd",
344
329
[FUNC_REF_CLK] = "ref_clk",
345
330
[FUNC_RCVRD_CLK] = "rcvrd_clk",
331
+
[FUNC_RGMII] = "rgmii",
346
332
};
347
333
348
334
struct ocelot_pmx_func {
···
374
358
const struct ocelot_pincfg_data *pincfg_data;
375
359
struct ocelot_pmx_func func[FUNC_MAX];
376
360
u8 stride;
361
+
u8 altm_stride;
377
362
struct workqueue_struct *wq;
378
363
};
379
364
380
365
struct ocelot_match_data {
381
366
struct pinctrl_desc desc;
382
367
struct ocelot_pincfg_data pincfg_data;
368
+
unsigned int n_alt_modes;
383
369
};
384
370
385
371
struct ocelot_irq_work {
···
1339
1321
LAN969X_PIN(66),
1340
1322
};
1341
1323
1324
+
#define LAN9645X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \
1325
+
static struct ocelot_pin_caps lan9645x_pin_##p = { \
1326
+
.pin = p, \
1327
+
.functions = { \
1328
+
FUNC_##f0, FUNC_##f1, FUNC_##f2, \
1329
+
FUNC_##f3 \
1330
+
}, \
1331
+
.a_functions = { \
1332
+
FUNC_##f4, FUNC_##f5, FUNC_##f6, \
1333
+
FUNC_##f7 \
1334
+
}, \
1335
+
}
1336
+
1337
+
/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */
1338
+
LAN9645X_P(0, GPIO, SPI, SI_Sa, I2C_Sa, MIIM_Sa, UART, MIIM, PHY_DBG);
1339
+
LAN9645X_P(1, GPIO, SPI, SI_Sa, I2C_Sa, MIIM_Sa, UART, MIIM, PHY_DBG);
1340
+
LAN9645X_P(2, GPIO, SPI, SI_Sa, I2C, NONE, NONE, NONE, PHY_DBG);
1341
+
LAN9645X_P(3, GPIO, SPI, SI_Sa, I2C, MIIM_Sa, NONE, NONE, PHY_DBG);
1342
+
LAN9645X_P(4, GPIO, RGMII, TWI_SCL_M, I2C, NONE, NONE, SI_Sa, PHY_DBG);
1343
+
LAN9645X_P(5, GPIO, RGMII, TWI_SCL_M, I2C, NONE, NONE, SI_Sa, PHY_DBG);
1344
+
LAN9645X_P(6, GPIO, RGMII, TWI_SCL_M, NONE, NONE, NONE, SI_Sa, PHY_DBG);
1345
+
LAN9645X_P(7, GPIO, RGMII, TWI_SCL_M, SFP, SGPIO_a, MIIM, SI_Sa, PHY_DBG);
1346
+
LAN9645X_P(8, GPIO, RGMII, TWI_SCL_M, SFP, SGPIO_a, MIIM, NONE, PHY_DBG);
1347
+
LAN9645X_P(9, GPIO, RGMII, TWI_SCL_M, RECO_CLK, SGPIO_a, IRQ1, UART, PHY_DBG);
1348
+
LAN9645X_P(10, GPIO, RGMII, TWI_SCL_M, RECO_CLK, SGPIO_a, IRQ2, UART, PHY_DBG);
1349
+
LAN9645X_P(11, GPIO, RGMII, TWI_SCL_M, MIIM, NONE, IRQ3, NONE, PHY_DBG);
1350
+
LAN9645X_P(12, GPIO, RGMII, TWI_SCL_M, MIIM, PTP0, NONE, NONE, PHY_DBG);
1351
+
LAN9645X_P(13, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP1, MACLED, NONE, PHY_DBG);
1352
+
LAN9645X_P(14, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP2, MACLED, NONE, PHY_DBG);
1353
+
LAN9645X_P(15, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP3, NONE, NONE, PHY_DBG);
1354
+
LAN9645X_P(16, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1355
+
LAN9645X_P(17, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1356
+
LAN9645X_P(18, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1357
+
LAN9645X_P(19, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1358
+
LAN9645X_P(20, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1359
+
LAN9645X_P(21, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1360
+
LAN9645X_P(22, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1361
+
LAN9645X_P(23, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1362
+
LAN9645X_P(24, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1363
+
LAN9645X_P(25, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1364
+
LAN9645X_P(26, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1365
+
LAN9645X_P(27, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1366
+
LAN9645X_P(28, GPIO, RECO_CLK, MIIM, NONE, NONE, NONE, NONE, R);
1367
+
LAN9645X_P(29, GPIO, RECO_CLK, MIIM, NONE, NONE, NONE, NONE, R);
1368
+
LAN9645X_P(30, GPIO, PTP0, I2C, UART, NONE, NONE, NONE, R);
1369
+
LAN9645X_P(31, GPIO, PTP1, TWI_SCL_M, UART, NONE, NONE, NONE, R);
1370
+
LAN9645X_P(32, GPIO, PTP2, TWI_SCL_M, NONE, NONE, NONE, NONE, R);
1371
+
LAN9645X_P(33, GPIO, PTP3, IRQ0, NONE, NONE, NONE, NONE, R);
1372
+
LAN9645X_P(34, GPIO, RECO_CLK, PHY_LED, PHY_LED, NONE, NONE, NONE, R);
1373
+
LAN9645X_P(35, GPIO, RECO_CLK, PHY_LED, PHY_LED, NONE, MACLED, NONE, R);
1374
+
LAN9645X_P(36, GPIO, PTP0, PHY_LED, PHY_LED, NONE, MACLED, NONE, R);
1375
+
LAN9645X_P(37, GPIO, PTP1, PHY_LED, PHY_LED, NONE, MACLED, NONE, R);
1376
+
LAN9645X_P(38, GPIO, NONE, PHY_LED, PHY_LED, NONE, MACLED, NONE, R);
1377
+
LAN9645X_P(39, GPIO, UART, PHY_LED, NONE, NONE, MACLED, NONE, R);
1378
+
LAN9645X_P(40, GPIO, SPI, PHY_LED, SGPIO_a, NONE, MACLED, NONE, R);
1379
+
LAN9645X_P(41, GPIO, SPI, PHY_LED, SGPIO_a, IRQ1, MACLED, NONE, R);
1380
+
LAN9645X_P(42, GPIO, SPI, PHY_LED, SGPIO_a, IRQ2, MACLED, SFP, R);
1381
+
LAN9645X_P(43, GPIO, SPI, PHY_LED, SGPIO_a, IRQ3, MACLED, SFP, R);
1382
+
LAN9645X_P(44, GPIO, MIIM, I2C, NONE, NONE, NONE, NONE, R);
1383
+
LAN9645X_P(45, GPIO, MIIM, I2C, NONE, NONE, NONE, NONE, R);
1384
+
LAN9645X_P(46, GPIO, NONE, PHY_LED, NONE, NONE, NONE, NONE, R);
1385
+
LAN9645X_P(47, GPIO, NONE, PHY_LED, NONE, NONE, NONE, NONE, R);
1386
+
LAN9645X_P(48, GPIO, MIIM_Sa, PHY_LED, NONE, NONE, NONE, NONE, R);
1387
+
LAN9645X_P(49, GPIO, MIIM_Sa, PHY_LED, I2C_Sa, NONE, NONE, NONE, R);
1388
+
LAN9645X_P(50, GPIO, MIIM_Sa, PHY_LED, I2C_Sa, NONE, NONE, NONE, R);
1389
+
1390
+
#define LAN9645X_PIN(n) { \
1391
+
.number = n, \
1392
+
.name = "GPIO_"#n, \
1393
+
.drv_data = &lan9645x_pin_##n \
1394
+
}
1395
+
1396
+
static const struct pinctrl_pin_desc lan9645x_pins[] = {
1397
+
LAN9645X_PIN(0),
1398
+
LAN9645X_PIN(1),
1399
+
LAN9645X_PIN(2),
1400
+
LAN9645X_PIN(3),
1401
+
LAN9645X_PIN(4),
1402
+
LAN9645X_PIN(5),
1403
+
LAN9645X_PIN(6),
1404
+
LAN9645X_PIN(7),
1405
+
LAN9645X_PIN(8),
1406
+
LAN9645X_PIN(9),
1407
+
LAN9645X_PIN(10),
1408
+
LAN9645X_PIN(11),
1409
+
LAN9645X_PIN(12),
1410
+
LAN9645X_PIN(13),
1411
+
LAN9645X_PIN(14),
1412
+
LAN9645X_PIN(15),
1413
+
LAN9645X_PIN(16),
1414
+
LAN9645X_PIN(17),
1415
+
LAN9645X_PIN(18),
1416
+
LAN9645X_PIN(19),
1417
+
LAN9645X_PIN(20),
1418
+
LAN9645X_PIN(21),
1419
+
LAN9645X_PIN(22),
1420
+
LAN9645X_PIN(23),
1421
+
LAN9645X_PIN(24),
1422
+
LAN9645X_PIN(25),
1423
+
LAN9645X_PIN(26),
1424
+
LAN9645X_PIN(27),
1425
+
LAN9645X_PIN(28),
1426
+
LAN9645X_PIN(29),
1427
+
LAN9645X_PIN(30),
1428
+
LAN9645X_PIN(31),
1429
+
LAN9645X_PIN(32),
1430
+
LAN9645X_PIN(33),
1431
+
LAN9645X_PIN(34),
1432
+
LAN9645X_PIN(35),
1433
+
LAN9645X_PIN(36),
1434
+
LAN9645X_PIN(37),
1435
+
LAN9645X_PIN(38),
1436
+
LAN9645X_PIN(39),
1437
+
LAN9645X_PIN(40),
1438
+
LAN9645X_PIN(41),
1439
+
LAN9645X_PIN(42),
1440
+
LAN9645X_PIN(43),
1441
+
LAN9645X_PIN(44),
1442
+
LAN9645X_PIN(45),
1443
+
LAN9645X_PIN(46),
1444
+
LAN9645X_PIN(47),
1445
+
LAN9645X_PIN(48),
1446
+
LAN9645X_PIN(49),
1447
+
LAN9645X_PIN(50),
1448
+
};
1449
+
1342
1450
static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
1343
1451
{
1344
1452
return ARRAY_SIZE(ocelot_function_names);
···
1506
1362
return -1;
1507
1363
}
1508
1364
1509
-
#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
1365
+
#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->altm_stride * ((p) / 32))))
1510
1366
1511
1367
static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
1512
1368
unsigned int selector, unsigned int group)
···
1613
1469
return 0;
1614
1470
}
1615
1471
1472
+
static int lan9645x_gpio_request_enable(struct pinctrl_dev *pctldev,
1473
+
struct pinctrl_gpio_range *range,
1474
+
unsigned int offset)
1475
+
{
1476
+
return 0;
1477
+
}
1478
+
1616
1479
static const struct pinmux_ops ocelot_pmx_ops = {
1617
1480
.get_functions_count = ocelot_get_functions_count,
1618
1481
.get_function_name = ocelot_get_function_name,
···
1636
1485
.set_mux = lan966x_pinmux_set_mux,
1637
1486
.gpio_set_direction = ocelot_gpio_set_direction,
1638
1487
.gpio_request_enable = lan966x_gpio_request_enable,
1488
+
};
1489
+
1490
+
static const struct pinmux_ops lan9645x_pmx_ops = {
1491
+
.get_functions_count = ocelot_get_functions_count,
1492
+
.get_function_name = ocelot_get_function_name,
1493
+
.get_function_groups = ocelot_get_function_groups,
1494
+
.set_mux = lan966x_pinmux_set_mux,
1495
+
.gpio_set_direction = ocelot_gpio_set_direction,
1496
+
.gpio_request_enable = lan9645x_gpio_request_enable,
1639
1497
};
1640
1498
1641
1499
static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
···
2044
1884
},
2045
1885
};
2046
1886
1887
+
static struct ocelot_match_data lan9645xf_desc = {
1888
+
.desc = {
1889
+
.name = "lan9645xf-pinctrl",
1890
+
.pins = lan9645x_pins,
1891
+
.npins = ARRAY_SIZE(lan9645x_pins),
1892
+
.pctlops = &ocelot_pctl_ops,
1893
+
.pmxops = &lan9645x_pmx_ops,
1894
+
.confops = &ocelot_confops,
1895
+
.owner = THIS_MODULE,
1896
+
},
1897
+
.pincfg_data = {
1898
+
.pd_bit = BIT(3),
1899
+
.pu_bit = BIT(2),
1900
+
.drive_bits = GENMASK(1, 0),
1901
+
},
1902
+
.n_alt_modes = 7,
1903
+
};
1904
+
2047
1905
static int ocelot_create_group_func_map(struct device *dev,
2048
1906
struct ocelot_pinctrl *info)
2049
1907
{
···
2396
2218
{ .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
2397
2219
{ .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
2398
2220
{ .compatible = "microchip,lan9691-pinctrl", .data = &lan969x_desc },
2221
+
{ .compatible = "microchip,lan96455f-pinctrl", .data = &lan9645xf_desc },
2399
2222
{},
2400
2223
};
2401
2224
MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match);
···
2473
2294
reset_control_reset(reset);
2474
2295
2475
2296
info->stride = 1 + (info->desc->npins - 1) / 32;
2297
+
info->altm_stride = info->stride;
2298
+
if (data->n_alt_modes)
2299
+
info->altm_stride = fls(data->n_alt_modes);
2476
2300
2477
2301
regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
2478
2302
+1
-1
drivers/pinctrl/pinctrl-pic64gx-gpio2.c
drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c
+1
-1
drivers/pinctrl/pinctrl-pic64gx-gpio2.c
drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c
+9
-10
drivers/pinctrl/pinctrl-rockchip.c
+9
-10
drivers/pinctrl/pinctrl-rockchip.c
···
3639
3639
* The lock makes sure that either gpio-probe has completed
3640
3640
* or the gpio driver hasn't probed yet.
3641
3641
*/
3642
-
mutex_lock(&bank->deferred_lock);
3643
-
if (!gpio || !gpio->direction_output) {
3644
-
rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
3645
-
arg);
3646
-
mutex_unlock(&bank->deferred_lock);
3647
-
if (rc)
3648
-
return rc;
3649
-
3650
-
break;
3642
+
scoped_guard(mutex, &bank->deferred_lock) {
3643
+
if (!gpio || !gpio->direction_output) {
3644
+
rc = rockchip_pinconf_defer_pin(bank,
3645
+
pin - bank->pin_base,
3646
+
param, arg);
3647
+
if (rc)
3648
+
return rc;
3649
+
break;
3650
+
}
3651
3651
}
3652
-
mutex_unlock(&bank->deferred_lock);
3653
3652
}
3654
3653
3655
3654
switch (param) {
+2
-1
drivers/pinctrl/pinctrl-scmi.c
+2
-1
drivers/pinctrl/pinctrl-scmi.c
+2
drivers/pinctrl/pinctrl-single.c
+2
drivers/pinctrl/pinctrl-single.c
···
1359
1359
}
1360
1360
range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1361
1361
if (!range) {
1362
+
of_node_put(gpiospec.np);
1362
1363
ret = -ENOMEM;
1363
1364
break;
1364
1365
}
···
1369
1368
mutex_lock(&pcs->mutex);
1370
1369
list_add_tail(&range->node, &pcs->gpiofuncs);
1371
1370
mutex_unlock(&pcs->mutex);
1371
+
of_node_put(gpiospec.np);
1372
1372
}
1373
1373
return ret;
1374
1374
}
+1
drivers/pinctrl/pinctrl-st.c
+1
drivers/pinctrl/pinctrl-st.c
+4
-13
drivers/pinctrl/pinctrl-tb10x.c
+4
-13
drivers/pinctrl/pinctrl-tb10x.c
···
607
607
int muxmode = -1;
608
608
int i;
609
609
610
-
mutex_lock(&state->mutex);
610
+
guard(mutex)(&state->mutex);
611
611
612
612
/*
613
613
* Figure out to which port the requested GPIO belongs and how to
···
642
642
* Error: The requested pin is already
643
643
* used for something else.
644
644
*/
645
-
mutex_unlock(&state->mutex);
646
645
return -EBUSY;
647
646
}
648
647
break;
···
665
666
*/
666
667
if (muxport >= 0)
667
668
tb10x_pinctrl_set_config(state, muxport, muxmode);
668
-
669
-
mutex_unlock(&state->mutex);
670
669
671
670
return 0;
672
671
}
···
692
695
if (grp->port < 0)
693
696
return 0;
694
697
695
-
mutex_lock(&state->mutex);
698
+
guard(mutex)(&state->mutex);
696
699
697
700
/*
698
701
* Check if the requested function is compatible with previously
699
702
* requested functions.
700
703
*/
701
704
if (state->ports[grp->port].count
702
-
&& (state->ports[grp->port].mode != grp->mode)) {
703
-
mutex_unlock(&state->mutex);
705
+
&& (state->ports[grp->port].mode != grp->mode))
704
706
return -EBUSY;
705
-
}
706
707
707
708
/*
708
709
* Check if the requested function is compatible with previously
709
710
* requested GPIOs.
710
711
*/
711
712
for (i = 0; i < grp->pincnt; i++)
712
-
if (test_bit(grp->pins[i], state->gpios)) {
713
-
mutex_unlock(&state->mutex);
713
+
if (test_bit(grp->pins[i], state->gpios))
714
714
return -EBUSY;
715
-
}
716
715
717
716
tb10x_pinctrl_set_config(state, grp->port, grp->mode);
718
717
719
718
state->ports[grp->port].count++;
720
-
721
-
mutex_unlock(&state->mutex);
722
719
723
720
return 0;
724
721
}
+43
-3
drivers/pinctrl/qcom/pinctrl-glymur.c
+43
-3
drivers/pinctrl/qcom/pinctrl-glymur.c
···
1729
1729
{ 232, 206 }, { 234, 172 }, { 235, 173 }, { 242, 158 }, { 244, 156 },
1730
1730
};
1731
1731
1732
+
static const struct msm_gpio_wakeirq_map mahua_pdc_map[] = {
1733
+
{ 0, 116 }, { 2, 114 }, { 3, 115 }, { 4, 175 }, { 5, 176 },
1734
+
{ 7, 111 }, { 11, 129 }, { 13, 130 }, { 15, 112 }, { 19, 113 },
1735
+
{ 23, 187 }, { 27, 188 }, { 28, 121 }, { 29, 122 }, { 30, 136 },
1736
+
{ 31, 203 }, { 32, 189 }, { 34, 174 }, { 35, 190 }, { 36, 191 },
1737
+
{ 39, 124 }, { 43, 192 }, { 47, 193 }, { 51, 123 }, { 53, 133 },
1738
+
{ 55, 125 }, { 59, 131 }, { 64, 134 }, { 65, 150 }, { 66, 186 },
1739
+
{ 67, 132 }, { 68, 195 }, { 71, 135 }, { 75, 196 }, { 79, 197 },
1740
+
{ 83, 198 }, { 84, 181 }, { 85, 199 }, { 87, 200 }, { 91, 201 },
1741
+
{ 92, 182 }, { 93, 183 }, { 94, 184 }, { 95, 185 }, { 98, 202 },
1742
+
{ 105, 157 }, { 113, 128 }, { 121, 117 }, { 123, 118 }, { 125, 119 },
1743
+
{ 129, 120 }, { 131, 126 }, { 132, 160 }, { 133, 194 }, { 134, 127 },
1744
+
{ 141, 137 }, { 144, 138 }, { 145, 139 }, { 147, 140 }, { 148, 141 },
1745
+
{ 150, 146 }, { 151, 147 }, { 153, 148 }, { 154, 144 }, { 155, 159 },
1746
+
{ 156, 149 }, { 157, 151 }, { 163, 142 }, { 172, 143 }, { 181, 145 },
1747
+
{ 193, 161 }, { 196, 152 }, { 203, 177 }, { 208, 178 }, { 215, 162 },
1748
+
{ 217, 153 }, { 220, 154 }, { 221, 155 }, { 228, 179 }, { 230, 180 },
1749
+
{ 232, 206 }, { 234, 172 }, { 235, 173 }, { 242, 158 }, { 244, 156 },
1750
+
};
1751
+
1732
1752
static const struct msm_pinctrl_soc_data glymur_tlmm = {
1733
1753
.pins = glymur_pins,
1734
1754
.npins = ARRAY_SIZE(glymur_pins),
···
1762
1742
.egpio_func = 11,
1763
1743
};
1764
1744
1745
+
static const struct msm_pinctrl_soc_data mahua_tlmm = {
1746
+
.pins = glymur_pins,
1747
+
.npins = ARRAY_SIZE(glymur_pins),
1748
+
.functions = glymur_functions,
1749
+
.nfunctions = ARRAY_SIZE(glymur_functions),
1750
+
.groups = glymur_groups,
1751
+
.ngroups = ARRAY_SIZE(glymur_groups),
1752
+
.ngpios = 251,
1753
+
.wakeirq_map = mahua_pdc_map,
1754
+
.nwakeirq_map = ARRAY_SIZE(mahua_pdc_map),
1755
+
.egpio_func = 11,
1756
+
};
1757
+
1765
1758
static const struct of_device_id glymur_tlmm_of_match[] = {
1766
-
{ .compatible = "qcom,glymur-tlmm", },
1767
-
{ }
1759
+
{ .compatible = "qcom,glymur-tlmm", .data = &glymur_tlmm },
1760
+
{ .compatible = "qcom,mahua-tlmm", .data = &mahua_tlmm },
1761
+
{ },
1768
1762
};
1769
1763
1770
1764
static int glymur_tlmm_probe(struct platform_device *pdev)
1771
1765
{
1772
-
return msm_pinctrl_probe(pdev, &glymur_tlmm);
1766
+
const struct msm_pinctrl_soc_data *data;
1767
+
1768
+
data = of_device_get_match_data(&pdev->dev);
1769
+
if (!data)
1770
+
return -ENODEV;
1771
+
1772
+
return msm_pinctrl_probe(pdev, data);
1773
1773
}
1774
1774
1775
1775
static struct platform_driver glymur_tlmm_driver = {
+1
-1
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
···
73
73
static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
74
74
static const char * const wsa_swr_clk_groups[] = { "gpio10" };
75
75
static const char * const wsa_swr_data_groups[] = { "gpio11" };
76
-
static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
76
+
static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
77
77
78
78
static const struct lpi_pingroup sm8250_groups[] = {
79
79
LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
+2
drivers/pinctrl/renesas/Kconfig
+2
drivers/pinctrl/renesas/Kconfig
···
308
308
bool "pin control support for RZ/N2H and RZ/T2H" if COMPILE_TEST
309
309
depends on 64BIT && OF
310
310
select GPIOLIB
311
+
select GPIOLIB_IRQCHIP
311
312
select GENERIC_PINCTRL_GROUPS
312
313
select GENERIC_PINMUX_FUNCTIONS
313
314
select GENERIC_PINCONF
315
+
select IRQ_DOMAIN_HIERARCHY
314
316
help
315
317
This selects GPIO and pinctrl driver for Renesas RZ/T2H
316
318
platforms.
+239
-9
drivers/pinctrl/renesas/pinctrl-rzt2h.c
+239
-9
drivers/pinctrl/renesas/pinctrl-rzt2h.c
···
18
18
#include <linux/module.h>
19
19
#include <linux/mutex.h>
20
20
#include <linux/of_device.h>
21
+
#include <linux/of_irq.h>
21
22
#include <linux/platform_device.h>
22
23
#include <linux/pm_runtime.h>
23
24
#include <linux/spinlock.h>
···
52
51
53
52
#define PFC_MASK GENMASK_ULL(5, 0)
54
53
#define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8))
54
+
#define PFC_FUNC_INTERRUPT 0
55
55
56
56
/*
57
57
* Use 16 lower bits [15:0] for pin identifier
···
65
63
#define RZT2H_PIN_ID_TO_PIN(id) ((id) % RZT2H_PINS_PER_PORT)
66
64
67
65
#define RZT2H_MAX_SAFETY_PORTS 12
66
+
67
+
#define RZT2H_INTERRUPTS_START 16
68
+
#define RZT2H_INTERRUPTS_NUM 17
68
69
69
70
struct rzt2h_pinctrl_data {
70
71
unsigned int n_port_pins;
···
84
79
struct device *dev;
85
80
struct gpio_chip gpio_chip;
86
81
struct pinctrl_gpio_range gpio_range;
82
+
DECLARE_BITMAP(used_irqs, RZT2H_INTERRUPTS_NUM);
87
83
spinlock_t lock; /* lock read/write registers */
88
84
struct mutex mutex; /* serialize adding groups and functions */
89
85
bool safety_port_enabled;
86
+
atomic_t wakeup_path;
90
87
};
91
88
92
89
#define RZT2H_GET_BASE(pctrl, port) \
···
126
119
return (pincfg & BIT(pin)) ? 0 : -EINVAL;
127
120
}
128
121
122
+
static void rzt2h_pinctrl_set_gpio_en(struct rzt2h_pinctrl *pctrl,
123
+
u8 port, u8 pin, bool en)
124
+
{
125
+
u8 reg = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
126
+
127
+
if (en)
128
+
reg &= ~BIT(pin);
129
+
else
130
+
reg |= BIT(pin);
131
+
132
+
rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port));
133
+
}
134
+
129
135
static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl,
130
136
u8 port, u8 pin, u8 func)
131
137
{
···
153
133
rzt2h_pinctrl_writew(pctrl, port, reg16, PM(port));
154
134
155
135
/* Temporarily switch to GPIO mode with PMC register */
156
-
reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
157
-
rzt2h_pinctrl_writeb(pctrl, port, reg16 & ~BIT(pin), PMC(port));
136
+
rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true);
158
137
159
138
/* Select Pin function mode with PFC register */
160
139
reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
···
161
142
rzt2h_pinctrl_writeq(pctrl, port, reg64 | ((u64)func << (pin * 8)), PFC(port));
162
143
163
144
/* Switch to Peripheral pin function with PMC register */
164
-
reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
165
-
rzt2h_pinctrl_writeb(pctrl, port, reg16 | BIT(pin), PMC(port));
145
+
rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false);
166
146
}
167
147
168
148
static int rzt2h_pinctrl_set_mux(struct pinctrl_dev *pctldev,
···
465
447
u8 port = RZT2H_PIN_ID_TO_PORT(offset);
466
448
u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
467
449
int ret;
468
-
u8 reg;
469
450
470
451
ret = rzt2h_validate_pin(pctrl, offset);
471
452
if (ret)
···
477
460
guard(spinlock_irqsave)(&pctrl->lock);
478
461
479
462
/* Select GPIO mode in PMC Register */
480
-
reg = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
481
-
reg &= ~BIT(bit);
482
-
rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port));
463
+
rzt2h_pinctrl_set_gpio_en(pctrl, port, bit, true);
483
464
484
465
return 0;
485
466
}
···
501
486
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
502
487
u8 port = RZT2H_PIN_ID_TO_PORT(offset);
503
488
u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
489
+
u64 reg64;
504
490
u16 reg;
505
491
int ret;
506
492
···
509
493
if (ret)
510
494
return ret;
511
495
512
-
if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit))
496
+
guard(spinlock_irqsave)(&pctrl->lock);
497
+
498
+
if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) {
499
+
/*
500
+
* When a GPIO is being requested as an IRQ, the pinctrl
501
+
* framework expects to be able to read the GPIO's direction.
502
+
* IRQ function is separate from GPIO, and enabling it takes the
503
+
* pin out of GPIO mode.
504
+
* At this point, .child_to_parent_hwirq() has already been
505
+
* called to enable the IRQ function.
506
+
* Default to input direction for IRQ function.
507
+
*/
508
+
reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
509
+
reg64 = (reg64 >> (bit * 8)) & PFC_MASK;
510
+
if (reg64 == PFC_FUNC_INTERRUPT)
511
+
return GPIO_LINE_DIRECTION_IN;
512
+
513
513
return -EINVAL;
514
+
}
514
515
515
516
reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
516
517
reg = (reg >> (bit * 2)) & PM_MASK;
···
650
617
"P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
651
618
};
652
619
620
+
/*
621
+
* Interrupts 0-15 are for INTCPUn, which are not exposed externally.
622
+
* Interrupts 16-31 are for IRQn. SEI is 32.
623
+
* This table matches the information found in User Manual's Section
624
+
* 17.5, Multiplexed Pin Configurations, Tables 17.5 to 17.40, on the
625
+
* Interrupt rows.
626
+
* RZ/N2H has the same GPIO to IRQ mapping, except for the pins which
627
+
* are not present.
628
+
*/
629
+
static const u8 rzt2h_gpio_irq_map[] = {
630
+
32, 16, 17, 18, 19, 0, 20, 21,
631
+
22, 0, 0, 0, 0, 0, 0, 0,
632
+
23, 24, 25, 26, 27, 0, 0, 0,
633
+
0, 0, 28, 29, 30, 31, 0, 0,
634
+
0, 0, 0, 0, 0, 32, 16, 17,
635
+
18, 19, 20, 21, 22, 0, 0, 0,
636
+
0, 0, 24, 25, 26, 27, 0, 28,
637
+
29, 30, 31, 0, 0, 0, 0, 0,
638
+
0, 0, 0, 0, 0, 24, 32, 16,
639
+
0, 0, 0, 0, 0, 0, 0, 0,
640
+
20, 23, 17, 18, 19, 0, 16, 25,
641
+
29, 20, 21, 22, 23, 0, 0, 0,
642
+
0, 0, 0, 0, 17, 0, 0, 18,
643
+
0, 0, 19, 0, 0, 20, 0, 30,
644
+
21, 0, 0, 22, 0, 0, 24, 25,
645
+
0, 0, 0, 0, 0, 16, 17, 0,
646
+
18, 0, 0, 26, 27, 0, 0, 0,
647
+
28, 29, 30, 31, 0, 0, 0, 0,
648
+
23, 31, 32, 16, 17, 18, 19, 20,
649
+
0, 0, 0, 0, 0, 0, 0, 0,
650
+
0, 0, 0, 0, 0, 0, 0, 0,
651
+
0, 0, 0, 0, 0, 0, 0, 0,
652
+
27, 0, 0, 21, 22, 23, 24, 25,
653
+
26, 0, 0, 0, 0, 0, 0, 0,
654
+
27, 28, 29, 30, 31, 0, 0, 0,
655
+
0, 0, 0, 0, 0, 0, 0, 0,
656
+
0, 0, 0, 0, 0, 28, 32, 16,
657
+
17, 18, 19, 0, 0, 0, 0, 20,
658
+
21, 22, 23, 0, 0, 0, 0, 0,
659
+
0, 0, 0, 0, 24, 25, 0, 0,
660
+
0, 0, 26, 27, 0, 0, 0, 30,
661
+
0, 29, 0, 0, 0, 0, 0, 0,
662
+
0, 0, 0, 0, 0, 0, 0, 0,
663
+
0, 0, 0, 28, 29, 30, 31, 0,
664
+
0, 0, 0, 0, 0, 0, 0, 30,
665
+
0, 0, 0, 0, 0, 0, 0, 0,
666
+
};
667
+
668
+
static void rzt2h_gpio_irq_disable(struct irq_data *d)
669
+
{
670
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
671
+
unsigned int hwirq = irqd_to_hwirq(d);
672
+
673
+
irq_chip_disable_parent(d);
674
+
gpiochip_disable_irq(gc, hwirq);
675
+
}
676
+
677
+
static void rzt2h_gpio_irq_enable(struct irq_data *d)
678
+
{
679
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
680
+
unsigned int hwirq = irqd_to_hwirq(d);
681
+
682
+
gpiochip_enable_irq(gc, hwirq);
683
+
irq_chip_enable_parent(d);
684
+
}
685
+
686
+
static int rzt2h_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
687
+
{
688
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
689
+
struct rzt2h_pinctrl *pctrl = container_of(gc, struct rzt2h_pinctrl, gpio_chip);
690
+
int ret;
691
+
692
+
ret = irq_chip_set_wake_parent(d, on);
693
+
if (ret)
694
+
return ret;
695
+
696
+
/*
697
+
* If any of the IRQs are in use, put the entire pin controller on the
698
+
* device wakeup path.
699
+
*/
700
+
if (on)
701
+
atomic_inc(&pctrl->wakeup_path);
702
+
else
703
+
atomic_dec(&pctrl->wakeup_path);
704
+
705
+
return 0;
706
+
}
707
+
708
+
static const struct irq_chip rzt2h_gpio_irqchip = {
709
+
.name = "rzt2h-gpio",
710
+
.irq_disable = rzt2h_gpio_irq_disable,
711
+
.irq_enable = rzt2h_gpio_irq_enable,
712
+
.irq_mask = irq_chip_mask_parent,
713
+
.irq_unmask = irq_chip_unmask_parent,
714
+
.irq_set_type = irq_chip_set_type_parent,
715
+
.irq_set_wake = rzt2h_gpio_irq_set_wake,
716
+
.irq_eoi = irq_chip_eoi_parent,
717
+
.irq_set_affinity = irq_chip_set_affinity_parent,
718
+
.flags = IRQCHIP_IMMUTABLE,
719
+
GPIOCHIP_IRQ_RESOURCE_HELPERS,
720
+
};
721
+
722
+
static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
723
+
unsigned int child,
724
+
unsigned int child_type,
725
+
unsigned int *parent,
726
+
unsigned int *parent_type)
727
+
{
728
+
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc);
729
+
u8 port = RZT2H_PIN_ID_TO_PORT(child);
730
+
u8 pin = RZT2H_PIN_ID_TO_PIN(child);
731
+
u8 parent_irq;
732
+
733
+
parent_irq = rzt2h_gpio_irq_map[child];
734
+
if (parent_irq < RZT2H_INTERRUPTS_START)
735
+
return -EINVAL;
736
+
737
+
if (test_and_set_bit(parent_irq - RZT2H_INTERRUPTS_START,
738
+
pctrl->used_irqs))
739
+
return -EBUSY;
740
+
741
+
rzt2h_pinctrl_set_pfc_mode(pctrl, port, pin, PFC_FUNC_INTERRUPT);
742
+
743
+
*parent = parent_irq;
744
+
*parent_type = child_type;
745
+
746
+
return 0;
747
+
}
748
+
749
+
static void rzt2h_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq,
750
+
unsigned int nr_irqs)
751
+
{
752
+
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
753
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
754
+
struct rzt2h_pinctrl *pctrl = container_of(gc, struct rzt2h_pinctrl, gpio_chip);
755
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
756
+
u8 port = RZT2H_PIN_ID_TO_PORT(hwirq);
757
+
u8 pin = RZT2H_PIN_ID_TO_PIN(hwirq);
758
+
759
+
if (test_and_clear_bit(hwirq - RZT2H_INTERRUPTS_START, pctrl->used_irqs))
760
+
rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false);
761
+
762
+
irq_domain_free_irqs_common(domain, virq, nr_irqs);
763
+
}
764
+
765
+
static void rzt2h_gpio_init_irq_valid_mask(struct gpio_chip *gc,
766
+
unsigned long *valid_mask,
767
+
unsigned int ngpios)
768
+
{
769
+
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc);
770
+
unsigned int offset;
771
+
772
+
for (offset = 0; offset < ngpios; offset++) {
773
+
if (!rzt2h_gpio_irq_map[offset] || rzt2h_validate_pin(pctrl, offset))
774
+
clear_bit(offset, valid_mask);
775
+
}
776
+
}
777
+
653
778
static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl)
654
779
{
655
780
struct pinctrl_gpio_range *range = &pctrl->gpio_range;
656
781
struct gpio_chip *chip = &pctrl->gpio_chip;
782
+
struct device_node *np = pctrl->dev->of_node;
783
+
struct irq_domain *parent_domain;
657
784
struct device *dev = pctrl->dev;
658
785
struct of_phandle_args of_args;
786
+
struct device_node *parent_np;
787
+
struct gpio_irq_chip *girq;
659
788
int ret;
789
+
790
+
parent_np = of_irq_find_parent(np);
791
+
if (!parent_np)
792
+
return -ENXIO;
793
+
794
+
parent_domain = irq_find_host(parent_np);
795
+
of_node_put(parent_np);
796
+
if (!parent_domain)
797
+
return -EPROBE_DEFER;
660
798
661
799
ret = of_parse_phandle_with_fixed_args(dev->of_node, "gpio-ranges", 3, 0, &of_args);
662
800
if (ret)
···
851
647
chip->get = rzt2h_gpio_get;
852
648
chip->set = rzt2h_gpio_set;
853
649
chip->label = dev_name(dev);
650
+
651
+
if (of_property_present(np, "interrupt-controller")) {
652
+
girq = &chip->irq;
653
+
gpio_irq_chip_set_chip(girq, &rzt2h_gpio_irqchip);
654
+
girq->fwnode = dev_fwnode(pctrl->dev);
655
+
girq->parent_domain = parent_domain;
656
+
girq->child_to_parent_hwirq = rzt2h_gpio_child_to_parent_hwirq;
657
+
girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell;
658
+
girq->child_irq_domain_ops.free = rzt2h_gpio_irq_domain_free;
659
+
girq->init_valid_mask = rzt2h_gpio_init_irq_valid_mask;
660
+
}
854
661
855
662
range->id = 0;
856
663
range->pin_base = 0;
···
1007
792
{ /* sentinel */ }
1008
793
};
1009
794
795
+
static int rzt2h_pinctrl_suspend_noirq(struct device *dev)
796
+
{
797
+
struct rzt2h_pinctrl *pctrl = dev_get_drvdata(dev);
798
+
799
+
if (atomic_read(&pctrl->wakeup_path))
800
+
device_set_wakeup_path(dev);
801
+
802
+
return 0;
803
+
}
804
+
805
+
static const struct dev_pm_ops rzt2h_pinctrl_pm_ops = {
806
+
NOIRQ_SYSTEM_SLEEP_PM_OPS(rzt2h_pinctrl_suspend_noirq, NULL)
807
+
};
808
+
1010
809
static struct platform_driver rzt2h_pinctrl_driver = {
1011
810
.driver = {
1012
811
.name = DRV_NAME,
1013
812
.of_match_table = of_match_ptr(rzt2h_pinctrl_of_table),
813
+
.pm = pm_sleep_ptr(&rzt2h_pinctrl_pm_ops),
1014
814
.suppress_bind_attrs = true,
1015
815
},
1016
816
.probe = rzt2h_pinctrl_probe,
+117
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+117
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
···
1770
1770
.num_ctrl = ARRAY_SIZE(exynos8895_pin_ctrl),
1771
1771
};
1772
1772
1773
+
/* pin banks of exynos9610 pin-controller 0 (ALIVE) */
1774
+
static const struct samsung_pin_bank_data exynos9610_pin_banks0[] __initconst = {
1775
+
EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc0"),
1776
+
GS101_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00, 0x00),
1777
+
GS101_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04, 0x08),
1778
+
GS101_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08, 0x0c),
1779
+
EXYNOS850_PIN_BANK_EINTN(5, 0x080, "gpq0"),
1780
+
};
1781
+
1782
+
/* pin banks of exynos9610 pin-controller 1 (CMGP) */
1783
+
static const struct samsung_pin_bank_data exynos9610_pin_banks1[] __initconst = {
1784
+
EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00),
1785
+
EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04),
1786
+
EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08),
1787
+
EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C),
1788
+
EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10),
1789
+
EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14),
1790
+
EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18),
1791
+
EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C),
1792
+
EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20),
1793
+
EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24),
1794
+
EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28),
1795
+
EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2C),
1796
+
EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30),
1797
+
EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x34),
1798
+
EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x38),
1799
+
EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x3C),
1800
+
EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40),
1801
+
EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44),
1802
+
EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48),
1803
+
EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4C),
1804
+
EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50),
1805
+
EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x54),
1806
+
EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x58),
1807
+
EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x5C),
1808
+
EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x60),
1809
+
EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x64),
1810
+
};
1811
+
1812
+
/* pin banks of exynos9610 pin-controller 2 (DISPAUD) */
1813
+
static const struct samsung_pin_bank_data exynos9610_pin_banks2[] __initconst = {
1814
+
GS101_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00, 0x00),
1815
+
GS101_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04, 0x08),
1816
+
GS101_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08, 0x0c),
1817
+
};
1818
+
1819
+
/* pin banks of exynos9610 pin-controller 3 (FSYS) */
1820
+
static const struct samsung_pin_bank_data exynos9610_pin_banks3[] __initconst = {
1821
+
GS101_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00, 0x00),
1822
+
GS101_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04, 0x04),
1823
+
GS101_PIN_BANK_EINTG(6, 0x040, "gpf2", 0x08, 0x0c),
1824
+
};
1825
+
1826
+
/* pin banks of exynos9610 pin-controller 4 (TOP) */
1827
+
static const struct samsung_pin_bank_data exynos9610_pin_banks4[] __initconst = {
1828
+
GS101_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00, 0x00),
1829
+
GS101_PIN_BANK_EINTG(6, 0x020, "gpp1", 0x04, 0x08),
1830
+
GS101_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08, 0x10),
1831
+
GS101_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C, 0x18),
1832
+
GS101_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10, 0x20),
1833
+
GS101_PIN_BANK_EINTG(5, 0x0A0, "gpc2", 0x14, 0x28),
1834
+
GS101_PIN_BANK_EINTG(8, 0x0C0, "gpg0", 0x18, 0x30),
1835
+
GS101_PIN_BANK_EINTG(8, 0x0E0, "gpg1", 0x1C, 0x38),
1836
+
GS101_PIN_BANK_EINTG(8, 0x100, "gpg2", 0x20, 0x40),
1837
+
GS101_PIN_BANK_EINTG(6, 0x120, "gpg3", 0x24, 0x48),
1838
+
GS101_PIN_BANK_EINTG(3, 0x140, "gpg4", 0x28, 0x50),
1839
+
};
1840
+
1841
+
/* pin banks of exynos9610 pin-controller 5 (SHUB) */
1842
+
static const struct samsung_pin_bank_data exynos9610_pin_banks5[] __initconst = {
1843
+
EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gph0", 0x00),
1844
+
EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gph1", 0x04),
1845
+
};
1846
+
1847
+
static const struct samsung_pin_ctrl exynos9610_pin_ctrl[] __initconst = {
1848
+
{
1849
+
/* pin-controller instance 0 ALIVE data */
1850
+
.pin_banks = exynos9610_pin_banks0,
1851
+
.nr_banks = ARRAY_SIZE(exynos9610_pin_banks0),
1852
+
.eint_wkup_init = exynos_eint_wkup_init,
1853
+
.suspend = exynos_pinctrl_suspend,
1854
+
.resume = exynos_pinctrl_resume,
1855
+
}, {
1856
+
/* pin-controller instance 1 CMGP data */
1857
+
.pin_banks = exynos9610_pin_banks1,
1858
+
.nr_banks = ARRAY_SIZE(exynos9610_pin_banks1),
1859
+
.eint_wkup_init = exynos_eint_wkup_init,
1860
+
.suspend = exynos_pinctrl_suspend,
1861
+
.resume = exynos_pinctrl_resume,
1862
+
}, {
1863
+
/* pin-controller instance 2 DISPAUD data */
1864
+
.pin_banks = exynos9610_pin_banks2,
1865
+
.nr_banks = ARRAY_SIZE(exynos9610_pin_banks2),
1866
+
}, {
1867
+
/* pin-controller instance 3 FSYS data */
1868
+
.pin_banks = exynos9610_pin_banks3,
1869
+
.nr_banks = ARRAY_SIZE(exynos9610_pin_banks3),
1870
+
.suspend = exynos_pinctrl_suspend,
1871
+
.resume = exynos_pinctrl_resume,
1872
+
}, {
1873
+
/* pin-controller instance 4 TOP data */
1874
+
.pin_banks = exynos9610_pin_banks4,
1875
+
.nr_banks = ARRAY_SIZE(exynos9610_pin_banks4),
1876
+
.suspend = exynos_pinctrl_suspend,
1877
+
.resume = exynos_pinctrl_resume,
1878
+
}, {
1879
+
/* pin-controller instance 5 SHUB data */
1880
+
.pin_banks = exynos9610_pin_banks5,
1881
+
.nr_banks = ARRAY_SIZE(exynos9610_pin_banks5),
1882
+
},
1883
+
};
1884
+
1885
+
const struct samsung_pinctrl_of_match_data exynos9610_of_data __initconst = {
1886
+
.ctrl = exynos9610_pin_ctrl,
1887
+
.num_ctrl = ARRAY_SIZE(exynos9610_pin_ctrl),
1888
+
};
1889
+
1773
1890
/*
1774
1891
* Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
1775
1892
* gpio/pin-mux/pinconfig controllers.
+2
drivers/pinctrl/samsung/pinctrl-samsung.c
+2
drivers/pinctrl/samsung/pinctrl-samsung.c
···
1504
1504
.data = &exynos8890_of_data },
1505
1505
{ .compatible = "samsung,exynos8895-pinctrl",
1506
1506
.data = &exynos8895_of_data },
1507
+
{ .compatible = "samsung,exynos9610-pinctrl",
1508
+
.data = &exynos9610_of_data },
1507
1509
{ .compatible = "samsung,exynos9810-pinctrl",
1508
1510
.data = &exynos9810_of_data },
1509
1511
{ .compatible = "samsung,exynos990-pinctrl",
+1
drivers/pinctrl/samsung/pinctrl-samsung.h
+1
drivers/pinctrl/samsung/pinctrl-samsung.h
···
398
398
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
399
399
extern const struct samsung_pinctrl_of_match_data exynos8890_of_data;
400
400
extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
401
+
extern const struct samsung_pinctrl_of_match_data exynos9610_of_data;
401
402
extern const struct samsung_pinctrl_of_match_data exynos9810_of_data;
402
403
extern const struct samsung_pinctrl_of_match_data exynos990_of_data;
403
404
extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
-4
drivers/pinctrl/sophgo/pinctrl-cv18xx.h
-4
drivers/pinctrl/sophgo/pinctrl-cv18xx.h
···
6
6
#ifndef _PINCTRL_SOPHGO_CV18XX_H
7
7
#define _PINCTRL_SOPHGO_CV18XX_H
8
8
9
-
#include <linux/bits.h>
10
9
#include <linux/bitfield.h>
11
-
#include <linux/mutex.h>
12
-
#include <linux/spinlock.h>
13
-
#include <linux/platform_device.h>
14
10
#include <linux/pinctrl/pinctrl.h>
15
11
#include <linux/pinctrl/pinconf.h>
16
12
-6
drivers/pinctrl/sophgo/pinctrl-sg2042.h
-6
drivers/pinctrl/sophgo/pinctrl-sg2042.h
···
6
6
#ifndef _PINCTRL_SOPHGO_SG2042_H
7
7
#define _PINCTRL_SOPHGO_SG2042_H
8
8
9
-
#include <linux/bits.h>
10
-
#include <linux/bitfield.h>
11
-
#include <linux/device.h>
12
-
#include <linux/mutex.h>
13
-
#include <linux/spinlock.h>
14
-
#include <linux/platform_device.h>
15
9
#include <linux/pinctrl/pinctrl.h>
16
10
#include <linux/pinctrl/pinconf.h>
17
11
+2
-2
drivers/pinctrl/spacemit/Kconfig
+2
-2
drivers/pinctrl/spacemit/Kconfig
···
4
4
#
5
5
6
6
config PINCTRL_SPACEMIT_K1
7
-
bool "SpacemiT K1 SoC Pinctrl driver"
7
+
bool "SpacemiT K1/K3 SoC Pinctrl driver"
8
8
depends on ARCH_SPACEMIT || COMPILE_TEST
9
9
depends on OF
10
10
default ARCH_SPACEMIT
···
12
12
select GENERIC_PINMUX_FUNCTIONS
13
13
select GENERIC_PINCONF
14
14
help
15
-
Say Y to select the pinctrl driver for K1 SoC.
15
+
Say Y to select the pinctrl driver for K1/K3 SoC.
16
16
This pin controller allows selecting the mux function for
17
17
each pin. This driver can also be built as a module called
18
18
pinctrl-k1.
+590
-52
drivers/pinctrl/spacemit/pinctrl-k1.c
+590
-52
drivers/pinctrl/spacemit/pinctrl-k1.c
···
7
7
#include <linux/io.h>
8
8
#include <linux/of.h>
9
9
#include <linux/platform_device.h>
10
+
#include <linux/regmap.h>
10
11
#include <linux/seq_file.h>
11
12
#include <linux/spinlock.h>
13
+
#include <linux/mfd/syscon.h>
12
14
#include <linux/module.h>
13
15
#include <linux/mutex.h>
14
16
···
26
24
#include "pinctrl-k1.h"
27
25
28
26
/*
29
-
* +---------+----------+-----------+--------+--------+----------+--------+
30
-
* | pull | drive | schmitter | slew | edge | strong | mux |
31
-
* | up/down | strength | trigger | rate | detect | pull | mode |
32
-
* +---------+----------+-----------+--------+--------+----------+--------+
33
-
* 3 bits 3 bits 2 bits 1 bit 3 bits 1 bit 3 bits
27
+
* | pull | drive | schmitter | slew | edge | strong | mux |
28
+
* SoC | up/down | strength | trigger | rate | detect | pull | mode |
29
+
*-----+---------+----------+-----------+-------+--------+--------+--------+
30
+
* K1 | 3 bits | 3 bits | 2 bits | 1 bit | 3 bits | 1 bit | 3 bits |
31
+
*-----+---------+----------+-----------+-------+--------+--------+--------+
32
+
* K3 | 3 bits | 4 bits | 1 bits | 1 bit | 3 bits | 1 bit | 3 bits |
34
33
*/
35
34
36
35
#define PAD_MUX GENMASK(2, 0)
···
41
38
#define PAD_EDGE_CLEAR BIT(6)
42
39
#define PAD_SLEW_RATE GENMASK(12, 11)
43
40
#define PAD_SLEW_RATE_EN BIT(7)
44
-
#define PAD_SCHMITT GENMASK(9, 8)
45
-
#define PAD_DRIVE GENMASK(12, 10)
41
+
#define PAD_SCHMITT_K1 GENMASK(9, 8)
42
+
#define PAD_DRIVE_K1 GENMASK(12, 10)
43
+
#define PAD_SCHMITT_K3 BIT(8)
44
+
#define PAD_DRIVE_K3 GENMASK(12, 9)
46
45
#define PAD_PULLDOWN BIT(13)
47
46
#define PAD_PULLUP BIT(14)
48
47
#define PAD_PULL_EN BIT(15)
48
+
49
+
#define IO_PWR_DOMAIN_OFFSET 0x800
50
+
51
+
#define IO_PWR_DOMAIN_GPIO2_Kx 0x0c
52
+
#define IO_PWR_DOMAIN_MMC_Kx 0x1c
53
+
54
+
#define IO_PWR_DOMAIN_GPIO3_K1 0x10
55
+
#define IO_PWR_DOMAIN_QSPI_K1 0x20
56
+
57
+
#define IO_PWR_DOMAIN_GPIO1_K3 0x04
58
+
#define IO_PWR_DOMAIN_GPIO5_K3 0x10
59
+
#define IO_PWR_DOMAIN_GPIO4_K3 0x20
60
+
#define IO_PWR_DOMAIN_QSPI_K3 0x2c
61
+
62
+
#define IO_PWR_DOMAIN_V18EN BIT(2)
63
+
64
+
#define APBC_ASFAR 0x50
65
+
#define APBC_ASSAR 0x54
66
+
67
+
#define APBC_ASFAR_AKEY 0xbaba
68
+
#define APBC_ASSAR_AKEY 0xeb10
69
+
70
+
struct spacemit_pin_drv_strength {
71
+
u8 val;
72
+
u32 mA;
73
+
};
74
+
75
+
struct spacemit_pinctrl_dconf {
76
+
u64 schmitt_mask;
77
+
u64 drive_mask;
78
+
79
+
struct spacemit_pin_drv_strength *ds_1v8_tbl;
80
+
size_t ds_1v8_tbl_num;
81
+
struct spacemit_pin_drv_strength *ds_3v3_tbl;
82
+
size_t ds_3v3_tbl_num;
83
+
};
49
84
50
85
struct spacemit_pin {
51
86
u16 pin;
···
101
60
raw_spinlock_t lock;
102
61
103
62
void __iomem *regs;
63
+
64
+
struct regmap *regmap_apbc;
104
65
};
105
66
106
67
struct spacemit_pinctrl_data {
107
68
const struct pinctrl_pin_desc *pins;
108
69
const struct spacemit_pin *data;
109
70
u16 npins;
71
+
unsigned int (*pin_to_offset)(unsigned int pin);
72
+
unsigned int (*pin_to_io_pd_offset)(unsigned int pin);
73
+
const struct spacemit_pinctrl_dconf *dconf;
110
74
};
111
75
112
76
struct spacemit_pin_mux_config {
···
119
73
u32 config;
120
74
};
121
75
122
-
struct spacemit_pin_drv_strength {
123
-
u8 val;
124
-
u32 mA;
125
-
};
126
-
127
76
/* map pin id to pinctrl register offset, refer MFPR definition */
128
-
static unsigned int spacemit_pin_to_offset(unsigned int pin)
77
+
static unsigned int spacemit_k1_pin_to_offset(unsigned int pin)
129
78
{
130
79
unsigned int offset = 0;
131
80
···
165
124
return offset << 2;
166
125
}
167
126
127
+
static unsigned int spacemit_k3_pin_to_offset(unsigned int pin)
128
+
{
129
+
unsigned int offset = pin > 130 ? (pin + 2) : pin;
130
+
131
+
return offset << 2;
132
+
}
133
+
134
+
static unsigned int spacemit_k1_pin_to_io_pd_offset(unsigned int pin)
135
+
{
136
+
unsigned int offset = 0;
137
+
138
+
switch (pin) {
139
+
case 47 ... 52:
140
+
offset = IO_PWR_DOMAIN_GPIO3_K1;
141
+
break;
142
+
case 75 ... 80:
143
+
offset = IO_PWR_DOMAIN_GPIO2_Kx;
144
+
break;
145
+
case 98 ... 103:
146
+
offset = IO_PWR_DOMAIN_QSPI_K1;
147
+
break;
148
+
case 104 ... 109:
149
+
offset = IO_PWR_DOMAIN_MMC_Kx;
150
+
break;
151
+
}
152
+
153
+
return offset;
154
+
}
155
+
156
+
static unsigned int spacemit_k3_pin_to_io_pd_offset(unsigned int pin)
157
+
{
158
+
unsigned int offset = 0;
159
+
160
+
switch (pin) {
161
+
case 0 ... 20:
162
+
offset = IO_PWR_DOMAIN_GPIO1_K3;
163
+
break;
164
+
case 21 ... 41:
165
+
offset = IO_PWR_DOMAIN_GPIO2_Kx;
166
+
break;
167
+
case 76 ... 98:
168
+
offset = IO_PWR_DOMAIN_GPIO4_K3;
169
+
break;
170
+
case 99 ... 127:
171
+
offset = IO_PWR_DOMAIN_GPIO5_K3;
172
+
break;
173
+
case 132 ... 137:
174
+
offset = IO_PWR_DOMAIN_MMC_Kx;
175
+
break;
176
+
case 138 ... 144:
177
+
offset = IO_PWR_DOMAIN_QSPI_K3;
178
+
break;
179
+
}
180
+
181
+
return offset;
182
+
}
183
+
168
184
static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl,
169
185
unsigned int pin)
170
186
{
171
-
return pctrl->regs + spacemit_pin_to_offset(pin);
187
+
return pctrl->regs + pctrl->data->pin_to_offset(pin);
172
188
}
173
189
174
190
static u16 spacemit_dt_get_pin(u32 value)
···
275
177
void __iomem *reg;
276
178
u32 value;
277
179
278
-
seq_printf(seq, "offset: 0x%04x ", spacemit_pin_to_offset(pin));
180
+
seq_printf(seq, "offset: 0x%04x ", pctrl->data->pin_to_offset(pin));
279
181
seq_printf(seq, "type: %s ", io_type_desc[type]);
280
182
281
183
reg = spacemit_pin_to_reg(pctrl, pin);
···
283
185
seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value);
284
186
}
285
187
286
-
/* use IO high level output current as the table */
287
-
static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = {
288
-
{ 0, 11 },
289
-
{ 2, 21 },
290
-
{ 4, 32 },
291
-
{ 6, 42 },
188
+
static const struct spacemit_pinctrl_dconf k1_drive_conf = {
189
+
.drive_mask = PAD_DRIVE_K1,
190
+
.schmitt_mask = PAD_SCHMITT_K1,
191
+
.ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) {
192
+
{ 0, 11 },
193
+
{ 2, 21 },
194
+
{ 4, 32 },
195
+
{ 6, 42 },
196
+
},
197
+
.ds_1v8_tbl_num = 4,
198
+
.ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) {
199
+
{ 0, 7 },
200
+
{ 2, 10 },
201
+
{ 4, 13 },
202
+
{ 6, 16 },
203
+
{ 1, 19 },
204
+
{ 3, 23 },
205
+
{ 5, 26 },
206
+
{ 7, 29 },
207
+
},
208
+
.ds_3v3_tbl_num = 8,
292
209
};
293
210
294
-
static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = {
295
-
{ 0, 7 },
296
-
{ 2, 10 },
297
-
{ 4, 13 },
298
-
{ 6, 16 },
299
-
{ 1, 19 },
300
-
{ 3, 23 },
301
-
{ 5, 26 },
302
-
{ 7, 29 },
211
+
static const struct spacemit_pinctrl_dconf k3_drive_conf = {
212
+
.drive_mask = PAD_DRIVE_K3,
213
+
.schmitt_mask = PAD_SCHMITT_K3,
214
+
.ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) {
215
+
{ 0, 2 },
216
+
{ 1, 4 },
217
+
{ 2, 6 },
218
+
{ 3, 7 },
219
+
{ 4, 9 },
220
+
{ 5, 11 },
221
+
{ 6, 13 },
222
+
{ 7, 14 },
223
+
{ 8, 21 },
224
+
{ 9, 23 },
225
+
{ 10, 25 },
226
+
{ 11, 26 },
227
+
{ 12, 28 },
228
+
{ 13, 30 },
229
+
{ 14, 31 },
230
+
{ 15, 33 },
231
+
},
232
+
.ds_1v8_tbl_num = 16,
233
+
.ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) {
234
+
{ 0, 3 },
235
+
{ 1, 5 },
236
+
{ 2, 7 },
237
+
{ 3, 9 },
238
+
{ 4, 11 },
239
+
{ 5, 13 },
240
+
{ 6, 15 },
241
+
{ 7, 17 },
242
+
{ 8, 25 },
243
+
{ 9, 27 },
244
+
{ 10, 29 },
245
+
{ 11, 31 },
246
+
{ 12, 33 },
247
+
{ 13, 35 },
248
+
{ 14, 37 },
249
+
{ 15, 38 },
250
+
},
251
+
.ds_3v3_tbl_num = 16,
303
252
};
304
253
305
254
static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl,
···
374
229
}
375
230
376
231
static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type,
232
+
const struct spacemit_pinctrl_dconf *dconf,
377
233
u32 mA)
378
234
{
379
235
switch (type) {
380
236
case IO_TYPE_1V8:
381
-
return spacemit_get_ds_value(spacemit_ds_1v8_tbl,
382
-
ARRAY_SIZE(spacemit_ds_1v8_tbl),
237
+
return spacemit_get_ds_value(dconf->ds_1v8_tbl,
238
+
dconf->ds_1v8_tbl_num,
383
239
mA);
384
240
case IO_TYPE_3V3:
385
-
return spacemit_get_ds_value(spacemit_ds_3v3_tbl,
386
-
ARRAY_SIZE(spacemit_ds_3v3_tbl),
241
+
return spacemit_get_ds_value(dconf->ds_3v3_tbl,
242
+
dconf->ds_3v3_tbl_num,
387
243
mA);
388
244
default:
389
245
return 0;
···
392
246
}
393
247
394
248
static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type,
249
+
const struct spacemit_pinctrl_dconf *dconf,
395
250
u32 value)
396
251
{
397
252
switch (type) {
398
253
case IO_TYPE_1V8:
399
-
return spacemit_get_ds_mA(spacemit_ds_1v8_tbl,
400
-
ARRAY_SIZE(spacemit_ds_1v8_tbl),
401
-
value & 0x6);
254
+
return spacemit_get_ds_mA(dconf->ds_1v8_tbl,
255
+
dconf->ds_1v8_tbl_num,
256
+
value);
402
257
case IO_TYPE_3V3:
403
-
return spacemit_get_ds_mA(spacemit_ds_3v3_tbl,
404
-
ARRAY_SIZE(spacemit_ds_3v3_tbl),
258
+
return spacemit_get_ds_mA(dconf->ds_3v3_tbl,
259
+
dconf->ds_3v3_tbl_num,
405
260
value);
406
261
default:
407
262
return 0;
···
439
292
}
440
293
441
294
return 0;
295
+
}
296
+
297
+
static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl,
298
+
const struct spacemit_pin *spin,
299
+
const enum spacemit_pin_io_type type)
300
+
{
301
+
u32 offset, val = 0;
302
+
303
+
if (!pctrl->regmap_apbc)
304
+
return;
305
+
306
+
offset = pctrl->data->pin_to_io_pd_offset(spin->pin);
307
+
308
+
/* Other bits are reserved so don't need to save them */
309
+
if (type == IO_TYPE_1V8)
310
+
val = IO_PWR_DOMAIN_V18EN;
311
+
312
+
/*
313
+
* IO power domain registers are protected and cannot be accessed
314
+
* directly. Before performing any read or write to the IO power
315
+
* domain registers, an explicit unlock sequence must be issued
316
+
* via the AIB Secure Access Register (ASAR).
317
+
*
318
+
* The unlock sequence allows exactly one subsequent access to the
319
+
* IO power domain registers. After that access completes, the ASAR
320
+
* keys are automatically cleared, and the registers become locked
321
+
* again.
322
+
*
323
+
* This mechanism ensures that IO power domain configuration is
324
+
* performed intentionally, as incorrect voltage settings may
325
+
* result in functional failures or hardware damage.
326
+
*/
327
+
regmap_write(pctrl->regmap_apbc, APBC_ASFAR, APBC_ASFAR_AKEY);
328
+
regmap_write(pctrl->regmap_apbc, APBC_ASSAR, APBC_ASSAR_AKEY);
329
+
330
+
writel_relaxed(val, pctrl->regs + IO_PWR_DOMAIN_OFFSET + offset);
442
331
}
443
332
444
333
static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
···
684
501
685
502
#define ENABLE_DRV_STRENGTH BIT(1)
686
503
#define ENABLE_SLEW_RATE BIT(2)
687
-
static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin,
504
+
static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl,
505
+
const struct spacemit_pin *spin,
506
+
const struct spacemit_pinctrl_dconf *dconf,
688
507
unsigned long *configs,
689
508
unsigned int num_configs,
690
509
u32 *value)
···
724
539
drv_strength = arg;
725
540
break;
726
541
case PIN_CONFIG_INPUT_SCHMITT:
727
-
v &= ~PAD_SCHMITT;
728
-
v |= FIELD_PREP(PAD_SCHMITT, arg);
542
+
v &= ~dconf->schmitt_mask;
543
+
v |= (arg << __ffs(dconf->schmitt_mask)) & dconf->schmitt_mask;
729
544
break;
730
545
case PIN_CONFIG_POWER_SOURCE:
731
546
voltage = arg;
···
759
574
default:
760
575
return -EINVAL;
761
576
}
577
+
spacemit_set_io_pwr_domain(pctrl, spin, type);
762
578
}
763
579
764
-
val = spacemit_get_driver_strength(type, drv_strength);
580
+
val = spacemit_get_driver_strength(type, dconf, drv_strength);
765
581
766
-
v &= ~PAD_DRIVE;
767
-
v |= FIELD_PREP(PAD_DRIVE, val);
582
+
v &= ~dconf->drive_mask;
583
+
v |= (val << __ffs(dconf->drive_mask)) & dconf->drive_mask;
768
584
}
769
585
770
586
if (flag & ENABLE_SLEW_RATE) {
···
815
629
const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
816
630
u32 value;
817
631
818
-
if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value))
632
+
if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf,
633
+
configs, num_configs, &value))
819
634
return -EINVAL;
820
635
821
636
return spacemit_pin_set_config(pctrl, pin, value);
···
838
651
return -EINVAL;
839
652
840
653
spin = spacemit_get_pin(pctrl, group->grp.pins[0]);
841
-
if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value))
654
+
if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf,
655
+
configs, num_configs, &value))
842
656
return -EINVAL;
843
657
844
658
for (i = 0; i < group->grp.npins; i++)
···
873
685
struct seq_file *seq, unsigned int pin)
874
686
{
875
687
struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
688
+
const struct spacemit_pinctrl_dconf *dconf = pctrl->data->dconf;
876
689
const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
877
690
enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin);
878
691
void __iomem *reg = spacemit_pin_to_reg(pctrl, pin);
···
884
695
885
696
seq_printf(seq, ", io type (%s)", io_type_desc[type]);
886
697
887
-
tmp = FIELD_GET(PAD_DRIVE, value);
698
+
tmp = (value & dconf->drive_mask) >> __ffs(dconf->drive_mask);
888
699
if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) {
889
-
mA = spacemit_get_drive_strength_mA(type, tmp);
700
+
mA = spacemit_get_drive_strength_mA(type, dconf, tmp);
890
701
seq_printf(seq, ", drive strength (%d mA)", mA);
891
702
}
892
703
893
704
/* drive strength depend on power source, so show all values */
894
705
if (type == IO_TYPE_EXTERNAL)
895
706
seq_printf(seq, ", drive strength (%d or %d mA)",
896
-
spacemit_get_drive_strength_mA(IO_TYPE_1V8, tmp),
897
-
spacemit_get_drive_strength_mA(IO_TYPE_3V3, tmp));
707
+
spacemit_get_drive_strength_mA(IO_TYPE_1V8, dconf, tmp),
708
+
spacemit_get_drive_strength_mA(IO_TYPE_3V3, dconf, tmp));
898
709
899
710
seq_printf(seq, ", register (0x%04x)", value);
900
711
}
···
909
720
910
721
static int spacemit_pinctrl_probe(struct platform_device *pdev)
911
722
{
723
+
struct device_node *np = pdev->dev.of_node;
912
724
struct device *dev = &pdev->dev;
913
725
struct spacemit_pinctrl *pctrl;
914
726
struct clk *func_clk, *bus_clk;
···
930
740
pctrl->regs = devm_platform_ioremap_resource(pdev, 0);
931
741
if (IS_ERR(pctrl->regs))
932
742
return PTR_ERR(pctrl->regs);
743
+
744
+
pctrl->regmap_apbc = syscon_regmap_lookup_by_phandle(np, "spacemit,apbc");
745
+
if (IS_ERR(pctrl->regmap_apbc)) {
746
+
dev_warn(dev, "no syscon found, disable power voltage switch functionality\n");
747
+
pctrl->regmap_apbc = NULL;
748
+
}
933
749
934
750
func_clk = devm_clk_get_enabled(dev, "func");
935
751
if (IS_ERR(func_clk))
···
1238
1042
.pins = k1_pin_desc,
1239
1043
.data = k1_pin_data,
1240
1044
.npins = ARRAY_SIZE(k1_pin_desc),
1045
+
.pin_to_offset = spacemit_k1_pin_to_offset,
1046
+
.pin_to_io_pd_offset = spacemit_k1_pin_to_io_pd_offset,
1047
+
.dconf = &k1_drive_conf,
1048
+
};
1049
+
1050
+
static const struct pinctrl_pin_desc k3_pin_desc[] = {
1051
+
PINCTRL_PIN(0, "GPIO_00"),
1052
+
PINCTRL_PIN(1, "GPIO_01"),
1053
+
PINCTRL_PIN(2, "GPIO_02"),
1054
+
PINCTRL_PIN(3, "GPIO_03"),
1055
+
PINCTRL_PIN(4, "GPIO_04"),
1056
+
PINCTRL_PIN(5, "GPIO_05"),
1057
+
PINCTRL_PIN(6, "GPIO_06"),
1058
+
PINCTRL_PIN(7, "GPIO_07"),
1059
+
PINCTRL_PIN(8, "GPIO_08"),
1060
+
PINCTRL_PIN(9, "GPIO_09"),
1061
+
PINCTRL_PIN(10, "GPIO_10"),
1062
+
PINCTRL_PIN(11, "GPIO_11"),
1063
+
PINCTRL_PIN(12, "GPIO_12"),
1064
+
PINCTRL_PIN(13, "GPIO_13"),
1065
+
PINCTRL_PIN(14, "GPIO_14"),
1066
+
PINCTRL_PIN(15, "GPIO_15"),
1067
+
PINCTRL_PIN(16, "GPIO_16"),
1068
+
PINCTRL_PIN(17, "GPIO_17"),
1069
+
PINCTRL_PIN(18, "GPIO_18"),
1070
+
PINCTRL_PIN(19, "GPIO_19"),
1071
+
PINCTRL_PIN(20, "GPIO_20"),
1072
+
PINCTRL_PIN(21, "GPIO_21"),
1073
+
PINCTRL_PIN(22, "GPIO_22"),
1074
+
PINCTRL_PIN(23, "GPIO_23"),
1075
+
PINCTRL_PIN(24, "GPIO_24"),
1076
+
PINCTRL_PIN(25, "GPIO_25"),
1077
+
PINCTRL_PIN(26, "GPIO_26"),
1078
+
PINCTRL_PIN(27, "GPIO_27"),
1079
+
PINCTRL_PIN(28, "GPIO_28"),
1080
+
PINCTRL_PIN(29, "GPIO_29"),
1081
+
PINCTRL_PIN(30, "GPIO_30"),
1082
+
PINCTRL_PIN(31, "GPIO_31"),
1083
+
PINCTRL_PIN(32, "GPIO_32"),
1084
+
PINCTRL_PIN(33, "GPIO_33"),
1085
+
PINCTRL_PIN(34, "GPIO_34"),
1086
+
PINCTRL_PIN(35, "GPIO_35"),
1087
+
PINCTRL_PIN(36, "GPIO_36"),
1088
+
PINCTRL_PIN(37, "GPIO_37"),
1089
+
PINCTRL_PIN(38, "GPIO_38"),
1090
+
PINCTRL_PIN(39, "GPIO_39"),
1091
+
PINCTRL_PIN(40, "GPIO_40"),
1092
+
PINCTRL_PIN(41, "GPIO_41"),
1093
+
PINCTRL_PIN(42, "GPIO_42"),
1094
+
PINCTRL_PIN(43, "GPIO_43"),
1095
+
PINCTRL_PIN(44, "GPIO_44"),
1096
+
PINCTRL_PIN(45, "GPIO_45"),
1097
+
PINCTRL_PIN(46, "GPIO_46"),
1098
+
PINCTRL_PIN(47, "GPIO_47"),
1099
+
PINCTRL_PIN(48, "GPIO_48"),
1100
+
PINCTRL_PIN(49, "GPIO_49"),
1101
+
PINCTRL_PIN(50, "GPIO_50"),
1102
+
PINCTRL_PIN(51, "GPIO_51"),
1103
+
PINCTRL_PIN(52, "GPIO_52"),
1104
+
PINCTRL_PIN(53, "GPIO_53"),
1105
+
PINCTRL_PIN(54, "GPIO_54"),
1106
+
PINCTRL_PIN(55, "GPIO_55"),
1107
+
PINCTRL_PIN(56, "GPIO_56"),
1108
+
PINCTRL_PIN(57, "GPIO_57"),
1109
+
PINCTRL_PIN(58, "GPIO_58"),
1110
+
PINCTRL_PIN(59, "GPIO_59"),
1111
+
PINCTRL_PIN(60, "GPIO_60"),
1112
+
PINCTRL_PIN(61, "GPIO_61"),
1113
+
PINCTRL_PIN(62, "GPIO_62"),
1114
+
PINCTRL_PIN(63, "GPIO_63"),
1115
+
PINCTRL_PIN(64, "GPIO_64"),
1116
+
PINCTRL_PIN(65, "GPIO_65"),
1117
+
PINCTRL_PIN(66, "GPIO_66"),
1118
+
PINCTRL_PIN(67, "GPIO_67"),
1119
+
PINCTRL_PIN(68, "GPIO_68"),
1120
+
PINCTRL_PIN(69, "GPIO_69"),
1121
+
PINCTRL_PIN(70, "GPIO_70"),
1122
+
PINCTRL_PIN(71, "GPIO_71"),
1123
+
PINCTRL_PIN(72, "GPIO_72"),
1124
+
PINCTRL_PIN(73, "GPIO_73"),
1125
+
PINCTRL_PIN(74, "GPIO_74"),
1126
+
PINCTRL_PIN(75, "GPIO_75"),
1127
+
PINCTRL_PIN(76, "GPIO_76"),
1128
+
PINCTRL_PIN(77, "GPIO_77"),
1129
+
PINCTRL_PIN(78, "GPIO_78"),
1130
+
PINCTRL_PIN(79, "GPIO_79"),
1131
+
PINCTRL_PIN(80, "GPIO_80"),
1132
+
PINCTRL_PIN(81, "GPIO_81"),
1133
+
PINCTRL_PIN(82, "GPIO_82"),
1134
+
PINCTRL_PIN(83, "GPIO_83"),
1135
+
PINCTRL_PIN(84, "GPIO_84"),
1136
+
PINCTRL_PIN(85, "GPIO_85"),
1137
+
PINCTRL_PIN(86, "GPIO_86"),
1138
+
PINCTRL_PIN(87, "GPIO_87"),
1139
+
PINCTRL_PIN(88, "GPIO_88"),
1140
+
PINCTRL_PIN(89, "GPIO_89"),
1141
+
PINCTRL_PIN(90, "GPIO_90"),
1142
+
PINCTRL_PIN(91, "GPIO_91"),
1143
+
PINCTRL_PIN(92, "GPIO_92"),
1144
+
PINCTRL_PIN(93, "GPIO_93"),
1145
+
PINCTRL_PIN(94, "GPIO_94"),
1146
+
PINCTRL_PIN(95, "GPIO_95"),
1147
+
PINCTRL_PIN(96, "GPIO_96"),
1148
+
PINCTRL_PIN(97, "GPIO_97"),
1149
+
PINCTRL_PIN(98, "GPIO_98"),
1150
+
PINCTRL_PIN(99, "GPIO_99"),
1151
+
PINCTRL_PIN(100, "GPIO_100"),
1152
+
PINCTRL_PIN(101, "GPIO_101"),
1153
+
PINCTRL_PIN(102, "GPIO_102"),
1154
+
PINCTRL_PIN(103, "GPIO_103"),
1155
+
PINCTRL_PIN(104, "GPIO_104"),
1156
+
PINCTRL_PIN(105, "GPIO_105"),
1157
+
PINCTRL_PIN(106, "GPIO_106"),
1158
+
PINCTRL_PIN(107, "GPIO_107"),
1159
+
PINCTRL_PIN(108, "GPIO_108"),
1160
+
PINCTRL_PIN(109, "GPIO_109"),
1161
+
PINCTRL_PIN(110, "GPIO_110"),
1162
+
PINCTRL_PIN(111, "GPIO_111"),
1163
+
PINCTRL_PIN(112, "GPIO_112"),
1164
+
PINCTRL_PIN(113, "GPIO_113"),
1165
+
PINCTRL_PIN(114, "GPIO_114"),
1166
+
PINCTRL_PIN(115, "GPIO_115"),
1167
+
PINCTRL_PIN(116, "GPIO_116"),
1168
+
PINCTRL_PIN(117, "GPIO_117"),
1169
+
PINCTRL_PIN(118, "GPIO_118"),
1170
+
PINCTRL_PIN(119, "GPIO_119"),
1171
+
PINCTRL_PIN(120, "GPIO_120"),
1172
+
PINCTRL_PIN(121, "GPIO_121"),
1173
+
PINCTRL_PIN(122, "GPIO_122"),
1174
+
PINCTRL_PIN(123, "GPIO_123"),
1175
+
PINCTRL_PIN(124, "GPIO_124"),
1176
+
PINCTRL_PIN(125, "GPIO_125"),
1177
+
PINCTRL_PIN(126, "GPIO_126"),
1178
+
PINCTRL_PIN(127, "GPIO_127"),
1179
+
PINCTRL_PIN(128, "PWR_SCL"),
1180
+
PINCTRL_PIN(129, "PWR_SDA"),
1181
+
PINCTRL_PIN(130, "VCXO_EN"),
1182
+
PINCTRL_PIN(131, "PMIC_INT_N"),
1183
+
PINCTRL_PIN(132, "MMC1_DAT3"),
1184
+
PINCTRL_PIN(133, "MMC1_DAT2"),
1185
+
PINCTRL_PIN(134, "MMC1_DAT1"),
1186
+
PINCTRL_PIN(135, "MMC1_DAT0"),
1187
+
PINCTRL_PIN(136, "MMC1_CMD"),
1188
+
PINCTRL_PIN(137, "MMC1_CLK"),
1189
+
PINCTRL_PIN(138, "QSPI_DAT0"),
1190
+
PINCTRL_PIN(139, "QSPI_DAT1"),
1191
+
PINCTRL_PIN(140, "QSPI_DAT2"),
1192
+
PINCTRL_PIN(141, "QSPI_DAT3"),
1193
+
PINCTRL_PIN(142, "QSPI_CS0"),
1194
+
PINCTRL_PIN(143, "QSPI_CS1"),
1195
+
PINCTRL_PIN(144, "QSPI_CLK"),
1196
+
PINCTRL_PIN(145, "PRI_TDI"),
1197
+
PINCTRL_PIN(146, "PRI_TMS"),
1198
+
PINCTRL_PIN(147, "PRI_TCK"),
1199
+
PINCTRL_PIN(148, "PRI_TDO"),
1200
+
PINCTRL_PIN(149, "PWR_SSP_SCLK"),
1201
+
PINCTRL_PIN(150, "PWR_SSP_FRM"),
1202
+
PINCTRL_PIN(151, "PWR_SSP_TXD"),
1203
+
PINCTRL_PIN(152, "PWR_SSP_RXD"),
1204
+
};
1205
+
1206
+
static const struct spacemit_pin k3_pin_data[ARRAY_SIZE(k3_pin_desc)] = {
1207
+
/* GPIO1 bank */
1208
+
K1_FUNC_PIN(0, 0, IO_TYPE_EXTERNAL),
1209
+
K1_FUNC_PIN(1, 0, IO_TYPE_EXTERNAL),
1210
+
K1_FUNC_PIN(2, 0, IO_TYPE_EXTERNAL),
1211
+
K1_FUNC_PIN(3, 0, IO_TYPE_EXTERNAL),
1212
+
K1_FUNC_PIN(4, 0, IO_TYPE_EXTERNAL),
1213
+
K1_FUNC_PIN(5, 0, IO_TYPE_EXTERNAL),
1214
+
K1_FUNC_PIN(6, 0, IO_TYPE_EXTERNAL),
1215
+
K1_FUNC_PIN(7, 0, IO_TYPE_EXTERNAL),
1216
+
K1_FUNC_PIN(8, 0, IO_TYPE_EXTERNAL),
1217
+
K1_FUNC_PIN(9, 0, IO_TYPE_EXTERNAL),
1218
+
K1_FUNC_PIN(10, 0, IO_TYPE_EXTERNAL),
1219
+
K1_FUNC_PIN(11, 0, IO_TYPE_EXTERNAL),
1220
+
K1_FUNC_PIN(12, 0, IO_TYPE_EXTERNAL),
1221
+
K1_FUNC_PIN(13, 0, IO_TYPE_EXTERNAL),
1222
+
K1_FUNC_PIN(14, 0, IO_TYPE_EXTERNAL),
1223
+
K1_FUNC_PIN(15, 0, IO_TYPE_EXTERNAL),
1224
+
K1_FUNC_PIN(16, 0, IO_TYPE_EXTERNAL),
1225
+
K1_FUNC_PIN(17, 0, IO_TYPE_EXTERNAL),
1226
+
K1_FUNC_PIN(18, 0, IO_TYPE_EXTERNAL),
1227
+
K1_FUNC_PIN(19, 0, IO_TYPE_EXTERNAL),
1228
+
K1_FUNC_PIN(20, 0, IO_TYPE_EXTERNAL),
1229
+
1230
+
/* GPIO2 bank */
1231
+
K1_FUNC_PIN(21, 0, IO_TYPE_EXTERNAL),
1232
+
K1_FUNC_PIN(22, 0, IO_TYPE_EXTERNAL),
1233
+
K1_FUNC_PIN(23, 0, IO_TYPE_EXTERNAL),
1234
+
K1_FUNC_PIN(24, 0, IO_TYPE_EXTERNAL),
1235
+
K1_FUNC_PIN(25, 0, IO_TYPE_EXTERNAL),
1236
+
K1_FUNC_PIN(26, 0, IO_TYPE_EXTERNAL),
1237
+
K1_FUNC_PIN(27, 0, IO_TYPE_EXTERNAL),
1238
+
K1_FUNC_PIN(28, 0, IO_TYPE_EXTERNAL),
1239
+
K1_FUNC_PIN(29, 0, IO_TYPE_EXTERNAL),
1240
+
K1_FUNC_PIN(30, 0, IO_TYPE_EXTERNAL),
1241
+
K1_FUNC_PIN(31, 0, IO_TYPE_EXTERNAL),
1242
+
K1_FUNC_PIN(32, 0, IO_TYPE_EXTERNAL),
1243
+
K1_FUNC_PIN(33, 0, IO_TYPE_EXTERNAL),
1244
+
K1_FUNC_PIN(34, 0, IO_TYPE_EXTERNAL),
1245
+
K1_FUNC_PIN(35, 0, IO_TYPE_EXTERNAL),
1246
+
K1_FUNC_PIN(36, 0, IO_TYPE_EXTERNAL),
1247
+
K1_FUNC_PIN(37, 0, IO_TYPE_EXTERNAL),
1248
+
K1_FUNC_PIN(38, 0, IO_TYPE_EXTERNAL),
1249
+
K1_FUNC_PIN(39, 0, IO_TYPE_EXTERNAL),
1250
+
K1_FUNC_PIN(40, 0, IO_TYPE_EXTERNAL),
1251
+
K1_FUNC_PIN(41, 0, IO_TYPE_EXTERNAL),
1252
+
1253
+
/* GPIO3 bank */
1254
+
K1_FUNC_PIN(42, 0, IO_TYPE_1V8),
1255
+
K1_FUNC_PIN(43, 0, IO_TYPE_1V8),
1256
+
K1_FUNC_PIN(44, 0, IO_TYPE_1V8),
1257
+
K1_FUNC_PIN(45, 0, IO_TYPE_1V8),
1258
+
K1_FUNC_PIN(46, 0, IO_TYPE_1V8),
1259
+
K1_FUNC_PIN(47, 0, IO_TYPE_1V8),
1260
+
K1_FUNC_PIN(48, 0, IO_TYPE_1V8),
1261
+
K1_FUNC_PIN(49, 0, IO_TYPE_1V8),
1262
+
K1_FUNC_PIN(50, 0, IO_TYPE_1V8),
1263
+
K1_FUNC_PIN(51, 0, IO_TYPE_1V8),
1264
+
K1_FUNC_PIN(52, 0, IO_TYPE_1V8),
1265
+
K1_FUNC_PIN(53, 0, IO_TYPE_1V8),
1266
+
K1_FUNC_PIN(54, 0, IO_TYPE_1V8),
1267
+
K1_FUNC_PIN(55, 0, IO_TYPE_1V8),
1268
+
K1_FUNC_PIN(56, 0, IO_TYPE_1V8),
1269
+
K1_FUNC_PIN(57, 0, IO_TYPE_1V8),
1270
+
K1_FUNC_PIN(58, 0, IO_TYPE_1V8),
1271
+
K1_FUNC_PIN(59, 0, IO_TYPE_1V8),
1272
+
K1_FUNC_PIN(60, 0, IO_TYPE_1V8),
1273
+
K1_FUNC_PIN(61, 0, IO_TYPE_1V8),
1274
+
K1_FUNC_PIN(62, 0, IO_TYPE_1V8),
1275
+
K1_FUNC_PIN(63, 0, IO_TYPE_1V8),
1276
+
K1_FUNC_PIN(64, 0, IO_TYPE_1V8),
1277
+
K1_FUNC_PIN(65, 0, IO_TYPE_1V8),
1278
+
K1_FUNC_PIN(66, 0, IO_TYPE_1V8),
1279
+
K1_FUNC_PIN(67, 0, IO_TYPE_1V8),
1280
+
K1_FUNC_PIN(68, 0, IO_TYPE_1V8),
1281
+
K1_FUNC_PIN(69, 0, IO_TYPE_1V8),
1282
+
K1_FUNC_PIN(70, 0, IO_TYPE_1V8),
1283
+
K1_FUNC_PIN(71, 0, IO_TYPE_1V8),
1284
+
K1_FUNC_PIN(72, 0, IO_TYPE_1V8),
1285
+
K1_FUNC_PIN(73, 0, IO_TYPE_1V8),
1286
+
K1_FUNC_PIN(74, 0, IO_TYPE_1V8),
1287
+
K1_FUNC_PIN(75, 0, IO_TYPE_1V8),
1288
+
1289
+
/* GPIO4 bank */
1290
+
K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL),
1291
+
K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL),
1292
+
K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL),
1293
+
K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL),
1294
+
K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL),
1295
+
K1_FUNC_PIN(81, 0, IO_TYPE_EXTERNAL),
1296
+
K1_FUNC_PIN(82, 0, IO_TYPE_EXTERNAL),
1297
+
K1_FUNC_PIN(83, 0, IO_TYPE_EXTERNAL),
1298
+
K1_FUNC_PIN(84, 0, IO_TYPE_EXTERNAL),
1299
+
K1_FUNC_PIN(85, 0, IO_TYPE_EXTERNAL),
1300
+
K1_FUNC_PIN(86, 0, IO_TYPE_EXTERNAL),
1301
+
K1_FUNC_PIN(87, 0, IO_TYPE_EXTERNAL),
1302
+
K1_FUNC_PIN(88, 0, IO_TYPE_EXTERNAL),
1303
+
K1_FUNC_PIN(89, 0, IO_TYPE_EXTERNAL),
1304
+
K1_FUNC_PIN(90, 0, IO_TYPE_EXTERNAL),
1305
+
K1_FUNC_PIN(91, 0, IO_TYPE_EXTERNAL),
1306
+
K1_FUNC_PIN(92, 0, IO_TYPE_EXTERNAL),
1307
+
K1_FUNC_PIN(93, 0, IO_TYPE_EXTERNAL),
1308
+
K1_FUNC_PIN(94, 0, IO_TYPE_EXTERNAL),
1309
+
K1_FUNC_PIN(95, 0, IO_TYPE_EXTERNAL),
1310
+
K1_FUNC_PIN(96, 0, IO_TYPE_EXTERNAL),
1311
+
K1_FUNC_PIN(97, 0, IO_TYPE_EXTERNAL),
1312
+
K1_FUNC_PIN(98, 0, IO_TYPE_EXTERNAL),
1313
+
1314
+
/* GPIO5 bank */
1315
+
K1_FUNC_PIN(99, 0, IO_TYPE_EXTERNAL),
1316
+
K1_FUNC_PIN(100, 0, IO_TYPE_EXTERNAL),
1317
+
K1_FUNC_PIN(101, 0, IO_TYPE_EXTERNAL),
1318
+
K1_FUNC_PIN(102, 0, IO_TYPE_EXTERNAL),
1319
+
K1_FUNC_PIN(103, 0, IO_TYPE_EXTERNAL),
1320
+
K1_FUNC_PIN(104, 0, IO_TYPE_EXTERNAL),
1321
+
K1_FUNC_PIN(105, 0, IO_TYPE_EXTERNAL),
1322
+
K1_FUNC_PIN(106, 0, IO_TYPE_EXTERNAL),
1323
+
K1_FUNC_PIN(107, 0, IO_TYPE_EXTERNAL),
1324
+
K1_FUNC_PIN(108, 0, IO_TYPE_EXTERNAL),
1325
+
K1_FUNC_PIN(109, 0, IO_TYPE_EXTERNAL),
1326
+
K1_FUNC_PIN(110, 0, IO_TYPE_EXTERNAL),
1327
+
K1_FUNC_PIN(111, 0, IO_TYPE_EXTERNAL),
1328
+
K1_FUNC_PIN(112, 0, IO_TYPE_EXTERNAL),
1329
+
K1_FUNC_PIN(113, 0, IO_TYPE_EXTERNAL),
1330
+
K1_FUNC_PIN(114, 0, IO_TYPE_EXTERNAL),
1331
+
K1_FUNC_PIN(115, 0, IO_TYPE_EXTERNAL),
1332
+
K1_FUNC_PIN(116, 0, IO_TYPE_EXTERNAL),
1333
+
K1_FUNC_PIN(117, 0, IO_TYPE_EXTERNAL),
1334
+
K1_FUNC_PIN(118, 0, IO_TYPE_EXTERNAL),
1335
+
K1_FUNC_PIN(119, 0, IO_TYPE_EXTERNAL),
1336
+
K1_FUNC_PIN(120, 0, IO_TYPE_EXTERNAL),
1337
+
K1_FUNC_PIN(121, 0, IO_TYPE_EXTERNAL),
1338
+
K1_FUNC_PIN(122, 0, IO_TYPE_EXTERNAL),
1339
+
K1_FUNC_PIN(123, 0, IO_TYPE_EXTERNAL),
1340
+
K1_FUNC_PIN(124, 0, IO_TYPE_EXTERNAL),
1341
+
K1_FUNC_PIN(125, 0, IO_TYPE_EXTERNAL),
1342
+
K1_FUNC_PIN(126, 0, IO_TYPE_EXTERNAL),
1343
+
K1_FUNC_PIN(127, 0, IO_TYPE_EXTERNAL),
1344
+
1345
+
/* PMIC */
1346
+
K1_FUNC_PIN(128, 0, IO_TYPE_1V8),
1347
+
K1_FUNC_PIN(129, 0, IO_TYPE_1V8),
1348
+
K1_FUNC_PIN(130, 0, IO_TYPE_1V8),
1349
+
K1_FUNC_PIN(131, 0, IO_TYPE_1V8),
1350
+
1351
+
/* SD/MMC1 */
1352
+
K1_FUNC_PIN(132, 1, IO_TYPE_EXTERNAL),
1353
+
K1_FUNC_PIN(133, 1, IO_TYPE_EXTERNAL),
1354
+
K1_FUNC_PIN(134, 1, IO_TYPE_EXTERNAL),
1355
+
K1_FUNC_PIN(135, 1, IO_TYPE_EXTERNAL),
1356
+
K1_FUNC_PIN(136, 1, IO_TYPE_EXTERNAL),
1357
+
K1_FUNC_PIN(137, 1, IO_TYPE_EXTERNAL),
1358
+
1359
+
/* QSPI */
1360
+
K1_FUNC_PIN(138, 1, IO_TYPE_EXTERNAL),
1361
+
K1_FUNC_PIN(139, 1, IO_TYPE_EXTERNAL),
1362
+
K1_FUNC_PIN(140, 1, IO_TYPE_EXTERNAL),
1363
+
K1_FUNC_PIN(141, 1, IO_TYPE_EXTERNAL),
1364
+
K1_FUNC_PIN(142, 1, IO_TYPE_EXTERNAL),
1365
+
K1_FUNC_PIN(143, 1, IO_TYPE_EXTERNAL),
1366
+
K1_FUNC_PIN(144, 1, IO_TYPE_EXTERNAL),
1367
+
1368
+
/* PMIC */
1369
+
K1_FUNC_PIN(145, 1, IO_TYPE_1V8),
1370
+
K1_FUNC_PIN(146, 1, IO_TYPE_1V8),
1371
+
K1_FUNC_PIN(147, 1, IO_TYPE_1V8),
1372
+
K1_FUNC_PIN(148, 1, IO_TYPE_1V8),
1373
+
K1_FUNC_PIN(149, 1, IO_TYPE_1V8),
1374
+
K1_FUNC_PIN(150, 1, IO_TYPE_1V8),
1375
+
K1_FUNC_PIN(151, 1, IO_TYPE_1V8),
1376
+
K1_FUNC_PIN(152, 1, IO_TYPE_1V8),
1377
+
};
1378
+
1379
+
static const struct spacemit_pinctrl_data k3_pinctrl_data = {
1380
+
.pins = k3_pin_desc,
1381
+
.data = k3_pin_data,
1382
+
.npins = ARRAY_SIZE(k3_pin_desc),
1383
+
.pin_to_offset = spacemit_k3_pin_to_offset,
1384
+
.pin_to_io_pd_offset = spacemit_k3_pin_to_io_pd_offset,
1385
+
.dconf = &k3_drive_conf,
1241
1386
};
1242
1387
1243
1388
static const struct of_device_id k1_pinctrl_ids[] = {
1244
1389
{ .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data },
1390
+
{ .compatible = "spacemit,k3-pinctrl", .data = &k3_pinctrl_data },
1245
1391
{ /* sentinel */ }
1246
1392
};
1247
1393
MODULE_DEVICE_TABLE(of, k1_pinctrl_ids);
···
1599
1061
builtin_platform_driver(k1_pinctrl_driver);
1600
1062
1601
1063
MODULE_AUTHOR("Yixun Lan <dlan@gentoo.org>");
1602
-
MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1 SoC");
1064
+
MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1/K3 SoC");
1603
1065
MODULE_LICENSE("GPL");
-3
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
-3
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
···
7
7
*/
8
8
9
9
#include <linux/bits.h>
10
-
#include <linux/clk.h>
11
10
#include <linux/gpio/driver.h>
12
11
#include <linux/io.h>
13
12
#include <linux/mod_devicetable.h>
14
13
#include <linux/module.h>
15
-
#include <linux/mutex.h>
16
14
#include <linux/platform_device.h>
17
-
#include <linux/reset.h>
18
15
#include <linux/spinlock.h>
19
16
20
17
#include <linux/pinctrl/pinctrl.h>
+13
-17
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
+13
-17
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
···
474
474
#endif
475
475
};
476
476
477
-
static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
477
+
static void tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
478
478
{
479
479
u32 value;
480
480
481
-
mutex_lock(&padctl->lock);
481
+
guard(mutex)(&padctl->lock);
482
482
483
483
if (padctl->enable++ > 0)
484
-
goto out;
484
+
return;
485
485
486
486
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
487
487
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
···
498
498
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
499
499
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
500
500
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
501
-
502
-
out:
503
-
mutex_unlock(&padctl->lock);
504
-
return 0;
505
501
}
506
502
507
-
static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
503
+
static void tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
508
504
{
509
505
u32 value;
510
506
511
-
mutex_lock(&padctl->lock);
507
+
guard(mutex)(&padctl->lock);
512
508
513
509
if (WARN_ON(padctl->enable == 0))
514
-
goto out;
510
+
return;
515
511
516
512
if (--padctl->enable > 0)
517
-
goto out;
513
+
return;
518
514
519
515
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
520
516
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
···
527
531
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
528
532
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
529
533
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
530
-
531
-
out:
532
-
mutex_unlock(&padctl->lock);
533
-
return 0;
534
534
}
535
535
536
536
static int tegra_xusb_phy_init(struct phy *phy)
537
537
{
538
538
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
539
539
540
-
return tegra_xusb_padctl_enable(padctl);
540
+
tegra_xusb_padctl_enable(padctl);
541
+
542
+
return 0;
541
543
}
542
544
543
545
static int tegra_xusb_phy_exit(struct phy *phy)
544
546
{
545
547
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
546
548
547
-
return tegra_xusb_padctl_disable(padctl);
549
+
tegra_xusb_padctl_disable(padctl);
550
+
551
+
return 0;
548
552
}
549
553
550
554
static int pcie_phy_power_on(struct phy *phy)
-6
include/linux/pinctrl/devinfo.h
-6
include/linux/pinctrl/devinfo.h
···
43
43
#endif
44
44
};
45
45
46
-
extern int pinctrl_bind_pins(struct device *dev);
47
46
extern int pinctrl_init_done(struct device *dev);
48
47
49
48
static inline struct pinctrl *dev_pinctrl(struct device *dev)
···
56
57
#else
57
58
58
59
/* Stubs if we're not using pinctrl */
59
-
60
-
static inline int pinctrl_bind_pins(struct device *dev)
61
-
{
62
-
return 0;
63
-
}
64
60
65
61
static inline int pinctrl_init_done(struct device *dev)
66
62
{
-5
include/linux/pinctrl/pinconf-generic.h
-5
include/linux/pinctrl/pinconf-generic.h
···
250
250
return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps,
251
251
PIN_MAP_TYPE_INVALID);
252
252
}
253
-
254
-
int pinconf_generic_dt_node_to_map_pinmux(struct pinctrl_dev *pctldev,
255
-
struct device_node *np,
256
-
struct pinctrl_map **map,
257
-
unsigned int *num_maps);
258
253
#endif /* __LINUX_PINCTRL_PINCONF_GENERIC_H */
-3
include/linux/pinctrl/pinctrl.h
-3
include/linux/pinctrl/pinctrl.h
···
187
187
const struct pinctrl_desc *pctldesc,
188
188
void *driver_data);
189
189
190
-
extern void devm_pinctrl_unregister(struct device *dev,
191
-
struct pinctrl_dev *pctldev);
192
-
193
190
extern void pinctrl_add_gpio_range(struct pinctrl_dev *pctldev,
194
191
struct pinctrl_gpio_range *range);
195
192
extern void pinctrl_add_gpio_ranges(struct pinctrl_dev *pctldev,