Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Cross-merge networking fixes after downstream PR.
No conflicts (sort of) and no adjacent changes.
This merge reverts commit b3c9e65eb227 ("net: hsr: remove seqnr_lock")
from net, as it was superseded by
commit 430d67bdcb04 ("net: hsr: Use the seqnr lock for frames received via interlink port.")
in net-next.
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+2472
-1140
-16
Documentation/arch/riscv/vm-layout.rst
-16
Documentation/arch/riscv/vm-layout.rst
···
134
134
ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | modules, BPF
135
135
ffffffff80000000 | -2 GB | ffffffffffffffff | 2 GB | kernel
136
136
__________________|____________|__________________|_________|____________________________________________________________
137
-
138
-
139
-
Userspace VAs
140
-
--------------------
141
-
To maintain compatibility with software that relies on the VA space with a
142
-
maximum of 48 bits the kernel will, by default, return virtual addresses to
143
-
userspace from a 48-bit range (sv48). This default behavior is achieved by
144
-
passing 0 into the hint address parameter of mmap. On CPUs with an address space
145
-
smaller than sv48, the CPU maximum supported address space will be the default.
146
-
147
-
Software can "opt-in" to receiving VAs from another VA space by providing
148
-
a hint address to mmap. When a hint address is passed to mmap, the returned
149
-
address will never use more bits than the hint address. For example, if a hint
150
-
address of `1 << 40` is passed to mmap, a valid returned address will never use
151
-
bits 41 through 63. If no mappable addresses are available in that range, mmap
152
-
will return `MAP_FAILED`.
+11
-4
Documentation/devicetree/bindings/display/panel/wl-355608-a8.yaml
Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-panel.yaml
+11
-4
Documentation/devicetree/bindings/display/panel/wl-355608-a8.yaml
Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-panel.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/display/panel/wl-355608-a8.yaml#
4
+
$id: http://devicetree.org/schemas/display/panel/anbernic,rg35xx-plus-panel.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: WL-355608-A8 3.5" (640x480 pixels) 24-bit IPS LCD panel
7
+
title: Anbernic RG35XX series (WL-355608-A8) 3.5" 640x480 24-bit IPS LCD panel
8
8
9
9
maintainers:
10
10
- Ryan Walklin <ryan@testtoast.com>
···
15
15
16
16
properties:
17
17
compatible:
18
-
const: wl-355608-a8
18
+
oneOf:
19
+
- const: anbernic,rg35xx-plus-panel
20
+
- items:
21
+
- enum:
22
+
- anbernic,rg35xx-2024-panel
23
+
- anbernic,rg35xx-h-panel
24
+
- anbernic,rg35xx-sp-panel
25
+
- const: anbernic,rg35xx-plus-panel
19
26
20
27
reg:
21
28
maxItems: 1
···
47
40
#size-cells = <0>;
48
41
49
42
panel@0 {
50
-
compatible = "wl-355608-a8";
43
+
compatible = "anbernic,rg35xx-plus-panel";
51
44
reg = <0>;
52
45
53
46
spi-3wire;
+46
-16
Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
+46
-16
Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
···
14
14
description:
15
15
Bindings for NXP TJA11xx automotive PHYs
16
16
17
+
properties:
18
+
compatible:
19
+
enum:
20
+
- ethernet-phy-id0180.dc40
21
+
- ethernet-phy-id0180.dc41
22
+
- ethernet-phy-id0180.dc48
23
+
- ethernet-phy-id0180.dd00
24
+
- ethernet-phy-id0180.dd01
25
+
- ethernet-phy-id0180.dd02
26
+
- ethernet-phy-id0180.dc80
27
+
- ethernet-phy-id0180.dc82
28
+
- ethernet-phy-id001b.b010
29
+
- ethernet-phy-id001b.b013
30
+
- ethernet-phy-id001b.b030
31
+
- ethernet-phy-id001b.b031
32
+
17
33
allOf:
18
34
- $ref: ethernet-phy.yaml#
35
+
- if:
36
+
properties:
37
+
compatible:
38
+
contains:
39
+
enum:
40
+
- ethernet-phy-id0180.dc40
41
+
- ethernet-phy-id0180.dc41
42
+
- ethernet-phy-id0180.dc48
43
+
- ethernet-phy-id0180.dd00
44
+
- ethernet-phy-id0180.dd01
45
+
- ethernet-phy-id0180.dd02
46
+
47
+
then:
48
+
properties:
49
+
nxp,rmii-refclk-in:
50
+
type: boolean
51
+
description: |
52
+
The REF_CLK is provided for both transmitted and received data
53
+
in RMII mode. This clock signal is provided by the PHY and is
54
+
typically derived from an external 25MHz crystal. Alternatively,
55
+
a 50MHz clock signal generated by an external oscillator can be
56
+
connected to pin REF_CLK. A third option is to connect a 25MHz
57
+
clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
58
+
as input or output according to the actual circuit connection.
59
+
If present, indicates that the REF_CLK will be configured as
60
+
interface reference clock input when RMII mode enabled.
61
+
If not present, the REF_CLK will be configured as interface
62
+
reference clock output when RMII mode enabled.
63
+
Only supported on TJA1100 and TJA1101.
19
64
20
65
patternProperties:
21
66
"^ethernet-phy@[0-9a-f]+$":
···
77
32
description:
78
33
The ID number for the child PHY. Should be +1 of parent PHY.
79
34
80
-
nxp,rmii-refclk-in:
81
-
type: boolean
82
-
description: |
83
-
The REF_CLK is provided for both transmitted and received data
84
-
in RMII mode. This clock signal is provided by the PHY and is
85
-
typically derived from an external 25MHz crystal. Alternatively,
86
-
a 50MHz clock signal generated by an external oscillator can be
87
-
connected to pin REF_CLK. A third option is to connect a 25MHz
88
-
clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
89
-
as input or output according to the actual circuit connection.
90
-
If present, indicates that the REF_CLK will be configured as
91
-
interface reference clock input when RMII mode enabled.
92
-
If not present, the REF_CLK will be configured as interface
93
-
reference clock output when RMII mode enabled.
94
-
Only supported on TJA1100 and TJA1101.
95
-
96
35
required:
97
36
- reg
98
37
···
89
60
#size-cells = <0>;
90
61
91
62
tja1101_phy0: ethernet-phy@4 {
63
+
compatible = "ethernet-phy-id0180.dc40";
92
64
reg = <0x4>;
93
65
nxp,rmii-refclk-in;
94
66
};
+1
-1
Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
+1
-1
Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
+9
-1
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+9
-1
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
···
31
31
- rockchip,rk3588-pcie3-pipe-grf
32
32
- rockchip,rk3588-usb-grf
33
33
- rockchip,rk3588-usbdpphy-grf
34
-
- rockchip,rk3588-vo-grf
34
+
- rockchip,rk3588-vo0-grf
35
+
- rockchip,rk3588-vo1-grf
35
36
- rockchip,rk3588-vop-grf
36
37
- rockchip,rv1108-usbgrf
37
38
- const: syscon
39
+
- items:
40
+
- const: rockchip,rk3588-vo-grf
41
+
- const: syscon
42
+
deprecated: true
43
+
description: Use rockchip,rk3588-vo{0,1}-grf instead.
38
44
- items:
39
45
- enum:
40
46
- rockchip,px30-grf
···
268
262
contains:
269
263
enum:
270
264
- rockchip,rk3588-vo-grf
265
+
- rockchip,rk3588-vo0-grf
266
+
- rockchip,rk3588-vo1-grf
271
267
272
268
then:
273
269
required:
-1
Documentation/netlink/specs/mptcp_pm.yaml
-1
Documentation/netlink/specs/mptcp_pm.yaml
+260
Documentation/virt/hyperv/coco.rst
+260
Documentation/virt/hyperv/coco.rst
···
1
+
.. SPDX-License-Identifier: GPL-2.0
2
+
3
+
Confidential Computing VMs
4
+
==========================
5
+
Hyper-V can create and run Linux guests that are Confidential Computing
6
+
(CoCo) VMs. Such VMs cooperate with the physical processor to better protect
7
+
the confidentiality and integrity of data in the VM's memory, even in the
8
+
face of a hypervisor/VMM that has been compromised and may behave maliciously.
9
+
CoCo VMs on Hyper-V share the generic CoCo VM threat model and security
10
+
objectives described in Documentation/security/snp-tdx-threat-model.rst. Note
11
+
that Hyper-V specific code in Linux refers to CoCo VMs as "isolated VMs" or
12
+
"isolation VMs".
13
+
14
+
A Linux CoCo VM on Hyper-V requires the cooperation and interaction of the
15
+
following:
16
+
17
+
* Physical hardware with a processor that supports CoCo VMs
18
+
19
+
* The hardware runs a version of Windows/Hyper-V with support for CoCo VMs
20
+
21
+
* The VM runs a version of Linux that supports being a CoCo VM
22
+
23
+
The physical hardware requirements are as follows:
24
+
25
+
* AMD processor with SEV-SNP. Hyper-V does not run guest VMs with AMD SME,
26
+
SEV, or SEV-ES encryption, and such encryption is not sufficient for a CoCo
27
+
VM on Hyper-V.
28
+
29
+
* Intel processor with TDX
30
+
31
+
To create a CoCo VM, the "Isolated VM" attribute must be specified to Hyper-V
32
+
when the VM is created. A VM cannot be changed from a CoCo VM to a normal VM,
33
+
or vice versa, after it is created.
34
+
35
+
Operational Modes
36
+
-----------------
37
+
Hyper-V CoCo VMs can run in two modes. The mode is selected when the VM is
38
+
created and cannot be changed during the life of the VM.
39
+
40
+
* Fully-enlightened mode. In this mode, the guest operating system is
41
+
enlightened to understand and manage all aspects of running as a CoCo VM.
42
+
43
+
* Paravisor mode. In this mode, a paravisor layer between the guest and the
44
+
host provides some operations needed to run as a CoCo VM. The guest operating
45
+
system can have fewer CoCo enlightenments than is required in the
46
+
fully-enlightened case.
47
+
48
+
Conceptually, fully-enlightened mode and paravisor mode may be treated as
49
+
points on a spectrum spanning the degree of guest enlightenment needed to run
50
+
as a CoCo VM. Fully-enlightened mode is one end of the spectrum. A full
51
+
implementation of paravisor mode is the other end of the spectrum, where all
52
+
aspects of running as a CoCo VM are handled by the paravisor, and a normal
53
+
guest OS with no knowledge of memory encryption or other aspects of CoCo VMs
54
+
can run successfully. However, the Hyper-V implementation of paravisor mode
55
+
does not go this far, and is somewhere in the middle of the spectrum. Some
56
+
aspects of CoCo VMs are handled by the Hyper-V paravisor while the guest OS
57
+
must be enlightened for other aspects. Unfortunately, there is no
58
+
standardized enumeration of feature/functions that might be provided in the
59
+
paravisor, and there is no standardized mechanism for a guest OS to query the
60
+
paravisor for the feature/functions it provides. The understanding of what
61
+
the paravisor provides is hard-coded in the guest OS.
62
+
63
+
Paravisor mode has similarities to the `Coconut project`_, which aims to provide
64
+
a limited paravisor to provide services to the guest such as a virtual TPM.
65
+
However, the Hyper-V paravisor generally handles more aspects of CoCo VMs
66
+
than is currently envisioned for Coconut, and so is further toward the "no
67
+
guest enlightenments required" end of the spectrum.
68
+
69
+
.. _Coconut project: https://github.com/coconut-svsm/svsm
70
+
71
+
In the CoCo VM threat model, the paravisor is in the guest security domain
72
+
and must be trusted by the guest OS. By implication, the hypervisor/VMM must
73
+
protect itself against a potentially malicious paravisor just like it
74
+
protects against a potentially malicious guest.
75
+
76
+
The hardware architectural approach to fully-enlightened vs. paravisor mode
77
+
varies depending on the underlying processor.
78
+
79
+
* With AMD SEV-SNP processors, in fully-enlightened mode the guest OS runs in
80
+
VMPL 0 and has full control of the guest context. In paravisor mode, the
81
+
guest OS runs in VMPL 2 and the paravisor runs in VMPL 0. The paravisor
82
+
running in VMPL 0 has privileges that the guest OS in VMPL 2 does not have.
83
+
Certain operations require the guest to invoke the paravisor. Furthermore, in
84
+
paravisor mode the guest OS operates in "virtual Top Of Memory" (vTOM) mode
85
+
as defined by the SEV-SNP architecture. This mode simplifies guest management
86
+
of memory encryption when a paravisor is used.
87
+
88
+
* With Intel TDX processor, in fully-enlightened mode the guest OS runs in an
89
+
L1 VM. In paravisor mode, TD partitioning is used. The paravisor runs in the
90
+
L1 VM, and the guest OS runs in a nested L2 VM.
91
+
92
+
Hyper-V exposes a synthetic MSR to guests that describes the CoCo mode. This
93
+
MSR indicates if the underlying processor uses AMD SEV-SNP or Intel TDX, and
94
+
whether a paravisor is being used. It is straightforward to build a single
95
+
kernel image that can boot and run properly on either architecture, and in
96
+
either mode.
97
+
98
+
Paravisor Effects
99
+
-----------------
100
+
Running in paravisor mode affects the following areas of generic Linux kernel
101
+
CoCo VM functionality:
102
+
103
+
* Initial guest memory setup. When a new VM is created in paravisor mode, the
104
+
paravisor runs first and sets up the guest physical memory as encrypted. The
105
+
guest Linux does normal memory initialization, except for explicitly marking
106
+
appropriate ranges as decrypted (shared). In paravisor mode, Linux does not
107
+
perform the early boot memory setup steps that are particularly tricky with
108
+
AMD SEV-SNP in fully-enlightened mode.
109
+
110
+
* #VC/#VE exception handling. In paravisor mode, Hyper-V configures the guest
111
+
CoCo VM to route #VC and #VE exceptions to VMPL 0 and the L1 VM,
112
+
respectively, and not the guest Linux. Consequently, these exception handlers
113
+
do not run in the guest Linux and are not a required enlightenment for a
114
+
Linux guest in paravisor mode.
115
+
116
+
* CPUID flags. Both AMD SEV-SNP and Intel TDX provide a CPUID flag in the
117
+
guest indicating that the VM is operating with the respective hardware
118
+
support. While these CPUID flags are visible in fully-enlightened CoCo VMs,
119
+
the paravisor filters out these flags and the guest Linux does not see them.
120
+
Throughout the Linux kernel, explicitly testing these flags has mostly been
121
+
eliminated in favor of the cc_platform_has() function, with the goal of
122
+
abstracting the differences between SEV-SNP and TDX. But the
123
+
cc_platform_has() abstraction also allows the Hyper-V paravisor configuration
124
+
to selectively enable aspects of CoCo VM functionality even when the CPUID
125
+
flags are not set. The exception is early boot memory setup on SEV-SNP, which
126
+
tests the CPUID SEV-SNP flag. But not having the flag in Hyper-V paravisor
127
+
mode VM achieves the desired effect or not running SEV-SNP specific early
128
+
boot memory setup.
129
+
130
+
* Device emulation. In paravisor mode, the Hyper-V paravisor provides
131
+
emulation of devices such as the IO-APIC and TPM. Because the emulation
132
+
happens in the paravisor in the guest context (instead of the hypervisor/VMM
133
+
context), MMIO accesses to these devices must be encrypted references instead
134
+
of the decrypted references that would be used in a fully-enlightened CoCo
135
+
VM. The __ioremap_caller() function has been enhanced to make a callback to
136
+
check whether a particular address range should be treated as encrypted
137
+
(private). See the "is_private_mmio" callback.
138
+
139
+
* Encrypt/decrypt memory transitions. In a CoCo VM, transitioning guest
140
+
memory between encrypted and decrypted requires coordinating with the
141
+
hypervisor/VMM. This is done via callbacks invoked from
142
+
__set_memory_enc_pgtable(). In fully-enlightened mode, the normal SEV-SNP and
143
+
TDX implementations of these callbacks are used. In paravisor mode, a Hyper-V
144
+
specific set of callbacks is used. These callbacks invoke the paravisor so
145
+
that the paravisor can coordinate the transitions and inform the hypervisor
146
+
as necessary. See hv_vtom_init() where these callback are set up.
147
+
148
+
* Interrupt injection. In fully enlightened mode, a malicious hypervisor
149
+
could inject interrupts into the guest OS at times that violate x86/x64
150
+
architectural rules. For full protection, the guest OS should include
151
+
enlightenments that use the interrupt injection management features provided
152
+
by CoCo-capable processors. In paravisor mode, the paravisor mediates
153
+
interrupt injection into the guest OS, and ensures that the guest OS only
154
+
sees interrupts that are "legal". The paravisor uses the interrupt injection
155
+
management features provided by the CoCo-capable physical processor, thereby
156
+
masking these complexities from the guest OS.
157
+
158
+
Hyper-V Hypercalls
159
+
------------------
160
+
When in fully-enlightened mode, hypercalls made by the Linux guest are routed
161
+
directly to the hypervisor, just as in a non-CoCo VM. But in paravisor mode,
162
+
normal hypercalls trap to the paravisor first, which may in turn invoke the
163
+
hypervisor. But the paravisor is idiosyncratic in this regard, and a few
164
+
hypercalls made by the Linux guest must always be routed directly to the
165
+
hypervisor. These hypercall sites test for a paravisor being present, and use
166
+
a special invocation sequence. See hv_post_message(), for example.
167
+
168
+
Guest communication with Hyper-V
169
+
--------------------------------
170
+
Separate from the generic Linux kernel handling of memory encryption in Linux
171
+
CoCo VMs, Hyper-V has VMBus and VMBus devices that communicate using memory
172
+
shared between the Linux guest and the host. This shared memory must be
173
+
marked decrypted to enable communication. Furthermore, since the threat model
174
+
includes a compromised and potentially malicious host, the guest must guard
175
+
against leaking any unintended data to the host through this shared memory.
176
+
177
+
These Hyper-V and VMBus memory pages are marked as decrypted:
178
+
179
+
* VMBus monitor pages
180
+
181
+
* Synthetic interrupt controller (synic) related pages (unless supplied by
182
+
the paravisor)
183
+
184
+
* Per-cpu hypercall input and output pages (unless running with a paravisor)
185
+
186
+
* VMBus ring buffers. The direct mapping is marked decrypted in
187
+
__vmbus_establish_gpadl(). The secondary mapping created in
188
+
hv_ringbuffer_init() must also include the "decrypted" attribute.
189
+
190
+
When the guest writes data to memory that is shared with the host, it must
191
+
ensure that only the intended data is written. Padding or unused fields must
192
+
be initialized to zeros before copying into the shared memory so that random
193
+
kernel data is not inadvertently given to the host.
194
+
195
+
Similarly, when the guest reads memory that is shared with the host, it must
196
+
validate the data before acting on it so that a malicious host cannot induce
197
+
the guest to expose unintended data. Doing such validation can be tricky
198
+
because the host can modify the shared memory areas even while or after
199
+
validation is performed. For messages passed from the host to the guest in a
200
+
VMBus ring buffer, the length of the message is validated, and the message is
201
+
copied into a temporary (encrypted) buffer for further validation and
202
+
processing. The copying adds a small amount of overhead, but is the only way
203
+
to protect against a malicious host. See hv_pkt_iter_first().
204
+
205
+
Many drivers for VMBus devices have been "hardened" by adding code to fully
206
+
validate messages received over VMBus, instead of assuming that Hyper-V is
207
+
acting cooperatively. Such drivers are marked as "allowed_in_isolated" in the
208
+
vmbus_devs[] table. Other drivers for VMBus devices that are not needed in a
209
+
CoCo VM have not been hardened, and they are not allowed to load in a CoCo
210
+
VM. See vmbus_is_valid_offer() where such devices are excluded.
211
+
212
+
Two VMBus devices depend on the Hyper-V host to do DMA data transfers:
213
+
storvsc for disk I/O and netvsc for network I/O. storvsc uses the normal
214
+
Linux kernel DMA APIs, and so bounce buffering through decrypted swiotlb
215
+
memory is done implicitly. netvsc has two modes for data transfers. The first
216
+
mode goes through send and receive buffer space that is explicitly allocated
217
+
by the netvsc driver, and is used for most smaller packets. These send and
218
+
receive buffers are marked decrypted by __vmbus_establish_gpadl(). Because
219
+
the netvsc driver explicitly copies packets to/from these buffers, the
220
+
equivalent of bounce buffering between encrypted and decrypted memory is
221
+
already part of the data path. The second mode uses the normal Linux kernel
222
+
DMA APIs, and is bounce buffered through swiotlb memory implicitly like in
223
+
storvsc.
224
+
225
+
Finally, the VMBus virtual PCI driver needs special handling in a CoCo VM.
226
+
Linux PCI device drivers access PCI config space using standard APIs provided
227
+
by the Linux PCI subsystem. On Hyper-V, these functions directly access MMIO
228
+
space, and the access traps to Hyper-V for emulation. But in CoCo VMs, memory
229
+
encryption prevents Hyper-V from reading the guest instruction stream to
230
+
emulate the access. So in a CoCo VM, these functions must make a hypercall
231
+
with arguments explicitly describing the access. See
232
+
_hv_pcifront_read_config() and _hv_pcifront_write_config() and the
233
+
"use_calls" flag indicating to use hypercalls.
234
+
235
+
load_unaligned_zeropad()
236
+
------------------------
237
+
When transitioning memory between encrypted and decrypted, the caller of
238
+
set_memory_encrypted() or set_memory_decrypted() is responsible for ensuring
239
+
the memory isn't in use and isn't referenced while the transition is in
240
+
progress. The transition has multiple steps, and includes interaction with
241
+
the Hyper-V host. The memory is in an inconsistent state until all steps are
242
+
complete. A reference while the state is inconsistent could result in an
243
+
exception that can't be cleanly fixed up.
244
+
245
+
However, the kernel load_unaligned_zeropad() mechanism may make stray
246
+
references that can't be prevented by the caller of set_memory_encrypted() or
247
+
set_memory_decrypted(), so there's specific code in the #VC or #VE exception
248
+
handler to fixup this case. But a CoCo VM running on Hyper-V may be
249
+
configured to run with a paravisor, with the #VC or #VE exception routed to
250
+
the paravisor. There's no architectural way to forward the exceptions back to
251
+
the guest kernel, and in such a case, the load_unaligned_zeropad() fixup code
252
+
in the #VC/#VE handlers doesn't run.
253
+
254
+
To avoid this problem, the Hyper-V specific functions for notifying the
255
+
hypervisor of the transition mark pages as "not present" while a transition
256
+
is in progress. If load_unaligned_zeropad() causes a stray reference, a
257
+
normal page fault is generated instead of #VC or #VE, and the page-fault-
258
+
based handlers for load_unaligned_zeropad() fixup the reference. When the
259
+
encrypted/decrypted transition is complete, the pages are marked as "present"
260
+
again. See hv_vtom_clear_present() and hv_vtom_set_host_visibility().
+2
-1
MAINTAINERS
+2
-1
MAINTAINERS
···
7466
7466
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
7467
7467
F: Documentation/devicetree/bindings/display/bridge/
7468
7468
F: drivers/gpu/drm/bridge/
7469
+
F: drivers/gpu/drm/display/drm_bridge_connector.c
7469
7470
F: drivers/gpu/drm/drm_bridge.c
7470
-
F: drivers/gpu/drm/drm_bridge_connector.c
7471
7471
F: include/drm/drm_bridge.h
7472
7472
F: include/drm/drm_bridge_connector.h
7473
7473
···
18434
18434
S: Maintained
18435
18435
F: Documentation/devicetree/bindings/net/pse-pd/
18436
18436
F: drivers/net/pse-pd/
18437
+
F: net/ethtool/pse-pd.c
18437
18438
18438
18439
PSTORE FILESYSTEM
18439
18440
M: Kees Cook <kees@kernel.org>
+1
-1
Makefile
+1
-1
Makefile
+1
-1
arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
+33
-3
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+33
-3
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
···
154
154
};
155
155
};
156
156
157
+
&gpio3 {
158
+
/*
159
+
* The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
160
+
* eMMC and SPI flash powered-down initially (in fact it keeps the
161
+
* reset signal asserted). BIOS_DISABLE_OVERRIDE pin allows to override
162
+
* that signal so that eMMC and SPI can be used regardless of the state
163
+
* of the signal.
164
+
*/
165
+
bios-disable-override-hog {
166
+
gpios = <RK_PD5 GPIO_ACTIVE_LOW>;
167
+
gpio-hog;
168
+
line-name = "bios_disable_override";
169
+
output-high;
170
+
};
171
+
};
172
+
157
173
&gmac {
158
174
assigned-clocks = <&cru SCLK_RMII_SRC>;
159
175
assigned-clock-parents = <&clkin_gmac>;
···
425
409
426
410
&i2s0 {
427
411
pinctrl-0 = <&i2s0_2ch_bus>;
412
+
pinctrl-1 = <&i2s0_2ch_bus_bclk_off>;
428
413
rockchip,playback-channels = <2>;
429
414
rockchip,capture-channels = <2>;
430
415
status = "okay";
···
434
417
/*
435
418
* As Q7 does not specify neither a global nor a RX clock for I2S these
436
419
* signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO.
437
-
* Therefore we have to redefine the i2s0_2ch_bus definition to prevent
438
-
* conflicts.
420
+
* Therefore we have to redefine the i2s0_2ch_bus and i2s0_2ch_bus_bclk_off
421
+
* definitions to prevent conflicts.
439
422
*/
440
423
&i2s0_2ch_bus {
441
424
rockchip,pins =
442
425
<3 RK_PD0 1 &pcfg_pull_none>,
426
+
<3 RK_PD2 1 &pcfg_pull_none>,
427
+
<3 RK_PD3 1 &pcfg_pull_none>,
428
+
<3 RK_PD7 1 &pcfg_pull_none>;
429
+
};
430
+
431
+
&i2s0_2ch_bus_bclk_off {
432
+
rockchip,pins =
433
+
<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
443
434
<3 RK_PD2 1 &pcfg_pull_none>,
444
435
<3 RK_PD3 1 &pcfg_pull_none>,
445
436
<3 RK_PD7 1 &pcfg_pull_none>;
···
474
449
475
450
&pinctrl {
476
451
pinctrl-names = "default";
477
-
pinctrl-0 = <&q7_thermal_pin>;
452
+
pinctrl-0 = <&q7_thermal_pin &bios_disable_override_hog_pin>;
478
453
479
454
gpios {
455
+
bios_disable_override_hog_pin: bios-disable-override-hog-pin {
456
+
rockchip,pins =
457
+
<3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
458
+
};
459
+
480
460
q7_thermal_pin: q7-thermal-pin {
481
461
rockchip,pins =
482
462
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+3
-4
arch/arm64/boot/dts/rockchip/rk356x.dtsi
+3
-4
arch/arm64/boot/dts/rockchip/rk356x.dtsi
···
1592
1592
<&cru SRST_TSADCPHY>;
1593
1593
rockchip,grf = <&grf>;
1594
1594
rockchip,hw-tshut-temp = <95000>;
1595
-
pinctrl-names = "init", "default", "sleep";
1596
-
pinctrl-0 = <&tsadc_pin>;
1597
-
pinctrl-1 = <&tsadc_shutorg>;
1598
-
pinctrl-2 = <&tsadc_pin>;
1595
+
pinctrl-names = "default", "sleep";
1596
+
pinctrl-0 = <&tsadc_shutorg>;
1597
+
pinctrl-1 = <&tsadc_pin>;
1599
1598
#thermal-sensor-cells = <1>;
1600
1599
status = "disabled";
1601
1600
};
+3
-3
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+3
-3
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
···
582
582
};
583
583
584
584
vo0_grf: syscon@fd5a6000 {
585
-
compatible = "rockchip,rk3588-vo-grf", "syscon";
585
+
compatible = "rockchip,rk3588-vo0-grf", "syscon";
586
586
reg = <0x0 0xfd5a6000 0x0 0x2000>;
587
587
clocks = <&cru PCLK_VO0GRF>;
588
588
};
589
589
590
590
vo1_grf: syscon@fd5a8000 {
591
-
compatible = "rockchip,rk3588-vo-grf", "syscon";
592
-
reg = <0x0 0xfd5a8000 0x0 0x100>;
591
+
compatible = "rockchip,rk3588-vo1-grf", "syscon";
592
+
reg = <0x0 0xfd5a8000 0x0 0x4000>;
593
593
clocks = <&cru PCLK_VO1GRF>;
594
594
};
595
595
+3
-1
arch/arm64/kernel/stacktrace.c
+3
-1
arch/arm64/kernel/stacktrace.c
···
25
25
*
26
26
* @common: Common unwind state.
27
27
* @task: The task being unwound.
28
+
* @graph_idx: Used by ftrace_graph_ret_addr() for optimized stack unwinding.
28
29
* @kr_cur: When KRETPROBES is selected, holds the kretprobe instance
29
30
* associated with the most recently encountered replacement lr
30
31
* value.
···
33
32
struct kunwind_state {
34
33
struct unwind_state common;
35
34
struct task_struct *task;
35
+
int graph_idx;
36
36
#ifdef CONFIG_KRETPROBES
37
37
struct llist_node *kr_cur;
38
38
#endif
···
108
106
if (state->task->ret_stack &&
109
107
(state->common.pc == (unsigned long)return_to_handler)) {
110
108
unsigned long orig_pc;
111
-
orig_pc = ftrace_graph_ret_addr(state->task, NULL,
109
+
orig_pc = ftrace_graph_ret_addr(state->task, &state->graph_idx,
112
110
state->common.pc,
113
111
(void *)state->common.fp);
114
112
if (WARN_ON_ONCE(state->common.pc == orig_pc))
+2
-2
arch/powerpc/include/asm/nohash/32/pgtable.h
+2
-2
arch/powerpc/include/asm/nohash/32/pgtable.h
···
52
52
#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
53
53
54
54
#define pgd_ERROR(e) \
55
-
pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
55
+
pr_err("%s:%d: bad pgd %08llx.\n", __FILE__, __LINE__, (unsigned long long)pgd_val(e))
56
56
57
57
/*
58
58
* This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
···
170
170
#define pmd_pfn(pmd) (pmd_val(pmd) >> PAGE_SHIFT)
171
171
#else
172
172
#define pmd_page_vaddr(pmd) \
173
-
((const void *)(pmd_val(pmd) & ~(PTE_TABLE_SIZE - 1)))
173
+
((const void *)((unsigned long)pmd_val(pmd) & ~(PTE_TABLE_SIZE - 1)))
174
174
#define pmd_pfn(pmd) (__pa(pmd_val(pmd)) >> PAGE_SHIFT)
175
175
#endif
176
176
+9
-3
arch/powerpc/include/asm/pgtable-types.h
+9
-3
arch/powerpc/include/asm/pgtable-types.h
···
49
49
#endif /* CONFIG_PPC64 */
50
50
51
51
/* PGD level */
52
-
#if defined(CONFIG_PPC_E500) && defined(CONFIG_PTE_64BIT)
52
+
#if defined(CONFIG_PPC_85xx) && defined(CONFIG_PTE_64BIT)
53
53
typedef struct { unsigned long long pgd; } pgd_t;
54
+
55
+
static inline unsigned long long pgd_val(pgd_t x)
56
+
{
57
+
return x.pgd;
58
+
}
54
59
#else
55
60
typedef struct { unsigned long pgd; } pgd_t;
56
-
#endif
57
-
#define __pgd(x) ((pgd_t) { (x) })
61
+
58
62
static inline unsigned long pgd_val(pgd_t x)
59
63
{
60
64
return x.pgd;
61
65
}
66
+
#endif
67
+
#define __pgd(x) ((pgd_t) { (x) })
62
68
63
69
/* Page protection bits */
64
70
typedef struct { unsigned long pgprot; } pgprot_t;
+3
-1
arch/powerpc/kernel/vdso/vdso32.lds.S
+3
-1
arch/powerpc/kernel/vdso/vdso32.lds.S
···
74
74
.got : { *(.got) } :text
75
75
.plt : { *(.plt) }
76
76
77
+
.rela.dyn : { *(.rela .rela*) }
78
+
77
79
_end = .;
78
80
__end = .;
79
81
PROVIDE(end = .);
···
89
87
*(.branch_lt)
90
88
*(.data .data.* .gnu.linkonce.d.* .sdata*)
91
89
*(.bss .sbss .dynbss .dynsbss)
92
-
*(.got1 .glink .iplt .rela*)
90
+
*(.got1 .glink .iplt)
93
91
}
94
92
}
95
93
+2
-2
arch/powerpc/kernel/vdso/vdso64.lds.S
+2
-2
arch/powerpc/kernel/vdso/vdso64.lds.S
···
69
69
.eh_frame_hdr : { *(.eh_frame_hdr) } :text :eh_frame_hdr
70
70
.eh_frame : { KEEP (*(.eh_frame)) } :text
71
71
.gcc_except_table : { *(.gcc_except_table) }
72
-
.rela.dyn ALIGN(8) : { *(.rela.dyn) }
72
+
.rela.dyn ALIGN(8) : { *(.rela .rela*) }
73
73
74
74
.got ALIGN(8) : { *(.got .toc) }
75
75
···
86
86
*(.data .data.* .gnu.linkonce.d.* .sdata*)
87
87
*(.bss .sbss .dynbss .dynsbss)
88
88
*(.opd)
89
-
*(.glink .iplt .plt .rela*)
89
+
*(.glink .iplt .plt)
90
90
}
91
91
}
92
92
+9
-1
arch/powerpc/lib/qspinlock.c
+9
-1
arch/powerpc/lib/qspinlock.c
···
697
697
}
698
698
699
699
release:
700
-
qnodesp->count--; /* release the node */
700
+
/*
701
+
* Clear the lock before releasing the node, as another CPU might see stale
702
+
* values if an interrupt occurs after we increment qnodesp->count
703
+
* but before node->lock is initialized. The barrier ensures that
704
+
* there are no further stores to the node after it has been released.
705
+
*/
706
+
node->lock = NULL;
707
+
barrier();
708
+
qnodesp->count--;
701
709
}
702
710
703
711
void queued_spin_lock_slowpath(struct qspinlock *lock)
+1
-1
arch/powerpc/mm/nohash/tlb_64e.c
+1
-1
arch/powerpc/mm/nohash/tlb_64e.c
···
33
33
* though this will probably be made common with other nohash
34
34
* implementations at some point
35
35
*/
36
-
int mmu_pte_psize; /* Page size used for PTE pages */
36
+
static int mmu_pte_psize; /* Page size used for PTE pages */
37
37
int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
38
38
int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */
39
39
unsigned long linear_map_top; /* Top of linear mapping */
+2
-2
arch/riscv/Kconfig
+2
-2
arch/riscv/Kconfig
···
552
552
config TOOLCHAIN_HAS_V
553
553
bool
554
554
default y
555
-
depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64iv)
556
-
depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32iv)
555
+
depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64imv)
556
+
depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32imv)
557
557
depends on LLD_VERSION >= 140000 || LD_VERSION >= 23800
558
558
depends on AS_HAS_OPTION_ARCH
559
559
+6
arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+6
arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+2
-24
arch/riscv/include/asm/processor.h
+2
-24
arch/riscv/include/asm/processor.h
···
14
14
15
15
#include <asm/ptrace.h>
16
16
17
-
/*
18
-
* addr is a hint to the maximum userspace address that mmap should provide, so
19
-
* this macro needs to return the largest address space available so that
20
-
* mmap_end < addr, being mmap_end the top of that address space.
21
-
* See Documentation/arch/riscv/vm-layout.rst for more details.
22
-
*/
23
17
#define arch_get_mmap_end(addr, len, flags) \
24
18
({ \
25
-
unsigned long mmap_end; \
26
-
typeof(addr) _addr = (addr); \
27
-
if ((_addr) == 0 || is_compat_task() || \
28
-
((_addr + len) > BIT(VA_BITS - 1))) \
29
-
mmap_end = STACK_TOP_MAX; \
30
-
else \
31
-
mmap_end = (_addr + len); \
32
-
mmap_end; \
19
+
STACK_TOP_MAX; \
33
20
})
34
21
35
22
#define arch_get_mmap_base(addr, base) \
36
23
({ \
37
-
unsigned long mmap_base; \
38
-
typeof(addr) _addr = (addr); \
39
-
typeof(base) _base = (base); \
40
-
unsigned long rnd_gap = DEFAULT_MAP_WINDOW - (_base); \
41
-
if ((_addr) == 0 || is_compat_task() || \
42
-
((_addr + len) > BIT(VA_BITS - 1))) \
43
-
mmap_base = (_base); \
44
-
else \
45
-
mmap_base = (_addr + len) - rnd_gap; \
46
-
mmap_base; \
24
+
base; \
47
25
})
48
26
49
27
#ifdef CONFIG_64BIT
+19
-1
arch/riscv/include/asm/sbi.h
+19
-1
arch/riscv/include/asm/sbi.h
···
9
9
10
10
#include <linux/types.h>
11
11
#include <linux/cpumask.h>
12
+
#include <linux/jump_label.h>
12
13
13
14
#ifdef CONFIG_RISCV_SBI
14
15
enum sbi_ext_id {
···
305
304
};
306
305
307
306
void sbi_init(void);
307
+
long __sbi_base_ecall(int fid);
308
308
struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
309
309
unsigned long arg2, unsigned long arg3,
310
310
unsigned long arg4, unsigned long arg5,
···
375
373
| (minor & SBI_SPEC_VERSION_MINOR_MASK);
376
374
}
377
375
378
-
int sbi_err_map_linux_errno(int err);
376
+
static inline int sbi_err_map_linux_errno(int err)
377
+
{
378
+
switch (err) {
379
+
case SBI_SUCCESS:
380
+
return 0;
381
+
case SBI_ERR_DENIED:
382
+
return -EPERM;
383
+
case SBI_ERR_INVALID_PARAM:
384
+
return -EINVAL;
385
+
case SBI_ERR_INVALID_ADDRESS:
386
+
return -EFAULT;
387
+
case SBI_ERR_NOT_SUPPORTED:
388
+
case SBI_ERR_FAILURE:
389
+
default:
390
+
return -ENOTSUPP;
391
+
};
392
+
}
379
393
380
394
extern bool sbi_debug_console_available;
381
395
int sbi_debug_console_write(const char *bytes, unsigned int num_bytes);
+5
-1
arch/riscv/kernel/Makefile
+5
-1
arch/riscv/kernel/Makefile
···
20
20
ifdef CONFIG_RISCV_ALTERNATIVE_EARLY
21
21
CFLAGS_alternative.o := -mcmodel=medany
22
22
CFLAGS_cpufeature.o := -mcmodel=medany
23
+
CFLAGS_sbi_ecall.o := -mcmodel=medany
23
24
ifdef CONFIG_FTRACE
24
25
CFLAGS_REMOVE_alternative.o = $(CC_FLAGS_FTRACE)
25
26
CFLAGS_REMOVE_cpufeature.o = $(CC_FLAGS_FTRACE)
27
+
CFLAGS_REMOVE_sbi_ecall.o = $(CC_FLAGS_FTRACE)
26
28
endif
27
29
ifdef CONFIG_RELOCATABLE
28
30
CFLAGS_alternative.o += -fno-pie
29
31
CFLAGS_cpufeature.o += -fno-pie
32
+
CFLAGS_sbi_ecall.o += -fno-pie
30
33
endif
31
34
ifdef CONFIG_KASAN
32
35
KASAN_SANITIZE_alternative.o := n
33
36
KASAN_SANITIZE_cpufeature.o := n
37
+
KASAN_SANITIZE_sbi_ecall.o := n
34
38
endif
35
39
endif
36
40
···
92
88
93
89
obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
94
90
obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o
95
-
obj-$(CONFIG_RISCV_SBI) += sbi.o
91
+
obj-$(CONFIG_RISCV_SBI) += sbi.o sbi_ecall.o
96
92
ifeq ($(CONFIG_RISCV_SBI), y)
97
93
obj-$(CONFIG_SMP) += sbi-ipi.o
98
94
obj-$(CONFIG_SMP) += cpu_ops_sbi.o
-63
arch/riscv/kernel/sbi.c
-63
arch/riscv/kernel/sbi.c
···
14
14
#include <asm/smp.h>
15
15
#include <asm/tlbflush.h>
16
16
17
-
#define CREATE_TRACE_POINTS
18
-
#include <asm/trace.h>
19
-
20
17
/* default SBI version is 0.1 */
21
18
unsigned long sbi_spec_version __ro_after_init = SBI_SPEC_VERSION_DEFAULT;
22
19
EXPORT_SYMBOL(sbi_spec_version);
···
23
26
static int (*__sbi_rfence)(int fid, const struct cpumask *cpu_mask,
24
27
unsigned long start, unsigned long size,
25
28
unsigned long arg4, unsigned long arg5) __ro_after_init;
26
-
27
-
struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
28
-
unsigned long arg2, unsigned long arg3,
29
-
unsigned long arg4, unsigned long arg5,
30
-
int fid, int ext)
31
-
{
32
-
struct sbiret ret;
33
-
34
-
trace_sbi_call(ext, fid);
35
-
36
-
register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
37
-
register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
38
-
register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
39
-
register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
40
-
register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
41
-
register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
42
-
register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
43
-
register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
44
-
asm volatile ("ecall"
45
-
: "+r" (a0), "+r" (a1)
46
-
: "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
47
-
: "memory");
48
-
ret.error = a0;
49
-
ret.value = a1;
50
-
51
-
trace_sbi_return(ext, ret.error, ret.value);
52
-
53
-
return ret;
54
-
}
55
-
EXPORT_SYMBOL(__sbi_ecall);
56
-
57
-
int sbi_err_map_linux_errno(int err)
58
-
{
59
-
switch (err) {
60
-
case SBI_SUCCESS:
61
-
return 0;
62
-
case SBI_ERR_DENIED:
63
-
return -EPERM;
64
-
case SBI_ERR_INVALID_PARAM:
65
-
return -EINVAL;
66
-
case SBI_ERR_INVALID_ADDRESS:
67
-
return -EFAULT;
68
-
case SBI_ERR_NOT_SUPPORTED:
69
-
case SBI_ERR_FAILURE:
70
-
default:
71
-
return -ENOTSUPP;
72
-
};
73
-
}
74
-
EXPORT_SYMBOL(sbi_err_map_linux_errno);
75
29
76
30
#ifdef CONFIG_RISCV_SBI_V01
77
31
static unsigned long __sbi_v01_cpumask_to_hartmask(const struct cpumask *cpu_mask)
···
482
534
return 0;
483
535
}
484
536
EXPORT_SYMBOL(sbi_probe_extension);
485
-
486
-
static long __sbi_base_ecall(int fid)
487
-
{
488
-
struct sbiret ret;
489
-
490
-
ret = sbi_ecall(SBI_EXT_BASE, fid, 0, 0, 0, 0, 0, 0);
491
-
if (!ret.error)
492
-
return ret.value;
493
-
else
494
-
return sbi_err_map_linux_errno(ret.error);
495
-
}
496
537
497
538
static inline long sbi_get_spec_version(void)
498
539
{
+48
arch/riscv/kernel/sbi_ecall.c
+48
arch/riscv/kernel/sbi_ecall.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/* Copyright (c) 2024 Rivos Inc. */
3
+
4
+
#include <asm/sbi.h>
5
+
#define CREATE_TRACE_POINTS
6
+
#include <asm/trace.h>
7
+
8
+
long __sbi_base_ecall(int fid)
9
+
{
10
+
struct sbiret ret;
11
+
12
+
ret = sbi_ecall(SBI_EXT_BASE, fid, 0, 0, 0, 0, 0, 0);
13
+
if (!ret.error)
14
+
return ret.value;
15
+
else
16
+
return sbi_err_map_linux_errno(ret.error);
17
+
}
18
+
EXPORT_SYMBOL(__sbi_base_ecall);
19
+
20
+
struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
21
+
unsigned long arg2, unsigned long arg3,
22
+
unsigned long arg4, unsigned long arg5,
23
+
int fid, int ext)
24
+
{
25
+
struct sbiret ret;
26
+
27
+
trace_sbi_call(ext, fid);
28
+
29
+
register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
30
+
register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
31
+
register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
32
+
register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
33
+
register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
34
+
register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
35
+
register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
36
+
register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
37
+
asm volatile ("ecall"
38
+
: "+r" (a0), "+r" (a1)
39
+
: "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
40
+
: "memory");
41
+
ret.error = a0;
42
+
ret.value = a1;
43
+
44
+
trace_sbi_return(ext, ret.error, ret.value);
45
+
46
+
return ret;
47
+
}
48
+
EXPORT_SYMBOL(__sbi_ecall);
+2
-2
arch/riscv/kernel/traps_misaligned.c
+2
-2
arch/riscv/kernel/traps_misaligned.c
···
417
417
418
418
val.data_u64 = 0;
419
419
if (user_mode(regs)) {
420
-
if (raw_copy_from_user(&val, (u8 __user *)addr, len))
420
+
if (copy_from_user(&val, (u8 __user *)addr, len))
421
421
return -1;
422
422
} else {
423
423
memcpy(&val, (u8 *)addr, len);
···
515
515
return -EOPNOTSUPP;
516
516
517
517
if (user_mode(regs)) {
518
-
if (raw_copy_to_user((u8 __user *)addr, &val, len))
518
+
if (copy_to_user((u8 __user *)addr, &val, len))
519
519
return -1;
520
520
} else {
521
521
memcpy((u8 *)addr, &val, len);
+1
-1
arch/riscv/mm/init.c
+1
-1
arch/riscv/mm/init.c
···
252
252
* The size of the linear page mapping may restrict the amount of
253
253
* usable RAM.
254
254
*/
255
-
if (IS_ENABLED(CONFIG_64BIT)) {
255
+
if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU)) {
256
256
max_mapped_addr = __pa(PAGE_OFFSET) + KERN_VIRT_SIZE;
257
257
memblock_cap_memory_range(phys_ram_base,
258
258
max_mapped_addr - phys_ram_base);
+1
-4
arch/x86/hyperv/hv_init.c
+1
-4
arch/x86/hyperv/hv_init.c
···
35
35
#include <clocksource/hyperv_timer.h>
36
36
#include <linux/highmem.h>
37
37
38
-
int hyperv_init_cpuhp;
39
38
u64 hv_current_partition_id = ~0ull;
40
39
EXPORT_SYMBOL_GPL(hv_current_partition_id);
41
40
···
606
607
607
608
register_syscore_ops(&hv_syscore_ops);
608
609
609
-
hyperv_init_cpuhp = cpuhp;
610
-
611
610
if (cpuid_ebx(HYPERV_CPUID_FEATURES) & HV_ACCESS_PARTITION_ID)
612
611
hv_get_partition_id();
613
612
···
634
637
clean_guest_os_id:
635
638
wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0);
636
639
hv_ivm_msr_write(HV_X64_MSR_GUEST_OS_ID, 0);
637
-
cpuhp_remove_state(cpuhp);
640
+
cpuhp_remove_state(CPUHP_AP_HYPERV_ONLINE);
638
641
free_ghcb_page:
639
642
free_percpu(hv_ghcb_pg);
640
643
free_vp_assist_page:
-1
arch/x86/include/asm/mshyperv.h
-1
arch/x86/include/asm/mshyperv.h
+18
-3
arch/x86/kernel/cpu/mshyperv.c
+18
-3
arch/x86/kernel/cpu/mshyperv.c
···
199
199
* Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor
200
200
* corrupts the old VP Assist Pages and can crash the kexec kernel.
201
201
*/
202
-
if (kexec_in_progress && hyperv_init_cpuhp > 0)
203
-
cpuhp_remove_state(hyperv_init_cpuhp);
202
+
if (kexec_in_progress)
203
+
cpuhp_remove_state(CPUHP_AP_HYPERV_ONLINE);
204
204
205
205
/* The function calls stop_other_cpus(). */
206
206
native_machine_shutdown();
···
424
424
ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
425
425
x86_platform.calibrate_tsc = hv_get_tsc_khz;
426
426
x86_platform.calibrate_cpu = hv_get_tsc_khz;
427
+
setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
427
428
}
428
429
429
430
if (ms_hyperv.priv_high & HV_ISOLATION) {
···
450
449
ms_hyperv.hints &= ~HV_X64_APIC_ACCESS_RECOMMENDED;
451
450
452
451
if (!ms_hyperv.paravisor_present) {
453
-
/* To be supported: more work is required. */
452
+
/*
453
+
* Mark the Hyper-V TSC page feature as disabled
454
+
* in a TDX VM without paravisor so that the
455
+
* Invariant TSC, which is a better clocksource
456
+
* anyway, is used instead.
457
+
*/
454
458
ms_hyperv.features &= ~HV_MSR_REFERENCE_TSC_AVAILABLE;
459
+
460
+
/*
461
+
* The Invariant TSC is expected to be available
462
+
* in a TDX VM without paravisor, but if not,
463
+
* print a warning message. The slower Hyper-V MSR-based
464
+
* Ref Counter should end up being the clocksource.
465
+
*/
466
+
if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT))
467
+
pr_warn("Hyper-V: Invariant TSC is unavailable\n");
455
468
456
469
/* HV_MSR_CRASH_CTL is unsupported. */
457
470
ms_hyperv.misc_features &= ~HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE;
+4
-3
arch/x86/kvm/Kconfig
+4
-3
arch/x86/kvm/Kconfig
···
19
19
20
20
config KVM
21
21
tristate "Kernel-based Virtual Machine (KVM) support"
22
-
depends on HIGH_RES_TIMERS
23
22
depends on X86_LOCAL_APIC
24
23
select KVM_COMMON
25
24
select KVM_GENERIC_MMU_NOTIFIER
···
143
144
select HAVE_KVM_ARCH_GMEM_PREPARE
144
145
select HAVE_KVM_ARCH_GMEM_INVALIDATE
145
146
help
146
-
Provides support for launching Encrypted VMs (SEV) and Encrypted VMs
147
-
with Encrypted State (SEV-ES) on AMD processors.
147
+
Provides support for launching encrypted VMs which use Secure
148
+
Encrypted Virtualization (SEV), Secure Encrypted Virtualization with
149
+
Encrypted State (SEV-ES), and Secure Encrypted Virtualization with
150
+
Secure Nested Paging (SEV-SNP) technologies on AMD processors.
148
151
149
152
config KVM_SMM
150
153
bool "System Management Mode emulation"
+3
-1
arch/x86/kvm/mmu/mmu.c
+3
-1
arch/x86/kvm/mmu/mmu.c
···
4750
4750
* reload is efficient when called repeatedly, so we can do it on
4751
4751
* every iteration.
4752
4752
*/
4753
-
kvm_mmu_reload(vcpu);
4753
+
r = kvm_mmu_reload(vcpu);
4754
+
if (r)
4755
+
return r;
4754
4756
4755
4757
if (kvm_arch_has_private_mem(vcpu->kvm) &&
4756
4758
kvm_mem_is_private(vcpu->kvm, gpa_to_gfn(range->gpa)))
+3
-3
arch/x86/kvm/mmu/spte.c
+3
-3
arch/x86/kvm/mmu/spte.c
···
391
391
mmio_value = 0;
392
392
393
393
/*
394
-
* The masked MMIO value must obviously match itself and a removed SPTE
395
-
* must not get a false positive. Removed SPTEs and MMIO SPTEs should
396
-
* never collide as MMIO must set some RWX bits, and removed SPTEs must
394
+
* The masked MMIO value must obviously match itself and a frozen SPTE
395
+
* must not get a false positive. Frozen SPTEs and MMIO SPTEs should
396
+
* never collide as MMIO must set some RWX bits, and frozen SPTEs must
397
397
* not set any RWX bits.
398
398
*/
399
399
if (WARN_ON((mmio_value & mmio_mask) != mmio_value) ||
+1
-1
arch/x86/kvm/mmu/spte.h
+1
-1
arch/x86/kvm/mmu/spte.h
···
214
214
*/
215
215
#define FROZEN_SPTE (SHADOW_NONPRESENT_VALUE | 0x5a0ULL)
216
216
217
-
/* Removed SPTEs must not be misconstrued as shadow present PTEs. */
217
+
/* Frozen SPTEs must not be misconstrued as shadow present PTEs. */
218
218
static_assert(!(FROZEN_SPTE & SPTE_MMU_PRESENT_MASK));
219
219
220
220
static inline bool is_frozen_spte(u64 spte)
+4
-4
arch/x86/kvm/mmu/tdp_mmu.c
+4
-4
arch/x86/kvm/mmu/tdp_mmu.c
···
359
359
/*
360
360
* Set the SPTE to a nonpresent value that other
361
361
* threads will not overwrite. If the SPTE was
362
-
* already marked as removed then another thread
362
+
* already marked as frozen then another thread
363
363
* handling a page fault could overwrite it, so
364
364
* set the SPTE until it is set from some other
365
-
* value to the removed SPTE value.
365
+
* value to the frozen SPTE value.
366
366
*/
367
367
for (;;) {
368
368
old_spte = kvm_tdp_mmu_write_spte_atomic(sptep, FROZEN_SPTE);
···
536
536
u64 *sptep = rcu_dereference(iter->sptep);
537
537
538
538
/*
539
-
* The caller is responsible for ensuring the old SPTE is not a REMOVED
540
-
* SPTE. KVM should never attempt to zap or manipulate a REMOVED SPTE,
539
+
* The caller is responsible for ensuring the old SPTE is not a FROZEN
540
+
* SPTE. KVM should never attempt to zap or manipulate a FROZEN SPTE,
541
541
* and pre-checking before inserting a new SPTE is advantageous as it
542
542
* avoids unnecessary work.
543
543
*/
+15
arch/x86/kvm/svm/svm.c
+15
arch/x86/kvm/svm/svm.c
···
2876
2876
case MSR_CSTAR:
2877
2877
msr_info->data = svm->vmcb01.ptr->save.cstar;
2878
2878
break;
2879
+
case MSR_GS_BASE:
2880
+
msr_info->data = svm->vmcb01.ptr->save.gs.base;
2881
+
break;
2882
+
case MSR_FS_BASE:
2883
+
msr_info->data = svm->vmcb01.ptr->save.fs.base;
2884
+
break;
2879
2885
case MSR_KERNEL_GS_BASE:
2880
2886
msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2881
2887
break;
···
3106
3100
break;
3107
3101
case MSR_CSTAR:
3108
3102
svm->vmcb01.ptr->save.cstar = data;
3103
+
break;
3104
+
case MSR_GS_BASE:
3105
+
svm->vmcb01.ptr->save.gs.base = data;
3106
+
break;
3107
+
case MSR_FS_BASE:
3108
+
svm->vmcb01.ptr->save.fs.base = data;
3109
3109
break;
3110
3110
case MSR_KERNEL_GS_BASE:
3111
3111
svm->vmcb01.ptr->save.kernel_gs_base = data;
···
5236
5224
5237
5225
/* CPUID 0x8000001F (SME/SEV features) */
5238
5226
sev_set_cpu_caps();
5227
+
5228
+
/* Don't advertise Bus Lock Detect to guest if SVM support is absent */
5229
+
kvm_cpu_cap_clear(X86_FEATURE_BUS_LOCK_DETECT);
5239
5230
}
5240
5231
5241
5232
static __init int svm_hardware_setup(void)
+5
-1
arch/x86/kvm/x86.c
+5
-1
arch/x86/kvm/x86.c
···
4656
4656
case KVM_CAP_ASYNC_PF_INT:
4657
4657
case KVM_CAP_GET_TSC_KHZ:
4658
4658
case KVM_CAP_KVMCLOCK_CTRL:
4659
-
case KVM_CAP_READONLY_MEM:
4660
4659
case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4661
4660
case KVM_CAP_TSC_DEADLINE_TIMER:
4662
4661
case KVM_CAP_DISABLE_QUIRKS:
···
4813
4814
break;
4814
4815
case KVM_CAP_VM_TYPES:
4815
4816
r = kvm_caps.supported_vm_types;
4817
+
break;
4818
+
case KVM_CAP_READONLY_MEM:
4819
+
r = kvm ? kvm_arch_has_readonly_mem(kvm) : 1;
4816
4820
break;
4817
4821
default:
4818
4822
break;
···
6042
6040
if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
6043
6041
break;
6044
6042
6043
+
kvm_vcpu_srcu_read_lock(vcpu);
6045
6044
r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
6045
+
kvm_vcpu_srcu_read_unlock(vcpu);
6046
6046
break;
6047
6047
}
6048
6048
case KVM_GET_DEBUGREGS: {
-4
block/bio-integrity.c
-4
block/bio-integrity.c
···
167
167
struct request_queue *q = bdev_get_queue(bio->bi_bdev);
168
168
struct bio_integrity_payload *bip = bio_integrity(bio);
169
169
170
-
if (((bip->bip_iter.bi_size + len) >> SECTOR_SHIFT) >
171
-
queue_max_hw_sectors(q))
172
-
return 0;
173
-
174
170
if (bip->bip_vcnt > 0) {
175
171
struct bio_vec *bv = &bip->bip_vec[bip->bip_vcnt - 1];
176
172
bool same_page = false;
+1
drivers/android/binder.c
+1
drivers/android/binder.c
+2
drivers/block/ublk_drv.c
+2
drivers/block/ublk_drv.c
+22
-3
drivers/clk/qcom/clk-alpha-pll.c
+22
-3
drivers/clk/qcom/clk-alpha-pll.c
···
40
40
41
41
#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
42
42
# define PLL_POST_DIV_SHIFT 8
43
-
# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
43
+
# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
44
+
# define PLL_ALPHA_MSB BIT(15)
44
45
# define PLL_ALPHA_EN BIT(24)
45
46
# define PLL_ALPHA_MODE BIT(25)
46
47
# define PLL_VCO_SHIFT 20
···
1553
1552
}
1554
1553
1555
1554
return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1556
-
PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1557
-
val << PLL_POST_DIV_SHIFT);
1555
+
PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
1556
+
val << pll->post_div_shift);
1558
1557
}
1559
1558
1560
1559
const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
···
2118
2117
regmap_write(regmap, PLL_OPMODE(pll), 0x0);
2119
2118
}
2120
2119
2120
+
static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l)
2121
+
{
2122
+
u64 remainder, quotient;
2123
+
2124
+
quotient = rate;
2125
+
remainder = do_div(quotient, prate);
2126
+
*l = quotient;
2127
+
2128
+
if ((remainder * 2) / prate)
2129
+
*l = *l + 1;
2130
+
}
2131
+
2121
2132
static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
2122
2133
unsigned long prate)
2123
2134
{
···
2146
2133
if (ret < 0)
2147
2134
return ret;
2148
2135
2136
+
if (a & PLL_ALPHA_MSB)
2137
+
zonda_pll_adjust_l_val(rate, prate, &l);
2138
+
2149
2139
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2150
2140
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2141
+
2142
+
if (!clk_hw_is_enabled(hw))
2143
+
return 0;
2151
2144
2152
2145
/* Wait before polling for the frequency latch */
2153
2146
udelay(5);
+1
drivers/clk/qcom/clk-rcg.h
+1
drivers/clk/qcom/clk-rcg.h
···
198
198
extern const struct clk_ops clk_pixel_ops;
199
199
extern const struct clk_ops clk_gfx3d_ops;
200
200
extern const struct clk_ops clk_rcg2_shared_ops;
201
+
extern const struct clk_ops clk_rcg2_shared_no_init_park_ops;
201
202
extern const struct clk_ops clk_dp_ops;
202
203
203
204
struct clk_rcg_dfs_data {
+30
drivers/clk/qcom/clk-rcg2.c
+30
drivers/clk/qcom/clk-rcg2.c
···
1348
1348
};
1349
1349
EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
1350
1350
1351
+
static int clk_rcg2_shared_no_init_park(struct clk_hw *hw)
1352
+
{
1353
+
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1354
+
1355
+
/*
1356
+
* Read the config register so that the parent is properly mapped at
1357
+
* registration time.
1358
+
*/
1359
+
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg);
1360
+
1361
+
return 0;
1362
+
}
1363
+
1364
+
/*
1365
+
* Like clk_rcg2_shared_ops but skip the init so that the clk frequency is left
1366
+
* unchanged at registration time.
1367
+
*/
1368
+
const struct clk_ops clk_rcg2_shared_no_init_park_ops = {
1369
+
.init = clk_rcg2_shared_no_init_park,
1370
+
.enable = clk_rcg2_shared_enable,
1371
+
.disable = clk_rcg2_shared_disable,
1372
+
.get_parent = clk_rcg2_shared_get_parent,
1373
+
.set_parent = clk_rcg2_shared_set_parent,
1374
+
.recalc_rate = clk_rcg2_shared_recalc_rate,
1375
+
.determine_rate = clk_rcg2_determine_rate,
1376
+
.set_rate = clk_rcg2_shared_set_rate,
1377
+
.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
1378
+
};
1379
+
EXPORT_SYMBOL_GPL(clk_rcg2_shared_no_init_park_ops);
1380
+
1351
1381
/* Common APIs to be used for DFS based RCGR */
1352
1382
static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
1353
1383
struct freq_tbl *f)
+6
-6
drivers/clk/qcom/gcc-ipq9574.c
+6
-6
drivers/clk/qcom/gcc-ipq9574.c
···
68
68
69
69
static struct clk_alpha_pll gpll0_main = {
70
70
.offset = 0x20000,
71
-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
71
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
72
72
.clkr = {
73
73
.enable_reg = 0x0b000,
74
74
.enable_mask = BIT(0),
···
96
96
97
97
static struct clk_alpha_pll_postdiv gpll0 = {
98
98
.offset = 0x20000,
99
-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
99
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
100
100
.width = 4,
101
101
.clkr.hw.init = &(const struct clk_init_data) {
102
102
.name = "gpll0",
···
110
110
111
111
static struct clk_alpha_pll gpll4_main = {
112
112
.offset = 0x22000,
113
-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
113
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
114
114
.clkr = {
115
115
.enable_reg = 0x0b000,
116
116
.enable_mask = BIT(2),
···
125
125
126
126
static struct clk_alpha_pll_postdiv gpll4 = {
127
127
.offset = 0x22000,
128
-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
128
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
129
129
.width = 4,
130
130
.clkr.hw.init = &(const struct clk_init_data) {
131
131
.name = "gpll4",
···
139
139
140
140
static struct clk_alpha_pll gpll2_main = {
141
141
.offset = 0x21000,
142
-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
142
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
143
143
.clkr = {
144
144
.enable_reg = 0x0b000,
145
145
.enable_mask = BIT(1),
···
154
154
155
155
static struct clk_alpha_pll_postdiv gpll2 = {
156
156
.offset = 0x21000,
157
-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
157
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
158
158
.width = 4,
159
159
.clkr.hw.init = &(const struct clk_init_data) {
160
160
.name = "gpll2",
+24
-24
drivers/clk/qcom/gcc-sc8280xp.c
+24
-24
drivers/clk/qcom/gcc-sc8280xp.c
···
1500
1500
.parent_data = gcc_parent_data_0,
1501
1501
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1502
1502
.flags = CLK_SET_RATE_PARENT,
1503
-
.ops = &clk_rcg2_shared_ops,
1503
+
.ops = &clk_rcg2_ops,
1504
1504
};
1505
1505
1506
1506
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
···
1517
1517
.parent_data = gcc_parent_data_0,
1518
1518
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1519
1519
.flags = CLK_SET_RATE_PARENT,
1520
-
.ops = &clk_rcg2_shared_ops,
1520
+
.ops = &clk_rcg2_ops,
1521
1521
};
1522
1522
1523
1523
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
···
1534
1534
.parent_data = gcc_parent_data_0,
1535
1535
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1536
1536
.flags = CLK_SET_RATE_PARENT,
1537
-
.ops = &clk_rcg2_shared_ops,
1537
+
.ops = &clk_rcg2_ops,
1538
1538
};
1539
1539
1540
1540
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
···
1551
1551
.parent_data = gcc_parent_data_0,
1552
1552
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1553
1553
.flags = CLK_SET_RATE_PARENT,
1554
-
.ops = &clk_rcg2_shared_ops,
1554
+
.ops = &clk_rcg2_ops,
1555
1555
};
1556
1556
1557
1557
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
···
1568
1568
.parent_data = gcc_parent_data_0,
1569
1569
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1570
1570
.flags = CLK_SET_RATE_PARENT,
1571
-
.ops = &clk_rcg2_shared_ops,
1571
+
.ops = &clk_rcg2_ops,
1572
1572
};
1573
1573
1574
1574
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
···
1585
1585
.parent_data = gcc_parent_data_0,
1586
1586
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1587
1587
.flags = CLK_SET_RATE_PARENT,
1588
-
.ops = &clk_rcg2_shared_ops,
1588
+
.ops = &clk_rcg2_ops,
1589
1589
};
1590
1590
1591
1591
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
···
1617
1617
.parent_data = gcc_parent_data_0,
1618
1618
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1619
1619
.flags = CLK_SET_RATE_PARENT,
1620
-
.ops = &clk_rcg2_shared_ops,
1620
+
.ops = &clk_rcg2_ops,
1621
1621
};
1622
1622
1623
1623
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
···
1634
1634
.parent_data = gcc_parent_data_0,
1635
1635
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1636
1636
.flags = CLK_SET_RATE_PARENT,
1637
-
.ops = &clk_rcg2_shared_ops,
1637
+
.ops = &clk_rcg2_ops,
1638
1638
};
1639
1639
1640
1640
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
···
1651
1651
.parent_data = gcc_parent_data_0,
1652
1652
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1653
1653
.flags = CLK_SET_RATE_PARENT,
1654
-
.ops = &clk_rcg2_shared_ops,
1654
+
.ops = &clk_rcg2_ops,
1655
1655
};
1656
1656
1657
1657
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
···
1668
1668
.parent_data = gcc_parent_data_0,
1669
1669
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1670
1670
.flags = CLK_SET_RATE_PARENT,
1671
-
.ops = &clk_rcg2_shared_ops,
1671
+
.ops = &clk_rcg2_ops,
1672
1672
};
1673
1673
1674
1674
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
···
1685
1685
.parent_data = gcc_parent_data_0,
1686
1686
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1687
1687
.flags = CLK_SET_RATE_PARENT,
1688
-
.ops = &clk_rcg2_shared_ops,
1688
+
.ops = &clk_rcg2_ops,
1689
1689
};
1690
1690
1691
1691
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
···
1702
1702
.parent_data = gcc_parent_data_0,
1703
1703
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1704
1704
.flags = CLK_SET_RATE_PARENT,
1705
-
.ops = &clk_rcg2_shared_ops,
1705
+
.ops = &clk_rcg2_ops,
1706
1706
};
1707
1707
1708
1708
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
···
1719
1719
.parent_data = gcc_parent_data_0,
1720
1720
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1721
1721
.flags = CLK_SET_RATE_PARENT,
1722
-
.ops = &clk_rcg2_shared_ops,
1722
+
.ops = &clk_rcg2_ops,
1723
1723
};
1724
1724
1725
1725
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
···
1736
1736
.parent_data = gcc_parent_data_0,
1737
1737
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1738
1738
.flags = CLK_SET_RATE_PARENT,
1739
-
.ops = &clk_rcg2_shared_ops,
1739
+
.ops = &clk_rcg2_ops,
1740
1740
};
1741
1741
1742
1742
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
···
1753
1753
.parent_data = gcc_parent_data_0,
1754
1754
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1755
1755
.flags = CLK_SET_RATE_PARENT,
1756
-
.ops = &clk_rcg2_shared_ops,
1756
+
.ops = &clk_rcg2_ops,
1757
1757
};
1758
1758
1759
1759
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
···
1770
1770
.parent_data = gcc_parent_data_0,
1771
1771
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1772
1772
.flags = CLK_SET_RATE_PARENT,
1773
-
.ops = &clk_rcg2_shared_ops,
1773
+
.ops = &clk_rcg2_ops,
1774
1774
};
1775
1775
1776
1776
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
···
1787
1787
.parent_data = gcc_parent_data_0,
1788
1788
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1789
1789
.flags = CLK_SET_RATE_PARENT,
1790
-
.ops = &clk_rcg2_shared_ops,
1790
+
.ops = &clk_rcg2_ops,
1791
1791
};
1792
1792
1793
1793
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
···
1804
1804
.parent_data = gcc_parent_data_0,
1805
1805
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1806
1806
.flags = CLK_SET_RATE_PARENT,
1807
-
.ops = &clk_rcg2_shared_ops,
1807
+
.ops = &clk_rcg2_ops,
1808
1808
};
1809
1809
1810
1810
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
···
1821
1821
.parent_data = gcc_parent_data_0,
1822
1822
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1823
1823
.flags = CLK_SET_RATE_PARENT,
1824
-
.ops = &clk_rcg2_shared_ops,
1824
+
.ops = &clk_rcg2_ops,
1825
1825
};
1826
1826
1827
1827
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
···
1838
1838
.parent_data = gcc_parent_data_0,
1839
1839
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1840
1840
.flags = CLK_SET_RATE_PARENT,
1841
-
.ops = &clk_rcg2_shared_ops,
1841
+
.ops = &clk_rcg2_ops,
1842
1842
};
1843
1843
1844
1844
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
···
1855
1855
.parent_data = gcc_parent_data_0,
1856
1856
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1857
1857
.flags = CLK_SET_RATE_PARENT,
1858
-
.ops = &clk_rcg2_shared_ops,
1858
+
.ops = &clk_rcg2_ops,
1859
1859
};
1860
1860
1861
1861
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
···
1872
1872
.parent_data = gcc_parent_data_0,
1873
1873
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1874
1874
.flags = CLK_SET_RATE_PARENT,
1875
-
.ops = &clk_rcg2_shared_ops,
1875
+
.ops = &clk_rcg2_ops,
1876
1876
};
1877
1877
1878
1878
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
···
1889
1889
.parent_data = gcc_parent_data_0,
1890
1890
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1891
1891
.flags = CLK_SET_RATE_PARENT,
1892
-
.ops = &clk_rcg2_shared_ops,
1892
+
.ops = &clk_rcg2_ops,
1893
1893
};
1894
1894
1895
1895
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
···
1906
1906
.parent_data = gcc_parent_data_0,
1907
1907
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1908
1908
.flags = CLK_SET_RATE_PARENT,
1909
-
.ops = &clk_rcg2_shared_ops,
1909
+
.ops = &clk_rcg2_ops,
1910
1910
};
1911
1911
1912
1912
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
+27
-27
drivers/clk/qcom/gcc-sm8550.c
+27
-27
drivers/clk/qcom/gcc-sm8550.c
···
536
536
.parent_data = gcc_parent_data_0,
537
537
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
538
538
.flags = CLK_SET_RATE_PARENT,
539
-
.ops = &clk_rcg2_shared_ops,
539
+
.ops = &clk_rcg2_ops,
540
540
},
541
541
};
542
542
···
551
551
.parent_data = gcc_parent_data_0,
552
552
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
553
553
.flags = CLK_SET_RATE_PARENT,
554
-
.ops = &clk_rcg2_shared_ops,
554
+
.ops = &clk_rcg2_ops,
555
555
},
556
556
};
557
557
···
566
566
.parent_data = gcc_parent_data_0,
567
567
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
568
568
.flags = CLK_SET_RATE_PARENT,
569
-
.ops = &clk_rcg2_shared_ops,
569
+
.ops = &clk_rcg2_ops,
570
570
},
571
571
};
572
572
···
581
581
.parent_data = gcc_parent_data_0,
582
582
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
583
583
.flags = CLK_SET_RATE_PARENT,
584
-
.ops = &clk_rcg2_shared_ops,
584
+
.ops = &clk_rcg2_ops,
585
585
},
586
586
};
587
587
···
596
596
.parent_data = gcc_parent_data_0,
597
597
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
598
598
.flags = CLK_SET_RATE_PARENT,
599
-
.ops = &clk_rcg2_shared_ops,
599
+
.ops = &clk_rcg2_ops,
600
600
},
601
601
};
602
602
···
611
611
.parent_data = gcc_parent_data_0,
612
612
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
613
613
.flags = CLK_SET_RATE_PARENT,
614
-
.ops = &clk_rcg2_shared_ops,
614
+
.ops = &clk_rcg2_ops,
615
615
},
616
616
};
617
617
···
626
626
.parent_data = gcc_parent_data_0,
627
627
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
628
628
.flags = CLK_SET_RATE_PARENT,
629
-
.ops = &clk_rcg2_shared_ops,
629
+
.ops = &clk_rcg2_ops,
630
630
},
631
631
};
632
632
···
641
641
.parent_data = gcc_parent_data_0,
642
642
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
643
643
.flags = CLK_SET_RATE_PARENT,
644
-
.ops = &clk_rcg2_shared_ops,
644
+
.ops = &clk_rcg2_ops,
645
645
},
646
646
};
647
647
···
656
656
.parent_data = gcc_parent_data_0,
657
657
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
658
658
.flags = CLK_SET_RATE_PARENT,
659
-
.ops = &clk_rcg2_shared_ops,
659
+
.ops = &clk_rcg2_ops,
660
660
},
661
661
};
662
662
···
671
671
.parent_data = gcc_parent_data_0,
672
672
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
673
673
.flags = CLK_SET_RATE_PARENT,
674
-
.ops = &clk_rcg2_shared_ops,
674
+
.ops = &clk_rcg2_ops,
675
675
},
676
676
};
677
677
···
700
700
.parent_data = gcc_parent_data_0,
701
701
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
702
702
.flags = CLK_SET_RATE_PARENT,
703
-
.ops = &clk_rcg2_shared_ops,
703
+
.ops = &clk_rcg2_ops,
704
704
};
705
705
706
706
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
···
717
717
.parent_data = gcc_parent_data_0,
718
718
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
719
719
.flags = CLK_SET_RATE_PARENT,
720
-
.ops = &clk_rcg2_shared_ops,
720
+
.ops = &clk_rcg2_ops,
721
721
};
722
722
723
723
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
···
750
750
.parent_data = gcc_parent_data_0,
751
751
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
752
752
.flags = CLK_SET_RATE_PARENT,
753
-
.ops = &clk_rcg2_shared_ops,
753
+
.ops = &clk_rcg2_ops,
754
754
};
755
755
756
756
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
···
767
767
.parent_data = gcc_parent_data_0,
768
768
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
769
769
.flags = CLK_SET_RATE_PARENT,
770
-
.ops = &clk_rcg2_shared_ops,
770
+
.ops = &clk_rcg2_ops,
771
771
};
772
772
773
773
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
···
784
784
.parent_data = gcc_parent_data_0,
785
785
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
786
786
.flags = CLK_SET_RATE_PARENT,
787
-
.ops = &clk_rcg2_shared_ops,
787
+
.ops = &clk_rcg2_ops,
788
788
};
789
789
790
790
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
···
801
801
.parent_data = gcc_parent_data_0,
802
802
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
803
803
.flags = CLK_SET_RATE_PARENT,
804
-
.ops = &clk_rcg2_shared_ops,
804
+
.ops = &clk_rcg2_ops,
805
805
};
806
806
807
807
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
···
818
818
.parent_data = gcc_parent_data_0,
819
819
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
820
820
.flags = CLK_SET_RATE_PARENT,
821
-
.ops = &clk_rcg2_shared_ops,
821
+
.ops = &clk_rcg2_ops,
822
822
};
823
823
824
824
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
···
835
835
.parent_data = gcc_parent_data_0,
836
836
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
837
837
.flags = CLK_SET_RATE_PARENT,
838
-
.ops = &clk_rcg2_shared_ops,
838
+
.ops = &clk_rcg2_ops,
839
839
};
840
840
841
841
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
···
852
852
.parent_data = gcc_parent_data_0,
853
853
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
854
854
.flags = CLK_SET_RATE_PARENT,
855
-
.ops = &clk_rcg2_shared_ops,
855
+
.ops = &clk_rcg2_ops,
856
856
};
857
857
858
858
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
···
869
869
.parent_data = gcc_parent_data_0,
870
870
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
871
871
.flags = CLK_SET_RATE_PARENT,
872
-
.ops = &clk_rcg2_shared_ops,
872
+
.ops = &clk_rcg2_ops,
873
873
};
874
874
875
875
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
···
886
886
.parent_data = gcc_parent_data_0,
887
887
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
888
888
.flags = CLK_SET_RATE_PARENT,
889
-
.ops = &clk_rcg2_shared_ops,
889
+
.ops = &clk_rcg2_ops,
890
890
};
891
891
892
892
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
···
903
903
.parent_data = gcc_parent_data_0,
904
904
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
905
905
.flags = CLK_SET_RATE_PARENT,
906
-
.ops = &clk_rcg2_shared_ops,
906
+
.ops = &clk_rcg2_ops,
907
907
};
908
908
909
909
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
···
920
920
.parent_data = gcc_parent_data_0,
921
921
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
922
922
.flags = CLK_SET_RATE_PARENT,
923
-
.ops = &clk_rcg2_shared_ops,
923
+
.ops = &clk_rcg2_ops,
924
924
};
925
925
926
926
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
···
937
937
.parent_data = gcc_parent_data_0,
938
938
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
939
939
.flags = CLK_SET_RATE_PARENT,
940
-
.ops = &clk_rcg2_shared_ops,
940
+
.ops = &clk_rcg2_ops,
941
941
};
942
942
943
943
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
···
975
975
.parent_data = gcc_parent_data_8,
976
976
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
977
977
.flags = CLK_SET_RATE_PARENT,
978
-
.ops = &clk_rcg2_shared_ops,
978
+
.ops = &clk_rcg2_ops,
979
979
};
980
980
981
981
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
···
992
992
.parent_data = gcc_parent_data_0,
993
993
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
994
994
.flags = CLK_SET_RATE_PARENT,
995
-
.ops = &clk_rcg2_shared_ops,
995
+
.ops = &clk_rcg2_ops,
996
996
};
997
997
998
998
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
···
1159
1159
.parent_data = gcc_parent_data_0,
1160
1160
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1161
1161
.flags = CLK_SET_RATE_PARENT,
1162
-
.ops = &clk_rcg2_shared_ops,
1162
+
.ops = &clk_rcg2_shared_no_init_park_ops,
1163
1163
},
1164
1164
};
1165
1165
+28
-28
drivers/clk/qcom/gcc-sm8650.c
+28
-28
drivers/clk/qcom/gcc-sm8650.c
···
713
713
.parent_data = gcc_parent_data_0,
714
714
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
715
715
.flags = CLK_SET_RATE_PARENT,
716
-
.ops = &clk_rcg2_shared_ops,
716
+
.ops = &clk_rcg2_ops,
717
717
},
718
718
};
719
719
···
728
728
.parent_data = gcc_parent_data_0,
729
729
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
730
730
.flags = CLK_SET_RATE_PARENT,
731
-
.ops = &clk_rcg2_shared_ops,
731
+
.ops = &clk_rcg2_ops,
732
732
},
733
733
};
734
734
···
743
743
.parent_data = gcc_parent_data_0,
744
744
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
745
745
.flags = CLK_SET_RATE_PARENT,
746
-
.ops = &clk_rcg2_shared_ops,
746
+
.ops = &clk_rcg2_ops,
747
747
},
748
748
};
749
749
···
758
758
.parent_data = gcc_parent_data_0,
759
759
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
760
760
.flags = CLK_SET_RATE_PARENT,
761
-
.ops = &clk_rcg2_shared_ops,
761
+
.ops = &clk_rcg2_ops,
762
762
},
763
763
};
764
764
···
773
773
.parent_data = gcc_parent_data_0,
774
774
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
775
775
.flags = CLK_SET_RATE_PARENT,
776
-
.ops = &clk_rcg2_shared_ops,
776
+
.ops = &clk_rcg2_ops,
777
777
},
778
778
};
779
779
···
788
788
.parent_data = gcc_parent_data_0,
789
789
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
790
790
.flags = CLK_SET_RATE_PARENT,
791
-
.ops = &clk_rcg2_shared_ops,
791
+
.ops = &clk_rcg2_ops,
792
792
},
793
793
};
794
794
···
803
803
.parent_data = gcc_parent_data_0,
804
804
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
805
805
.flags = CLK_SET_RATE_PARENT,
806
-
.ops = &clk_rcg2_shared_ops,
806
+
.ops = &clk_rcg2_ops,
807
807
},
808
808
};
809
809
···
818
818
.parent_data = gcc_parent_data_0,
819
819
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
820
820
.flags = CLK_SET_RATE_PARENT,
821
-
.ops = &clk_rcg2_shared_ops,
821
+
.ops = &clk_rcg2_ops,
822
822
},
823
823
};
824
824
···
833
833
.parent_data = gcc_parent_data_0,
834
834
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
835
835
.flags = CLK_SET_RATE_PARENT,
836
-
.ops = &clk_rcg2_shared_ops,
836
+
.ops = &clk_rcg2_ops,
837
837
},
838
838
};
839
839
···
848
848
.parent_data = gcc_parent_data_0,
849
849
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
850
850
.flags = CLK_SET_RATE_PARENT,
851
-
.ops = &clk_rcg2_shared_ops,
851
+
.ops = &clk_rcg2_ops,
852
852
},
853
853
};
854
854
···
863
863
.parent_data = gcc_parent_data_0,
864
864
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
865
865
.flags = CLK_SET_RATE_PARENT,
866
-
.ops = &clk_rcg2_shared_ops,
866
+
.ops = &clk_rcg2_ops,
867
867
};
868
868
869
869
static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = {
···
899
899
.parent_data = gcc_parent_data_0,
900
900
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
901
901
.flags = CLK_SET_RATE_PARENT,
902
-
.ops = &clk_rcg2_shared_ops,
902
+
.ops = &clk_rcg2_ops,
903
903
};
904
904
905
905
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
···
916
916
.parent_data = gcc_parent_data_0,
917
917
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
918
918
.flags = CLK_SET_RATE_PARENT,
919
-
.ops = &clk_rcg2_shared_ops,
919
+
.ops = &clk_rcg2_ops,
920
920
};
921
921
922
922
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
···
948
948
.parent_data = gcc_parent_data_0,
949
949
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
950
950
.flags = CLK_SET_RATE_PARENT,
951
-
.ops = &clk_rcg2_shared_ops,
951
+
.ops = &clk_rcg2_ops,
952
952
};
953
953
954
954
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
···
980
980
.parent_data = gcc_parent_data_0,
981
981
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
982
982
.flags = CLK_SET_RATE_PARENT,
983
-
.ops = &clk_rcg2_shared_ops,
983
+
.ops = &clk_rcg2_ops,
984
984
};
985
985
986
986
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
···
997
997
.parent_data = gcc_parent_data_0,
998
998
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
999
999
.flags = CLK_SET_RATE_PARENT,
1000
-
.ops = &clk_rcg2_shared_ops,
1000
+
.ops = &clk_rcg2_ops,
1001
1001
};
1002
1002
1003
1003
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
···
1014
1014
.parent_data = gcc_parent_data_0,
1015
1015
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1016
1016
.flags = CLK_SET_RATE_PARENT,
1017
-
.ops = &clk_rcg2_shared_ops,
1017
+
.ops = &clk_rcg2_ops,
1018
1018
};
1019
1019
1020
1020
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
···
1031
1031
.parent_data = gcc_parent_data_0,
1032
1032
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1033
1033
.flags = CLK_SET_RATE_PARENT,
1034
-
.ops = &clk_rcg2_shared_ops,
1034
+
.ops = &clk_rcg2_ops,
1035
1035
};
1036
1036
1037
1037
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
···
1059
1059
.parent_data = gcc_parent_data_2,
1060
1060
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1061
1061
.flags = CLK_SET_RATE_PARENT,
1062
-
.ops = &clk_rcg2_shared_ops,
1062
+
.ops = &clk_rcg2_ops,
1063
1063
},
1064
1064
};
1065
1065
···
1068
1068
.parent_data = gcc_parent_data_0,
1069
1069
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1070
1070
.flags = CLK_SET_RATE_PARENT,
1071
-
.ops = &clk_rcg2_shared_ops,
1071
+
.ops = &clk_rcg2_ops,
1072
1072
};
1073
1073
1074
1074
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
···
1085
1085
.parent_data = gcc_parent_data_0,
1086
1086
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1087
1087
.flags = CLK_SET_RATE_PARENT,
1088
-
.ops = &clk_rcg2_shared_ops,
1088
+
.ops = &clk_rcg2_ops,
1089
1089
};
1090
1090
1091
1091
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
···
1102
1102
.parent_data = gcc_parent_data_0,
1103
1103
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1104
1104
.flags = CLK_SET_RATE_PARENT,
1105
-
.ops = &clk_rcg2_shared_ops,
1105
+
.ops = &clk_rcg2_ops,
1106
1106
};
1107
1107
1108
1108
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
···
1119
1119
.parent_data = gcc_parent_data_0,
1120
1120
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1121
1121
.flags = CLK_SET_RATE_PARENT,
1122
-
.ops = &clk_rcg2_shared_ops,
1122
+
.ops = &clk_rcg2_ops,
1123
1123
};
1124
1124
1125
1125
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
···
1136
1136
.parent_data = gcc_parent_data_0,
1137
1137
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1138
1138
.flags = CLK_SET_RATE_PARENT,
1139
-
.ops = &clk_rcg2_shared_ops,
1139
+
.ops = &clk_rcg2_ops,
1140
1140
};
1141
1141
1142
1142
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
···
1153
1153
.parent_data = gcc_parent_data_0,
1154
1154
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1155
1155
.flags = CLK_SET_RATE_PARENT,
1156
-
.ops = &clk_rcg2_shared_ops,
1156
+
.ops = &clk_rcg2_ops,
1157
1157
};
1158
1158
1159
1159
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
···
1186
1186
.parent_data = gcc_parent_data_10,
1187
1187
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
1188
1188
.flags = CLK_SET_RATE_PARENT,
1189
-
.ops = &clk_rcg2_shared_ops,
1189
+
.ops = &clk_rcg2_ops,
1190
1190
};
1191
1191
1192
1192
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
···
1203
1203
.parent_data = gcc_parent_data_0,
1204
1204
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1205
1205
.flags = CLK_SET_RATE_PARENT,
1206
-
.ops = &clk_rcg2_shared_ops,
1206
+
.ops = &clk_rcg2_ops,
1207
1207
};
1208
1208
1209
1209
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
···
1226
1226
.parent_data = gcc_parent_data_0,
1227
1227
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1228
1228
.flags = CLK_SET_RATE_PARENT,
1229
-
.ops = &clk_rcg2_shared_ops,
1229
+
.ops = &clk_rcg2_ops,
1230
1230
};
1231
1231
1232
1232
static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = {
+26
-26
drivers/clk/qcom/gcc-x1e80100.c
+26
-26
drivers/clk/qcom/gcc-x1e80100.c
···
670
670
.parent_data = gcc_parent_data_0,
671
671
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
672
672
.flags = CLK_SET_RATE_PARENT,
673
-
.ops = &clk_rcg2_shared_ops,
673
+
.ops = &clk_rcg2_ops,
674
674
};
675
675
676
676
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
···
687
687
.parent_data = gcc_parent_data_0,
688
688
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
689
689
.flags = CLK_SET_RATE_PARENT,
690
-
.ops = &clk_rcg2_shared_ops,
690
+
.ops = &clk_rcg2_ops,
691
691
};
692
692
693
693
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
···
719
719
.parent_data = gcc_parent_data_0,
720
720
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
721
721
.flags = CLK_SET_RATE_PARENT,
722
-
.ops = &clk_rcg2_shared_ops,
722
+
.ops = &clk_rcg2_ops,
723
723
};
724
724
725
725
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
···
736
736
.parent_data = gcc_parent_data_0,
737
737
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
738
738
.flags = CLK_SET_RATE_PARENT,
739
-
.ops = &clk_rcg2_shared_ops,
739
+
.ops = &clk_rcg2_ops,
740
740
};
741
741
742
742
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
···
768
768
.parent_data = gcc_parent_data_0,
769
769
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
770
770
.flags = CLK_SET_RATE_PARENT,
771
-
.ops = &clk_rcg2_shared_ops,
771
+
.ops = &clk_rcg2_ops,
772
772
};
773
773
774
774
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
···
785
785
.parent_data = gcc_parent_data_0,
786
786
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
787
787
.flags = CLK_SET_RATE_PARENT,
788
-
.ops = &clk_rcg2_shared_ops,
788
+
.ops = &clk_rcg2_ops,
789
789
};
790
790
791
791
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
···
802
802
.parent_data = gcc_parent_data_0,
803
803
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
804
804
.flags = CLK_SET_RATE_PARENT,
805
-
.ops = &clk_rcg2_shared_ops,
805
+
.ops = &clk_rcg2_ops,
806
806
};
807
807
808
808
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
···
819
819
.parent_data = gcc_parent_data_0,
820
820
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
821
821
.flags = CLK_SET_RATE_PARENT,
822
-
.ops = &clk_rcg2_shared_ops,
822
+
.ops = &clk_rcg2_ops,
823
823
};
824
824
825
825
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
···
836
836
.parent_data = gcc_parent_data_0,
837
837
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
838
838
.flags = CLK_SET_RATE_PARENT,
839
-
.ops = &clk_rcg2_shared_ops,
839
+
.ops = &clk_rcg2_ops,
840
840
};
841
841
842
842
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
···
853
853
.parent_data = gcc_parent_data_0,
854
854
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
855
855
.flags = CLK_SET_RATE_PARENT,
856
-
.ops = &clk_rcg2_shared_ops,
856
+
.ops = &clk_rcg2_ops,
857
857
};
858
858
859
859
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
···
870
870
.parent_data = gcc_parent_data_0,
871
871
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
872
872
.flags = CLK_SET_RATE_PARENT,
873
-
.ops = &clk_rcg2_shared_ops,
873
+
.ops = &clk_rcg2_ops,
874
874
};
875
875
876
876
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
···
887
887
.parent_data = gcc_parent_data_0,
888
888
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
889
889
.flags = CLK_SET_RATE_PARENT,
890
-
.ops = &clk_rcg2_shared_ops,
890
+
.ops = &clk_rcg2_ops,
891
891
};
892
892
893
893
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
···
904
904
.parent_data = gcc_parent_data_0,
905
905
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
906
906
.flags = CLK_SET_RATE_PARENT,
907
-
.ops = &clk_rcg2_shared_ops,
907
+
.ops = &clk_rcg2_ops,
908
908
};
909
909
910
910
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
···
921
921
.parent_data = gcc_parent_data_0,
922
922
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
923
923
.flags = CLK_SET_RATE_PARENT,
924
-
.ops = &clk_rcg2_shared_ops,
924
+
.ops = &clk_rcg2_ops,
925
925
};
926
926
927
927
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
···
938
938
.parent_data = gcc_parent_data_0,
939
939
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
940
940
.flags = CLK_SET_RATE_PARENT,
941
-
.ops = &clk_rcg2_shared_ops,
941
+
.ops = &clk_rcg2_ops,
942
942
};
943
943
944
944
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
···
955
955
.parent_data = gcc_parent_data_0,
956
956
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
957
957
.flags = CLK_SET_RATE_PARENT,
958
-
.ops = &clk_rcg2_shared_ops,
958
+
.ops = &clk_rcg2_ops,
959
959
};
960
960
961
961
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
···
972
972
.parent_data = gcc_parent_data_0,
973
973
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
974
974
.flags = CLK_SET_RATE_PARENT,
975
-
.ops = &clk_rcg2_shared_ops,
975
+
.ops = &clk_rcg2_ops,
976
976
};
977
977
978
978
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
···
989
989
.parent_data = gcc_parent_data_0,
990
990
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
991
991
.flags = CLK_SET_RATE_PARENT,
992
-
.ops = &clk_rcg2_shared_ops,
992
+
.ops = &clk_rcg2_ops,
993
993
};
994
994
995
995
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
···
1006
1006
.parent_data = gcc_parent_data_0,
1007
1007
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1008
1008
.flags = CLK_SET_RATE_PARENT,
1009
-
.ops = &clk_rcg2_shared_ops,
1009
+
.ops = &clk_rcg2_ops,
1010
1010
};
1011
1011
1012
1012
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
···
1023
1023
.parent_data = gcc_parent_data_0,
1024
1024
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1025
1025
.flags = CLK_SET_RATE_PARENT,
1026
-
.ops = &clk_rcg2_shared_ops,
1026
+
.ops = &clk_rcg2_ops,
1027
1027
};
1028
1028
1029
1029
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
···
1040
1040
.parent_data = gcc_parent_data_0,
1041
1041
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1042
1042
.flags = CLK_SET_RATE_PARENT,
1043
-
.ops = &clk_rcg2_shared_ops,
1043
+
.ops = &clk_rcg2_ops,
1044
1044
};
1045
1045
1046
1046
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
···
1057
1057
.parent_data = gcc_parent_data_0,
1058
1058
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1059
1059
.flags = CLK_SET_RATE_PARENT,
1060
-
.ops = &clk_rcg2_shared_ops,
1060
+
.ops = &clk_rcg2_ops,
1061
1061
};
1062
1062
1063
1063
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
···
1074
1074
.parent_data = gcc_parent_data_8,
1075
1075
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
1076
1076
.flags = CLK_SET_RATE_PARENT,
1077
-
.ops = &clk_rcg2_shared_ops,
1077
+
.ops = &clk_rcg2_ops,
1078
1078
};
1079
1079
1080
1080
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
···
1091
1091
.parent_data = gcc_parent_data_0,
1092
1092
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1093
1093
.flags = CLK_SET_RATE_PARENT,
1094
-
.ops = &clk_rcg2_shared_ops,
1094
+
.ops = &clk_rcg2_ops,
1095
1095
};
1096
1096
1097
1097
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
···
6203
6203
.pd = {
6204
6204
.name = "gcc_usb_0_phy_gdsc",
6205
6205
},
6206
-
.pwrsts = PWRSTS_OFF_ON,
6206
+
.pwrsts = PWRSTS_RET_ON,
6207
6207
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6208
6208
};
6209
6209
···
6215
6215
.pd = {
6216
6216
.name = "gcc_usb_1_phy_gdsc",
6217
6217
},
6218
-
.pwrsts = PWRSTS_OFF_ON,
6218
+
.pwrsts = PWRSTS_RET_ON,
6219
6219
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6220
6220
};
6221
6221
+30
-1
drivers/clk/starfive/clk-starfive-jh7110-sys.c
+30
-1
drivers/clk/starfive/clk-starfive-jh7110-sys.c
···
385
385
}
386
386
EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
387
387
388
+
/*
389
+
* This clock notifier is called when the rate of PLL0 clock is to be changed.
390
+
* The cpu_root clock should save the curent parent clock and switch its parent
391
+
* clock to osc before PLL0 rate will be changed. Then switch its parent clock
392
+
* back after the PLL0 rate is completed.
393
+
*/
394
+
static int jh7110_pll0_clk_notifier_cb(struct notifier_block *nb,
395
+
unsigned long action, void *data)
396
+
{
397
+
struct jh71x0_clk_priv *priv = container_of(nb, struct jh71x0_clk_priv, pll_clk_nb);
398
+
struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk;
399
+
int ret = 0;
400
+
401
+
if (action == PRE_RATE_CHANGE) {
402
+
struct clk *osc = clk_get(priv->dev, "osc");
403
+
404
+
priv->original_clk = clk_get_parent(cpu_root);
405
+
ret = clk_set_parent(cpu_root, osc);
406
+
clk_put(osc);
407
+
} else if (action == POST_RATE_CHANGE) {
408
+
ret = clk_set_parent(cpu_root, priv->original_clk);
409
+
}
410
+
411
+
return notifier_from_errno(ret);
412
+
}
413
+
388
414
static int __init jh7110_syscrg_probe(struct platform_device *pdev)
389
415
{
390
416
struct jh71x0_clk_priv *priv;
···
439
413
if (IS_ERR(priv->pll[0]))
440
414
return PTR_ERR(priv->pll[0]);
441
415
} else {
442
-
clk_put(pllclk);
416
+
priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb;
417
+
ret = clk_notifier_register(pllclk, &priv->pll_clk_nb);
418
+
if (ret)
419
+
return ret;
443
420
priv->pll[0] = NULL;
444
421
}
445
422
+2
drivers/clk/starfive/clk-starfive-jh71x0.h
+2
drivers/clk/starfive/clk-starfive-jh71x0.h
+15
-1
drivers/clocksource/hyperv_timer.c
+15
-1
drivers/clocksource/hyperv_timer.c
···
137
137
ce->name = "Hyper-V clockevent";
138
138
ce->features = CLOCK_EVT_FEAT_ONESHOT;
139
139
ce->cpumask = cpumask_of(cpu);
140
-
ce->rating = 1000;
140
+
141
+
/*
142
+
* Lower the rating of the Hyper-V timer in a TDX VM without paravisor,
143
+
* so the local APIC timer (lapic_clockevent) is the default timer in
144
+
* such a VM. The Hyper-V timer is not preferred in such a VM because
145
+
* it depends on the slow VM Reference Counter MSR (the Hyper-V TSC
146
+
* page is not enbled in such a VM because the VM uses Invariant TSC
147
+
* as a better clocksource and it's challenging to mark the Hyper-V
148
+
* TSC page shared in very early boot).
149
+
*/
150
+
if (!ms_hyperv.paravisor_present && hv_isolation_type_tdx())
151
+
ce->rating = 90;
152
+
else
153
+
ce->rating = 1000;
154
+
141
155
ce->set_state_shutdown = hv_ce_shutdown;
142
156
ce->set_state_oneshot = hv_ce_set_oneshot;
143
157
ce->set_next_event = hv_ce_set_next_event;
+12
-4
drivers/clocksource/timer-imx-tpm.c
+12
-4
drivers/clocksource/timer-imx-tpm.c
···
83
83
static int tpm_set_next_event(unsigned long delta,
84
84
struct clock_event_device *evt)
85
85
{
86
-
unsigned long next, now;
86
+
unsigned long next, prev, now;
87
87
88
-
next = tpm_read_counter();
89
-
next += delta;
88
+
prev = tpm_read_counter();
89
+
next = prev + delta;
90
90
writel(next, timer_base + TPM_C0V);
91
91
now = tpm_read_counter();
92
+
93
+
/*
94
+
* Need to wait CNT increase at least 1 cycle to make sure
95
+
* the C0V has been updated into HW.
96
+
*/
97
+
if ((next & 0xffffffff) != readl(timer_base + TPM_C0V))
98
+
while (now == tpm_read_counter())
99
+
;
92
100
93
101
/*
94
102
* NOTE: We observed in a very small probability, the bus fabric
···
104
96
* of writing CNT registers which may cause the min_delta event got
105
97
* missed, so we need add a ETIME check here in case it happened.
106
98
*/
107
-
return (int)(next - now) <= 0 ? -ETIME : 0;
99
+
return (now - prev) >= delta ? -ETIME : 0;
108
100
}
109
101
110
102
static int tpm_set_state_oneshot(struct clock_event_device *evt)
+4
-13
drivers/clocksource/timer-of.c
+4
-13
drivers/clocksource/timer-of.c
···
25
25
26
26
struct clock_event_device *clkevt = &to->clkevt;
27
27
28
-
if (of_irq->percpu)
29
-
free_percpu_irq(of_irq->irq, clkevt);
30
-
else
31
-
free_irq(of_irq->irq, clkevt);
28
+
free_irq(of_irq->irq, clkevt);
32
29
}
33
30
34
31
/**
···
38
41
*
39
42
* - Get interrupt number by name
40
43
* - Get interrupt number by index
41
-
*
42
-
* When the interrupt is per CPU, 'request_percpu_irq()' is called,
43
-
* otherwise 'request_irq()' is used.
44
44
*
45
45
* Returns 0 on success, < 0 otherwise
46
46
*/
···
63
69
return -EINVAL;
64
70
}
65
71
66
-
ret = of_irq->percpu ?
67
-
request_percpu_irq(of_irq->irq, of_irq->handler,
68
-
np->full_name, clkevt) :
69
-
request_irq(of_irq->irq, of_irq->handler,
70
-
of_irq->flags ? of_irq->flags : IRQF_TIMER,
71
-
np->full_name, clkevt);
72
+
ret = request_irq(of_irq->irq, of_irq->handler,
73
+
of_irq->flags ? of_irq->flags : IRQF_TIMER,
74
+
np->full_name, clkevt);
72
75
if (ret) {
73
76
pr_err("Failed to request irq %d for %pOF\n", of_irq->irq, np);
74
77
return ret;
-1
drivers/clocksource/timer-of.h
-1
drivers/clocksource/timer-of.h
+24
-10
drivers/cpufreq/amd-pstate.c
+24
-10
drivers/cpufreq/amd-pstate.c
···
1834
1834
}
1835
1835
1836
1836
/*
1837
-
* If the CPPC feature is disabled in the BIOS for processors that support MSR-based CPPC,
1838
-
* the AMD Pstate driver may not function correctly.
1839
-
* Check the CPPC flag and display a warning message if the platform supports CPPC.
1840
-
* Note: below checking code will not abort the driver registeration process because of
1841
-
* the code is added for debugging purposes.
1837
+
* If the CPPC feature is disabled in the BIOS for processors
1838
+
* that support MSR-based CPPC, the AMD Pstate driver may not
1839
+
* function correctly.
1840
+
*
1841
+
* For such processors, check the CPPC flag and display a
1842
+
* warning message if the platform supports CPPC.
1843
+
*
1844
+
* Note: The code check below will not abort the driver
1845
+
* registration process because of the code is added for
1846
+
* debugging purposes. Besides, it may still be possible for
1847
+
* the driver to work using the shared-memory mechanism.
1842
1848
*/
1843
1849
if (!cpu_feature_enabled(X86_FEATURE_CPPC)) {
1844
-
if (cpu_feature_enabled(X86_FEATURE_ZEN1) || cpu_feature_enabled(X86_FEATURE_ZEN2)) {
1845
-
if (c->x86_model > 0x60 && c->x86_model < 0xaf)
1850
+
if (cpu_feature_enabled(X86_FEATURE_ZEN2)) {
1851
+
switch (c->x86_model) {
1852
+
case 0x60 ... 0x6F:
1853
+
case 0x80 ... 0xAF:
1846
1854
warn = true;
1847
-
} else if (cpu_feature_enabled(X86_FEATURE_ZEN3) || cpu_feature_enabled(X86_FEATURE_ZEN4)) {
1848
-
if ((c->x86_model > 0x10 && c->x86_model < 0x1F) ||
1849
-
(c->x86_model > 0x40 && c->x86_model < 0xaf))
1855
+
break;
1856
+
}
1857
+
} else if (cpu_feature_enabled(X86_FEATURE_ZEN3) ||
1858
+
cpu_feature_enabled(X86_FEATURE_ZEN4)) {
1859
+
switch (c->x86_model) {
1860
+
case 0x10 ... 0x1F:
1861
+
case 0x40 ... 0xAF:
1850
1862
warn = true;
1863
+
break;
1864
+
}
1851
1865
} else if (cpu_feature_enabled(X86_FEATURE_ZEN5)) {
1852
1866
warn = true;
1853
1867
}
+4
drivers/firmware/qcom/qcom_qseecom_uefisecapp.c
+4
drivers/firmware/qcom/qcom_qseecom_uefisecapp.c
+1
drivers/gpio/gpio-rockchip.c
+1
drivers/gpio/gpio-rockchip.c
+1
drivers/gpio/gpio-zynqmp-modepin.c
+1
drivers/gpio/gpio-zynqmp-modepin.c
-1
drivers/gpu/drm/Makefile
-1
drivers/gpu/drm/Makefile
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
···
348
348
return -EINVAL;
349
349
}
350
350
351
+
/* always clear VRAM */
352
+
flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
353
+
351
354
/* create a gem object to contain this object in */
352
355
if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
353
356
AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
···
657
657
uint64_t queue_mask = 0;
658
658
int r, i, j;
659
659
660
-
if (adev->enable_mes)
660
+
if (adev->mes.enable_legacy_queue_map)
661
661
return amdgpu_gfx_mes_enable_kcq(adev, xcc_id);
662
662
663
663
if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
···
719
719
720
720
amdgpu_device_flush_hdp(adev, NULL);
721
721
722
-
if (adev->enable_mes) {
722
+
if (adev->mes.enable_legacy_queue_map) {
723
723
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
724
724
j = i + xcc_id * adev->gfx.num_gfx_rings;
725
725
r = amdgpu_mes_map_legacy_queue(adev,
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+34
-15
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+34
-15
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
···
693
693
(void **)&adev->mes.ucode_fw_ptr[pipe]);
694
694
}
695
695
696
+
static void mes_v11_0_get_fw_version(struct amdgpu_device *adev)
697
+
{
698
+
int pipe;
699
+
700
+
/* get MES scheduler/KIQ versions */
701
+
mutex_lock(&adev->srbm_mutex);
702
+
703
+
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
704
+
soc21_grbm_select(adev, 3, pipe, 0, 0);
705
+
706
+
if (pipe == AMDGPU_MES_SCHED_PIPE)
707
+
adev->mes.sched_version =
708
+
RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
709
+
else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
710
+
adev->mes.kiq_version =
711
+
RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
712
+
}
713
+
714
+
soc21_grbm_select(adev, 0, 0, 0, 0);
715
+
mutex_unlock(&adev->srbm_mutex);
716
+
}
717
+
696
718
static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
697
719
{
698
720
uint64_t ucode_addr;
···
1084
1062
mes_v11_0_queue_init_register(ring);
1085
1063
}
1086
1064
1087
-
/* get MES scheduler/KIQ versions */
1088
-
mutex_lock(&adev->srbm_mutex);
1089
-
soc21_grbm_select(adev, 3, pipe, 0, 0);
1090
-
1091
-
if (pipe == AMDGPU_MES_SCHED_PIPE)
1092
-
adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1093
-
else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
1094
-
adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1095
-
1096
-
soc21_grbm_select(adev, 0, 0, 0, 0);
1097
-
mutex_unlock(&adev->srbm_mutex);
1098
-
1099
1065
return 0;
1100
1066
}
1101
1067
···
1330
1320
1331
1321
mes_v11_0_enable(adev, true);
1332
1322
1323
+
mes_v11_0_get_fw_version(adev);
1324
+
1333
1325
mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring);
1334
1326
1335
1327
r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1336
1328
if (r)
1337
1329
goto failure;
1338
1330
1339
-
r = mes_v11_0_hw_init(adev);
1340
-
if (r)
1341
-
goto failure;
1331
+
if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47)
1332
+
adev->mes.enable_legacy_queue_map = true;
1333
+
else
1334
+
adev->mes.enable_legacy_queue_map = false;
1335
+
1336
+
if (adev->mes.enable_legacy_queue_map) {
1337
+
r = mes_v11_0_hw_init(adev);
1338
+
if (r)
1339
+
goto failure;
1340
+
}
1342
1341
1343
1342
return r;
1344
1343
+6
-3
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+6
-3
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
···
1266
1266
adev->mes.funcs = &mes_v12_0_funcs;
1267
1267
adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init;
1268
1268
adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;
1269
+
adev->mes.enable_legacy_queue_map = true;
1269
1270
1270
1271
adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE;
1271
1272
···
1423
1422
mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE);
1424
1423
}
1425
1424
1426
-
r = mes_v12_0_hw_init(adev);
1427
-
if (r)
1428
-
goto failure;
1425
+
if (adev->mes.enable_legacy_queue_map) {
1426
+
r = mes_v12_0_hw_init(adev);
1427
+
if (r)
1428
+
goto failure;
1429
+
}
1429
1430
1430
1431
return r;
1431
1432
+37
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+37
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
1752
1752
return bb;
1753
1753
}
1754
1754
1755
+
static enum dmub_ips_disable_type dm_get_default_ips_mode(
1756
+
struct amdgpu_device *adev)
1757
+
{
1758
+
/*
1759
+
* On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to
1760
+
* cause a hard hang. A fix exists for newer PMFW.
1761
+
*
1762
+
* As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest
1763
+
* IPS state in all cases, except for s0ix and all displays off (DPMS),
1764
+
* where IPS2 is allowed.
1765
+
*
1766
+
* When checking pmfw version, use the major and minor only.
1767
+
*/
1768
+
if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 5, 0) &&
1769
+
(adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)
1770
+
return DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1771
+
1772
+
if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0))
1773
+
return DMUB_IPS_ENABLE;
1774
+
1775
+
/* ASICs older than DCN35 do not have IPSs */
1776
+
return DMUB_IPS_DISABLE_ALL;
1777
+
}
1778
+
1755
1779
static int amdgpu_dm_init(struct amdgpu_device *adev)
1756
1780
{
1757
1781
struct dc_init_data init_data;
···
1887
1863
if (amdgpu_dc_debug_mask & DC_DISABLE_IPS)
1888
1864
init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
1889
1865
else
1890
-
init_data.flags.disable_ips = DMUB_IPS_ENABLE;
1866
+
init_data.flags.disable_ips = dm_get_default_ips_mode(adev);
1891
1867
1892
1868
init_data.flags.disable_ips_in_vpb = 0;
1893
1869
···
4516
4492
struct amdgpu_dm_backlight_caps caps;
4517
4493
struct dc_link *link;
4518
4494
u32 brightness;
4519
-
bool rc;
4495
+
bool rc, reallow_idle = false;
4520
4496
4521
4497
amdgpu_dm_update_backlight_caps(dm, bl_idx);
4522
4498
caps = dm->backlight_caps[bl_idx];
···
4529
4505
link = (struct dc_link *)dm->backlight_link[bl_idx];
4530
4506
4531
4507
/* Change brightness based on AUX property */
4508
+
mutex_lock(&dm->dc_lock);
4509
+
if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {
4510
+
dc_allow_idle_optimizations(dm->dc, false);
4511
+
reallow_idle = true;
4512
+
}
4513
+
4532
4514
if (caps.aux_support) {
4533
4515
rc = dc_link_set_backlight_level_nits(link, true, brightness,
4534
4516
AUX_BL_DEFAULT_TRANSITION_TIME_MS);
···
4545
4515
if (!rc)
4546
4516
DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4547
4517
}
4518
+
4519
+
if (dm->dc->caps.ips_support && reallow_idle)
4520
+
dc_allow_idle_optimizations(dm->dc, true);
4521
+
4522
+
mutex_unlock(&dm->dc_lock);
4548
4523
4549
4524
if (rc)
4550
4525
dm->actual_brightness[bl_idx] = user_brightness;
+2
-1
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+2
-1
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
···
811
811
for (j = i + 1; j < display_config->display_config.num_streams; j++) {
812
812
if (memcmp(master_timing,
813
813
&display_config->display_config.stream_descriptors[j].timing,
814
-
sizeof(struct dml2_timing_cfg)) == 0) {
814
+
sizeof(struct dml2_timing_cfg)) == 0 &&
815
+
display_config->display_config.stream_descriptors[i].output.output_encoder == display_config->display_config.stream_descriptors[j].output.output_encoder) {
815
816
set_bit_in_bitfield(&pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], j);
816
817
set_bit_in_bitfield(&stream_mapped_mask, j);
817
818
}
+4
-2
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+4
-2
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
···
2266
2266
smu_dpm_ctx->dpm_level = level;
2267
2267
}
2268
2268
2269
-
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2269
+
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2270
+
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2270
2271
index = fls(smu->workload_mask);
2271
2272
index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
2272
2273
workload[0] = smu->workload_setting[index];
···
2346
2345
workload[0] = smu->workload_setting[index];
2347
2346
}
2348
2347
2349
-
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
2348
+
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2349
+
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
2350
2350
smu_bump_power_profile_mode(smu, workload, 0);
2351
2351
2352
2352
return 0;
+7
-3
drivers/gpu/drm/arm/display/komeda/komeda_kms.c
+7
-3
drivers/gpu/drm/arm/display/komeda/komeda_kms.c
···
160
160
struct drm_plane *plane;
161
161
struct list_head zorder_list;
162
162
int order = 0, err;
163
+
u32 slave_zpos = 0;
163
164
164
165
DRM_DEBUG_ATOMIC("[CRTC:%d:%s] calculating normalized zpos values\n",
165
166
crtc->base.id, crtc->name);
···
200
199
plane_st->zpos, plane_st->normalized_zpos);
201
200
202
201
/* calculate max slave zorder */
203
-
if (has_bit(drm_plane_index(plane), kcrtc->slave_planes))
202
+
if (has_bit(drm_plane_index(plane), kcrtc->slave_planes)) {
203
+
slave_zpos = plane_st->normalized_zpos;
204
+
if (to_kplane_st(plane_st)->layer_split)
205
+
slave_zpos++;
204
206
kcrtc_st->max_slave_zorder =
205
-
max(plane_st->normalized_zpos,
206
-
kcrtc_st->max_slave_zorder);
207
+
max(slave_zpos, kcrtc_st->max_slave_zorder);
208
+
}
207
209
}
208
210
209
211
crtc_st->zpos_changed = true;
+1
drivers/gpu/drm/bridge/Kconfig
+1
drivers/gpu/drm/bridge/Kconfig
+14
-10
drivers/gpu/drm/display/Kconfig
+14
-10
drivers/gpu/drm/display/Kconfig
···
1
1
# SPDX-License-Identifier: MIT
2
2
3
+
config DRM_DISPLAY_DP_AUX_BUS
4
+
tristate
5
+
depends on DRM
6
+
depends on OF || COMPILE_TEST
7
+
3
8
config DRM_DISPLAY_HELPER
4
9
tristate
5
10
depends on DRM
6
11
help
7
12
DRM helpers for display adapters.
8
13
9
-
config DRM_DISPLAY_DP_AUX_BUS
10
-
tristate
11
-
depends on DRM
12
-
depends on OF || COMPILE_TEST
14
+
if DRM_DISPLAY_HELPER
15
+
16
+
config DRM_BRIDGE_CONNECTOR
17
+
bool
18
+
select DRM_DISPLAY_HDMI_STATE_HELPER
19
+
help
20
+
DRM connector implementation terminating DRM bridge chains.
13
21
14
22
config DRM_DISPLAY_DP_AUX_CEC
15
23
bool "Enable DisplayPort CEC-Tunneling-over-AUX HDMI support"
16
-
depends on DRM && DRM_DISPLAY_HELPER
17
24
select DRM_DISPLAY_DP_HELPER
18
25
select CEC_CORE
19
26
help
···
32
25
33
26
config DRM_DISPLAY_DP_AUX_CHARDEV
34
27
bool "DRM DP AUX Interface"
35
-
depends on DRM && DRM_DISPLAY_HELPER
36
28
select DRM_DISPLAY_DP_HELPER
37
29
help
38
30
Choose this option to enable a /dev/drm_dp_auxN node that allows to
···
40
34
41
35
config DRM_DISPLAY_DP_HELPER
42
36
bool
43
-
depends on DRM_DISPLAY_HELPER
44
37
help
45
38
DRM display helpers for DisplayPort.
46
39
···
66
61
67
62
config DRM_DISPLAY_HDCP_HELPER
68
63
bool
69
-
depends on DRM_DISPLAY_HELPER
70
64
help
71
65
DRM display helpers for HDCP.
72
66
73
67
config DRM_DISPLAY_HDMI_HELPER
74
68
bool
75
-
depends on DRM_DISPLAY_HELPER
76
69
help
77
70
DRM display helpers for HDMI.
78
71
79
72
config DRM_DISPLAY_HDMI_STATE_HELPER
80
73
bool
81
-
depends on DRM_DISPLAY_HELPER
82
74
select DRM_DISPLAY_HDMI_HELPER
83
75
help
84
76
DRM KMS state helpers for HDMI.
77
+
78
+
endif # DRM_DISPLAY_HELPER
+2
drivers/gpu/drm/display/Makefile
+2
drivers/gpu/drm/display/Makefile
···
3
3
obj-$(CONFIG_DRM_DISPLAY_DP_AUX_BUS) += drm_dp_aux_bus.o
4
4
5
5
drm_display_helper-y := drm_display_helper_mod.o
6
+
drm_display_helper-$(CONFIG_DRM_BRIDGE_CONNECTOR) += \
7
+
drm_bridge_connector.o
6
8
drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_HELPER) += \
7
9
drm_dp_dual_mode_helper.o \
8
10
drm_dp_helper.o \
+12
-1
drivers/gpu/drm/drm_bridge_connector.c
drivers/gpu/drm/display/drm_bridge_connector.c
+12
-1
drivers/gpu/drm/drm_bridge_connector.c
drivers/gpu/drm/display/drm_bridge_connector.c
···
216
216
}
217
217
}
218
218
219
+
static void drm_bridge_connector_reset(struct drm_connector *connector)
220
+
{
221
+
struct drm_bridge_connector *bridge_connector =
222
+
to_drm_bridge_connector(connector);
223
+
224
+
drm_atomic_helper_connector_reset(connector);
225
+
if (bridge_connector->bridge_hdmi)
226
+
__drm_atomic_helper_connector_hdmi_reset(connector,
227
+
connector->state);
228
+
}
229
+
219
230
static const struct drm_connector_funcs drm_bridge_connector_funcs = {
220
-
.reset = drm_atomic_helper_connector_reset,
231
+
.reset = drm_bridge_connector_reset,
221
232
.detect = drm_bridge_connector_detect,
222
233
.fill_modes = drm_helper_probe_single_connector_modes,
223
234
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+64
-19
drivers/gpu/drm/drm_fbdev_dma.c
+64
-19
drivers/gpu/drm/drm_fbdev_dma.c
···
36
36
return 0;
37
37
}
38
38
39
-
FB_GEN_DEFAULT_DEFERRED_DMAMEM_OPS(drm_fbdev_dma,
40
-
drm_fb_helper_damage_range,
41
-
drm_fb_helper_damage_area);
42
-
43
39
static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
44
40
{
45
41
struct drm_fb_helper *fb_helper = info->par;
46
-
struct drm_framebuffer *fb = fb_helper->fb;
47
-
struct drm_gem_dma_object *dma = drm_fb_dma_get_gem_obj(fb, 0);
48
42
49
-
if (!dma->map_noncoherent)
50
-
vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
51
-
52
-
return fb_deferred_io_mmap(info, vma);
43
+
return drm_gem_prime_mmap(fb_helper->buffer->gem, vma);
53
44
}
54
45
55
46
static void drm_fbdev_dma_fb_destroy(struct fb_info *info)
···
64
73
.owner = THIS_MODULE,
65
74
.fb_open = drm_fbdev_dma_fb_open,
66
75
.fb_release = drm_fbdev_dma_fb_release,
76
+
__FB_DEFAULT_DMAMEM_OPS_RDWR,
77
+
DRM_FB_HELPER_DEFAULT_OPS,
78
+
__FB_DEFAULT_DMAMEM_OPS_DRAW,
79
+
.fb_mmap = drm_fbdev_dma_fb_mmap,
80
+
.fb_destroy = drm_fbdev_dma_fb_destroy,
81
+
};
82
+
83
+
FB_GEN_DEFAULT_DEFERRED_DMAMEM_OPS(drm_fbdev_dma,
84
+
drm_fb_helper_damage_range,
85
+
drm_fb_helper_damage_area);
86
+
87
+
static int drm_fbdev_dma_deferred_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
88
+
{
89
+
struct drm_fb_helper *fb_helper = info->par;
90
+
struct drm_framebuffer *fb = fb_helper->fb;
91
+
struct drm_gem_dma_object *dma = drm_fb_dma_get_gem_obj(fb, 0);
92
+
93
+
if (!dma->map_noncoherent)
94
+
vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
95
+
96
+
return fb_deferred_io_mmap(info, vma);
97
+
}
98
+
99
+
static const struct fb_ops drm_fbdev_dma_deferred_fb_ops = {
100
+
.owner = THIS_MODULE,
101
+
.fb_open = drm_fbdev_dma_fb_open,
102
+
.fb_release = drm_fbdev_dma_fb_release,
67
103
__FB_DEFAULT_DEFERRED_OPS_RDWR(drm_fbdev_dma),
68
104
DRM_FB_HELPER_DEFAULT_OPS,
69
105
__FB_DEFAULT_DEFERRED_OPS_DRAW(drm_fbdev_dma),
70
-
.fb_mmap = drm_fbdev_dma_fb_mmap,
106
+
.fb_mmap = drm_fbdev_dma_deferred_fb_mmap,
71
107
.fb_destroy = drm_fbdev_dma_fb_destroy,
72
108
};
73
109
···
107
89
{
108
90
struct drm_client_dev *client = &fb_helper->client;
109
91
struct drm_device *dev = fb_helper->dev;
92
+
bool use_deferred_io = false;
110
93
struct drm_client_buffer *buffer;
111
94
struct drm_gem_dma_object *dma_obj;
112
95
struct drm_framebuffer *fb;
···
130
111
131
112
fb = buffer->fb;
132
113
114
+
/*
115
+
* Deferred I/O requires struct page for framebuffer memory,
116
+
* which is not guaranteed for all DMA ranges. We thus only
117
+
* install deferred I/O if we have a framebuffer that requires
118
+
* it.
119
+
*/
120
+
if (fb->funcs->dirty)
121
+
use_deferred_io = true;
122
+
133
123
ret = drm_client_buffer_vmap(buffer, &map);
134
124
if (ret) {
135
125
goto err_drm_client_buffer_delete;
···
158
130
159
131
drm_fb_helper_fill_info(info, fb_helper, sizes);
160
132
161
-
info->fbops = &drm_fbdev_dma_fb_ops;
133
+
if (use_deferred_io)
134
+
info->fbops = &drm_fbdev_dma_deferred_fb_ops;
135
+
else
136
+
info->fbops = &drm_fbdev_dma_fb_ops;
162
137
163
138
/* screen */
164
139
info->flags |= FBINFO_VIRTFB; /* system memory */
···
175
144
}
176
145
info->fix.smem_len = info->screen_size;
177
146
178
-
/* deferred I/O */
179
-
fb_helper->fbdefio.delay = HZ / 20;
180
-
fb_helper->fbdefio.deferred_io = drm_fb_helper_deferred_io;
147
+
/*
148
+
* Only set up deferred I/O if the screen buffer supports
149
+
* it. If this disagrees with the previous test for ->dirty,
150
+
* mmap on the /dev/fb file might not work correctly.
151
+
*/
152
+
if (!is_vmalloc_addr(info->screen_buffer) && info->fix.smem_start) {
153
+
unsigned long pfn = info->fix.smem_start >> PAGE_SHIFT;
181
154
182
-
info->fbdefio = &fb_helper->fbdefio;
183
-
ret = fb_deferred_io_init(info);
184
-
if (ret)
185
-
goto err_drm_fb_helper_release_info;
155
+
if (drm_WARN_ON(dev, !pfn_to_page(pfn)))
156
+
use_deferred_io = false;
157
+
}
158
+
159
+
/* deferred I/O */
160
+
if (use_deferred_io) {
161
+
fb_helper->fbdefio.delay = HZ / 20;
162
+
fb_helper->fbdefio.deferred_io = drm_fb_helper_deferred_io;
163
+
164
+
info->fbdefio = &fb_helper->fbdefio;
165
+
ret = fb_deferred_io_init(info);
166
+
if (ret)
167
+
goto err_drm_fb_helper_release_info;
168
+
}
186
169
187
170
return 0;
188
171
+1
-1
drivers/gpu/drm/i915/display/intel_alpm.c
+1
-1
drivers/gpu/drm/i915/display/intel_alpm.c
···
228
228
int tfw_exit_latency = 20; /* eDP spec */
229
229
int phy_wake = 4; /* eDP spec */
230
230
int preamble = 8; /* eDP spec */
231
-
int precharge = intel_dp_aux_fw_sync_len() - preamble;
231
+
int precharge = intel_dp_aux_fw_sync_len(intel_dp) - preamble;
232
232
u8 max_wake_lines;
233
233
234
234
io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) +
+4
drivers/gpu/drm/i915/display/intel_display_types.h
+4
drivers/gpu/drm/i915/display/intel_display_types.h
+4
drivers/gpu/drm/i915/display/intel_dp.c
+4
drivers/gpu/drm/i915/display/intel_dp.c
···
82
82
#include "intel_pch_display.h"
83
83
#include "intel_pps.h"
84
84
#include "intel_psr.h"
85
+
#include "intel_quirks.h"
85
86
#include "intel_tc.h"
86
87
#include "intel_vdsc.h"
87
88
#include "intel_vrr.h"
···
3953
3952
3954
3953
drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3955
3954
drm_dp_is_branch(intel_dp->dpcd));
3955
+
intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);
3956
3956
3957
3957
/*
3958
3958
* Read the eDP display control registers.
···
4065
4063
if (!intel_dp_is_edp(intel_dp)) {
4066
4064
drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4067
4065
drm_dp_is_branch(intel_dp->dpcd));
4066
+
4067
+
intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);
4068
4068
4069
4069
intel_dp_update_sink_caps(intel_dp);
4070
4070
}
+11
-5
drivers/gpu/drm/i915/display/intel_dp_aux.c
+11
-5
drivers/gpu/drm/i915/display/intel_dp_aux.c
···
13
13
#include "intel_dp_aux.h"
14
14
#include "intel_dp_aux_regs.h"
15
15
#include "intel_pps.h"
16
+
#include "intel_quirks.h"
16
17
#include "intel_tc.h"
17
18
18
19
#define AUX_CH_NAME_BUFSIZE 6
···
143
142
return precharge + preamble;
144
143
}
145
144
146
-
int intel_dp_aux_fw_sync_len(void)
145
+
int intel_dp_aux_fw_sync_len(struct intel_dp *intel_dp)
147
146
{
147
+
int precharge = 10; /* 10-16 */
148
+
int preamble = 8;
149
+
148
150
/*
149
151
* We faced some glitches on Dell Precision 5490 MTL laptop with panel:
150
152
* "Manufacturer: AUO, Model: 63898" when using HW default 18. Using 20
151
153
* is fixing these problems with the panel. It is still within range
152
-
* mentioned in eDP specification.
154
+
* mentioned in eDP specification. Increasing Fast Wake sync length is
155
+
* causing problems with other panels: increase length as a quirk for
156
+
* this specific laptop.
153
157
*/
154
-
int precharge = 12; /* 10-16 */
155
-
int preamble = 8;
158
+
if (intel_has_dpcd_quirk(intel_dp, QUIRK_FW_SYNC_LEN))
159
+
precharge += 2;
156
160
157
161
return precharge + preamble;
158
162
}
···
217
211
DP_AUX_CH_CTL_TIME_OUT_MAX |
218
212
DP_AUX_CH_CTL_RECEIVE_ERROR |
219
213
DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) |
220
-
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len()) |
214
+
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len(intel_dp)) |
221
215
DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len());
222
216
223
217
if (intel_tc_port_in_tbt_alt_mode(dig_port))
+1
-1
drivers/gpu/drm/i915/display/intel_dp_aux.h
+1
-1
drivers/gpu/drm/i915/display/intel_dp_aux.h
+26
-5
drivers/gpu/drm/i915/display/intel_modeset_setup.c
+26
-5
drivers/gpu/drm/i915/display/intel_modeset_setup.c
···
326
326
327
327
static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
328
328
{
329
+
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
330
+
329
331
if (intel_crtc_is_joiner_secondary(crtc_state))
330
332
return;
331
333
···
339
337
crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
340
338
crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
341
339
342
-
/* assume 1:1 mapping */
343
-
drm_property_replace_blob(&crtc_state->hw.degamma_lut,
344
-
crtc_state->pre_csc_lut);
345
-
drm_property_replace_blob(&crtc_state->hw.gamma_lut,
346
-
crtc_state->post_csc_lut);
340
+
if (DISPLAY_INFO(i915)->color.degamma_lut_size) {
341
+
/* assume 1:1 mapping */
342
+
drm_property_replace_blob(&crtc_state->hw.degamma_lut,
343
+
crtc_state->pre_csc_lut);
344
+
drm_property_replace_blob(&crtc_state->hw.gamma_lut,
345
+
crtc_state->post_csc_lut);
346
+
} else {
347
+
/*
348
+
* ilk/snb hw may be configured for either pre_csc_lut
349
+
* or post_csc_lut, but we don't advertise degamma_lut as
350
+
* being available in the uapi since there is only one
351
+
* hardware LUT. Always assign the result of the readout
352
+
* to gamma_lut as that is the only valid source of LUTs
353
+
* in the uapi.
354
+
*/
355
+
drm_WARN_ON(&i915->drm, crtc_state->post_csc_lut &&
356
+
crtc_state->pre_csc_lut);
357
+
358
+
drm_property_replace_blob(&crtc_state->hw.degamma_lut,
359
+
NULL);
360
+
drm_property_replace_blob(&crtc_state->hw.gamma_lut,
361
+
crtc_state->post_csc_lut ?:
362
+
crtc_state->pre_csc_lut);
363
+
}
347
364
348
365
drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
349
366
crtc_state->hw.degamma_lut);
+68
drivers/gpu/drm/i915/display/intel_quirks.c
+68
drivers/gpu/drm/i915/display/intel_quirks.c
···
14
14
display->quirks.mask |= BIT(quirk);
15
15
}
16
16
17
+
static void intel_set_dpcd_quirk(struct intel_dp *intel_dp, enum intel_quirk_id quirk)
18
+
{
19
+
intel_dp->quirks.mask |= BIT(quirk);
20
+
}
21
+
17
22
/*
18
23
* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
19
24
*/
···
70
65
drm_info(display->drm, "Applying no pps backlight power quirk\n");
71
66
}
72
67
68
+
static void quirk_fw_sync_len(struct intel_dp *intel_dp)
69
+
{
70
+
struct intel_display *display = to_intel_display(intel_dp);
71
+
72
+
intel_set_dpcd_quirk(intel_dp, QUIRK_FW_SYNC_LEN);
73
+
drm_info(display->drm, "Applying Fast Wake sync pulse count quirk\n");
74
+
}
75
+
73
76
struct intel_quirk {
74
77
int device;
75
78
int subsystem_vendor;
76
79
int subsystem_device;
77
80
void (*hook)(struct intel_display *display);
78
81
};
82
+
83
+
struct intel_dpcd_quirk {
84
+
int device;
85
+
int subsystem_vendor;
86
+
int subsystem_device;
87
+
u8 sink_oui[3];
88
+
u8 sink_device_id[6];
89
+
void (*hook)(struct intel_dp *intel_dp);
90
+
};
91
+
92
+
#define SINK_OUI(first, second, third) { (first), (second), (third) }
93
+
#define SINK_DEVICE_ID(first, second, third, fourth, fifth, sixth) \
94
+
{ (first), (second), (third), (fourth), (fifth), (sixth) }
95
+
96
+
#define SINK_DEVICE_ID_ANY SINK_DEVICE_ID(0, 0, 0, 0, 0, 0)
79
97
80
98
/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
81
99
struct intel_dmi_quirk {
···
231
203
{ 0x0f31, 0x103c, 0x220f, quirk_invert_brightness },
232
204
};
233
205
206
+
static struct intel_dpcd_quirk intel_dpcd_quirks[] = {
207
+
/* Dell Precision 5490 */
208
+
{
209
+
.device = 0x7d55,
210
+
.subsystem_vendor = 0x1028,
211
+
.subsystem_device = 0x0cc7,
212
+
.sink_oui = SINK_OUI(0x38, 0xec, 0x11),
213
+
.hook = quirk_fw_sync_len,
214
+
},
215
+
216
+
};
217
+
234
218
void intel_init_quirks(struct intel_display *display)
235
219
{
236
220
struct pci_dev *d = to_pci_dev(display->drm->dev);
···
264
224
}
265
225
}
266
226
227
+
void intel_init_dpcd_quirks(struct intel_dp *intel_dp,
228
+
const struct drm_dp_dpcd_ident *ident)
229
+
{
230
+
struct intel_display *display = to_intel_display(intel_dp);
231
+
struct pci_dev *d = to_pci_dev(display->drm->dev);
232
+
int i;
233
+
234
+
for (i = 0; i < ARRAY_SIZE(intel_dpcd_quirks); i++) {
235
+
struct intel_dpcd_quirk *q = &intel_dpcd_quirks[i];
236
+
237
+
if (d->device == q->device &&
238
+
(d->subsystem_vendor == q->subsystem_vendor ||
239
+
q->subsystem_vendor == PCI_ANY_ID) &&
240
+
(d->subsystem_device == q->subsystem_device ||
241
+
q->subsystem_device == PCI_ANY_ID) &&
242
+
!memcmp(q->sink_oui, ident->oui, sizeof(ident->oui)) &&
243
+
(!memcmp(q->sink_device_id, ident->device_id,
244
+
sizeof(ident->device_id)) ||
245
+
!memchr_inv(q->sink_device_id, 0, sizeof(q->sink_device_id))))
246
+
q->hook(intel_dp);
247
+
}
248
+
}
249
+
267
250
bool intel_has_quirk(struct intel_display *display, enum intel_quirk_id quirk)
268
251
{
269
252
return display->quirks.mask & BIT(quirk);
253
+
}
254
+
255
+
bool intel_has_dpcd_quirk(struct intel_dp *intel_dp, enum intel_quirk_id quirk)
256
+
{
257
+
return intel_dp->quirks.mask & BIT(quirk);
270
258
}
+6
drivers/gpu/drm/i915/display/intel_quirks.h
+6
drivers/gpu/drm/i915/display/intel_quirks.h
···
9
9
#include <linux/types.h>
10
10
11
11
struct intel_display;
12
+
struct intel_dp;
13
+
struct drm_dp_dpcd_ident;
12
14
13
15
enum intel_quirk_id {
14
16
QUIRK_BACKLIGHT_PRESENT,
···
19
17
QUIRK_INVERT_BRIGHTNESS,
20
18
QUIRK_LVDS_SSC_DISABLE,
21
19
QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK,
20
+
QUIRK_FW_SYNC_LEN,
22
21
};
23
22
24
23
void intel_init_quirks(struct intel_display *display);
24
+
void intel_init_dpcd_quirks(struct intel_dp *intel_dp,
25
+
const struct drm_dp_dpcd_ident *ident);
25
26
bool intel_has_quirk(struct intel_display *display, enum intel_quirk_id quirk);
27
+
bool intel_has_dpcd_quirk(struct intel_dp *intel_dp, enum intel_quirk_id quirk);
26
28
27
29
#endif /* __INTEL_QUIRKS_H__ */
+1
-1
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
+1
-1
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
+5
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
+5
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
···
258
258
return __intel_uc_fw_status(uc_fw) == INTEL_UC_FIRMWARE_RUNNING;
259
259
}
260
260
261
+
static inline bool intel_uc_fw_is_in_error(struct intel_uc_fw *uc_fw)
262
+
{
263
+
return intel_uc_fw_status_to_error(__intel_uc_fw_status(uc_fw)) != 0;
264
+
}
265
+
261
266
static inline bool intel_uc_fw_is_overridden(const struct intel_uc_fw *uc_fw)
262
267
{
263
268
return uc_fw->user_overridden;
+4
-4
drivers/gpu/drm/i915/i915_sw_fence.c
+4
-4
drivers/gpu/drm/i915/i915_sw_fence.c
···
51
51
debug_object_init(fence, &i915_sw_fence_debug_descr);
52
52
}
53
53
54
-
static inline void debug_fence_init_onstack(struct i915_sw_fence *fence)
54
+
static inline __maybe_unused void debug_fence_init_onstack(struct i915_sw_fence *fence)
55
55
{
56
56
debug_object_init_on_stack(fence, &i915_sw_fence_debug_descr);
57
57
}
···
77
77
debug_object_destroy(fence, &i915_sw_fence_debug_descr);
78
78
}
79
79
80
-
static inline void debug_fence_free(struct i915_sw_fence *fence)
80
+
static inline __maybe_unused void debug_fence_free(struct i915_sw_fence *fence)
81
81
{
82
82
debug_object_free(fence, &i915_sw_fence_debug_descr);
83
83
smp_wmb(); /* flush the change in state before reallocation */
···
94
94
{
95
95
}
96
96
97
-
static inline void debug_fence_init_onstack(struct i915_sw_fence *fence)
97
+
static inline __maybe_unused void debug_fence_init_onstack(struct i915_sw_fence *fence)
98
98
{
99
99
}
100
100
···
115
115
{
116
116
}
117
117
118
-
static inline void debug_fence_free(struct i915_sw_fence *fence)
118
+
static inline __maybe_unused void debug_fence_free(struct i915_sw_fence *fence)
119
119
{
120
120
}
121
121
+4
drivers/gpu/drm/imagination/pvr_vm.c
+4
drivers/gpu/drm/imagination/pvr_vm.c
···
114
114
struct drm_gpuva base;
115
115
};
116
116
117
+
#define to_pvr_vm_gpuva(va) container_of_const(va, struct pvr_vm_gpuva, base)
118
+
117
119
enum pvr_vm_bind_type {
118
120
PVR_VM_BIND_TYPE_MAP,
119
121
PVR_VM_BIND_TYPE_UNMAP,
···
388
386
389
387
drm_gpuva_unmap(&op->unmap);
390
388
drm_gpuva_unlink(op->unmap.va);
389
+
kfree(to_pvr_vm_gpuva(op->unmap.va));
391
390
392
391
return 0;
393
392
}
···
436
433
}
437
434
438
435
drm_gpuva_unlink(op->remap.unmap->va);
436
+
kfree(to_pvr_vm_gpuva(op->remap.unmap->va));
439
437
440
438
return 0;
441
439
}
+2
drivers/gpu/drm/imx/dcss/Kconfig
+2
drivers/gpu/drm/imx/dcss/Kconfig
+2
drivers/gpu/drm/imx/lcdc/Kconfig
+2
drivers/gpu/drm/imx/lcdc/Kconfig
+2
drivers/gpu/drm/ingenic/Kconfig
+2
drivers/gpu/drm/ingenic/Kconfig
+2
drivers/gpu/drm/kmb/Kconfig
+2
drivers/gpu/drm/kmb/Kconfig
+2
drivers/gpu/drm/mediatek/Kconfig
+2
drivers/gpu/drm/mediatek/Kconfig
+2
drivers/gpu/drm/meson/Kconfig
+2
drivers/gpu/drm/meson/Kconfig
+1
drivers/gpu/drm/msm/Kconfig
+1
drivers/gpu/drm/msm/Kconfig
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/fwsec.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/fwsec.c
+2
drivers/gpu/drm/omapdrm/Kconfig
+2
drivers/gpu/drm/omapdrm/Kconfig
···
5
5
depends on DRM && OF
6
6
depends on ARCH_OMAP2PLUS || (COMPILE_TEST && PAGE_SIZE_LESS_THAN_64KB)
7
7
select DRM_KMS_HELPER
8
+
select DRM_DISPLAY_HELPER
9
+
select DRM_BRIDGE_CONNECTOR
8
10
select FB_DMAMEM_HELPERS_DEFERRED if DRM_FBDEV_EMULATION
9
11
select VIDEOMODE_HELPERS
10
12
select HDMI
+1
-1
drivers/gpu/drm/panel/panel-newvision-nv3052c.c
+1
-1
drivers/gpu/drm/panel/panel-newvision-nv3052c.c
···
925
925
static const struct of_device_id nv3052c_of_match[] = {
926
926
{ .compatible = "leadtek,ltk035c5444t", .data = <k035c5444t_panel_info },
927
927
{ .compatible = "fascontek,fs035vg158", .data = &fs035vg158_panel_info },
928
-
{ .compatible = "wl-355608-a8", .data = &wl_355608_a8_panel_info },
928
+
{ .compatible = "anbernic,rg35xx-plus-panel", .data = &wl_355608_a8_panel_info },
929
929
{ /* sentinel */ }
930
930
};
931
931
MODULE_DEVICE_TABLE(of, nv3052c_of_match);
+23
drivers/gpu/drm/panthor/panthor_drv.c
+23
drivers/gpu/drm/panthor/panthor_drv.c
···
10
10
#include <linux/platform_device.h>
11
11
#include <linux/pm_runtime.h>
12
12
13
+
#include <drm/drm_auth.h>
13
14
#include <drm/drm_debugfs.h>
14
15
#include <drm/drm_drv.h>
15
16
#include <drm/drm_exec.h>
···
997
996
return panthor_group_destroy(pfile, args->group_handle);
998
997
}
999
998
999
+
static int group_priority_permit(struct drm_file *file,
1000
+
u8 priority)
1001
+
{
1002
+
/* Ensure that priority is valid */
1003
+
if (priority > PANTHOR_GROUP_PRIORITY_HIGH)
1004
+
return -EINVAL;
1005
+
1006
+
/* Medium priority and below are always allowed */
1007
+
if (priority <= PANTHOR_GROUP_PRIORITY_MEDIUM)
1008
+
return 0;
1009
+
1010
+
/* Higher priorities require CAP_SYS_NICE or DRM_MASTER */
1011
+
if (capable(CAP_SYS_NICE) || drm_is_current_master(file))
1012
+
return 0;
1013
+
1014
+
return -EACCES;
1015
+
}
1016
+
1000
1017
static int panthor_ioctl_group_create(struct drm_device *ddev, void *data,
1001
1018
struct drm_file *file)
1002
1019
{
···
1027
1008
return -EINVAL;
1028
1009
1029
1010
ret = PANTHOR_UOBJ_GET_ARRAY(queue_args, &args->queues);
1011
+
if (ret)
1012
+
return ret;
1013
+
1014
+
ret = group_priority_permit(file, args->priority);
1030
1015
if (ret)
1031
1016
return ret;
1032
1017
+7
-1
drivers/gpu/drm/panthor/panthor_fw.c
+7
-1
drivers/gpu/drm/panthor/panthor_fw.c
···
1089
1089
panthor_fw_stop(ptdev);
1090
1090
ptdev->fw->fast_reset = false;
1091
1091
drm_err(&ptdev->base, "FW fast reset failed, trying a slow reset");
1092
+
1093
+
ret = panthor_vm_flush_all(ptdev->fw->vm);
1094
+
if (ret) {
1095
+
drm_err(&ptdev->base, "FW slow reset failed (couldn't flush FW's AS l2cache)");
1096
+
return ret;
1097
+
}
1092
1098
}
1093
1099
1094
1100
/* Reload all sections, including RO ones. We're not supposed
···
1105
1099
1106
1100
ret = panthor_fw_start(ptdev);
1107
1101
if (ret) {
1108
-
drm_err(&ptdev->base, "FW slow reset failed");
1102
+
drm_err(&ptdev->base, "FW slow reset failed (couldn't start the FW )");
1109
1103
return ret;
1110
1104
}
1111
1105
+18
-3
drivers/gpu/drm/panthor/panthor_mmu.c
+18
-3
drivers/gpu/drm/panthor/panthor_mmu.c
···
576
576
if (as_nr < 0)
577
577
return 0;
578
578
579
+
/*
580
+
* If the AS number is greater than zero, then we can be sure
581
+
* the device is up and running, so we don't need to explicitly
582
+
* power it up
583
+
*/
584
+
579
585
if (op != AS_COMMAND_UNLOCK)
580
586
lock_region(ptdev, as_nr, iova, size);
581
587
···
880
874
if (!drm_dev_enter(&ptdev->base, &cookie))
881
875
return 0;
882
876
883
-
/* Flush the PTs only if we're already awake */
884
-
if (pm_runtime_active(ptdev->base.dev))
885
-
ret = mmu_hw_do_operation(vm, iova, size, AS_COMMAND_FLUSH_PT);
877
+
ret = mmu_hw_do_operation(vm, iova, size, AS_COMMAND_FLUSH_PT);
886
878
887
879
drm_dev_exit(cookie);
888
880
return ret;
881
+
}
882
+
883
+
/**
884
+
* panthor_vm_flush_all() - Flush L2 caches for the entirety of a VM's AS
885
+
* @vm: VM whose cache to flush
886
+
*
887
+
* Return: 0 on success, a negative error code if flush failed.
888
+
*/
889
+
int panthor_vm_flush_all(struct panthor_vm *vm)
890
+
{
891
+
return panthor_vm_flush_range(vm, vm->base.mm_start, vm->base.mm_range);
889
892
}
890
893
891
894
static int panthor_vm_unmap_pages(struct panthor_vm *vm, u64 iova, u64 size)
+1
drivers/gpu/drm/panthor/panthor_mmu.h
+1
drivers/gpu/drm/panthor/panthor_mmu.h
···
31
31
int panthor_vm_active(struct panthor_vm *vm);
32
32
void panthor_vm_idle(struct panthor_vm *vm);
33
33
int panthor_vm_as(struct panthor_vm *vm);
34
+
int panthor_vm_flush_all(struct panthor_vm *vm);
34
35
35
36
struct panthor_heap_pool *
36
37
panthor_vm_get_heap_pool(struct panthor_vm *vm, bool create);
+1
-1
drivers/gpu/drm/panthor/panthor_sched.c
+1
-1
drivers/gpu/drm/panthor/panthor_sched.c
···
3092
3092
if (group_args->pad)
3093
3093
return -EINVAL;
3094
3094
3095
-
if (group_args->priority > PANTHOR_CSG_PRIORITY_HIGH)
3095
+
if (group_args->priority >= PANTHOR_CSG_PRIORITY_COUNT)
3096
3096
return -EINVAL;
3097
3097
3098
3098
if ((group_args->compute_core_mask & ~ptdev->gpu_info.shader_present) ||
+2
drivers/gpu/drm/renesas/rcar-du/Kconfig
+2
drivers/gpu/drm/renesas/rcar-du/Kconfig
+2
drivers/gpu/drm/renesas/rz-du/Kconfig
+2
drivers/gpu/drm/renesas/rz-du/Kconfig
+2
drivers/gpu/drm/renesas/shmobile/Kconfig
+2
drivers/gpu/drm/renesas/shmobile/Kconfig
+4
drivers/gpu/drm/rockchip/Kconfig
+4
drivers/gpu/drm/rockchip/Kconfig
···
86
86
bool "Rockchip LVDS support"
87
87
depends on DRM_ROCKCHIP
88
88
depends on PINCTRL && OF
89
+
select DRM_DISPLAY_HELPER
90
+
select DRM_BRIDGE_CONNECTOR
89
91
help
90
92
Choose this option to enable support for Rockchip LVDS controllers.
91
93
Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
···
98
96
bool "Rockchip RGB support"
99
97
depends on DRM_ROCKCHIP
100
98
depends on PINCTRL
99
+
select DRM_DISPLAY_HELPER
100
+
select DRM_BRIDGE_CONNECTOR
101
101
help
102
102
Choose this option to enable support for Rockchip RGB output.
103
103
Some Rockchip CRTCs, like rv1108, can directly output parallel
+1
drivers/gpu/drm/tegra/Kconfig
+1
drivers/gpu/drm/tegra/Kconfig
+2
drivers/gpu/drm/tidss/Kconfig
+2
drivers/gpu/drm/tidss/Kconfig
+4
-4
drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
+4
-4
drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
···
13
13
snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
14
14
int fast_timeout_us, int slow_timeout_ms)
15
15
{
16
-
return xe_pcode_write_timeout(__compat_uncore_to_gt(uncore), mbox, val,
16
+
return xe_pcode_write_timeout(__compat_uncore_to_tile(uncore), mbox, val,
17
17
slow_timeout_ms ?: 1);
18
18
}
19
19
···
21
21
snb_pcode_write(struct intel_uncore *uncore, u32 mbox, u32 val)
22
22
{
23
23
24
-
return xe_pcode_write(__compat_uncore_to_gt(uncore), mbox, val);
24
+
return xe_pcode_write(__compat_uncore_to_tile(uncore), mbox, val);
25
25
}
26
26
27
27
static inline int
28
28
snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
29
29
{
30
-
return xe_pcode_read(__compat_uncore_to_gt(uncore), mbox, val, val1);
30
+
return xe_pcode_read(__compat_uncore_to_tile(uncore), mbox, val, val1);
31
31
}
32
32
33
33
static inline int
···
35
35
u32 request, u32 reply_mask, u32 reply,
36
36
int timeout_base_ms)
37
37
{
38
-
return xe_pcode_request(__compat_uncore_to_gt(uncore), mbox, request, reply_mask, reply,
38
+
return xe_pcode_request(__compat_uncore_to_tile(uncore), mbox, request, reply_mask, reply,
39
39
timeout_base_ms);
40
40
}
41
41
+7
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
+7
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
···
17
17
return xe_root_mmio_gt(xe);
18
18
}
19
19
20
+
static inline struct xe_tile *__compat_uncore_to_tile(struct intel_uncore *uncore)
21
+
{
22
+
struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
23
+
24
+
return xe_device_get_root_tile(xe);
25
+
}
26
+
20
27
static inline u32 intel_uncore_read(struct intel_uncore *uncore,
21
28
i915_reg_t i915_reg)
22
29
{
+17
-6
drivers/gpu/drm/xe/display/xe_display.c
+17
-6
drivers/gpu/drm/xe/display/xe_display.c
···
315
315
* properly.
316
316
*/
317
317
intel_power_domains_disable(xe);
318
-
if (has_display(xe))
318
+
intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_SUSPENDED, true);
319
+
if (has_display(xe)) {
319
320
drm_kms_helper_poll_disable(&xe->drm);
321
+
if (!runtime)
322
+
intel_display_driver_disable_user_access(xe);
323
+
}
320
324
321
325
if (!runtime)
322
326
intel_display_driver_suspend(xe);
···
331
327
332
328
intel_hpd_cancel_work(xe);
333
329
334
-
intel_encoder_suspend_all(&xe->display);
330
+
if (!runtime && has_display(xe)) {
331
+
intel_display_driver_suspend_access(xe);
332
+
intel_encoder_suspend_all(&xe->display);
333
+
}
335
334
336
335
intel_opregion_suspend(xe, s2idle ? PCI_D1 : PCI_D3cold);
337
-
338
-
intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_SUSPENDED, true);
339
336
340
337
intel_dmc_suspend(xe);
341
338
}
···
375
370
intel_display_driver_init_hw(xe);
376
371
intel_hpd_init(xe);
377
372
373
+
if (!runtime && has_display(xe))
374
+
intel_display_driver_resume_access(xe);
375
+
378
376
/* MST sideband requires HPD interrupts enabled */
379
377
intel_dp_mst_resume(xe);
380
378
if (!runtime)
381
379
intel_display_driver_resume(xe);
382
380
383
-
intel_hpd_poll_disable(xe);
384
-
if (has_display(xe))
381
+
if (has_display(xe)) {
385
382
drm_kms_helper_poll_enable(&xe->drm);
383
+
if (!runtime)
384
+
intel_display_driver_enable_user_access(xe);
385
+
}
386
+
intel_hpd_poll_disable(xe);
386
387
387
388
intel_opregion_resume(xe);
388
389
+6
drivers/gpu/drm/xe/xe_device_types.h
+6
drivers/gpu/drm/xe/xe_device_types.h
···
203
203
} vf;
204
204
} sriov;
205
205
206
+
/** @pcode: tile's PCODE */
207
+
struct {
208
+
/** @pcode.lock: protecting tile's PCODE mailbox data */
209
+
struct mutex lock;
210
+
} pcode;
211
+
206
212
/** @migrate: Migration helper for vram blits and clearing */
207
213
struct xe_migrate *migrate;
208
214
+12
drivers/gpu/drm/xe/xe_gsc.c
+12
drivers/gpu/drm/xe/xe_gsc.c
···
519
519
void xe_gsc_load_start(struct xe_gsc *gsc)
520
520
{
521
521
struct xe_gt *gt = gsc_to_gt(gsc);
522
+
struct xe_device *xe = gt_to_xe(gt);
522
523
523
524
if (!xe_uc_fw_is_loadable(&gsc->fw) || !gsc->q)
525
+
return;
526
+
527
+
/*
528
+
* The GSC HW is only reset by driver FLR or D3cold entry. We don't
529
+
* support the former at runtime, while the latter is only supported on
530
+
* DGFX, for which we don't support GSC. Therefore, if GSC failed to
531
+
* load previously there is no need to try again because the HW is
532
+
* stuck in the error state.
533
+
*/
534
+
xe_assert(xe, !IS_DGFX(xe));
535
+
if (xe_uc_fw_is_in_error_state(&gsc->fw))
524
536
return;
525
537
526
538
/* GSC FW survives GT reset and D3Hot */
+3
-4
drivers/gpu/drm/xe/xe_gt.c
+3
-4
drivers/gpu/drm/xe/xe_gt.c
···
47
47
#include "xe_migrate.h"
48
48
#include "xe_mmio.h"
49
49
#include "xe_pat.h"
50
-
#include "xe_pcode.h"
51
50
#include "xe_pm.h"
52
51
#include "xe_mocs.h"
53
52
#include "xe_reg_sr.h"
···
386
387
xe_tuning_process_gt(gt);
387
388
388
389
xe_force_wake_init_gt(gt, gt_to_fw(gt));
389
-
xe_pcode_init(gt);
390
390
spin_lock_init(>->global_invl_lock);
391
391
392
392
return 0;
···
753
755
754
756
xe_gt_info(gt, "reset started\n");
755
757
758
+
xe_pm_runtime_get(gt_to_xe(gt));
759
+
756
760
if (xe_fault_inject_gt_reset()) {
757
761
err = -ECANCELED;
758
762
goto err_fail;
759
763
}
760
764
761
-
xe_pm_runtime_get(gt_to_xe(gt));
762
765
xe_gt_sanitize(gt);
763
766
764
767
err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
···
794
795
XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));
795
796
err_msg:
796
797
XE_WARN_ON(xe_uc_start(>->uc));
797
-
xe_pm_runtime_put(gt_to_xe(gt));
798
798
err_fail:
799
799
xe_gt_err(gt, "reset failed (%pe)\n", ERR_PTR(err));
800
800
801
801
xe_device_declare_wedged(gt_to_xe(gt));
802
+
xe_pm_runtime_put(gt_to_xe(gt));
802
803
803
804
return err;
804
805
}
-6
drivers/gpu/drm/xe/xe_gt_types.h
-6
drivers/gpu/drm/xe/xe_gt_types.h
···
310
310
/** @eclass: per hardware engine class interface on the GT */
311
311
struct xe_hw_engine_class_intf eclass[XE_ENGINE_CLASS_MAX];
312
312
313
-
/** @pcode: GT's PCODE */
314
-
struct {
315
-
/** @pcode.lock: protecting GT's PCODE mailbox data */
316
-
struct mutex lock;
317
-
} pcode;
318
-
319
313
/** @sysfs: sysfs' kobj used by xe_gt_sysfs */
320
314
struct kobject *sysfs;
321
315
+1
-1
drivers/gpu/drm/xe/xe_guc_pc.c
+1
-1
drivers/gpu/drm/xe/xe_guc_pc.c
···
915
915
u32 min = DIV_ROUND_CLOSEST(pc->rpn_freq, GT_FREQUENCY_MULTIPLIER);
916
916
u32 max = DIV_ROUND_CLOSEST(pc->rp0_freq, GT_FREQUENCY_MULTIPLIER);
917
917
918
-
XE_WARN_ON(xe_pcode_init_min_freq_table(pc_to_gt(pc), min, max));
918
+
XE_WARN_ON(xe_pcode_init_min_freq_table(gt_to_tile(pc_to_gt(pc)), min, max));
919
919
}
920
920
921
921
static int pc_init_freqs(struct xe_guc_pc *pc)
+2
-2
drivers/gpu/drm/xe/xe_hwmon.c
+2
-2
drivers/gpu/drm/xe/xe_hwmon.c
···
441
441
if (gt_to_xe(gt)->info.platform == XE_DG2)
442
442
return -ENXIO;
443
443
444
-
return xe_pcode_read(gt, PCODE_MBOX(PCODE_POWER_SETUP,
444
+
return xe_pcode_read(gt_to_tile(gt), PCODE_MBOX(PCODE_POWER_SETUP,
445
445
POWER_SETUP_SUBCOMMAND_READ_I1, 0),
446
446
uval, NULL);
447
447
}
448
448
449
449
static int xe_hwmon_pcode_write_i1(struct xe_gt *gt, u32 uval)
450
450
{
451
-
return xe_pcode_write(gt, PCODE_MBOX(PCODE_POWER_SETUP,
451
+
return xe_pcode_write(gt_to_tile(gt), PCODE_MBOX(PCODE_POWER_SETUP,
452
452
POWER_SETUP_SUBCOMMAND_WRITE_I1, 0),
453
453
(uval & POWER_SETUP_I1_DATA_MASK));
454
454
}
+52
-52
drivers/gpu/drm/xe/xe_pcode.c
+52
-52
drivers/gpu/drm/xe/xe_pcode.c
···
12
12
13
13
#include "xe_assert.h"
14
14
#include "xe_device.h"
15
-
#include "xe_gt.h"
16
15
#include "xe_mmio.h"
17
16
#include "xe_pcode_api.h"
18
17
···
29
30
* - PCODE for display operations
30
31
*/
31
32
32
-
static int pcode_mailbox_status(struct xe_gt *gt)
33
+
static int pcode_mailbox_status(struct xe_tile *tile)
33
34
{
34
35
u32 err;
35
36
static const struct pcode_err_decode err_decode[] = {
···
44
45
[PCODE_ERROR_MASK] = {-EPROTO, "Unknown"},
45
46
};
46
47
47
-
err = xe_mmio_read32(gt, PCODE_MAILBOX) & PCODE_ERROR_MASK;
48
+
err = xe_mmio_read32(tile->primary_gt, PCODE_MAILBOX) & PCODE_ERROR_MASK;
48
49
if (err) {
49
-
drm_err(>_to_xe(gt)->drm, "PCODE Mailbox failed: %d %s", err,
50
+
drm_err(&tile_to_xe(tile)->drm, "PCODE Mailbox failed: %d %s", err,
50
51
err_decode[err].str ?: "Unknown");
51
52
return err_decode[err].errno ?: -EPROTO;
52
53
}
···
54
55
return 0;
55
56
}
56
57
57
-
static int __pcode_mailbox_rw(struct xe_gt *gt, u32 mbox, u32 *data0, u32 *data1,
58
+
static int __pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *data1,
58
59
unsigned int timeout_ms, bool return_data,
59
60
bool atomic)
60
61
{
62
+
struct xe_gt *mmio = tile->primary_gt;
61
63
int err;
62
64
63
-
if (gt_to_xe(gt)->info.skip_pcode)
65
+
if (tile_to_xe(tile)->info.skip_pcode)
64
66
return 0;
65
67
66
-
if ((xe_mmio_read32(gt, PCODE_MAILBOX) & PCODE_READY) != 0)
68
+
if ((xe_mmio_read32(mmio, PCODE_MAILBOX) & PCODE_READY) != 0)
67
69
return -EAGAIN;
68
70
69
-
xe_mmio_write32(gt, PCODE_DATA0, *data0);
70
-
xe_mmio_write32(gt, PCODE_DATA1, data1 ? *data1 : 0);
71
-
xe_mmio_write32(gt, PCODE_MAILBOX, PCODE_READY | mbox);
71
+
xe_mmio_write32(mmio, PCODE_DATA0, *data0);
72
+
xe_mmio_write32(mmio, PCODE_DATA1, data1 ? *data1 : 0);
73
+
xe_mmio_write32(mmio, PCODE_MAILBOX, PCODE_READY | mbox);
72
74
73
-
err = xe_mmio_wait32(gt, PCODE_MAILBOX, PCODE_READY, 0,
75
+
err = xe_mmio_wait32(mmio, PCODE_MAILBOX, PCODE_READY, 0,
74
76
timeout_ms * USEC_PER_MSEC, NULL, atomic);
75
77
if (err)
76
78
return err;
77
79
78
80
if (return_data) {
79
-
*data0 = xe_mmio_read32(gt, PCODE_DATA0);
81
+
*data0 = xe_mmio_read32(mmio, PCODE_DATA0);
80
82
if (data1)
81
-
*data1 = xe_mmio_read32(gt, PCODE_DATA1);
83
+
*data1 = xe_mmio_read32(mmio, PCODE_DATA1);
82
84
}
83
85
84
-
return pcode_mailbox_status(gt);
86
+
return pcode_mailbox_status(tile);
85
87
}
86
88
87
-
static int pcode_mailbox_rw(struct xe_gt *gt, u32 mbox, u32 *data0, u32 *data1,
89
+
static int pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *data1,
88
90
unsigned int timeout_ms, bool return_data,
89
91
bool atomic)
90
92
{
91
-
if (gt_to_xe(gt)->info.skip_pcode)
93
+
if (tile_to_xe(tile)->info.skip_pcode)
92
94
return 0;
93
95
94
-
lockdep_assert_held(>->pcode.lock);
96
+
lockdep_assert_held(&tile->pcode.lock);
95
97
96
-
return __pcode_mailbox_rw(gt, mbox, data0, data1, timeout_ms, return_data, atomic);
98
+
return __pcode_mailbox_rw(tile, mbox, data0, data1, timeout_ms, return_data, atomic);
97
99
}
98
100
99
-
int xe_pcode_write_timeout(struct xe_gt *gt, u32 mbox, u32 data, int timeout)
101
+
int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 data, int timeout)
100
102
{
101
103
int err;
102
104
103
-
mutex_lock(>->pcode.lock);
104
-
err = pcode_mailbox_rw(gt, mbox, &data, NULL, timeout, false, false);
105
-
mutex_unlock(>->pcode.lock);
105
+
mutex_lock(&tile->pcode.lock);
106
+
err = pcode_mailbox_rw(tile, mbox, &data, NULL, timeout, false, false);
107
+
mutex_unlock(&tile->pcode.lock);
106
108
107
109
return err;
108
110
}
109
111
110
-
int xe_pcode_read(struct xe_gt *gt, u32 mbox, u32 *val, u32 *val1)
112
+
int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1)
111
113
{
112
114
int err;
113
115
114
-
mutex_lock(>->pcode.lock);
115
-
err = pcode_mailbox_rw(gt, mbox, val, val1, 1, true, false);
116
-
mutex_unlock(>->pcode.lock);
116
+
mutex_lock(&tile->pcode.lock);
117
+
err = pcode_mailbox_rw(tile, mbox, val, val1, 1, true, false);
118
+
mutex_unlock(&tile->pcode.lock);
117
119
118
120
return err;
119
121
}
120
122
121
-
static int pcode_try_request(struct xe_gt *gt, u32 mbox,
123
+
static int pcode_try_request(struct xe_tile *tile, u32 mbox,
122
124
u32 request, u32 reply_mask, u32 reply,
123
125
u32 *status, bool atomic, int timeout_us, bool locked)
124
126
{
125
127
int slept, wait = 10;
126
128
127
-
xe_gt_assert(gt, timeout_us > 0);
129
+
xe_tile_assert(tile, timeout_us > 0);
128
130
129
131
for (slept = 0; slept < timeout_us; slept += wait) {
130
132
if (locked)
131
-
*status = pcode_mailbox_rw(gt, mbox, &request, NULL, 1, true,
133
+
*status = pcode_mailbox_rw(tile, mbox, &request, NULL, 1, true,
132
134
atomic);
133
135
else
134
-
*status = __pcode_mailbox_rw(gt, mbox, &request, NULL, 1, true,
136
+
*status = __pcode_mailbox_rw(tile, mbox, &request, NULL, 1, true,
135
137
atomic);
136
138
if ((*status == 0) && ((request & reply_mask) == reply))
137
139
return 0;
···
149
149
150
150
/**
151
151
* xe_pcode_request - send PCODE request until acknowledgment
152
-
* @gt: gt
152
+
* @tile: tile
153
153
* @mbox: PCODE mailbox ID the request is targeted for
154
154
* @request: request ID
155
155
* @reply_mask: mask used to check for request acknowledgment
···
166
166
* Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
167
167
* other error as reported by PCODE.
168
168
*/
169
-
int xe_pcode_request(struct xe_gt *gt, u32 mbox, u32 request,
170
-
u32 reply_mask, u32 reply, int timeout_base_ms)
169
+
int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,
170
+
u32 reply_mask, u32 reply, int timeout_base_ms)
171
171
{
172
172
u32 status;
173
173
int ret;
174
174
175
-
xe_gt_assert(gt, timeout_base_ms <= 3);
175
+
xe_tile_assert(tile, timeout_base_ms <= 3);
176
176
177
-
mutex_lock(>->pcode.lock);
177
+
mutex_lock(&tile->pcode.lock);
178
178
179
-
ret = pcode_try_request(gt, mbox, request, reply_mask, reply, &status,
179
+
ret = pcode_try_request(tile, mbox, request, reply_mask, reply, &status,
180
180
false, timeout_base_ms * 1000, true);
181
181
if (!ret)
182
182
goto out;
···
191
191
* requests, and for any quirks of the PCODE firmware that delays
192
192
* the request completion.
193
193
*/
194
-
drm_err(>_to_xe(gt)->drm,
194
+
drm_err(&tile_to_xe(tile)->drm,
195
195
"PCODE timeout, retrying with preemption disabled\n");
196
196
preempt_disable();
197
-
ret = pcode_try_request(gt, mbox, request, reply_mask, reply, &status,
197
+
ret = pcode_try_request(tile, mbox, request, reply_mask, reply, &status,
198
198
true, 50 * 1000, true);
199
199
preempt_enable();
200
200
201
201
out:
202
-
mutex_unlock(>->pcode.lock);
202
+
mutex_unlock(&tile->pcode.lock);
203
203
return status ? status : ret;
204
204
}
205
205
/**
206
206
* xe_pcode_init_min_freq_table - Initialize PCODE's QOS frequency table
207
-
* @gt: gt instance
207
+
* @tile: tile instance
208
208
* @min_gt_freq: Minimal (RPn) GT frequency in units of 50MHz.
209
209
* @max_gt_freq: Maximal (RP0) GT frequency in units of 50MHz.
210
210
*
···
227
227
* - -EACCES, "PCODE Rejected"
228
228
* - -EPROTO, "Unknown"
229
229
*/
230
-
int xe_pcode_init_min_freq_table(struct xe_gt *gt, u32 min_gt_freq,
230
+
int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq,
231
231
u32 max_gt_freq)
232
232
{
233
233
int ret;
234
234
u32 freq;
235
235
236
-
if (!gt_to_xe(gt)->info.has_llc)
236
+
if (!tile_to_xe(tile)->info.has_llc)
237
237
return 0;
238
238
239
239
if (max_gt_freq <= min_gt_freq)
240
240
return -EINVAL;
241
241
242
-
mutex_lock(>->pcode.lock);
242
+
mutex_lock(&tile->pcode.lock);
243
243
for (freq = min_gt_freq; freq <= max_gt_freq; freq++) {
244
244
u32 data = freq << PCODE_FREQ_RING_RATIO_SHIFT | freq;
245
245
246
-
ret = pcode_mailbox_rw(gt, PCODE_WRITE_MIN_FREQ_TABLE,
246
+
ret = pcode_mailbox_rw(tile, PCODE_WRITE_MIN_FREQ_TABLE,
247
247
&data, NULL, 1, false, false);
248
248
if (ret)
249
249
goto unlock;
250
250
}
251
251
252
252
unlock:
253
-
mutex_unlock(>->pcode.lock);
253
+
mutex_unlock(&tile->pcode.lock);
254
254
return ret;
255
255
}
256
256
···
270
270
int xe_pcode_ready(struct xe_device *xe, bool locked)
271
271
{
272
272
u32 status, request = DGFX_GET_INIT_STATUS;
273
-
struct xe_gt *gt = xe_root_mmio_gt(xe);
273
+
struct xe_tile *tile = xe_device_get_root_tile(xe);
274
274
int timeout_us = 180000000; /* 3 min */
275
275
int ret;
276
276
···
281
281
return 0;
282
282
283
283
if (locked)
284
-
mutex_lock(>->pcode.lock);
284
+
mutex_lock(&tile->pcode.lock);
285
285
286
-
ret = pcode_try_request(gt, DGFX_PCODE_STATUS, request,
286
+
ret = pcode_try_request(tile, DGFX_PCODE_STATUS, request,
287
287
DGFX_INIT_STATUS_COMPLETE,
288
288
DGFX_INIT_STATUS_COMPLETE,
289
289
&status, false, timeout_us, locked);
290
290
291
291
if (locked)
292
-
mutex_unlock(>->pcode.lock);
292
+
mutex_unlock(&tile->pcode.lock);
293
293
294
294
if (ret)
295
295
drm_err(&xe->drm,
···
300
300
301
301
/**
302
302
* xe_pcode_init: initialize components of PCODE
303
-
* @gt: gt instance
303
+
* @tile: tile instance
304
304
*
305
305
* This function initializes the xe_pcode component.
306
306
* To be called once only during probe.
307
307
*/
308
-
void xe_pcode_init(struct xe_gt *gt)
308
+
void xe_pcode_init(struct xe_tile *tile)
309
309
{
310
-
drmm_mutex_init(>_to_xe(gt)->drm, >->pcode.lock);
310
+
drmm_mutex_init(&tile_to_xe(tile)->drm, &tile->pcode.lock);
311
311
}
312
312
313
313
/**
+8
-8
drivers/gpu/drm/xe/xe_pcode.h
+8
-8
drivers/gpu/drm/xe/xe_pcode.h
···
7
7
#define _XE_PCODE_H_
8
8
9
9
#include <linux/types.h>
10
-
struct xe_gt;
10
+
struct xe_tile;
11
11
struct xe_device;
12
12
13
-
void xe_pcode_init(struct xe_gt *gt);
13
+
void xe_pcode_init(struct xe_tile *tile);
14
14
int xe_pcode_probe_early(struct xe_device *xe);
15
15
int xe_pcode_ready(struct xe_device *xe, bool locked);
16
-
int xe_pcode_init_min_freq_table(struct xe_gt *gt, u32 min_gt_freq,
16
+
int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq,
17
17
u32 max_gt_freq);
18
-
int xe_pcode_read(struct xe_gt *gt, u32 mbox, u32 *val, u32 *val1);
19
-
int xe_pcode_write_timeout(struct xe_gt *gt, u32 mbox, u32 val,
18
+
int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1);
19
+
int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val,
20
20
int timeout_ms);
21
-
#define xe_pcode_write(gt, mbox, val) \
22
-
xe_pcode_write_timeout(gt, mbox, val, 1)
21
+
#define xe_pcode_write(tile, mbox, val) \
22
+
xe_pcode_write_timeout(tile, mbox, val, 1)
23
23
24
-
int xe_pcode_request(struct xe_gt *gt, u32 mbox, u32 request,
24
+
int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,
25
25
u32 reply_mask, u32 reply, int timeout_ms);
26
26
27
27
#define PCODE_MBOX(mbcmd, param1, param2)\
+3
drivers/gpu/drm/xe/xe_tile.c
+3
drivers/gpu/drm/xe/xe_tile.c
···
9
9
#include "xe_ggtt.h"
10
10
#include "xe_gt.h"
11
11
#include "xe_migrate.h"
12
+
#include "xe_pcode.h"
12
13
#include "xe_sa.h"
13
14
#include "xe_tile.h"
14
15
#include "xe_tile_sysfs.h"
···
124
123
tile->primary_gt = xe_gt_alloc(tile);
125
124
if (IS_ERR(tile->primary_gt))
126
125
return PTR_ERR(tile->primary_gt);
126
+
127
+
xe_pcode_init(tile);
127
128
128
129
return 0;
129
130
}
+7
-2
drivers/gpu/drm/xe/xe_uc_fw.h
+7
-2
drivers/gpu/drm/xe/xe_uc_fw.h
···
65
65
return "<invalid>";
66
66
}
67
67
68
-
static inline int xe_uc_fw_status_to_error(enum xe_uc_fw_status status)
68
+
static inline int xe_uc_fw_status_to_error(const enum xe_uc_fw_status status)
69
69
{
70
70
switch (status) {
71
71
case XE_UC_FIRMWARE_NOT_SUPPORTED:
···
108
108
}
109
109
110
110
static inline enum xe_uc_fw_status
111
-
__xe_uc_fw_status(struct xe_uc_fw *uc_fw)
111
+
__xe_uc_fw_status(const struct xe_uc_fw *uc_fw)
112
112
{
113
113
/* shouldn't call this before checking hw/blob availability */
114
114
XE_WARN_ON(uc_fw->status == XE_UC_FIRMWARE_UNINITIALIZED);
···
154
154
static inline bool xe_uc_fw_is_overridden(const struct xe_uc_fw *uc_fw)
155
155
{
156
156
return uc_fw->user_overridden;
157
+
}
158
+
159
+
static inline bool xe_uc_fw_is_in_error_state(const struct xe_uc_fw *uc_fw)
160
+
{
161
+
return xe_uc_fw_status_to_error(__xe_uc_fw_status(uc_fw)) < 0;
157
162
}
158
163
159
164
static inline void xe_uc_fw_sanitize(struct xe_uc_fw *uc_fw)
+2
-4
drivers/gpu/drm/xe/xe_vram_freq.c
+2
-4
drivers/gpu/drm/xe/xe_vram_freq.c
···
34
34
char *buf)
35
35
{
36
36
struct xe_tile *tile = dev_to_tile(dev);
37
-
struct xe_gt *gt = tile->primary_gt;
38
37
u32 val, mbox;
39
38
int err;
40
39
···
41
42
| REG_FIELD_PREP(PCODE_MB_PARAM1, PCODE_MBOX_FC_SC_READ_FUSED_P0)
42
43
| REG_FIELD_PREP(PCODE_MB_PARAM2, PCODE_MBOX_DOMAIN_HBM);
43
44
44
-
err = xe_pcode_read(gt, mbox, &val, NULL);
45
+
err = xe_pcode_read(tile, mbox, &val, NULL);
45
46
if (err)
46
47
return err;
47
48
···
56
57
char *buf)
57
58
{
58
59
struct xe_tile *tile = dev_to_tile(dev);
59
-
struct xe_gt *gt = tile->primary_gt;
60
60
u32 val, mbox;
61
61
int err;
62
62
···
63
65
| REG_FIELD_PREP(PCODE_MB_PARAM1, PCODE_MBOX_FC_SC_READ_FUSED_PN)
64
66
| REG_FIELD_PREP(PCODE_MB_PARAM2, PCODE_MBOX_DOMAIN_HBM);
65
67
66
-
err = xe_pcode_read(gt, mbox, &val, NULL);
68
+
err = xe_pcode_read(tile, mbox, &val, NULL);
67
69
if (err)
68
70
return err;
69
71
+1
drivers/gpu/drm/xlnx/Kconfig
+1
drivers/gpu/drm/xlnx/Kconfig
+3
-3
drivers/hv/hv.c
+3
-3
drivers/hv/hv.c
···
342
342
return 0;
343
343
}
344
344
345
-
/*
346
-
* hv_synic_cleanup - Cleanup routine for hv_synic_init().
347
-
*/
348
345
void hv_synic_disable_regs(unsigned int cpu)
349
346
{
350
347
struct hv_per_cpu_context *hv_cpu =
···
433
436
return pending;
434
437
}
435
438
439
+
/*
440
+
* hv_synic_cleanup - Cleanup routine for hv_synic_init().
441
+
*/
436
442
int hv_synic_cleanup(unsigned int cpu)
437
443
{
438
444
struct vmbus_channel *channel, *sc;
-6
drivers/hv/hyperv_vmbus.h
-6
drivers/hv/hyperv_vmbus.h
···
380
380
int hv_vss_pre_suspend(void);
381
381
int hv_vss_pre_resume(void);
382
382
void hv_vss_onchannelcallback(void *context);
383
-
384
-
int hv_fcopy_init(struct hv_util_service *srv);
385
-
void hv_fcopy_deinit(void);
386
-
int hv_fcopy_pre_suspend(void);
387
-
int hv_fcopy_pre_resume(void);
388
-
void hv_fcopy_onchannelcallback(void *context);
389
383
void vmbus_initiate_unload(bool crash);
390
384
391
385
static inline void hv_poll_channel(struct vmbus_channel *channel,
+3
-2
drivers/hv/vmbus_drv.c
+3
-2
drivers/hv/vmbus_drv.c
···
1803
1803
return attr->mode;
1804
1804
}
1805
1805
1806
-
static struct attribute_group vmbus_chan_group = {
1806
+
static const struct attribute_group vmbus_chan_group = {
1807
1807
.attrs = vmbus_chan_attrs,
1808
1808
.is_visible = vmbus_chan_attr_is_visible
1809
1809
};
1810
1810
1811
-
static struct kobj_type vmbus_chan_ktype = {
1811
+
static const struct kobj_type vmbus_chan_ktype = {
1812
1812
.sysfs_ops = &vmbus_chan_sysfs_ops,
1813
1813
.release = vmbus_chan_release,
1814
1814
};
···
1952
1952
*/
1953
1953
device_unregister(&device_obj->device);
1954
1954
}
1955
+
EXPORT_SYMBOL_GPL(vmbus_device_unregister);
1955
1956
1956
1957
#ifdef CONFIG_ACPI
1957
1958
/*
+17
-13
drivers/iio/adc/ad7124.c
+17
-13
drivers/iio/adc/ad7124.c
···
147
147
struct ad7124_channel_config {
148
148
bool live;
149
149
unsigned int cfg_slot;
150
-
enum ad7124_ref_sel refsel;
151
-
bool bipolar;
152
-
bool buf_positive;
153
-
bool buf_negative;
154
-
unsigned int vref_mv;
155
-
unsigned int pga_bits;
156
-
unsigned int odr;
157
-
unsigned int odr_sel_bits;
158
-
unsigned int filter_type;
150
+
/* Following fields are used to compare equality. */
151
+
struct_group(config_props,
152
+
enum ad7124_ref_sel refsel;
153
+
bool bipolar;
154
+
bool buf_positive;
155
+
bool buf_negative;
156
+
unsigned int vref_mv;
157
+
unsigned int pga_bits;
158
+
unsigned int odr;
159
+
unsigned int odr_sel_bits;
160
+
unsigned int filter_type;
161
+
);
159
162
};
160
163
161
164
struct ad7124_channel {
···
337
334
ptrdiff_t cmp_size;
338
335
int i;
339
336
340
-
cmp_size = (u8 *)&cfg->live - (u8 *)cfg;
337
+
cmp_size = sizeof_field(struct ad7124_channel_config, config_props);
341
338
for (i = 0; i < st->num_channels; i++) {
342
339
cfg_aux = &st->channels[i].cfg;
343
340
344
-
if (cfg_aux->live && !memcmp(cfg, cfg_aux, cmp_size))
341
+
if (cfg_aux->live &&
342
+
!memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size))
345
343
return cfg_aux;
346
344
}
347
345
···
768
764
if (ret < 0)
769
765
return ret;
770
766
767
+
fsleep(200);
771
768
timeout = 100;
772
769
do {
773
770
ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
···
844
839
st->channels = channels;
845
840
846
841
device_for_each_child_node_scoped(dev, child) {
847
-
cfg = &st->channels[channel].cfg;
848
-
849
842
ret = fwnode_property_read_u32(child, "reg", &channel);
850
843
if (ret)
851
844
return ret;
···
861
858
st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
862
859
AD7124_CHANNEL_AINM(ain[1]);
863
860
861
+
cfg = &st->channels[channel].cfg;
864
862
cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
865
863
866
864
ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp);
+5
-8
drivers/iio/adc/ad7173.c
+5
-8
drivers/iio/adc/ad7173.c
···
302
302
.num_configs = 8,
303
303
.num_voltage_in = 16,
304
304
.num_gpios = 4,
305
-
.higher_gpio_bits = true,
306
305
.has_vincom_input = true,
307
306
.has_temp = true,
308
307
.has_input_buf = true,
···
319
320
.num_configs = 8,
320
321
.num_voltage_in = 16,
321
322
.num_gpios = 4,
322
-
.higher_gpio_bits = true,
323
323
.has_vincom_input = true,
324
324
.has_temp = true,
325
325
.has_input_buf = true,
···
336
338
.num_configs = 8,
337
339
.num_voltage_in = 16,
338
340
.num_gpios = 4,
339
-
.higher_gpio_bits = true,
340
341
.has_vincom_input = true,
341
342
.has_temp = true,
342
343
.has_input_buf = true,
···
1432
1435
}
1433
1436
1434
1437
static const struct of_device_id ad7173_of_match[] = {
1435
-
{ .compatible = "ad4111", .data = &ad4111_device_info },
1436
-
{ .compatible = "ad4112", .data = &ad4112_device_info },
1437
-
{ .compatible = "ad4114", .data = &ad4114_device_info },
1438
-
{ .compatible = "ad4115", .data = &ad4115_device_info },
1439
-
{ .compatible = "ad4116", .data = &ad4116_device_info },
1438
+
{ .compatible = "adi,ad4111", .data = &ad4111_device_info },
1439
+
{ .compatible = "adi,ad4112", .data = &ad4112_device_info },
1440
+
{ .compatible = "adi,ad4114", .data = &ad4114_device_info },
1441
+
{ .compatible = "adi,ad4115", .data = &ad4115_device_info },
1442
+
{ .compatible = "adi,ad4116", .data = &ad4116_device_info },
1440
1443
{ .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info },
1441
1444
{ .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info },
1442
1445
{ .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info },
+2
-26
drivers/iio/adc/ad7606.c
+2
-26
drivers/iio/adc/ad7606.c
···
49
49
1, 2, 4, 8, 16, 32, 64, 128,
50
50
};
51
51
52
-
static int ad7606_reset(struct ad7606_state *st)
52
+
int ad7606_reset(struct ad7606_state *st)
53
53
{
54
54
if (st->gpio_reset) {
55
55
gpiod_set_value(st->gpio_reset, 1);
···
60
60
61
61
return -ENODEV;
62
62
}
63
+
EXPORT_SYMBOL_NS_GPL(ad7606_reset, IIO_AD7606);
63
64
64
65
static int ad7606_reg_access(struct iio_dev *indio_dev,
65
66
unsigned int reg,
···
89
88
{
90
89
unsigned int num = st->chip_info->num_channels - 1;
91
90
u16 *data = st->data;
92
-
int ret;
93
-
94
-
/*
95
-
* The frstdata signal is set to high while and after reading the sample
96
-
* of the first channel and low for all other channels. This can be used
97
-
* to check that the incoming data is correctly aligned. During normal
98
-
* operation the data should never become unaligned, but some glitch or
99
-
* electrostatic discharge might cause an extra read or clock cycle.
100
-
* Monitoring the frstdata signal allows to recover from such failure
101
-
* situations.
102
-
*/
103
-
104
-
if (st->gpio_frstdata) {
105
-
ret = st->bops->read_block(st->dev, 1, data);
106
-
if (ret)
107
-
return ret;
108
-
109
-
if (!gpiod_get_value(st->gpio_frstdata)) {
110
-
ad7606_reset(st);
111
-
return -EIO;
112
-
}
113
-
114
-
data++;
115
-
num--;
116
-
}
117
91
118
92
return st->bops->read_block(st->dev, num, data);
119
93
}
+2
drivers/iio/adc/ad7606.h
+2
drivers/iio/adc/ad7606.h
+44
-2
drivers/iio/adc/ad7606_par.c
+44
-2
drivers/iio/adc/ad7606_par.c
···
7
7
8
8
#include <linux/mod_devicetable.h>
9
9
#include <linux/module.h>
10
+
#include <linux/gpio/consumer.h>
10
11
#include <linux/platform_device.h>
11
12
#include <linux/types.h>
12
13
#include <linux/err.h>
···
22
21
struct iio_dev *indio_dev = dev_get_drvdata(dev);
23
22
struct ad7606_state *st = iio_priv(indio_dev);
24
23
25
-
insw((unsigned long)st->base_address, buf, count);
26
24
25
+
/*
26
+
* On the parallel interface, the frstdata signal is set to high while
27
+
* and after reading the sample of the first channel and low for all
28
+
* other channels. This can be used to check that the incoming data is
29
+
* correctly aligned. During normal operation the data should never
30
+
* become unaligned, but some glitch or electrostatic discharge might
31
+
* cause an extra read or clock cycle. Monitoring the frstdata signal
32
+
* allows to recover from such failure situations.
33
+
*/
34
+
int num = count;
35
+
u16 *_buf = buf;
36
+
37
+
if (st->gpio_frstdata) {
38
+
insw((unsigned long)st->base_address, _buf, 1);
39
+
if (!gpiod_get_value(st->gpio_frstdata)) {
40
+
ad7606_reset(st);
41
+
return -EIO;
42
+
}
43
+
_buf++;
44
+
num--;
45
+
}
46
+
insw((unsigned long)st->base_address, _buf, num);
27
47
return 0;
28
48
}
29
49
···
57
35
{
58
36
struct iio_dev *indio_dev = dev_get_drvdata(dev);
59
37
struct ad7606_state *st = iio_priv(indio_dev);
38
+
/*
39
+
* On the parallel interface, the frstdata signal is set to high while
40
+
* and after reading the sample of the first channel and low for all
41
+
* other channels. This can be used to check that the incoming data is
42
+
* correctly aligned. During normal operation the data should never
43
+
* become unaligned, but some glitch or electrostatic discharge might
44
+
* cause an extra read or clock cycle. Monitoring the frstdata signal
45
+
* allows to recover from such failure situations.
46
+
*/
47
+
int num = count;
48
+
u16 *_buf = buf;
60
49
61
-
insb((unsigned long)st->base_address, buf, count * 2);
50
+
if (st->gpio_frstdata) {
51
+
insb((unsigned long)st->base_address, _buf, 2);
52
+
if (!gpiod_get_value(st->gpio_frstdata)) {
53
+
ad7606_reset(st);
54
+
return -EIO;
55
+
}
56
+
_buf++;
57
+
num--;
58
+
}
59
+
insb((unsigned long)st->base_address, _buf, num * 2);
62
60
63
61
return 0;
64
62
}
+1
-1
drivers/iio/adc/ad_sigma_delta.c
+1
-1
drivers/iio/adc/ad_sigma_delta.c
···
569
569
static int devm_ad_sd_probe_trigger(struct device *dev, struct iio_dev *indio_dev)
570
570
{
571
571
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
572
-
unsigned long irq_flags = irq_get_trigger_type(sigma_delta->spi->irq);
572
+
unsigned long irq_flags = irq_get_trigger_type(sigma_delta->irq_line);
573
573
int ret;
574
574
575
575
if (dev != &sigma_delta->spi->dev) {
+1
-1
drivers/iio/adc/ti-ads1119.c
+1
-1
drivers/iio/adc/ti-ads1119.c
+3
-1
drivers/iio/buffer/industrialio-buffer-dmaengine.c
+3
-1
drivers/iio/buffer/industrialio-buffer-dmaengine.c
···
237
237
238
238
ret = dma_get_slave_caps(chan, &caps);
239
239
if (ret < 0)
240
-
goto err_free;
240
+
goto err_release;
241
241
242
242
/* Needs to be aligned to the maximum of the minimums */
243
243
if (caps.src_addr_widths)
···
263
263
264
264
return &dmaengine_buffer->queue.buffer;
265
265
266
+
err_release:
267
+
dma_release_channel(chan);
266
268
err_free:
267
269
kfree(dmaengine_buffer);
268
270
return ERR_PTR(ret);
+11
-2
drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c
+11
-2
drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c
···
248
248
int result;
249
249
250
250
switch (st->chip_type) {
251
+
case INV_MPU6000:
251
252
case INV_MPU6050:
253
+
case INV_MPU9150:
254
+
/*
255
+
* WoM is not supported and interrupt status read seems to be broken for
256
+
* some chips. Since data ready is the only interrupt, bypass interrupt
257
+
* status read and always assert data ready bit.
258
+
*/
259
+
wom_bits = 0;
260
+
int_status = INV_MPU6050_BIT_RAW_DATA_RDY_INT;
261
+
goto data_ready_interrupt;
252
262
case INV_MPU6500:
253
263
case INV_MPU6515:
254
264
case INV_MPU6880:
255
-
case INV_MPU6000:
256
-
case INV_MPU9150:
257
265
case INV_MPU9250:
258
266
case INV_MPU9255:
259
267
wom_bits = INV_MPU6500_BIT_WOM_INT;
···
287
279
}
288
280
}
289
281
282
+
data_ready_interrupt:
290
283
/* handle raw data interrupt */
291
284
if (int_status & INV_MPU6050_BIT_RAW_DATA_RDY_INT) {
292
285
indio_dev->pollfunc->timestamp = st->it_timestamp;
+4
-4
drivers/iio/inkern.c
+4
-4
drivers/iio/inkern.c
···
647
647
break;
648
648
case IIO_VAL_INT_PLUS_MICRO:
649
649
if (scale_val2 < 0)
650
-
*processed = -raw64 * scale_val;
650
+
*processed = -raw64 * scale_val * scale;
651
651
else
652
-
*processed = raw64 * scale_val;
652
+
*processed = raw64 * scale_val * scale;
653
653
*processed += div_s64(raw64 * (s64)scale_val2 * scale,
654
654
1000000LL);
655
655
break;
656
656
case IIO_VAL_INT_PLUS_NANO:
657
657
if (scale_val2 < 0)
658
-
*processed = -raw64 * scale_val;
658
+
*processed = -raw64 * scale_val * scale;
659
659
else
660
-
*processed = raw64 * scale_val;
660
+
*processed = raw64 * scale_val * scale;
661
661
*processed += div_s64(raw64 * (s64)scale_val2 * scale,
662
662
1000000000LL);
663
663
break;
+3
-1
drivers/md/dm-integrity.c
+3
-1
drivers/md/dm-integrity.c
···
2174
2174
struct bio *bio = dm_bio_from_per_bio_data(dio, sizeof(struct dm_integrity_io));
2175
2175
unsigned int journal_section, journal_entry;
2176
2176
unsigned int journal_read_pos;
2177
+
sector_t recalc_sector;
2177
2178
struct completion read_comp;
2178
2179
bool discard_retried = false;
2179
2180
bool need_sync_io = ic->internal_hash && dio->op == REQ_OP_READ;
···
2315
2314
goto lock_retry;
2316
2315
}
2317
2316
}
2317
+
recalc_sector = le64_to_cpu(ic->sb->recalc_sector);
2318
2318
spin_unlock_irq(&ic->endio_wait.lock);
2319
2319
2320
2320
if (unlikely(journal_read_pos != NOT_FOUND)) {
···
2370
2368
if (need_sync_io) {
2371
2369
wait_for_completion_io(&read_comp);
2372
2370
if (ic->sb->flags & cpu_to_le32(SB_FLAG_RECALCULATING) &&
2373
-
dio->range.logical_sector + dio->range.n_sectors > le64_to_cpu(ic->sb->recalc_sector))
2371
+
dio->range.logical_sector + dio->range.n_sectors > recalc_sector)
2374
2372
goto skip_check;
2375
2373
if (ic->mode == 'B') {
2376
2374
if (!block_bitmap_op(ic, ic->recalc_bitmap, dio->range.logical_sector,
+2
-3
drivers/misc/fastrpc.c
+2
-3
drivers/misc/fastrpc.c
···
1910
1910
&args[0]);
1911
1911
if (err) {
1912
1912
dev_err(dev, "mmap error (len 0x%08llx)\n", buf->size);
1913
-
goto err_invoke;
1913
+
fastrpc_buf_free(buf);
1914
+
return err;
1914
1915
}
1915
1916
1916
1917
/* update the buffer to be able to deallocate the memory on the DSP */
···
1949
1948
1950
1949
err_assign:
1951
1950
fastrpc_req_munmap_impl(fl, buf);
1952
-
err_invoke:
1953
-
fastrpc_buf_free(buf);
1954
1951
1955
1952
return err;
1956
1953
}
+4
-10
drivers/misc/keba/cp500.c
+4
-10
drivers/misc/keba/cp500.c
···
212
212
}
213
213
static DEVICE_ATTR_RW(keep_cfg);
214
214
215
-
static struct attribute *attrs[] = {
215
+
static struct attribute *cp500_attrs[] = {
216
216
&dev_attr_version.attr,
217
217
&dev_attr_keep_cfg.attr,
218
218
NULL
219
219
};
220
-
static const struct attribute_group attrs_group = { .attrs = attrs };
220
+
ATTRIBUTE_GROUPS(cp500);
221
221
222
222
static void cp500_i2c_release(struct device *dev)
223
223
{
···
396
396
397
397
pci_set_drvdata(pci_dev, cp500);
398
398
399
-
ret = sysfs_create_group(&pci_dev->dev.kobj, &attrs_group);
400
-
if (ret != 0)
401
-
goto out_free_irq;
402
399
403
400
ret = cp500_enable(cp500);
404
401
if (ret != 0)
405
-
goto out_remove_group;
402
+
goto out_free_irq;
406
403
407
404
cp500_register_auxiliary_devs(cp500);
408
405
409
406
return 0;
410
407
411
-
out_remove_group:
412
-
sysfs_remove_group(&pci_dev->dev.kobj, &attrs_group);
413
408
out_free_irq:
414
409
pci_free_irq_vectors(pci_dev);
415
410
out_disable:
···
421
426
cp500_unregister_auxiliary_devs(cp500);
422
427
423
428
cp500_disable(cp500);
424
-
425
-
sysfs_remove_group(&pci_dev->dev.kobj, &attrs_group);
426
429
427
430
pci_set_drvdata(pci_dev, 0);
428
431
···
443
450
.id_table = cp500_ids,
444
451
.probe = cp500_probe,
445
452
.remove = cp500_remove,
453
+
.dev_groups = cp500_groups,
446
454
};
447
455
module_pci_driver(cp500_driver);
448
456
+2
-1
drivers/misc/vmw_vmci/vmci_resource.c
+2
-1
drivers/misc/vmw_vmci/vmci_resource.c
···
144
144
spin_lock(&vmci_resource_table.lock);
145
145
146
146
hlist_for_each_entry(r, &vmci_resource_table.entries[idx], node) {
147
-
if (vmci_handle_is_equal(r->handle, resource->handle)) {
147
+
if (vmci_handle_is_equal(r->handle, resource->handle) &&
148
+
resource->type == r->type) {
148
149
hlist_del_init_rcu(&r->node);
149
150
break;
150
151
}
+13
-9
drivers/mmc/core/quirks.h
+13
-9
drivers/mmc/core/quirks.h
···
15
15
16
16
#include "card.h"
17
17
18
+
static const struct mmc_fixup __maybe_unused mmc_sd_fixups[] = {
19
+
/*
20
+
* Kingston Canvas Go! Plus microSD cards never finish SD cache flush.
21
+
* This has so far only been observed on cards from 11/2019, while new
22
+
* cards from 2023/05 do not exhibit this behavior.
23
+
*/
24
+
_FIXUP_EXT("SD64G", CID_MANFID_KINGSTON_SD, 0x5449, 2019, 11,
25
+
0, -1ull, SDIO_ANY_ID, SDIO_ANY_ID, add_quirk_sd,
26
+
MMC_QUIRK_BROKEN_SD_CACHE, EXT_CSD_REV_ANY),
27
+
28
+
END_FIXUP
29
+
};
30
+
18
31
static const struct mmc_fixup __maybe_unused mmc_blk_fixups[] = {
19
32
#define INAND_CMD38_ARG_EXT_CSD 113
20
33
#define INAND_CMD38_ARG_ERASE 0x00
···
65
52
MMC_QUIRK_BLK_NO_CMD23),
66
53
MMC_FIXUP("MMC32G", CID_MANFID_TOSHIBA, CID_OEMID_ANY, add_quirk_mmc,
67
54
MMC_QUIRK_BLK_NO_CMD23),
68
-
69
-
/*
70
-
* Kingston Canvas Go! Plus microSD cards never finish SD cache flush.
71
-
* This has so far only been observed on cards from 11/2019, while new
72
-
* cards from 2023/05 do not exhibit this behavior.
73
-
*/
74
-
_FIXUP_EXT("SD64G", CID_MANFID_KINGSTON_SD, 0x5449, 2019, 11,
75
-
0, -1ull, SDIO_ANY_ID, SDIO_ANY_ID, add_quirk_sd,
76
-
MMC_QUIRK_BROKEN_SD_CACHE, EXT_CSD_REV_ANY),
77
55
78
56
/*
79
57
* Some SD cards lockup while using CMD23 multiblock transfers.
+4
drivers/mmc/core/sd.c
+4
drivers/mmc/core/sd.c
···
26
26
#include "host.h"
27
27
#include "bus.h"
28
28
#include "mmc_ops.h"
29
+
#include "quirks.h"
29
30
#include "sd.h"
30
31
#include "sd_ops.h"
31
32
···
1475
1474
if (err)
1476
1475
goto free_card;
1477
1476
}
1477
+
1478
+
/* Apply quirks prior to card setup */
1479
+
mmc_fixup_device(card, mmc_sd_fixups);
1478
1480
1479
1481
err = mmc_sd_setup_card(host, card, oldcard != NULL);
1480
1482
if (err)
+1
-1
drivers/mmc/host/cqhci-core.c
+1
-1
drivers/mmc/host/cqhci-core.c
···
617
617
cqhci_writel(cq_host, 0, CQHCI_CTL);
618
618
mmc->cqe_on = true;
619
619
pr_debug("%s: cqhci: CQE on\n", mmc_hostname(mmc));
620
-
if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT) {
620
+
if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) {
621
621
pr_err("%s: cqhci: CQE failed to exit halt state\n",
622
622
mmc_hostname(mmc));
623
623
}
+2
-2
drivers/mmc/host/dw_mmc.c
+2
-2
drivers/mmc/host/dw_mmc.c
···
2957
2957
if (host->use_dma == TRANS_MODE_IDMAC) {
2958
2958
mmc->max_segs = host->ring_size;
2959
2959
mmc->max_blk_size = 65535;
2960
-
mmc->max_seg_size = 0x1000;
2961
-
mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2960
+
mmc->max_req_size = DW_MCI_DESC_DATA_LENGTH * host->ring_size;
2961
+
mmc->max_seg_size = mmc->max_req_size;
2962
2962
mmc->max_blk_count = mmc->max_req_size / 512;
2963
2963
} else if (host->use_dma == TRANS_MODE_EDMAC) {
2964
2964
mmc->max_segs = 64;
+1
drivers/mmc/host/sdhci-of-aspeed.c
+1
drivers/mmc/host/sdhci-of-aspeed.c
+7
-4
drivers/net/dsa/ocelot/felix_vsc9959.c
+7
-4
drivers/net/dsa/ocelot/felix_vsc9959.c
···
1474
1474
/* Hardware errata - Admin config could not be overwritten if
1475
1475
* config is pending, need reset the TAS module
1476
1476
*/
1477
-
val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1478
-
if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) {
1479
-
ret = -EBUSY;
1480
-
goto err_reset_tc;
1477
+
val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port);
1478
+
if (val & QSYS_TAG_CONFIG_ENABLE) {
1479
+
val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1480
+
if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) {
1481
+
ret = -EBUSY;
1482
+
goto err_reset_tc;
1483
+
}
1481
1484
}
1482
1485
1483
1486
ocelot_rmw_rix(ocelot,
+1
-1
drivers/net/ethernet/faraday/ftgmac100.h
+1
-1
drivers/net/ethernet/faraday/ftgmac100.h
+8
-1
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
+8
-1
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
···
2273
2273
dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
2274
2274
{
2275
2275
const int queue_mapping = skb_get_queue_mapping(skb);
2276
-
bool nonlinear = skb_is_nonlinear(skb);
2277
2276
struct rtnl_link_stats64 *percpu_stats;
2278
2277
struct dpaa_percpu_priv *percpu_priv;
2279
2278
struct netdev_queue *txq;
2280
2279
struct dpaa_priv *priv;
2281
2280
struct qm_fd fd;
2281
+
bool nonlinear;
2282
2282
int offset = 0;
2283
2283
int err = 0;
2284
2284
···
2288
2288
2289
2289
qm_fd_clear_fd(&fd);
2290
2290
2291
+
/* Packet data is always read as 32-bit words, so zero out any part of
2292
+
* the skb which might be sent if we have to pad the packet
2293
+
*/
2294
+
if (__skb_put_padto(skb, ETH_ZLEN, false))
2295
+
goto enomem;
2296
+
2297
+
nonlinear = skb_is_nonlinear(skb);
2291
2298
if (!nonlinear) {
2292
2299
/* We're going to store the skb backpointer at the beginning
2293
2300
* of the data buffer, so we need a privately owned skb
+8
-7
drivers/net/ethernet/intel/ice/ice_lib.c
+8
-7
drivers/net/ethernet/intel/ice/ice_lib.c
···
2433
2433
struct ice_pf *pf = vsi->back;
2434
2434
int err;
2435
2435
2436
-
/* The Rx rule will only exist to remove if the LLDP FW
2437
-
* engine is currently stopped
2438
-
*/
2439
-
if (!ice_is_safe_mode(pf) && vsi->type == ICE_VSI_PF &&
2440
-
!test_bit(ICE_FLAG_FW_LLDP_AGENT, pf->flags))
2441
-
ice_cfg_sw_lldp(vsi, false, false);
2442
-
2443
2436
ice_rm_vsi_lan_cfg(vsi->port_info, vsi->idx);
2444
2437
err = ice_rm_vsi_rdma_cfg(vsi->port_info, vsi->idx);
2445
2438
if (err)
···
2799
2806
ice_rss_clean(vsi);
2800
2807
2801
2808
ice_vsi_close(vsi);
2809
+
2810
+
/* The Rx rule will only exist to remove if the LLDP FW
2811
+
* engine is currently stopped
2812
+
*/
2813
+
if (!ice_is_safe_mode(pf) && vsi->type == ICE_VSI_PF &&
2814
+
!test_bit(ICE_FLAG_FW_LLDP_AGENT, pf->flags))
2815
+
ice_cfg_sw_lldp(vsi, false, false);
2816
+
2802
2817
ice_vsi_decfg(vsi);
2803
2818
2804
2819
/* retain SW VSI data structure since it is needed to unregister and
-2
drivers/net/ethernet/intel/ice/ice_main.c
-2
drivers/net/ethernet/intel/ice/ice_main.c
···
5351
5351
ice_deinit(pf);
5352
5352
err_init:
5353
5353
ice_adapter_put(pdev);
5354
-
pci_disable_device(pdev);
5355
5354
return err;
5356
5355
}
5357
5356
···
5458
5459
ice_set_wake(pf);
5459
5460
5460
5461
ice_adapter_put(pdev);
5461
-
pci_disable_device(pdev);
5462
5462
}
5463
5463
5464
5464
/**
+2
-2
drivers/net/ethernet/intel/ice/ice_switch.c
+2
-2
drivers/net/ethernet/intel/ice/ice_switch.c
···
3194
3194
3195
3195
/* A rule already exists with the new VSI being added */
3196
3196
if (test_bit(vsi_handle, m_entry->vsi_list_info->vsi_map))
3197
-
return 0;
3197
+
return -EEXIST;
3198
3198
3199
3199
/* Update the previously created VSI list set with
3200
3200
* the new VSI ID passed in
···
3264
3264
3265
3265
list_head = &sw->recp_list[recp_id].filt_rules;
3266
3266
list_for_each_entry(list_itr, list_head, list_entry) {
3267
-
if (list_itr->vsi_list_info) {
3267
+
if (list_itr->vsi_count == 1 && list_itr->vsi_list_info) {
3268
3268
map_info = list_itr->vsi_list_info;
3269
3269
if (test_bit(vsi_handle, map_info->vsi_map)) {
3270
3270
*vsi_list_id = map_info->vsi_list_id;
+13
-4
drivers/net/ethernet/intel/igb/igb_main.c
+13
-4
drivers/net/ethernet/intel/igb/igb_main.c
···
33
33
#include <linux/bpf_trace.h>
34
34
#include <linux/pm_runtime.h>
35
35
#include <linux/etherdevice.h>
36
+
#include <linux/lockdep.h>
36
37
#ifdef CONFIG_IGB_DCA
37
38
#include <linux/dca.h>
38
39
#endif
···
2915
2914
}
2916
2915
}
2917
2916
2917
+
/* This function assumes __netif_tx_lock is held by the caller. */
2918
2918
static void igb_xdp_ring_update_tail(struct igb_ring *ring)
2919
2919
{
2920
+
lockdep_assert_held(&txring_txq(ring)->_xmit_lock);
2921
+
2920
2922
/* Force memory writes to complete before letting h/w know there
2921
2923
* are new descriptors to fetch.
2922
2924
*/
···
3004
3000
nxmit++;
3005
3001
}
3006
3002
3007
-
__netif_tx_unlock(nq);
3008
-
3009
3003
if (unlikely(flags & XDP_XMIT_FLUSH))
3010
3004
igb_xdp_ring_update_tail(tx_ring);
3005
+
3006
+
__netif_tx_unlock(nq);
3011
3007
3012
3008
return nxmit;
3013
3009
}
···
8868
8864
8869
8865
static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
8870
8866
{
8867
+
unsigned int total_bytes = 0, total_packets = 0;
8871
8868
struct igb_adapter *adapter = q_vector->adapter;
8872
8869
struct igb_ring *rx_ring = q_vector->rx.ring;
8873
-
struct sk_buff *skb = rx_ring->skb;
8874
-
unsigned int total_bytes = 0, total_packets = 0;
8875
8870
u16 cleaned_count = igb_desc_unused(rx_ring);
8871
+
struct sk_buff *skb = rx_ring->skb;
8872
+
int cpu = smp_processor_id();
8876
8873
unsigned int xdp_xmit = 0;
8874
+
struct netdev_queue *nq;
8877
8875
struct xdp_buff xdp;
8878
8876
u32 frame_sz = 0;
8879
8877
int rx_buf_pgcnt;
···
9003
8997
if (xdp_xmit & IGB_XDP_TX) {
9004
8998
struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter);
9005
8999
9000
+
nq = txring_txq(tx_ring);
9001
+
__netif_tx_lock(nq, cpu);
9006
9002
igb_xdp_ring_update_tail(tx_ring);
9003
+
__netif_tx_unlock(nq);
9007
9004
}
9008
9005
9009
9006
u64_stats_update_begin(&rx_ring->rx_syncp);
+1
-2
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+1
-2
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
···
319
319
320
320
/* smq(flush) to tl1 cir/pir info */
321
321
struct nix_smq_tree_ctx {
322
+
u16 schq;
322
323
u64 cir_off;
323
324
u64 cir_val;
324
325
u64 pir_off;
···
329
328
/* smq flush context */
330
329
struct nix_smq_flush_ctx {
331
330
int smq;
332
-
u16 tl1_schq;
333
-
u16 tl2_schq;
334
331
struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT];
335
332
};
336
333
+47
-12
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+47
-12
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
···
2259
2259
schq = smq;
2260
2260
for (lvl = NIX_TXSCH_LVL_SMQ; lvl <= NIX_TXSCH_LVL_TL1; lvl++) {
2261
2261
smq_tree_ctx = &smq_flush_ctx->smq_tree_ctx[lvl];
2262
+
smq_tree_ctx->schq = schq;
2262
2263
if (lvl == NIX_TXSCH_LVL_TL1) {
2263
-
smq_flush_ctx->tl1_schq = schq;
2264
2264
smq_tree_ctx->cir_off = NIX_AF_TL1X_CIR(schq);
2265
2265
smq_tree_ctx->pir_off = 0;
2266
2266
smq_tree_ctx->pir_val = 0;
2267
2267
parent_off = 0;
2268
2268
} else if (lvl == NIX_TXSCH_LVL_TL2) {
2269
-
smq_flush_ctx->tl2_schq = schq;
2270
2269
smq_tree_ctx->cir_off = NIX_AF_TL2X_CIR(schq);
2271
2270
smq_tree_ctx->pir_off = NIX_AF_TL2X_PIR(schq);
2272
2271
parent_off = NIX_AF_TL2X_PARENT(schq);
···
2300
2301
{
2301
2302
struct nix_txsch *txsch;
2302
2303
struct nix_hw *nix_hw;
2304
+
int tl2, tl2_schq;
2303
2305
u64 regoff;
2304
-
int tl2;
2305
2306
2306
2307
nix_hw = get_nix_hw(rvu->hw, blkaddr);
2307
2308
if (!nix_hw)
···
2309
2310
2310
2311
/* loop through all TL2s with matching PF_FUNC */
2311
2312
txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];
2313
+
tl2_schq = smq_flush_ctx->smq_tree_ctx[NIX_TXSCH_LVL_TL2].schq;
2312
2314
for (tl2 = 0; tl2 < txsch->schq.max; tl2++) {
2313
2315
/* skip the smq(flush) TL2 */
2314
-
if (tl2 == smq_flush_ctx->tl2_schq)
2316
+
if (tl2 == tl2_schq)
2315
2317
continue;
2316
2318
/* skip unused TL2s */
2317
2319
if (TXSCH_MAP_FLAGS(txsch->pfvf_map[tl2]) & NIX_TXSCHQ_FREE)
2318
2320
continue;
2319
2321
/* skip if PF_FUNC doesn't match */
2320
2322
if ((TXSCH_MAP_FUNC(txsch->pfvf_map[tl2]) & ~RVU_PFVF_FUNC_MASK) !=
2321
-
(TXSCH_MAP_FUNC(txsch->pfvf_map[smq_flush_ctx->tl2_schq] &
2323
+
(TXSCH_MAP_FUNC(txsch->pfvf_map[tl2_schq] &
2322
2324
~RVU_PFVF_FUNC_MASK)))
2323
2325
continue;
2324
2326
/* enable/disable XOFF */
···
2361
2361
int smq, u16 pcifunc, int nixlf)
2362
2362
{
2363
2363
struct nix_smq_flush_ctx *smq_flush_ctx;
2364
+
int err, restore_tx_en = 0, i;
2364
2365
int pf = rvu_get_pf(pcifunc);
2365
2366
u8 cgx_id = 0, lmac_id = 0;
2366
-
int err, restore_tx_en = 0;
2367
-
u64 cfg;
2367
+
u16 tl2_tl3_link_schq;
2368
+
u8 link, link_level;
2369
+
u64 cfg, bmap = 0;
2368
2370
2369
2371
if (!is_rvu_otx2(rvu)) {
2370
2372
/* Skip SMQ flush if pkt count is zero */
···
2390
2388
nix_smq_flush_enadis_xoff(rvu, blkaddr, smq_flush_ctx, true);
2391
2389
nix_smq_flush_enadis_rate(rvu, blkaddr, smq_flush_ctx, false);
2392
2390
2393
-
cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq));
2394
-
/* Do SMQ flush and set enqueue xoff */
2395
-
cfg |= BIT_ULL(50) | BIT_ULL(49);
2396
-
rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq), cfg);
2397
-
2398
2391
/* Disable backpressure from physical link,
2399
2392
* otherwise SMQ flush may stall.
2400
2393
*/
2401
2394
rvu_cgx_enadis_rx_bp(rvu, pf, false);
2395
+
2396
+
link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ?
2397
+
NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2;
2398
+
tl2_tl3_link_schq = smq_flush_ctx->smq_tree_ctx[link_level].schq;
2399
+
link = smq_flush_ctx->smq_tree_ctx[NIX_TXSCH_LVL_TL1].schq;
2400
+
2401
+
/* SMQ set enqueue xoff */
2402
+
cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq));
2403
+
cfg |= BIT_ULL(50);
2404
+
rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq), cfg);
2405
+
2406
+
/* Clear all NIX_AF_TL3_TL2_LINK_CFG[ENA] for the TL3/TL2 queue */
2407
+
for (i = 0; i < (rvu->hw->cgx_links + rvu->hw->lbk_links); i++) {
2408
+
cfg = rvu_read64(rvu, blkaddr,
2409
+
NIX_AF_TL3_TL2X_LINKX_CFG(tl2_tl3_link_schq, link));
2410
+
if (!(cfg & BIT_ULL(12)))
2411
+
continue;
2412
+
bmap |= (1 << i);
2413
+
cfg &= ~BIT_ULL(12);
2414
+
rvu_write64(rvu, blkaddr,
2415
+
NIX_AF_TL3_TL2X_LINKX_CFG(tl2_tl3_link_schq, link), cfg);
2416
+
}
2417
+
2418
+
/* Do SMQ flush and set enqueue xoff */
2419
+
cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq));
2420
+
cfg |= BIT_ULL(50) | BIT_ULL(49);
2421
+
rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq), cfg);
2402
2422
2403
2423
/* Wait for flush to complete */
2404
2424
err = rvu_poll_reg(rvu, blkaddr,
···
2429
2405
dev_info(rvu->dev,
2430
2406
"NIXLF%d: SMQ%d flush failed, txlink might be busy\n",
2431
2407
nixlf, smq);
2408
+
2409
+
/* Set NIX_AF_TL3_TL2_LINKX_CFG[ENA] for the TL3/TL2 queue */
2410
+
for (i = 0; i < (rvu->hw->cgx_links + rvu->hw->lbk_links); i++) {
2411
+
if (!(bmap & (1 << i)))
2412
+
continue;
2413
+
cfg = rvu_read64(rvu, blkaddr,
2414
+
NIX_AF_TL3_TL2X_LINKX_CFG(tl2_tl3_link_schq, link));
2415
+
cfg |= BIT_ULL(12);
2416
+
rvu_write64(rvu, blkaddr,
2417
+
NIX_AF_TL3_TL2X_LINKX_CFG(tl2_tl3_link_schq, link), cfg);
2418
+
}
2432
2419
2433
2420
/* clear XOFF on TL2s */
2434
2421
nix_smq_flush_enadis_rate(rvu, blkaddr, smq_flush_ctx, true);
+10
drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
+10
drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
···
137
137
ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
138
138
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
139
139
ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
140
+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100BASE_TX, legacy,
141
+
ETHTOOL_LINK_MODE_100baseT_Full_BIT);
142
+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_T, legacy,
143
+
ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
140
144
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
141
145
ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
142
146
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
···
206
202
ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
207
203
ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
208
204
ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
205
+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_8_400GBASE_CR8, ext,
206
+
ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
207
+
ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
208
+
ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
209
+
ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
210
+
ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT);
209
211
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
210
212
ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
211
213
ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
+2
-2
drivers/net/ethernet/mellanox/mlx5/core/esw/legacy.c
+2
-2
drivers/net/ethernet/mellanox/mlx5/core/esw/legacy.c
···
319
319
return -EPERM;
320
320
321
321
mutex_lock(&esw->state_lock);
322
-
if (esw->mode != MLX5_ESWITCH_LEGACY) {
322
+
if (esw->mode != MLX5_ESWITCH_LEGACY || !mlx5_esw_is_fdb_created(esw)) {
323
323
err = -EOPNOTSUPP;
324
324
goto out;
325
325
}
···
339
339
if (!mlx5_esw_allowed(esw))
340
340
return -EPERM;
341
341
342
-
if (esw->mode != MLX5_ESWITCH_LEGACY)
342
+
if (esw->mode != MLX5_ESWITCH_LEGACY || !mlx5_esw_is_fdb_created(esw))
343
343
return -EOPNOTSUPP;
344
344
345
345
*setting = esw->fdb_table.legacy.vepa_uplink_rule ? 1 : 0;
+31
-20
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
+31
-20
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
···
312
312
return err;
313
313
}
314
314
315
+
static bool esw_qos_element_type_supported(struct mlx5_core_dev *dev, int type)
316
+
{
317
+
switch (type) {
318
+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR:
319
+
return MLX5_CAP_QOS(dev, esw_element_type) &
320
+
ELEMENT_TYPE_CAP_MASK_TSAR;
321
+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT:
322
+
return MLX5_CAP_QOS(dev, esw_element_type) &
323
+
ELEMENT_TYPE_CAP_MASK_VPORT;
324
+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC:
325
+
return MLX5_CAP_QOS(dev, esw_element_type) &
326
+
ELEMENT_TYPE_CAP_MASK_VPORT_TC;
327
+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC:
328
+
return MLX5_CAP_QOS(dev, esw_element_type) &
329
+
ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;
330
+
}
331
+
return false;
332
+
}
333
+
315
334
static int esw_qos_vport_create_sched_element(struct mlx5_eswitch *esw,
316
335
struct mlx5_vport *vport,
317
336
u32 max_rate, u32 bw_share)
···
341
322
u32 parent_tsar_ix;
342
323
void *vport_elem;
343
324
int err;
325
+
326
+
if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT))
327
+
return -EOPNOTSUPP;
344
328
345
329
parent_tsar_ix = group ? group->tsar_ix : esw->qos.root_tsar_ix;
346
330
MLX5_SET(scheduling_context, sched_ctx, element_type,
···
443
421
{
444
422
u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {};
445
423
struct mlx5_esw_rate_group *group;
424
+
__be32 *attr;
446
425
u32 divider;
447
426
int err;
448
427
449
428
group = kzalloc(sizeof(*group), GFP_KERNEL);
450
429
if (!group)
451
430
return ERR_PTR(-ENOMEM);
431
+
432
+
MLX5_SET(scheduling_context, tsar_ctx, element_type,
433
+
SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR);
434
+
435
+
attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes);
436
+
*attr = cpu_to_be32(TSAR_ELEMENT_TSAR_TYPE_DWRR << 16);
452
437
453
438
MLX5_SET(scheduling_context, tsar_ctx, parent_element_id,
454
439
esw->qos.root_tsar_ix);
···
555
526
return err;
556
527
}
557
528
558
-
static bool esw_qos_element_type_supported(struct mlx5_core_dev *dev, int type)
559
-
{
560
-
switch (type) {
561
-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR:
562
-
return MLX5_CAP_QOS(dev, esw_element_type) &
563
-
ELEMENT_TYPE_CAP_MASK_TSAR;
564
-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT:
565
-
return MLX5_CAP_QOS(dev, esw_element_type) &
566
-
ELEMENT_TYPE_CAP_MASK_VPORT;
567
-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC:
568
-
return MLX5_CAP_QOS(dev, esw_element_type) &
569
-
ELEMENT_TYPE_CAP_MASK_VPORT_TC;
570
-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC:
571
-
return MLX5_CAP_QOS(dev, esw_element_type) &
572
-
ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;
573
-
}
574
-
return false;
575
-
}
576
-
577
529
static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack)
578
530
{
579
531
u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {};
···
565
555
if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling))
566
556
return -EOPNOTSUPP;
567
557
568
-
if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR))
558
+
if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR) ||
559
+
!(MLX5_CAP_QOS(dev, esw_tsar_type) & TSAR_TYPE_CAP_MASK_DWRR))
569
560
return -EOPNOTSUPP;
570
561
571
562
MLX5_SET(scheduling_context, tsar_ctx, element_type,
+1
drivers/net/ethernet/mellanox/mlx5/core/main.c
+1
drivers/net/ethernet/mellanox/mlx5/core/main.c
···
2223
2223
{ PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
2224
2224
{ PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
2225
2225
{ PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
2226
+
{ PCI_VDEVICE(MELLANOX, 0x1025) }, /* ConnectX-9 */
2226
2227
{ PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2227
2228
{ PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
2228
2229
{ PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
+7
drivers/net/ethernet/mellanox/mlx5/core/qos.c
+7
drivers/net/ethernet/mellanox/mlx5/core/qos.c
···
28
28
{
29
29
u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
30
30
31
+
if (!(MLX5_CAP_QOS(mdev, nic_element_type) & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP))
32
+
return -EOPNOTSUPP;
33
+
31
34
MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
32
35
MLX5_SET(scheduling_context, sched_ctx, element_type,
33
36
SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP);
···
46
43
{
47
44
u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
48
45
void *attr;
46
+
47
+
if (!(MLX5_CAP_QOS(mdev, nic_element_type) & ELEMENT_TYPE_CAP_MASK_TSAR) ||
48
+
!(MLX5_CAP_QOS(mdev, nic_tsar_type) & TSAR_TYPE_CAP_MASK_DWRR))
49
+
return -EOPNOTSUPP;
49
50
50
51
MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
51
52
MLX5_SET(scheduling_context, sched_ctx, element_type,
+3
-3
drivers/net/ethernet/wangxun/libwx/wx_type.h
+3
-3
drivers/net/ethernet/wangxun/libwx/wx_type.h
···
426
426
#define WX_MIN_RXD 128
427
427
#define WX_MIN_TXD 128
428
428
429
-
/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
430
-
#define WX_REQ_RX_DESCRIPTOR_MULTIPLE 8
431
-
#define WX_REQ_TX_DESCRIPTOR_MULTIPLE 8
429
+
/* Number of Transmit and Receive Descriptors must be a multiple of 128 */
430
+
#define WX_REQ_RX_DESCRIPTOR_MULTIPLE 128
431
+
#define WX_REQ_TX_DESCRIPTOR_MULTIPLE 128
432
432
433
433
#define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
434
434
#define VMDQ_P(p) p
+22
-13
drivers/net/phy/dp83822.c
+22
-13
drivers/net/phy/dp83822.c
···
271
271
DP83822_ENERGY_DET_INT_EN |
272
272
DP83822_LINK_QUAL_INT_EN);
273
273
274
-
/* Private data pointer is NULL on DP83825 */
275
-
if (!dp83822 || !dp83822->fx_enabled)
274
+
if (!dp83822->fx_enabled)
276
275
misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
277
276
DP83822_DUP_MODE_CHANGE_INT_EN |
278
277
DP83822_SPEED_CHANGED_INT_EN;
···
291
292
DP83822_PAGE_RX_INT_EN |
292
293
DP83822_EEE_ERROR_CHANGE_INT_EN);
293
294
294
-
/* Private data pointer is NULL on DP83825 */
295
-
if (!dp83822 || !dp83822->fx_enabled)
295
+
if (!dp83822->fx_enabled)
296
296
misr_status |= DP83822_ANEG_ERR_INT_EN |
297
297
DP83822_WOL_PKT_INT_EN;
298
298
···
689
691
return 0;
690
692
}
691
693
692
-
static int dp83822_probe(struct phy_device *phydev)
694
+
static int dp8382x_probe(struct phy_device *phydev)
693
695
{
694
696
struct dp83822_private *dp83822;
695
-
int ret;
696
697
697
698
dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
698
699
GFP_KERNEL);
···
699
702
return -ENOMEM;
700
703
701
704
phydev->priv = dp83822;
705
+
706
+
return 0;
707
+
}
708
+
709
+
static int dp83822_probe(struct phy_device *phydev)
710
+
{
711
+
struct dp83822_private *dp83822;
712
+
int ret;
713
+
714
+
ret = dp8382x_probe(phydev);
715
+
if (ret)
716
+
return ret;
717
+
718
+
dp83822 = phydev->priv;
702
719
703
720
ret = dp83822_read_straps(phydev);
704
721
if (ret)
···
728
717
729
718
static int dp83826_probe(struct phy_device *phydev)
730
719
{
731
-
struct dp83822_private *dp83822;
720
+
int ret;
732
721
733
-
dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
734
-
GFP_KERNEL);
735
-
if (!dp83822)
736
-
return -ENOMEM;
737
-
738
-
phydev->priv = dp83822;
722
+
ret = dp8382x_probe(phydev);
723
+
if (ret)
724
+
return ret;
739
725
740
726
dp83826_of_init(phydev);
741
727
···
803
795
PHY_ID_MATCH_MODEL(_id), \
804
796
.name = (_name), \
805
797
/* PHY_BASIC_FEATURES */ \
798
+
.probe = dp8382x_probe, \
806
799
.soft_reset = dp83822_phy_reset, \
807
800
.config_init = dp8382x_config_init, \
808
801
.get_wol = dp83822_get_wol, \
+48
-51
drivers/net/virtio_net.c
+48
-51
drivers/net/virtio_net.c
···
356
356
struct xdp_rxq_info xsk_rxq_info;
357
357
358
358
struct xdp_buff **xsk_buffs;
359
+
360
+
/* Do dma by self */
361
+
bool do_dma;
359
362
};
360
363
361
364
/* This structure can contain rss message with maximum settings for indirection table and keysize
···
888
885
void *buf;
889
886
890
887
buf = virtqueue_get_buf_ctx(rq->vq, len, ctx);
891
-
if (buf)
888
+
if (buf && rq->do_dma)
892
889
virtnet_rq_unmap(rq, buf, *len);
893
890
894
891
return buf;
···
900
897
dma_addr_t addr;
901
898
u32 offset;
902
899
void *head;
900
+
901
+
if (!rq->do_dma) {
902
+
sg_init_one(rq->sg, buf, len);
903
+
return;
904
+
}
903
905
904
906
head = page_address(rq->alloc_frag.page);
905
907
···
931
923
932
924
head = page_address(alloc_frag->page);
933
925
934
-
dma = head;
926
+
if (rq->do_dma) {
927
+
dma = head;
935
928
936
-
/* new pages */
937
-
if (!alloc_frag->offset) {
938
-
if (rq->last_dma) {
939
-
/* Now, the new page is allocated, the last dma
940
-
* will not be used. So the dma can be unmapped
941
-
* if the ref is 0.
929
+
/* new pages */
930
+
if (!alloc_frag->offset) {
931
+
if (rq->last_dma) {
932
+
/* Now, the new page is allocated, the last dma
933
+
* will not be used. So the dma can be unmapped
934
+
* if the ref is 0.
935
+
*/
936
+
virtnet_rq_unmap(rq, rq->last_dma, 0);
937
+
rq->last_dma = NULL;
938
+
}
939
+
940
+
dma->len = alloc_frag->size - sizeof(*dma);
941
+
942
+
addr = virtqueue_dma_map_single_attrs(rq->vq, dma + 1,
943
+
dma->len, DMA_FROM_DEVICE, 0);
944
+
if (virtqueue_dma_mapping_error(rq->vq, addr))
945
+
return NULL;
946
+
947
+
dma->addr = addr;
948
+
dma->need_sync = virtqueue_dma_need_sync(rq->vq, addr);
949
+
950
+
/* Add a reference to dma to prevent the entire dma from
951
+
* being released during error handling. This reference
952
+
* will be freed after the pages are no longer used.
942
953
*/
943
-
virtnet_rq_unmap(rq, rq->last_dma, 0);
944
-
rq->last_dma = NULL;
954
+
get_page(alloc_frag->page);
955
+
dma->ref = 1;
956
+
alloc_frag->offset = sizeof(*dma);
957
+
958
+
rq->last_dma = dma;
945
959
}
946
960
947
-
dma->len = alloc_frag->size - sizeof(*dma);
948
-
949
-
addr = virtqueue_dma_map_single_attrs(rq->vq, dma + 1,
950
-
dma->len, DMA_FROM_DEVICE, 0);
951
-
if (virtqueue_dma_mapping_error(rq->vq, addr))
952
-
return NULL;
953
-
954
-
dma->addr = addr;
955
-
dma->need_sync = virtqueue_dma_need_sync(rq->vq, addr);
956
-
957
-
/* Add a reference to dma to prevent the entire dma from
958
-
* being released during error handling. This reference
959
-
* will be freed after the pages are no longer used.
960
-
*/
961
-
get_page(alloc_frag->page);
962
-
dma->ref = 1;
963
-
alloc_frag->offset = sizeof(*dma);
964
-
965
-
rq->last_dma = dma;
961
+
++dma->ref;
966
962
}
967
-
968
-
++dma->ref;
969
963
970
964
buf = head + alloc_frag->offset;
971
965
···
975
965
alloc_frag->offset += size;
976
966
977
967
return buf;
978
-
}
979
-
980
-
static void virtnet_rq_set_premapped(struct virtnet_info *vi)
981
-
{
982
-
int i;
983
-
984
-
/* disable for big mode */
985
-
if (!vi->mergeable_rx_bufs && vi->big_packets)
986
-
return;
987
-
988
-
for (i = 0; i < vi->max_queue_pairs; i++)
989
-
/* error should never happen */
990
-
BUG_ON(virtqueue_set_dma_premapped(vi->rq[i].vq));
991
968
}
992
969
993
970
static void virtnet_rq_unmap_free_buf(struct virtqueue *vq, void *buf)
···
990
993
return;
991
994
}
992
995
993
-
if (!vi->big_packets || vi->mergeable_rx_bufs)
996
+
if (rq->do_dma)
994
997
virtnet_rq_unmap(rq, buf, 0);
995
998
996
999
virtnet_rq_free_buf(vi, rq, buf);
···
2427
2430
2428
2431
err = virtqueue_add_inbuf_ctx(rq->vq, rq->sg, 1, buf, ctx, gfp);
2429
2432
if (err < 0) {
2430
-
virtnet_rq_unmap(rq, buf, 0);
2433
+
if (rq->do_dma)
2434
+
virtnet_rq_unmap(rq, buf, 0);
2431
2435
put_page(virt_to_head_page(buf));
2432
2436
}
2433
2437
···
2542
2544
ctx = mergeable_len_to_ctx(len + room, headroom);
2543
2545
err = virtqueue_add_inbuf_ctx(rq->vq, rq->sg, 1, buf, ctx, gfp);
2544
2546
if (err < 0) {
2545
-
virtnet_rq_unmap(rq, buf, 0);
2547
+
if (rq->do_dma)
2548
+
virtnet_rq_unmap(rq, buf, 0);
2546
2549
put_page(virt_to_head_page(buf));
2547
2550
}
2548
2551
···
2700
2701
}
2701
2702
} else {
2702
2703
while (packets < budget &&
2703
-
(buf = virtqueue_get_buf(rq->vq, &len)) != NULL) {
2704
+
(buf = virtnet_rq_get_buf(rq, &len, NULL)) != NULL) {
2704
2705
receive_buf(vi, rq, buf, len, NULL, xdp_xmit, stats);
2705
2706
packets++;
2706
2707
}
···
5910
5911
int i;
5911
5912
for (i = 0; i < vi->max_queue_pairs; i++)
5912
5913
if (vi->rq[i].alloc_frag.page) {
5913
-
if (vi->rq[i].last_dma)
5914
+
if (vi->rq[i].do_dma && vi->rq[i].last_dma)
5914
5915
virtnet_rq_unmap(&vi->rq[i], vi->rq[i].last_dma, 0);
5915
5916
put_page(vi->rq[i].alloc_frag.page);
5916
5917
}
···
6107
6108
ret = virtnet_find_vqs(vi);
6108
6109
if (ret)
6109
6110
goto err_free;
6110
-
6111
-
virtnet_rq_set_premapped(vi);
6112
6111
6113
6112
cpus_read_lock();
6114
6113
virtnet_set_affinity(vi);
+2
-1
drivers/nvme/host/core.c
+2
-1
drivers/nvme/host/core.c
···
4437
4437
4438
4438
static void nvme_handle_aer_persistent_error(struct nvme_ctrl *ctrl)
4439
4439
{
4440
-
dev_warn(ctrl->device, "resetting controller due to AER\n");
4440
+
dev_warn(ctrl->device,
4441
+
"resetting controller due to persistent internal error\n");
4441
4442
nvme_reset_ctrl(ctrl);
4442
4443
}
4443
4444
+3
-1
drivers/nvme/host/multipath.c
+3
-1
drivers/nvme/host/multipath.c
···
616
616
blk_set_stacking_limits(&lim);
617
617
lim.dma_alignment = 3;
618
618
lim.features |= BLK_FEAT_IO_STAT | BLK_FEAT_NOWAIT | BLK_FEAT_POLL;
619
-
if (head->ids.csi != NVME_CSI_ZNS)
619
+
if (head->ids.csi == NVME_CSI_ZNS)
620
+
lim.features |= BLK_FEAT_ZONED;
621
+
else
620
622
lim.max_zone_append_sectors = 0;
621
623
622
624
head->disk = blk_alloc_disk(&lim, ctrl->numa_node);
+17
drivers/nvme/host/pci.c
+17
drivers/nvme/host/pci.c
···
2508
2508
2509
2509
static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2510
2510
{
2511
+
if (!dev->ctrl.tagset) {
2512
+
nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
2513
+
nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
2514
+
return;
2515
+
}
2516
+
2511
2517
blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2512
2518
/* free previously allocated queues that are no longer usable */
2513
2519
nvme_free_queues(dev, dev->online_queues);
···
2972
2966
dmi_match(DMI_BOARD_NAME, "NS5x_7xAU") ||
2973
2967
dmi_match(DMI_BOARD_NAME, "NS5x_7xPU") ||
2974
2968
dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1"))
2969
+
return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
2970
+
} else if (pdev->vendor == 0x144d && pdev->device == 0xa80d) {
2971
+
/*
2972
+
* Exclude Samsung 990 Evo from NVME_QUIRK_SIMPLE_SUSPEND
2973
+
* because of high power consumption (> 2 Watt) in s2idle
2974
+
* sleep. Only some boards with Intel CPU are affected.
2975
+
*/
2976
+
if (dmi_match(DMI_BOARD_NAME, "GMxPXxx") ||
2977
+
dmi_match(DMI_BOARD_NAME, "PH4PG31") ||
2978
+
dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1") ||
2979
+
dmi_match(DMI_BOARD_NAME, "PH6PG01_PH6PG71"))
2975
2980
return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
2976
2981
}
2977
2982
+10
drivers/nvme/target/admin-cmd.c
+10
drivers/nvme/target/admin-cmd.c
···
587
587
u16 status = 0;
588
588
int i = 0;
589
589
590
+
/*
591
+
* NSID values 0xFFFFFFFE and NVME_NSID_ALL are invalid
592
+
* See NVMe Base Specification, Active Namespace ID list (CNS 02h).
593
+
*/
594
+
if (min_nsid == 0xFFFFFFFE || min_nsid == NVME_NSID_ALL) {
595
+
req->error_loc = offsetof(struct nvme_identify, nsid);
596
+
status = NVME_SC_INVALID_NS | NVME_STATUS_DNR;
597
+
goto out;
598
+
}
599
+
590
600
list = kzalloc(buf_size, GFP_KERNEL);
591
601
if (!list) {
592
602
status = NVME_SC_INTERNAL;
+1
-1
drivers/nvme/target/debugfs.c
+1
-1
drivers/nvme/target/debugfs.c
+3
-1
drivers/nvme/target/tcp.c
+3
-1
drivers/nvme/target/tcp.c
+3
-3
drivers/nvmem/core.c
+3
-3
drivers/nvmem/core.c
···
1276
1276
EXPORT_SYMBOL_GPL(nvmem_device_put);
1277
1277
1278
1278
/**
1279
-
* devm_nvmem_device_get() - Get nvmem cell of device form a given id
1279
+
* devm_nvmem_device_get() - Get nvmem device of device form a given id
1280
1280
*
1281
1281
* @dev: Device that requests the nvmem device.
1282
1282
* @id: name id for the requested nvmem device.
1283
1283
*
1284
-
* Return: ERR_PTR() on error or a valid pointer to a struct nvmem_cell
1285
-
* on success. The nvmem_cell will be freed by the automatically once the
1284
+
* Return: ERR_PTR() on error or a valid pointer to a struct nvmem_device
1285
+
* on success. The nvmem_device will be freed by the automatically once the
1286
1286
* device is freed.
1287
1287
*/
1288
1288
struct nvmem_device *devm_nvmem_device_get(struct device *dev, const char *id)
+7
drivers/nvmem/u-boot-env.c
+7
drivers/nvmem/u-boot-env.c
···
176
176
data_offset = offsetof(struct u_boot_env_image_broadcom, data);
177
177
break;
178
178
}
179
+
180
+
if (dev_size < data_offset) {
181
+
dev_err(dev, "Device too small for u-boot-env\n");
182
+
err = -EIO;
183
+
goto err_kfree;
184
+
}
185
+
179
186
crc32_addr = (__le32 *)(buf + crc32_offset);
180
187
crc32 = le32_to_cpu(*crc32_addr);
181
188
crc32_data_len = dev_size - crc32_data_offset;
+22
-34
drivers/opp/core.c
+22
-34
drivers/opp/core.c
···
1061
1061
return 0;
1062
1062
}
1063
1063
1064
+
static int _set_opp_level(struct device *dev, struct dev_pm_opp *opp)
1065
+
{
1066
+
unsigned int level = 0;
1067
+
int ret = 0;
1068
+
1069
+
if (opp) {
1070
+
if (opp->level == OPP_LEVEL_UNSET)
1071
+
return 0;
1072
+
1073
+
level = opp->level;
1074
+
}
1075
+
1076
+
/* Request a new performance state through the device's PM domain. */
1077
+
ret = dev_pm_domain_set_performance_state(dev, level);
1078
+
if (ret)
1079
+
dev_err(dev, "Failed to set performance state %u (%d)\n", level,
1080
+
ret);
1081
+
1082
+
return ret;
1083
+
}
1084
+
1064
1085
/* This is only called for PM domain for now */
1065
1086
static int _set_required_opps(struct device *dev, struct opp_table *opp_table,
1066
1087
struct dev_pm_opp *opp, bool up)
···
1112
1091
if (devs[index]) {
1113
1092
required_opp = opp ? opp->required_opps[index] : NULL;
1114
1093
1115
-
ret = dev_pm_opp_set_opp(devs[index], required_opp);
1094
+
ret = _set_opp_level(devs[index], required_opp);
1116
1095
if (ret)
1117
1096
return ret;
1118
1097
}
···
1121
1100
}
1122
1101
1123
1102
return 0;
1124
-
}
1125
-
1126
-
static int _set_opp_level(struct device *dev, struct dev_pm_opp *opp)
1127
-
{
1128
-
unsigned int level = 0;
1129
-
int ret = 0;
1130
-
1131
-
if (opp) {
1132
-
if (opp->level == OPP_LEVEL_UNSET)
1133
-
return 0;
1134
-
1135
-
level = opp->level;
1136
-
}
1137
-
1138
-
/* Request a new performance state through the device's PM domain. */
1139
-
ret = dev_pm_domain_set_performance_state(dev, level);
1140
-
if (ret)
1141
-
dev_err(dev, "Failed to set performance state %u (%d)\n", level,
1142
-
ret);
1143
-
1144
-
return ret;
1145
1103
}
1146
1104
1147
1105
static void _find_current_opp(struct device *dev, struct opp_table *opp_table)
···
2455
2455
} else {
2456
2456
dev_pm_opp_put_opp_table(genpd_table);
2457
2457
}
2458
-
}
2459
-
2460
-
/*
2461
-
* Add the virtual genpd device as a user of the OPP table, so
2462
-
* we can call dev_pm_opp_set_opp() on it directly.
2463
-
*
2464
-
* This will be automatically removed when the OPP table is
2465
-
* removed, don't need to handle that here.
2466
-
*/
2467
-
if (!_add_opp_dev(virt_dev, opp_table->required_opp_tables[index])) {
2468
-
ret = -ENOMEM;
2469
-
goto err;
2470
2458
}
2471
2459
2472
2460
opp_table->required_devs[index] = virt_dev;
+23
-3
drivers/pci/pwrctl/core.c
+23
-3
drivers/pci/pwrctl/core.c
···
48
48
return NOTIFY_DONE;
49
49
}
50
50
51
+
static void rescan_work_func(struct work_struct *work)
52
+
{
53
+
struct pci_pwrctl *pwrctl = container_of(work, struct pci_pwrctl, work);
54
+
55
+
pci_lock_rescan_remove();
56
+
pci_rescan_bus(to_pci_dev(pwrctl->dev->parent)->bus);
57
+
pci_unlock_rescan_remove();
58
+
}
59
+
60
+
/**
61
+
* pci_pwrctl_init() - Initialize the PCI power control context struct
62
+
*
63
+
* @pwrctl: PCI power control data
64
+
* @dev: Parent device
65
+
*/
66
+
void pci_pwrctl_init(struct pci_pwrctl *pwrctl, struct device *dev)
67
+
{
68
+
pwrctl->dev = dev;
69
+
INIT_WORK(&pwrctl->work, rescan_work_func);
70
+
}
71
+
EXPORT_SYMBOL_GPL(pci_pwrctl_init);
72
+
51
73
/**
52
74
* pci_pwrctl_device_set_ready() - Notify the pwrctl subsystem that the PCI
53
75
* device is powered-up and ready to be detected.
···
96
74
if (ret)
97
75
return ret;
98
76
99
-
pci_lock_rescan_remove();
100
-
pci_rescan_bus(to_pci_dev(pwrctl->dev->parent)->bus);
101
-
pci_unlock_rescan_remove();
77
+
schedule_work(&pwrctl->work);
102
78
103
79
return 0;
104
80
}
+1
-1
drivers/pci/pwrctl/pci-pwrctl-pwrseq.c
+1
-1
drivers/pci/pwrctl/pci-pwrctl-pwrseq.c
+17
-1
drivers/pci/remove.c
+17
-1
drivers/pci/remove.c
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
#include <linux/pci.h>
3
3
#include <linux/module.h>
4
+
#include <linux/of.h>
4
5
#include <linux/of_platform.h>
6
+
#include <linux/platform_device.h>
7
+
5
8
#include "pci.h"
6
9
7
10
static void pci_free_resources(struct pci_dev *dev)
···
17
14
}
18
15
}
19
16
17
+
static int pci_pwrctl_unregister(struct device *dev, void *data)
18
+
{
19
+
struct device_node *pci_node = data, *plat_node = dev_of_node(dev);
20
+
21
+
if (dev_is_platform(dev) && plat_node && plat_node == pci_node) {
22
+
of_device_unregister(to_platform_device(dev));
23
+
of_node_clear_flag(plat_node, OF_POPULATED);
24
+
}
25
+
26
+
return 0;
27
+
}
28
+
20
29
static void pci_stop_dev(struct pci_dev *dev)
21
30
{
22
31
pci_pme_active(dev, false);
23
32
24
33
if (pci_dev_is_added(dev)) {
25
-
of_platform_depopulate(&dev->dev);
34
+
device_for_each_child(dev->dev.parent, dev_of_node(&dev->dev),
35
+
pci_pwrctl_unregister);
26
36
device_release_driver(&dev->dev);
27
37
pci_proc_detach_device(dev);
28
38
pci_remove_sysfs_dev_files(dev);
+3
-1
drivers/pinctrl/qcom/pinctrl-x1e80100.c
+3
-1
drivers/pinctrl/qcom/pinctrl-x1e80100.c
···
1839
1839
.ngroups = ARRAY_SIZE(x1e80100_groups),
1840
1840
.ngpios = 239,
1841
1841
.wakeirq_map = x1e80100_pdc_map,
1842
-
.nwakeirq_map = ARRAY_SIZE(x1e80100_pdc_map),
1842
+
/* TODO: Enabling PDC currently breaks GPIO interrupts */
1843
+
.nwakeirq_map = 0,
1844
+
/* .nwakeirq_map = ARRAY_SIZE(x1e80100_pdc_map), */
1843
1845
.egpio_func = 9,
1844
1846
};
1845
1847
+1
-1
drivers/platform/cznic/Kconfig
+1
-1
drivers/platform/cznic/Kconfig
···
70
70
bool "Turris Omnia MCU true random number generator"
71
71
default y
72
72
depends on TURRIS_OMNIA_MCU_GPIO
73
-
depends on HW_RANDOM
73
+
depends on HW_RANDOM=y || HW_RANDOM=TURRIS_OMNIA_MCU
74
74
help
75
75
Say Y here to add support for the true random number generator
76
76
provided by CZ.NIC's Turris Omnia MCU.
+10
drivers/platform/x86/asus-wmi.c
+10
drivers/platform/x86/asus-wmi.c
···
1793
1793
goto error;
1794
1794
}
1795
1795
1796
+
if (asus_wmi_dev_is_present(asus, ASUS_WMI_DEVID_OOBE)) {
1797
+
/*
1798
+
* Disable OOBE state, so that e.g. the keyboard backlight
1799
+
* works.
1800
+
*/
1801
+
rv = asus_wmi_set_devstate(ASUS_WMI_DEVID_OOBE, 1, NULL);
1802
+
if (rv)
1803
+
goto error;
1804
+
}
1805
+
1796
1806
error:
1797
1807
if (rv)
1798
1808
asus_wmi_led_exit(asus);
+47
-11
drivers/platform/x86/panasonic-laptop.c
+47
-11
drivers/platform/x86/panasonic-laptop.c
···
337
337
}
338
338
339
339
if (pcc->num_sifr < hkey->package.count) {
340
-
pr_err("SQTY reports bad SINF length\n");
340
+
pr_err("SQTY reports bad SINF length SQTY: %lu SINF-pkg-count: %u\n",
341
+
pcc->num_sifr, hkey->package.count);
341
342
status = AE_ERROR;
342
343
goto end;
343
344
}
···
774
773
static DEVICE_ATTR_RW(current_brightness);
775
774
static DEVICE_ATTR_RW(cdpower);
776
775
776
+
static umode_t pcc_sysfs_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
777
+
{
778
+
struct device *dev = kobj_to_dev(kobj);
779
+
struct acpi_device *acpi = to_acpi_device(dev);
780
+
struct pcc_acpi *pcc = acpi_driver_data(acpi);
781
+
782
+
if (attr == &dev_attr_mute.attr)
783
+
return (pcc->num_sifr > SINF_MUTE) ? attr->mode : 0;
784
+
785
+
if (attr == &dev_attr_eco_mode.attr)
786
+
return (pcc->num_sifr > SINF_ECO_MODE) ? attr->mode : 0;
787
+
788
+
if (attr == &dev_attr_current_brightness.attr)
789
+
return (pcc->num_sifr > SINF_CUR_BRIGHT) ? attr->mode : 0;
790
+
791
+
return attr->mode;
792
+
}
793
+
777
794
static struct attribute *pcc_sysfs_entries[] = {
778
795
&dev_attr_numbatt.attr,
779
796
&dev_attr_lcdtype.attr,
···
806
787
};
807
788
808
789
static const struct attribute_group pcc_attr_group = {
809
-
.name = NULL, /* put in device directory */
810
-
.attrs = pcc_sysfs_entries,
790
+
.name = NULL, /* put in device directory */
791
+
.attrs = pcc_sysfs_entries,
792
+
.is_visible = pcc_sysfs_is_visible,
811
793
};
812
794
813
795
···
961
941
if (!pcc)
962
942
return -EINVAL;
963
943
964
-
acpi_pcc_write_sset(pcc, SINF_MUTE, pcc->mute);
965
-
acpi_pcc_write_sset(pcc, SINF_ECO_MODE, pcc->eco_mode);
944
+
if (pcc->num_sifr > SINF_MUTE)
945
+
acpi_pcc_write_sset(pcc, SINF_MUTE, pcc->mute);
946
+
if (pcc->num_sifr > SINF_ECO_MODE)
947
+
acpi_pcc_write_sset(pcc, SINF_ECO_MODE, pcc->eco_mode);
966
948
acpi_pcc_write_sset(pcc, SINF_STICKY_KEY, pcc->sticky_key);
967
949
acpi_pcc_write_sset(pcc, SINF_AC_CUR_BRIGHT, pcc->ac_brightness);
968
950
acpi_pcc_write_sset(pcc, SINF_DC_CUR_BRIGHT, pcc->dc_brightness);
969
-
acpi_pcc_write_sset(pcc, SINF_CUR_BRIGHT, pcc->current_brightness);
951
+
if (pcc->num_sifr > SINF_CUR_BRIGHT)
952
+
acpi_pcc_write_sset(pcc, SINF_CUR_BRIGHT, pcc->current_brightness);
970
953
971
954
return 0;
972
955
}
···
986
963
987
964
num_sifr = acpi_pcc_get_sqty(device);
988
965
989
-
if (num_sifr < 0 || num_sifr > 255) {
990
-
pr_err("num_sifr out of range");
966
+
/*
967
+
* pcc->sinf is expected to at least have the AC+DC brightness entries.
968
+
* Accesses to higher SINF entries are checked against num_sifr.
969
+
*/
970
+
if (num_sifr <= SINF_DC_CUR_BRIGHT || num_sifr > 255) {
971
+
pr_err("num_sifr %d out of range %d - 255\n", num_sifr, SINF_DC_CUR_BRIGHT + 1);
991
972
return -ENODEV;
992
973
}
974
+
975
+
/*
976
+
* Some DSDT-s have an off-by-one bug where the SINF package count is
977
+
* one higher than the SQTY reported value, allocate 1 entry extra.
978
+
*/
979
+
num_sifr++;
993
980
994
981
pcc = kzalloc(sizeof(struct pcc_acpi), GFP_KERNEL);
995
982
if (!pcc) {
···
1053
1020
acpi_pcc_write_sset(pcc, SINF_STICKY_KEY, 0);
1054
1021
pcc->sticky_key = 0;
1055
1022
1056
-
pcc->eco_mode = pcc->sinf[SINF_ECO_MODE];
1057
-
pcc->mute = pcc->sinf[SINF_MUTE];
1058
1023
pcc->ac_brightness = pcc->sinf[SINF_AC_CUR_BRIGHT];
1059
1024
pcc->dc_brightness = pcc->sinf[SINF_DC_CUR_BRIGHT];
1060
-
pcc->current_brightness = pcc->sinf[SINF_CUR_BRIGHT];
1025
+
if (pcc->num_sifr > SINF_MUTE)
1026
+
pcc->mute = pcc->sinf[SINF_MUTE];
1027
+
if (pcc->num_sifr > SINF_ECO_MODE)
1028
+
pcc->eco_mode = pcc->sinf[SINF_ECO_MODE];
1029
+
if (pcc->num_sifr > SINF_CUR_BRIGHT)
1030
+
pcc->current_brightness = pcc->sinf[SINF_CUR_BRIGHT];
1061
1031
1062
1032
/* add sysfs attributes */
1063
1033
result = sysfs_create_group(&device->dev.kobj, &pcc_attr_group);
+1
-1
drivers/pwm/pwm-stm32.c
+1
-1
drivers/pwm/pwm-stm32.c
+1
-1
drivers/staging/iio/frequency/ad9834.c
+1
-1
drivers/staging/iio/frequency/ad9834.c
+19
-7
drivers/staging/media/atomisp/pci/sh_css_frac.h
+19
-7
drivers/staging/media/atomisp/pci/sh_css_frac.h
···
32
32
#define uISP_VAL_MAX ((unsigned int)((1 << uISP_REG_BIT) - 1))
33
33
34
34
/* a:fraction bits for 16bit precision, b:fraction bits for ISP precision */
35
-
#define sDIGIT_FITTING(v, a, b) \
36
-
min_t(int, max_t(int, (((v) >> sSHIFT) >> max(sFRACTION_BITS_FITTING(a) - (b), 0)), \
37
-
sISP_VAL_MIN), sISP_VAL_MAX)
38
-
#define uDIGIT_FITTING(v, a, b) \
39
-
min((unsigned int)max((unsigned)(((v) >> uSHIFT) \
40
-
>> max((int)(uFRACTION_BITS_FITTING(a) - (b)), 0)), \
41
-
uISP_VAL_MIN), uISP_VAL_MAX)
35
+
static inline int sDIGIT_FITTING(int v, int a, int b)
36
+
{
37
+
int fit_shift = sFRACTION_BITS_FITTING(a) - b;
38
+
39
+
v >>= sSHIFT;
40
+
v >>= fit_shift > 0 ? fit_shift : 0;
41
+
42
+
return clamp_t(int, v, sISP_VAL_MIN, sISP_VAL_MAX);
43
+
}
44
+
45
+
static inline unsigned int uDIGIT_FITTING(unsigned int v, int a, int b)
46
+
{
47
+
int fit_shift = uFRACTION_BITS_FITTING(a) - b;
48
+
49
+
v >>= uSHIFT;
50
+
v >>= fit_shift > 0 ? fit_shift : 0;
51
+
52
+
return clamp_t(unsigned int, v, uISP_VAL_MIN, uISP_VAL_MAX);
53
+
}
42
54
43
55
#endif /* __SH_CSS_FRAC_H */
+3
drivers/ufs/host/ufs-mediatek.c
+3
drivers/ufs/host/ufs-mediatek.c
+10
-1
drivers/uio/uio_hv_generic.c
+10
-1
drivers/uio/uio_hv_generic.c
···
106
106
107
107
/*
108
108
* Callback from vmbus_event when channel is rescinded.
109
+
* It is meant for rescind of primary channels only.
109
110
*/
110
111
static void hv_uio_rescind(struct vmbus_channel *channel)
111
112
{
112
-
struct hv_device *hv_dev = channel->primary_channel->device_obj;
113
+
struct hv_device *hv_dev = channel->device_obj;
113
114
struct hv_uio_private_data *pdata = hv_get_drvdata(hv_dev);
114
115
115
116
/*
···
121
120
122
121
/* Wake up reader */
123
122
uio_event_notify(&pdata->info);
123
+
124
+
/*
125
+
* With rescind callback registered, rescind path will not unregister the device
126
+
* from vmbus when the primary channel is rescinded.
127
+
* Without it, rescind handling is incomplete and next onoffer msg does not come.
128
+
* Unregister the device from vmbus here.
129
+
*/
130
+
vmbus_device_unregister(channel->device_obj);
124
131
}
125
132
126
133
/* Sysfs API to allow mmap of the ring buffers
+15
drivers/usb/dwc3/core.c
+15
drivers/usb/dwc3/core.c
···
1387
1387
}
1388
1388
1389
1389
/*
1390
+
* STAR 9001285599: This issue affects DWC_usb3 version 3.20a
1391
+
* only. If the PM TIMER ECM is enabled through GUCTL2[19], the
1392
+
* link compliance test (TD7.21) may fail. If the ECN is not
1393
+
* enabled (GUCTL2[19] = 0), the controller will use the old timer
1394
+
* value (5us), which is still acceptable for the link compliance
1395
+
* test. Therefore, do not enable PM TIMER ECM in 3.20a by
1396
+
* setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0.
1397
+
*/
1398
+
if (DWC3_VER_IS(DWC3, 320A)) {
1399
+
reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1400
+
reg &= ~DWC3_GUCTL2_LC_TIMER;
1401
+
dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1402
+
}
1403
+
1404
+
/*
1390
1405
* When configured in HOST mode, after issuing U3/L2 exit controller
1391
1406
* fails to send proper CRC checksum in CRC5 feild. Because of this
1392
1407
* behaviour Transaction Error is generated, resulting in reset and
+2
drivers/usb/dwc3/core.h
+2
drivers/usb/dwc3/core.h
···
421
421
422
422
/* Global User Control Register 2 */
423
423
#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
424
+
#define DWC3_GUCTL2_LC_TIMER BIT(19)
424
425
425
426
/* Global User Control Register 3 */
426
427
#define DWC3_GUCTL3_SPLITDISABLE BIT(14)
···
1270
1269
#define DWC3_REVISION_290A 0x5533290a
1271
1270
#define DWC3_REVISION_300A 0x5533300a
1272
1271
#define DWC3_REVISION_310A 0x5533310a
1272
+
#define DWC3_REVISION_320A 0x5533320a
1273
1273
#define DWC3_REVISION_330A 0x5533330a
1274
1274
1275
1275
#define DWC31_REVISION_ANY 0x0
+17
-24
drivers/usb/dwc3/gadget.c
+17
-24
drivers/usb/dwc3/gadget.c
···
287
287
*
288
288
* Caller should handle locking. This function will issue @cmd with given
289
289
* @params to @dep and wait for its completion.
290
+
*
291
+
* According to the programming guide, if the link state is in L1/L2/U3,
292
+
* then sending the Start Transfer command may not complete. The
293
+
* programming guide suggested to bring the link state back to ON/U0 by
294
+
* performing remote wakeup prior to sending the command. However, don't
295
+
* initiate remote wakeup when the user/function does not send wakeup
296
+
* request via wakeup ops. Send the command when it's allowed.
297
+
*
298
+
* Notes:
299
+
* For L1 link state, issuing a command requires the clearing of
300
+
* GUSB2PHYCFG.SUSPENDUSB2, which turns on the signal required to complete
301
+
* the given command (usually within 50us). This should happen within the
302
+
* command timeout set by driver. No additional step is needed.
303
+
*
304
+
* For L2 or U3 link state, the gadget is in USB suspend. Care should be
305
+
* taken when sending Start Transfer command to ensure that it's done after
306
+
* USB resume.
290
307
*/
291
308
int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
292
309
struct dwc3_gadget_ep_cmd_params *params)
···
342
325
343
326
if (saved_config)
344
327
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
345
-
}
346
-
347
-
if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
348
-
int link_state;
349
-
350
-
/*
351
-
* Initiate remote wakeup if the link state is in U3 when
352
-
* operating in SS/SSP or L1/L2 when operating in HS/FS. If the
353
-
* link state is in U1/U2, no remote wakeup is needed. The Start
354
-
* Transfer command will initiate the link recovery.
355
-
*/
356
-
link_state = dwc3_gadget_get_link_state(dwc);
357
-
switch (link_state) {
358
-
case DWC3_LINK_STATE_U2:
359
-
if (dwc->gadget->speed >= USB_SPEED_SUPER)
360
-
break;
361
-
362
-
fallthrough;
363
-
case DWC3_LINK_STATE_U3:
364
-
ret = __dwc3_gadget_wakeup(dwc, false);
365
-
dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
366
-
ret);
367
-
break;
368
-
}
369
328
}
370
329
371
330
/*
+3
-9
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
+3
-9
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
···
2251
2251
{
2252
2252
u32 max_speed;
2253
2253
void *buf;
2254
-
int val;
2255
2254
int ret;
2256
2255
2257
2256
pdev->usb_regs = pdev->regs;
···
2260
2261
pdev->adma_regs = pdev->regs + CDNS2_ADMA_REGS_OFFSET;
2261
2262
2262
2263
/* Reset controller. */
2263
-
set_reg_bit_8(&pdev->usb_regs->cpuctrl, CPUCTRL_SW_RST);
2264
-
2265
-
ret = readl_poll_timeout_atomic(&pdev->usb_regs->cpuctrl, val,
2266
-
!(val & CPUCTRL_SW_RST), 1, 10000);
2267
-
if (ret) {
2268
-
dev_err(pdev->dev, "Error: reset controller timeout\n");
2269
-
return -EINVAL;
2270
-
}
2264
+
writeb(CPUCTRL_SW_RST | CPUCTRL_UPCLK | CPUCTRL_WUEN,
2265
+
&pdev->usb_regs->cpuctrl);
2266
+
usleep_range(5, 10);
2271
2267
2272
2268
usb_initialize_gadget(pdev->dev, &pdev->gadget, NULL);
2273
2269
+9
drivers/usb/gadget/udc/cdns2/cdns2-gadget.h
+9
drivers/usb/gadget/udc/cdns2/cdns2-gadget.h
···
292
292
#define SPEEDCTRL_HSDISABLE BIT(7)
293
293
294
294
/* CPUCTRL- bitmasks. */
295
+
/* UP clock enable */
296
+
#define CPUCTRL_UPCLK BIT(0)
295
297
/* Controller reset bit. */
296
298
#define CPUCTRL_SW_RST BIT(1)
299
+
/**
300
+
* If the wuen bit is ‘1’, the upclken is automatically set to ‘1’ after
301
+
* detecting rising edge of wuintereq interrupt. If the wuen bit is ‘0’,
302
+
* the wuintereq interrupt is ignored.
303
+
*/
304
+
#define CPUCTRL_WUEN BIT(7)
305
+
297
306
298
307
/**
299
308
* struct cdns2_adma_regs - ADMA controller registers.
+41
-39
drivers/usb/typec/ucsi/ucsi.c
+41
-39
drivers/usb/typec/ucsi/ucsi.c
···
965
965
966
966
static int ucsi_register_cable(struct ucsi_connector *con)
967
967
{
968
+
struct ucsi_cable_property cable_prop;
968
969
struct typec_cable *cable;
969
970
struct typec_cable_desc desc = {};
971
+
u64 command;
972
+
int ret;
970
973
971
-
switch (UCSI_CABLE_PROP_FLAG_PLUG_TYPE(con->cable_prop.flags)) {
974
+
command = UCSI_GET_CABLE_PROPERTY | UCSI_CONNECTOR_NUMBER(con->num);
975
+
ret = ucsi_send_command(con->ucsi, command, &cable_prop, sizeof(cable_prop));
976
+
if (ret < 0) {
977
+
dev_err(con->ucsi->dev, "GET_CABLE_PROPERTY failed (%d)\n", ret);
978
+
return ret;
979
+
}
980
+
981
+
switch (UCSI_CABLE_PROP_FLAG_PLUG_TYPE(cable_prop.flags)) {
972
982
case UCSI_CABLE_PROPERTY_PLUG_TYPE_A:
973
983
desc.type = USB_PLUG_TYPE_A;
974
984
break;
···
994
984
}
995
985
996
986
desc.identity = &con->cable_identity;
997
-
desc.active = !!(UCSI_CABLE_PROP_FLAG_ACTIVE_CABLE &
998
-
con->cable_prop.flags);
999
-
desc.pd_revision = UCSI_CABLE_PROP_FLAG_PD_MAJOR_REV_AS_BCD(
1000
-
con->cable_prop.flags);
987
+
desc.active = !!(UCSI_CABLE_PROP_FLAG_ACTIVE_CABLE & cable_prop.flags);
988
+
989
+
if (con->ucsi->version >= UCSI_VERSION_2_1)
990
+
desc.pd_revision = UCSI_CABLE_PROP_FLAG_PD_MAJOR_REV_AS_BCD(cable_prop.flags);
1001
991
1002
992
cable = typec_register_cable(con->port, &desc);
1003
993
if (IS_ERR(cable)) {
···
1022
1012
con->cable = NULL;
1023
1013
}
1024
1014
1015
+
static int ucsi_check_connector_capability(struct ucsi_connector *con)
1016
+
{
1017
+
u64 command;
1018
+
int ret;
1019
+
1020
+
if (!con->partner || con->ucsi->version < UCSI_VERSION_2_1)
1021
+
return 0;
1022
+
1023
+
command = UCSI_GET_CONNECTOR_CAPABILITY | UCSI_CONNECTOR_NUMBER(con->num);
1024
+
ret = ucsi_send_command(con->ucsi, command, &con->cap, sizeof(con->cap));
1025
+
if (ret < 0) {
1026
+
dev_err(con->ucsi->dev, "GET_CONNECTOR_CAPABILITY failed (%d)\n", ret);
1027
+
return ret;
1028
+
}
1029
+
1030
+
typec_partner_set_pd_revision(con->partner,
1031
+
UCSI_CONCAP_FLAG_PARTNER_PD_MAJOR_REV_AS_BCD(con->cap.flags));
1032
+
1033
+
return ret;
1034
+
}
1035
+
1025
1036
static void ucsi_pwr_opmode_change(struct ucsi_connector *con)
1026
1037
{
1027
1038
switch (UCSI_CONSTAT_PWR_OPMODE(con->status.flags)) {
···
1052
1021
ucsi_partner_task(con, ucsi_get_src_pdos, 30, 0);
1053
1022
ucsi_partner_task(con, ucsi_check_altmodes, 30, HZ);
1054
1023
ucsi_partner_task(con, ucsi_register_partner_pdos, 1, HZ);
1024
+
ucsi_partner_task(con, ucsi_check_connector_capability, 1, HZ);
1055
1025
break;
1056
1026
case UCSI_CONSTAT_PWR_OPMODE_TYPEC1_5:
1057
1027
con->rdo = 0;
···
1096
1064
1097
1065
desc.identity = &con->partner_identity;
1098
1066
desc.usb_pd = pwr_opmode == UCSI_CONSTAT_PWR_OPMODE_PD;
1099
-
desc.pd_revision = UCSI_CONCAP_FLAG_PARTNER_PD_MAJOR_REV_AS_BCD(con->cap.flags);
1100
1067
1101
1068
partner = typec_register_partner(con->port, &desc);
1102
1069
if (IS_ERR(partner)) {
···
1172
1141
con->num, u_role);
1173
1142
}
1174
1143
1175
-
static int ucsi_check_connector_capability(struct ucsi_connector *con)
1176
-
{
1177
-
u64 command;
1178
-
int ret;
1179
-
1180
-
if (!con->partner || con->ucsi->version < UCSI_VERSION_2_0)
1181
-
return 0;
1182
-
1183
-
command = UCSI_GET_CONNECTOR_CAPABILITY | UCSI_CONNECTOR_NUMBER(con->num);
1184
-
ret = ucsi_send_command(con->ucsi, command, &con->cap, sizeof(con->cap));
1185
-
if (ret < 0) {
1186
-
dev_err(con->ucsi->dev, "GET_CONNECTOR_CAPABILITY failed (%d)\n", ret);
1187
-
return ret;
1188
-
}
1189
-
1190
-
typec_partner_set_pd_revision(con->partner,
1191
-
UCSI_CONCAP_FLAG_PARTNER_PD_MAJOR_REV_AS_BCD(con->cap.flags));
1192
-
1193
-
return ret;
1194
-
}
1195
-
1196
1144
static int ucsi_check_connection(struct ucsi_connector *con)
1197
1145
{
1198
1146
u8 prev_flags = con->status.flags;
···
1203
1193
1204
1194
static int ucsi_check_cable(struct ucsi_connector *con)
1205
1195
{
1206
-
u64 command;
1207
1196
int ret, num_plug_am;
1208
1197
1209
1198
if (con->cable)
1210
1199
return 0;
1211
-
1212
-
command = UCSI_GET_CABLE_PROPERTY | UCSI_CONNECTOR_NUMBER(con->num);
1213
-
ret = ucsi_send_command(con->ucsi, command, &con->cable_prop,
1214
-
sizeof(con->cable_prop));
1215
-
if (ret < 0) {
1216
-
dev_err(con->ucsi->dev, "GET_CABLE_PROPERTY failed (%d)\n",
1217
-
ret);
1218
-
return ret;
1219
-
}
1220
1200
1221
1201
ret = ucsi_register_cable(con);
1222
1202
if (ret < 0)
···
1283
1283
if (con->status.flags & UCSI_CONSTAT_CONNECTED) {
1284
1284
ucsi_register_partner(con);
1285
1285
ucsi_partner_task(con, ucsi_check_connection, 1, HZ);
1286
-
ucsi_partner_task(con, ucsi_check_connector_capability, 1, HZ);
1287
1286
if (con->ucsi->cap.features & UCSI_CAP_GET_PD_MESSAGE)
1288
1287
ucsi_partner_task(con, ucsi_get_partner_identity, 1, HZ);
1289
1288
if (con->ucsi->cap.features & UCSI_CAP_CABLE_DETAILS)
1290
1289
ucsi_partner_task(con, ucsi_check_cable, 1, HZ);
1291
1290
1292
1291
if (UCSI_CONSTAT_PWR_OPMODE(con->status.flags) ==
1293
-
UCSI_CONSTAT_PWR_OPMODE_PD)
1292
+
UCSI_CONSTAT_PWR_OPMODE_PD) {
1294
1293
ucsi_partner_task(con, ucsi_register_partner_pdos, 1, HZ);
1294
+
ucsi_partner_task(con, ucsi_check_connector_capability, 1, HZ);
1295
+
}
1295
1296
} else {
1296
1297
ucsi_unregister_partner(con);
1297
1298
}
···
1707
1706
ucsi_register_device_pdos(con);
1708
1707
ucsi_get_src_pdos(con);
1709
1708
ucsi_check_altmodes(con);
1709
+
ucsi_check_connector_capability(con);
1710
1710
}
1711
1711
1712
1712
trace_ucsi_register_port(con->num, &con->status);
-1
drivers/usb/typec/ucsi/ucsi.h
-1
drivers/usb/typec/ucsi/ucsi.h
+12
-12
fs/bcachefs/alloc_background.c
+12
-12
fs/bcachefs/alloc_background.c
···
1968
1968
break;
1969
1969
}
1970
1970
1971
-
bch2_write_ref_put(c, BCH_WRITE_REF_discard_fast);
1972
1971
percpu_ref_put(&ca->io_ref);
1972
+
bch2_write_ref_put(c, BCH_WRITE_REF_discard_fast);
1973
1973
}
1974
1974
1975
1975
static void bch2_discard_one_bucket_fast(struct bch_dev *ca, u64 bucket)
···
1979
1979
if (discard_in_flight_add(ca, bucket, false))
1980
1980
return;
1981
1981
1982
-
if (!bch2_dev_get_ioref(c, ca->dev_idx, WRITE))
1982
+
if (!bch2_write_ref_tryget(c, BCH_WRITE_REF_discard_fast))
1983
1983
return;
1984
1984
1985
-
if (!bch2_write_ref_tryget(c, BCH_WRITE_REF_discard_fast))
1986
-
goto put_ioref;
1985
+
if (!bch2_dev_get_ioref(c, ca->dev_idx, WRITE))
1986
+
goto put_ref;
1987
1987
1988
1988
if (queue_work(c->write_ref_wq, &ca->discard_fast_work))
1989
1989
return;
1990
1990
1991
-
bch2_write_ref_put(c, BCH_WRITE_REF_discard_fast);
1992
-
put_ioref:
1993
1991
percpu_ref_put(&ca->io_ref);
1992
+
put_ref:
1993
+
bch2_write_ref_put(c, BCH_WRITE_REF_discard_fast);
1994
1994
}
1995
1995
1996
1996
static int invalidate_one_bucket(struct btree_trans *trans,
···
2132
2132
bch2_trans_iter_exit(trans, &iter);
2133
2133
err:
2134
2134
bch2_trans_put(trans);
2135
-
bch2_write_ref_put(c, BCH_WRITE_REF_invalidate);
2136
2135
percpu_ref_put(&ca->io_ref);
2136
+
bch2_write_ref_put(c, BCH_WRITE_REF_invalidate);
2137
2137
}
2138
2138
2139
2139
void bch2_dev_do_invalidates(struct bch_dev *ca)
2140
2140
{
2141
2141
struct bch_fs *c = ca->fs;
2142
2142
2143
-
if (!bch2_dev_get_ioref(c, ca->dev_idx, WRITE))
2143
+
if (!bch2_write_ref_tryget(c, BCH_WRITE_REF_invalidate))
2144
2144
return;
2145
2145
2146
-
if (!bch2_write_ref_tryget(c, BCH_WRITE_REF_invalidate))
2147
-
goto put_ioref;
2146
+
if (!bch2_dev_get_ioref(c, ca->dev_idx, WRITE))
2147
+
goto put_ref;
2148
2148
2149
2149
if (queue_work(c->write_ref_wq, &ca->invalidate_work))
2150
2150
return;
2151
2151
2152
-
bch2_write_ref_put(c, BCH_WRITE_REF_invalidate);
2153
-
put_ioref:
2154
2152
percpu_ref_put(&ca->io_ref);
2153
+
put_ref:
2154
+
bch2_write_ref_put(c, BCH_WRITE_REF_invalidate);
2155
2155
}
2156
2156
2157
2157
void bch2_do_invalidates(struct bch_fs *c)
+2
fs/bcachefs/btree_journal_iter.c
+2
fs/bcachefs/btree_journal_iter.c
+8
-7
fs/bcachefs/buckets.c
+8
-7
fs/bcachefs/buckets.c
···
100
100
101
101
struct bch_dev *ca = bch2_dev_tryget(c, p.ptr.dev);
102
102
if (!ca) {
103
-
if (fsck_err(trans, ptr_to_invalid_device,
104
-
"pointer to missing device %u\n"
105
-
"while marking %s",
106
-
p.ptr.dev,
107
-
(printbuf_reset(&buf),
108
-
bch2_bkey_val_to_text(&buf, c, k), buf.buf)))
103
+
if (fsck_err_on(p.ptr.dev != BCH_SB_MEMBER_INVALID,
104
+
trans, ptr_to_invalid_device,
105
+
"pointer to missing device %u\n"
106
+
"while marking %s",
107
+
p.ptr.dev,
108
+
(printbuf_reset(&buf),
109
+
bch2_bkey_val_to_text(&buf, c, k), buf.buf)))
109
110
*do_update = true;
110
111
return 0;
111
112
}
···
563
562
struct bch_fs *c = trans->c;
564
563
struct bch_dev *ca = bch2_dev_tryget(c, p.ptr.dev);
565
564
if (unlikely(!ca)) {
566
-
if (insert)
565
+
if (insert && p.ptr.dev != BCH_SB_MEMBER_INVALID)
567
566
ret = -EIO;
568
567
goto err;
569
568
}
+3
-1
fs/bcachefs/ec.h
+3
-1
fs/bcachefs/ec.h
···
97
97
const struct bch_extent_ptr *data_ptr,
98
98
unsigned sectors)
99
99
{
100
-
return data_ptr->dev == stripe_ptr->dev &&
100
+
return (data_ptr->dev == stripe_ptr->dev ||
101
+
data_ptr->dev == BCH_SB_MEMBER_INVALID ||
102
+
stripe_ptr->dev == BCH_SB_MEMBER_INVALID) &&
101
103
data_ptr->gen == stripe_ptr->gen &&
102
104
data_ptr->offset >= stripe_ptr->offset &&
103
105
data_ptr->offset < stripe_ptr->offset + sectors;
+10
-16
fs/bcachefs/extents.c
+10
-16
fs/bcachefs/extents.c
···
781
781
/*
782
782
* Returns pointer to the next entry after the one being dropped:
783
783
*/
784
-
union bch_extent_entry *bch2_bkey_drop_ptr_noerror(struct bkey_s k,
785
-
struct bch_extent_ptr *ptr)
784
+
void bch2_bkey_drop_ptr_noerror(struct bkey_s k, struct bch_extent_ptr *ptr)
786
785
{
787
786
struct bkey_ptrs ptrs = bch2_bkey_ptrs(k);
788
787
union bch_extent_entry *entry = to_entry(ptr), *next;
789
-
union bch_extent_entry *ret = entry;
790
788
bool drop_crc = true;
789
+
790
+
if (k.k->type == KEY_TYPE_stripe) {
791
+
ptr->dev = BCH_SB_MEMBER_INVALID;
792
+
return;
793
+
}
791
794
792
795
EBUG_ON(ptr < &ptrs.start->ptr ||
793
796
ptr >= &ptrs.end->ptr);
···
814
811
break;
815
812
816
813
if ((extent_entry_is_crc(entry) && drop_crc) ||
817
-
extent_entry_is_stripe_ptr(entry)) {
818
-
ret = (void *) ret - extent_entry_bytes(entry);
814
+
extent_entry_is_stripe_ptr(entry))
819
815
extent_entry_drop(k, entry);
820
-
}
821
816
}
822
-
823
-
return ret;
824
817
}
825
818
826
-
union bch_extent_entry *bch2_bkey_drop_ptr(struct bkey_s k,
827
-
struct bch_extent_ptr *ptr)
819
+
void bch2_bkey_drop_ptr(struct bkey_s k, struct bch_extent_ptr *ptr)
828
820
{
829
821
bool have_dirty = bch2_bkey_dirty_devs(k.s_c).nr;
830
-
union bch_extent_entry *ret =
831
-
bch2_bkey_drop_ptr_noerror(k, ptr);
822
+
823
+
bch2_bkey_drop_ptr_noerror(k, ptr);
832
824
833
825
/*
834
826
* If we deleted all the dirty pointers and there's still cached
···
835
837
!bch2_bkey_dirty_devs(k.s_c).nr) {
836
838
k.k->type = KEY_TYPE_error;
837
839
set_bkey_val_u64s(k.k, 0);
838
-
ret = NULL;
839
840
} else if (!bch2_bkey_nr_ptrs(k.s_c)) {
840
841
k.k->type = KEY_TYPE_deleted;
841
842
set_bkey_val_u64s(k.k, 0);
842
-
ret = NULL;
843
843
}
844
-
845
-
return ret;
846
844
}
847
845
848
846
void bch2_bkey_drop_device(struct bkey_s k, unsigned dev)
+9
-14
fs/bcachefs/extents.h
+9
-14
fs/bcachefs/extents.h
···
649
649
650
650
void bch2_extent_ptr_decoded_append(struct bkey_i *,
651
651
struct extent_ptr_decoded *);
652
-
union bch_extent_entry *bch2_bkey_drop_ptr_noerror(struct bkey_s,
653
-
struct bch_extent_ptr *);
654
-
union bch_extent_entry *bch2_bkey_drop_ptr(struct bkey_s,
655
-
struct bch_extent_ptr *);
652
+
void bch2_bkey_drop_ptr_noerror(struct bkey_s, struct bch_extent_ptr *);
653
+
void bch2_bkey_drop_ptr(struct bkey_s, struct bch_extent_ptr *);
656
654
657
655
#define bch2_bkey_drop_ptrs(_k, _ptr, _cond) \
658
656
do { \
659
-
struct bkey_ptrs _ptrs = bch2_bkey_ptrs(_k); \
657
+
__label__ _again; \
658
+
struct bkey_ptrs _ptrs; \
659
+
_again: \
660
+
_ptrs = bch2_bkey_ptrs(_k); \
660
661
\
661
-
struct bch_extent_ptr *_ptr = &_ptrs.start->ptr; \
662
-
\
663
-
while ((_ptr = bkey_ptr_next(_ptrs, _ptr))) { \
662
+
bkey_for_each_ptr(_ptrs, _ptr) \
664
663
if (_cond) { \
665
-
_ptr = (void *) bch2_bkey_drop_ptr(_k, _ptr); \
666
-
_ptrs = bch2_bkey_ptrs(_k); \
667
-
continue; \
664
+
bch2_bkey_drop_ptr(_k, _ptr); \
665
+
goto _again; \
668
666
} \
669
-
\
670
-
(_ptr)++; \
671
-
} \
672
667
} while (0)
673
668
674
669
bool bch2_bkey_matches_ptr(struct bch_fs *, struct bkey_s_c,
+8
fs/bcachefs/fs.c
+8
fs/bcachefs/fs.c
···
177
177
return jhash_3words(inum.subvol, inum.inum >> 32, inum.inum, JHASH_INITVAL);
178
178
}
179
179
180
+
struct bch_inode_info *__bch2_inode_hash_find(struct bch_fs *c, subvol_inum inum)
181
+
{
182
+
return to_bch_ei(ilookup5_nowait(c->vfs_sb,
183
+
bch2_inode_hash(inum),
184
+
bch2_iget5_test,
185
+
&inum));
186
+
}
187
+
180
188
static struct bch_inode_info *bch2_inode_insert(struct bch_fs *c, struct bch_inode_info *inode)
181
189
{
182
190
subvol_inum inum = inode_inum(inode);
+7
fs/bcachefs/fs.h
+7
fs/bcachefs/fs.h
···
56
56
};
57
57
}
58
58
59
+
struct bch_inode_info *__bch2_inode_hash_find(struct bch_fs *, subvol_inum);
60
+
59
61
/*
60
62
* Set if we've gotten a btree error for this inode, and thus the vfs inode and
61
63
* btree inode may be inconsistent:
···
195
193
#else
196
194
197
195
#define bch2_inode_update_after_write(_trans, _inode, _inode_u, _fields) ({ do {} while (0); })
196
+
197
+
static inline struct bch_inode_info *__bch2_inode_hash_find(struct bch_fs *c, subvol_inum inum)
198
+
{
199
+
return NULL;
200
+
}
198
201
199
202
static inline void bch2_evict_subvolume_inodes(struct bch_fs *c,
200
203
snapshot_id_list *s) {}
+18
fs/bcachefs/fsck.c
+18
fs/bcachefs/fsck.c
···
8
8
#include "darray.h"
9
9
#include "dirent.h"
10
10
#include "error.h"
11
+
#include "fs.h"
11
12
#include "fs-common.h"
12
13
#include "fsck.h"
13
14
#include "inode.h"
···
963
962
return ret;
964
963
}
965
964
965
+
static bool bch2_inode_open(struct bch_fs *c, struct bpos p)
966
+
{
967
+
subvol_inum inum = {
968
+
.subvol = snapshot_t(c, p.snapshot)->subvol,
969
+
.inum = p.offset,
970
+
};
971
+
972
+
/* snapshot tree corruption, can't safely delete */
973
+
if (!inum.subvol) {
974
+
bch_err_ratelimited(c, "%s(): snapshot %u has no subvol", __func__, p.snapshot);
975
+
return true;
976
+
}
977
+
978
+
return __bch2_inode_hash_find(c, inum) != NULL;
979
+
}
980
+
966
981
static int check_inode(struct btree_trans *trans,
967
982
struct btree_iter *iter,
968
983
struct bkey_s_c k,
···
1057
1040
}
1058
1041
1059
1042
if (u.bi_flags & BCH_INODE_unlinked &&
1043
+
!bch2_inode_open(c, k.k->p) &&
1060
1044
(!c->sb.clean ||
1061
1045
fsck_err(trans, inode_unlinked_but_clean,
1062
1046
"filesystem marked clean, but inode %llu unlinked",
+1
-1
fs/bcachefs/replicas.c
+1
-1
fs/bcachefs/replicas.c
+1
-1
fs/bcachefs/sysfs.c
+1
-1
fs/bcachefs/sysfs.c
···
461
461
462
462
sc.gfp_mask = GFP_KERNEL;
463
463
sc.nr_to_scan = strtoul_or_return(buf);
464
-
c->btree_key_cache.shrink->scan_objects(c->btree_cache.shrink, &sc);
464
+
c->btree_key_cache.shrink->scan_objects(c->btree_key_cache.shrink, &sc);
465
465
}
466
466
467
467
if (attr == &sysfs_trigger_gc)
+3
-3
fs/libfs.c
+3
-3
fs/libfs.c
···
2117
2117
}
2118
2118
EXPORT_SYMBOL(simple_inode_init_ts);
2119
2119
2120
-
static inline struct dentry *get_stashed_dentry(struct dentry *stashed)
2120
+
static inline struct dentry *get_stashed_dentry(struct dentry **stashed)
2121
2121
{
2122
2122
struct dentry *dentry;
2123
2123
2124
2124
guard(rcu)();
2125
-
dentry = READ_ONCE(stashed);
2125
+
dentry = rcu_dereference(*stashed);
2126
2126
if (!dentry)
2127
2127
return NULL;
2128
2128
if (!lockref_get_not_dead(&dentry->d_lockref))
···
2219
2219
const struct stashed_operations *sops = mnt->mnt_sb->s_fs_info;
2220
2220
2221
2221
/* See if dentry can be reused. */
2222
-
path->dentry = get_stashed_dentry(*stashed);
2222
+
path->dentry = get_stashed_dentry(stashed);
2223
2223
if (path->dentry) {
2224
2224
sops->put_data(data);
2225
2225
goto out_path;
+1
-1
fs/netfs/io.c
+1
-1
fs/netfs/io.c
···
270
270
if (count == remaining)
271
271
return;
272
272
273
-
_debug("R=%08x[%u] ITER RESUB-MISMATCH %zx != %zx-%zx-%llx %x\n",
273
+
_debug("R=%08x[%u] ITER RESUB-MISMATCH %zx != %zx-%zx-%llx %x",
274
274
rreq->debug_id, subreq->debug_index,
275
275
iov_iter_count(&subreq->io_iter), subreq->transferred,
276
276
subreq->len, rreq->i_size,
+46
-8
fs/smb/client/cifssmb.c
+46
-8
fs/smb/client/cifssmb.c
···
1261
1261
return rc;
1262
1262
}
1263
1263
1264
+
static void cifs_readv_worker(struct work_struct *work)
1265
+
{
1266
+
struct cifs_io_subrequest *rdata =
1267
+
container_of(work, struct cifs_io_subrequest, subreq.work);
1268
+
1269
+
netfs_subreq_terminated(&rdata->subreq,
1270
+
(rdata->result == 0 || rdata->result == -EAGAIN) ?
1271
+
rdata->got_bytes : rdata->result, true);
1272
+
}
1273
+
1264
1274
static void
1265
1275
cifs_readv_callback(struct mid_q_entry *mid)
1266
1276
{
1267
1277
struct cifs_io_subrequest *rdata = mid->callback_data;
1278
+
struct netfs_inode *ictx = netfs_inode(rdata->rreq->inode);
1268
1279
struct cifs_tcon *tcon = tlink_tcon(rdata->req->cfile->tlink);
1269
1280
struct TCP_Server_Info *server = tcon->ses->server;
1270
1281
struct smb_rqst rqst = { .rq_iov = rdata->iov,
1271
1282
.rq_nvec = 2,
1272
1283
.rq_iter = rdata->subreq.io_iter };
1273
-
struct cifs_credits credits = { .value = 1, .instance = 0 };
1284
+
struct cifs_credits credits = {
1285
+
.value = 1,
1286
+
.instance = 0,
1287
+
.rreq_debug_id = rdata->rreq->debug_id,
1288
+
.rreq_debug_index = rdata->subreq.debug_index,
1289
+
};
1274
1290
1275
1291
cifs_dbg(FYI, "%s: mid=%llu state=%d result=%d bytes=%zu\n",
1276
1292
__func__, mid->mid, mid->mid_state, rdata->result,
···
1298
1282
if (server->sign) {
1299
1283
int rc = 0;
1300
1284
1285
+
iov_iter_truncate(&rqst.rq_iter, rdata->got_bytes);
1301
1286
rc = cifs_verify_signature(&rqst, server,
1302
1287
mid->sequence_number);
1303
1288
if (rc)
···
1323
1306
rdata->result = -EIO;
1324
1307
}
1325
1308
1326
-
if (rdata->result == 0 || rdata->result == -EAGAIN)
1327
-
iov_iter_advance(&rdata->subreq.io_iter, rdata->got_bytes);
1309
+
if (rdata->result == -ENODATA) {
1310
+
__set_bit(NETFS_SREQ_HIT_EOF, &rdata->subreq.flags);
1311
+
rdata->result = 0;
1312
+
} else {
1313
+
if (rdata->got_bytes < rdata->actual_len &&
1314
+
rdata->subreq.start + rdata->subreq.transferred + rdata->got_bytes ==
1315
+
ictx->remote_i_size) {
1316
+
__set_bit(NETFS_SREQ_HIT_EOF, &rdata->subreq.flags);
1317
+
rdata->result = 0;
1318
+
}
1319
+
}
1320
+
1328
1321
rdata->credits.value = 0;
1329
-
netfs_subreq_terminated(&rdata->subreq,
1330
-
(rdata->result == 0 || rdata->result == -EAGAIN) ?
1331
-
rdata->got_bytes : rdata->result,
1332
-
false);
1322
+
INIT_WORK(&rdata->subreq.work, cifs_readv_worker);
1323
+
queue_work(cifsiod_wq, &rdata->subreq.work);
1333
1324
release_mid(mid);
1334
1325
add_credits(server, &credits, 0);
1335
1326
}
···
1644
1619
cifs_writev_callback(struct mid_q_entry *mid)
1645
1620
{
1646
1621
struct cifs_io_subrequest *wdata = mid->callback_data;
1622
+
struct TCP_Server_Info *server = wdata->server;
1647
1623
struct cifs_tcon *tcon = tlink_tcon(wdata->req->cfile->tlink);
1648
1624
WRITE_RSP *smb = (WRITE_RSP *)mid->resp_buf;
1649
-
struct cifs_credits credits = { .value = 1, .instance = 0 };
1625
+
struct cifs_credits credits = {
1626
+
.value = 1,
1627
+
.instance = 0,
1628
+
.rreq_debug_id = wdata->rreq->debug_id,
1629
+
.rreq_debug_index = wdata->subreq.debug_index,
1630
+
};
1650
1631
ssize_t result;
1651
1632
size_t written;
1652
1633
···
1688
1657
break;
1689
1658
}
1690
1659
1660
+
trace_smb3_rw_credits(credits.rreq_debug_id, credits.rreq_debug_index,
1661
+
wdata->credits.value,
1662
+
server->credits, server->in_flight,
1663
+
0, cifs_trace_rw_credits_write_response_clear);
1691
1664
wdata->credits.value = 0;
1692
1665
cifs_write_subrequest_terminated(wdata, result, true);
1693
1666
release_mid(mid);
1667
+
trace_smb3_rw_credits(credits.rreq_debug_id, credits.rreq_debug_index, 0,
1668
+
server->credits, server->in_flight,
1669
+
credits.value, cifs_trace_rw_credits_write_response_add);
1694
1670
add_credits(tcon->ses->server, &credits, 0);
1695
1671
}
1696
1672
+13
-1
fs/smb/client/connect.c
+13
-1
fs/smb/client/connect.c
···
657
657
server_unresponsive(struct TCP_Server_Info *server)
658
658
{
659
659
/*
660
+
* If we're in the process of mounting a share or reconnecting a session
661
+
* and the server abruptly shut down (e.g. socket wasn't closed, packet
662
+
* had been ACK'ed but no SMB response), don't wait longer than 20s to
663
+
* negotiate protocol.
664
+
*/
665
+
spin_lock(&server->srv_lock);
666
+
if (server->tcpStatus == CifsInNegotiate &&
667
+
time_after(jiffies, server->lstrp + 20 * HZ)) {
668
+
spin_unlock(&server->srv_lock);
669
+
cifs_reconnect(server, false);
670
+
return true;
671
+
}
672
+
/*
660
673
* We need to wait 3 echo intervals to make sure we handle such
661
674
* situations right:
662
675
* 1s client sends a normal SMB request
···
680
667
* 65s kernel_recvmsg times out, and we see that we haven't gotten
681
668
* a response in >60s.
682
669
*/
683
-
spin_lock(&server->srv_lock);
684
670
if ((server->tcpStatus == CifsGood ||
685
671
server->tcpStatus == CifsNeedNegotiate) &&
686
672
(!server->ops->can_echo || server->ops->can_echo(server)) &&
+2
fs/smb/client/inode.c
+2
fs/smb/client/inode.c
+3
fs/smb/client/smb2inode.c
+3
fs/smb/client/smb2inode.c
···
1106
1106
co, DELETE, SMB2_OP_RENAME, cfile, source_dentry);
1107
1107
if (rc == -EINVAL) {
1108
1108
cifs_dbg(FYI, "invalid lease key, resending request without lease");
1109
+
cifs_get_writable_path(tcon, from_name,
1110
+
FIND_WR_WITH_DELETE, &cfile);
1109
1111
rc = smb2_set_path_attr(xid, tcon, from_name, to_name, cifs_sb,
1110
1112
co, DELETE, SMB2_OP_RENAME, cfile, NULL);
1111
1113
}
···
1151
1149
cfile, NULL, NULL, dentry);
1152
1150
if (rc == -EINVAL) {
1153
1151
cifs_dbg(FYI, "invalid lease key, resending request without lease");
1152
+
cifs_get_writable_path(tcon, full_path, FIND_WR_ANY, &cfile);
1154
1153
rc = smb2_compound_op(xid, tcon, cifs_sb,
1155
1154
full_path, &oparms, &in_iov,
1156
1155
&(int){SMB2_OP_SET_EOF}, 1,
+5
-3
fs/smb/client/smb2ops.c
+5
-3
fs/smb/client/smb2ops.c
···
316
316
cifs_trace_rw_credits_no_adjust_up);
317
317
trace_smb3_too_many_credits(server->CurrentMid,
318
318
server->conn_id, server->hostname, 0, credits->value - new_val, 0);
319
-
cifs_server_dbg(VFS, "request has less credits (%d) than required (%d)",
319
+
cifs_server_dbg(VFS, "R=%x[%x] request has less credits (%d) than required (%d)",
320
+
subreq->rreq->debug_id, subreq->subreq.debug_index,
320
321
credits->value, new_val);
321
322
322
323
return -EOPNOTSUPP;
···
339
338
trace_smb3_reconnect_detected(server->CurrentMid,
340
339
server->conn_id, server->hostname, scredits,
341
340
credits->value - new_val, in_flight);
342
-
cifs_server_dbg(VFS, "trying to return %d credits to old session\n",
343
-
credits->value - new_val);
341
+
cifs_server_dbg(VFS, "R=%x[%x] trying to return %d credits to old session\n",
342
+
subreq->rreq->debug_id, subreq->subreq.debug_index,
343
+
credits->value - new_val);
344
344
return -EAGAIN;
345
345
}
346
346
+1
include/kunit/test.h
+1
include/kunit/test.h
+4
-2
include/linux/context_tracking.h
+4
-2
include/linux/context_tracking.h
···
80
80
return context_tracking_enabled_this_cpu();
81
81
}
82
82
83
-
static __always_inline void context_tracking_guest_exit(void)
83
+
static __always_inline bool context_tracking_guest_exit(void)
84
84
{
85
85
if (context_tracking_enabled())
86
86
__ct_user_exit(CONTEXT_GUEST);
87
+
88
+
return context_tracking_enabled_this_cpu();
87
89
}
88
90
89
91
#define CT_WARN_ON(cond) WARN_ON(context_tracking_enabled() && (cond))
···
100
98
static inline int ct_state(void) { return -1; }
101
99
static inline int __ct_state(void) { return -1; }
102
100
static __always_inline bool context_tracking_guest_enter(void) { return false; }
103
-
static __always_inline void context_tracking_guest_exit(void) { }
101
+
static __always_inline bool context_tracking_guest_exit(void) { return false; }
104
102
#define CT_WARN_ON(cond) do { } while (0)
105
103
#endif /* !CONFIG_CONTEXT_TRACKING_USER */
106
104
+9
-1
include/linux/kvm_host.h
+9
-1
include/linux/kvm_host.h
···
485
485
*/
486
486
static __always_inline void guest_context_exit_irqoff(void)
487
487
{
488
-
context_tracking_guest_exit();
488
+
/*
489
+
* Guest mode is treated as a quiescent state, see
490
+
* guest_context_enter_irqoff() for more details.
491
+
*/
492
+
if (!context_tracking_guest_exit()) {
493
+
instrumentation_begin();
494
+
rcu_virt_note_context_switch();
495
+
instrumentation_end();
496
+
}
489
497
}
490
498
491
499
/*
+9
-1
include/linux/mlx5/mlx5_ifc.h
+9
-1
include/linux/mlx5/mlx5_ifc.h
···
1113
1113
1114
1114
u8 max_tsar_bw_share[0x20];
1115
1115
1116
-
u8 reserved_at_100[0x20];
1116
+
u8 nic_element_type[0x10];
1117
+
u8 nic_tsar_type[0x10];
1117
1118
1118
1119
u8 reserved_at_120[0x3];
1119
1120
u8 log_meter_aso_granularity[0x5];
···
4077
4076
ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
4078
4077
ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
4079
4078
ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
4079
+
ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4,
4080
4080
};
4081
4081
4082
4082
struct mlx5_ifc_scheduling_context_bits {
···
4785
4783
TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4786
4784
TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4787
4785
TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4786
+
};
4787
+
4788
+
enum {
4789
+
TSAR_TYPE_CAP_MASK_DWRR = 1 << 0,
4790
+
TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1,
4791
+
TSAR_TYPE_CAP_MASK_ETS = 1 << 2,
4788
4792
};
4789
4793
4790
4794
struct mlx5_ifc_tsar_element_bits {
+3
include/linux/pci-pwrctl.h
+3
include/linux/pci-pwrctl.h
···
7
7
#define __PCI_PWRCTL_H__
8
8
9
9
#include <linux/notifier.h>
10
+
#include <linux/workqueue.h>
10
11
11
12
struct device;
12
13
struct device_link;
···
42
41
/* Private: don't use. */
43
42
struct notifier_block nb;
44
43
struct device_link *link;
44
+
struct work_struct work;
45
45
};
46
46
47
+
void pci_pwrctl_init(struct pci_pwrctl *pwrctl, struct device *dev);
47
48
int pci_pwrctl_device_set_ready(struct pci_pwrctl *pwrctl);
48
49
void pci_pwrctl_device_unset_ready(struct pci_pwrctl *pwrctl);
49
50
int devm_pci_pwrctl_device_set_ready(struct device *dev,
+1
include/linux/platform_data/x86/asus-wmi.h
+1
include/linux/platform_data/x86/asus-wmi.h
···
62
62
#define ASUS_WMI_DEVID_KBD_BACKLIGHT 0x00050021
63
63
#define ASUS_WMI_DEVID_LIGHT_SENSOR 0x00050022 /* ?? */
64
64
#define ASUS_WMI_DEVID_LIGHTBAR 0x00050025
65
+
#define ASUS_WMI_DEVID_OOBE 0x0005002F
65
66
/* This can only be used to disable the screen, not re-enable */
66
67
#define ASUS_WMI_DEVID_SCREENPAD_POWER 0x00050031
67
68
/* Writing a brightness re-enables the screen if disabled */
+2
-1
include/linux/virtio_net.h
+2
-1
include/linux/virtio_net.h
+1
-1
include/sound/sof/topology.h
+1
-1
include/sound/sof/topology.h
+5
-1
include/uapi/drm/panthor_drm.h
+5
-1
include/uapi/drm/panthor_drm.h
···
692
692
/** @PANTHOR_GROUP_PRIORITY_MEDIUM: Medium priority group. */
693
693
PANTHOR_GROUP_PRIORITY_MEDIUM,
694
694
695
-
/** @PANTHOR_GROUP_PRIORITY_HIGH: High priority group. */
695
+
/**
696
+
* @PANTHOR_GROUP_PRIORITY_HIGH: High priority group.
697
+
*
698
+
* Requires CAP_SYS_NICE or DRM_MASTER.
699
+
*/
696
700
PANTHOR_GROUP_PRIORITY_HIGH,
697
701
};
698
702
+1
-1
include/uapi/sound/sof/abi.h
+1
-1
include/uapi/sound/sof/abi.h
+4
-2
kernel/bpf/btf.c
+4
-2
kernel/bpf/btf.c
···
823
823
const char *src = btf_str_by_offset(btf, offset);
824
824
const char *src_limit;
825
825
826
+
if (!*src)
827
+
return false;
828
+
826
829
/* set a limit on identifier length */
827
830
src_limit = src + KSYM_NAME_LEN;
828
-
src++;
829
831
while (*src && src < src_limit) {
830
832
if (!isprint(*src))
831
833
return false;
···
6285
6283
6286
6284
errout:
6287
6285
btf_verifier_env_free(env);
6288
-
if (base_btf != vmlinux_btf)
6286
+
if (!IS_ERR(base_btf) && base_btf != vmlinux_btf)
6289
6287
btf_free(base_btf);
6290
6288
if (btf) {
6291
6289
kvfree(btf->data);
+12
-6
kernel/events/core.c
+12
-6
kernel/events/core.c
···
1255
1255
* perf_event_context::mutex
1256
1256
* perf_event::child_mutex;
1257
1257
* perf_event_context::lock
1258
-
* perf_event::mmap_mutex
1259
1258
* mmap_lock
1259
+
* perf_event::mmap_mutex
1260
+
* perf_buffer::aux_mutex
1260
1261
* perf_addr_filters_head::lock
1261
1262
*
1262
1263
* cpu_hotplug_lock
···
6374
6373
event->pmu->event_unmapped(event, vma->vm_mm);
6375
6374
6376
6375
/*
6377
-
* rb->aux_mmap_count will always drop before rb->mmap_count and
6378
-
* event->mmap_count, so it is ok to use event->mmap_mutex to
6379
-
* serialize with perf_mmap here.
6376
+
* The AUX buffer is strictly a sub-buffer, serialize using aux_mutex
6377
+
* to avoid complications.
6380
6378
*/
6381
6379
if (rb_has_aux(rb) && vma->vm_pgoff == rb->aux_pgoff &&
6382
-
atomic_dec_and_mutex_lock(&rb->aux_mmap_count, &event->mmap_mutex)) {
6380
+
atomic_dec_and_mutex_lock(&rb->aux_mmap_count, &rb->aux_mutex)) {
6383
6381
/*
6384
6382
* Stop all AUX events that are writing to this buffer,
6385
6383
* so that we can free its AUX pages and corresponding PMU
···
6395
6395
rb_free_aux(rb);
6396
6396
WARN_ON_ONCE(refcount_read(&rb->aux_refcount));
6397
6397
6398
-
mutex_unlock(&event->mmap_mutex);
6398
+
mutex_unlock(&rb->aux_mutex);
6399
6399
}
6400
6400
6401
6401
if (atomic_dec_and_test(&rb->mmap_count))
···
6483
6483
struct perf_event *event = file->private_data;
6484
6484
unsigned long user_locked, user_lock_limit;
6485
6485
struct user_struct *user = current_user();
6486
+
struct mutex *aux_mutex = NULL;
6486
6487
struct perf_buffer *rb = NULL;
6487
6488
unsigned long locked, lock_limit;
6488
6489
unsigned long vma_size;
···
6531
6530
rb = event->rb;
6532
6531
if (!rb)
6533
6532
goto aux_unlock;
6533
+
6534
+
aux_mutex = &rb->aux_mutex;
6535
+
mutex_lock(aux_mutex);
6534
6536
6535
6537
aux_offset = READ_ONCE(rb->user_page->aux_offset);
6536
6538
aux_size = READ_ONCE(rb->user_page->aux_size);
···
6685
6681
atomic_dec(&rb->mmap_count);
6686
6682
}
6687
6683
aux_unlock:
6684
+
if (aux_mutex)
6685
+
mutex_unlock(aux_mutex);
6688
6686
mutex_unlock(&event->mmap_mutex);
6689
6687
6690
6688
/*
+1
kernel/events/internal.h
+1
kernel/events/internal.h
+2
kernel/events/ring_buffer.c
+2
kernel/events/ring_buffer.c
+1
-2
kernel/events/uprobes.c
+1
-2
kernel/events/uprobes.c
···
1489
1489
struct xol_area *area;
1490
1490
void *insns;
1491
1491
1492
-
area = kmalloc(sizeof(*area), GFP_KERNEL);
1492
+
area = kzalloc(sizeof(*area), GFP_KERNEL);
1493
1493
if (unlikely(!area))
1494
1494
goto out;
1495
1495
···
1499
1499
goto free_area;
1500
1500
1501
1501
area->xol_mapping.name = "[uprobes]";
1502
-
area->xol_mapping.fault = NULL;
1503
1502
area->xol_mapping.pages = area->pages;
1504
1503
area->pages[0] = alloc_page(GFP_HIGHUSER);
1505
1504
if (!area->pages[0])
+1
kernel/printk/printk.c
+1
kernel/printk/printk.c
-4
kernel/trace/trace.c
-4
kernel/trace/trace.c
+5
-5
kernel/trace/trace_osnoise.c
+5
-5
kernel/trace/trace_osnoise.c
···
228
228
return this_cpu_ptr(&per_cpu_osnoise_var);
229
229
}
230
230
231
+
/*
232
+
* Protect the interface.
233
+
*/
234
+
static struct mutex interface_lock;
235
+
231
236
#ifdef CONFIG_TIMERLAT_TRACER
232
237
/*
233
238
* Runtime information for the timer mode.
···
256
251
{
257
252
return this_cpu_ptr(&per_cpu_timerlat_var);
258
253
}
259
-
260
-
/*
261
-
* Protect the interface.
262
-
*/
263
-
static struct mutex interface_lock;
264
254
265
255
/*
266
256
* tlat_var_reset - Reset the values of the given timerlat_variables
+22
-5
mm/memory.c
+22
-5
mm/memory.c
···
2632
2632
return 0;
2633
2633
}
2634
2634
2635
-
/*
2636
-
* Variant of remap_pfn_range that does not call track_pfn_remap. The caller
2637
-
* must have pre-validated the caching bits of the pgprot_t.
2638
-
*/
2639
-
int remap_pfn_range_notrack(struct vm_area_struct *vma, unsigned long addr,
2635
+
static int remap_pfn_range_internal(struct vm_area_struct *vma, unsigned long addr,
2640
2636
unsigned long pfn, unsigned long size, pgprot_t prot)
2641
2637
{
2642
2638
pgd_t *pgd;
···
2683
2687
} while (pgd++, addr = next, addr != end);
2684
2688
2685
2689
return 0;
2690
+
}
2691
+
2692
+
/*
2693
+
* Variant of remap_pfn_range that does not call track_pfn_remap. The caller
2694
+
* must have pre-validated the caching bits of the pgprot_t.
2695
+
*/
2696
+
int remap_pfn_range_notrack(struct vm_area_struct *vma, unsigned long addr,
2697
+
unsigned long pfn, unsigned long size, pgprot_t prot)
2698
+
{
2699
+
int error = remap_pfn_range_internal(vma, addr, pfn, size, prot);
2700
+
2701
+
if (!error)
2702
+
return 0;
2703
+
2704
+
/*
2705
+
* A partial pfn range mapping is dangerous: it does not
2706
+
* maintain page reference counts, and callers may free
2707
+
* pages due to the error. So zap it early.
2708
+
*/
2709
+
zap_page_range_single(vma, addr, size, NULL);
2710
+
return error;
2686
2711
}
2687
2712
2688
2713
/**
+4
net/hsr/hsr_device.c
+4
net/hsr/hsr_device.c
···
427
427
* of SAN nodes stored in ProxyNodeTable.
428
428
*/
429
429
interlink = hsr_port_get_hsr(hsr, HSR_PT_INTERLINK);
430
+
if (!interlink)
431
+
goto done;
432
+
430
433
list_for_each_entry_rcu(node, &hsr->proxy_node_db, mac_list) {
431
434
if (hsr_addr_is_redbox(hsr, node->macaddress_A))
432
435
continue;
···
444
441
mod_timer(&hsr->announce_proxy_timer, jiffies + interval);
445
442
}
446
443
444
+
done:
447
445
rcu_read_unlock();
448
446
}
449
447
+2
-2
net/ipv4/fou_core.c
+2
-2
net/ipv4/fou_core.c
+9
-4
net/mptcp/pm_netlink.c
+9
-4
net/mptcp/pm_netlink.c
···
338
338
{
339
339
struct mptcp_pm_add_entry *entry;
340
340
struct sock *sk = (struct sock *)msk;
341
+
struct timer_list *add_timer = NULL;
341
342
342
343
spin_lock_bh(&msk->pm.lock);
343
344
entry = mptcp_lookup_anno_list_by_saddr(msk, addr);
344
-
if (entry && (!check_id || entry->addr.id == addr->id))
345
+
if (entry && (!check_id || entry->addr.id == addr->id)) {
345
346
entry->retrans_times = ADD_ADDR_RETRANS_MAX;
347
+
add_timer = &entry->add_timer;
348
+
}
349
+
if (!check_id && entry)
350
+
list_del(&entry->list);
346
351
spin_unlock_bh(&msk->pm.lock);
347
352
348
-
if (entry && (!check_id || entry->addr.id == addr->id))
349
-
sk_stop_timer_sync(sk, &entry->add_timer);
353
+
/* no lock, because sk_stop_timer_sync() is calling del_timer_sync() */
354
+
if (add_timer)
355
+
sk_stop_timer_sync(sk, add_timer);
350
356
351
357
return entry;
352
358
}
···
1450
1444
1451
1445
entry = mptcp_pm_del_add_timer(msk, addr, false);
1452
1446
if (entry) {
1453
-
list_del(&entry->list);
1454
1447
kfree(entry);
1455
1448
return true;
1456
1449
}
+6
net/netfilter/nf_flow_table_core.c
+6
net/netfilter/nf_flow_table_core.c
···
670
670
if (ret)
671
671
goto out_offload;
672
672
673
+
ret = nf_flow_register_bpf();
674
+
if (ret)
675
+
goto out_bpf;
676
+
673
677
return 0;
674
678
679
+
out_bpf:
680
+
nf_flow_table_offload_exit();
675
681
out_offload:
676
682
unregister_pernet_subsys(&nf_flow_table_net_ops);
677
683
return ret;
+1
-1
net/netfilter/nf_flow_table_inet.c
+1
-1
net/netfilter/nf_flow_table_inet.c
+42
-6
net/netfilter/nft_socket.c
+42
-6
net/netfilter/nft_socket.c
···
9
9
10
10
struct nft_socket {
11
11
enum nft_socket_keys key:8;
12
-
u8 level;
12
+
u8 level; /* cgroupv2 level to extract */
13
+
u8 level_user; /* cgroupv2 level provided by userspace */
13
14
u8 len;
14
15
union {
15
16
u8 dreg;
···
53
52
cgid = cgroup_id(cgrp);
54
53
memcpy(dest, &cgid, sizeof(u64));
55
54
return true;
55
+
}
56
+
57
+
/* process context only, uses current->nsproxy. */
58
+
static noinline int nft_socket_cgroup_subtree_level(void)
59
+
{
60
+
struct cgroup *cgrp = cgroup_get_from_path("/");
61
+
int level;
62
+
63
+
if (!cgrp)
64
+
return -ENOENT;
65
+
66
+
level = cgrp->level;
67
+
68
+
cgroup_put(cgrp);
69
+
70
+
if (WARN_ON_ONCE(level > 255))
71
+
return -ERANGE;
72
+
73
+
if (WARN_ON_ONCE(level < 0))
74
+
return -EINVAL;
75
+
76
+
return level;
56
77
}
57
78
#endif
58
79
···
133
110
*dest = READ_ONCE(sk->sk_mark);
134
111
} else {
135
112
regs->verdict.code = NFT_BREAK;
136
-
return;
113
+
goto out_put_sk;
137
114
}
138
115
break;
139
116
case NFT_SOCKET_WILDCARD:
140
117
if (!sk_fullsock(sk)) {
141
118
regs->verdict.code = NFT_BREAK;
142
-
return;
119
+
goto out_put_sk;
143
120
}
144
121
nft_socket_wildcard(pkt, regs, sk, dest);
145
122
break;
···
147
124
case NFT_SOCKET_CGROUPV2:
148
125
if (!nft_sock_get_eval_cgroupv2(dest, sk, pkt, priv->level)) {
149
126
regs->verdict.code = NFT_BREAK;
150
-
return;
127
+
goto out_put_sk;
151
128
}
152
129
break;
153
130
#endif
···
156
133
regs->verdict.code = NFT_BREAK;
157
134
}
158
135
136
+
out_put_sk:
159
137
if (sk != skb->sk)
160
138
sock_gen_put(sk);
161
139
}
···
197
173
case NFT_SOCKET_MARK:
198
174
len = sizeof(u32);
199
175
break;
200
-
#ifdef CONFIG_CGROUPS
176
+
#ifdef CONFIG_SOCK_CGROUP_DATA
201
177
case NFT_SOCKET_CGROUPV2: {
202
178
unsigned int level;
179
+
int err;
203
180
204
181
if (!tb[NFTA_SOCKET_LEVEL])
205
182
return -EINVAL;
206
183
207
184
level = ntohl(nla_get_be32(tb[NFTA_SOCKET_LEVEL]));
208
185
if (level > 255)
186
+
return -EOPNOTSUPP;
187
+
188
+
err = nft_socket_cgroup_subtree_level();
189
+
if (err < 0)
190
+
return err;
191
+
192
+
priv->level_user = level;
193
+
194
+
level += err;
195
+
/* Implies a giant cgroup tree */
196
+
if (WARN_ON_ONCE(level > 255))
209
197
return -EOPNOTSUPP;
210
198
211
199
priv->level = level;
···
244
208
if (nft_dump_register(skb, NFTA_SOCKET_DREG, priv->dreg))
245
209
return -1;
246
210
if (priv->key == NFT_SOCKET_CGROUPV2 &&
247
-
nla_put_be32(skb, NFTA_SOCKET_LEVEL, htonl(priv->level)))
211
+
nla_put_be32(skb, NFTA_SOCKET_LEVEL, htonl(priv->level_user)))
248
212
return -1;
249
213
return 0;
250
214
}
+11
sound/pci/hda/patch_conexant.c
+11
sound/pci/hda/patch_conexant.c
···
307
307
CXT_FIXUP_HEADSET_MIC,
308
308
CXT_FIXUP_HP_MIC_NO_PRESENCE,
309
309
CXT_PINCFG_SWS_JS201D,
310
+
CXT_PINCFG_TOP_SPEAKER,
310
311
};
311
312
312
313
/* for hda_fixup_thinkpad_acpi() */
···
975
974
.type = HDA_FIXUP_PINS,
976
975
.v.pins = cxt_pincfg_sws_js201d,
977
976
},
977
+
[CXT_PINCFG_TOP_SPEAKER] = {
978
+
.type = HDA_FIXUP_PINS,
979
+
.v.pins = (const struct hda_pintbl[]) {
980
+
{ 0x1d, 0x82170111 },
981
+
{ }
982
+
},
983
+
},
978
984
};
979
985
980
986
static const struct snd_pci_quirk cxt5045_fixups[] = {
···
1078
1070
SND_PCI_QUIRK_VENDOR(0x17aa, "Thinkpad", CXT_FIXUP_THINKPAD_ACPI),
1079
1071
SND_PCI_QUIRK(0x1c06, 0x2011, "Lemote A1004", CXT_PINCFG_LEMOTE_A1004),
1080
1072
SND_PCI_QUIRK(0x1c06, 0x2012, "Lemote A1205", CXT_PINCFG_LEMOTE_A1205),
1073
+
SND_PCI_QUIRK(0x2782, 0x12c3, "Sirius Gen1", CXT_PINCFG_TOP_SPEAKER),
1074
+
SND_PCI_QUIRK(0x2782, 0x12c5, "Sirius Gen2", CXT_PINCFG_TOP_SPEAKER),
1081
1075
{}
1082
1076
};
1083
1077
···
1099
1089
{ .id = CXT_FIXUP_HP_MIC_NO_PRESENCE, .name = "hp-mic-fix" },
1100
1090
{ .id = CXT_PINCFG_LENOVO_NOTEBOOK, .name = "lenovo-20149" },
1101
1091
{ .id = CXT_PINCFG_SWS_JS201D, .name = "sws-js201d" },
1092
+
{ .id = CXT_PINCFG_TOP_SPEAKER, .name = "sirius-top-speaker" },
1102
1093
{}
1103
1094
};
1104
1095
+1
sound/pci/hda/patch_hdmi.c
+1
sound/pci/hda/patch_hdmi.c
···
4639
4639
HDA_CODEC_ENTRY(0x8086281e, "Battlemage HDMI", patch_i915_adlp_hdmi),
4640
4640
HDA_CODEC_ENTRY(0x8086281f, "Raptor Lake P HDMI", patch_i915_adlp_hdmi),
4641
4641
HDA_CODEC_ENTRY(0x80862820, "Lunar Lake HDMI", patch_i915_adlp_hdmi),
4642
+
HDA_CODEC_ENTRY(0x80862822, "Panther Lake HDMI", patch_i915_adlp_hdmi),
4642
4643
HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4643
4644
HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4644
4645
HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
+21
-1
sound/pci/hda/patch_realtek.c
+21
-1
sound/pci/hda/patch_realtek.c
···
7538
7538
ALC236_FIXUP_HP_GPIO_LED,
7539
7539
ALC236_FIXUP_HP_MUTE_LED,
7540
7540
ALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF,
7541
+
ALC236_FIXUP_LENOVO_INV_DMIC,
7541
7542
ALC298_FIXUP_SAMSUNG_AMP,
7542
7543
ALC298_FIXUP_SAMSUNG_AMP2,
7543
7544
ALC298_FIXUP_SAMSUNG_HEADPHONE_VERY_QUIET,
···
7638
7637
ALC287_FIXUP_LENOVO_14ARP8_LEGION_IAH7,
7639
7638
ALC287_FIXUP_LENOVO_SSID_17AA3820,
7640
7639
ALCXXX_FIXUP_CS35LXX,
7640
+
ALC245_FIXUP_CLEVO_NOISY_MIC,
7641
7641
};
7642
7642
7643
7643
/* A special fixup for Lenovo C940 and Yoga Duet 7;
···
9163
9161
.type = HDA_FIXUP_FUNC,
9164
9162
.v.func = alc236_fixup_hp_mute_led_micmute_vref,
9165
9163
},
9164
+
[ALC236_FIXUP_LENOVO_INV_DMIC] = {
9165
+
.type = HDA_FIXUP_FUNC,
9166
+
.v.func = alc_fixup_inv_dmic,
9167
+
.chained = true,
9168
+
.chain_id = ALC283_FIXUP_INT_MIC,
9169
+
},
9166
9170
[ALC298_FIXUP_SAMSUNG_AMP] = {
9167
9171
.type = HDA_FIXUP_FUNC,
9168
9172
.v.func = alc298_fixup_samsung_amp,
···
9978
9970
.type = HDA_FIXUP_FUNC,
9979
9971
.v.func = cs35lxx_autodet_fixup,
9980
9972
},
9973
+
[ALC245_FIXUP_CLEVO_NOISY_MIC] = {
9974
+
.type = HDA_FIXUP_FUNC,
9975
+
.v.func = alc269_fixup_limit_int_mic_boost,
9976
+
.chained = true,
9977
+
.chain_id = ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE,
9978
+
},
9981
9979
};
9982
9980
9983
9981
static const struct snd_pci_quirk alc269_fixup_tbl[] = {
···
10232
10218
SND_PCI_QUIRK(0x103c, 0x87f5, "HP", ALC287_FIXUP_HP_GPIO_LED),
10233
10219
SND_PCI_QUIRK(0x103c, 0x87f6, "HP Spectre x360 14", ALC245_FIXUP_HP_X360_AMP),
10234
10220
SND_PCI_QUIRK(0x103c, 0x87f7, "HP Spectre x360 14", ALC245_FIXUP_HP_X360_AMP),
10221
+
SND_PCI_QUIRK(0x103c, 0x87fd, "HP Laptop 14-dq2xxx", ALC236_FIXUP_HP_MUTE_LED_COEFBIT2),
10235
10222
SND_PCI_QUIRK(0x103c, 0x87fe, "HP Laptop 15s-fq2xxx", ALC236_FIXUP_HP_MUTE_LED_COEFBIT2),
10236
10223
SND_PCI_QUIRK(0x103c, 0x8805, "HP ProBook 650 G8 Notebook PC", ALC236_FIXUP_HP_GPIO_LED),
10237
10224
SND_PCI_QUIRK(0x103c, 0x880d, "HP EliteBook 830 G8 Notebook PC", ALC285_FIXUP_HP_GPIO_LED),
···
10357
10342
SND_PCI_QUIRK(0x103c, 0x8c16, "HP Spectre 16", ALC287_FIXUP_CS35L41_I2C_2),
10358
10343
SND_PCI_QUIRK(0x103c, 0x8c17, "HP Spectre 16", ALC287_FIXUP_CS35L41_I2C_2),
10359
10344
SND_PCI_QUIRK(0x103c, 0x8c21, "HP Pavilion Plus Laptop 14-ey0XXX", ALC245_FIXUP_HP_X360_MUTE_LEDS),
10345
+
SND_PCI_QUIRK(0x103c, 0x8c30, "HP Victus 15-fb1xxx", ALC245_FIXUP_HP_MUTE_LED_COEFBIT),
10360
10346
SND_PCI_QUIRK(0x103c, 0x8c46, "HP EliteBook 830 G11", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED),
10361
10347
SND_PCI_QUIRK(0x103c, 0x8c47, "HP EliteBook 840 G11", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED),
10362
10348
SND_PCI_QUIRK(0x103c, 0x8c48, "HP EliteBook 860 G11", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED),
···
10495
10479
SND_PCI_QUIRK(0x1043, 0x1e02, "ASUS UX3402ZA", ALC245_FIXUP_CS35L41_SPI_2),
10496
10480
SND_PCI_QUIRK(0x1043, 0x1e11, "ASUS Zephyrus G15", ALC289_FIXUP_ASUS_GA502),
10497
10481
SND_PCI_QUIRK(0x1043, 0x1e12, "ASUS UM3402", ALC287_FIXUP_CS35L41_I2C_2),
10482
+
SND_PCI_QUIRK(0x1043, 0x1e1f, "ASUS Vivobook 15 X1504VAP", ALC2XX_FIXUP_HEADSET_MIC),
10498
10483
SND_PCI_QUIRK(0x1043, 0x1e51, "ASUS Zephyrus M15", ALC294_FIXUP_ASUS_GU502_PINS),
10499
10484
SND_PCI_QUIRK(0x1043, 0x1e5e, "ASUS ROG Strix G513", ALC294_FIXUP_ASUS_G513_PINS),
10500
10485
SND_PCI_QUIRK(0x1043, 0x1e63, "ASUS H7606W", ALC285_FIXUP_CS35L56_I2C_2),
···
10636
10619
SND_PCI_QUIRK(0x1558, 0xa600, "Clevo NL50NU", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
10637
10620
SND_PCI_QUIRK(0x1558, 0xa650, "Clevo NP[567]0SN[CD]", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
10638
10621
SND_PCI_QUIRK(0x1558, 0xa671, "Clevo NP70SN[CDE]", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
10639
-
SND_PCI_QUIRK(0x1558, 0xa763, "Clevo V54x_6x_TU", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
10622
+
SND_PCI_QUIRK(0x1558, 0xa741, "Clevo V54x_6x_TNE", ALC245_FIXUP_CLEVO_NOISY_MIC),
10623
+
SND_PCI_QUIRK(0x1558, 0xa763, "Clevo V54x_6x_TU", ALC245_FIXUP_CLEVO_NOISY_MIC),
10640
10624
SND_PCI_QUIRK(0x1558, 0xb018, "Clevo NP50D[BE]", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
10641
10625
SND_PCI_QUIRK(0x1558, 0xb019, "Clevo NH77D[BE]Q", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
10642
10626
SND_PCI_QUIRK(0x1558, 0xb022, "Clevo NH77D[DC][QW]", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE),
···
10760
10742
SND_PCI_QUIRK(0x17aa, 0x38f9, "Thinkbook 16P Gen5", ALC287_FIXUP_CS35L41_I2C_2),
10761
10743
SND_PCI_QUIRK(0x17aa, 0x38fa, "Thinkbook 16P Gen5", ALC287_FIXUP_CS35L41_I2C_2),
10762
10744
SND_PCI_QUIRK(0x17aa, 0x3902, "Lenovo E50-80", ALC269_FIXUP_DMIC_THINKPAD_ACPI),
10745
+
SND_PCI_QUIRK(0x17aa, 0x3913, "Lenovo 145", ALC236_FIXUP_LENOVO_INV_DMIC),
10763
10746
SND_PCI_QUIRK(0x17aa, 0x3977, "IdeaPad S210", ALC283_FIXUP_INT_MIC),
10764
10747
SND_PCI_QUIRK(0x17aa, 0x3978, "Lenovo B50-70", ALC269_FIXUP_DMIC_THINKPAD_ACPI),
10765
10748
SND_PCI_QUIRK(0x17aa, 0x3bf8, "Quanta FL1", ALC269_FIXUP_PCM_44K),
···
11013
10994
{.id = ALC623_FIXUP_LENOVO_THINKSTATION_P340, .name = "alc623-lenovo-thinkstation-p340"},
11014
10995
{.id = ALC255_FIXUP_ACER_HEADPHONE_AND_MIC, .name = "alc255-acer-headphone-and-mic"},
11015
10996
{.id = ALC285_FIXUP_HP_GPIO_AMP_INIT, .name = "alc285-hp-amp-init"},
10997
+
{.id = ALC236_FIXUP_LENOVO_INV_DMIC, .name = "alc236-fixup-lenovo-inv-mic"},
11016
10998
{}
11017
10999
};
11018
11000
#define ALC225_STANDARD_PINS \
+7
sound/soc/amd/yc/acp6x-mach.c
+7
sound/soc/amd/yc/acp6x-mach.c
···
356
356
{
357
357
.driver_data = &acp6x_card,
358
358
.matches = {
359
+
DMI_MATCH(DMI_BOARD_VENDOR, "Micro-Star International Co., Ltd."),
360
+
DMI_MATCH(DMI_PRODUCT_NAME, "Bravo 17 D7VEK"),
361
+
}
362
+
},
363
+
{
364
+
.driver_data = &acp6x_card,
365
+
.matches = {
359
366
DMI_MATCH(DMI_BOARD_VENDOR, "Alienware"),
360
367
DMI_MATCH(DMI_PRODUCT_NAME, "Alienware m17 R5 AMD"),
361
368
}
+1
sound/soc/codecs/chv3-codec.c
+1
sound/soc/codecs/chv3-codec.c
+10
-1
sound/soc/codecs/lpass-va-macro.c
+10
-1
sound/soc/codecs/lpass-va-macro.c
···
228
228
struct va_macro_data {
229
229
bool has_swr_master;
230
230
bool has_npl_clk;
231
+
int version;
231
232
};
232
233
233
234
static const struct va_macro_data sm8250_va_data = {
234
235
.has_swr_master = false,
235
236
.has_npl_clk = false,
237
+
.version = LPASS_CODEC_VERSION_1_0,
236
238
};
237
239
238
240
static const struct va_macro_data sm8450_va_data = {
···
1589
1587
goto err_npl;
1590
1588
}
1591
1589
1592
-
va_macro_set_lpass_codec_version(va);
1590
+
/**
1591
+
* old version of codecs do not have a reliable way to determine the
1592
+
* version from registers, get them from soc specific data
1593
+
*/
1594
+
if (data->version)
1595
+
lpass_macro_set_codec_version(data->version);
1596
+
else /* read version from register */
1597
+
va_macro_set_lpass_codec_version(va);
1593
1598
1594
1599
if (va->has_swr_master) {
1595
1600
/* Set default CLK div to 1 */
+1
sound/soc/codecs/tda7419.c
+1
sound/soc/codecs/tda7419.c
+1
sound/soc/google/chv3-i2s.c
+1
sound/soc/google/chv3-i2s.c
+1
-1
sound/soc/intel/boards/bxt_rt298.c
+1
-1
sound/soc/intel/boards/bxt_rt298.c
···
605
605
int i;
606
606
607
607
for (i = 0; i < ARRAY_SIZE(broxton_rt298_dais); i++) {
608
-
if (card->dai_link[i].codecs->name &&
608
+
if (card->dai_link[i].num_codecs &&
609
609
!strncmp(card->dai_link[i].codecs->name, "i2c-INT343A:00",
610
610
I2C_NAME_SIZE)) {
611
611
if (!strncmp(card->name, "broxton-rt298",
+1
-1
sound/soc/intel/boards/bytcht_cx2072x.c
+1
-1
sound/soc/intel/boards/bytcht_cx2072x.c
···
241
241
242
242
/* fix index of codec dai */
243
243
for (i = 0; i < ARRAY_SIZE(byt_cht_cx2072x_dais); i++) {
244
-
if (byt_cht_cx2072x_dais[i].codecs->name &&
244
+
if (byt_cht_cx2072x_dais[i].num_codecs &&
245
245
!strcmp(byt_cht_cx2072x_dais[i].codecs->name,
246
246
"i2c-14F10720:00")) {
247
247
dai_index = i;
+1
-1
sound/soc/intel/boards/bytcht_da7213.c
+1
-1
sound/soc/intel/boards/bytcht_da7213.c
+1
-1
sound/soc/intel/boards/bytcht_es8316.c
+1
-1
sound/soc/intel/boards/bytcht_es8316.c
···
546
546
547
547
/* fix index of codec dai */
548
548
for (i = 0; i < ARRAY_SIZE(byt_cht_es8316_dais); i++) {
549
-
if (byt_cht_es8316_dais[i].codecs->name &&
549
+
if (byt_cht_es8316_dais[i].num_codecs &&
550
550
!strcmp(byt_cht_es8316_dais[i].codecs->name,
551
551
"i2c-ESSX8316:00")) {
552
552
dai_index = i;
+1
-1
sound/soc/intel/boards/bytcr_rt5640.c
+1
-1
sound/soc/intel/boards/bytcr_rt5640.c
···
1677
1677
1678
1678
/* fix index of codec dai */
1679
1679
for (i = 0; i < ARRAY_SIZE(byt_rt5640_dais); i++) {
1680
-
if (byt_rt5640_dais[i].codecs->name &&
1680
+
if (byt_rt5640_dais[i].num_codecs &&
1681
1681
!strcmp(byt_rt5640_dais[i].codecs->name,
1682
1682
"i2c-10EC5640:00")) {
1683
1683
dai_index = i;
+1
-1
sound/soc/intel/boards/bytcr_rt5651.c
+1
-1
sound/soc/intel/boards/bytcr_rt5651.c
+1
-1
sound/soc/intel/boards/bytcr_wm5102.c
+1
-1
sound/soc/intel/boards/bytcr_wm5102.c
+1
-1
sound/soc/intel/boards/cht_bsw_rt5645.c
+1
-1
sound/soc/intel/boards/cht_bsw_rt5645.c
+1
-1
sound/soc/intel/boards/cht_bsw_rt5672.c
+1
-1
sound/soc/intel/boards/cht_bsw_rt5672.c
-1
sound/soc/intel/common/soc-acpi-intel-cht-match.c
-1
sound/soc/intel/common/soc-acpi-intel-cht-match.c
+1
sound/soc/intel/keembay/kmb_platform.c
+1
sound/soc/intel/keembay/kmb_platform.c
+13
-4
sound/soc/mediatek/mt8188/mt8188-mt6359.c
+13
-4
sound/soc/mediatek/mt8188/mt8188-mt6359.c
···
734
734
struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(rtd->card);
735
735
struct snd_soc_jack *jack = &soc_card_data->card_data->jacks[MT8188_JACK_HEADSET];
736
736
struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component;
737
+
struct mtk_platform_card_data *card_data = soc_card_data->card_data;
737
738
int ret;
738
739
739
740
ret = snd_soc_dapm_new_controls(&card->dapm, mt8188_nau8825_widgets,
···
763
762
return ret;
764
763
}
765
764
766
-
snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
767
-
snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
768
-
snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
769
-
snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
765
+
if (card_data->flags & ES8326_HS_PRESENT) {
766
+
snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
767
+
snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
768
+
snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
769
+
snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
770
+
} else {
771
+
snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
772
+
snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
773
+
snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
774
+
snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
775
+
}
776
+
770
777
ret = snd_soc_component_set_jack(component, jack, NULL);
771
778
772
779
if (ret) {
+1
sound/soc/soc-dapm.c
+1
sound/soc/soc-dapm.c
+2
sound/soc/sof/topology.c
+2
sound/soc/sof/topology.c
+73
-70
sound/soc/sunxi/sun4i-i2s.c
+73
-70
sound/soc/sunxi/sun4i-i2s.c
···
100
100
#define SUN8I_I2S_CTRL_MODE_PCM (0 << 4)
101
101
102
102
#define SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(19)
103
-
#define SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 19)
104
-
#define SUN8I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 19)
103
+
#define SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH (1 << 19)
104
+
#define SUN8I_I2S_FMT0_LRCLK_POLARITY_START_LOW (0 << 19)
105
105
#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8)
106
106
#define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
107
107
#define SUN8I_I2S_FMT0_BCLK_POLARITY_MASK BIT(7)
···
729
729
static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
730
730
unsigned int fmt)
731
731
{
732
-
u32 mode, val;
732
+
u32 mode, lrclk_pol, bclk_pol, val;
733
733
u8 offset;
734
-
735
-
/*
736
-
* DAI clock polarity
737
-
*
738
-
* The setup for LRCK contradicts the datasheet, but under a
739
-
* scope it's clear that the LRCK polarity is reversed
740
-
* compared to the expected polarity on the bus.
741
-
*/
742
-
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
743
-
case SND_SOC_DAIFMT_IB_IF:
744
-
/* Invert both clocks */
745
-
val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
746
-
break;
747
-
case SND_SOC_DAIFMT_IB_NF:
748
-
/* Invert bit clock */
749
-
val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
750
-
SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
751
-
break;
752
-
case SND_SOC_DAIFMT_NB_IF:
753
-
/* Invert frame clock */
754
-
val = 0;
755
-
break;
756
-
case SND_SOC_DAIFMT_NB_NF:
757
-
val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
758
-
break;
759
-
default:
760
-
return -EINVAL;
761
-
}
762
-
763
-
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
764
-
SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
765
-
SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
766
-
val);
767
734
768
735
/* DAI Mode */
769
736
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
770
737
case SND_SOC_DAIFMT_DSP_A:
738
+
lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
771
739
mode = SUN8I_I2S_CTRL_MODE_PCM;
772
740
offset = 1;
773
741
break;
774
742
775
743
case SND_SOC_DAIFMT_DSP_B:
744
+
lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
776
745
mode = SUN8I_I2S_CTRL_MODE_PCM;
777
746
offset = 0;
778
747
break;
779
748
780
749
case SND_SOC_DAIFMT_I2S:
750
+
lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_LOW;
781
751
mode = SUN8I_I2S_CTRL_MODE_LEFT;
782
752
offset = 1;
783
753
break;
784
754
785
755
case SND_SOC_DAIFMT_LEFT_J:
756
+
lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
786
757
mode = SUN8I_I2S_CTRL_MODE_LEFT;
787
758
offset = 0;
788
759
break;
789
760
790
761
case SND_SOC_DAIFMT_RIGHT_J:
762
+
lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
791
763
mode = SUN8I_I2S_CTRL_MODE_RIGHT;
792
764
offset = 0;
793
765
break;
···
776
804
regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
777
805
SUN8I_I2S_TX_CHAN_OFFSET_MASK,
778
806
SUN8I_I2S_TX_CHAN_OFFSET(offset));
807
+
808
+
/* DAI clock polarity */
809
+
bclk_pol = SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL;
810
+
811
+
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
812
+
case SND_SOC_DAIFMT_IB_IF:
813
+
/* Invert both clocks */
814
+
lrclk_pol ^= SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK;
815
+
bclk_pol = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
816
+
break;
817
+
case SND_SOC_DAIFMT_IB_NF:
818
+
/* Invert bit clock */
819
+
bclk_pol = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
820
+
break;
821
+
case SND_SOC_DAIFMT_NB_IF:
822
+
/* Invert frame clock */
823
+
lrclk_pol ^= SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK;
824
+
break;
825
+
case SND_SOC_DAIFMT_NB_NF:
826
+
/* No inversion */
827
+
break;
828
+
default:
829
+
return -EINVAL;
830
+
}
831
+
832
+
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
833
+
SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
834
+
SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
835
+
lrclk_pol | bclk_pol);
779
836
780
837
/* DAI clock master masks */
781
838
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
···
837
836
static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
838
837
unsigned int fmt)
839
838
{
840
-
u32 mode, val;
839
+
u32 mode, lrclk_pol, bclk_pol, val;
841
840
u8 offset;
842
-
843
-
/*
844
-
* DAI clock polarity
845
-
*
846
-
* The setup for LRCK contradicts the datasheet, but under a
847
-
* scope it's clear that the LRCK polarity is reversed
848
-
* compared to the expected polarity on the bus.
849
-
*/
850
-
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
851
-
case SND_SOC_DAIFMT_IB_IF:
852
-
/* Invert both clocks */
853
-
val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
854
-
break;
855
-
case SND_SOC_DAIFMT_IB_NF:
856
-
/* Invert bit clock */
857
-
val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
858
-
SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
859
-
break;
860
-
case SND_SOC_DAIFMT_NB_IF:
861
-
/* Invert frame clock */
862
-
val = 0;
863
-
break;
864
-
case SND_SOC_DAIFMT_NB_NF:
865
-
val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
866
-
break;
867
-
default:
868
-
return -EINVAL;
869
-
}
870
-
871
-
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
872
-
SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
873
-
SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
874
-
val);
875
841
876
842
/* DAI Mode */
877
843
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
878
844
case SND_SOC_DAIFMT_DSP_A:
845
+
lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
879
846
mode = SUN8I_I2S_CTRL_MODE_PCM;
880
847
offset = 1;
881
848
break;
882
849
883
850
case SND_SOC_DAIFMT_DSP_B:
851
+
lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
884
852
mode = SUN8I_I2S_CTRL_MODE_PCM;
885
853
offset = 0;
886
854
break;
887
855
888
856
case SND_SOC_DAIFMT_I2S:
857
+
lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_LOW;
889
858
mode = SUN8I_I2S_CTRL_MODE_LEFT;
890
859
offset = 1;
891
860
break;
892
861
893
862
case SND_SOC_DAIFMT_LEFT_J:
863
+
lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
894
864
mode = SUN8I_I2S_CTRL_MODE_LEFT;
895
865
offset = 0;
896
866
break;
897
867
898
868
case SND_SOC_DAIFMT_RIGHT_J:
869
+
lrclk_pol = SUN8I_I2S_FMT0_LRCLK_POLARITY_START_HIGH;
899
870
mode = SUN8I_I2S_CTRL_MODE_RIGHT;
900
871
offset = 0;
901
872
break;
···
884
911
regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
885
912
SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK,
886
913
SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset));
914
+
915
+
/* DAI clock polarity */
916
+
bclk_pol = SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL;
917
+
918
+
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
919
+
case SND_SOC_DAIFMT_IB_IF:
920
+
/* Invert both clocks */
921
+
lrclk_pol ^= SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK;
922
+
bclk_pol = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
923
+
break;
924
+
case SND_SOC_DAIFMT_IB_NF:
925
+
/* Invert bit clock */
926
+
bclk_pol = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
927
+
break;
928
+
case SND_SOC_DAIFMT_NB_IF:
929
+
/* Invert frame clock */
930
+
lrclk_pol ^= SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK;
931
+
break;
932
+
case SND_SOC_DAIFMT_NB_NF:
933
+
/* No inversion */
934
+
break;
935
+
default:
936
+
return -EINVAL;
937
+
}
938
+
939
+
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
940
+
SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
941
+
SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
942
+
lrclk_pol | bclk_pol);
943
+
887
944
888
945
/* DAI clock master masks */
889
946
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
+7
-5
sound/soc/tegra/tegra210_ahub.c
+7
-5
sound/soc/tegra/tegra210_ahub.c
···
2
2
//
3
3
// tegra210_ahub.c - Tegra210 AHUB driver
4
4
//
5
-
// Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
5
+
// Copyright (c) 2020-2024, NVIDIA CORPORATION. All rights reserved.
6
6
7
7
#include <linux/clk.h>
8
8
#include <linux/device.h>
···
1391
1391
return err;
1392
1392
}
1393
1393
1394
-
err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
1395
-
if (err)
1396
-
return err;
1397
-
1398
1394
pm_runtime_enable(&pdev->dev);
1395
+
1396
+
err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
1397
+
if (err) {
1398
+
pm_runtime_disable(&pdev->dev);
1399
+
return err;
1400
+
}
1399
1401
1400
1402
return 0;
1401
1403
}
+1
-1
tools/hv/Makefile
+1
-1
tools/hv/Makefile
···
52
52
53
53
clean:
54
54
rm -f $(ALL_PROGRAMS)
55
-
find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.d' -delete
55
+
find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.d' -delete -o -name '\.*.cmd' -delete
56
56
57
57
install: $(ALL_PROGRAMS)
58
58
install -d -m 755 $(DESTDIR)$(sbindir); \
+1
-1
tools/hv/lsvmbus
+1
-1
tools/hv/lsvmbus
+34
tools/testing/selftests/bpf/prog_tests/btf.c
+34
tools/testing/selftests/bpf/prog_tests/btf.c
···
3551
3551
BTF_STR_SEC("\0x\0?.foo bar:buz"),
3552
3552
},
3553
3553
{
3554
+
.descr = "datasec: name with non-printable first char not is ok",
3555
+
.raw_types = {
3556
+
/* int */
3557
+
BTF_TYPE_INT_ENC(0, BTF_INT_SIGNED, 0, 32, 4), /* [1] */
3558
+
/* VAR x */ /* [2] */
3559
+
BTF_TYPE_ENC(1, BTF_INFO_ENC(BTF_KIND_VAR, 0, 0), 1),
3560
+
BTF_VAR_STATIC,
3561
+
/* DATASEC ?.data */ /* [3] */
3562
+
BTF_TYPE_ENC(3, BTF_INFO_ENC(BTF_KIND_DATASEC, 0, 1), 4),
3563
+
BTF_VAR_SECINFO_ENC(2, 0, 4),
3564
+
BTF_END_RAW,
3565
+
},
3566
+
BTF_STR_SEC("\0x\0\7foo"),
3567
+
.err_str = "Invalid name",
3568
+
.btf_load_err = true,
3569
+
},
3570
+
{
3571
+
.descr = "datasec: name '\\0' is not ok",
3572
+
.raw_types = {
3573
+
/* int */
3574
+
BTF_TYPE_INT_ENC(0, BTF_INT_SIGNED, 0, 32, 4), /* [1] */
3575
+
/* VAR x */ /* [2] */
3576
+
BTF_TYPE_ENC(1, BTF_INFO_ENC(BTF_KIND_VAR, 0, 0), 1),
3577
+
BTF_VAR_STATIC,
3578
+
/* DATASEC \0 */ /* [3] */
3579
+
BTF_TYPE_ENC(3, BTF_INFO_ENC(BTF_KIND_DATASEC, 0, 1), 4),
3580
+
BTF_VAR_SECINFO_ENC(2, 0, 4),
3581
+
BTF_END_RAW,
3582
+
},
3583
+
BTF_STR_SEC("\0x\0"),
3584
+
.err_str = "Invalid name",
3585
+
.btf_load_err = true,
3586
+
},
3587
+
{
3554
3588
.descr = "type name '?foo' is not ok",
3555
3589
.raw_types = {
3556
3590
/* union ?foo; */
+14
-2
tools/testing/selftests/net/lib/csum.c
+14
-2
tools/testing/selftests/net/lib/csum.c
···
654
654
{
655
655
struct iphdr *iph = nh;
656
656
uint16_t proto = cfg_encap ? IPPROTO_UDP : cfg_proto;
657
+
uint16_t ip_len;
657
658
658
659
if (len < sizeof(*iph) || iph->protocol != proto)
659
660
return -1;
660
661
662
+
ip_len = ntohs(iph->tot_len);
663
+
if (ip_len > len || ip_len < sizeof(*iph))
664
+
return -1;
665
+
666
+
len = ip_len;
661
667
iph_addr_p = &iph->saddr;
662
668
if (proto == IPPROTO_TCP)
663
669
return recv_verify_packet_tcp(iph + 1, len - sizeof(*iph));
···
675
669
{
676
670
struct ipv6hdr *ip6h = nh;
677
671
uint16_t proto = cfg_encap ? IPPROTO_UDP : cfg_proto;
672
+
uint16_t ip_len;
678
673
679
674
if (len < sizeof(*ip6h) || ip6h->nexthdr != proto)
680
675
return -1;
681
676
677
+
ip_len = ntohs(ip6h->payload_len);
678
+
if (ip_len > len - sizeof(*ip6h))
679
+
return -1;
680
+
681
+
len = ip_len;
682
682
iph_addr_p = &ip6h->saddr;
683
683
684
684
if (proto == IPPROTO_TCP)
685
-
return recv_verify_packet_tcp(ip6h + 1, len - sizeof(*ip6h));
685
+
return recv_verify_packet_tcp(ip6h + 1, len);
686
686
else
687
-
return recv_verify_packet_udp(ip6h + 1, len - sizeof(*ip6h));
687
+
return recv_verify_packet_udp(ip6h + 1, len);
688
688
}
689
689
690
690
/* return whether auxdata includes TP_STATUS_CSUM_VALID */
+2
tools/testing/selftests/net/mptcp/Makefile
+2
tools/testing/selftests/net/mptcp/Makefile
+3
-1
tools/testing/selftests/net/mptcp/mptcp_join.sh
+3
-1
tools/testing/selftests/net/mptcp/mptcp_join.sh
···
3130
3130
pm_nl_set_limits $ns1 1 3
3131
3131
pm_nl_set_limits $ns2 1 3
3132
3132
pm_nl_add_endpoint $ns1 10.0.2.1 flags signal
3133
-
pm_nl_add_endpoint $ns2 10.0.1.2 flags subflow,fullmesh
3133
+
if mptcp_lib_kallsyms_has "mptcp_pm_subflow_check_next$"; then
3134
+
pm_nl_add_endpoint $ns2 10.0.1.2 flags subflow,fullmesh
3135
+
fi
3134
3136
fullmesh=1 speed=slow \
3135
3137
run_tests $ns1 $ns2 10.0.1.1
3136
3138
chk_join_nr 3 3 3
-2
tools/testing/selftests/riscv/mm/mmap_bottomup.c
-2
tools/testing/selftests/riscv/mm/mmap_bottomup.c
-2
tools/testing/selftests/riscv/mm/mmap_default.c
-2
tools/testing/selftests/riscv/mm/mmap_default.c
-67
tools/testing/selftests/riscv/mm/mmap_test.h
-67
tools/testing/selftests/riscv/mm/mmap_test.h
···
10
10
#define TOP_DOWN 0
11
11
#define BOTTOM_UP 1
12
12
13
-
#if __riscv_xlen == 64
14
-
uint64_t random_addresses[] = {
15
-
0x19764f0d73b3a9f0, 0x016049584cecef59, 0x3580bdd3562f4acd,
16
-
0x1164219f20b17da0, 0x07d97fcb40ff2373, 0x76ec528921272ee7,
17
-
0x4dd48c38a3de3f70, 0x2e11415055f6997d, 0x14b43334ac476c02,
18
-
0x375a60795aff19f6, 0x47f3051725b8ee1a, 0x4e697cf240494a9f,
19
-
0x456b59b5c2f9e9d1, 0x101724379d63cb96, 0x7fe9ad31619528c1,
20
-
0x2f417247c495c2ea, 0x329a5a5b82943a5e, 0x06d7a9d6adcd3827,
21
-
0x327b0b9ee37f62d5, 0x17c7b1851dfd9b76, 0x006ebb6456ec2cd9,
22
-
0x00836cd14146a134, 0x00e5c4dcde7126db, 0x004c29feadf75753,
23
-
0x00d8b20149ed930c, 0x00d71574c269387a, 0x0006ebe4a82acb7a,
24
-
0x0016135df51f471b, 0x00758bdb55455160, 0x00d0bdd949b13b32,
25
-
0x00ecea01e7c5f54b, 0x00e37b071b9948b1, 0x0011fdd00ff57ab3,
26
-
0x00e407294b52f5ea, 0x00567748c200ed20, 0x000d073084651046,
27
-
0x00ac896f4365463c, 0x00eb0d49a0b26216, 0x0066a2564a982a31,
28
-
0x002e0d20237784ae, 0x0000554ff8a77a76, 0x00006ce07a54c012,
29
-
0x000009570516d799, 0x00000954ca15b84d, 0x0000684f0d453379,
30
-
0x00002ae5816302b5, 0x0000042403fb54bf, 0x00004bad7392bf30,
31
-
0x00003e73bfa4b5e3, 0x00005442c29978e0, 0x00002803f11286b6,
32
-
0x000073875d745fc6, 0x00007cede9cb8240, 0x000027df84cc6a4f,
33
-
0x00006d7e0e74242a, 0x00004afd0b836e02, 0x000047d0e837cd82,
34
-
0x00003b42405efeda, 0x00001531bafa4c95, 0x00007172cae34ac4,
35
-
};
36
-
#else
37
-
uint32_t random_addresses[] = {
38
-
0x8dc302e0, 0x929ab1e0, 0xb47683ba, 0xea519c73, 0xa19f1c90, 0xc49ba213,
39
-
0x8f57c625, 0xadfe5137, 0x874d4d95, 0xaa20f09d, 0xcf21ebfc, 0xda7737f1,
40
-
0xcedf392a, 0x83026c14, 0xccedca52, 0xc6ccf826, 0xe0cd9415, 0x997472ca,
41
-
0xa21a44c1, 0xe82196f5, 0xa23fd66b, 0xc28d5590, 0xd009cdce, 0xcf0be646,
42
-
0x8fc8c7ff, 0xe2a85984, 0xa3d3236b, 0x89a0619d, 0xc03db924, 0xb5d4cc1b,
43
-
0xb96ee04c, 0xd191da48, 0xb432a000, 0xaa2bebbc, 0xa2fcb289, 0xb0cca89b,
44
-
0xb0c18d6a, 0x88f58deb, 0xa4d42d1c, 0xe4d74e86, 0x99902b09, 0x8f786d31,
45
-
0xbec5e381, 0x9a727e65, 0xa9a65040, 0xa880d789, 0x8f1b335e, 0xfc821c1e,
46
-
0x97e34be4, 0xbbef84ed, 0xf447d197, 0xfd7ceee2, 0xe632348d, 0xee4590f4,
47
-
0x958992a5, 0xd57e05d6, 0xfd240970, 0xc5b0dcff, 0xd96da2c2, 0xa7ae041d,
48
-
};
49
-
#endif
50
-
51
-
// Only works on 64 bit
52
-
#if __riscv_xlen == 64
53
13
#define PROT (PROT_READ | PROT_WRITE)
54
14
#define FLAGS (MAP_PRIVATE | MAP_ANONYMOUS)
55
-
56
-
/* mmap must return a value that doesn't use more bits than the hint address. */
57
-
static inline unsigned long get_max_value(unsigned long input)
58
-
{
59
-
unsigned long max_bit = (1UL << (((sizeof(unsigned long) * 8) - 1 -
60
-
__builtin_clzl(input))));
61
-
62
-
return max_bit + (max_bit - 1);
63
-
}
64
-
65
-
#define TEST_MMAPS \
66
-
({ \
67
-
void *mmap_addr; \
68
-
for (int i = 0; i < ARRAY_SIZE(random_addresses); i++) { \
69
-
mmap_addr = mmap((void *)random_addresses[i], \
70
-
5 * sizeof(int), PROT, FLAGS, 0, 0); \
71
-
EXPECT_NE(MAP_FAILED, mmap_addr); \
72
-
EXPECT_GE((void *)get_max_value(random_addresses[i]), \
73
-
mmap_addr); \
74
-
mmap_addr = mmap((void *)random_addresses[i], \
75
-
5 * sizeof(int), PROT, FLAGS, 0, 0); \
76
-
EXPECT_NE(MAP_FAILED, mmap_addr); \
77
-
EXPECT_GE((void *)get_max_value(random_addresses[i]), \
78
-
mmap_addr); \
79
-
} \
80
-
})
81
-
#endif /* __riscv_xlen == 64 */
82
15
83
16
static inline int memory_layout(void)
84
17
{