Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
rMerge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM fixes from Radim Krčmář:
"ARM:
- PSCI selection API, a leftover from 4.16 (for stable)
- Kick vcpu on active interrupt affinity change
- Plug a VMID allocation race on oversubscribed systems
- Silence debug messages
- Update Christoffer's email address (linaro -> arm)
x86:
- Expose userspace-relevant bits of a newly added feature
- Fix TLB flushing on VMX with VPID, but without EPT"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
x86/headers/UAPI: Move DISABLE_EXITS KVM capability bits to the UAPI
kvm: apic: Flush TLB after APIC mode/address change if VPIDs are in use
arm/arm64: KVM: Add PSCI version selection API
KVM: arm/arm64: vgic: Kick new VCPU on interrupt migration
arm64: KVM: Demote SVE and LORegion warnings to debug only
MAINTAINERS: Update e-mail address for Christoffer Dall
KVM: arm/arm64: Close VMID generation race
+189
-32
+8
-1
Documentation/virtual/kvm/api.txt
+8
-1
Documentation/virtual/kvm/api.txt
···
1960
1960
ARM 64-bit FP registers have the following id bit patterns:
1961
1961
0x4030 0000 0012 0 <regno:12>
1962
1962
1963
+
ARM firmware pseudo-registers have the following bit pattern:
1964
+
0x4030 0000 0014 <regno:16>
1965
+
1963
1966
1964
1967
arm64 registers are mapped using the lower 32 bits. The upper 16 of
1965
1968
that is the register group type, or coprocessor number:
···
1978
1975
1979
1976
arm64 system registers have the following id bit patterns:
1980
1977
0x6030 0000 0013 <op0:2> <op1:3> <crn:4> <crm:4> <op2:3>
1978
+
1979
+
arm64 firmware pseudo-registers have the following bit pattern:
1980
+
0x6030 0000 0014 <regno:16>
1981
1981
1982
1982
1983
1983
MIPS registers are mapped using the lower 32 bits. The upper 16 of that is
···
2516
2510
and execute guest code when KVM_RUN is called.
2517
2511
- KVM_ARM_VCPU_EL1_32BIT: Starts the CPU in a 32bit mode.
2518
2512
Depends on KVM_CAP_ARM_EL1_32BIT (arm64 only).
2519
-
- KVM_ARM_VCPU_PSCI_0_2: Emulate PSCI v0.2 for the CPU.
2513
+
- KVM_ARM_VCPU_PSCI_0_2: Emulate PSCI v0.2 (or a future revision
2514
+
backward compatible with v0.2) for the CPU.
2520
2515
Depends on KVM_CAP_ARM_PSCI_0_2.
2521
2516
- KVM_ARM_VCPU_PMU_V3: Emulate PMUv3 for the CPU.
2522
2517
Depends on KVM_CAP_ARM_PMU_V3.
+30
Documentation/virtual/kvm/arm/psci.txt
+30
Documentation/virtual/kvm/arm/psci.txt
···
1
+
KVM implements the PSCI (Power State Coordination Interface)
2
+
specification in order to provide services such as CPU on/off, reset
3
+
and power-off to the guest.
4
+
5
+
The PSCI specification is regularly updated to provide new features,
6
+
and KVM implements these updates if they make sense from a virtualization
7
+
point of view.
8
+
9
+
This means that a guest booted on two different versions of KVM can
10
+
observe two different "firmware" revisions. This could cause issues if
11
+
a given guest is tied to a particular PSCI revision (unlikely), or if
12
+
a migration causes a different PSCI version to be exposed out of the
13
+
blue to an unsuspecting guest.
14
+
15
+
In order to remedy this situation, KVM exposes a set of "firmware
16
+
pseudo-registers" that can be manipulated using the GET/SET_ONE_REG
17
+
interface. These registers can be saved/restored by userspace, and set
18
+
to a convenient value if required.
19
+
20
+
The following register is defined:
21
+
22
+
* KVM_REG_ARM_PSCI_VERSION:
23
+
24
+
- Only valid if the vcpu has the KVM_ARM_VCPU_PSCI_0_2 feature set
25
+
(and thus has already been initialized)
26
+
- Returns the current PSCI version on GET_ONE_REG (defaulting to the
27
+
highest PSCI version implemented by KVM and compatible with v0.2)
28
+
- Allows any PSCI version implemented by KVM and compatible with
29
+
v0.2 to be set with SET_ONE_REG
30
+
- Affects the whole VM (even if the register view is per-vcpu)
+2
-2
MAINTAINERS
+2
-2
MAINTAINERS
···
7744
7744
F: arch/x86/kvm/svm.c
7745
7745
7746
7746
KERNEL VIRTUAL MACHINE FOR ARM (KVM/arm)
7747
-
M: Christoffer Dall <christoffer.dall@linaro.org>
7747
+
M: Christoffer Dall <christoffer.dall@arm.com>
7748
7748
M: Marc Zyngier <marc.zyngier@arm.com>
7749
7749
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
7750
7750
L: kvmarm@lists.cs.columbia.edu
···
7758
7758
F: include/kvm/arm_*
7759
7759
7760
7760
KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)
7761
-
M: Christoffer Dall <christoffer.dall@linaro.org>
7761
+
M: Christoffer Dall <christoffer.dall@arm.com>
7762
7762
M: Marc Zyngier <marc.zyngier@arm.com>
7763
7763
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
7764
7764
L: kvmarm@lists.cs.columbia.edu
+3
arch/arm/include/asm/kvm_host.h
+3
arch/arm/include/asm/kvm_host.h
+6
arch/arm/include/uapi/asm/kvm.h
+6
arch/arm/include/uapi/asm/kvm.h
···
195
195
#define KVM_REG_ARM_VFP_FPINST 0x1009
196
196
#define KVM_REG_ARM_VFP_FPINST2 0x100A
197
197
198
+
/* KVM-as-firmware specific pseudo-registers */
199
+
#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
200
+
#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM | KVM_REG_SIZE_U64 | \
201
+
KVM_REG_ARM_FW | ((r) & 0xffff))
202
+
#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
203
+
198
204
/* Device Control API: ARM VGIC */
199
205
#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
200
206
#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
+13
arch/arm/kvm/guest.c
+13
arch/arm/kvm/guest.c
···
22
22
#include <linux/module.h>
23
23
#include <linux/vmalloc.h>
24
24
#include <linux/fs.h>
25
+
#include <kvm/arm_psci.h>
25
26
#include <asm/cputype.h>
26
27
#include <linux/uaccess.h>
27
28
#include <asm/kvm.h>
···
177
176
unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
178
177
{
179
178
return num_core_regs() + kvm_arm_num_coproc_regs(vcpu)
179
+
+ kvm_arm_get_fw_num_regs(vcpu)
180
180
+ NUM_TIMER_REGS;
181
181
}
182
182
···
198
196
uindices++;
199
197
}
200
198
199
+
ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices);
200
+
if (ret)
201
+
return ret;
202
+
uindices += kvm_arm_get_fw_num_regs(vcpu);
203
+
201
204
ret = copy_timer_indices(vcpu, uindices);
202
205
if (ret)
203
206
return ret;
···
221
214
if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
222
215
return get_core_reg(vcpu, reg);
223
216
217
+
if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW)
218
+
return kvm_arm_get_fw_reg(vcpu, reg);
219
+
224
220
if (is_timer_reg(reg->id))
225
221
return get_timer_reg(vcpu, reg);
226
222
···
239
229
/* Register group 16 means we set a core register. */
240
230
if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
241
231
return set_core_reg(vcpu, reg);
232
+
233
+
if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW)
234
+
return kvm_arm_set_fw_reg(vcpu, reg);
242
235
243
236
if (is_timer_reg(reg->id))
244
237
return set_timer_reg(vcpu, reg);
+3
arch/arm64/include/asm/kvm_host.h
+3
arch/arm64/include/asm/kvm_host.h
+6
arch/arm64/include/uapi/asm/kvm.h
+6
arch/arm64/include/uapi/asm/kvm.h
···
206
206
#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
207
207
#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
208
208
209
+
/* KVM-as-firmware specific pseudo-registers */
210
+
#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
211
+
#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
212
+
KVM_REG_ARM_FW | ((r) & 0xffff))
213
+
#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
214
+
209
215
/* Device Control API: ARM VGIC */
210
216
#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
211
217
#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
+13
-1
arch/arm64/kvm/guest.c
+13
-1
arch/arm64/kvm/guest.c
···
25
25
#include <linux/module.h>
26
26
#include <linux/vmalloc.h>
27
27
#include <linux/fs.h>
28
+
#include <kvm/arm_psci.h>
28
29
#include <asm/cputype.h>
29
30
#include <linux/uaccess.h>
30
31
#include <asm/kvm.h>
···
206
205
unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
207
206
{
208
207
return num_core_regs() + kvm_arm_num_sys_reg_descs(vcpu)
209
-
+ NUM_TIMER_REGS;
208
+
+ kvm_arm_get_fw_num_regs(vcpu) + NUM_TIMER_REGS;
210
209
}
211
210
212
211
/**
···
226
225
uindices++;
227
226
}
228
227
228
+
ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices);
229
+
if (ret)
230
+
return ret;
231
+
uindices += kvm_arm_get_fw_num_regs(vcpu);
232
+
229
233
ret = copy_timer_indices(vcpu, uindices);
230
234
if (ret)
231
235
return ret;
···
249
243
if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
250
244
return get_core_reg(vcpu, reg);
251
245
246
+
if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW)
247
+
return kvm_arm_get_fw_reg(vcpu, reg);
248
+
252
249
if (is_timer_reg(reg->id))
253
250
return get_timer_reg(vcpu, reg);
254
251
···
267
258
/* Register group 16 means we set a core register. */
268
259
if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
269
260
return set_core_reg(vcpu, reg);
261
+
262
+
if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW)
263
+
return kvm_arm_set_fw_reg(vcpu, reg);
270
264
271
265
if (is_timer_reg(reg->id))
272
266
return set_timer_reg(vcpu, reg);
+2
-4
arch/arm64/kvm/sys_regs.c
+2
-4
arch/arm64/kvm/sys_regs.c
···
996
996
997
997
if (id == SYS_ID_AA64PFR0_EL1) {
998
998
if (val & (0xfUL << ID_AA64PFR0_SVE_SHIFT))
999
-
pr_err_once("kvm [%i]: SVE unsupported for guests, suppressing\n",
1000
-
task_pid_nr(current));
999
+
kvm_debug("SVE unsupported for guests, suppressing\n");
1001
1000
1002
1001
val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
1003
1002
} else if (id == SYS_ID_AA64MMFR1_EL1) {
1004
1003
if (val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))
1005
-
pr_err_once("kvm [%i]: LORegions unsupported for guests, suppressing\n",
1006
-
task_pid_nr(current));
1004
+
kvm_debug("LORegions unsupported for guests, suppressing\n");
1007
1005
1008
1006
val &= ~(0xfUL << ID_AA64MMFR1_LOR_SHIFT);
1009
1007
}
+4
-10
arch/x86/kvm/vmx.c
+4
-10
arch/x86/kvm/vmx.c
···
4544
4544
__vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4545
4545
}
4546
4546
4547
-
static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4548
-
{
4549
-
if (enable_ept)
4550
-
vmx_flush_tlb(vcpu, true);
4551
-
}
4552
-
4553
4547
static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4554
4548
{
4555
4549
ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
···
9272
9278
} else {
9273
9279
sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9274
9280
sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9275
-
vmx_flush_tlb_ept_only(vcpu);
9281
+
vmx_flush_tlb(vcpu, true);
9276
9282
}
9277
9283
vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9278
9284
···
9300
9306
!nested_cpu_has2(get_vmcs12(&vmx->vcpu),
9301
9307
SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9302
9308
vmcs_write64(APIC_ACCESS_ADDR, hpa);
9303
-
vmx_flush_tlb_ept_only(vcpu);
9309
+
vmx_flush_tlb(vcpu, true);
9304
9310
}
9305
9311
}
9306
9312
···
11214
11220
}
11215
11221
} else if (nested_cpu_has2(vmcs12,
11216
11222
SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11217
-
vmx_flush_tlb_ept_only(vcpu);
11223
+
vmx_flush_tlb(vcpu, true);
11218
11224
}
11219
11225
11220
11226
/*
···
12067
12073
} else if (!nested_cpu_has_ept(vmcs12) &&
12068
12074
nested_cpu_has2(vmcs12,
12069
12075
SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
12070
-
vmx_flush_tlb_ept_only(vcpu);
12076
+
vmx_flush_tlb(vcpu, true);
12071
12077
}
12072
12078
12073
12079
/* This is needed for same reason as it was needed in prepare_vmcs02 */
-7
arch/x86/kvm/x86.h
-7
arch/x86/kvm/x86.h
···
302
302
__rem; \
303
303
})
304
304
305
-
#define KVM_X86_DISABLE_EXITS_MWAIT (1 << 0)
306
-
#define KVM_X86_DISABLE_EXITS_HTL (1 << 1)
307
-
#define KVM_X86_DISABLE_EXITS_PAUSE (1 << 2)
308
-
#define KVM_X86_DISABLE_VALID_EXITS (KVM_X86_DISABLE_EXITS_MWAIT | \
309
-
KVM_X86_DISABLE_EXITS_HTL | \
310
-
KVM_X86_DISABLE_EXITS_PAUSE)
311
-
312
305
static inline bool kvm_mwait_in_guest(struct kvm *kvm)
313
306
{
314
307
return kvm->arch.mwait_in_guest;
+14
-2
include/kvm/arm_psci.h
+14
-2
include/kvm/arm_psci.h
···
37
37
* Our PSCI implementation stays the same across versions from
38
38
* v0.2 onward, only adding the few mandatory functions (such
39
39
* as FEATURES with 1.0) that are required by newer
40
-
* revisions. It is thus safe to return the latest.
40
+
* revisions. It is thus safe to return the latest, unless
41
+
* userspace has instructed us otherwise.
41
42
*/
42
-
if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features))
43
+
if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features)) {
44
+
if (vcpu->kvm->arch.psci_version)
45
+
return vcpu->kvm->arch.psci_version;
46
+
43
47
return KVM_ARM_PSCI_LATEST;
48
+
}
44
49
45
50
return KVM_ARM_PSCI_0_1;
46
51
}
47
52
48
53
49
54
int kvm_hvc_call_handler(struct kvm_vcpu *vcpu);
55
+
56
+
struct kvm_one_reg;
57
+
58
+
int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu);
59
+
int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
60
+
int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
61
+
int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
50
62
51
63
#endif /* __KVM_ARM_PSCI_H__ */
+7
include/uapi/linux/kvm.h
+7
include/uapi/linux/kvm.h
···
676
676
__u8 pad[36];
677
677
};
678
678
679
+
#define KVM_X86_DISABLE_EXITS_MWAIT (1 << 0)
680
+
#define KVM_X86_DISABLE_EXITS_HTL (1 << 1)
681
+
#define KVM_X86_DISABLE_EXITS_PAUSE (1 << 2)
682
+
#define KVM_X86_DISABLE_VALID_EXITS (KVM_X86_DISABLE_EXITS_MWAIT | \
683
+
KVM_X86_DISABLE_EXITS_HTL | \
684
+
KVM_X86_DISABLE_EXITS_PAUSE)
685
+
679
686
/* for KVM_ENABLE_CAP */
680
687
struct kvm_enable_cap {
681
688
/* in */
+10
-5
virt/kvm/arm/arm.c
+10
-5
virt/kvm/arm/arm.c
···
63
63
static atomic64_t kvm_vmid_gen = ATOMIC64_INIT(1);
64
64
static u32 kvm_next_vmid;
65
65
static unsigned int kvm_vmid_bits __read_mostly;
66
-
static DEFINE_SPINLOCK(kvm_vmid_lock);
66
+
static DEFINE_RWLOCK(kvm_vmid_lock);
67
67
68
68
static bool vgic_present;
69
69
···
473
473
{
474
474
phys_addr_t pgd_phys;
475
475
u64 vmid;
476
+
bool new_gen;
476
477
477
-
if (!need_new_vmid_gen(kvm))
478
+
read_lock(&kvm_vmid_lock);
479
+
new_gen = need_new_vmid_gen(kvm);
480
+
read_unlock(&kvm_vmid_lock);
481
+
482
+
if (!new_gen)
478
483
return;
479
484
480
-
spin_lock(&kvm_vmid_lock);
485
+
write_lock(&kvm_vmid_lock);
481
486
482
487
/*
483
488
* We need to re-check the vmid_gen here to ensure that if another vcpu
···
490
485
* use the same vmid.
491
486
*/
492
487
if (!need_new_vmid_gen(kvm)) {
493
-
spin_unlock(&kvm_vmid_lock);
488
+
write_unlock(&kvm_vmid_lock);
494
489
return;
495
490
}
496
491
···
524
519
vmid = ((u64)(kvm->arch.vmid) << VTTBR_VMID_SHIFT) & VTTBR_VMID_MASK(kvm_vmid_bits);
525
520
kvm->arch.vttbr = kvm_phys_to_vttbr(pgd_phys) | vmid;
526
521
527
-
spin_unlock(&kvm_vmid_lock);
522
+
write_unlock(&kvm_vmid_lock);
528
523
}
529
524
530
525
static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
+60
virt/kvm/arm/psci.c
+60
virt/kvm/arm/psci.c
···
18
18
#include <linux/arm-smccc.h>
19
19
#include <linux/preempt.h>
20
20
#include <linux/kvm_host.h>
21
+
#include <linux/uaccess.h>
21
22
#include <linux/wait.h>
22
23
23
24
#include <asm/cputype.h>
···
427
426
428
427
smccc_set_retval(vcpu, val, 0, 0, 0);
429
428
return 1;
429
+
}
430
+
431
+
int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu)
432
+
{
433
+
return 1; /* PSCI version */
434
+
}
435
+
436
+
int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
437
+
{
438
+
if (put_user(KVM_REG_ARM_PSCI_VERSION, uindices))
439
+
return -EFAULT;
440
+
441
+
return 0;
442
+
}
443
+
444
+
int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
445
+
{
446
+
if (reg->id == KVM_REG_ARM_PSCI_VERSION) {
447
+
void __user *uaddr = (void __user *)(long)reg->addr;
448
+
u64 val;
449
+
450
+
val = kvm_psci_version(vcpu, vcpu->kvm);
451
+
if (copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)))
452
+
return -EFAULT;
453
+
454
+
return 0;
455
+
}
456
+
457
+
return -EINVAL;
458
+
}
459
+
460
+
int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
461
+
{
462
+
if (reg->id == KVM_REG_ARM_PSCI_VERSION) {
463
+
void __user *uaddr = (void __user *)(long)reg->addr;
464
+
bool wants_02;
465
+
u64 val;
466
+
467
+
if (copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id)))
468
+
return -EFAULT;
469
+
470
+
wants_02 = test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features);
471
+
472
+
switch (val) {
473
+
case KVM_ARM_PSCI_0_1:
474
+
if (wants_02)
475
+
return -EINVAL;
476
+
vcpu->kvm->arch.psci_version = val;
477
+
return 0;
478
+
case KVM_ARM_PSCI_0_2:
479
+
case KVM_ARM_PSCI_1_0:
480
+
if (!wants_02)
481
+
return -EINVAL;
482
+
vcpu->kvm->arch.psci_version = val;
483
+
return 0;
484
+
}
485
+
}
486
+
487
+
return -EINVAL;
430
488
}
+8
virt/kvm/arm/vgic/vgic.c
+8
virt/kvm/arm/vgic/vgic.c
···
600
600
601
601
list_for_each_entry_safe(irq, tmp, &vgic_cpu->ap_list_head, ap_list) {
602
602
struct kvm_vcpu *target_vcpu, *vcpuA, *vcpuB;
603
+
bool target_vcpu_needs_kick = false;
603
604
604
605
spin_lock(&irq->irq_lock);
605
606
···
671
670
list_del(&irq->ap_list);
672
671
irq->vcpu = target_vcpu;
673
672
list_add_tail(&irq->ap_list, &new_cpu->ap_list_head);
673
+
target_vcpu_needs_kick = true;
674
674
}
675
675
676
676
spin_unlock(&irq->irq_lock);
677
677
spin_unlock(&vcpuB->arch.vgic_cpu.ap_list_lock);
678
678
spin_unlock_irqrestore(&vcpuA->arch.vgic_cpu.ap_list_lock, flags);
679
+
680
+
if (target_vcpu_needs_kick) {
681
+
kvm_make_request(KVM_REQ_IRQ_PENDING, target_vcpu);
682
+
kvm_vcpu_kick(target_vcpu);
683
+
}
684
+
679
685
goto retry;
680
686
}
681
687