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net: phy: dp83869: fix setting CLK_O_SEL field.

Table 7-121 in datasheet says we have to set register 0xc6
to value 0x10 before CLK_O_SEL can be modified. No more infos
about this field found in datasheet. With this fix, setting
of CLK_O_SEL field in IO_MUX_CFG register worked through dts
property "ti,clk-output-sel" on a DP83869HMRGZR.

Signed-off-by: Heiko Schocher <hs@nabladev.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Fixes: 01db923e8377 ("net: phy: dp83869: Add TI dp83869 phy")
Link: https://patch.msgid.link/20260425031339.3318-1-hs@nabladev.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

authored by

Heiko Schocher and committed by
Paolo Abeni 46f74a3f 4ca07b92

+12 -1
+12 -1
drivers/net/phy/dp83869.c
··· 31 31 #define DP83869_RGMIICTL 0x0032 32 32 #define DP83869_STRAP_STS1 0x006e 33 33 #define DP83869_RGMIIDCTL 0x0086 34 + #define DP83869_ANA_PLL_PROG_PI 0x00c6 34 35 #define DP83869_RXFCFG 0x0134 35 36 #define DP83869_RXFPMD1 0x0136 36 37 #define DP83869_RXFPMD2 0x0137 ··· 827 826 dp83869_config_port_mirroring(phydev); 828 827 829 828 /* Clock output selection if muxing property is set */ 830 - if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) 829 + if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) { 830 + /* 831 + * Table 7-121 in datasheet says we have to set register 0xc6 832 + * to value 0x10 before CLK_O_SEL can be modified. 833 + */ 834 + ret = phy_write_mmd(phydev, DP83869_DEVADDR, 835 + DP83869_ANA_PLL_PROG_PI, 0x10); 836 + if (ret) 837 + return ret; 838 + 831 839 ret = phy_modify_mmd(phydev, 832 840 DP83869_DEVADDR, DP83869_IO_MUX_CFG, 833 841 DP83869_IO_MUX_CFG_CLK_O_SEL_MASK, 834 842 dp83869->clk_output_sel << 835 843 DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); 844 + } 836 845 837 846 if (phy_interface_is_rgmii(phydev)) { 838 847 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,