Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc:
davinci: DM365 EVM: fix video input mux bits
ARM: davinci: Check for NULL return from irq_alloc_generic_chip
arm: davinci: Fix low level gpio irq handlers' argument
+24
-7
+2
-2
arch/arm/mach-davinci/board-dm365-evm.c
+2
-2
arch/arm/mach-davinci/board-dm365-evm.c
···
520
520
*/
521
521
if (have_imager()) {
522
522
label = "HD imager";
523
-
mux |= 1;
523
+
mux |= 2;
524
524
525
525
/* externally mux MMC1/ENET/AIC33 to imager */
526
526
mux |= BIT(6) | BIT(5) | BIT(3);
···
540
540
resets &= ~BIT(1);
541
541
542
542
if (have_tvp7002()) {
543
-
mux |= 2;
543
+
mux |= 1;
544
544
resets &= ~BIT(2);
545
545
label = "tvp7002 HD";
546
546
} else {
+16
-5
arch/arm/mach-davinci/gpio.c
+16
-5
arch/arm/mach-davinci/gpio.c
···
254
254
{
255
255
struct davinci_gpio_regs __iomem *g;
256
256
u32 mask = 0xffff;
257
+
struct davinci_gpio_controller *d;
257
258
258
-
g = (__force struct davinci_gpio_regs __iomem *) irq_desc_get_handler_data(desc);
259
+
d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
260
+
g = (struct davinci_gpio_regs __iomem *)d->regs;
259
261
260
262
/* we only care about one bank */
261
263
if (irq & 1)
···
276
274
if (!status)
277
275
break;
278
276
__raw_writel(status, &g->intstat);
279
-
if (irq & 1)
280
-
status >>= 16;
281
277
282
278
/* now demux them to the right lowlevel handler */
283
-
n = (int)irq_get_handler_data(irq);
279
+
n = d->irq_base;
280
+
if (irq & 1) {
281
+
n += 16;
282
+
status >>= 16;
283
+
}
284
+
284
285
while (status) {
285
286
res = ffs(status);
286
287
n += res;
···
429
424
430
425
/* set up all irqs in this bank */
431
426
irq_set_chained_handler(bank_irq, gpio_irq_handler);
432
-
irq_set_handler_data(bank_irq, (__force void *)g);
427
+
428
+
/*
429
+
* Each chip handles 32 gpios, and each irq bank consists of 16
430
+
* gpio irqs. Pass the irq bank's corresponding controller to
431
+
* the chained irq handler.
432
+
*/
433
+
irq_set_handler_data(bank_irq, &chips[gpio / 32]);
433
434
434
435
for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
435
436
irq_set_chip(irq, &gpio_irqchip);
+6
arch/arm/mach-davinci/irq.c
+6
arch/arm/mach-davinci/irq.c
···
52
52
struct irq_chip_type *ct;
53
53
54
54
gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
55
+
if (!gc) {
56
+
pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",
57
+
__func__, irq_start);
58
+
return;
59
+
}
60
+
55
61
ct = gc->chip_types;
56
62
ct->chip.irq_ack = irq_gc_ack_set_bit;
57
63
ct->chip.irq_mask = irq_gc_mask_clr_bit;