tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'rproc-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux

Pull remoteproc updates from Bjorn Andersson:

- Transition the i.MX8MP DSP remoteproc driver to use the reset
framework for driving the run/stall reset bits

- Add support for managing the modem remoteprocessor on the Qualcomm
MSM8226, MSM8926, and SM8750 platforms

* tag 'rproc-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (28 commits)
remoteproc: qcom_q6v5_pas: Make single-PD handling more robust
remoteproc: qcom_q6v5_pas: Use resource with CX PD for MSM8226
remoteproc: core: Clear table_sz when rproc_shutdown
remoteproc: sysmon: Update qcom_add_sysmon_subdev() comment
dt-bindings: remoteproc: Consolidate SC8180X and SM8150 PAS files
irqdomain: remoteproc: Switch to of_fwnode_handle()
remoteproc: qcom: pas: add minidump_id to SC7280 WPSS
remoteproc: imx_dsp_rproc: Document run_stall struct member
remoteproc: qcom: pas: Add SM8750 MPSS
dt-bindings: remoteproc: Add SM8750 MPSS
imx_dsp_rproc: Use reset controller API to control the DSP
reset: imx8mp-audiomix: Add support for DSP run/stall
reset: imx8mp-audiomix: Introduce active_low configuration option
reset: imx8mp-audiomix: Prepare the code for more reset bits
reset: imx8mp-audiomix: Add prefix for internal macro
dt-bindings: dsp: fsl,dsp: Add resets property
dt-bindings: reset: audiomix: Add reset ids for EARC and DSP
remoteproc: qcom_wcnss: Handle platforms with only single power domain
dt-bindings: remoteproc: qcom,wcnss-pil: Add support for single power-domain platforms
remoteproc: qcom_q6v5_mss: Add modem support on MSM8926
...

Linus Torvalds 472863ab 7d4eca7a

+500 -166
+23 -1
Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
··· 82 82 description: 83 83 Phandle to syscon block which provide access for processor enablement 84 84 85 + resets: 86 + minItems: 1 87 + 88 + reset-names: 89 + minItems: 1 90 + items: 91 + - const: runstall 92 + - const: softreset 93 + 85 94 required: 86 95 - compatible 87 96 - reg ··· 173 164 - const: txdb1 174 165 - const: rxdb0 175 166 - const: rxdb1 167 + - if: 168 + properties: 169 + compatible: 170 + contains: 171 + enum: 172 + - fsl,imx8mp-dsp 173 + - fsl,imx8mp-hifi4 174 + then: 175 + required: 176 + - resets 177 + - reset-names 176 178 177 179 additionalProperties: false 178 180 ··· 206 186 }; 207 187 - | 208 188 #include <dt-bindings/clock/imx8mp-clock.h> 189 + #include <dt-bindings/reset/imx8mp-reset-audiomix.h> 209 190 dsp_reserved: dsp@92400000 { 210 191 reg = <0x92400000 0x1000000>; 211 192 no-map; ··· 241 220 <&mu2 3 0>; 242 221 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, 243 222 <&dsp_vdev0vring1>, <&dsp_reserved>; 244 - fsl,dsp-ctrl = <&audio_blk_ctrl>; 223 + resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>; 224 + reset-names = "runstall"; 245 225 };
+59 -5
Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml
··· 17 17 compatible: 18 18 oneOf: 19 19 - enum: 20 + - qcom,msm8226-mss-pil 20 21 - qcom,msm8909-mss-pil 21 22 - qcom,msm8916-mss-pil 23 + - qcom,msm8926-mss-pil 22 24 - qcom,msm8953-mss-pil 23 25 - qcom,msm8974-mss-pil 24 26 ··· 72 70 items: 73 71 - description: CX proxy power domain (control handed over after startup) 74 72 - description: MX proxy power domain (control handed over after startup) 73 + (not valid for qcom,msm8226-mss-pil, qcom,msm8926-mss-pil 74 + and qcom,msm8974-mss-pil) 75 75 - description: MSS proxy power domain (control handed over after startup) 76 76 (only valid for qcom,msm8953-mss-pil) 77 - minItems: 2 77 + minItems: 1 78 78 79 79 power-domain-names: 80 80 items: 81 81 - const: cx 82 - - const: mx 82 + - const: mx # not valid for qcom,msm8226-mss-pil, qcom-msm8926-mss-pil and qcom,msm8974-mss-pil 83 83 - const: mss # only valid for qcom,msm8953-mss-pil 84 - minItems: 2 84 + minItems: 1 85 85 86 86 pll-supply: 87 87 description: PLL proxy supply (control handed over after startup) ··· 109 105 description: Names of the states used by the AP to signal the Hexagon core 110 106 items: 111 107 - const: stop 108 + 109 + qcom,ext-bhs-reg: 110 + $ref: /schemas/types.yaml#/definitions/phandle-array 111 + description: External power block headswitch (BHS) register 112 + (only valid for qcom,msm8226-mss-pil) 113 + items: 114 + - items: 115 + - description: phandle to external BHS syscon region 116 + - description: offset to the external BHS register 112 117 113 118 qcom,halt-regs: 114 119 $ref: /schemas/types.yaml#/definitions/phandle-array ··· 220 207 required: 221 208 - power-domains 222 209 - power-domain-names 223 - else: 210 + 211 + - if: 212 + properties: 213 + compatible: 214 + contains: 215 + enum: 216 + - qcom,msm8909-mss-pil 217 + - qcom,msm8916-mss-pil 218 + then: 224 219 properties: 225 220 power-domains: 221 + minItems: 2 226 222 maxItems: 2 227 223 power-domain-names: 224 + minItems: 2 228 225 maxItems: 2 229 226 230 227 - if: 231 228 properties: 232 229 compatible: 233 - const: qcom,msm8974-mss-pil 230 + contains: 231 + enum: 232 + - qcom,msm8226-mss-pil 233 + - qcom,msm8926-mss-pil 234 + - qcom,msm8974-mss-pil 235 + then: 236 + properties: 237 + power-domains: 238 + maxItems: 1 239 + power-domain-names: 240 + maxItems: 1 241 + required: 242 + - mx-supply 243 + 244 + - if: 245 + properties: 246 + compatible: 247 + const: qcom,msm8226-mss-pil 248 + then: 249 + required: 250 + - qcom,ext-bhs-reg 251 + else: 252 + properties: 253 + qcom,ext-bhs-reg: false 254 + 255 + - if: 256 + properties: 257 + compatible: 258 + contains: 259 + enum: 260 + - qcom,msm8926-mss-pil 261 + - qcom,msm8974-mss-pil 234 262 then: 235 263 required: 236 264 - mss-supply
-96
Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml
··· 1 - # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2 - %YAML 1.2 3 - --- 4 - $id: http://devicetree.org/schemas/remoteproc/qcom,sc8180x-pas.yaml# 5 - $schema: http://devicetree.org/meta-schemas/core.yaml# 6 - 7 - title: Qualcomm SC8180X Peripheral Authentication Service 8 - 9 - maintainers: 10 - - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 11 - 12 - description: 13 - Qualcomm SC8180X SoC Peripheral Authentication Service loads and boots 14 - firmware on the Qualcomm DSP Hexagon cores. 15 - 16 - properties: 17 - compatible: 18 - enum: 19 - - qcom,sc8180x-adsp-pas 20 - - qcom,sc8180x-cdsp-pas 21 - - qcom,sc8180x-mpss-pas 22 - 23 - reg: 24 - maxItems: 1 25 - 26 - clocks: 27 - items: 28 - - description: XO clock 29 - 30 - clock-names: 31 - items: 32 - - const: xo 33 - 34 - qcom,qmp: 35 - $ref: /schemas/types.yaml#/definitions/phandle 36 - description: Reference to the AOSS side-channel message RAM. 37 - 38 - smd-edge: false 39 - 40 - memory-region: 41 - maxItems: 1 42 - description: Reference to the reserved-memory for the Hexagon core 43 - 44 - firmware-name: 45 - maxItems: 1 46 - description: Firmware name for the Hexagon core 47 - 48 - required: 49 - - compatible 50 - - reg 51 - - memory-region 52 - 53 - allOf: 54 - - $ref: /schemas/remoteproc/qcom,pas-common.yaml# 55 - - if: 56 - properties: 57 - compatible: 58 - enum: 59 - - qcom,sc8180x-adsp-pas 60 - - qcom,sc8180x-cdsp-pas 61 - then: 62 - properties: 63 - interrupts: 64 - maxItems: 5 65 - interrupt-names: 66 - maxItems: 5 67 - else: 68 - properties: 69 - interrupts: 70 - minItems: 6 71 - interrupt-names: 72 - minItems: 6 73 - 74 - - if: 75 - properties: 76 - compatible: 77 - enum: 78 - - qcom,sc8180x-adsp-pas 79 - - qcom,sc8180x-cdsp-pas 80 - then: 81 - properties: 82 - power-domains: 83 - items: 84 - - description: LCX power domain 85 - - description: LMX power domain 86 - power-domain-names: 87 - items: 88 - - const: lcx 89 - - const: lmx 90 - else: 91 - properties: 92 - # TODO: incomplete 93 - power-domains: false 94 - power-domain-names: false 95 - 96 - unevaluatedProperties: false
+1 -1
Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml
··· 127 127 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 128 128 clock-names = "xo"; 129 129 130 - firmware-name = "qcom/sm6115/adsp.mdt"; 130 + firmware-name = "qcom/sm6115/adsp.mbn"; 131 131 132 132 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 133 133 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+7
Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml
··· 60 60 properties: 61 61 compatible: 62 62 enum: 63 + - qcom,sc8180x-adsp-pas 64 + - qcom,sc8180x-cdsp-pas 65 + - qcom,sc8180x-slpi-pas 63 66 - qcom,sm8150-adsp-pas 64 67 - qcom,sm8150-cdsp-pas 65 68 - qcom,sm8150-slpi-pas ··· 86 83 properties: 87 84 compatible: 88 85 enum: 86 + - qcom,sc8180x-adsp-pas 87 + - qcom,sc8180x-cdsp-pas 89 88 - qcom,sm8150-adsp-pas 90 89 - qcom,sm8150-cdsp-pas 91 90 - qcom,sm8250-cdsp-pas ··· 104 99 properties: 105 100 compatible: 106 101 enum: 102 + - qcom,sc8180x-mpss-pas 107 103 - qcom,sm8150-mpss-pas 108 104 then: 109 105 properties: ··· 121 115 properties: 122 116 compatible: 123 117 enum: 118 + - qcom,sc8180x-slpi-pas 124 119 - qcom,sm8150-slpi-pas 125 120 - qcom,sm8250-adsp-pas 126 121 - qcom,sm8250-slpi-pas
+42 -4
Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
··· 24 24 - qcom,sm8650-adsp-pas 25 25 - qcom,sm8650-cdsp-pas 26 26 - qcom,sm8650-mpss-pas 27 + - qcom,sm8750-mpss-pas 27 28 - qcom,x1e80100-adsp-pas 28 29 - qcom,x1e80100-cdsp-pas 29 30 - items: 30 31 - const: qcom,sm8750-adsp-pas 31 32 - const: qcom,sm8550-adsp-pas 33 + - items: 34 + - const: qcom,sm8750-cdsp-pas 35 + - const: qcom,sm8650-cdsp-pas 32 36 33 37 reg: 34 38 maxItems: 1 ··· 118 114 memory-region: 119 115 minItems: 3 120 116 maxItems: 3 117 + 118 + - if: 119 + properties: 120 + compatible: 121 + contains: 122 + enum: 123 + - qcom,sm8750-cdsp-pas 124 + then: 125 + properties: 126 + interrupts: 127 + maxItems: 6 128 + interrupt-names: 129 + maxItems: 6 130 + memory-region: 131 + minItems: 3 132 + maxItems: 3 133 + 121 134 - if: 122 135 properties: 123 136 compatible: ··· 168 147 - if: 169 148 properties: 170 149 compatible: 150 + enum: 151 + - qcom,sm8750-mpss-pas 152 + then: 153 + properties: 154 + interrupts: 155 + minItems: 6 156 + interrupt-names: 157 + minItems: 6 158 + memory-region: 159 + minItems: 4 160 + maxItems: 4 161 + 162 + - if: 163 + properties: 164 + compatible: 171 165 contains: 172 166 enum: 173 167 - qcom,sm8550-adsp-pas ··· 207 171 - qcom,sdx75-mpss-pas 208 172 - qcom,sm8550-mpss-pas 209 173 - qcom,sm8650-mpss-pas 174 + - qcom,sm8750-mpss-pas 210 175 then: 211 176 properties: 212 177 power-domains: ··· 221 184 - if: 222 185 properties: 223 186 compatible: 224 - enum: 225 - - qcom,sm8550-cdsp-pas 226 - - qcom,sm8650-cdsp-pas 227 - - qcom,x1e80100-cdsp-pas 187 + contains: 188 + enum: 189 + - qcom,sm8550-cdsp-pas 190 + - qcom,sm8650-cdsp-pas 191 + - qcom,x1e80100-cdsp-pas 228 192 then: 229 193 properties: 230 194 power-domains:
+36 -9
Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml
··· 69 69 CX regulator to be held on behalf of the booting of the WCNSS core. 70 70 71 71 power-domains: 72 + minItems: 1 72 73 maxItems: 2 73 74 74 75 power-domain-names: 76 + minItems: 1 75 77 items: 76 78 - const: cx 77 79 - const: mx ··· 189 187 - qcom,pronto-v1-pil 190 188 - qcom,pronto-v2-pil 191 189 then: 192 - properties: 193 - vddmx-supply: 194 - deprecated: true 195 - description: Deprecated for qcom,pronto-v1/2-pil 196 - 197 - vddcx-supply: 198 - deprecated: true 199 - description: Deprecated for qcom,pronto-v1/2-pil 200 - 190 + # CX and MX must be present either as power domains or regulators 201 191 oneOf: 192 + # Both CX and MX represented as power domains 202 193 - required: 203 194 - power-domains 204 195 - power-domain-names 196 + properties: 197 + power-domains: 198 + minItems: 2 199 + power-domain-names: 200 + minItems: 2 201 + vddmx-supply: false 202 + vddcx-supply: false 203 + # CX represented as power domain, MX as regulator 204 + - required: 205 + - power-domains 206 + - power-domain-names 207 + - vddmx-supply 208 + properties: 209 + power-domains: 210 + maxItems: 1 211 + power-domain-names: 212 + maxItems: 1 213 + vddcx-supply: false 214 + # Both CX and MX represented as regulators 205 215 - required: 206 216 - vddmx-supply 207 217 - vddcx-supply 218 + properties: 219 + power-domains: false 220 + power-domain-names: false 221 + vddmx-supply: 222 + deprecated: true 223 + description: Deprecated for qcom,pronto-v1/2-pil 224 + vddcx-supply: 225 + deprecated: true 226 + description: Deprecated for qcom,pronto-v1/2-pil 208 227 209 228 - if: 210 229 properties: ··· 235 212 - qcom,pronto-v3-pil 236 213 then: 237 214 properties: 215 + power-domains: 216 + minItems: 2 217 + power-domain-names: 218 + minItems: 2 238 219 vddmx-supply: false 239 220 vddcx-supply: false 240 221
+18 -8
drivers/remoteproc/imx_dsp_rproc.c
··· 19 19 #include <linux/pm_runtime.h> 20 20 #include <linux/regmap.h> 21 21 #include <linux/remoteproc.h> 22 + #include <linux/reset.h> 22 23 #include <linux/slab.h> 23 24 24 25 #include "imx_rproc.h" ··· 96 95 /** 97 96 * struct imx_dsp_rproc - DSP remote processor state 98 97 * @regmap: regmap handler 98 + * @run_stall: reset control handle used for Run/Stall operation 99 99 * @rproc: rproc handler 100 100 * @dsp_dcfg: device configuration pointer 101 101 * @clks: clocks needed by this device ··· 113 111 */ 114 112 struct imx_dsp_rproc { 115 113 struct regmap *regmap; 114 + struct reset_control *run_stall; 116 115 struct rproc *rproc; 117 116 const struct imx_dsp_rproc_dcfg *dsp_dcfg; 118 117 struct clk_bulk_data clks[DSP_RPROC_CLK_MAX]; ··· 195 192 /* Keep reset asserted for 10 cycles */ 196 193 usleep_range(1, 2); 197 194 198 - regmap_update_bits(priv->regmap, IMX8M_AudioDSP_REG2, 199 - IMX8M_AudioDSP_REG2_RUNSTALL, 200 - IMX8M_AudioDSP_REG2_RUNSTALL); 195 + reset_control_assert(priv->run_stall); 201 196 202 197 /* Take the DSP out of reset and keep stalled for FW loading */ 203 198 pwrctl = readl(dap + IMX8M_DAP_PWRCTL); ··· 232 231 233 232 /* Specific configuration for i.MX8MP */ 234 233 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8mp = { 235 - .src_reg = IMX8M_AudioDSP_REG2, 236 - .src_mask = IMX8M_AudioDSP_REG2_RUNSTALL, 237 - .src_start = 0, 238 - .src_stop = IMX8M_AudioDSP_REG2_RUNSTALL, 239 234 .att = imx_dsp_rproc_att_imx8mp, 240 235 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8mp), 241 - .method = IMX_RPROC_MMIO, 236 + .method = IMX_RPROC_RESET_CONTROLLER, 242 237 }; 243 238 244 239 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8mp = { ··· 326 329 true, 327 330 rproc->bootaddr); 328 331 break; 332 + case IMX_RPROC_RESET_CONTROLLER: 333 + ret = reset_control_deassert(priv->run_stall); 334 + break; 329 335 default: 330 336 return -EOPNOTSUPP; 331 337 } ··· 368 368 IMX_SC_R_DSP, 369 369 false, 370 370 rproc->bootaddr); 371 + break; 372 + case IMX_RPROC_RESET_CONTROLLER: 373 + ret = reset_control_assert(priv->run_stall); 371 374 break; 372 375 default: 373 376 return -EOPNOTSUPP; ··· 997 994 } 998 995 999 996 priv->regmap = regmap; 997 + break; 998 + case IMX_RPROC_RESET_CONTROLLER: 999 + priv->run_stall = devm_reset_control_get_exclusive(dev, "runstall"); 1000 + if (IS_ERR(priv->run_stall)) { 1001 + dev_err(dev, "Failed to get DSP runstall reset control\n"); 1002 + return PTR_ERR(priv->run_stall); 1003 + } 1000 1004 break; 1001 1005 default: 1002 1006 ret = -EOPNOTSUPP;
+2
drivers/remoteproc/imx_rproc.h
··· 24 24 IMX_RPROC_SMC, 25 25 /* Through System Control Unit API */ 26 26 IMX_RPROC_SCU_API, 27 + /* Through Reset Controller API */ 28 + IMX_RPROC_RESET_CONTROLLER, 27 29 }; 28 30 29 31 /* dcfg flags */
+1
drivers/remoteproc/omap_remoteproc.c
··· 724 724 * @rproc: remote processor to apply the address translation for 725 725 * @da: device address to translate 726 726 * @len: length of the memory buffer 727 + * @is_iomem: pointer filled in to indicate if @da is iomapped memory 727 728 * 728 729 * Custom function implementing the rproc .da_to_va ops to provide address 729 730 * translation (device address to kernel virtual address) for internal RAMs
+1 -1
drivers/remoteproc/pru_rproc.c
··· 563 563 return -ENODEV; 564 564 } 565 565 566 - fwspec.fwnode = of_node_to_fwnode(irq_parent); 566 + fwspec.fwnode = of_fwnode_handle(irq_parent); 567 567 fwspec.param_count = 3; 568 568 for (i = 0; i < pru->evt_count; i++) { 569 569 fwspec.param[0] = rsc->pru_intc_map[i].event;
+181 -5
drivers/remoteproc/qcom_q6v5_mss.c
··· 134 134 #define BOOT_FSM_TIMEOUT 10000 135 135 #define BHS_CHECK_MAX_LOOPS 200 136 136 137 + /* External power block headswitch */ 138 + #define EXTERNAL_BHS_ON BIT(0) 139 + #define EXTERNAL_BHS_STATUS BIT(4) 140 + #define EXTERNAL_BHS_TIMEOUT_US 50 141 + 137 142 struct reg_info { 138 143 struct regulator *reg; 139 144 int uV; ··· 166 161 bool has_mba_logs; 167 162 bool has_spare_reg; 168 163 bool has_qaccept_regs; 164 + bool has_ext_bhs_reg; 169 165 bool has_ext_cntl_regs; 170 166 bool has_vq6; 171 167 }; ··· 186 180 u32 halt_nc; 187 181 u32 halt_vq6; 188 182 u32 conn_box; 183 + u32 ext_bhs; 189 184 190 185 u32 qaccept_mdm; 191 186 u32 qaccept_cx; ··· 244 237 bool has_mba_logs; 245 238 bool has_spare_reg; 246 239 bool has_qaccept_regs; 240 + bool has_ext_bhs_reg; 247 241 bool has_ext_cntl_regs; 248 242 bool has_vq6; 249 243 u64 mpss_perm; ··· 254 246 }; 255 247 256 248 enum { 249 + MSS_MSM8226, 257 250 MSS_MSM8909, 258 251 MSS_MSM8916, 252 + MSS_MSM8926, 259 253 MSS_MSM8953, 260 254 MSS_MSM8974, 261 255 MSS_MSM8996, ··· 423 413 dev_pm_genpd_set_performance_state(pds[i], 0); 424 414 pm_runtime_put(pds[i]); 425 415 } 416 + } 417 + 418 + static int q6v5_external_bhs_enable(struct q6v5 *qproc) 419 + { 420 + u32 val; 421 + int ret = 0; 422 + 423 + /* 424 + * Enable external power block headswitch and wait for it to 425 + * stabilize 426 + */ 427 + regmap_set_bits(qproc->conn_map, qproc->ext_bhs, EXTERNAL_BHS_ON); 428 + 429 + ret = regmap_read_poll_timeout(qproc->conn_map, qproc->ext_bhs, 430 + val, val & EXTERNAL_BHS_STATUS, 431 + 1, EXTERNAL_BHS_TIMEOUT_US); 432 + 433 + if (ret) { 434 + dev_err(qproc->dev, "External BHS timed out\n"); 435 + ret = -ETIMEDOUT; 436 + } 437 + 438 + return ret; 439 + } 440 + 441 + static void q6v5_external_bhs_disable(struct q6v5 *qproc) 442 + { 443 + regmap_clear_bits(qproc->conn_map, qproc->ext_bhs, EXTERNAL_BHS_ON); 426 444 } 427 445 428 446 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, u64 *current_perm, ··· 1150 1112 goto disable_proxy_clk; 1151 1113 } 1152 1114 1115 + if (qproc->has_ext_bhs_reg) { 1116 + ret = q6v5_external_bhs_enable(qproc); 1117 + if (ret < 0) 1118 + goto disable_vdd; 1119 + } 1120 + 1153 1121 ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks, 1154 1122 qproc->reset_clk_count); 1155 1123 if (ret) { 1156 1124 dev_err(qproc->dev, "failed to enable reset clocks\n"); 1157 - goto disable_vdd; 1125 + goto disable_ext_bhs; 1158 1126 } 1159 1127 1160 1128 ret = q6v5_reset_deassert(qproc); ··· 1258 1214 disable_reset_clks: 1259 1215 q6v5_clk_disable(qproc->dev, qproc->reset_clks, 1260 1216 qproc->reset_clk_count); 1217 + disable_ext_bhs: 1218 + if (qproc->has_ext_bhs_reg) 1219 + q6v5_external_bhs_disable(qproc); 1261 1220 disable_vdd: 1262 1221 q6v5_regulator_disable(qproc, qproc->active_regs, 1263 1222 qproc->active_reg_count); ··· 1328 1281 qproc->reset_clk_count); 1329 1282 q6v5_clk_disable(qproc->dev, qproc->active_clks, 1330 1283 qproc->active_clk_count); 1284 + if (qproc->has_ext_bhs_reg) 1285 + q6v5_external_bhs_disable(qproc); 1331 1286 q6v5_regulator_disable(qproc, qproc->active_regs, 1332 1287 qproc->active_reg_count); 1333 1288 ··· 1799 1750 qproc->qaccept_axi = args.args[2]; 1800 1751 } 1801 1752 1753 + if (qproc->has_ext_bhs_reg) { 1754 + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, 1755 + "qcom,ext-bhs-reg", 1756 + 1, 0, &args); 1757 + if (ret < 0) { 1758 + dev_err(&pdev->dev, "failed to parse ext-bhs-reg index 0\n"); 1759 + return -EINVAL; 1760 + } 1761 + 1762 + qproc->conn_map = syscon_node_to_regmap(args.np); 1763 + of_node_put(args.np); 1764 + if (IS_ERR(qproc->conn_map)) 1765 + return PTR_ERR(qproc->conn_map); 1766 + 1767 + qproc->ext_bhs = args.args[0]; 1768 + } 1769 + 1802 1770 if (qproc->has_ext_cntl_regs) { 1803 1771 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, 1804 1772 "qcom,ext-regs", ··· 1897 1831 while (pd_names[num_pds]) 1898 1832 num_pds++; 1899 1833 1834 + /* Handle single power domain */ 1835 + if (num_pds == 1 && dev->pm_domain) { 1836 + devs[0] = dev; 1837 + pm_runtime_enable(dev); 1838 + return 1; 1839 + } 1840 + 1900 1841 for (i = 0; i < num_pds; i++) { 1901 1842 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); 1902 1843 if (IS_ERR_OR_NULL(devs[i])) { ··· 1924 1851 static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds, 1925 1852 size_t pd_count) 1926 1853 { 1854 + struct device *dev = qproc->dev; 1927 1855 int i; 1856 + 1857 + /* Handle single power domain */ 1858 + if (pd_count == 1 && dev->pm_domain) { 1859 + pm_runtime_disable(dev); 1860 + return; 1861 + } 1928 1862 1929 1863 for (i = 0; i < pd_count; i++) 1930 1864 dev_pm_domain_detach(pds[i], false); ··· 2087 2007 platform_set_drvdata(pdev, qproc); 2088 2008 2089 2009 qproc->has_qaccept_regs = desc->has_qaccept_regs; 2010 + qproc->has_ext_bhs_reg = desc->has_ext_bhs_reg; 2090 2011 qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs; 2091 2012 qproc->has_vq6 = desc->has_vq6; 2092 2013 qproc->has_spare_reg = desc->has_spare_reg; ··· 2241 2160 .has_mba_logs = true, 2242 2161 .has_spare_reg = true, 2243 2162 .has_qaccept_regs = false, 2163 + .has_ext_bhs_reg = false, 2244 2164 .has_ext_cntl_regs = false, 2245 2165 .has_vq6 = false, 2246 2166 .version = MSS_SC7180, ··· 2270 2188 .has_mba_logs = true, 2271 2189 .has_spare_reg = false, 2272 2190 .has_qaccept_regs = true, 2191 + .has_ext_bhs_reg = false, 2273 2192 .has_ext_cntl_regs = true, 2274 2193 .has_vq6 = true, 2275 2194 .version = MSS_SC7280, ··· 2302 2219 .has_mba_logs = false, 2303 2220 .has_spare_reg = false, 2304 2221 .has_qaccept_regs = false, 2222 + .has_ext_bhs_reg = false, 2305 2223 .has_ext_cntl_regs = false, 2306 2224 .has_vq6 = false, 2307 2225 .version = MSS_SDM660, ··· 2338 2254 .has_mba_logs = false, 2339 2255 .has_spare_reg = false, 2340 2256 .has_qaccept_regs = false, 2257 + .has_ext_bhs_reg = false, 2341 2258 .has_ext_cntl_regs = false, 2342 2259 .has_vq6 = false, 2343 2260 .version = MSS_SDM845, ··· 2370 2285 .has_mba_logs = false, 2371 2286 .has_spare_reg = false, 2372 2287 .has_qaccept_regs = false, 2288 + .has_ext_bhs_reg = false, 2373 2289 .has_ext_cntl_regs = false, 2374 2290 .has_vq6 = false, 2375 2291 .version = MSS_MSM8998, ··· 2409 2323 .has_mba_logs = false, 2410 2324 .has_spare_reg = false, 2411 2325 .has_qaccept_regs = false, 2326 + .has_ext_bhs_reg = false, 2412 2327 .has_ext_cntl_regs = false, 2413 2328 .has_vq6 = false, 2414 2329 .version = MSS_MSM8996, ··· 2444 2357 .has_mba_logs = false, 2445 2358 .has_spare_reg = false, 2446 2359 .has_qaccept_regs = false, 2360 + .has_ext_bhs_reg = false, 2447 2361 .has_ext_cntl_regs = false, 2448 2362 .has_vq6 = false, 2449 2363 .version = MSS_MSM8909, ··· 2490 2402 .has_mba_logs = false, 2491 2403 .has_spare_reg = false, 2492 2404 .has_qaccept_regs = false, 2405 + .has_ext_bhs_reg = false, 2493 2406 .has_ext_cntl_regs = false, 2494 2407 .has_vq6 = false, 2495 2408 .version = MSS_MSM8916, ··· 2526 2437 .has_mba_logs = false, 2527 2438 .has_spare_reg = false, 2528 2439 .has_qaccept_regs = false, 2440 + .has_ext_bhs_reg = false, 2529 2441 .has_ext_cntl_regs = false, 2530 2442 .has_vq6 = false, 2531 2443 .version = MSS_MSM8953, ··· 2539 2449 .supply = "pll", 2540 2450 .uA = 100000, 2541 2451 }, 2542 - {} 2543 - }, 2544 - .fallback_proxy_supply = (struct qcom_mss_reg_res[]) { 2545 2452 { 2546 2453 .supply = "mx", 2547 2454 .uV = 1050000, 2548 2455 }, 2456 + {} 2457 + }, 2458 + .fallback_proxy_supply = (struct qcom_mss_reg_res[]) { 2549 2459 { 2550 2460 .supply = "cx", 2551 2461 .uA = 100000, ··· 2571 2481 NULL 2572 2482 }, 2573 2483 .proxy_pd_names = (char*[]){ 2574 - "mx", 2575 2484 "cx", 2576 2485 NULL 2577 2486 }, ··· 2579 2490 .has_mba_logs = false, 2580 2491 .has_spare_reg = false, 2581 2492 .has_qaccept_regs = false, 2493 + .has_ext_bhs_reg = false, 2582 2494 .has_ext_cntl_regs = false, 2583 2495 .has_vq6 = false, 2584 2496 .version = MSS_MSM8974, 2585 2497 }; 2586 2498 2499 + static const struct rproc_hexagon_res msm8226_mss = { 2500 + .hexagon_mba_image = "mba.b00", 2501 + .proxy_supply = (struct qcom_mss_reg_res[]) { 2502 + { 2503 + .supply = "pll", 2504 + .uA = 100000, 2505 + }, 2506 + { 2507 + .supply = "mx", 2508 + .uV = 1050000, 2509 + }, 2510 + {} 2511 + }, 2512 + .proxy_clk_names = (char*[]){ 2513 + "xo", 2514 + NULL 2515 + }, 2516 + .active_clk_names = (char*[]){ 2517 + "iface", 2518 + "bus", 2519 + "mem", 2520 + NULL 2521 + }, 2522 + .proxy_pd_names = (char*[]){ 2523 + "cx", 2524 + NULL 2525 + }, 2526 + .need_mem_protection = false, 2527 + .has_alt_reset = false, 2528 + .has_mba_logs = false, 2529 + .has_spare_reg = false, 2530 + .has_qaccept_regs = false, 2531 + .has_ext_bhs_reg = true, 2532 + .has_ext_cntl_regs = false, 2533 + .has_vq6 = false, 2534 + .version = MSS_MSM8226, 2535 + }; 2536 + 2537 + static const struct rproc_hexagon_res msm8926_mss = { 2538 + .hexagon_mba_image = "mba.b00", 2539 + .proxy_supply = (struct qcom_mss_reg_res[]) { 2540 + { 2541 + .supply = "pll", 2542 + .uA = 100000, 2543 + }, 2544 + { 2545 + .supply = "mx", 2546 + .uV = 1050000, 2547 + }, 2548 + {} 2549 + }, 2550 + .active_supply = (struct qcom_mss_reg_res[]) { 2551 + { 2552 + .supply = "mss", 2553 + .uV = 1050000, 2554 + .uA = 100000, 2555 + }, 2556 + {} 2557 + }, 2558 + .proxy_clk_names = (char*[]){ 2559 + "xo", 2560 + NULL 2561 + }, 2562 + .active_clk_names = (char*[]){ 2563 + "iface", 2564 + "bus", 2565 + "mem", 2566 + NULL 2567 + }, 2568 + .proxy_pd_names = (char*[]){ 2569 + "cx", 2570 + NULL 2571 + }, 2572 + .need_mem_protection = false, 2573 + .has_alt_reset = false, 2574 + .has_mba_logs = false, 2575 + .has_spare_reg = false, 2576 + .has_qaccept_regs = false, 2577 + .has_ext_bhs_reg = false, 2578 + .has_ext_cntl_regs = false, 2579 + .has_vq6 = false, 2580 + .version = MSS_MSM8926, 2581 + }; 2582 + 2587 2583 static const struct of_device_id q6v5_of_match[] = { 2588 2584 { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss}, 2585 + { .compatible = "qcom,msm8226-mss-pil", .data = &msm8226_mss}, 2589 2586 { .compatible = "qcom,msm8909-mss-pil", .data = &msm8909_mss}, 2590 2587 { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss}, 2588 + { .compatible = "qcom,msm8926-mss-pil", .data = &msm8926_mss}, 2591 2589 { .compatible = "qcom,msm8953-mss-pil", .data = &msm8953_mss}, 2592 2590 { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss}, 2593 2591 { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
+32 -6
drivers/remoteproc/qcom_q6v5_pas.c
··· 501 501 if (!pd_names) 502 502 return 0; 503 503 504 + while (pd_names[num_pds]) 505 + num_pds++; 506 + 504 507 /* Handle single power domain */ 505 - if (dev->pm_domain) { 508 + if (num_pds == 1 && dev->pm_domain) { 506 509 devs[0] = dev; 507 510 pm_runtime_enable(dev); 508 511 return 1; 509 512 } 510 - 511 - while (pd_names[num_pds]) 512 - num_pds++; 513 513 514 514 for (i = 0; i < num_pds; i++) { 515 515 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); ··· 535 535 int i; 536 536 537 537 /* Handle single power domain */ 538 - if (dev->pm_domain && pd_count) { 538 + if (pd_count == 1 && dev->pm_domain) { 539 539 pm_runtime_disable(dev); 540 540 return; 541 541 } ··· 1348 1348 .crash_reason_smem = 626, 1349 1349 .firmware_name = "wpss.mdt", 1350 1350 .pas_id = 6, 1351 + .minidump_id = 4, 1351 1352 .auto_boot = false, 1352 1353 .proxy_pd_names = (char*[]){ 1353 1354 "cx", ··· 1410 1409 .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA, 1411 1410 }; 1412 1411 1412 + static const struct adsp_data sm8750_mpss_resource = { 1413 + .crash_reason_smem = 421, 1414 + .firmware_name = "modem.mdt", 1415 + .dtb_firmware_name = "modem_dtb.mdt", 1416 + .pas_id = 4, 1417 + .dtb_pas_id = 0x26, 1418 + .minidump_id = 3, 1419 + .auto_boot = false, 1420 + .decrypt_shutdown = true, 1421 + .proxy_pd_names = (char*[]){ 1422 + "cx", 1423 + "mss", 1424 + NULL 1425 + }, 1426 + .load_state = "modem", 1427 + .ssr_name = "mpss", 1428 + .sysmon_name = "modem", 1429 + .ssctl_id = 0x12, 1430 + .smem_host_id = 1, 1431 + .region_assign_idx = 2, 1432 + .region_assign_count = 2, 1433 + .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA, 1434 + }; 1435 + 1413 1436 static const struct of_device_id adsp_of_match[] = { 1414 - { .compatible = "qcom,msm8226-adsp-pil", .data = &adsp_resource_init}, 1437 + { .compatible = "qcom,msm8226-adsp-pil", .data = &msm8996_adsp_resource}, 1415 1438 { .compatible = "qcom,msm8953-adsp-pil", .data = &msm8996_adsp_resource}, 1416 1439 { .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init}, 1417 1440 { .compatible = "qcom,msm8996-adsp-pil", .data = &msm8996_adsp_resource}, ··· 1499 1474 { .compatible = "qcom,sm8650-adsp-pas", .data = &sm8550_adsp_resource}, 1500 1475 { .compatible = "qcom,sm8650-cdsp-pas", .data = &sm8650_cdsp_resource}, 1501 1476 { .compatible = "qcom,sm8650-mpss-pas", .data = &sm8650_mpss_resource}, 1477 + { .compatible = "qcom,sm8750-mpss-pas", .data = &sm8750_mpss_resource}, 1502 1478 { .compatible = "qcom,x1e80100-adsp-pas", .data = &x1e80100_adsp_resource}, 1503 1479 { .compatible = "qcom,x1e80100-cdsp-pas", .data = &x1e80100_cdsp_resource}, 1504 1480 { },
+1 -1
drivers/remoteproc/qcom_sysmon.c
··· 619 619 * @name: name of this subdev, to use in SSR 620 620 * @ssctl_instance: instance id of the ssctl QMI service 621 621 * 622 - * Return: A new qcom_sysmon object, or NULL on failure 622 + * Return: A new qcom_sysmon object, or an error pointer on failure 623 623 */ 624 624 struct qcom_sysmon *qcom_add_sysmon_subdev(struct rproc *rproc, 625 625 const char *name,
+26 -7
drivers/remoteproc/qcom_wcnss.c
··· 117 117 .pmu_offset = 0x1004, 118 118 .spare_offset = 0x1088, 119 119 120 - .pd_names = { "mx", "cx" }, 120 + .pd_names = { "cx", "mx" }, 121 121 .vregs = (struct wcnss_vreg_info[]) { 122 - { "vddmx", 950000, 1150000, 0 }, 123 122 { "vddcx", .super_turbo = true}, 123 + { "vddmx", 950000, 1150000, 0 }, 124 124 { "vddpx", 1800000, 1800000, 0 }, 125 125 }, 126 126 .num_pd_vregs = 2, ··· 131 131 .pmu_offset = 0x1004, 132 132 .spare_offset = 0x1088, 133 133 134 - .pd_names = { "mx", "cx" }, 134 + .pd_names = { "cx", "mx" }, 135 135 .vregs = (struct wcnss_vreg_info[]) { 136 - { "vddmx", 1287500, 1287500, 0 }, 137 136 { "vddcx", .super_turbo = true }, 137 + { "vddmx", 1287500, 1287500, 0 }, 138 138 { "vddpx", 1800000, 1800000, 0 }, 139 139 }, 140 140 .num_pd_vregs = 2, ··· 397 397 static int wcnss_init_pds(struct qcom_wcnss *wcnss, 398 398 const char * const pd_names[WCNSS_MAX_PDS]) 399 399 { 400 + struct device *dev = wcnss->dev; 400 401 int i, ret; 402 + 403 + /* Handle single power domain */ 404 + if (dev->pm_domain) { 405 + wcnss->pds[0] = dev; 406 + wcnss->num_pds = 1; 407 + pm_runtime_enable(dev); 408 + return 0; 409 + } 401 410 402 411 for (i = 0; i < WCNSS_MAX_PDS; i++) { 403 412 if (!pd_names[i]) ··· 427 418 428 419 static void wcnss_release_pds(struct qcom_wcnss *wcnss) 429 420 { 421 + struct device *dev = wcnss->dev; 430 422 int i; 423 + 424 + /* Handle single power domain */ 425 + if (wcnss->num_pds == 1 && dev->pm_domain) { 426 + pm_runtime_disable(dev); 427 + return; 428 + } 431 429 432 430 for (i = 0; i < wcnss->num_pds; i++) 433 431 dev_pm_domain_detach(wcnss->pds[i], false); ··· 453 437 * the regulators for the power domains. For old device trees we need to 454 438 * reserve extra space to manage them through the regulator interface. 455 439 */ 456 - if (wcnss->num_pds) 457 - info += num_pd_vregs; 458 - else 440 + if (wcnss->num_pds) { 441 + info += wcnss->num_pds; 442 + /* Handle single power domain case */ 443 + num_vregs += num_pd_vregs - wcnss->num_pds; 444 + } else { 459 445 num_vregs += num_pd_vregs; 446 + } 460 447 461 448 bulk = devm_kcalloc(wcnss->dev, 462 449 num_vregs, sizeof(struct regulator_bulk_data),
+1
drivers/remoteproc/remoteproc_core.c
··· 2025 2025 kfree(rproc->cached_table); 2026 2026 rproc->cached_table = NULL; 2027 2027 rproc->table_ptr = NULL; 2028 + rproc->table_sz = 0; 2028 2029 out: 2029 2030 mutex_unlock(&rproc->lock); 2030 2031 return ret;
+56 -22
drivers/reset/reset-imx8mp-audiomix.c
··· 3 3 * Copyright 2024 NXP 4 4 */ 5 5 6 + #include <dt-bindings/reset/imx8mp-reset-audiomix.h> 7 + 6 8 #include <linux/auxiliary_bus.h> 7 9 #include <linux/device.h> 8 10 #include <linux/io.h> ··· 13 11 #include <linux/of_address.h> 14 12 #include <linux/reset-controller.h> 15 13 16 - #define EARC 0x200 17 - #define EARC_RESET_MASK 0x3 14 + #define IMX8MP_AUDIOMIX_EARC_RESET_OFFSET 0x200 15 + #define IMX8MP_AUDIOMIX_EARC_RESET_MASK BIT(1) 16 + #define IMX8MP_AUDIOMIX_EARC_PHY_RESET_MASK BIT(2) 17 + 18 + #define IMX8MP_AUDIOMIX_DSP_RUNSTALL_OFFSET 0x108 19 + #define IMX8MP_AUDIOMIX_DSP_RUNSTALL_MASK BIT(5) 20 + 21 + struct imx8mp_reset_map { 22 + unsigned int offset; 23 + unsigned int mask; 24 + bool active_low; 25 + }; 26 + 27 + static const struct imx8mp_reset_map reset_map[] = { 28 + [IMX8MP_AUDIOMIX_EARC_RESET] = { 29 + .offset = IMX8MP_AUDIOMIX_EARC_RESET_OFFSET, 30 + .mask = IMX8MP_AUDIOMIX_EARC_RESET_MASK, 31 + .active_low = true, 32 + }, 33 + [IMX8MP_AUDIOMIX_EARC_PHY_RESET] = { 34 + .offset = IMX8MP_AUDIOMIX_EARC_RESET_OFFSET, 35 + .mask = IMX8MP_AUDIOMIX_EARC_PHY_RESET_MASK, 36 + .active_low = true, 37 + }, 38 + [IMX8MP_AUDIOMIX_DSP_RUNSTALL] = { 39 + .offset = IMX8MP_AUDIOMIX_DSP_RUNSTALL_OFFSET, 40 + .mask = IMX8MP_AUDIOMIX_DSP_RUNSTALL_MASK, 41 + .active_low = false, 42 + }, 43 + }; 18 44 19 45 struct imx8mp_audiomix_reset { 20 46 struct reset_controller_dev rcdev; ··· 55 25 return container_of(rcdev, struct imx8mp_audiomix_reset, rcdev); 56 26 } 57 27 58 - static int imx8mp_audiomix_reset_assert(struct reset_controller_dev *rcdev, 59 - unsigned long id) 28 + static int imx8mp_audiomix_update(struct reset_controller_dev *rcdev, 29 + unsigned long id, bool assert) 60 30 { 61 31 struct imx8mp_audiomix_reset *priv = to_imx8mp_audiomix_reset(rcdev); 62 32 void __iomem *reg_addr = priv->base; 63 - unsigned int mask, reg; 64 - unsigned long flags; 33 + unsigned int mask, offset, active_low; 34 + unsigned long reg, flags; 65 35 66 - mask = BIT(id); 36 + mask = reset_map[id].mask; 37 + offset = reset_map[id].offset; 38 + active_low = reset_map[id].active_low; 39 + 67 40 spin_lock_irqsave(&priv->lock, flags); 68 - reg = readl(reg_addr + EARC); 69 - writel(reg & ~mask, reg_addr + EARC); 41 + 42 + reg = readl(reg_addr + offset); 43 + if (active_low ^ assert) 44 + reg |= mask; 45 + else 46 + reg &= ~mask; 47 + writel(reg, reg_addr + offset); 48 + 70 49 spin_unlock_irqrestore(&priv->lock, flags); 71 50 72 51 return 0; 73 52 } 74 53 54 + static int imx8mp_audiomix_reset_assert(struct reset_controller_dev *rcdev, 55 + unsigned long id) 56 + { 57 + return imx8mp_audiomix_update(rcdev, id, true); 58 + } 59 + 75 60 static int imx8mp_audiomix_reset_deassert(struct reset_controller_dev *rcdev, 76 61 unsigned long id) 77 62 { 78 - struct imx8mp_audiomix_reset *priv = to_imx8mp_audiomix_reset(rcdev); 79 - void __iomem *reg_addr = priv->base; 80 - unsigned int mask, reg; 81 - unsigned long flags; 82 - 83 - mask = BIT(id); 84 - spin_lock_irqsave(&priv->lock, flags); 85 - reg = readl(reg_addr + EARC); 86 - writel(reg | mask, reg_addr + EARC); 87 - spin_unlock_irqrestore(&priv->lock, flags); 88 - 89 - return 0; 63 + return imx8mp_audiomix_update(rcdev, id, false); 90 64 } 91 65 92 66 static const struct reset_control_ops imx8mp_audiomix_reset_ops = { ··· 112 78 spin_lock_init(&priv->lock); 113 79 114 80 priv->rcdev.owner = THIS_MODULE; 115 - priv->rcdev.nr_resets = fls(EARC_RESET_MASK); 81 + priv->rcdev.nr_resets = ARRAY_SIZE(reset_map); 116 82 priv->rcdev.ops = &imx8mp_audiomix_reset_ops; 117 83 priv->rcdev.of_node = dev->parent->of_node; 118 84 priv->rcdev.dev = dev;
+13
include/dt-bindings/reset/imx8mp-reset-audiomix.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 + /* 3 + * Copyright 2025 NXP 4 + */ 5 + 6 + #ifndef DT_BINDING_RESET_IMX8MP_AUDIOMIX_H 7 + #define DT_BINDING_RESET_IMX8MP_AUDIOMIX_H 8 + 9 + #define IMX8MP_AUDIOMIX_EARC_RESET 0 10 + #define IMX8MP_AUDIOMIX_EARC_PHY_RESET 1 11 + #define IMX8MP_AUDIOMIX_DSP_RUNSTALL 2 12 + 13 + #endif /* DT_BINDING_RESET_IMX8MP_AUDIOMIX_H */