Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"The biggest change for SPI this release is the addition of offload
support from David Lechner, allowing the hardware to trigger SPI
transactions autonomously. The initial use case is for triggering IIO
operations but there are other applications where having the hardware
ready to go at a minimal signal is useful for synchronising with
external inputs (eg, interrupt handling) or reducing latency (eg, CAN
networking).
Otherwise there's the usual fixes, improvements and cleanups, plus
support for a bunch of new devices.
- Support for offloading support from David Lechner
- Support for GOcontrol1 Moduline modules, Mediatek MT7988, NXP
i.MX94, Qualcomm SPI NAMD, Rockchip RK3562, Sophogo SG2044 and ST
STM32 OSPI"
* tag 'spi-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (59 commits)
spi: spi-mem: Introduce a default ->exec_op() debug log
spi: dt-bindings: cdns,qspi-nor: Require some peripheral properties
spi: dt-bindings: cdns,qspi-nor: Deprecate the Cadence compatible alone
spi: dt-bindings: cdns,qspi-nor: Be more descriptive regarding what this controller is
spi: stm32-ospi: Include "gpio/consumer.h"
MAINTAINERS: adjust the file entry in GOCONTROLL MODULINE MODULE SLOT
spi: spi-qpic-snand: avoid memleak in qcom_spi_ecc_init_ctx_pipelined()
spi: spi-mux: Fix coverity issue, unchecked return value
spi: sophgo: fix incorrect type for ret in sg2044_spifmc_write()
spi: sg2044-nor: fix uninitialized variable in probe
spi: sg2044-nor: fix signedness bug in sg2044_spifmc_write()
spi: sg2044-nor: Convert to dev_err_probe()
spi: sg2044-nor: Fully convert to device managed resources
dt-bindings: spi: add compatibles for mt7988
spi: spidev: Add an entry for the gocontroll moduline module slot
MAINTAINERS: add maintainer for the GOcontroll Moduline module slot
dt-bindings: connector: Add the GOcontroll Moduline module slot bindings
dt-bindings: vendor-prefixes: add GOcontroll
spi: Use inclusive language
spi: cadence-qspi: Improve spi memory performance
...
+5188
-307
+88
Documentation/devicetree/bindings/connector/gocontroll,moduline-module-slot.yaml
+88
Documentation/devicetree/bindings/connector/gocontroll,moduline-module-slot.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/connector/gocontroll,moduline-module-slot.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: GOcontroll Moduline Module slot
8
+
9
+
maintainers:
10
+
- Maud Spierings <maudspierings@gocontroll.com>
11
+
12
+
description:
13
+
The GOcontroll Moduline module slot represents a connector that fullfills the
14
+
Moduline slot specification, and can thus house any IO module that is also
15
+
built to this spec.
16
+
17
+
properties:
18
+
compatible:
19
+
const: gocontroll,moduline-module-slot
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
interrupts:
25
+
description: indicates readiness, high means busy.
26
+
maxItems: 1
27
+
reset-gpios:
28
+
description: resets the module, active low.
29
+
maxItems: 1
30
+
sync-gpios:
31
+
description: sync line between all module slots.
32
+
maxItems: 1
33
+
34
+
vdd-supply:
35
+
description: low power 3v3 supply generally for the microcontroller.
36
+
vddp-supply:
37
+
description: medium power 5v0 supply for on module low power peripherals.
38
+
vddhpp-supply:
39
+
description: high power 6v-8v supply for on module high power peripherals.
40
+
power-supply:
41
+
description: high power 6v-30v supply for high power module circuits.
42
+
43
+
i2c-bus:
44
+
description: i2c bus shared between module slots and the SoC
45
+
$ref: /schemas/types.yaml#/definitions/phandle
46
+
47
+
slot-number:
48
+
description:
49
+
The number of the module slot representing the location of on the pcb.
50
+
This enables access to the modules based on slot location.
51
+
$ref: /schemas/types.yaml#/definitions/uint32
52
+
53
+
spi-max-frequency: true
54
+
55
+
required:
56
+
- compatible
57
+
- reg
58
+
- reset-gpios
59
+
- interrupts
60
+
- sync-gpios
61
+
- i2c-bus
62
+
- slot-number
63
+
64
+
additionalProperties: false
65
+
66
+
examples:
67
+
- |
68
+
#include <dt-bindings/gpio/gpio.h>
69
+
#include <dt-bindings/interrupt-controller/irq.h>
70
+
71
+
spi {
72
+
#address-cells = <1>;
73
+
#size-cells = <0>;
74
+
75
+
connector@0 {
76
+
reg = <0>;
77
+
compatible = "gocontroll,moduline-module-slot";
78
+
reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
79
+
sync-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
80
+
interrupt-parent = <&gpio4>;
81
+
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
82
+
vdd-supply = <®_3v3_per>;
83
+
vddp-supply = <®_5v0>;
84
+
vddhpp-supply = <®_6v4>;
85
+
i2c-bus = <&i2c2>;
86
+
slot-number = <1>;
87
+
};
88
+
};
+24
Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml
+24
Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml
···
41
41
- const: s_axi_aclk
42
42
- const: spi_clk
43
43
44
+
trigger-sources:
45
+
description:
46
+
An array of trigger source phandles for offload instances. The index in
47
+
the array corresponds to the offload instance number.
48
+
minItems: 1
49
+
maxItems: 32
50
+
51
+
dmas:
52
+
description:
53
+
DMA channels connected to the input or output stream interface of an
54
+
offload instance.
55
+
minItems: 1
56
+
maxItems: 32
57
+
58
+
dma-names:
59
+
items:
60
+
pattern: "^offload(?:[12]?[0-9]|3[01])-[tr]x$"
61
+
minItems: 1
62
+
maxItems: 32
63
+
44
64
required:
45
65
- compatible
46
66
- reg
···
78
58
interrupts = <0 56 4>;
79
59
clocks = <&clkc 15>, <&clkc 15>;
80
60
clock-names = "s_axi_aclk", "spi_clk";
61
+
62
+
trigger-sources = <&trigger_clock>;
63
+
dmas = <&dma 0>;
64
+
dma-names = "offload0-rx";
81
65
82
66
#address-cells = <1>;
83
67
#size-cells = <0>;
+23
-2
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+23
-2
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
···
4
4
$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Cadence Quad SPI controller
7
+
title: Cadence Quad/Octal SPI controller
8
8
9
9
maintainers:
10
10
- Vaishnav Achath <vaishnav.a@ti.com>
···
76
76
- ti,am654-ospi
77
77
- ti,k2g-qspi
78
78
- xlnx,versal-ospi-1.0
79
+
# The compatible is qspi-nor for historical reasons but such
80
+
# controllers are meant to be used with flashes of all kinds,
81
+
# ie. also NAND flashes, not only NOR flashes.
79
82
- const: cdns,qspi-nor
80
83
- const: cdns,qspi-nor
84
+
deprecated: true
81
85
82
86
reg:
83
87
items:
···
146
142
items:
147
143
enum: [ qspi, qspi-ocp, rstc_ref ]
148
144
145
+
patternProperties:
146
+
"^flash@[0-9a-f]+$":
147
+
type: object
148
+
$ref: cdns,qspi-nor-peripheral-props.yaml
149
+
additionalProperties: true
150
+
required:
151
+
- cdns,read-delay
152
+
- cdns,tshsl-ns
153
+
- cdns,tsd2d-ns
154
+
- cdns,tchsh-ns
155
+
- cdns,tslch-ns
156
+
149
157
required:
150
158
- compatible
151
159
- reg
···
173
157
examples:
174
158
- |
175
159
qspi: spi@ff705000 {
176
-
compatible = "cdns,qspi-nor";
160
+
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
177
161
#address-cells = <1>;
178
162
#size-cells = <0>;
179
163
reg = <0xff705000 0x1000>,
···
189
173
flash@0 {
190
174
compatible = "jedec,spi-nor";
191
175
reg = <0x0>;
176
+
cdns,read-delay = <4>;
177
+
cdns,tshsl-ns = <60>;
178
+
cdns,tsd2d-ns = <60>;
179
+
cdns,tchsh-ns = <60>;
180
+
cdns,tslch-ns = <60>;
192
181
};
193
182
};
+65
Documentation/devicetree/bindings/spi/fsl,espi.yaml
+65
Documentation/devicetree/bindings/spi/fsl,espi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/fsl,espi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale eSPI (Enhanced Serial Peripheral Interface) controller
8
+
9
+
maintainers:
10
+
- J. Neuschäfer <j.ne@posteo.net>
11
+
12
+
properties:
13
+
compatible:
14
+
const: fsl,mpc8536-espi
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
interrupts:
20
+
maxItems: 1
21
+
22
+
fsl,espi-num-chipselects:
23
+
$ref: /schemas/types.yaml#/definitions/uint32
24
+
enum: [ 1, 4 ]
25
+
description: The number of the chipselect signals.
26
+
27
+
fsl,csbef:
28
+
$ref: /schemas/types.yaml#/definitions/uint32
29
+
minimum: 0
30
+
maximum: 15
31
+
description: Chip select assertion time in bits before frame starts
32
+
33
+
fsl,csaft:
34
+
$ref: /schemas/types.yaml#/definitions/uint32
35
+
minimum: 0
36
+
maximum: 15
37
+
description: Chip select negation time in bits after frame ends
38
+
39
+
required:
40
+
- compatible
41
+
- reg
42
+
- interrupts
43
+
- fsl,espi-num-chipselects
44
+
45
+
allOf:
46
+
- $ref: spi-controller.yaml#
47
+
48
+
unevaluatedProperties: false
49
+
50
+
examples:
51
+
- |
52
+
#include <dt-bindings/interrupt-controller/irq.h>
53
+
54
+
spi@110000 {
55
+
compatible = "fsl,mpc8536-espi";
56
+
reg = <0x110000 0x1000>;
57
+
#address-cells = <1>;
58
+
#size-cells = <0>;
59
+
interrupts = <53 IRQ_TYPE_EDGE_FALLING>;
60
+
fsl,espi-num-chipselects = <4>;
61
+
fsl,csbef = <1>;
62
+
fsl,csaft = <1>;
63
+
};
64
+
65
+
...
+74
Documentation/devicetree/bindings/spi/fsl,spi.yaml
+74
Documentation/devicetree/bindings/spi/fsl,spi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/fsl,spi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale SPI (Serial Peripheral Interface) controller
8
+
9
+
maintainers:
10
+
- J. Neuschäfer <j.ne@posteo.net>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- fsl,spi
16
+
- aeroflexgaisler,spictrl
17
+
18
+
reg:
19
+
maxItems: 1
20
+
21
+
cell-index:
22
+
$ref: /schemas/types.yaml#/definitions/uint32
23
+
description: |
24
+
QE SPI subblock index.
25
+
0: QE subblock SPI1
26
+
1: QE subblock SPI2
27
+
28
+
mode:
29
+
description: SPI operation mode
30
+
enum:
31
+
- cpu
32
+
- cpu-qe
33
+
34
+
interrupts:
35
+
maxItems: 1
36
+
37
+
clock-frequency:
38
+
description: input clock frequency to non FSL_SOC cores
39
+
40
+
cs-gpios: true
41
+
42
+
fsl,spisel_boot:
43
+
$ref: /schemas/types.yaml#/definitions/flag
44
+
description:
45
+
For the MPC8306 and MPC8309, specifies that the SPISEL_BOOT signal is used
46
+
as chip select for a slave device. Use reg = <number of gpios> in the
47
+
corresponding child node, i.e. 0 if the cs-gpios property is not present.
48
+
49
+
required:
50
+
- compatible
51
+
- reg
52
+
- mode
53
+
- interrupts
54
+
55
+
allOf:
56
+
- $ref: spi-controller.yaml#
57
+
58
+
unevaluatedProperties: false
59
+
60
+
examples:
61
+
- |
62
+
#include <dt-bindings/interrupt-controller/irq.h>
63
+
64
+
spi@4c0 {
65
+
compatible = "fsl,spi";
66
+
reg = <0x4c0 0x40>;
67
+
cell-index = <0>;
68
+
interrupts = <82 0>;
69
+
mode = "cpu";
70
+
cs-gpios = <&gpio 18 IRQ_TYPE_EDGE_RISING // device reg=<0>
71
+
&gpio 19 IRQ_TYPE_EDGE_RISING>; // device reg=<1>
72
+
};
73
+
74
+
...
-62
Documentation/devicetree/bindings/spi/fsl-spi.txt
-62
Documentation/devicetree/bindings/spi/fsl-spi.txt
···
1
-
* SPI (Serial Peripheral Interface)
2
-
3
-
Required properties:
4
-
- cell-index : QE SPI subblock index.
5
-
0: QE subblock SPI1
6
-
1: QE subblock SPI2
7
-
- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
8
-
- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
9
-
- reg : Offset and length of the register set for the device
10
-
- interrupts : <a b> where a is the interrupt number and b is a
11
-
field that represents an encoding of the sense and level
12
-
information for the interrupt. This should be encoded based on
13
-
the information in section 2) depending on the type of interrupt
14
-
controller you have.
15
-
- clock-frequency : input clock frequency to non FSL_SOC cores
16
-
17
-
Optional properties:
18
-
- cs-gpios : specifies the gpio pins to be used for chipselects.
19
-
The gpios will be referred to as reg = <index> in the SPI child nodes.
20
-
If unspecified, a single SPI device without a chip select can be used.
21
-
- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
22
-
SPISEL_BOOT signal is used as chip select for a slave device. Use
23
-
reg = <number of gpios> in the corresponding child node, i.e. 0 if
24
-
the cs-gpios property is not present.
25
-
26
-
Example:
27
-
spi@4c0 {
28
-
cell-index = <0>;
29
-
compatible = "fsl,spi";
30
-
reg = <4c0 40>;
31
-
interrupts = <82 0>;
32
-
interrupt-parent = <700>;
33
-
mode = "cpu";
34
-
cs-gpios = <&gpio 18 1 // device reg=<0>
35
-
&gpio 19 1>; // device reg=<1>
36
-
};
37
-
38
-
39
-
* eSPI (Enhanced Serial Peripheral Interface)
40
-
41
-
Required properties:
42
-
- compatible : should be "fsl,mpc8536-espi".
43
-
- reg : Offset and length of the register set for the device.
44
-
- interrupts : should contain eSPI interrupt, the device has one interrupt.
45
-
- fsl,espi-num-chipselects : the number of the chipselect signals.
46
-
47
-
Optional properties:
48
-
- fsl,csbef: chip select assertion time in bits before frame starts
49
-
- fsl,csaft: chip select negation time in bits after frame ends
50
-
51
-
Example:
52
-
spi@110000 {
53
-
#address-cells = <1>;
54
-
#size-cells = <0>;
55
-
compatible = "fsl,mpc8536-espi";
56
-
reg = <0x110000 0x1000>;
57
-
interrupts = <53 0x2>;
58
-
interrupt-parent = <&mpic>;
59
-
fsl,espi-num-chipselects = <4>;
60
-
fsl,csbef = <1>;
61
-
fsl,csaft = <1>;
62
-
};
+2
Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
+2
Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
+83
Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
+83
Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm QPIC NAND controller
8
+
9
+
maintainers:
10
+
- Md sadre Alam <quic_mdalam@quicinc.com>
11
+
12
+
description:
13
+
The QCOM QPIC-SPI-NAND flash controller is an extended version of
14
+
the QCOM QPIC NAND flash controller. It can work both in serial
15
+
and parallel mode. It supports typical SPI-NAND page cache
16
+
operations in single, dual or quad IO mode with pipelined ECC
17
+
encoding/decoding using the QPIC ECC HW engine.
18
+
19
+
allOf:
20
+
- $ref: /schemas/spi/spi-controller.yaml#
21
+
22
+
properties:
23
+
compatible:
24
+
enum:
25
+
- qcom,ipq9574-snand
26
+
27
+
reg:
28
+
maxItems: 1
29
+
30
+
clocks:
31
+
maxItems: 3
32
+
33
+
clock-names:
34
+
items:
35
+
- const: core
36
+
- const: aon
37
+
- const: iom
38
+
39
+
dmas:
40
+
items:
41
+
- description: tx DMA channel
42
+
- description: rx DMA channel
43
+
- description: cmd DMA channel
44
+
45
+
dma-names:
46
+
items:
47
+
- const: tx
48
+
- const: rx
49
+
- const: cmd
50
+
51
+
required:
52
+
- compatible
53
+
- reg
54
+
- clocks
55
+
- clock-names
56
+
57
+
unevaluatedProperties: false
58
+
59
+
examples:
60
+
- |
61
+
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
62
+
spi@79b0000 {
63
+
compatible = "qcom,ipq9574-snand";
64
+
reg = <0x1ac00000 0x800>;
65
+
66
+
clocks = <&gcc GCC_QPIC_CLK>,
67
+
<&gcc GCC_QPIC_AHB_CLK>,
68
+
<&gcc GCC_QPIC_IO_MACRO_CLK>;
69
+
clock-names = "core", "aon", "iom";
70
+
71
+
#address-cells = <1>;
72
+
#size-cells = <0>;
73
+
74
+
flash@0 {
75
+
compatible = "spi-nand";
76
+
reg = <0>;
77
+
#address-cells = <1>;
78
+
#size-cells = <1>;
79
+
nand-ecc-engine = <&qpic_nand>;
80
+
nand-ecc-strength = <4>;
81
+
nand-ecc-step-size = <512>;
82
+
};
83
+
};
+1
Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
+1
Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
+1
Documentation/devicetree/bindings/spi/spi-rockchip.yaml
+1
Documentation/devicetree/bindings/spi/spi-rockchip.yaml
+52
Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml
+52
Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/spi-sg2044-nor.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: SG2044 SPI NOR controller
8
+
9
+
maintainers:
10
+
- Longbin Li <looong.bin@gmail.com>
11
+
12
+
allOf:
13
+
- $ref: spi-controller.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: sophgo,sg2044-spifmc-nor
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
clocks:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
resets:
29
+
maxItems: 1
30
+
31
+
required:
32
+
- compatible
33
+
- reg
34
+
- clocks
35
+
- interrupts
36
+
- resets
37
+
38
+
unevaluatedProperties: false
39
+
40
+
examples:
41
+
- |
42
+
#include <dt-bindings/interrupt-controller/irq.h>
43
+
44
+
spi@1000000 {
45
+
compatible = "sophgo,sg2044-spifmc-nor";
46
+
reg = <0x1000000 0x4000000>;
47
+
#address-cells = <1>;
48
+
#size-cells = <0>;
49
+
clocks = <&clk 0>;
50
+
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
51
+
resets = <&rst 0>;
52
+
};
+105
Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml
+105
Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/st,stm32mp25-ospi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: STMicroelectronics STM32 Octal Serial Peripheral Interface (OSPI)
8
+
9
+
maintainers:
10
+
- Patrice Chotard <patrice.chotard@foss.st.com>
11
+
12
+
allOf:
13
+
- $ref: spi-controller.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: st,stm32mp25-ospi
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
memory-region:
23
+
description:
24
+
Memory region to be used for memory-map read access.
25
+
In memory-mapped mode, read access are performed from the memory
26
+
device using the direct mapping.
27
+
maxItems: 1
28
+
29
+
clocks:
30
+
maxItems: 1
31
+
32
+
interrupts:
33
+
maxItems: 1
34
+
35
+
resets:
36
+
items:
37
+
- description: phandle to OSPI block reset
38
+
- description: phandle to delay block reset
39
+
40
+
dmas:
41
+
maxItems: 2
42
+
43
+
dma-names:
44
+
items:
45
+
- const: tx
46
+
- const: rx
47
+
48
+
st,syscfg-dlyb:
49
+
description: configure OCTOSPI delay block.
50
+
$ref: /schemas/types.yaml#/definitions/phandle-array
51
+
items:
52
+
- description: phandle to syscfg
53
+
- description: register offset within syscfg
54
+
55
+
access-controllers:
56
+
description: phandle to the rifsc device to check access right
57
+
and in some cases, an additional phandle to the rcc device for
58
+
secure clock control.
59
+
items:
60
+
- description: phandle to bus controller
61
+
- description: phandle to clock controller
62
+
minItems: 1
63
+
64
+
power-domains:
65
+
maxItems: 1
66
+
67
+
required:
68
+
- compatible
69
+
- reg
70
+
- clocks
71
+
- interrupts
72
+
- st,syscfg-dlyb
73
+
74
+
unevaluatedProperties: false
75
+
76
+
examples:
77
+
- |
78
+
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
79
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
80
+
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
81
+
82
+
spi@40430000 {
83
+
compatible = "st,stm32mp25-ospi";
84
+
reg = <0x40430000 0x400>;
85
+
memory-region = <&mm_ospi1>;
86
+
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
87
+
dmas = <&hpdma 2 0x62 0x00003121 0x0>,
88
+
<&hpdma 2 0x42 0x00003112 0x0>;
89
+
dma-names = "tx", "rx";
90
+
clocks = <&scmi_clk CK_SCMI_OSPI1>;
91
+
resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>;
92
+
access-controllers = <&rifsc 74>;
93
+
power-domains = <&CLUSTER_PD>;
94
+
st,syscfg-dlyb = <&syscfg 0x1000>;
95
+
96
+
#address-cells = <1>;
97
+
#size-cells = <0>;
98
+
99
+
flash@0 {
100
+
compatible = "jedec,spi-nor";
101
+
reg = <0>;
102
+
spi-rx-bus-width = <4>;
103
+
spi-max-frequency = <108000000>;
104
+
};
105
+
};
+37
Documentation/devicetree/bindings/trigger-source/pwm-trigger.yaml
+37
Documentation/devicetree/bindings/trigger-source/pwm-trigger.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/trigger-source/pwm-trigger.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Generic trigger source using PWM
8
+
9
+
description: Remaps a PWM channel as a trigger source.
10
+
11
+
maintainers:
12
+
- David Lechner <dlechner@baylibre.com>
13
+
14
+
properties:
15
+
compatible:
16
+
const: pwm-trigger
17
+
18
+
'#trigger-source-cells':
19
+
const: 0
20
+
21
+
pwms:
22
+
maxItems: 1
23
+
24
+
required:
25
+
- compatible
26
+
- '#trigger-source-cells'
27
+
- pwms
28
+
29
+
additionalProperties: false
30
+
31
+
examples:
32
+
- |
33
+
trigger {
34
+
compatible = "pwm-trigger";
35
+
#trigger-source-cells = <0>;
36
+
pwms = <&pwm 0 1000000 0>;
37
+
};
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
···
593
593
description: GlobalTop Technology, Inc.
594
594
"^gmt,.*":
595
595
description: Global Mixed-mode Technology, Inc.
596
+
"^gocontroll,.*":
597
+
description: GOcontroll Modular Embedded Electronics B.V.
596
598
"^goldelico,.*":
597
599
description: Golden Delicious Computers GmbH & Co. KG
598
600
"^goodix,.*":
+17
MAINTAINERS
+17
MAINTAINERS
···
9863
9863
S: Maintained
9864
9864
F: drivers/media/usb/go7007/
9865
9865
9866
+
GOCONTROLL MODULINE MODULE SLOT
9867
+
M: Maud Spierings <maudspierings@gocontroll.com>
9868
+
S: Maintained
9869
+
F: Documentation/devicetree/bindings/connector/gocontroll,moduline-module-slot.yaml
9870
+
9866
9871
GOODIX TOUCHSCREEN
9867
9872
M: Hans de Goede <hdegoede@redhat.com>
9868
9873
L: linux-input@vger.kernel.org
···
22425
22420
F: drivers/mtd/spi-nor/
22426
22421
F: include/linux/mtd/spi-nor.h
22427
22422
22423
+
SPI OFFLOAD
22424
+
R: David Lechner <dlechner@baylibre.com>
22425
+
F: drivers/spi/spi-offload-trigger-pwm.c
22426
+
F: drivers/spi/spi-offload.c
22427
+
F: include/linux/spi/offload/
22428
+
K: spi_offload
22429
+
22428
22430
SPI SUBSYSTEM
22429
22431
M: Mark Brown <broonie@kernel.org>
22430
22432
L: linux-spi@vger.kernel.org
···
24179
24167
W: https://github.com/srcres258/linux-doc
24180
24168
T: git git://github.com/srcres258/linux-doc.git doc-zh-tw
24181
24169
F: Documentation/translations/zh_TW/
24170
+
24171
+
TRIGGER SOURCE - PWM
24172
+
M: David Lechner <dlechner@baylibre.com>
24173
+
S: Maintained
24174
+
F: Documentation/devicetree/bindings/trigger-source/pwm-trigger.yaml
24182
24175
24183
24176
TRUSTED SECURITY MODULE (TSM) ATTESTATION REPORTS
24184
24177
M: Dan Williams <dan.j.williams@intel.com>
+4
drivers/mtd/nand/Makefile
+4
drivers/mtd/nand/Makefile
···
3
3
nandcore-objs := core.o bbt.o
4
4
obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
5
5
obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
6
+
ifeq ($(CONFIG_SPI_QPIC_SNAND),y)
7
+
obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o
8
+
else
6
9
obj-$(CONFIG_MTD_NAND_QCOM) += qpic_common.o
10
+
endif
7
11
obj-y += onenand/
8
12
obj-y += raw/
9
13
obj-y += spi/
+44
drivers/spi/Kconfig
+44
drivers/spi/Kconfig
···
55
55
This extension is meant to simplify interaction with SPI memories
56
56
by providing a high-level interface to send memory-like commands.
57
57
58
+
config SPI_OFFLOAD
59
+
bool
60
+
58
61
comment "SPI Master Controller Drivers"
59
62
60
63
config SPI_AIROHA_SNFI
···
179
176
config SPI_AXI_SPI_ENGINE
180
177
tristate "Analog Devices AXI SPI Engine controller"
181
178
depends on HAS_IOMEM
179
+
select SPI_OFFLOAD
182
180
help
183
181
This enables support for the Analog Devices AXI SPI Engine SPI controller.
184
182
It is part of the SPI Engine framework that is used in some Analog Devices
···
936
932
help
937
933
QSPI(Quad SPI) driver for Qualcomm QSPI controller.
938
934
935
+
config SPI_QPIC_SNAND
936
+
bool "QPIC SNAND controller"
937
+
depends on ARCH_QCOM || COMPILE_TEST
938
+
select MTD
939
+
help
940
+
QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller.
941
+
QPIC controller supports both parallel nand and serial nand.
942
+
This config will enable serial nand driver for QPIC controller.
943
+
939
944
config SPI_QUP
940
945
tristate "Qualcomm SPI controller with QUP interface"
941
946
depends on ARCH_QCOM || COMPILE_TEST
···
1034
1021
for connecting an SPI Flash memory over up to 8-bit wide bus.
1035
1022
It supports indirect access mode only.
1036
1023
1024
+
config SPI_SG2044_NOR
1025
+
tristate "SG2044 SPI NOR Controller"
1026
+
depends on ARCH_SOPHGO || COMPILE_TEST
1027
+
help
1028
+
This enables support for the SG2044 SPI NOR controller,
1029
+
which supports Dual/Quad read and write operations while
1030
+
also supporting 3Byte address devices and 4Byte address
1031
+
devices.
1032
+
1037
1033
config SPI_SPRD
1038
1034
tristate "Spreadtrum SPI controller"
1039
1035
depends on ARCH_SPRD || COMPILE_TEST
···
1066
1044
STM32 SPI controller supports DMA and PIO modes. When DMA
1067
1045
is not available, the driver automatically falls back to
1068
1046
PIO mode.
1047
+
1048
+
config SPI_STM32_OSPI
1049
+
tristate "STMicroelectronics STM32 OCTO SPI controller"
1050
+
depends on ARCH_STM32 || COMPILE_TEST
1051
+
depends on OF
1052
+
depends on SPI_MEM
1053
+
help
1054
+
This enables support for the Octo SPI controller in master mode.
1055
+
This driver does not support generic SPI. The implementation only
1056
+
supports spi-mem interface.
1069
1057
1070
1058
config SPI_STM32_QSPI
1071
1059
tristate "STMicroelectronics STM32 QUAD SPI controller"
···
1348
1316
1349
1317
config SPI_DYNAMIC
1350
1318
def_bool ACPI || OF_DYNAMIC || SPI_SLAVE
1319
+
1320
+
if SPI_OFFLOAD
1321
+
1322
+
comment "SPI Offload triggers"
1323
+
1324
+
config SPI_OFFLOAD_TRIGGER_PWM
1325
+
tristate "SPI offload trigger using PWM"
1326
+
depends on PWM
1327
+
help
1328
+
Generic SPI offload trigger implemented using PWM output.
1329
+
1330
+
endif # SPI_OFFLOAD
1351
1331
1352
1332
endif # SPI
+7
drivers/spi/Makefile
+7
drivers/spi/Makefile
···
10
10
obj-$(CONFIG_SPI_MASTER) += spi.o
11
11
obj-$(CONFIG_SPI_MEM) += spi-mem.o
12
12
obj-$(CONFIG_SPI_MUX) += spi-mux.o
13
+
obj-$(CONFIG_SPI_OFFLOAD) += spi-offload.o
13
14
obj-$(CONFIG_SPI_SPIDEV) += spidev.o
14
15
obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
15
16
···
117
116
obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
118
117
obj-$(CONFIG_SPI_QCOM_GENI) += spi-geni-qcom.o
119
118
obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o
119
+
obj-$(CONFIG_SPI_QPIC_SNAND) += spi-qpic-snand.o
120
120
obj-$(CONFIG_SPI_QUP) += spi-qup.o
121
121
obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
122
122
obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o
···
136
134
obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
137
135
obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o
138
136
obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o
137
+
obj-$(CONFIG_SPI_SG2044_NOR) += spi-sg2044-nor.o
139
138
obj-$(CONFIG_SPI_SPRD) += spi-sprd.o
140
139
obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o
141
140
obj-$(CONFIG_SPI_STM32) += spi-stm32.o
141
+
obj-$(CONFIG_SPI_STM32_OSPI) += spi-stm32-ospi.o
142
142
obj-$(CONFIG_SPI_STM32_QSPI) += spi-stm32-qspi.o
143
143
obj-$(CONFIG_SPI_ST_SSC4) += spi-st-ssc4.o
144
144
obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
···
167
163
# SPI slave protocol handlers
168
164
obj-$(CONFIG_SPI_SLAVE_TIME) += spi-slave-time.o
169
165
obj-$(CONFIG_SPI_SLAVE_SYSTEM_CONTROL) += spi-slave-system-control.o
166
+
167
+
# SPI offload triggers
168
+
obj-$(CONFIG_SPI_OFFLOAD_TRIGGER_PWM) += spi-offload-trigger-pwm.o
-7
drivers/spi/spi-aspeed-smc.c
-7
drivers/spi/spi-aspeed-smc.c
···
303
303
u32 ctl_val;
304
304
int ret = 0;
305
305
306
-
dev_dbg(aspi->dev,
307
-
"CE%d %s OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x len:%#x",
308
-
chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
309
-
op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
310
-
op->dummy.buswidth, op->data.buswidth,
311
-
op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
312
-
313
306
addr_mode = readl(aspi->regs + CE_CTRL_REG);
314
307
addr_mode_backup = addr_mode;
315
308
+308
-7
drivers/spi/spi-axi-spi-engine.c
+308
-7
drivers/spi/spi-axi-spi-engine.c
···
2
2
/*
3
3
* SPI-Engine SPI controller driver
4
4
* Copyright 2015 Analog Devices Inc.
5
+
* Copyright 2024 BayLibre, SAS
5
6
* Author: Lars-Peter Clausen <lars@metafoo.de>
6
7
*/
7
8
9
+
#include <linux/bitfield.h>
10
+
#include <linux/bitops.h>
8
11
#include <linux/clk.h>
9
12
#include <linux/completion.h>
13
+
#include <linux/dmaengine.h>
10
14
#include <linux/fpga/adi-axi-common.h>
11
15
#include <linux/interrupt.h>
12
16
#include <linux/io.h>
···
18
14
#include <linux/module.h>
19
15
#include <linux/overflow.h>
20
16
#include <linux/platform_device.h>
17
+
#include <linux/spi/offload/provider.h>
21
18
#include <linux/spi/spi.h>
22
19
#include <trace/events/spi.h>
23
20
21
+
#define SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH 0x10
24
22
#define SPI_ENGINE_REG_RESET 0x40
25
23
26
24
#define SPI_ENGINE_REG_INT_ENABLE 0x80
···
30
24
#define SPI_ENGINE_REG_INT_SOURCE 0x88
31
25
32
26
#define SPI_ENGINE_REG_SYNC_ID 0xc0
27
+
#define SPI_ENGINE_REG_OFFLOAD_SYNC_ID 0xc4
33
28
34
29
#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xd0
35
30
#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xd4
···
41
34
#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xe8
42
35
#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xec
43
36
37
+
#define SPI_ENGINE_MAX_NUM_OFFLOADS 32
38
+
39
+
#define SPI_ENGINE_REG_OFFLOAD_CTRL(x) (0x100 + SPI_ENGINE_MAX_NUM_OFFLOADS * (x))
40
+
#define SPI_ENGINE_REG_OFFLOAD_STATUS(x) (0x104 + SPI_ENGINE_MAX_NUM_OFFLOADS * (x))
41
+
#define SPI_ENGINE_REG_OFFLOAD_RESET(x) (0x108 + SPI_ENGINE_MAX_NUM_OFFLOADS * (x))
42
+
#define SPI_ENGINE_REG_OFFLOAD_CMD_FIFO(x) (0x110 + SPI_ENGINE_MAX_NUM_OFFLOADS * (x))
43
+
#define SPI_ENGINE_REG_OFFLOAD_SDO_FIFO(x) (0x114 + SPI_ENGINE_MAX_NUM_OFFLOADS * (x))
44
+
45
+
#define SPI_ENGINE_SPI_OFFLOAD_MEM_WIDTH_SDO GENMASK(15, 8)
46
+
#define SPI_ENGINE_SPI_OFFLOAD_MEM_WIDTH_CMD GENMASK(7, 0)
47
+
44
48
#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0)
45
49
#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1)
46
50
#define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2)
47
51
#define SPI_ENGINE_INT_SYNC BIT(3)
52
+
#define SPI_ENGINE_INT_OFFLOAD_SYNC BIT(4)
53
+
54
+
#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE BIT(0)
48
55
49
56
#define SPI_ENGINE_CONFIG_CPHA BIT(0)
50
57
#define SPI_ENGINE_CONFIG_CPOL BIT(1)
···
100
79
#define SPI_ENGINE_CMD_CS_INV(flags) \
101
80
SPI_ENGINE_CMD(SPI_ENGINE_INST_CS_INV, 0, (flags))
102
81
82
+
/* default sizes - can be changed when SPI Engine firmware is compiled */
83
+
#define SPI_ENGINE_OFFLOAD_CMD_FIFO_SIZE 16
84
+
#define SPI_ENGINE_OFFLOAD_SDO_FIFO_SIZE 16
85
+
103
86
struct spi_engine_program {
104
87
unsigned int length;
105
88
uint16_t instructions[] __counted_by(length);
···
131
106
uint8_t *rx_buf;
132
107
};
133
108
109
+
enum {
110
+
SPI_ENGINE_OFFLOAD_FLAG_ASSIGNED,
111
+
SPI_ENGINE_OFFLOAD_FLAG_PREPARED,
112
+
};
113
+
114
+
struct spi_engine_offload {
115
+
struct spi_engine *spi_engine;
116
+
unsigned long flags;
117
+
unsigned int offload_num;
118
+
};
119
+
134
120
struct spi_engine {
135
121
struct clk *clk;
136
122
struct clk *ref_clk;
···
154
118
unsigned int int_enable;
155
119
/* shadows hardware CS inversion flag state */
156
120
u8 cs_inv;
121
+
122
+
unsigned int offload_ctrl_mem_size;
123
+
unsigned int offload_sdo_mem_size;
124
+
struct spi_offload *offload;
125
+
u32 offload_caps;
157
126
};
158
127
159
128
static void spi_engine_program_add_cmd(struct spi_engine_program *p,
···
204
163
unsigned int n = min(len, 256U);
205
164
unsigned int flags = 0;
206
165
207
-
if (xfer->tx_buf)
166
+
if (xfer->tx_buf || (xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM))
208
167
flags |= SPI_ENGINE_TRANSFER_WRITE;
209
-
if (xfer->rx_buf)
168
+
if (xfer->rx_buf || (xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM))
210
169
flags |= SPI_ENGINE_TRANSFER_READ;
211
170
212
171
spi_engine_program_add_cmd(p, dry,
···
258
217
*
259
218
* NB: This is separate from spi_engine_compile_message() because the latter
260
219
* is called twice and would otherwise result in double-evaluation.
220
+
*
221
+
* Returns 0 on success, -EINVAL on failure.
261
222
*/
262
-
static void spi_engine_precompile_message(struct spi_message *msg)
223
+
static int spi_engine_precompile_message(struct spi_message *msg)
263
224
{
264
225
unsigned int clk_div, max_hz = msg->spi->controller->max_speed_hz;
265
226
struct spi_transfer *xfer;
266
227
267
228
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
229
+
/* If we have an offload transfer, we can't rx to buffer */
230
+
if (msg->offload && xfer->rx_buf)
231
+
return -EINVAL;
232
+
268
233
clk_div = DIV_ROUND_UP(max_hz, xfer->speed_hz);
269
234
xfer->effective_speed_hz = max_hz / min(clk_div, 256U);
270
235
}
236
+
237
+
return 0;
271
238
}
272
239
273
240
static void spi_engine_compile_message(struct spi_message *msg, bool dry,
···
570
521
return IRQ_HANDLED;
571
522
}
572
523
524
+
static int spi_engine_offload_prepare(struct spi_message *msg)
525
+
{
526
+
struct spi_controller *host = msg->spi->controller;
527
+
struct spi_engine *spi_engine = spi_controller_get_devdata(host);
528
+
struct spi_engine_program *p = msg->opt_state;
529
+
struct spi_engine_offload *priv = msg->offload->priv;
530
+
struct spi_transfer *xfer;
531
+
void __iomem *cmd_addr;
532
+
void __iomem *sdo_addr;
533
+
size_t tx_word_count = 0;
534
+
unsigned int i;
535
+
536
+
if (p->length > spi_engine->offload_ctrl_mem_size)
537
+
return -EINVAL;
538
+
539
+
/* count total number of tx words in message */
540
+
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
541
+
/* no support for reading to rx_buf */
542
+
if (xfer->rx_buf)
543
+
return -EINVAL;
544
+
545
+
if (!xfer->tx_buf)
546
+
continue;
547
+
548
+
if (xfer->bits_per_word <= 8)
549
+
tx_word_count += xfer->len;
550
+
else if (xfer->bits_per_word <= 16)
551
+
tx_word_count += xfer->len / 2;
552
+
else
553
+
tx_word_count += xfer->len / 4;
554
+
}
555
+
556
+
if (tx_word_count && !(spi_engine->offload_caps & SPI_OFFLOAD_CAP_TX_STATIC_DATA))
557
+
return -EINVAL;
558
+
559
+
if (tx_word_count > spi_engine->offload_sdo_mem_size)
560
+
return -EINVAL;
561
+
562
+
/*
563
+
* This protects against calling spi_optimize_message() with an offload
564
+
* that has already been prepared with a different message.
565
+
*/
566
+
if (test_and_set_bit_lock(SPI_ENGINE_OFFLOAD_FLAG_PREPARED, &priv->flags))
567
+
return -EBUSY;
568
+
569
+
cmd_addr = spi_engine->base +
570
+
SPI_ENGINE_REG_OFFLOAD_CMD_FIFO(priv->offload_num);
571
+
sdo_addr = spi_engine->base +
572
+
SPI_ENGINE_REG_OFFLOAD_SDO_FIFO(priv->offload_num);
573
+
574
+
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
575
+
if (!xfer->tx_buf)
576
+
continue;
577
+
578
+
if (xfer->bits_per_word <= 8) {
579
+
const u8 *buf = xfer->tx_buf;
580
+
581
+
for (i = 0; i < xfer->len; i++)
582
+
writel_relaxed(buf[i], sdo_addr);
583
+
} else if (xfer->bits_per_word <= 16) {
584
+
const u16 *buf = xfer->tx_buf;
585
+
586
+
for (i = 0; i < xfer->len / 2; i++)
587
+
writel_relaxed(buf[i], sdo_addr);
588
+
} else {
589
+
const u32 *buf = xfer->tx_buf;
590
+
591
+
for (i = 0; i < xfer->len / 4; i++)
592
+
writel_relaxed(buf[i], sdo_addr);
593
+
}
594
+
}
595
+
596
+
for (i = 0; i < p->length; i++)
597
+
writel_relaxed(p->instructions[i], cmd_addr);
598
+
599
+
return 0;
600
+
}
601
+
602
+
static void spi_engine_offload_unprepare(struct spi_offload *offload)
603
+
{
604
+
struct spi_engine_offload *priv = offload->priv;
605
+
struct spi_engine *spi_engine = priv->spi_engine;
606
+
607
+
writel_relaxed(1, spi_engine->base +
608
+
SPI_ENGINE_REG_OFFLOAD_RESET(priv->offload_num));
609
+
writel_relaxed(0, spi_engine->base +
610
+
SPI_ENGINE_REG_OFFLOAD_RESET(priv->offload_num));
611
+
612
+
clear_bit_unlock(SPI_ENGINE_OFFLOAD_FLAG_PREPARED, &priv->flags);
613
+
}
614
+
573
615
static int spi_engine_optimize_message(struct spi_message *msg)
574
616
{
575
617
struct spi_engine_program p_dry, *p;
618
+
int ret;
576
619
577
-
spi_engine_precompile_message(msg);
620
+
ret = spi_engine_precompile_message(msg);
621
+
if (ret)
622
+
return ret;
578
623
579
624
p_dry.length = 0;
580
625
spi_engine_compile_message(msg, true, &p_dry);
···
680
537
spi_engine_compile_message(msg, false, p);
681
538
682
539
spi_engine_program_add_cmd(p, false, SPI_ENGINE_CMD_SYNC(
683
-
AXI_SPI_ENGINE_CUR_MSG_SYNC_ID));
540
+
msg->offload ? 0 : AXI_SPI_ENGINE_CUR_MSG_SYNC_ID));
684
541
685
542
msg->opt_state = p;
543
+
544
+
if (msg->offload) {
545
+
ret = spi_engine_offload_prepare(msg);
546
+
if (ret) {
547
+
msg->opt_state = NULL;
548
+
kfree(p);
549
+
return ret;
550
+
}
551
+
}
686
552
687
553
return 0;
688
554
}
689
555
690
556
static int spi_engine_unoptimize_message(struct spi_message *msg)
691
557
{
558
+
if (msg->offload)
559
+
spi_engine_offload_unprepare(msg->offload);
560
+
692
561
kfree(msg->opt_state);
693
562
694
563
return 0;
564
+
}
565
+
566
+
static struct spi_offload
567
+
*spi_engine_get_offload(struct spi_device *spi,
568
+
const struct spi_offload_config *config)
569
+
{
570
+
struct spi_controller *host = spi->controller;
571
+
struct spi_engine *spi_engine = spi_controller_get_devdata(host);
572
+
struct spi_engine_offload *priv;
573
+
574
+
if (!spi_engine->offload)
575
+
return ERR_PTR(-ENODEV);
576
+
577
+
if (config->capability_flags & ~spi_engine->offload_caps)
578
+
return ERR_PTR(-EINVAL);
579
+
580
+
priv = spi_engine->offload->priv;
581
+
582
+
if (test_and_set_bit_lock(SPI_ENGINE_OFFLOAD_FLAG_ASSIGNED, &priv->flags))
583
+
return ERR_PTR(-EBUSY);
584
+
585
+
return spi_engine->offload;
586
+
}
587
+
588
+
static void spi_engine_put_offload(struct spi_offload *offload)
589
+
{
590
+
struct spi_engine_offload *priv = offload->priv;
591
+
592
+
clear_bit_unlock(SPI_ENGINE_OFFLOAD_FLAG_ASSIGNED, &priv->flags);
695
593
}
696
594
697
595
static int spi_engine_setup(struct spi_device *device)
···
766
582
struct spi_engine_program *p = msg->opt_state;
767
583
unsigned int int_enable = 0;
768
584
unsigned long flags;
585
+
586
+
if (msg->offload) {
587
+
dev_err(&host->dev, "Single transfer offload not supported\n");
588
+
msg->status = -EOPNOTSUPP;
589
+
goto out;
590
+
}
769
591
770
592
/* reinitialize message state for this transfer */
771
593
memset(st, 0, sizeof(*st));
···
822
632
trace_spi_transfer_stop(msg, xfer);
823
633
}
824
634
635
+
out:
825
636
spi_finalize_current_message(host);
826
637
827
638
return msg->status;
828
639
}
640
+
641
+
static int spi_engine_trigger_enable(struct spi_offload *offload)
642
+
{
643
+
struct spi_engine_offload *priv = offload->priv;
644
+
struct spi_engine *spi_engine = priv->spi_engine;
645
+
unsigned int reg;
646
+
647
+
reg = readl_relaxed(spi_engine->base +
648
+
SPI_ENGINE_REG_OFFLOAD_CTRL(priv->offload_num));
649
+
reg |= SPI_ENGINE_OFFLOAD_CTRL_ENABLE;
650
+
writel_relaxed(reg, spi_engine->base +
651
+
SPI_ENGINE_REG_OFFLOAD_CTRL(priv->offload_num));
652
+
return 0;
653
+
}
654
+
655
+
static void spi_engine_trigger_disable(struct spi_offload *offload)
656
+
{
657
+
struct spi_engine_offload *priv = offload->priv;
658
+
struct spi_engine *spi_engine = priv->spi_engine;
659
+
unsigned int reg;
660
+
661
+
reg = readl_relaxed(spi_engine->base +
662
+
SPI_ENGINE_REG_OFFLOAD_CTRL(priv->offload_num));
663
+
reg &= ~SPI_ENGINE_OFFLOAD_CTRL_ENABLE;
664
+
writel_relaxed(reg, spi_engine->base +
665
+
SPI_ENGINE_REG_OFFLOAD_CTRL(priv->offload_num));
666
+
}
667
+
668
+
static struct dma_chan
669
+
*spi_engine_tx_stream_request_dma_chan(struct spi_offload *offload)
670
+
{
671
+
struct spi_engine_offload *priv = offload->priv;
672
+
char name[16];
673
+
674
+
snprintf(name, sizeof(name), "offload%u-tx", priv->offload_num);
675
+
676
+
return dma_request_chan(offload->provider_dev, name);
677
+
}
678
+
679
+
static struct dma_chan
680
+
*spi_engine_rx_stream_request_dma_chan(struct spi_offload *offload)
681
+
{
682
+
struct spi_engine_offload *priv = offload->priv;
683
+
char name[16];
684
+
685
+
snprintf(name, sizeof(name), "offload%u-rx", priv->offload_num);
686
+
687
+
return dma_request_chan(offload->provider_dev, name);
688
+
}
689
+
690
+
static const struct spi_offload_ops spi_engine_offload_ops = {
691
+
.trigger_enable = spi_engine_trigger_enable,
692
+
.trigger_disable = spi_engine_trigger_disable,
693
+
.tx_stream_request_dma_chan = spi_engine_tx_stream_request_dma_chan,
694
+
.rx_stream_request_dma_chan = spi_engine_rx_stream_request_dma_chan,
695
+
};
829
696
830
697
static void spi_engine_release_hw(void *p)
831
698
{
···
898
651
struct spi_engine *spi_engine;
899
652
struct spi_controller *host;
900
653
unsigned int version;
901
-
int irq;
902
-
int ret;
654
+
int irq, ret;
903
655
904
656
irq = platform_get_irq(pdev, 0);
905
657
if (irq < 0)
···
912
666
913
667
spin_lock_init(&spi_engine->lock);
914
668
init_completion(&spi_engine->msg_complete);
669
+
670
+
/*
671
+
* REVISIT: for now, all SPI Engines only have one offload. In the
672
+
* future, this should be read from a memory mapped register to
673
+
* determine the number of offloads enabled at HDL compile time. For
674
+
* now, we can tell if an offload is present if there is a trigger
675
+
* source wired up to it.
676
+
*/
677
+
if (device_property_present(&pdev->dev, "trigger-sources")) {
678
+
struct spi_engine_offload *priv;
679
+
680
+
spi_engine->offload =
681
+
devm_spi_offload_alloc(&pdev->dev,
682
+
sizeof(struct spi_engine_offload));
683
+
if (IS_ERR(spi_engine->offload))
684
+
return PTR_ERR(spi_engine->offload);
685
+
686
+
priv = spi_engine->offload->priv;
687
+
priv->spi_engine = spi_engine;
688
+
priv->offload_num = 0;
689
+
690
+
spi_engine->offload->ops = &spi_engine_offload_ops;
691
+
spi_engine->offload_caps = SPI_OFFLOAD_CAP_TRIGGER;
692
+
693
+
if (device_property_match_string(&pdev->dev, "dma-names", "offload0-rx") >= 0) {
694
+
spi_engine->offload_caps |= SPI_OFFLOAD_CAP_RX_STREAM_DMA;
695
+
spi_engine->offload->xfer_flags |= SPI_OFFLOAD_XFER_RX_STREAM;
696
+
}
697
+
698
+
if (device_property_match_string(&pdev->dev, "dma-names", "offload0-tx") >= 0) {
699
+
spi_engine->offload_caps |= SPI_OFFLOAD_CAP_TX_STREAM_DMA;
700
+
spi_engine->offload->xfer_flags |= SPI_OFFLOAD_XFER_TX_STREAM;
701
+
} else {
702
+
/*
703
+
* HDL compile option to enable TX DMA stream also disables
704
+
* the SDO memory, so can't do both at the same time.
705
+
*/
706
+
spi_engine->offload_caps |= SPI_OFFLOAD_CAP_TX_STATIC_DATA;
707
+
}
708
+
}
915
709
916
710
spi_engine->clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
917
711
if (IS_ERR(spi_engine->clk))
···
972
686
ADI_AXI_PCORE_VER_MINOR(version),
973
687
ADI_AXI_PCORE_VER_PATCH(version));
974
688
return -ENODEV;
689
+
}
690
+
691
+
if (ADI_AXI_PCORE_VER_MINOR(version) >= 1) {
692
+
unsigned int sizes = readl(spi_engine->base +
693
+
SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH);
694
+
695
+
spi_engine->offload_ctrl_mem_size = 1 <<
696
+
FIELD_GET(SPI_ENGINE_SPI_OFFLOAD_MEM_WIDTH_CMD, sizes);
697
+
spi_engine->offload_sdo_mem_size = 1 <<
698
+
FIELD_GET(SPI_ENGINE_SPI_OFFLOAD_MEM_WIDTH_SDO, sizes);
699
+
} else {
700
+
spi_engine->offload_ctrl_mem_size = SPI_ENGINE_OFFLOAD_CMD_FIFO_SIZE;
701
+
spi_engine->offload_sdo_mem_size = SPI_ENGINE_OFFLOAD_SDO_FIFO_SIZE;
975
702
}
976
703
977
704
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET);
···
1008
709
host->transfer_one_message = spi_engine_transfer_one_message;
1009
710
host->optimize_message = spi_engine_optimize_message;
1010
711
host->unoptimize_message = spi_engine_unoptimize_message;
712
+
host->get_offload = spi_engine_get_offload;
713
+
host->put_offload = spi_engine_put_offload;
1011
714
host->num_chipselect = 8;
1012
715
1013
716
/* Some features depend of the IP core version. */
+7
-1
drivers/spi/spi-cadence-quadspi.c
+7
-1
drivers/spi/spi-cadence-quadspi.c
···
1658
1658
int ret = PTR_ERR(cqspi->rx_chan);
1659
1659
1660
1660
cqspi->rx_chan = NULL;
1661
+
if (ret == -ENODEV) {
1662
+
/* DMA support is not mandatory */
1663
+
dev_info(&cqspi->pdev->dev, "No Rx DMA available\n");
1664
+
return 0;
1665
+
}
1666
+
1661
1667
return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1662
1668
}
1663
1669
init_completion(&cqspi->rx_dma_complete);
···
2073
2067
2074
2068
static const struct cqspi_driver_platdata am654_ospi = {
2075
2069
.hwcaps_mask = CQSPI_SUPPORTS_OCTAL | CQSPI_SUPPORTS_QUAD,
2076
-
.quirks = CQSPI_NEEDS_WR_DELAY,
2070
+
.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NEEDS_WR_DELAY,
2077
2071
};
2078
2072
2079
2073
static const struct cqspi_driver_platdata intel_lgm_qspi = {
+13
drivers/spi/spi-fsi.c
+13
drivers/spi/spi-fsi.c
···
479
479
480
480
shift = SPI_FSI_SEQUENCE_SHIFT_IN(next->len);
481
481
fsi_spi_sequence_add(&seq, shift);
482
+
} else if (next->tx_buf) {
483
+
if ((next->len + transfer->len) > (SPI_FSI_MAX_TX_SIZE + 8)) {
484
+
rc = -EINVAL;
485
+
goto error;
486
+
}
487
+
488
+
len = next->len;
489
+
while (len > 8) {
490
+
fsi_spi_sequence_add(&seq,
491
+
SPI_FSI_SEQUENCE_SHIFT_OUT(8));
492
+
len -= 8;
493
+
}
494
+
fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SHIFT_OUT(len));
482
495
} else {
483
496
next = NULL;
484
497
}
+1
-1
drivers/spi/spi-fsl-lpspi.c
+1
-1
drivers/spi/spi-fsl-lpspi.c
+7
-38
drivers/spi/spi-gpio.c
+7
-38
drivers/spi/spi-gpio.c
···
39
39
40
40
/*----------------------------------------------------------------------*/
41
41
42
-
/*
43
-
* Because the overhead of going through four GPIO procedure calls
44
-
* per transferred bit can make performance a problem, this code
45
-
* is set up so that you can use it in either of two ways:
46
-
*
47
-
* - The slow generic way: set up platform_data to hold the GPIO
48
-
* numbers used for MISO/MOSI/SCK, and issue procedure calls for
49
-
* each of them. This driver can handle several such busses.
50
-
*
51
-
* - The quicker inlined way: only helps with platform GPIO code
52
-
* that inlines operations for constant GPIOs. This can give
53
-
* you tight (fast!) inner loops, but each such bus needs a
54
-
* new driver. You'll define a new C file, with Makefile and
55
-
* Kconfig support; the C code can be a total of six lines:
56
-
*
57
-
* #define DRIVER_NAME "myboard_spi2"
58
-
* #define SPI_MISO_GPIO 119
59
-
* #define SPI_MOSI_GPIO 120
60
-
* #define SPI_SCK_GPIO 121
61
-
* #define SPI_N_CHIPSEL 4
62
-
* #include "spi-gpio.c"
63
-
*/
64
-
65
-
#ifndef DRIVER_NAME
66
42
#define DRIVER_NAME "spi_gpio"
67
-
68
-
#define GENERIC_BITBANG /* vs tight inlines */
69
-
70
-
#endif
71
43
72
44
/*----------------------------------------------------------------------*/
73
45
···
313
341
struct spi_gpio *spi_gpio = spi_controller_get_devdata(host);
314
342
int i;
315
343
316
-
#ifdef GENERIC_BITBANG
317
-
if (!pdata || !pdata->num_chipselect)
344
+
if (!pdata)
318
345
return -ENODEV;
319
-
#endif
320
-
/*
321
-
* The host needs to think there is a chipselect even if not
322
-
* connected
323
-
*/
324
-
host->num_chipselect = pdata->num_chipselect ?: 1;
325
346
347
+
/* It's just one always-selected device, fine to continue */
348
+
if (!pdata->num_chipselect)
349
+
return 0;
350
+
351
+
host->num_chipselect = pdata->num_chipselect;
326
352
spi_gpio->cs_gpios = devm_kcalloc(dev, host->num_chipselect,
327
353
sizeof(*spi_gpio->cs_gpios),
328
354
GFP_KERNEL);
···
415
445
return devm_spi_register_controller(&pdev->dev, host);
416
446
}
417
447
418
-
MODULE_ALIAS("platform:" DRIVER_NAME);
419
-
420
448
static const struct of_device_id spi_gpio_dt_ids[] = {
421
449
{ .compatible = "spi-gpio" },
422
450
{}
···
433
465
MODULE_DESCRIPTION("SPI host driver using generic bitbanged GPIO ");
434
466
MODULE_AUTHOR("David Brownell");
435
467
MODULE_LICENSE("GPL");
468
+
MODULE_ALIAS("platform:" DRIVER_NAME);
+1
-1
drivers/spi/spi-imx.c
+1
-1
drivers/spi/spi-imx.c
+11
drivers/spi/spi-mem.c
+11
drivers/spi/spi-mem.c
···
377
377
/* Make sure the operation frequency is correct before going futher */
378
378
spi_mem_adjust_op_freq(mem, (struct spi_mem_op *)op);
379
379
380
+
dev_vdbg(&mem->spi->dev, "[cmd: 0x%02x][%dB addr: %#8llx][%2dB dummy][%4dB data %s] %d%c-%d%c-%d%c-%d%c @ %uHz\n",
381
+
op->cmd.opcode,
382
+
op->addr.nbytes, (op->addr.nbytes ? op->addr.val : 0),
383
+
op->dummy.nbytes,
384
+
op->data.nbytes, (op->data.nbytes ? (op->data.dir == SPI_MEM_DATA_IN ? " read" : "write") : " "),
385
+
op->cmd.buswidth, op->cmd.dtr ? 'D' : 'S',
386
+
op->addr.buswidth, op->addr.dtr ? 'D' : 'S',
387
+
op->dummy.buswidth, op->dummy.dtr ? 'D' : 'S',
388
+
op->data.buswidth, op->data.dtr ? 'D' : 'S',
389
+
op->max_freq ? op->max_freq : mem->spi->max_speed_hz);
390
+
380
391
ret = spi_mem_check_op(op);
381
392
if (ret)
382
393
return ret;
+17
drivers/spi/spi-mt65xx.c
+17
drivers/spi/spi-mt65xx.c
···
20
20
#include <linux/spi/spi.h>
21
21
#include <linux/spi/spi-mem.h>
22
22
#include <linux/dma-mapping.h>
23
+
#include <linux/pm_qos.h>
23
24
24
25
#define SPI_CFG0_REG 0x0000
25
26
#define SPI_CFG1_REG 0x0004
···
148
147
* @tx_sgl_len: Size of TX DMA transfer
149
148
* @rx_sgl_len: Size of RX DMA transfer
150
149
* @dev_comp: Device data structure
150
+
* @qos_request: QoS request
151
151
* @spi_clk_hz: Current SPI clock in Hz
152
152
* @spimem_done: SPI-MEM operation completion
153
153
* @use_spimem: Enables SPI-MEM
···
168
166
struct scatterlist *tx_sgl, *rx_sgl;
169
167
u32 tx_sgl_len, rx_sgl_len;
170
168
const struct mtk_spi_compatible *dev_comp;
169
+
struct pm_qos_request qos_request;
171
170
u32 spi_clk_hz;
172
171
struct completion spimem_done;
173
172
bool use_spimem;
···
359
356
struct mtk_chip_config *chip_config = spi->controller_data;
360
357
struct mtk_spi *mdata = spi_controller_get_devdata(host);
361
358
359
+
cpu_latency_qos_update_request(&mdata->qos_request, 500);
362
360
cpha = spi->mode & SPI_CPHA ? 1 : 0;
363
361
cpol = spi->mode & SPI_CPOL ? 1 : 0;
364
362
···
461
457
struct spi_message *msg)
462
458
{
463
459
return mtk_spi_hw_init(host, msg->spi);
460
+
}
461
+
462
+
static int mtk_spi_unprepare_message(struct spi_controller *host,
463
+
struct spi_message *message)
464
+
{
465
+
struct mtk_spi *mdata = spi_controller_get_devdata(host);
466
+
467
+
cpu_latency_qos_update_request(&mdata->qos_request, PM_QOS_DEFAULT_VALUE);
468
+
return 0;
464
469
}
465
470
466
471
static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
···
1156
1143
1157
1144
host->set_cs = mtk_spi_set_cs;
1158
1145
host->prepare_message = mtk_spi_prepare_message;
1146
+
host->unprepare_message = mtk_spi_unprepare_message;
1159
1147
host->transfer_one = mtk_spi_transfer_one;
1160
1148
host->can_dma = mtk_spi_can_dma;
1161
1149
host->setup = mtk_spi_setup;
···
1263
1249
clk_disable_unprepare(mdata->spi_hclk);
1264
1250
}
1265
1251
1252
+
cpu_latency_qos_add_request(&mdata->qos_request, PM_QOS_DEFAULT_VALUE);
1253
+
1266
1254
if (mdata->dev_comp->need_pad_sel) {
1267
1255
if (mdata->pad_num != host->num_chipselect)
1268
1256
return dev_err_probe(dev, -EINVAL,
···
1308
1292
struct mtk_spi *mdata = spi_controller_get_devdata(host);
1309
1293
int ret;
1310
1294
1295
+
cpu_latency_qos_remove_request(&mdata->qos_request);
1311
1296
if (mdata->use_spimem && !completion_done(&mdata->spimem_done))
1312
1297
complete(&mdata->spimem_done);
1313
1298
-3
drivers/spi/spi-mtk-snfi.c
-3
drivers/spi/spi-mtk-snfi.c
···
1284
1284
{
1285
1285
struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->controller);
1286
1286
1287
-
dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
1288
-
op->addr.val, op->addr.buswidth, op->addr.nbytes,
1289
-
op->data.buswidth, op->data.nbytes);
1290
1287
if (mtk_snand_is_page_ops(op)) {
1291
1288
if (op->data.dir == SPI_MEM_DATA_IN)
1292
1289
return mtk_snand_read_page_cache(ms, op);
+1
-3
drivers/spi/spi-mux.c
+1
-3
drivers/spi/spi-mux.c
-5
drivers/spi/spi-npcm-fiu.c
-5
drivers/spi/spi-npcm-fiu.c
···
550
550
int ret = 0;
551
551
u8 *buf;
552
552
553
-
dev_dbg(fiu->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
554
-
op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
555
-
op->dummy.buswidth, op->data.buswidth, op->addr.val,
556
-
op->data.nbytes);
557
-
558
553
if (fiu->spix_mode || op->addr.nbytes > 4)
559
554
return -EOPNOTSUPP;
560
555
+169
drivers/spi/spi-offload-trigger-pwm.c
+169
drivers/spi/spi-offload-trigger-pwm.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) 2024 Analog Devices Inc.
4
+
* Copyright (C) 2024 BayLibre, SAS
5
+
*
6
+
* Generic PWM trigger for SPI offload.
7
+
*/
8
+
9
+
#include <linux/device.h>
10
+
#include <linux/err.h>
11
+
#include <linux/math.h>
12
+
#include <linux/mod_devicetable.h>
13
+
#include <linux/module.h>
14
+
#include <linux/platform_device.h>
15
+
#include <linux/property.h>
16
+
#include <linux/pwm.h>
17
+
#include <linux/spi/offload/provider.h>
18
+
#include <linux/spi/offload/types.h>
19
+
#include <linux/time.h>
20
+
#include <linux/types.h>
21
+
22
+
struct spi_offload_trigger_pwm_state {
23
+
struct device *dev;
24
+
struct pwm_device *pwm;
25
+
};
26
+
27
+
static bool spi_offload_trigger_pwm_match(struct spi_offload_trigger *trigger,
28
+
enum spi_offload_trigger_type type,
29
+
u64 *args, u32 nargs)
30
+
{
31
+
if (nargs)
32
+
return false;
33
+
34
+
return type == SPI_OFFLOAD_TRIGGER_PERIODIC;
35
+
}
36
+
37
+
static int spi_offload_trigger_pwm_validate(struct spi_offload_trigger *trigger,
38
+
struct spi_offload_trigger_config *config)
39
+
{
40
+
struct spi_offload_trigger_pwm_state *st = spi_offload_trigger_get_priv(trigger);
41
+
struct spi_offload_trigger_periodic *periodic = &config->periodic;
42
+
struct pwm_waveform wf = { };
43
+
int ret;
44
+
45
+
if (config->type != SPI_OFFLOAD_TRIGGER_PERIODIC)
46
+
return -EINVAL;
47
+
48
+
if (!periodic->frequency_hz)
49
+
return -EINVAL;
50
+
51
+
wf.period_length_ns = DIV_ROUND_UP_ULL(NSEC_PER_SEC, periodic->frequency_hz);
52
+
/* REVISIT: 50% duty-cycle for now - may add config parameter later */
53
+
wf.duty_length_ns = wf.period_length_ns / 2;
54
+
55
+
ret = pwm_round_waveform_might_sleep(st->pwm, &wf);
56
+
if (ret < 0)
57
+
return ret;
58
+
59
+
periodic->frequency_hz = DIV_ROUND_UP_ULL(NSEC_PER_SEC, wf.period_length_ns);
60
+
61
+
return 0;
62
+
}
63
+
64
+
static int spi_offload_trigger_pwm_enable(struct spi_offload_trigger *trigger,
65
+
struct spi_offload_trigger_config *config)
66
+
{
67
+
struct spi_offload_trigger_pwm_state *st = spi_offload_trigger_get_priv(trigger);
68
+
struct spi_offload_trigger_periodic *periodic = &config->periodic;
69
+
struct pwm_waveform wf = { };
70
+
71
+
if (config->type != SPI_OFFLOAD_TRIGGER_PERIODIC)
72
+
return -EINVAL;
73
+
74
+
if (!periodic->frequency_hz)
75
+
return -EINVAL;
76
+
77
+
wf.period_length_ns = DIV_ROUND_UP_ULL(NSEC_PER_SEC, periodic->frequency_hz);
78
+
/* REVISIT: 50% duty-cycle for now - may add config parameter later */
79
+
wf.duty_length_ns = wf.period_length_ns / 2;
80
+
81
+
return pwm_set_waveform_might_sleep(st->pwm, &wf, false);
82
+
}
83
+
84
+
static void spi_offload_trigger_pwm_disable(struct spi_offload_trigger *trigger)
85
+
{
86
+
struct spi_offload_trigger_pwm_state *st = spi_offload_trigger_get_priv(trigger);
87
+
struct pwm_waveform wf;
88
+
int ret;
89
+
90
+
ret = pwm_get_waveform_might_sleep(st->pwm, &wf);
91
+
if (ret < 0) {
92
+
dev_err(st->dev, "failed to get waveform: %d\n", ret);
93
+
return;
94
+
}
95
+
96
+
wf.duty_length_ns = 0;
97
+
98
+
ret = pwm_set_waveform_might_sleep(st->pwm, &wf, false);
99
+
if (ret < 0)
100
+
dev_err(st->dev, "failed to disable PWM: %d\n", ret);
101
+
}
102
+
103
+
static const struct spi_offload_trigger_ops spi_offload_trigger_pwm_ops = {
104
+
.match = spi_offload_trigger_pwm_match,
105
+
.validate = spi_offload_trigger_pwm_validate,
106
+
.enable = spi_offload_trigger_pwm_enable,
107
+
.disable = spi_offload_trigger_pwm_disable,
108
+
};
109
+
110
+
static void spi_offload_trigger_pwm_release(void *data)
111
+
{
112
+
pwm_disable(data);
113
+
}
114
+
115
+
static int spi_offload_trigger_pwm_probe(struct platform_device *pdev)
116
+
{
117
+
struct device *dev = &pdev->dev;
118
+
struct spi_offload_trigger_info info = {
119
+
.fwnode = dev_fwnode(dev),
120
+
.ops = &spi_offload_trigger_pwm_ops,
121
+
};
122
+
struct spi_offload_trigger_pwm_state *st;
123
+
struct pwm_state state;
124
+
int ret;
125
+
126
+
st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
127
+
if (!st)
128
+
return -ENOMEM;
129
+
130
+
info.priv = st;
131
+
st->dev = dev;
132
+
133
+
st->pwm = devm_pwm_get(dev, NULL);
134
+
if (IS_ERR(st->pwm))
135
+
return dev_err_probe(dev, PTR_ERR(st->pwm), "failed to get PWM\n");
136
+
137
+
/* init with duty_cycle = 0, output enabled to ensure trigger off */
138
+
pwm_init_state(st->pwm, &state);
139
+
state.enabled = true;
140
+
141
+
ret = pwm_apply_might_sleep(st->pwm, &state);
142
+
if (ret < 0)
143
+
return dev_err_probe(dev, ret, "failed to apply PWM state\n");
144
+
145
+
ret = devm_add_action_or_reset(dev, spi_offload_trigger_pwm_release, st->pwm);
146
+
if (ret)
147
+
return ret;
148
+
149
+
return devm_spi_offload_trigger_register(dev, &info);
150
+
}
151
+
152
+
static const struct of_device_id spi_offload_trigger_pwm_of_match_table[] = {
153
+
{ .compatible = "pwm-trigger" },
154
+
{ }
155
+
};
156
+
MODULE_DEVICE_TABLE(of, spi_offload_trigger_pwm_of_match_table);
157
+
158
+
static struct platform_driver spi_offload_trigger_pwm_driver = {
159
+
.driver = {
160
+
.name = "pwm-trigger",
161
+
.of_match_table = spi_offload_trigger_pwm_of_match_table,
162
+
},
163
+
.probe = spi_offload_trigger_pwm_probe,
164
+
};
165
+
module_platform_driver(spi_offload_trigger_pwm_driver);
166
+
167
+
MODULE_AUTHOR("David Lechner <dlechner@baylibre.com>");
168
+
MODULE_DESCRIPTION("Generic PWM trigger");
169
+
MODULE_LICENSE("GPL");
+468
drivers/spi/spi-offload.c
+468
drivers/spi/spi-offload.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) 2024 Analog Devices Inc.
4
+
* Copyright (C) 2024 BayLibre, SAS
5
+
*/
6
+
7
+
/*
8
+
* SPI Offloading support.
9
+
*
10
+
* Some SPI controllers support offloading of SPI transfers. Essentially, this
11
+
* is the ability for a SPI controller to perform SPI transfers with minimal
12
+
* or even no CPU intervention, e.g. via a specialized SPI controller with a
13
+
* hardware trigger or via a conventional SPI controller using a non-Linux MCU
14
+
* processor core to offload the work.
15
+
*/
16
+
17
+
#define DEFAULT_SYMBOL_NAMESPACE "SPI_OFFLOAD"
18
+
19
+
#include <linux/cleanup.h>
20
+
#include <linux/device.h>
21
+
#include <linux/dmaengine.h>
22
+
#include <linux/export.h>
23
+
#include <linux/kref.h>
24
+
#include <linux/list.h>
25
+
#include <linux/mutex.h>
26
+
#include <linux/of.h>
27
+
#include <linux/property.h>
28
+
#include <linux/spi/offload/consumer.h>
29
+
#include <linux/spi/offload/provider.h>
30
+
#include <linux/spi/offload/types.h>
31
+
#include <linux/spi/spi.h>
32
+
#include <linux/types.h>
33
+
34
+
struct spi_controller_and_offload {
35
+
struct spi_controller *controller;
36
+
struct spi_offload *offload;
37
+
};
38
+
39
+
struct spi_offload_trigger {
40
+
struct list_head list;
41
+
struct kref ref;
42
+
struct fwnode_handle *fwnode;
43
+
/* synchronizes calling ops and driver registration */
44
+
struct mutex lock;
45
+
/*
46
+
* If the provider goes away while the consumer still has a reference,
47
+
* ops and priv will be set to NULL and all calls will fail with -ENODEV.
48
+
*/
49
+
const struct spi_offload_trigger_ops *ops;
50
+
void *priv;
51
+
};
52
+
53
+
static LIST_HEAD(spi_offload_triggers);
54
+
static DEFINE_MUTEX(spi_offload_triggers_lock);
55
+
56
+
/**
57
+
* devm_spi_offload_alloc() - Allocate offload instance
58
+
* @dev: Device for devm purposes and assigned to &struct spi_offload.provider_dev
59
+
* @priv_size: Size of private data to allocate
60
+
*
61
+
* Offload providers should use this to allocate offload instances.
62
+
*
63
+
* Return: Pointer to new offload instance or error on failure.
64
+
*/
65
+
struct spi_offload *devm_spi_offload_alloc(struct device *dev,
66
+
size_t priv_size)
67
+
{
68
+
struct spi_offload *offload;
69
+
void *priv;
70
+
71
+
offload = devm_kzalloc(dev, sizeof(*offload), GFP_KERNEL);
72
+
if (!offload)
73
+
return ERR_PTR(-ENOMEM);
74
+
75
+
priv = devm_kzalloc(dev, priv_size, GFP_KERNEL);
76
+
if (!priv)
77
+
return ERR_PTR(-ENOMEM);
78
+
79
+
offload->provider_dev = dev;
80
+
offload->priv = priv;
81
+
82
+
return offload;
83
+
}
84
+
EXPORT_SYMBOL_GPL(devm_spi_offload_alloc);
85
+
86
+
static void spi_offload_put(void *data)
87
+
{
88
+
struct spi_controller_and_offload *resource = data;
89
+
90
+
resource->controller->put_offload(resource->offload);
91
+
kfree(resource);
92
+
}
93
+
94
+
/**
95
+
* devm_spi_offload_get() - Get an offload instance
96
+
* @dev: Device for devm purposes
97
+
* @spi: SPI device to use for the transfers
98
+
* @config: Offload configuration
99
+
*
100
+
* Peripheral drivers call this function to get an offload instance that meets
101
+
* the requirements specified in @config. If no suitable offload instance is
102
+
* available, -ENODEV is returned.
103
+
*
104
+
* Return: Offload instance or error on failure.
105
+
*/
106
+
struct spi_offload *devm_spi_offload_get(struct device *dev,
107
+
struct spi_device *spi,
108
+
const struct spi_offload_config *config)
109
+
{
110
+
struct spi_controller_and_offload *resource;
111
+
struct spi_offload *offload;
112
+
int ret;
113
+
114
+
if (!spi || !config)
115
+
return ERR_PTR(-EINVAL);
116
+
117
+
if (!spi->controller->get_offload)
118
+
return ERR_PTR(-ENODEV);
119
+
120
+
resource = kzalloc(sizeof(*resource), GFP_KERNEL);
121
+
if (!resource)
122
+
return ERR_PTR(-ENOMEM);
123
+
124
+
offload = spi->controller->get_offload(spi, config);
125
+
if (IS_ERR(offload)) {
126
+
kfree(resource);
127
+
return offload;
128
+
}
129
+
130
+
resource->controller = spi->controller;
131
+
resource->offload = offload;
132
+
133
+
ret = devm_add_action_or_reset(dev, spi_offload_put, resource);
134
+
if (ret)
135
+
return ERR_PTR(ret);
136
+
137
+
return offload;
138
+
}
139
+
EXPORT_SYMBOL_GPL(devm_spi_offload_get);
140
+
141
+
static void spi_offload_trigger_free(struct kref *ref)
142
+
{
143
+
struct spi_offload_trigger *trigger =
144
+
container_of(ref, struct spi_offload_trigger, ref);
145
+
146
+
mutex_destroy(&trigger->lock);
147
+
fwnode_handle_put(trigger->fwnode);
148
+
kfree(trigger);
149
+
}
150
+
151
+
static void spi_offload_trigger_put(void *data)
152
+
{
153
+
struct spi_offload_trigger *trigger = data;
154
+
155
+
scoped_guard(mutex, &trigger->lock)
156
+
if (trigger->ops && trigger->ops->release)
157
+
trigger->ops->release(trigger);
158
+
159
+
kref_put(&trigger->ref, spi_offload_trigger_free);
160
+
}
161
+
162
+
static struct spi_offload_trigger
163
+
*spi_offload_trigger_get(enum spi_offload_trigger_type type,
164
+
struct fwnode_reference_args *args)
165
+
{
166
+
struct spi_offload_trigger *trigger;
167
+
bool match = false;
168
+
int ret;
169
+
170
+
guard(mutex)(&spi_offload_triggers_lock);
171
+
172
+
list_for_each_entry(trigger, &spi_offload_triggers, list) {
173
+
if (trigger->fwnode != args->fwnode)
174
+
continue;
175
+
176
+
match = trigger->ops->match(trigger, type, args->args, args->nargs);
177
+
if (match)
178
+
break;
179
+
}
180
+
181
+
if (!match)
182
+
return ERR_PTR(-EPROBE_DEFER);
183
+
184
+
guard(mutex)(&trigger->lock);
185
+
186
+
if (!trigger->ops)
187
+
return ERR_PTR(-ENODEV);
188
+
189
+
if (trigger->ops->request) {
190
+
ret = trigger->ops->request(trigger, type, args->args, args->nargs);
191
+
if (ret)
192
+
return ERR_PTR(ret);
193
+
}
194
+
195
+
kref_get(&trigger->ref);
196
+
197
+
return trigger;
198
+
}
199
+
200
+
/**
201
+
* devm_spi_offload_trigger_get() - Get an offload trigger instance
202
+
* @dev: Device for devm purposes.
203
+
* @offload: Offload instance connected to a trigger.
204
+
* @type: Trigger type to get.
205
+
*
206
+
* Return: Offload trigger instance or error on failure.
207
+
*/
208
+
struct spi_offload_trigger
209
+
*devm_spi_offload_trigger_get(struct device *dev,
210
+
struct spi_offload *offload,
211
+
enum spi_offload_trigger_type type)
212
+
{
213
+
struct spi_offload_trigger *trigger;
214
+
struct fwnode_reference_args args;
215
+
int ret;
216
+
217
+
ret = fwnode_property_get_reference_args(dev_fwnode(offload->provider_dev),
218
+
"trigger-sources",
219
+
"#trigger-source-cells", 0, 0,
220
+
&args);
221
+
if (ret)
222
+
return ERR_PTR(ret);
223
+
224
+
trigger = spi_offload_trigger_get(type, &args);
225
+
fwnode_handle_put(args.fwnode);
226
+
if (IS_ERR(trigger))
227
+
return trigger;
228
+
229
+
ret = devm_add_action_or_reset(dev, spi_offload_trigger_put, trigger);
230
+
if (ret)
231
+
return ERR_PTR(ret);
232
+
233
+
return trigger;
234
+
}
235
+
EXPORT_SYMBOL_GPL(devm_spi_offload_trigger_get);
236
+
237
+
/**
238
+
* spi_offload_trigger_validate - Validate the requested trigger
239
+
* @trigger: Offload trigger instance
240
+
* @config: Trigger config to validate
241
+
*
242
+
* On success, @config may be modifed to reflect what the hardware can do.
243
+
* For example, the frequency of a periodic trigger may be adjusted to the
244
+
* nearest supported value.
245
+
*
246
+
* Callers will likely need to do additional validation of the modified trigger
247
+
* parameters.
248
+
*
249
+
* Return: 0 on success, negative error code on failure.
250
+
*/
251
+
int spi_offload_trigger_validate(struct spi_offload_trigger *trigger,
252
+
struct spi_offload_trigger_config *config)
253
+
{
254
+
guard(mutex)(&trigger->lock);
255
+
256
+
if (!trigger->ops)
257
+
return -ENODEV;
258
+
259
+
if (!trigger->ops->validate)
260
+
return -EOPNOTSUPP;
261
+
262
+
return trigger->ops->validate(trigger, config);
263
+
}
264
+
EXPORT_SYMBOL_GPL(spi_offload_trigger_validate);
265
+
266
+
/**
267
+
* spi_offload_trigger_enable - enables trigger for offload
268
+
* @offload: Offload instance
269
+
* @trigger: Offload trigger instance
270
+
* @config: Trigger config to validate
271
+
*
272
+
* There must be a prepared offload instance with the specified ID (i.e.
273
+
* spi_optimize_message() was called with the same offload assigned to the
274
+
* message). This will also reserve the bus for exclusive use by the offload
275
+
* instance until the trigger is disabled. Any other attempts to send a
276
+
* transfer or lock the bus will fail with -EBUSY during this time.
277
+
*
278
+
* Calls must be balanced with spi_offload_trigger_disable().
279
+
*
280
+
* Context: can sleep
281
+
* Return: 0 on success, else a negative error code.
282
+
*/
283
+
int spi_offload_trigger_enable(struct spi_offload *offload,
284
+
struct spi_offload_trigger *trigger,
285
+
struct spi_offload_trigger_config *config)
286
+
{
287
+
int ret;
288
+
289
+
guard(mutex)(&trigger->lock);
290
+
291
+
if (!trigger->ops)
292
+
return -ENODEV;
293
+
294
+
if (offload->ops && offload->ops->trigger_enable) {
295
+
ret = offload->ops->trigger_enable(offload);
296
+
if (ret)
297
+
return ret;
298
+
}
299
+
300
+
if (trigger->ops->enable) {
301
+
ret = trigger->ops->enable(trigger, config);
302
+
if (ret) {
303
+
if (offload->ops->trigger_disable)
304
+
offload->ops->trigger_disable(offload);
305
+
return ret;
306
+
}
307
+
}
308
+
309
+
return 0;
310
+
}
311
+
EXPORT_SYMBOL_GPL(spi_offload_trigger_enable);
312
+
313
+
/**
314
+
* spi_offload_trigger_disable - disables hardware trigger for offload
315
+
* @offload: Offload instance
316
+
* @trigger: Offload trigger instance
317
+
*
318
+
* Disables the hardware trigger for the offload instance with the specified ID
319
+
* and releases the bus for use by other clients.
320
+
*
321
+
* Context: can sleep
322
+
*/
323
+
void spi_offload_trigger_disable(struct spi_offload *offload,
324
+
struct spi_offload_trigger *trigger)
325
+
{
326
+
if (offload->ops && offload->ops->trigger_disable)
327
+
offload->ops->trigger_disable(offload);
328
+
329
+
guard(mutex)(&trigger->lock);
330
+
331
+
if (!trigger->ops)
332
+
return;
333
+
334
+
if (trigger->ops->disable)
335
+
trigger->ops->disable(trigger);
336
+
}
337
+
EXPORT_SYMBOL_GPL(spi_offload_trigger_disable);
338
+
339
+
static void spi_offload_release_dma_chan(void *chan)
340
+
{
341
+
dma_release_channel(chan);
342
+
}
343
+
344
+
/**
345
+
* devm_spi_offload_tx_stream_request_dma_chan - Get the DMA channel info for the TX stream
346
+
* @dev: Device for devm purposes.
347
+
* @offload: Offload instance
348
+
*
349
+
* This is the DMA channel that will provide data to transfers that use the
350
+
* %SPI_OFFLOAD_XFER_TX_STREAM offload flag.
351
+
*
352
+
* Return: Pointer to DMA channel info, or negative error code
353
+
*/
354
+
struct dma_chan
355
+
*devm_spi_offload_tx_stream_request_dma_chan(struct device *dev,
356
+
struct spi_offload *offload)
357
+
{
358
+
struct dma_chan *chan;
359
+
int ret;
360
+
361
+
if (!offload->ops || !offload->ops->tx_stream_request_dma_chan)
362
+
return ERR_PTR(-EOPNOTSUPP);
363
+
364
+
chan = offload->ops->tx_stream_request_dma_chan(offload);
365
+
if (IS_ERR(chan))
366
+
return chan;
367
+
368
+
ret = devm_add_action_or_reset(dev, spi_offload_release_dma_chan, chan);
369
+
if (ret)
370
+
return ERR_PTR(ret);
371
+
372
+
return chan;
373
+
}
374
+
EXPORT_SYMBOL_GPL(devm_spi_offload_tx_stream_request_dma_chan);
375
+
376
+
/**
377
+
* devm_spi_offload_rx_stream_request_dma_chan - Get the DMA channel info for the RX stream
378
+
* @dev: Device for devm purposes.
379
+
* @offload: Offload instance
380
+
*
381
+
* This is the DMA channel that will receive data from transfers that use the
382
+
* %SPI_OFFLOAD_XFER_RX_STREAM offload flag.
383
+
*
384
+
* Return: Pointer to DMA channel info, or negative error code
385
+
*/
386
+
struct dma_chan
387
+
*devm_spi_offload_rx_stream_request_dma_chan(struct device *dev,
388
+
struct spi_offload *offload)
389
+
{
390
+
struct dma_chan *chan;
391
+
int ret;
392
+
393
+
if (!offload->ops || !offload->ops->rx_stream_request_dma_chan)
394
+
return ERR_PTR(-EOPNOTSUPP);
395
+
396
+
chan = offload->ops->rx_stream_request_dma_chan(offload);
397
+
if (IS_ERR(chan))
398
+
return chan;
399
+
400
+
ret = devm_add_action_or_reset(dev, spi_offload_release_dma_chan, chan);
401
+
if (ret)
402
+
return ERR_PTR(ret);
403
+
404
+
return chan;
405
+
}
406
+
EXPORT_SYMBOL_GPL(devm_spi_offload_rx_stream_request_dma_chan);
407
+
408
+
/* Triggers providers */
409
+
410
+
static void spi_offload_trigger_unregister(void *data)
411
+
{
412
+
struct spi_offload_trigger *trigger = data;
413
+
414
+
scoped_guard(mutex, &spi_offload_triggers_lock)
415
+
list_del(&trigger->list);
416
+
417
+
scoped_guard(mutex, &trigger->lock) {
418
+
trigger->priv = NULL;
419
+
trigger->ops = NULL;
420
+
}
421
+
422
+
kref_put(&trigger->ref, spi_offload_trigger_free);
423
+
}
424
+
425
+
/**
426
+
* devm_spi_offload_trigger_register() - Allocate and register an offload trigger
427
+
* @dev: Device for devm purposes.
428
+
* @info: Provider-specific trigger info.
429
+
*
430
+
* Return: 0 on success, else a negative error code.
431
+
*/
432
+
int devm_spi_offload_trigger_register(struct device *dev,
433
+
struct spi_offload_trigger_info *info)
434
+
{
435
+
struct spi_offload_trigger *trigger;
436
+
437
+
if (!info->fwnode || !info->ops)
438
+
return -EINVAL;
439
+
440
+
trigger = kzalloc(sizeof(*trigger), GFP_KERNEL);
441
+
if (!trigger)
442
+
return -ENOMEM;
443
+
444
+
kref_init(&trigger->ref);
445
+
mutex_init(&trigger->lock);
446
+
trigger->fwnode = fwnode_handle_get(info->fwnode);
447
+
trigger->ops = info->ops;
448
+
trigger->priv = info->priv;
449
+
450
+
scoped_guard(mutex, &spi_offload_triggers_lock)
451
+
list_add_tail(&trigger->list, &spi_offload_triggers);
452
+
453
+
return devm_add_action_or_reset(dev, spi_offload_trigger_unregister, trigger);
454
+
}
455
+
EXPORT_SYMBOL_GPL(devm_spi_offload_trigger_register);
456
+
457
+
/**
458
+
* spi_offload_trigger_get_priv() - Get the private data for the trigger
459
+
*
460
+
* @trigger: Offload trigger instance.
461
+
*
462
+
* Return: Private data for the trigger.
463
+
*/
464
+
void *spi_offload_trigger_get_priv(struct spi_offload_trigger *trigger)
465
+
{
466
+
return trigger->priv;
467
+
}
468
+
EXPORT_SYMBOL_GPL(spi_offload_trigger_get_priv);
+1633
drivers/spi/spi-qpic-snand.c
+1633
drivers/spi/spi-qpic-snand.c
···
1
+
/*
2
+
* SPDX-License-Identifier: GPL-2.0
3
+
*
4
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
5
+
*
6
+
* Authors:
7
+
* Md Sadre Alam <quic_mdalam@quicinc.com>
8
+
* Sricharan R <quic_srichara@quicinc.com>
9
+
* Varadarajan Narayanan <quic_varada@quicinc.com>
10
+
*/
11
+
#include <linux/bitops.h>
12
+
#include <linux/clk.h>
13
+
#include <linux/delay.h>
14
+
#include <linux/dmaengine.h>
15
+
#include <linux/dma-mapping.h>
16
+
#include <linux/dma/qcom_adm.h>
17
+
#include <linux/dma/qcom_bam_dma.h>
18
+
#include <linux/module.h>
19
+
#include <linux/of.h>
20
+
#include <linux/platform_device.h>
21
+
#include <linux/slab.h>
22
+
#include <linux/mtd/nand-qpic-common.h>
23
+
#include <linux/mtd/spinand.h>
24
+
#include <linux/bitfield.h>
25
+
26
+
#define NAND_FLASH_SPI_CFG 0xc0
27
+
#define NAND_NUM_ADDR_CYCLES 0xc4
28
+
#define NAND_BUSY_CHECK_WAIT_CNT 0xc8
29
+
#define NAND_FLASH_FEATURES 0xf64
30
+
31
+
/* QSPI NAND config reg bits */
32
+
#define LOAD_CLK_CNTR_INIT_EN BIT(28)
33
+
#define CLK_CNTR_INIT_VAL_VEC 0x924
34
+
#define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16)
35
+
#define FEA_STATUS_DEV_ADDR 0xc0
36
+
#define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8)
37
+
#define SPI_CFG BIT(0)
38
+
#define SPI_NUM_ADDR 0xDA4DB
39
+
#define SPI_WAIT_CNT 0x10
40
+
#define QPIC_QSPI_NUM_CS 1
41
+
#define SPI_TRANSFER_MODE_x1 BIT(29)
42
+
#define SPI_TRANSFER_MODE_x4 (3 << 29)
43
+
#define SPI_WP BIT(28)
44
+
#define SPI_HOLD BIT(27)
45
+
#define QPIC_SET_FEATURE BIT(31)
46
+
47
+
#define SPINAND_RESET 0xff
48
+
#define SPINAND_READID 0x9f
49
+
#define SPINAND_GET_FEATURE 0x0f
50
+
#define SPINAND_SET_FEATURE 0x1f
51
+
#define SPINAND_READ 0x13
52
+
#define SPINAND_ERASE 0xd8
53
+
#define SPINAND_WRITE_EN 0x06
54
+
#define SPINAND_PROGRAM_EXECUTE 0x10
55
+
#define SPINAND_PROGRAM_LOAD 0x84
56
+
57
+
#define ACC_FEATURE 0xe
58
+
#define BAD_BLOCK_MARKER_SIZE 0x2
59
+
#define OOB_BUF_SIZE 128
60
+
#define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng)
61
+
62
+
struct qpic_snand_op {
63
+
u32 cmd_reg;
64
+
u32 addr1_reg;
65
+
u32 addr2_reg;
66
+
};
67
+
68
+
struct snandc_read_status {
69
+
__le32 snandc_flash;
70
+
__le32 snandc_buffer;
71
+
__le32 snandc_erased_cw;
72
+
};
73
+
74
+
/*
75
+
* ECC state struct
76
+
* @corrected: ECC corrected
77
+
* @bitflips: Max bit flip
78
+
* @failed: ECC failed
79
+
*/
80
+
struct qcom_ecc_stats {
81
+
u32 corrected;
82
+
u32 bitflips;
83
+
u32 failed;
84
+
};
85
+
86
+
struct qpic_ecc {
87
+
struct device *dev;
88
+
int ecc_bytes_hw;
89
+
int spare_bytes;
90
+
int bbm_size;
91
+
int ecc_mode;
92
+
int bytes;
93
+
int steps;
94
+
int step_size;
95
+
int strength;
96
+
int cw_size;
97
+
int cw_data;
98
+
u32 cfg0;
99
+
u32 cfg1;
100
+
u32 cfg0_raw;
101
+
u32 cfg1_raw;
102
+
u32 ecc_buf_cfg;
103
+
u32 ecc_bch_cfg;
104
+
u32 clrflashstatus;
105
+
u32 clrreadstatus;
106
+
bool bch_enabled;
107
+
};
108
+
109
+
struct qpic_spi_nand {
110
+
struct qcom_nand_controller *snandc;
111
+
struct spi_controller *ctlr;
112
+
struct mtd_info *mtd;
113
+
struct clk *iomacro_clk;
114
+
struct qpic_ecc *ecc;
115
+
struct qcom_ecc_stats ecc_stats;
116
+
struct nand_ecc_engine ecc_eng;
117
+
u8 *data_buf;
118
+
u8 *oob_buf;
119
+
u32 wlen;
120
+
__le32 addr1;
121
+
__le32 addr2;
122
+
__le32 cmd;
123
+
u32 num_cw;
124
+
bool oob_rw;
125
+
bool page_rw;
126
+
bool raw_rw;
127
+
};
128
+
129
+
static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
130
+
int reg, int cw_offset, int read_size,
131
+
int is_last_read_loc)
132
+
{
133
+
__le32 locreg_val;
134
+
u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
135
+
((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)
136
+
<< READ_LOCATION_LAST));
137
+
138
+
locreg_val = cpu_to_le32(val);
139
+
140
+
if (reg == NAND_READ_LOCATION_0)
141
+
snandc->regs->read_location0 = locreg_val;
142
+
else if (reg == NAND_READ_LOCATION_1)
143
+
snandc->regs->read_location1 = locreg_val;
144
+
else if (reg == NAND_READ_LOCATION_2)
145
+
snandc->regs->read_location1 = locreg_val;
146
+
else if (reg == NAND_READ_LOCATION_3)
147
+
snandc->regs->read_location3 = locreg_val;
148
+
}
149
+
150
+
static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc,
151
+
int reg, int cw_offset, int read_size,
152
+
int is_last_read_loc)
153
+
{
154
+
__le32 locreg_val;
155
+
u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
156
+
((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)
157
+
<< READ_LOCATION_LAST));
158
+
159
+
locreg_val = cpu_to_le32(val);
160
+
161
+
if (reg == NAND_READ_LOCATION_LAST_CW_0)
162
+
snandc->regs->read_location_last0 = locreg_val;
163
+
else if (reg == NAND_READ_LOCATION_LAST_CW_1)
164
+
snandc->regs->read_location_last1 = locreg_val;
165
+
else if (reg == NAND_READ_LOCATION_LAST_CW_2)
166
+
snandc->regs->read_location_last2 = locreg_val;
167
+
else if (reg == NAND_READ_LOCATION_LAST_CW_3)
168
+
snandc->regs->read_location_last3 = locreg_val;
169
+
}
170
+
171
+
static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand)
172
+
{
173
+
struct nand_ecc_engine *eng = nand->ecc.engine;
174
+
struct qpic_spi_nand *qspi = ecceng_to_qspi(eng);
175
+
176
+
return qspi->snandc;
177
+
}
178
+
179
+
static int qcom_spi_init(struct qcom_nand_controller *snandc)
180
+
{
181
+
u32 snand_cfg_val = 0x0;
182
+
int ret;
183
+
184
+
snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) |
185
+
FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) |
186
+
FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) |
187
+
FIELD_PREP(SPI_CFG, 0);
188
+
189
+
snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
190
+
snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR);
191
+
snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT);
192
+
193
+
qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
194
+
195
+
snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
196
+
snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
197
+
198
+
qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
199
+
200
+
qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0);
201
+
qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1,
202
+
NAND_BAM_NEXT_SGL);
203
+
204
+
ret = qcom_submit_descs(snandc);
205
+
if (ret) {
206
+
dev_err(snandc->dev, "failure in submitting spi init descriptor\n");
207
+
return ret;
208
+
}
209
+
210
+
return ret;
211
+
}
212
+
213
+
static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section,
214
+
struct mtd_oob_region *oobregion)
215
+
{
216
+
struct nand_device *nand = mtd_to_nanddev(mtd);
217
+
struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
218
+
struct qpic_ecc *qecc = snandc->qspi->ecc;
219
+
220
+
if (section > 1)
221
+
return -ERANGE;
222
+
223
+
oobregion->length = qecc->ecc_bytes_hw + qecc->spare_bytes;
224
+
oobregion->offset = mtd->oobsize - oobregion->length;
225
+
226
+
return 0;
227
+
}
228
+
229
+
static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section,
230
+
struct mtd_oob_region *oobregion)
231
+
{
232
+
struct nand_device *nand = mtd_to_nanddev(mtd);
233
+
struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
234
+
struct qpic_ecc *qecc = snandc->qspi->ecc;
235
+
236
+
if (section)
237
+
return -ERANGE;
238
+
239
+
oobregion->length = qecc->steps * 4;
240
+
oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size;
241
+
242
+
return 0;
243
+
}
244
+
245
+
static const struct mtd_ooblayout_ops qcom_spi_ooblayout = {
246
+
.ecc = qcom_spi_ooblayout_ecc,
247
+
.free = qcom_spi_ooblayout_free,
248
+
};
249
+
250
+
static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
251
+
{
252
+
struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
253
+
struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
254
+
struct mtd_info *mtd = nanddev_to_mtd(nand);
255
+
int cwperpage, bad_block_byte;
256
+
struct qpic_ecc *ecc_cfg;
257
+
258
+
cwperpage = mtd->writesize / NANDC_STEP_SIZE;
259
+
snandc->qspi->num_cw = cwperpage;
260
+
261
+
ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
262
+
if (!ecc_cfg)
263
+
return -ENOMEM;
264
+
snandc->qspi->oob_buf = kzalloc(mtd->writesize + mtd->oobsize,
265
+
GFP_KERNEL);
266
+
if (!snandc->qspi->oob_buf) {
267
+
kfree(ecc_cfg);
268
+
return -ENOMEM;
269
+
}
270
+
271
+
memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize);
272
+
273
+
nand->ecc.ctx.priv = ecc_cfg;
274
+
snandc->qspi->mtd = mtd;
275
+
276
+
ecc_cfg->ecc_bytes_hw = 7;
277
+
ecc_cfg->spare_bytes = 4;
278
+
ecc_cfg->bbm_size = 1;
279
+
ecc_cfg->bch_enabled = true;
280
+
ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
281
+
282
+
ecc_cfg->steps = 4;
283
+
ecc_cfg->strength = 4;
284
+
ecc_cfg->step_size = 512;
285
+
ecc_cfg->cw_data = 516;
286
+
ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
287
+
bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
288
+
289
+
mtd_set_ooblayout(mtd, &qcom_spi_ooblayout);
290
+
291
+
ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
292
+
FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) |
293
+
FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) |
294
+
FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
295
+
FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) |
296
+
FIELD_PREP(STATUS_BFR_READ, 0) |
297
+
FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
298
+
FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes);
299
+
300
+
ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
301
+
FIELD_PREP(CS_ACTIVE_BSY, 0) |
302
+
FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
303
+
FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
304
+
FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
305
+
FIELD_PREP(WIDE_FLASH, 0) |
306
+
FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled);
307
+
308
+
ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
309
+
FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
310
+
FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) |
311
+
FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
312
+
313
+
ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
314
+
FIELD_PREP(CS_ACTIVE_BSY, 0) |
315
+
FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
316
+
FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
317
+
FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
318
+
FIELD_PREP(WIDE_FLASH, 0) |
319
+
FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
320
+
321
+
ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) |
322
+
FIELD_PREP(ECC_SW_RESET, 0) |
323
+
FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
324
+
FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
325
+
FIELD_PREP(ECC_MODE_MASK, 0) |
326
+
FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
327
+
328
+
ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS;
329
+
ecc_cfg->clrflashstatus = FS_READY_BSY_N;
330
+
ecc_cfg->clrreadstatus = 0xc0;
331
+
332
+
conf->step_size = ecc_cfg->step_size;
333
+
conf->strength = ecc_cfg->strength;
334
+
335
+
snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET);
336
+
snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET);
337
+
338
+
dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n",
339
+
ecc_cfg->strength, ecc_cfg->step_size);
340
+
341
+
return 0;
342
+
}
343
+
344
+
static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand)
345
+
{
346
+
struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
347
+
348
+
kfree(ecc_cfg);
349
+
}
350
+
351
+
static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand,
352
+
struct nand_page_io_req *req)
353
+
{
354
+
struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
355
+
struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
356
+
357
+
snandc->qspi->ecc = ecc_cfg;
358
+
snandc->qspi->raw_rw = false;
359
+
snandc->qspi->oob_rw = false;
360
+
snandc->qspi->page_rw = false;
361
+
362
+
if (req->datalen)
363
+
snandc->qspi->page_rw = true;
364
+
365
+
if (req->ooblen)
366
+
snandc->qspi->oob_rw = true;
367
+
368
+
if (req->mode == MTD_OPS_RAW)
369
+
snandc->qspi->raw_rw = true;
370
+
371
+
return 0;
372
+
}
373
+
374
+
static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand,
375
+
struct nand_page_io_req *req)
376
+
{
377
+
struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
378
+
struct mtd_info *mtd = nanddev_to_mtd(nand);
379
+
380
+
if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ)
381
+
return 0;
382
+
383
+
if (snandc->qspi->ecc_stats.failed)
384
+
mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed;
385
+
else
386
+
mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected;
387
+
388
+
if (snandc->qspi->ecc_stats.failed)
389
+
return -EBADMSG;
390
+
else
391
+
return snandc->qspi->ecc_stats.bitflips;
392
+
}
393
+
394
+
static struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = {
395
+
.init_ctx = qcom_spi_ecc_init_ctx_pipelined,
396
+
.cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined,
397
+
.prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined,
398
+
.finish_io_req = qcom_spi_ecc_finish_io_req_pipelined,
399
+
};
400
+
401
+
/* helper to configure location register values */
402
+
static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg,
403
+
int cw_offset, int read_size, int is_last_read_loc)
404
+
{
405
+
int reg_base = NAND_READ_LOCATION_0;
406
+
int num_cw = snandc->qspi->num_cw;
407
+
408
+
if (cw == (num_cw - 1))
409
+
reg_base = NAND_READ_LOCATION_LAST_CW_0;
410
+
411
+
reg_base += reg * 4;
412
+
413
+
if (cw == (num_cw - 1))
414
+
return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset,
415
+
read_size, is_last_read_loc);
416
+
else
417
+
return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset,
418
+
read_size, is_last_read_loc);
419
+
}
420
+
421
+
static void
422
+
qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw)
423
+
{
424
+
__le32 *reg = &snandc->regs->read_location0;
425
+
int num_cw = snandc->qspi->num_cw;
426
+
427
+
qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
428
+
if (cw == (num_cw - 1)) {
429
+
reg = &snandc->regs->read_location_last0;
430
+
qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4,
431
+
NAND_BAM_NEXT_SGL);
432
+
}
433
+
434
+
qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
435
+
qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
436
+
437
+
qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
438
+
qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
439
+
NAND_BAM_NEXT_SGL);
440
+
}
441
+
442
+
static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)
443
+
{
444
+
struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
445
+
int ret;
446
+
447
+
snandc->buf_count = 0;
448
+
snandc->buf_start = 0;
449
+
qcom_clear_read_regs(snandc);
450
+
qcom_clear_bam_transaction(snandc);
451
+
452
+
snandc->regs->cmd = snandc->qspi->cmd;
453
+
snandc->regs->addr0 = snandc->qspi->addr1;
454
+
snandc->regs->addr1 = snandc->qspi->addr2;
455
+
snandc->regs->cfg0 = cpu_to_le32(ecc_cfg->cfg0_raw & ~(7 << CW_PER_PAGE));
456
+
snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw);
457
+
snandc->regs->exec = cpu_to_le32(1);
458
+
459
+
qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
460
+
qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
461
+
qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
462
+
463
+
ret = qcom_submit_descs(snandc);
464
+
if (ret) {
465
+
dev_err(snandc->dev, "failure to erase block\n");
466
+
return ret;
467
+
}
468
+
469
+
return 0;
470
+
}
471
+
472
+
static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc,
473
+
bool use_ecc, int cw)
474
+
{
475
+
__le32 *reg = &snandc->regs->read_location0;
476
+
int num_cw = snandc->qspi->num_cw;
477
+
478
+
qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
479
+
qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
480
+
qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
481
+
NAND_ERASED_CW_DETECT_CFG, 1, 0);
482
+
qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
483
+
NAND_ERASED_CW_DETECT_CFG, 1,
484
+
NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
485
+
486
+
if (cw == (num_cw - 1)) {
487
+
reg = &snandc->regs->read_location_last0;
488
+
qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL);
489
+
}
490
+
qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
491
+
qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
492
+
493
+
qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0);
494
+
}
495
+
496
+
static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc,
497
+
const struct spi_mem_op *op)
498
+
{
499
+
struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
500
+
struct mtd_info *mtd = snandc->qspi->mtd;
501
+
int size, ret = 0;
502
+
int col, bbpos;
503
+
u32 cfg0, cfg1, ecc_bch_cfg;
504
+
u32 num_cw = snandc->qspi->num_cw;
505
+
506
+
qcom_clear_bam_transaction(snandc);
507
+
qcom_clear_read_regs(snandc);
508
+
509
+
size = ecc_cfg->cw_size;
510
+
col = ecc_cfg->cw_size * (num_cw - 1);
511
+
512
+
memset(snandc->data_buffer, 0xff, size);
513
+
snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
514
+
snandc->regs->addr1 = snandc->qspi->addr2;
515
+
516
+
cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
517
+
0 << CW_PER_PAGE;
518
+
cfg1 = ecc_cfg->cfg1_raw;
519
+
ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
520
+
521
+
snandc->regs->cmd = snandc->qspi->cmd;
522
+
snandc->regs->cfg0 = cpu_to_le32(cfg0);
523
+
snandc->regs->cfg1 = cpu_to_le32(cfg1);
524
+
snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
525
+
snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
526
+
snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
527
+
snandc->regs->exec = cpu_to_le32(1);
528
+
529
+
qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1);
530
+
531
+
qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1);
532
+
533
+
qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0);
534
+
535
+
ret = qcom_submit_descs(snandc);
536
+
if (ret) {
537
+
dev_err(snandc->dev, "failed to read last cw\n");
538
+
return ret;
539
+
}
540
+
541
+
qcom_nandc_dev_to_mem(snandc, true);
542
+
u32 flash = le32_to_cpu(snandc->reg_read_buf[0]);
543
+
544
+
if (flash & (FS_OP_ERR | FS_MPU_ERR))
545
+
return -EIO;
546
+
547
+
bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
548
+
549
+
if (snandc->data_buffer[bbpos] == 0xff)
550
+
snandc->data_buffer[bbpos + 1] = 0xff;
551
+
if (snandc->data_buffer[bbpos] != 0xff)
552
+
snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos];
553
+
554
+
memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes);
555
+
556
+
return ret;
557
+
}
558
+
559
+
static int qcom_spi_check_error(struct qcom_nand_controller *snandc, u8 *data_buf, u8 *oob_buf)
560
+
{
561
+
struct snandc_read_status *buf;
562
+
struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
563
+
int i, num_cw = snandc->qspi->num_cw;
564
+
bool flash_op_err = false, erased;
565
+
unsigned int max_bitflips = 0;
566
+
unsigned int uncorrectable_cws = 0;
567
+
568
+
snandc->qspi->ecc_stats.failed = 0;
569
+
snandc->qspi->ecc_stats.corrected = 0;
570
+
571
+
qcom_nandc_dev_to_mem(snandc, true);
572
+
buf = (struct snandc_read_status *)snandc->reg_read_buf;
573
+
574
+
for (i = 0; i < num_cw; i++, buf++) {
575
+
u32 flash, buffer, erased_cw;
576
+
int data_len, oob_len;
577
+
578
+
if (i == (num_cw - 1)) {
579
+
data_len = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
580
+
oob_len = num_cw << 2;
581
+
} else {
582
+
data_len = ecc_cfg->cw_data;
583
+
oob_len = 0;
584
+
}
585
+
586
+
flash = le32_to_cpu(buf->snandc_flash);
587
+
buffer = le32_to_cpu(buf->snandc_buffer);
588
+
erased_cw = le32_to_cpu(buf->snandc_erased_cw);
589
+
590
+
if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) {
591
+
if (ecc_cfg->bch_enabled)
592
+
erased = (erased_cw & ERASED_CW) == ERASED_CW;
593
+
else
594
+
erased = false;
595
+
596
+
if (!erased)
597
+
uncorrectable_cws |= BIT(i);
598
+
599
+
} else if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
600
+
flash_op_err = true;
601
+
} else {
602
+
unsigned int stat;
603
+
604
+
stat = buffer & BS_CORRECTABLE_ERR_MSK;
605
+
snandc->qspi->ecc_stats.corrected += stat;
606
+
max_bitflips = max(max_bitflips, stat);
607
+
}
608
+
609
+
if (data_buf)
610
+
data_buf += data_len;
611
+
if (oob_buf)
612
+
oob_buf += oob_len + ecc_cfg->bytes;
613
+
}
614
+
615
+
if (flash_op_err)
616
+
return -EIO;
617
+
618
+
if (!uncorrectable_cws)
619
+
snandc->qspi->ecc_stats.bitflips = max_bitflips;
620
+
else
621
+
snandc->qspi->ecc_stats.failed++;
622
+
623
+
return 0;
624
+
}
625
+
626
+
static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt)
627
+
{
628
+
int i;
629
+
630
+
qcom_nandc_dev_to_mem(snandc, true);
631
+
632
+
for (i = 0; i < cw_cnt; i++) {
633
+
u32 flash = le32_to_cpu(snandc->reg_read_buf[i]);
634
+
635
+
if (flash & (FS_OP_ERR | FS_MPU_ERR))
636
+
return -EIO;
637
+
}
638
+
639
+
return 0;
640
+
}
641
+
642
+
static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf,
643
+
u8 *oob_buf, int cw)
644
+
{
645
+
struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
646
+
struct mtd_info *mtd = snandc->qspi->mtd;
647
+
int data_size1, data_size2, oob_size1, oob_size2;
648
+
int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
649
+
int raw_cw = cw;
650
+
u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
651
+
int col;
652
+
653
+
snandc->buf_count = 0;
654
+
snandc->buf_start = 0;
655
+
qcom_clear_read_regs(snandc);
656
+
qcom_clear_bam_transaction(snandc);
657
+
raw_cw = num_cw - 1;
658
+
659
+
cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
660
+
0 << CW_PER_PAGE;
661
+
cfg1 = ecc_cfg->cfg1_raw;
662
+
ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
663
+
664
+
col = ecc_cfg->cw_size * cw;
665
+
666
+
snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
667
+
snandc->regs->addr1 = snandc->qspi->addr2;
668
+
snandc->regs->cmd = snandc->qspi->cmd;
669
+
snandc->regs->cfg0 = cpu_to_le32(cfg0);
670
+
snandc->regs->cfg1 = cpu_to_le32(cfg1);
671
+
snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
672
+
snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
673
+
snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
674
+
snandc->regs->exec = cpu_to_le32(1);
675
+
676
+
qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1);
677
+
678
+
qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
679
+
qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
680
+
qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
681
+
682
+
qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
683
+
NAND_ERASED_CW_DETECT_CFG, 1, 0);
684
+
qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
685
+
NAND_ERASED_CW_DETECT_CFG, 1,
686
+
NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
687
+
688
+
data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
689
+
oob_size1 = ecc_cfg->bbm_size;
690
+
691
+
if (cw == (num_cw - 1)) {
692
+
data_size2 = NANDC_STEP_SIZE - data_size1 -
693
+
((num_cw - 1) * 4);
694
+
oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw +
695
+
ecc_cfg->spare_bytes;
696
+
} else {
697
+
data_size2 = ecc_cfg->cw_data - data_size1;
698
+
oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
699
+
}
700
+
701
+
qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0);
702
+
read_loc += data_size1;
703
+
704
+
qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0);
705
+
read_loc += oob_size1;
706
+
707
+
qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0);
708
+
read_loc += data_size2;
709
+
710
+
qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1);
711
+
712
+
qcom_spi_config_cw_read(snandc, false, raw_cw);
713
+
714
+
qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0);
715
+
reg_off += data_size1;
716
+
717
+
qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0);
718
+
reg_off += oob_size1;
719
+
720
+
qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0);
721
+
reg_off += data_size2;
722
+
723
+
qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
724
+
725
+
ret = qcom_submit_descs(snandc);
726
+
if (ret) {
727
+
dev_err(snandc->dev, "failure to read raw cw %d\n", cw);
728
+
return ret;
729
+
}
730
+
731
+
return qcom_spi_check_raw_flash_errors(snandc, 1);
732
+
}
733
+
734
+
static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc,
735
+
const struct spi_mem_op *op)
736
+
{
737
+
struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
738
+
u8 *data_buf = NULL, *oob_buf = NULL;
739
+
int ret, cw;
740
+
u32 num_cw = snandc->qspi->num_cw;
741
+
742
+
if (snandc->qspi->page_rw)
743
+
data_buf = op->data.buf.in;
744
+
745
+
oob_buf = snandc->qspi->oob_buf;
746
+
memset(oob_buf, 0xff, OOB_BUF_SIZE);
747
+
748
+
for (cw = 0; cw < num_cw; cw++) {
749
+
ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw);
750
+
if (ret)
751
+
return ret;
752
+
753
+
if (data_buf)
754
+
data_buf += ecc_cfg->cw_data;
755
+
if (oob_buf)
756
+
oob_buf += ecc_cfg->bytes;
757
+
}
758
+
759
+
return 0;
760
+
}
761
+
762
+
static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc,
763
+
const struct spi_mem_op *op)
764
+
{
765
+
struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
766
+
u8 *data_buf = NULL, *data_buf_start, *oob_buf = NULL, *oob_buf_start;
767
+
int ret, i;
768
+
u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
769
+
770
+
data_buf = op->data.buf.in;
771
+
data_buf_start = data_buf;
772
+
773
+
oob_buf = snandc->qspi->oob_buf;
774
+
oob_buf_start = oob_buf;
775
+
776
+
snandc->buf_count = 0;
777
+
snandc->buf_start = 0;
778
+
qcom_clear_read_regs(snandc);
779
+
780
+
cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
781
+
(num_cw - 1) << CW_PER_PAGE;
782
+
cfg1 = ecc_cfg->cfg1;
783
+
ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
784
+
785
+
snandc->regs->addr0 = snandc->qspi->addr1;
786
+
snandc->regs->addr1 = snandc->qspi->addr2;
787
+
snandc->regs->cmd = snandc->qspi->cmd;
788
+
snandc->regs->cfg0 = cpu_to_le32(cfg0);
789
+
snandc->regs->cfg1 = cpu_to_le32(cfg1);
790
+
snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
791
+
snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
792
+
snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
793
+
snandc->regs->exec = cpu_to_le32(1);
794
+
795
+
qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
796
+
797
+
qcom_clear_bam_transaction(snandc);
798
+
799
+
qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
800
+
qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
801
+
qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
802
+
NAND_ERASED_CW_DETECT_CFG, 1, 0);
803
+
qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
804
+
NAND_ERASED_CW_DETECT_CFG, 1,
805
+
NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
806
+
807
+
for (i = 0; i < num_cw; i++) {
808
+
int data_size, oob_size;
809
+
810
+
if (i == (num_cw - 1)) {
811
+
data_size = 512 - ((num_cw - 1) << 2);
812
+
oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
813
+
ecc_cfg->spare_bytes;
814
+
} else {
815
+
data_size = ecc_cfg->cw_data;
816
+
oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
817
+
}
818
+
819
+
if (data_buf && oob_buf) {
820
+
qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0);
821
+
qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1);
822
+
} else if (data_buf) {
823
+
qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1);
824
+
} else {
825
+
qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
826
+
}
827
+
828
+
qcom_spi_config_cw_read(snandc, true, i);
829
+
830
+
if (data_buf)
831
+
qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf,
832
+
data_size, 0);
833
+
if (oob_buf) {
834
+
int j;
835
+
836
+
for (j = 0; j < ecc_cfg->bbm_size; j++)
837
+
*oob_buf++ = 0xff;
838
+
839
+
qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
840
+
oob_buf, oob_size, 0);
841
+
}
842
+
843
+
if (data_buf)
844
+
data_buf += data_size;
845
+
if (oob_buf)
846
+
oob_buf += oob_size;
847
+
}
848
+
849
+
ret = qcom_submit_descs(snandc);
850
+
if (ret) {
851
+
dev_err(snandc->dev, "failure to read page\n");
852
+
return ret;
853
+
}
854
+
855
+
return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start);
856
+
}
857
+
858
+
static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
859
+
const struct spi_mem_op *op)
860
+
{
861
+
struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
862
+
u8 *data_buf = NULL, *data_buf_start, *oob_buf = NULL, *oob_buf_start;
863
+
int ret, i;
864
+
u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
865
+
866
+
oob_buf = op->data.buf.in;
867
+
oob_buf_start = oob_buf;
868
+
869
+
data_buf_start = data_buf;
870
+
871
+
snandc->buf_count = 0;
872
+
snandc->buf_start = 0;
873
+
qcom_clear_read_regs(snandc);
874
+
qcom_clear_bam_transaction(snandc);
875
+
876
+
cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
877
+
(num_cw - 1) << CW_PER_PAGE;
878
+
cfg1 = ecc_cfg->cfg1;
879
+
ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
880
+
881
+
snandc->regs->addr0 = snandc->qspi->addr1;
882
+
snandc->regs->addr1 = snandc->qspi->addr2;
883
+
snandc->regs->cmd = snandc->qspi->cmd;
884
+
snandc->regs->cfg0 = cpu_to_le32(cfg0);
885
+
snandc->regs->cfg1 = cpu_to_le32(cfg1);
886
+
snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
887
+
snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
888
+
snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
889
+
snandc->regs->exec = cpu_to_le32(1);
890
+
891
+
qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
892
+
893
+
qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
894
+
qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
895
+
qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
896
+
NAND_ERASED_CW_DETECT_CFG, 1, 0);
897
+
qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
898
+
NAND_ERASED_CW_DETECT_CFG, 1,
899
+
NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
900
+
901
+
for (i = 0; i < num_cw; i++) {
902
+
int data_size, oob_size;
903
+
904
+
if (i == (num_cw - 1)) {
905
+
data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
906
+
oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
907
+
ecc_cfg->spare_bytes;
908
+
} else {
909
+
data_size = ecc_cfg->cw_data;
910
+
oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
911
+
}
912
+
913
+
qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
914
+
915
+
qcom_spi_config_cw_read(snandc, true, i);
916
+
917
+
if (oob_buf) {
918
+
int j;
919
+
920
+
for (j = 0; j < ecc_cfg->bbm_size; j++)
921
+
*oob_buf++ = 0xff;
922
+
923
+
qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
924
+
oob_buf, oob_size, 0);
925
+
}
926
+
927
+
if (oob_buf)
928
+
oob_buf += oob_size;
929
+
}
930
+
931
+
ret = qcom_submit_descs(snandc);
932
+
if (ret) {
933
+
dev_err(snandc->dev, "failure to read oob\n");
934
+
return ret;
935
+
}
936
+
937
+
return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start);
938
+
}
939
+
940
+
static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
941
+
const struct spi_mem_op *op)
942
+
{
943
+
if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
944
+
return qcom_spi_read_page_raw(snandc, op);
945
+
946
+
if (snandc->qspi->page_rw)
947
+
return qcom_spi_read_page_ecc(snandc, op);
948
+
949
+
if (snandc->qspi->oob_rw && snandc->qspi->raw_rw)
950
+
return qcom_spi_read_last_cw(snandc, op);
951
+
952
+
if (snandc->qspi->oob_rw)
953
+
return qcom_spi_read_page_oob(snandc, op);
954
+
955
+
return 0;
956
+
}
957
+
958
+
static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc)
959
+
{
960
+
qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
961
+
qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
962
+
qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG,
963
+
1, NAND_BAM_NEXT_SGL);
964
+
}
965
+
966
+
static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc)
967
+
{
968
+
qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
969
+
qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
970
+
qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
971
+
972
+
qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
973
+
qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
974
+
NAND_BAM_NEXT_SGL);
975
+
}
976
+
977
+
static int qcom_spi_program_raw(struct qcom_nand_controller *snandc,
978
+
const struct spi_mem_op *op)
979
+
{
980
+
struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
981
+
struct mtd_info *mtd = snandc->qspi->mtd;
982
+
u8 *data_buf = NULL, *oob_buf = NULL;
983
+
int i, ret;
984
+
int num_cw = snandc->qspi->num_cw;
985
+
u32 cfg0, cfg1, ecc_bch_cfg;
986
+
987
+
cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
988
+
(num_cw - 1) << CW_PER_PAGE;
989
+
cfg1 = ecc_cfg->cfg1_raw;
990
+
ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
991
+
992
+
data_buf = snandc->qspi->data_buf;
993
+
994
+
oob_buf = snandc->qspi->oob_buf;
995
+
memset(oob_buf, 0xff, OOB_BUF_SIZE);
996
+
997
+
snandc->buf_count = 0;
998
+
snandc->buf_start = 0;
999
+
qcom_clear_read_regs(snandc);
1000
+
qcom_clear_bam_transaction(snandc);
1001
+
1002
+
snandc->regs->addr0 = snandc->qspi->addr1;
1003
+
snandc->regs->addr1 = snandc->qspi->addr2;
1004
+
snandc->regs->cmd = snandc->qspi->cmd;
1005
+
snandc->regs->cfg0 = cpu_to_le32(cfg0);
1006
+
snandc->regs->cfg1 = cpu_to_le32(cfg1);
1007
+
snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1008
+
snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
1009
+
snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
1010
+
snandc->regs->exec = cpu_to_le32(1);
1011
+
1012
+
qcom_spi_config_page_write(snandc);
1013
+
1014
+
for (i = 0; i < num_cw; i++) {
1015
+
int data_size1, data_size2, oob_size1, oob_size2;
1016
+
int reg_off = FLASH_BUF_ACC;
1017
+
1018
+
data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
1019
+
oob_size1 = ecc_cfg->bbm_size;
1020
+
1021
+
if (i == (num_cw - 1)) {
1022
+
data_size2 = NANDC_STEP_SIZE - data_size1 -
1023
+
((num_cw - 1) << 2);
1024
+
oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1025
+
ecc_cfg->spare_bytes;
1026
+
} else {
1027
+
data_size2 = ecc_cfg->cw_data - data_size1;
1028
+
oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
1029
+
}
1030
+
1031
+
qcom_write_data_dma(snandc, reg_off, data_buf, data_size1,
1032
+
NAND_BAM_NO_EOT);
1033
+
reg_off += data_size1;
1034
+
data_buf += data_size1;
1035
+
1036
+
qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1,
1037
+
NAND_BAM_NO_EOT);
1038
+
oob_buf += oob_size1;
1039
+
reg_off += oob_size1;
1040
+
1041
+
qcom_write_data_dma(snandc, reg_off, data_buf, data_size2,
1042
+
NAND_BAM_NO_EOT);
1043
+
reg_off += data_size2;
1044
+
data_buf += data_size2;
1045
+
1046
+
qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0);
1047
+
oob_buf += oob_size2;
1048
+
1049
+
qcom_spi_config_cw_write(snandc);
1050
+
}
1051
+
1052
+
ret = qcom_submit_descs(snandc);
1053
+
if (ret) {
1054
+
dev_err(snandc->dev, "failure to write raw page\n");
1055
+
return ret;
1056
+
}
1057
+
1058
+
return 0;
1059
+
}
1060
+
1061
+
static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc,
1062
+
const struct spi_mem_op *op)
1063
+
{
1064
+
struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1065
+
u8 *data_buf = NULL, *oob_buf = NULL;
1066
+
int i, ret;
1067
+
int num_cw = snandc->qspi->num_cw;
1068
+
u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1069
+
1070
+
cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
1071
+
(num_cw - 1) << CW_PER_PAGE;
1072
+
cfg1 = ecc_cfg->cfg1;
1073
+
ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1074
+
ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1075
+
1076
+
if (snandc->qspi->data_buf)
1077
+
data_buf = snandc->qspi->data_buf;
1078
+
1079
+
oob_buf = snandc->qspi->oob_buf;
1080
+
1081
+
snandc->buf_count = 0;
1082
+
snandc->buf_start = 0;
1083
+
qcom_clear_read_regs(snandc);
1084
+
qcom_clear_bam_transaction(snandc);
1085
+
1086
+
snandc->regs->addr0 = snandc->qspi->addr1;
1087
+
snandc->regs->addr1 = snandc->qspi->addr2;
1088
+
snandc->regs->cmd = snandc->qspi->cmd;
1089
+
snandc->regs->cfg0 = cpu_to_le32(cfg0);
1090
+
snandc->regs->cfg1 = cpu_to_le32(cfg1);
1091
+
snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1092
+
snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1093
+
snandc->regs->exec = cpu_to_le32(1);
1094
+
1095
+
qcom_spi_config_page_write(snandc);
1096
+
1097
+
for (i = 0; i < num_cw; i++) {
1098
+
int data_size, oob_size;
1099
+
1100
+
if (i == (num_cw - 1)) {
1101
+
data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1102
+
oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1103
+
ecc_cfg->spare_bytes;
1104
+
} else {
1105
+
data_size = ecc_cfg->cw_data;
1106
+
oob_size = ecc_cfg->bytes;
1107
+
}
1108
+
1109
+
if (data_buf)
1110
+
qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size,
1111
+
i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0);
1112
+
1113
+
if (i == (num_cw - 1)) {
1114
+
if (oob_buf) {
1115
+
oob_buf += ecc_cfg->bbm_size;
1116
+
qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size,
1117
+
oob_buf, oob_size, 0);
1118
+
}
1119
+
}
1120
+
1121
+
qcom_spi_config_cw_write(snandc);
1122
+
1123
+
if (data_buf)
1124
+
data_buf += data_size;
1125
+
if (oob_buf)
1126
+
oob_buf += oob_size;
1127
+
}
1128
+
1129
+
ret = qcom_submit_descs(snandc);
1130
+
if (ret) {
1131
+
dev_err(snandc->dev, "failure to write page\n");
1132
+
return ret;
1133
+
}
1134
+
1135
+
return 0;
1136
+
}
1137
+
1138
+
static int qcom_spi_program_oob(struct qcom_nand_controller *snandc,
1139
+
const struct spi_mem_op *op)
1140
+
{
1141
+
struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1142
+
u8 *oob_buf = NULL;
1143
+
int ret, col, data_size, oob_size;
1144
+
int num_cw = snandc->qspi->num_cw;
1145
+
u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1146
+
1147
+
cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
1148
+
(num_cw - 1) << CW_PER_PAGE;
1149
+
cfg1 = ecc_cfg->cfg1;
1150
+
ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1151
+
ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1152
+
1153
+
col = ecc_cfg->cw_size * (num_cw - 1);
1154
+
1155
+
oob_buf = snandc->qspi->data_buf;
1156
+
1157
+
snandc->buf_count = 0;
1158
+
snandc->buf_start = 0;
1159
+
qcom_clear_read_regs(snandc);
1160
+
qcom_clear_bam_transaction(snandc);
1161
+
snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
1162
+
snandc->regs->addr1 = snandc->qspi->addr2;
1163
+
snandc->regs->cmd = snandc->qspi->cmd;
1164
+
snandc->regs->cfg0 = cpu_to_le32(cfg0);
1165
+
snandc->regs->cfg1 = cpu_to_le32(cfg1);
1166
+
snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1167
+
snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1168
+
snandc->regs->exec = cpu_to_le32(1);
1169
+
1170
+
/* calculate the data and oob size for the last codeword/step */
1171
+
data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1172
+
oob_size = snandc->qspi->mtd->oobavail;
1173
+
1174
+
memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data);
1175
+
/* override new oob content to last codeword */
1176
+
mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size,
1177
+
oob_buf, 0, snandc->qspi->mtd->oobavail);
1178
+
qcom_spi_config_page_write(snandc);
1179
+
qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0);
1180
+
qcom_spi_config_cw_write(snandc);
1181
+
1182
+
ret = qcom_submit_descs(snandc);
1183
+
if (ret) {
1184
+
dev_err(snandc->dev, "failure to write oob\n");
1185
+
return ret;
1186
+
}
1187
+
1188
+
return 0;
1189
+
}
1190
+
1191
+
static int qcom_spi_program_execute(struct qcom_nand_controller *snandc,
1192
+
const struct spi_mem_op *op)
1193
+
{
1194
+
if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1195
+
return qcom_spi_program_raw(snandc, op);
1196
+
1197
+
if (snandc->qspi->page_rw)
1198
+
return qcom_spi_program_ecc(snandc, op);
1199
+
1200
+
if (snandc->qspi->oob_rw)
1201
+
return qcom_spi_program_oob(snandc, op);
1202
+
1203
+
return 0;
1204
+
}
1205
+
1206
+
static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, u32 *cmd)
1207
+
{
1208
+
switch (opcode) {
1209
+
case SPINAND_RESET:
1210
+
*cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
1211
+
break;
1212
+
case SPINAND_READID:
1213
+
*cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
1214
+
break;
1215
+
case SPINAND_GET_FEATURE:
1216
+
*cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
1217
+
break;
1218
+
case SPINAND_SET_FEATURE:
1219
+
*cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
1220
+
QPIC_SET_FEATURE);
1221
+
break;
1222
+
case SPINAND_READ:
1223
+
if (snandc->qspi->raw_rw) {
1224
+
*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1225
+
SPI_WP | SPI_HOLD | OP_PAGE_READ);
1226
+
} else {
1227
+
*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1228
+
SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
1229
+
}
1230
+
1231
+
break;
1232
+
case SPINAND_ERASE:
1233
+
*cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
1234
+
SPI_HOLD | SPI_TRANSFER_MODE_x1;
1235
+
break;
1236
+
case SPINAND_WRITE_EN:
1237
+
*cmd = SPINAND_WRITE_EN;
1238
+
break;
1239
+
case SPINAND_PROGRAM_EXECUTE:
1240
+
*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1241
+
SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
1242
+
break;
1243
+
case SPINAND_PROGRAM_LOAD:
1244
+
*cmd = SPINAND_PROGRAM_LOAD;
1245
+
break;
1246
+
default:
1247
+
dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
1248
+
return -EOPNOTSUPP;
1249
+
}
1250
+
1251
+
return 0;
1252
+
}
1253
+
1254
+
static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
1255
+
const struct spi_mem_op *op)
1256
+
{
1257
+
int ret;
1258
+
u32 cmd;
1259
+
1260
+
ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
1261
+
if (ret < 0)
1262
+
return ret;
1263
+
1264
+
if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
1265
+
snandc->qspi->data_buf = (u8 *)op->data.buf.out;
1266
+
1267
+
return 0;
1268
+
}
1269
+
1270
+
static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
1271
+
const struct spi_mem_op *op)
1272
+
{
1273
+
struct qpic_snand_op s_op = {};
1274
+
u32 cmd;
1275
+
int ret, opcode;
1276
+
1277
+
ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
1278
+
if (ret < 0)
1279
+
return ret;
1280
+
1281
+
s_op.cmd_reg = cmd;
1282
+
s_op.addr1_reg = op->addr.val;
1283
+
s_op.addr2_reg = 0;
1284
+
1285
+
opcode = op->cmd.opcode;
1286
+
1287
+
switch (opcode) {
1288
+
case SPINAND_WRITE_EN:
1289
+
return 0;
1290
+
case SPINAND_PROGRAM_EXECUTE:
1291
+
s_op.addr1_reg = op->addr.val << 16;
1292
+
s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1293
+
snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1294
+
snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1295
+
snandc->qspi->cmd = cpu_to_le32(cmd);
1296
+
return qcom_spi_program_execute(snandc, op);
1297
+
case SPINAND_READ:
1298
+
s_op.addr1_reg = (op->addr.val << 16);
1299
+
s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1300
+
snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1301
+
snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1302
+
snandc->qspi->cmd = cpu_to_le32(cmd);
1303
+
return 0;
1304
+
case SPINAND_ERASE:
1305
+
s_op.addr2_reg = (op->addr.val >> 16) & 0xffff;
1306
+
s_op.addr1_reg = op->addr.val;
1307
+
snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16);
1308
+
snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1309
+
snandc->qspi->cmd = cpu_to_le32(cmd);
1310
+
qcom_spi_block_erase(snandc);
1311
+
return 0;
1312
+
default:
1313
+
break;
1314
+
}
1315
+
1316
+
snandc->buf_count = 0;
1317
+
snandc->buf_start = 0;
1318
+
qcom_clear_read_regs(snandc);
1319
+
qcom_clear_bam_transaction(snandc);
1320
+
1321
+
snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg);
1322
+
snandc->regs->exec = cpu_to_le32(1);
1323
+
snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg);
1324
+
snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg);
1325
+
1326
+
qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1327
+
qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1328
+
1329
+
ret = qcom_submit_descs(snandc);
1330
+
if (ret)
1331
+
dev_err(snandc->dev, "failure in submitting cmd descriptor\n");
1332
+
1333
+
return ret;
1334
+
}
1335
+
1336
+
static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op)
1337
+
{
1338
+
int ret, val, opcode;
1339
+
bool copy = false, copy_ftr = false;
1340
+
1341
+
ret = qcom_spi_send_cmdaddr(snandc, op);
1342
+
if (ret)
1343
+
return ret;
1344
+
1345
+
snandc->buf_count = 0;
1346
+
snandc->buf_start = 0;
1347
+
qcom_clear_read_regs(snandc);
1348
+
qcom_clear_bam_transaction(snandc);
1349
+
opcode = op->cmd.opcode;
1350
+
1351
+
switch (opcode) {
1352
+
case SPINAND_READID:
1353
+
snandc->buf_count = 4;
1354
+
qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1355
+
copy = true;
1356
+
break;
1357
+
case SPINAND_GET_FEATURE:
1358
+
snandc->buf_count = 4;
1359
+
qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1360
+
copy_ftr = true;
1361
+
break;
1362
+
case SPINAND_SET_FEATURE:
1363
+
snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out);
1364
+
qcom_write_reg_dma(snandc, &snandc->regs->flash_feature,
1365
+
NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1366
+
break;
1367
+
case SPINAND_PROGRAM_EXECUTE:
1368
+
case SPINAND_WRITE_EN:
1369
+
case SPINAND_RESET:
1370
+
case SPINAND_ERASE:
1371
+
case SPINAND_READ:
1372
+
return 0;
1373
+
default:
1374
+
return -EOPNOTSUPP;
1375
+
}
1376
+
1377
+
ret = qcom_submit_descs(snandc);
1378
+
if (ret)
1379
+
dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode);
1380
+
1381
+
if (copy) {
1382
+
qcom_nandc_dev_to_mem(snandc, true);
1383
+
memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
1384
+
}
1385
+
1386
+
if (copy_ftr) {
1387
+
qcom_nandc_dev_to_mem(snandc, true);
1388
+
val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf);
1389
+
val >>= 8;
1390
+
memcpy(op->data.buf.in, &val, snandc->buf_count);
1391
+
}
1392
+
1393
+
return ret;
1394
+
}
1395
+
1396
+
static bool qcom_spi_is_page_op(const struct spi_mem_op *op)
1397
+
{
1398
+
if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4)
1399
+
return false;
1400
+
1401
+
if (op->data.dir == SPI_MEM_DATA_IN) {
1402
+
if (op->addr.buswidth == 4 && op->data.buswidth == 4)
1403
+
return true;
1404
+
1405
+
if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1406
+
return true;
1407
+
1408
+
} else if (op->data.dir == SPI_MEM_DATA_OUT) {
1409
+
if (op->data.buswidth == 4)
1410
+
return true;
1411
+
if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1412
+
return true;
1413
+
}
1414
+
1415
+
return false;
1416
+
}
1417
+
1418
+
static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
1419
+
{
1420
+
if (!spi_mem_default_supports_op(mem, op))
1421
+
return false;
1422
+
1423
+
if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
1424
+
return false;
1425
+
1426
+
if (qcom_spi_is_page_op(op))
1427
+
return true;
1428
+
1429
+
return ((!op->addr.nbytes || op->addr.buswidth == 1) &&
1430
+
(!op->dummy.nbytes || op->dummy.buswidth == 1) &&
1431
+
(!op->data.nbytes || op->data.buswidth == 1));
1432
+
}
1433
+
1434
+
static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
1435
+
{
1436
+
struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller);
1437
+
1438
+
dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
1439
+
op->addr.val, op->addr.buswidth, op->addr.nbytes,
1440
+
op->data.buswidth, op->data.nbytes);
1441
+
1442
+
if (qcom_spi_is_page_op(op)) {
1443
+
if (op->data.dir == SPI_MEM_DATA_IN)
1444
+
return qcom_spi_read_page(snandc, op);
1445
+
if (op->data.dir == SPI_MEM_DATA_OUT)
1446
+
return qcom_spi_write_page(snandc, op);
1447
+
} else {
1448
+
return qcom_spi_io_op(snandc, op);
1449
+
}
1450
+
1451
+
return 0;
1452
+
}
1453
+
1454
+
static const struct spi_controller_mem_ops qcom_spi_mem_ops = {
1455
+
.supports_op = qcom_spi_supports_op,
1456
+
.exec_op = qcom_spi_exec_op,
1457
+
};
1458
+
1459
+
static const struct spi_controller_mem_caps qcom_spi_mem_caps = {
1460
+
.ecc = true,
1461
+
};
1462
+
1463
+
static int qcom_spi_probe(struct platform_device *pdev)
1464
+
{
1465
+
struct device *dev = &pdev->dev;
1466
+
struct spi_controller *ctlr;
1467
+
struct qcom_nand_controller *snandc;
1468
+
struct qpic_spi_nand *qspi;
1469
+
struct qpic_ecc *ecc;
1470
+
struct resource *res;
1471
+
const void *dev_data;
1472
+
int ret;
1473
+
1474
+
ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
1475
+
if (!ecc)
1476
+
return -ENOMEM;
1477
+
1478
+
qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
1479
+
if (!qspi)
1480
+
return -ENOMEM;
1481
+
1482
+
ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false);
1483
+
if (!ctlr)
1484
+
return -ENOMEM;
1485
+
1486
+
platform_set_drvdata(pdev, ctlr);
1487
+
1488
+
snandc = spi_controller_get_devdata(ctlr);
1489
+
qspi->snandc = snandc;
1490
+
1491
+
snandc->dev = dev;
1492
+
snandc->qspi = qspi;
1493
+
snandc->qspi->ctlr = ctlr;
1494
+
snandc->qspi->ecc = ecc;
1495
+
1496
+
dev_data = of_device_get_match_data(dev);
1497
+
if (!dev_data) {
1498
+
dev_err(&pdev->dev, "failed to get device data\n");
1499
+
return -ENODEV;
1500
+
}
1501
+
1502
+
snandc->props = dev_data;
1503
+
snandc->dev = &pdev->dev;
1504
+
1505
+
snandc->core_clk = devm_clk_get(dev, "core");
1506
+
if (IS_ERR(snandc->core_clk))
1507
+
return PTR_ERR(snandc->core_clk);
1508
+
1509
+
snandc->aon_clk = devm_clk_get(dev, "aon");
1510
+
if (IS_ERR(snandc->aon_clk))
1511
+
return PTR_ERR(snandc->aon_clk);
1512
+
1513
+
snandc->qspi->iomacro_clk = devm_clk_get(dev, "iom");
1514
+
if (IS_ERR(snandc->qspi->iomacro_clk))
1515
+
return PTR_ERR(snandc->qspi->iomacro_clk);
1516
+
1517
+
snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1518
+
if (IS_ERR(snandc->base))
1519
+
return PTR_ERR(snandc->base);
1520
+
1521
+
snandc->base_phys = res->start;
1522
+
snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res),
1523
+
DMA_BIDIRECTIONAL, 0);
1524
+
if (dma_mapping_error(dev, snandc->base_dma))
1525
+
return -ENXIO;
1526
+
1527
+
ret = clk_prepare_enable(snandc->core_clk);
1528
+
if (ret)
1529
+
goto err_dis_core_clk;
1530
+
1531
+
ret = clk_prepare_enable(snandc->aon_clk);
1532
+
if (ret)
1533
+
goto err_dis_aon_clk;
1534
+
1535
+
ret = clk_prepare_enable(snandc->qspi->iomacro_clk);
1536
+
if (ret)
1537
+
goto err_dis_iom_clk;
1538
+
1539
+
ret = qcom_nandc_alloc(snandc);
1540
+
if (ret)
1541
+
goto err_snand_alloc;
1542
+
1543
+
ret = qcom_spi_init(snandc);
1544
+
if (ret)
1545
+
goto err_spi_init;
1546
+
1547
+
/* setup ECC engine */
1548
+
snandc->qspi->ecc_eng.dev = &pdev->dev;
1549
+
snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
1550
+
snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined;
1551
+
snandc->qspi->ecc_eng.priv = snandc;
1552
+
1553
+
ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng);
1554
+
if (ret) {
1555
+
dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret);
1556
+
goto err_spi_init;
1557
+
}
1558
+
1559
+
ctlr->num_chipselect = QPIC_QSPI_NUM_CS;
1560
+
ctlr->mem_ops = &qcom_spi_mem_ops;
1561
+
ctlr->mem_caps = &qcom_spi_mem_caps;
1562
+
ctlr->dev.of_node = pdev->dev.of_node;
1563
+
ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL |
1564
+
SPI_TX_QUAD | SPI_RX_QUAD;
1565
+
1566
+
ret = spi_register_controller(ctlr);
1567
+
if (ret) {
1568
+
dev_err(&pdev->dev, "spi_register_controller failed.\n");
1569
+
goto err_spi_init;
1570
+
}
1571
+
1572
+
return 0;
1573
+
1574
+
err_spi_init:
1575
+
qcom_nandc_unalloc(snandc);
1576
+
err_snand_alloc:
1577
+
clk_disable_unprepare(snandc->qspi->iomacro_clk);
1578
+
err_dis_iom_clk:
1579
+
clk_disable_unprepare(snandc->aon_clk);
1580
+
err_dis_aon_clk:
1581
+
clk_disable_unprepare(snandc->core_clk);
1582
+
err_dis_core_clk:
1583
+
dma_unmap_resource(dev, res->start, resource_size(res),
1584
+
DMA_BIDIRECTIONAL, 0);
1585
+
return ret;
1586
+
}
1587
+
1588
+
static void qcom_spi_remove(struct platform_device *pdev)
1589
+
{
1590
+
struct spi_controller *ctlr = platform_get_drvdata(pdev);
1591
+
struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr);
1592
+
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1593
+
1594
+
spi_unregister_controller(ctlr);
1595
+
1596
+
qcom_nandc_unalloc(snandc);
1597
+
1598
+
clk_disable_unprepare(snandc->aon_clk);
1599
+
clk_disable_unprepare(snandc->core_clk);
1600
+
clk_disable_unprepare(snandc->qspi->iomacro_clk);
1601
+
1602
+
dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res),
1603
+
DMA_BIDIRECTIONAL, 0);
1604
+
}
1605
+
1606
+
static const struct qcom_nandc_props ipq9574_snandc_props = {
1607
+
.dev_cmd_reg_start = 0x7000,
1608
+
.supports_bam = true,
1609
+
};
1610
+
1611
+
static const struct of_device_id qcom_snandc_of_match[] = {
1612
+
{
1613
+
.compatible = "qcom,ipq9574-snand",
1614
+
.data = &ipq9574_snandc_props,
1615
+
},
1616
+
{}
1617
+
}
1618
+
MODULE_DEVICE_TABLE(of, qcom_snandc_of_match);
1619
+
1620
+
static struct platform_driver qcom_spi_driver = {
1621
+
.driver = {
1622
+
.name = "qcom_snand",
1623
+
.of_match_table = qcom_snandc_of_match,
1624
+
},
1625
+
.probe = qcom_spi_probe,
1626
+
.remove = qcom_spi_remove,
1627
+
};
1628
+
module_platform_driver(qcom_spi_driver);
1629
+
1630
+
MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores");
1631
+
MODULE_AUTHOR("Md Sadre Alam <quic_mdalam@quicinc.com>");
1632
+
MODULE_LICENSE("GPL");
1633
+
-1
drivers/spi/spi-realtek-rtl-snand.c
-1
drivers/spi/spi-realtek-rtl-snand.c
+3
-1
drivers/spi/spi-s3c64xx.c
+3
-1
drivers/spi/spi-s3c64xx.c
···
139
139
* struct s3c64xx_spi_port_config - SPI Controller hardware info
140
140
* @fifo_lvl_mask: [DEPRECATED] use @{rx, tx}_fifomask instead.
141
141
* @rx_lvl_offset: [DEPRECATED] use @{rx,tx}_fifomask instead.
142
-
* @fifo_depth: depth of the FIFO.
142
+
* @fifo_depth: depth of the FIFOs. Used by compatibles where all the instances
143
+
* of the IP define the same FIFO depth. It has higher precedence
144
+
* than the FIFO depth specified via DT.
143
145
* @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's
144
146
* length and position.
145
147
* @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's
+488
drivers/spi/spi-sg2044-nor.c
+488
drivers/spi/spi-sg2044-nor.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* SG2044 SPI NOR controller driver
4
+
*
5
+
* Copyright (c) 2025 Longbin Li <looong.bin@gmail.com>
6
+
*/
7
+
8
+
#include <linux/bitfield.h>
9
+
#include <linux/clk.h>
10
+
#include <linux/iopoll.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of.h>
13
+
#include <linux/platform_device.h>
14
+
#include <linux/spi/spi-mem.h>
15
+
16
+
/* Hardware register definitions */
17
+
#define SPIFMC_CTRL 0x00
18
+
#define SPIFMC_CTRL_CPHA BIT(12)
19
+
#define SPIFMC_CTRL_CPOL BIT(13)
20
+
#define SPIFMC_CTRL_HOLD_OL BIT(14)
21
+
#define SPIFMC_CTRL_WP_OL BIT(15)
22
+
#define SPIFMC_CTRL_LSBF BIT(20)
23
+
#define SPIFMC_CTRL_SRST BIT(21)
24
+
#define SPIFMC_CTRL_SCK_DIV_SHIFT 0
25
+
#define SPIFMC_CTRL_FRAME_LEN_SHIFT 16
26
+
#define SPIFMC_CTRL_SCK_DIV_MASK 0x7FF
27
+
28
+
#define SPIFMC_CE_CTRL 0x04
29
+
#define SPIFMC_CE_CTRL_CEMANUAL BIT(0)
30
+
#define SPIFMC_CE_CTRL_CEMANUAL_EN BIT(1)
31
+
32
+
#define SPIFMC_DLY_CTRL 0x08
33
+
#define SPIFMC_CTRL_FM_INTVL_MASK 0x000f
34
+
#define SPIFMC_CTRL_FM_INTVL BIT(0)
35
+
#define SPIFMC_CTRL_CET_MASK 0x0f00
36
+
#define SPIFMC_CTRL_CET BIT(8)
37
+
38
+
#define SPIFMC_DMMR 0x0c
39
+
40
+
#define SPIFMC_TRAN_CSR 0x10
41
+
#define SPIFMC_TRAN_CSR_TRAN_MODE_MASK GENMASK(1, 0)
42
+
#define SPIFMC_TRAN_CSR_TRAN_MODE_RX BIT(0)
43
+
#define SPIFMC_TRAN_CSR_TRAN_MODE_TX BIT(1)
44
+
#define SPIFMC_TRAN_CSR_FAST_MODE BIT(3)
45
+
#define SPIFMC_TRAN_CSR_BUS_WIDTH_1_BIT (0x00 << 4)
46
+
#define SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT (0x01 << 4)
47
+
#define SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT (0x02 << 4)
48
+
#define SPIFMC_TRAN_CSR_DMA_EN BIT(6)
49
+
#define SPIFMC_TRAN_CSR_MISO_LEVEL BIT(7)
50
+
#define SPIFMC_TRAN_CSR_ADDR_BYTES_MASK GENMASK(10, 8)
51
+
#define SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT 8
52
+
#define SPIFMC_TRAN_CSR_WITH_CMD BIT(11)
53
+
#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_MASK GENMASK(13, 12)
54
+
#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE (0x00 << 12)
55
+
#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_2_BYTE (0x01 << 12)
56
+
#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_4_BYTE (0x02 << 12)
57
+
#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE (0x03 << 12)
58
+
#define SPIFMC_TRAN_CSR_GO_BUSY BIT(15)
59
+
#define SPIFMC_TRAN_CSR_ADDR4B_SHIFT 20
60
+
#define SPIFMC_TRAN_CSR_CMD4B_SHIFT 21
61
+
62
+
#define SPIFMC_TRAN_NUM 0x14
63
+
#define SPIFMC_FIFO_PORT 0x18
64
+
#define SPIFMC_FIFO_PT 0x20
65
+
66
+
#define SPIFMC_INT_STS 0x28
67
+
#define SPIFMC_INT_TRAN_DONE BIT(0)
68
+
#define SPIFMC_INT_RD_FIFO BIT(2)
69
+
#define SPIFMC_INT_WR_FIFO BIT(3)
70
+
#define SPIFMC_INT_RX_FRAME BIT(4)
71
+
#define SPIFMC_INT_TX_FRAME BIT(5)
72
+
73
+
#define SPIFMC_INT_EN 0x2c
74
+
#define SPIFMC_INT_TRAN_DONE_EN BIT(0)
75
+
#define SPIFMC_INT_RD_FIFO_EN BIT(2)
76
+
#define SPIFMC_INT_WR_FIFO_EN BIT(3)
77
+
#define SPIFMC_INT_RX_FRAME_EN BIT(4)
78
+
#define SPIFMC_INT_TX_FRAME_EN BIT(5)
79
+
80
+
#define SPIFMC_OPT 0x030
81
+
#define SPIFMC_OPT_DISABLE_FIFO_FLUSH BIT(1)
82
+
83
+
#define SPIFMC_MAX_FIFO_DEPTH 8
84
+
85
+
#define SPIFMC_MAX_READ_SIZE 0x10000
86
+
87
+
struct sg2044_spifmc {
88
+
struct spi_controller *ctrl;
89
+
void __iomem *io_base;
90
+
struct device *dev;
91
+
struct mutex lock;
92
+
struct clk *clk;
93
+
};
94
+
95
+
static int sg2044_spifmc_wait_int(struct sg2044_spifmc *spifmc, u8 int_type)
96
+
{
97
+
u32 stat;
98
+
99
+
return readl_poll_timeout(spifmc->io_base + SPIFMC_INT_STS, stat,
100
+
(stat & int_type), 0, 1000000);
101
+
}
102
+
103
+
static int sg2044_spifmc_wait_xfer_size(struct sg2044_spifmc *spifmc,
104
+
int xfer_size)
105
+
{
106
+
u8 stat;
107
+
108
+
return readl_poll_timeout(spifmc->io_base + SPIFMC_FIFO_PT, stat,
109
+
((stat & 0xf) == xfer_size), 1, 1000000);
110
+
}
111
+
112
+
static u32 sg2044_spifmc_init_reg(struct sg2044_spifmc *spifmc)
113
+
{
114
+
u32 reg;
115
+
116
+
reg = readl(spifmc->io_base + SPIFMC_TRAN_CSR);
117
+
reg &= ~(SPIFMC_TRAN_CSR_TRAN_MODE_MASK |
118
+
SPIFMC_TRAN_CSR_FAST_MODE |
119
+
SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT |
120
+
SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT |
121
+
SPIFMC_TRAN_CSR_DMA_EN |
122
+
SPIFMC_TRAN_CSR_ADDR_BYTES_MASK |
123
+
SPIFMC_TRAN_CSR_WITH_CMD |
124
+
SPIFMC_TRAN_CSR_FIFO_TRG_LVL_MASK);
125
+
126
+
writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
127
+
128
+
return reg;
129
+
}
130
+
131
+
static ssize_t sg2044_spifmc_read_64k(struct sg2044_spifmc *spifmc,
132
+
const struct spi_mem_op *op, loff_t from,
133
+
size_t len, u_char *buf)
134
+
{
135
+
int xfer_size, offset;
136
+
u32 reg;
137
+
int ret;
138
+
int i;
139
+
140
+
reg = sg2044_spifmc_init_reg(spifmc);
141
+
reg |= (op->addr.nbytes + op->dummy.nbytes) << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT;
142
+
reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE;
143
+
reg |= SPIFMC_TRAN_CSR_WITH_CMD;
144
+
reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX;
145
+
146
+
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
147
+
writeb(op->cmd.opcode, spifmc->io_base + SPIFMC_FIFO_PORT);
148
+
149
+
for (i = op->addr.nbytes - 1; i >= 0; i--)
150
+
writeb((from >> i * 8) & 0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
151
+
152
+
for (i = 0; i < op->dummy.nbytes; i++)
153
+
writeb(0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
154
+
155
+
writel(len, spifmc->io_base + SPIFMC_TRAN_NUM);
156
+
writel(0, spifmc->io_base + SPIFMC_INT_STS);
157
+
reg |= SPIFMC_TRAN_CSR_GO_BUSY;
158
+
writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
159
+
160
+
ret = sg2044_spifmc_wait_int(spifmc, SPIFMC_INT_RD_FIFO);
161
+
if (ret < 0)
162
+
return ret;
163
+
164
+
offset = 0;
165
+
while (offset < len) {
166
+
xfer_size = min_t(size_t, SPIFMC_MAX_FIFO_DEPTH, len - offset);
167
+
168
+
ret = sg2044_spifmc_wait_xfer_size(spifmc, xfer_size);
169
+
if (ret < 0)
170
+
return ret;
171
+
172
+
for (i = 0; i < xfer_size; i++)
173
+
buf[i + offset] = readb(spifmc->io_base + SPIFMC_FIFO_PORT);
174
+
175
+
offset += xfer_size;
176
+
}
177
+
178
+
ret = sg2044_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE);
179
+
if (ret < 0)
180
+
return ret;
181
+
182
+
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
183
+
184
+
return len;
185
+
}
186
+
187
+
static ssize_t sg2044_spifmc_read(struct sg2044_spifmc *spifmc,
188
+
const struct spi_mem_op *op)
189
+
{
190
+
size_t xfer_size;
191
+
size_t offset;
192
+
loff_t from = op->addr.val;
193
+
size_t len = op->data.nbytes;
194
+
int ret;
195
+
u8 *din = op->data.buf.in;
196
+
197
+
offset = 0;
198
+
while (offset < len) {
199
+
xfer_size = min_t(size_t, SPIFMC_MAX_READ_SIZE, len - offset);
200
+
201
+
ret = sg2044_spifmc_read_64k(spifmc, op, from, xfer_size, din);
202
+
if (ret < 0)
203
+
return ret;
204
+
205
+
offset += xfer_size;
206
+
din += xfer_size;
207
+
from += xfer_size;
208
+
}
209
+
210
+
return 0;
211
+
}
212
+
213
+
static ssize_t sg2044_spifmc_write(struct sg2044_spifmc *spifmc,
214
+
const struct spi_mem_op *op)
215
+
{
216
+
size_t xfer_size;
217
+
const u8 *dout = op->data.buf.out;
218
+
int i, offset;
219
+
int ret;
220
+
u32 reg;
221
+
222
+
reg = sg2044_spifmc_init_reg(spifmc);
223
+
reg |= (op->addr.nbytes + op->dummy.nbytes) << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT;
224
+
reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE;
225
+
reg |= SPIFMC_TRAN_CSR_WITH_CMD;
226
+
reg |= SPIFMC_TRAN_CSR_TRAN_MODE_TX;
227
+
228
+
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
229
+
writeb(op->cmd.opcode, spifmc->io_base + SPIFMC_FIFO_PORT);
230
+
231
+
for (i = op->addr.nbytes - 1; i >= 0; i--)
232
+
writeb((op->addr.val >> i * 8) & 0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
233
+
234
+
for (i = 0; i < op->dummy.nbytes; i++)
235
+
writeb(0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
236
+
237
+
writel(0, spifmc->io_base + SPIFMC_INT_STS);
238
+
writel(op->data.nbytes, spifmc->io_base + SPIFMC_TRAN_NUM);
239
+
reg |= SPIFMC_TRAN_CSR_GO_BUSY;
240
+
writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
241
+
242
+
ret = sg2044_spifmc_wait_xfer_size(spifmc, 0);
243
+
if (ret < 0)
244
+
return ret;
245
+
246
+
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
247
+
248
+
offset = 0;
249
+
while (offset < op->data.nbytes) {
250
+
xfer_size = min_t(size_t, SPIFMC_MAX_FIFO_DEPTH, op->data.nbytes - offset);
251
+
252
+
ret = sg2044_spifmc_wait_xfer_size(spifmc, 0);
253
+
if (ret < 0)
254
+
return ret;
255
+
256
+
for (i = 0; i < xfer_size; i++)
257
+
writeb(dout[i + offset], spifmc->io_base + SPIFMC_FIFO_PORT);
258
+
259
+
offset += xfer_size;
260
+
}
261
+
262
+
ret = sg2044_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE);
263
+
if (ret < 0)
264
+
return ret;
265
+
266
+
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
267
+
268
+
return 0;
269
+
}
270
+
271
+
static ssize_t sg2044_spifmc_tran_cmd(struct sg2044_spifmc *spifmc,
272
+
const struct spi_mem_op *op)
273
+
{
274
+
int i, ret;
275
+
u32 reg;
276
+
277
+
reg = sg2044_spifmc_init_reg(spifmc);
278
+
reg |= (op->addr.nbytes + op->dummy.nbytes) << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT;
279
+
reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE;
280
+
reg |= SPIFMC_TRAN_CSR_WITH_CMD;
281
+
282
+
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
283
+
writeb(op->cmd.opcode, spifmc->io_base + SPIFMC_FIFO_PORT);
284
+
285
+
for (i = op->addr.nbytes - 1; i >= 0; i--)
286
+
writeb((op->addr.val >> i * 8) & 0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
287
+
288
+
for (i = 0; i < op->dummy.nbytes; i++)
289
+
writeb(0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
290
+
291
+
writel(0, spifmc->io_base + SPIFMC_INT_STS);
292
+
reg |= SPIFMC_TRAN_CSR_GO_BUSY;
293
+
writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
294
+
295
+
ret = sg2044_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE);
296
+
if (ret < 0)
297
+
return ret;
298
+
299
+
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
300
+
301
+
return 0;
302
+
}
303
+
304
+
static void sg2044_spifmc_trans(struct sg2044_spifmc *spifmc,
305
+
const struct spi_mem_op *op)
306
+
{
307
+
if (op->data.dir == SPI_MEM_DATA_IN)
308
+
sg2044_spifmc_read(spifmc, op);
309
+
else if (op->data.dir == SPI_MEM_DATA_OUT)
310
+
sg2044_spifmc_write(spifmc, op);
311
+
else
312
+
sg2044_spifmc_tran_cmd(spifmc, op);
313
+
}
314
+
315
+
static ssize_t sg2044_spifmc_trans_reg(struct sg2044_spifmc *spifmc,
316
+
const struct spi_mem_op *op)
317
+
{
318
+
const u8 *dout = NULL;
319
+
u8 *din = NULL;
320
+
size_t len = op->data.nbytes;
321
+
int ret, i;
322
+
u32 reg;
323
+
324
+
if (op->data.dir == SPI_MEM_DATA_IN)
325
+
din = op->data.buf.in;
326
+
else
327
+
dout = op->data.buf.out;
328
+
329
+
reg = sg2044_spifmc_init_reg(spifmc);
330
+
reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE;
331
+
reg |= SPIFMC_TRAN_CSR_WITH_CMD;
332
+
333
+
if (din) {
334
+
reg |= SPIFMC_TRAN_CSR_BUS_WIDTH_1_BIT;
335
+
reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX;
336
+
reg |= SPIFMC_TRAN_CSR_TRAN_MODE_TX;
337
+
338
+
writel(SPIFMC_OPT_DISABLE_FIFO_FLUSH, spifmc->io_base + SPIFMC_OPT);
339
+
} else {
340
+
/*
341
+
* If write values to the Status Register,
342
+
* configure TRAN_CSR register as the same as
343
+
* sg2044_spifmc_read_reg.
344
+
*/
345
+
if (op->cmd.opcode == 0x01) {
346
+
reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX;
347
+
reg |= SPIFMC_TRAN_CSR_TRAN_MODE_TX;
348
+
writel(len, spifmc->io_base + SPIFMC_TRAN_NUM);
349
+
}
350
+
}
351
+
352
+
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
353
+
writeb(op->cmd.opcode, spifmc->io_base + SPIFMC_FIFO_PORT);
354
+
355
+
for (i = 0; i < len; i++) {
356
+
if (din)
357
+
writeb(0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
358
+
else
359
+
writeb(dout[i], spifmc->io_base + SPIFMC_FIFO_PORT);
360
+
}
361
+
362
+
writel(0, spifmc->io_base + SPIFMC_INT_STS);
363
+
writel(len, spifmc->io_base + SPIFMC_TRAN_NUM);
364
+
reg |= SPIFMC_TRAN_CSR_GO_BUSY;
365
+
writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
366
+
367
+
ret = sg2044_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE);
368
+
if (ret < 0)
369
+
return ret;
370
+
371
+
if (din) {
372
+
while (len--)
373
+
*din++ = readb(spifmc->io_base + SPIFMC_FIFO_PORT);
374
+
}
375
+
376
+
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
377
+
378
+
return 0;
379
+
}
380
+
381
+
static int sg2044_spifmc_exec_op(struct spi_mem *mem,
382
+
const struct spi_mem_op *op)
383
+
{
384
+
struct sg2044_spifmc *spifmc;
385
+
386
+
spifmc = spi_controller_get_devdata(mem->spi->controller);
387
+
388
+
mutex_lock(&spifmc->lock);
389
+
390
+
if (op->addr.nbytes == 0)
391
+
sg2044_spifmc_trans_reg(spifmc, op);
392
+
else
393
+
sg2044_spifmc_trans(spifmc, op);
394
+
395
+
mutex_unlock(&spifmc->lock);
396
+
397
+
return 0;
398
+
}
399
+
400
+
static const struct spi_controller_mem_ops sg2044_spifmc_mem_ops = {
401
+
.exec_op = sg2044_spifmc_exec_op,
402
+
};
403
+
404
+
static void sg2044_spifmc_init(struct sg2044_spifmc *spifmc)
405
+
{
406
+
u32 tran_csr;
407
+
u32 reg;
408
+
409
+
writel(0, spifmc->io_base + SPIFMC_DMMR);
410
+
411
+
reg = readl(spifmc->io_base + SPIFMC_CTRL);
412
+
reg |= SPIFMC_CTRL_SRST;
413
+
reg &= ~(SPIFMC_CTRL_SCK_DIV_MASK);
414
+
reg |= 1;
415
+
writel(reg, spifmc->io_base + SPIFMC_CTRL);
416
+
417
+
writel(0, spifmc->io_base + SPIFMC_CE_CTRL);
418
+
419
+
tran_csr = readl(spifmc->io_base + SPIFMC_TRAN_CSR);
420
+
tran_csr |= (0 << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT);
421
+
tran_csr |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_4_BYTE;
422
+
tran_csr |= SPIFMC_TRAN_CSR_WITH_CMD;
423
+
writel(tran_csr, spifmc->io_base + SPIFMC_TRAN_CSR);
424
+
}
425
+
426
+
static int sg2044_spifmc_probe(struct platform_device *pdev)
427
+
{
428
+
struct device *dev = &pdev->dev;
429
+
struct spi_controller *ctrl;
430
+
struct sg2044_spifmc *spifmc;
431
+
int ret;
432
+
433
+
ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(*spifmc));
434
+
if (!ctrl)
435
+
return -ENOMEM;
436
+
437
+
spifmc = spi_controller_get_devdata(ctrl);
438
+
439
+
spifmc->clk = devm_clk_get_enabled(&pdev->dev, NULL);
440
+
if (IS_ERR(spifmc->clk))
441
+
return dev_err_probe(dev, PTR_ERR(spifmc->clk), "Cannot get and enable AHB clock\n");
442
+
443
+
spifmc->dev = &pdev->dev;
444
+
spifmc->ctrl = ctrl;
445
+
446
+
spifmc->io_base = devm_platform_ioremap_resource(pdev, 0);
447
+
if (IS_ERR(spifmc->io_base))
448
+
return PTR_ERR(spifmc->io_base);
449
+
450
+
ctrl->num_chipselect = 1;
451
+
ctrl->dev.of_node = pdev->dev.of_node;
452
+
ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
453
+
ctrl->auto_runtime_pm = false;
454
+
ctrl->mem_ops = &sg2044_spifmc_mem_ops;
455
+
ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | SPI_RX_QUAD | SPI_TX_QUAD;
456
+
457
+
ret = devm_mutex_init(dev, &spifmc->lock);
458
+
if (ret)
459
+
return ret;
460
+
461
+
sg2044_spifmc_init(spifmc);
462
+
sg2044_spifmc_init_reg(spifmc);
463
+
464
+
ret = devm_spi_register_controller(&pdev->dev, ctrl);
465
+
if (ret)
466
+
return dev_err_probe(dev, ret, "spi_register_controller failed\n");
467
+
468
+
return 0;
469
+
}
470
+
471
+
static const struct of_device_id sg2044_spifmc_match[] = {
472
+
{ .compatible = "sophgo,sg2044-spifmc-nor" },
473
+
{ /* sentinel */ }
474
+
};
475
+
MODULE_DEVICE_TABLE(of, sg2044_spifmc_match);
476
+
477
+
static struct platform_driver sg2044_nor_driver = {
478
+
.driver = {
479
+
.name = "sg2044,spifmc-nor",
480
+
.of_match_table = sg2044_spifmc_match,
481
+
},
482
+
.probe = sg2044_spifmc_probe,
483
+
};
484
+
module_platform_driver(sg2044_nor_driver);
485
+
486
+
MODULE_DESCRIPTION("SG2044 SPI NOR controller driver");
487
+
MODULE_AUTHOR("Longbin Li <looong.bin@gmail.com>");
488
+
MODULE_LICENSE("GPL");
+1063
drivers/spi/spi-stm32-ospi.c
+1063
drivers/spi/spi-stm32-ospi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
4
+
*/
5
+
6
+
#include <linux/bitfield.h>
7
+
#include <linux/clk.h>
8
+
#include <linux/delay.h>
9
+
#include <linux/dma-mapping.h>
10
+
#include <linux/dmaengine.h>
11
+
#include <linux/err.h>
12
+
#include <linux/errno.h>
13
+
#include <linux/gpio/consumer.h>
14
+
#include <linux/interrupt.h>
15
+
#include <linux/io.h>
16
+
#include <linux/iopoll.h>
17
+
#include <linux/mfd/syscon.h>
18
+
#include <linux/module.h>
19
+
#include <linux/mutex.h>
20
+
#include <linux/of.h>
21
+
#include <linux/of_address.h>
22
+
#include <linux/of_device.h>
23
+
#include <linux/of_reserved_mem.h>
24
+
#include <linux/pinctrl/consumer.h>
25
+
#include <linux/platform_device.h>
26
+
#include <linux/pm_runtime.h>
27
+
#include <linux/reset.h>
28
+
#include <linux/sizes.h>
29
+
#include <linux/spi/spi-mem.h>
30
+
#include <linux/types.h>
31
+
32
+
#define OSPI_CR 0x00
33
+
#define CR_EN BIT(0)
34
+
#define CR_ABORT BIT(1)
35
+
#define CR_DMAEN BIT(2)
36
+
#define CR_FTHRES_SHIFT 8
37
+
#define CR_TEIE BIT(16)
38
+
#define CR_TCIE BIT(17)
39
+
#define CR_SMIE BIT(19)
40
+
#define CR_APMS BIT(22)
41
+
#define CR_CSSEL BIT(24)
42
+
#define CR_FMODE_MASK GENMASK(29, 28)
43
+
#define CR_FMODE_INDW (0U)
44
+
#define CR_FMODE_INDR (1U)
45
+
#define CR_FMODE_APM (2U)
46
+
#define CR_FMODE_MM (3U)
47
+
48
+
#define OSPI_DCR1 0x08
49
+
#define DCR1_DLYBYP BIT(3)
50
+
#define DCR1_DEVSIZE_MASK GENMASK(20, 16)
51
+
#define DCR1_MTYP_MASK GENMASK(26, 24)
52
+
#define DCR1_MTYP_MX_MODE 1
53
+
#define DCR1_MTYP_HP_MEMMODE 4
54
+
55
+
#define OSPI_DCR2 0x0c
56
+
#define DCR2_PRESC_MASK GENMASK(7, 0)
57
+
58
+
#define OSPI_SR 0x20
59
+
#define SR_TEF BIT(0)
60
+
#define SR_TCF BIT(1)
61
+
#define SR_FTF BIT(2)
62
+
#define SR_SMF BIT(3)
63
+
#define SR_BUSY BIT(5)
64
+
65
+
#define OSPI_FCR 0x24
66
+
#define FCR_CTEF BIT(0)
67
+
#define FCR_CTCF BIT(1)
68
+
#define FCR_CSMF BIT(3)
69
+
70
+
#define OSPI_DLR 0x40
71
+
#define OSPI_AR 0x48
72
+
#define OSPI_DR 0x50
73
+
#define OSPI_PSMKR 0x80
74
+
#define OSPI_PSMAR 0x88
75
+
76
+
#define OSPI_CCR 0x100
77
+
#define CCR_IMODE_MASK GENMASK(2, 0)
78
+
#define CCR_IDTR BIT(3)
79
+
#define CCR_ISIZE_MASK GENMASK(5, 4)
80
+
#define CCR_ADMODE_MASK GENMASK(10, 8)
81
+
#define CCR_ADMODE_8LINES 4
82
+
#define CCR_ADDTR BIT(11)
83
+
#define CCR_ADSIZE_MASK GENMASK(13, 12)
84
+
#define CCR_ADSIZE_32BITS 3
85
+
#define CCR_DMODE_MASK GENMASK(26, 24)
86
+
#define CCR_DMODE_8LINES 4
87
+
#define CCR_DQSE BIT(29)
88
+
#define CCR_DDTR BIT(27)
89
+
#define CCR_BUSWIDTH_0 0x0
90
+
#define CCR_BUSWIDTH_1 0x1
91
+
#define CCR_BUSWIDTH_2 0x2
92
+
#define CCR_BUSWIDTH_4 0x3
93
+
#define CCR_BUSWIDTH_8 0x4
94
+
95
+
#define OSPI_TCR 0x108
96
+
#define TCR_DCYC_MASK GENMASK(4, 0)
97
+
#define TCR_DHQC BIT(28)
98
+
#define TCR_SSHIFT BIT(30)
99
+
100
+
#define OSPI_IR 0x110
101
+
102
+
#define STM32_OSPI_MAX_MMAP_SZ SZ_256M
103
+
#define STM32_OSPI_MAX_NORCHIP 2
104
+
105
+
#define STM32_FIFO_TIMEOUT_US 30000
106
+
#define STM32_ABT_TIMEOUT_US 100000
107
+
#define STM32_COMP_TIMEOUT_MS 5000
108
+
#define STM32_BUSY_TIMEOUT_US 100000
109
+
110
+
111
+
#define STM32_AUTOSUSPEND_DELAY -1
112
+
113
+
struct stm32_ospi {
114
+
struct device *dev;
115
+
struct spi_controller *ctrl;
116
+
struct clk *clk;
117
+
struct reset_control *rstc;
118
+
119
+
struct completion data_completion;
120
+
struct completion match_completion;
121
+
122
+
struct dma_chan *dma_chtx;
123
+
struct dma_chan *dma_chrx;
124
+
struct completion dma_completion;
125
+
126
+
void __iomem *regs_base;
127
+
void __iomem *mm_base;
128
+
phys_addr_t regs_phys_base;
129
+
resource_size_t mm_size;
130
+
u32 clk_rate;
131
+
u32 fmode;
132
+
u32 cr_reg;
133
+
u32 dcr_reg;
134
+
u32 flash_presc[STM32_OSPI_MAX_NORCHIP];
135
+
int irq;
136
+
unsigned long status_timeout;
137
+
138
+
/*
139
+
* To protect device configuration, could be different between
140
+
* 2 flash access
141
+
*/
142
+
struct mutex lock;
143
+
};
144
+
145
+
static void stm32_ospi_read_fifo(u8 *val, void __iomem *addr)
146
+
{
147
+
*val = readb_relaxed(addr);
148
+
}
149
+
150
+
static void stm32_ospi_write_fifo(u8 *val, void __iomem *addr)
151
+
{
152
+
writeb_relaxed(*val, addr);
153
+
}
154
+
155
+
static int stm32_ospi_abort(struct stm32_ospi *ospi)
156
+
{
157
+
void __iomem *regs_base = ospi->regs_base;
158
+
u32 cr;
159
+
int timeout;
160
+
161
+
cr = readl_relaxed(regs_base + OSPI_CR) | CR_ABORT;
162
+
writel_relaxed(cr, regs_base + OSPI_CR);
163
+
164
+
/* wait clear of abort bit by hw */
165
+
timeout = readl_relaxed_poll_timeout_atomic(regs_base + OSPI_CR,
166
+
cr, !(cr & CR_ABORT), 1,
167
+
STM32_ABT_TIMEOUT_US);
168
+
169
+
if (timeout)
170
+
dev_err(ospi->dev, "%s abort timeout:%d\n", __func__, timeout);
171
+
172
+
return timeout;
173
+
}
174
+
175
+
static int stm32_ospi_poll(struct stm32_ospi *ospi, u8 *buf, u32 len, bool read)
176
+
{
177
+
void __iomem *regs_base = ospi->regs_base;
178
+
void (*fifo)(u8 *val, void __iomem *addr);
179
+
u32 sr;
180
+
int ret;
181
+
182
+
if (read)
183
+
fifo = stm32_ospi_read_fifo;
184
+
else
185
+
fifo = stm32_ospi_write_fifo;
186
+
187
+
while (len--) {
188
+
ret = readl_relaxed_poll_timeout_atomic(regs_base + OSPI_SR,
189
+
sr, sr & SR_FTF, 1,
190
+
STM32_FIFO_TIMEOUT_US);
191
+
if (ret) {
192
+
dev_err(ospi->dev, "fifo timeout (len:%d stat:%#x)\n",
193
+
len, sr);
194
+
return ret;
195
+
}
196
+
fifo(buf++, regs_base + OSPI_DR);
197
+
}
198
+
199
+
return 0;
200
+
}
201
+
202
+
static int stm32_ospi_wait_nobusy(struct stm32_ospi *ospi)
203
+
{
204
+
u32 sr;
205
+
206
+
return readl_relaxed_poll_timeout_atomic(ospi->regs_base + OSPI_SR,
207
+
sr, !(sr & SR_BUSY), 1,
208
+
STM32_BUSY_TIMEOUT_US);
209
+
}
210
+
211
+
static int stm32_ospi_wait_cmd(struct stm32_ospi *ospi)
212
+
{
213
+
void __iomem *regs_base = ospi->regs_base;
214
+
u32 cr, sr;
215
+
int err = 0;
216
+
217
+
if ((readl_relaxed(regs_base + OSPI_SR) & SR_TCF) ||
218
+
ospi->fmode == CR_FMODE_APM)
219
+
goto out;
220
+
221
+
reinit_completion(&ospi->data_completion);
222
+
cr = readl_relaxed(regs_base + OSPI_CR);
223
+
writel_relaxed(cr | CR_TCIE | CR_TEIE, regs_base + OSPI_CR);
224
+
225
+
if (!wait_for_completion_timeout(&ospi->data_completion,
226
+
msecs_to_jiffies(STM32_COMP_TIMEOUT_MS)))
227
+
err = -ETIMEDOUT;
228
+
229
+
sr = readl_relaxed(regs_base + OSPI_SR);
230
+
if (sr & SR_TCF)
231
+
/* avoid false timeout */
232
+
err = 0;
233
+
if (sr & SR_TEF)
234
+
err = -EIO;
235
+
236
+
out:
237
+
/* clear flags */
238
+
writel_relaxed(FCR_CTCF | FCR_CTEF, regs_base + OSPI_FCR);
239
+
240
+
if (!err)
241
+
err = stm32_ospi_wait_nobusy(ospi);
242
+
243
+
return err;
244
+
}
245
+
246
+
static void stm32_ospi_dma_callback(void *arg)
247
+
{
248
+
struct completion *dma_completion = arg;
249
+
250
+
complete(dma_completion);
251
+
}
252
+
253
+
static irqreturn_t stm32_ospi_irq(int irq, void *dev_id)
254
+
{
255
+
struct stm32_ospi *ospi = (struct stm32_ospi *)dev_id;
256
+
void __iomem *regs_base = ospi->regs_base;
257
+
u32 cr, sr;
258
+
259
+
cr = readl_relaxed(regs_base + OSPI_CR);
260
+
sr = readl_relaxed(regs_base + OSPI_SR);
261
+
262
+
if (cr & CR_SMIE && sr & SR_SMF) {
263
+
/* disable irq */
264
+
cr &= ~CR_SMIE;
265
+
writel_relaxed(cr, regs_base + OSPI_CR);
266
+
complete(&ospi->match_completion);
267
+
268
+
return IRQ_HANDLED;
269
+
}
270
+
271
+
if (sr & (SR_TEF | SR_TCF)) {
272
+
/* disable irq */
273
+
cr &= ~CR_TCIE & ~CR_TEIE;
274
+
writel_relaxed(cr, regs_base + OSPI_CR);
275
+
complete(&ospi->data_completion);
276
+
}
277
+
278
+
return IRQ_HANDLED;
279
+
}
280
+
281
+
static void stm32_ospi_dma_setup(struct stm32_ospi *ospi,
282
+
struct dma_slave_config *dma_cfg)
283
+
{
284
+
if (dma_cfg && ospi->dma_chrx) {
285
+
if (dmaengine_slave_config(ospi->dma_chrx, dma_cfg)) {
286
+
dev_err(ospi->dev, "dma rx config failed\n");
287
+
dma_release_channel(ospi->dma_chrx);
288
+
ospi->dma_chrx = NULL;
289
+
}
290
+
}
291
+
292
+
if (dma_cfg && ospi->dma_chtx) {
293
+
if (dmaengine_slave_config(ospi->dma_chtx, dma_cfg)) {
294
+
dev_err(ospi->dev, "dma tx config failed\n");
295
+
dma_release_channel(ospi->dma_chtx);
296
+
ospi->dma_chtx = NULL;
297
+
}
298
+
}
299
+
300
+
init_completion(&ospi->dma_completion);
301
+
}
302
+
303
+
static int stm32_ospi_tx_mm(struct stm32_ospi *ospi,
304
+
const struct spi_mem_op *op)
305
+
{
306
+
memcpy_fromio(op->data.buf.in, ospi->mm_base + op->addr.val,
307
+
op->data.nbytes);
308
+
return 0;
309
+
}
310
+
311
+
static int stm32_ospi_tx_dma(struct stm32_ospi *ospi,
312
+
const struct spi_mem_op *op)
313
+
{
314
+
struct dma_async_tx_descriptor *desc;
315
+
void __iomem *regs_base = ospi->regs_base;
316
+
enum dma_transfer_direction dma_dir;
317
+
struct dma_chan *dma_ch;
318
+
struct sg_table sgt;
319
+
dma_cookie_t cookie;
320
+
u32 cr, t_out;
321
+
int err;
322
+
323
+
if (op->data.dir == SPI_MEM_DATA_IN) {
324
+
dma_dir = DMA_DEV_TO_MEM;
325
+
dma_ch = ospi->dma_chrx;
326
+
} else {
327
+
dma_dir = DMA_MEM_TO_DEV;
328
+
dma_ch = ospi->dma_chtx;
329
+
}
330
+
331
+
/*
332
+
* Spi_map_buf return -EINVAL if the buffer is not DMA-able
333
+
* (DMA-able: in vmalloc | kmap | virt_addr_valid)
334
+
*/
335
+
err = spi_controller_dma_map_mem_op_data(ospi->ctrl, op, &sgt);
336
+
if (err)
337
+
return err;
338
+
339
+
desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents,
340
+
dma_dir, DMA_PREP_INTERRUPT);
341
+
if (!desc) {
342
+
err = -ENOMEM;
343
+
goto out_unmap;
344
+
}
345
+
346
+
cr = readl_relaxed(regs_base + OSPI_CR);
347
+
348
+
reinit_completion(&ospi->dma_completion);
349
+
desc->callback = stm32_ospi_dma_callback;
350
+
desc->callback_param = &ospi->dma_completion;
351
+
cookie = dmaengine_submit(desc);
352
+
err = dma_submit_error(cookie);
353
+
if (err)
354
+
goto out;
355
+
356
+
dma_async_issue_pending(dma_ch);
357
+
358
+
writel_relaxed(cr | CR_DMAEN, regs_base + OSPI_CR);
359
+
360
+
t_out = sgt.nents * STM32_COMP_TIMEOUT_MS;
361
+
if (!wait_for_completion_timeout(&ospi->dma_completion,
362
+
msecs_to_jiffies(t_out)))
363
+
err = -ETIMEDOUT;
364
+
365
+
if (err)
366
+
dmaengine_terminate_all(dma_ch);
367
+
368
+
out:
369
+
writel_relaxed(cr & ~CR_DMAEN, regs_base + OSPI_CR);
370
+
out_unmap:
371
+
spi_controller_dma_unmap_mem_op_data(ospi->ctrl, op, &sgt);
372
+
373
+
return err;
374
+
}
375
+
376
+
static int stm32_ospi_xfer(struct stm32_ospi *ospi, const struct spi_mem_op *op)
377
+
{
378
+
u8 *buf;
379
+
380
+
if (!op->data.nbytes)
381
+
return 0;
382
+
383
+
if (ospi->fmode == CR_FMODE_MM)
384
+
return stm32_ospi_tx_mm(ospi, op);
385
+
else if (((op->data.dir == SPI_MEM_DATA_IN && ospi->dma_chrx) ||
386
+
(op->data.dir == SPI_MEM_DATA_OUT && ospi->dma_chtx)) &&
387
+
op->data.nbytes > 8)
388
+
if (!stm32_ospi_tx_dma(ospi, op))
389
+
return 0;
390
+
391
+
if (op->data.dir == SPI_MEM_DATA_IN)
392
+
buf = op->data.buf.in;
393
+
else
394
+
buf = (u8 *)op->data.buf.out;
395
+
396
+
return stm32_ospi_poll(ospi, buf, op->data.nbytes,
397
+
op->data.dir == SPI_MEM_DATA_IN);
398
+
}
399
+
400
+
static int stm32_ospi_wait_poll_status(struct stm32_ospi *ospi,
401
+
const struct spi_mem_op *op)
402
+
{
403
+
void __iomem *regs_base = ospi->regs_base;
404
+
u32 cr;
405
+
406
+
reinit_completion(&ospi->match_completion);
407
+
cr = readl_relaxed(regs_base + OSPI_CR);
408
+
writel_relaxed(cr | CR_SMIE, regs_base + OSPI_CR);
409
+
410
+
if (!wait_for_completion_timeout(&ospi->match_completion,
411
+
msecs_to_jiffies(ospi->status_timeout))) {
412
+
u32 sr = readl_relaxed(regs_base + OSPI_SR);
413
+
414
+
/* Avoid false timeout */
415
+
if (!(sr & SR_SMF))
416
+
return -ETIMEDOUT;
417
+
}
418
+
419
+
writel_relaxed(FCR_CSMF, regs_base + OSPI_FCR);
420
+
421
+
return 0;
422
+
}
423
+
424
+
static int stm32_ospi_get_mode(u8 buswidth)
425
+
{
426
+
switch (buswidth) {
427
+
case 8:
428
+
return CCR_BUSWIDTH_8;
429
+
case 4:
430
+
return CCR_BUSWIDTH_4;
431
+
default:
432
+
return buswidth;
433
+
}
434
+
}
435
+
436
+
static int stm32_ospi_send(struct spi_device *spi, const struct spi_mem_op *op)
437
+
{
438
+
struct stm32_ospi *ospi = spi_controller_get_devdata(spi->controller);
439
+
void __iomem *regs_base = ospi->regs_base;
440
+
u32 ccr, cr, dcr2, tcr;
441
+
int timeout, err = 0, err_poll_status = 0;
442
+
u8 cs = spi->chip_select[ffs(spi->cs_index_mask) - 1];
443
+
444
+
dev_dbg(ospi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
445
+
op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
446
+
op->dummy.buswidth, op->data.buswidth,
447
+
op->addr.val, op->data.nbytes);
448
+
449
+
cr = readl_relaxed(ospi->regs_base + OSPI_CR);
450
+
cr &= ~CR_CSSEL;
451
+
cr |= FIELD_PREP(CR_CSSEL, cs);
452
+
cr &= ~CR_FMODE_MASK;
453
+
cr |= FIELD_PREP(CR_FMODE_MASK, ospi->fmode);
454
+
writel_relaxed(cr, regs_base + OSPI_CR);
455
+
456
+
if (op->data.nbytes)
457
+
writel_relaxed(op->data.nbytes - 1, regs_base + OSPI_DLR);
458
+
459
+
/* set prescaler */
460
+
dcr2 = readl_relaxed(regs_base + OSPI_DCR2);
461
+
dcr2 |= FIELD_PREP(DCR2_PRESC_MASK, ospi->flash_presc[cs]);
462
+
writel_relaxed(dcr2, regs_base + OSPI_DCR2);
463
+
464
+
ccr = FIELD_PREP(CCR_IMODE_MASK, stm32_ospi_get_mode(op->cmd.buswidth));
465
+
466
+
if (op->addr.nbytes) {
467
+
ccr |= FIELD_PREP(CCR_ADMODE_MASK,
468
+
stm32_ospi_get_mode(op->addr.buswidth));
469
+
ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
470
+
}
471
+
472
+
tcr = TCR_SSHIFT;
473
+
if (op->dummy.buswidth && op->dummy.nbytes) {
474
+
tcr |= FIELD_PREP(TCR_DCYC_MASK,
475
+
op->dummy.nbytes * 8 / op->dummy.buswidth);
476
+
}
477
+
writel_relaxed(tcr, regs_base + OSPI_TCR);
478
+
479
+
if (op->data.nbytes) {
480
+
ccr |= FIELD_PREP(CCR_DMODE_MASK,
481
+
stm32_ospi_get_mode(op->data.buswidth));
482
+
}
483
+
484
+
writel_relaxed(ccr, regs_base + OSPI_CCR);
485
+
486
+
/* set instruction, must be set after ccr register update */
487
+
writel_relaxed(op->cmd.opcode, regs_base + OSPI_IR);
488
+
489
+
if (op->addr.nbytes && ospi->fmode != CR_FMODE_MM)
490
+
writel_relaxed(op->addr.val, regs_base + OSPI_AR);
491
+
492
+
if (ospi->fmode == CR_FMODE_APM)
493
+
err_poll_status = stm32_ospi_wait_poll_status(ospi, op);
494
+
495
+
err = stm32_ospi_xfer(ospi, op);
496
+
497
+
/*
498
+
* Abort in:
499
+
* -error case
500
+
* -read memory map: prefetching must be stopped if we read the last
501
+
* byte of device (device size - fifo size). like device size is not
502
+
* knows, the prefetching is always stop.
503
+
*/
504
+
if (err || err_poll_status || ospi->fmode == CR_FMODE_MM)
505
+
goto abort;
506
+
507
+
/* Wait end of tx in indirect mode */
508
+
err = stm32_ospi_wait_cmd(ospi);
509
+
if (err)
510
+
goto abort;
511
+
512
+
return 0;
513
+
514
+
abort:
515
+
timeout = stm32_ospi_abort(ospi);
516
+
writel_relaxed(FCR_CTCF | FCR_CSMF, regs_base + OSPI_FCR);
517
+
518
+
if (err || err_poll_status || timeout)
519
+
dev_err(ospi->dev, "%s err:%d err_poll_status:%d abort timeout:%d\n",
520
+
__func__, err, err_poll_status, timeout);
521
+
522
+
return err;
523
+
}
524
+
525
+
static int stm32_ospi_poll_status(struct spi_mem *mem,
526
+
const struct spi_mem_op *op,
527
+
u16 mask, u16 match,
528
+
unsigned long initial_delay_us,
529
+
unsigned long polling_rate_us,
530
+
unsigned long timeout_ms)
531
+
{
532
+
struct stm32_ospi *ospi = spi_controller_get_devdata(mem->spi->controller);
533
+
void __iomem *regs_base = ospi->regs_base;
534
+
int ret;
535
+
536
+
ret = pm_runtime_resume_and_get(ospi->dev);
537
+
if (ret < 0)
538
+
return ret;
539
+
540
+
mutex_lock(&ospi->lock);
541
+
542
+
writel_relaxed(mask, regs_base + OSPI_PSMKR);
543
+
writel_relaxed(match, regs_base + OSPI_PSMAR);
544
+
ospi->fmode = CR_FMODE_APM;
545
+
ospi->status_timeout = timeout_ms;
546
+
547
+
ret = stm32_ospi_send(mem->spi, op);
548
+
mutex_unlock(&ospi->lock);
549
+
550
+
pm_runtime_mark_last_busy(ospi->dev);
551
+
pm_runtime_put_autosuspend(ospi->dev);
552
+
553
+
return ret;
554
+
}
555
+
556
+
static int stm32_ospi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
557
+
{
558
+
struct stm32_ospi *ospi = spi_controller_get_devdata(mem->spi->controller);
559
+
int ret;
560
+
561
+
ret = pm_runtime_resume_and_get(ospi->dev);
562
+
if (ret < 0)
563
+
return ret;
564
+
565
+
mutex_lock(&ospi->lock);
566
+
if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes)
567
+
ospi->fmode = CR_FMODE_INDR;
568
+
else
569
+
ospi->fmode = CR_FMODE_INDW;
570
+
571
+
ret = stm32_ospi_send(mem->spi, op);
572
+
mutex_unlock(&ospi->lock);
573
+
574
+
pm_runtime_mark_last_busy(ospi->dev);
575
+
pm_runtime_put_autosuspend(ospi->dev);
576
+
577
+
return ret;
578
+
}
579
+
580
+
static int stm32_ospi_dirmap_create(struct spi_mem_dirmap_desc *desc)
581
+
{
582
+
struct stm32_ospi *ospi = spi_controller_get_devdata(desc->mem->spi->controller);
583
+
584
+
if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
585
+
return -EOPNOTSUPP;
586
+
587
+
/* Should never happen, as mm_base == null is an error probe exit condition */
588
+
if (!ospi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
589
+
return -EOPNOTSUPP;
590
+
591
+
if (!ospi->mm_size)
592
+
return -EOPNOTSUPP;
593
+
594
+
return 0;
595
+
}
596
+
597
+
static ssize_t stm32_ospi_dirmap_read(struct spi_mem_dirmap_desc *desc,
598
+
u64 offs, size_t len, void *buf)
599
+
{
600
+
struct stm32_ospi *ospi = spi_controller_get_devdata(desc->mem->spi->controller);
601
+
struct spi_mem_op op;
602
+
u32 addr_max;
603
+
int ret;
604
+
605
+
ret = pm_runtime_resume_and_get(ospi->dev);
606
+
if (ret < 0)
607
+
return ret;
608
+
609
+
mutex_lock(&ospi->lock);
610
+
/*
611
+
* Make a local copy of desc op_tmpl and complete dirmap rdesc
612
+
* spi_mem_op template with offs, len and *buf in order to get
613
+
* all needed transfer information into struct spi_mem_op
614
+
*/
615
+
memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op));
616
+
dev_dbg(ospi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf);
617
+
618
+
op.data.nbytes = len;
619
+
op.addr.val = desc->info.offset + offs;
620
+
op.data.buf.in = buf;
621
+
622
+
addr_max = op.addr.val + op.data.nbytes + 1;
623
+
if (addr_max < ospi->mm_size && op.addr.buswidth)
624
+
ospi->fmode = CR_FMODE_MM;
625
+
else
626
+
ospi->fmode = CR_FMODE_INDR;
627
+
628
+
ret = stm32_ospi_send(desc->mem->spi, &op);
629
+
mutex_unlock(&ospi->lock);
630
+
631
+
pm_runtime_mark_last_busy(ospi->dev);
632
+
pm_runtime_put_autosuspend(ospi->dev);
633
+
634
+
return ret ?: len;
635
+
}
636
+
637
+
static int stm32_ospi_transfer_one_message(struct spi_controller *ctrl,
638
+
struct spi_message *msg)
639
+
{
640
+
struct stm32_ospi *ospi = spi_controller_get_devdata(ctrl);
641
+
struct spi_transfer *transfer;
642
+
struct spi_device *spi = msg->spi;
643
+
struct spi_mem_op op;
644
+
struct gpio_desc *cs_gpiod = spi->cs_gpiod[ffs(spi->cs_index_mask) - 1];
645
+
int ret = 0;
646
+
647
+
if (!cs_gpiod)
648
+
return -EOPNOTSUPP;
649
+
650
+
ret = pm_runtime_resume_and_get(ospi->dev);
651
+
if (ret < 0)
652
+
return ret;
653
+
654
+
mutex_lock(&ospi->lock);
655
+
656
+
gpiod_set_value_cansleep(cs_gpiod, true);
657
+
658
+
list_for_each_entry(transfer, &msg->transfers, transfer_list) {
659
+
u8 dummy_bytes = 0;
660
+
661
+
memset(&op, 0, sizeof(op));
662
+
663
+
dev_dbg(ospi->dev, "tx_buf:%p tx_nbits:%d rx_buf:%p rx_nbits:%d len:%d dummy_data:%d\n",
664
+
transfer->tx_buf, transfer->tx_nbits,
665
+
transfer->rx_buf, transfer->rx_nbits,
666
+
transfer->len, transfer->dummy_data);
667
+
668
+
/*
669
+
* OSPI hardware supports dummy bytes transfer.
670
+
* If current transfer is dummy byte, merge it with the next
671
+
* transfer in order to take into account OSPI block constraint
672
+
*/
673
+
if (transfer->dummy_data) {
674
+
op.dummy.buswidth = transfer->tx_nbits;
675
+
op.dummy.nbytes = transfer->len;
676
+
dummy_bytes = transfer->len;
677
+
678
+
/* If happens, means that message is not correctly built */
679
+
if (list_is_last(&transfer->transfer_list, &msg->transfers)) {
680
+
ret = -EINVAL;
681
+
goto end_of_transfer;
682
+
}
683
+
684
+
transfer = list_next_entry(transfer, transfer_list);
685
+
}
686
+
687
+
op.data.nbytes = transfer->len;
688
+
689
+
if (transfer->rx_buf) {
690
+
ospi->fmode = CR_FMODE_INDR;
691
+
op.data.buswidth = transfer->rx_nbits;
692
+
op.data.dir = SPI_MEM_DATA_IN;
693
+
op.data.buf.in = transfer->rx_buf;
694
+
} else {
695
+
ospi->fmode = CR_FMODE_INDW;
696
+
op.data.buswidth = transfer->tx_nbits;
697
+
op.data.dir = SPI_MEM_DATA_OUT;
698
+
op.data.buf.out = transfer->tx_buf;
699
+
}
700
+
701
+
ret = stm32_ospi_send(spi, &op);
702
+
if (ret)
703
+
goto end_of_transfer;
704
+
705
+
msg->actual_length += transfer->len + dummy_bytes;
706
+
}
707
+
708
+
end_of_transfer:
709
+
gpiod_set_value_cansleep(cs_gpiod, false);
710
+
711
+
mutex_unlock(&ospi->lock);
712
+
713
+
msg->status = ret;
714
+
spi_finalize_current_message(ctrl);
715
+
716
+
pm_runtime_mark_last_busy(ospi->dev);
717
+
pm_runtime_put_autosuspend(ospi->dev);
718
+
719
+
return ret;
720
+
}
721
+
722
+
static int stm32_ospi_setup(struct spi_device *spi)
723
+
{
724
+
struct spi_controller *ctrl = spi->controller;
725
+
struct stm32_ospi *ospi = spi_controller_get_devdata(ctrl);
726
+
void __iomem *regs_base = ospi->regs_base;
727
+
int ret;
728
+
u8 cs = spi->chip_select[ffs(spi->cs_index_mask) - 1];
729
+
730
+
if (ctrl->busy)
731
+
return -EBUSY;
732
+
733
+
if (!spi->max_speed_hz)
734
+
return -EINVAL;
735
+
736
+
ret = pm_runtime_resume_and_get(ospi->dev);
737
+
if (ret < 0)
738
+
return ret;
739
+
740
+
ospi->flash_presc[cs] = DIV_ROUND_UP(ospi->clk_rate, spi->max_speed_hz) - 1;
741
+
742
+
mutex_lock(&ospi->lock);
743
+
744
+
ospi->cr_reg = CR_APMS | 3 << CR_FTHRES_SHIFT | CR_EN;
745
+
writel_relaxed(ospi->cr_reg, regs_base + OSPI_CR);
746
+
747
+
/* set dcr fsize to max address */
748
+
ospi->dcr_reg = DCR1_DEVSIZE_MASK | DCR1_DLYBYP;
749
+
writel_relaxed(ospi->dcr_reg, regs_base + OSPI_DCR1);
750
+
751
+
mutex_unlock(&ospi->lock);
752
+
753
+
pm_runtime_mark_last_busy(ospi->dev);
754
+
pm_runtime_put_autosuspend(ospi->dev);
755
+
756
+
return 0;
757
+
}
758
+
759
+
/*
760
+
* No special host constraint, so use default spi_mem_default_supports_op
761
+
* to check supported mode.
762
+
*/
763
+
static const struct spi_controller_mem_ops stm32_ospi_mem_ops = {
764
+
.exec_op = stm32_ospi_exec_op,
765
+
.dirmap_create = stm32_ospi_dirmap_create,
766
+
.dirmap_read = stm32_ospi_dirmap_read,
767
+
.poll_status = stm32_ospi_poll_status,
768
+
};
769
+
770
+
static int stm32_ospi_get_resources(struct platform_device *pdev)
771
+
{
772
+
struct device *dev = &pdev->dev;
773
+
struct stm32_ospi *ospi = platform_get_drvdata(pdev);
774
+
struct resource *res;
775
+
struct reserved_mem *rmem = NULL;
776
+
struct device_node *node;
777
+
int ret;
778
+
779
+
ospi->regs_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
780
+
if (IS_ERR(ospi->regs_base))
781
+
return PTR_ERR(ospi->regs_base);
782
+
783
+
ospi->regs_phys_base = res->start;
784
+
785
+
ospi->clk = devm_clk_get(dev, NULL);
786
+
if (IS_ERR(ospi->clk))
787
+
return dev_err_probe(dev, PTR_ERR(ospi->clk),
788
+
"Can't get clock\n");
789
+
790
+
ospi->clk_rate = clk_get_rate(ospi->clk);
791
+
if (!ospi->clk_rate) {
792
+
dev_err(dev, "Invalid clock rate\n");
793
+
return -EINVAL;
794
+
}
795
+
796
+
ospi->irq = platform_get_irq(pdev, 0);
797
+
if (ospi->irq < 0)
798
+
return ospi->irq;
799
+
800
+
ret = devm_request_irq(dev, ospi->irq, stm32_ospi_irq, 0,
801
+
dev_name(dev), ospi);
802
+
if (ret) {
803
+
dev_err(dev, "Failed to request irq\n");
804
+
return ret;
805
+
}
806
+
807
+
ospi->rstc = devm_reset_control_array_get_optional_exclusive(dev);
808
+
if (IS_ERR(ospi->rstc))
809
+
return dev_err_probe(dev, PTR_ERR(ospi->rstc),
810
+
"Can't get reset\n");
811
+
812
+
ospi->dma_chrx = dma_request_chan(dev, "rx");
813
+
if (IS_ERR(ospi->dma_chrx)) {
814
+
ret = PTR_ERR(ospi->dma_chrx);
815
+
ospi->dma_chrx = NULL;
816
+
if (ret == -EPROBE_DEFER)
817
+
goto err_dma;
818
+
}
819
+
820
+
ospi->dma_chtx = dma_request_chan(dev, "tx");
821
+
if (IS_ERR(ospi->dma_chtx)) {
822
+
ret = PTR_ERR(ospi->dma_chtx);
823
+
ospi->dma_chtx = NULL;
824
+
if (ret == -EPROBE_DEFER)
825
+
goto err_dma;
826
+
}
827
+
828
+
node = of_parse_phandle(dev->of_node, "memory-region", 0);
829
+
if (node)
830
+
rmem = of_reserved_mem_lookup(node);
831
+
of_node_put(node);
832
+
833
+
if (rmem) {
834
+
ospi->mm_size = rmem->size;
835
+
ospi->mm_base = devm_ioremap(dev, rmem->base, rmem->size);
836
+
if (!ospi->mm_base) {
837
+
dev_err(dev, "unable to map memory region: %pa+%pa\n",
838
+
&rmem->base, &rmem->size);
839
+
ret = -ENOMEM;
840
+
goto err_dma;
841
+
}
842
+
843
+
if (ospi->mm_size > STM32_OSPI_MAX_MMAP_SZ) {
844
+
dev_err(dev, "Memory map size outsize bounds\n");
845
+
ret = -EINVAL;
846
+
goto err_dma;
847
+
}
848
+
} else {
849
+
dev_info(dev, "No memory-map region found\n");
850
+
}
851
+
852
+
init_completion(&ospi->data_completion);
853
+
init_completion(&ospi->match_completion);
854
+
855
+
return 0;
856
+
857
+
err_dma:
858
+
dev_info(dev, "Can't get all resources (%d)\n", ret);
859
+
860
+
if (ospi->dma_chtx)
861
+
dma_release_channel(ospi->dma_chtx);
862
+
if (ospi->dma_chrx)
863
+
dma_release_channel(ospi->dma_chrx);
864
+
865
+
return ret;
866
+
};
867
+
868
+
static int stm32_ospi_probe(struct platform_device *pdev)
869
+
{
870
+
struct device *dev = &pdev->dev;
871
+
struct spi_controller *ctrl;
872
+
struct stm32_ospi *ospi;
873
+
struct dma_slave_config dma_cfg;
874
+
struct device_node *child;
875
+
int ret;
876
+
u8 spi_flash_count = 0;
877
+
878
+
/*
879
+
* Flash subnodes sanity check:
880
+
* 1 or 2 spi-nand/spi-nor flashes => supported
881
+
* All other flash node configuration => not supported
882
+
*/
883
+
for_each_available_child_of_node(dev->of_node, child) {
884
+
if (of_device_is_compatible(child, "jedec,spi-nor") ||
885
+
of_device_is_compatible(child, "spi-nand"))
886
+
spi_flash_count++;
887
+
}
888
+
889
+
if (spi_flash_count == 0 || spi_flash_count > 2) {
890
+
dev_err(dev, "Incorrect DT flash node\n");
891
+
return -ENODEV;
892
+
}
893
+
894
+
ctrl = devm_spi_alloc_host(dev, sizeof(*ospi));
895
+
if (!ctrl)
896
+
return -ENOMEM;
897
+
898
+
ospi = spi_controller_get_devdata(ctrl);
899
+
ospi->ctrl = ctrl;
900
+
901
+
ospi->dev = &pdev->dev;
902
+
platform_set_drvdata(pdev, ospi);
903
+
904
+
ret = stm32_ospi_get_resources(pdev);
905
+
if (ret)
906
+
return ret;
907
+
908
+
memset(&dma_cfg, 0, sizeof(dma_cfg));
909
+
dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
910
+
dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
911
+
dma_cfg.src_addr = ospi->regs_phys_base + OSPI_DR;
912
+
dma_cfg.dst_addr = ospi->regs_phys_base + OSPI_DR;
913
+
dma_cfg.src_maxburst = 4;
914
+
dma_cfg.dst_maxburst = 4;
915
+
stm32_ospi_dma_setup(ospi, &dma_cfg);
916
+
917
+
mutex_init(&ospi->lock);
918
+
919
+
ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
920
+
SPI_TX_DUAL | SPI_TX_QUAD |
921
+
SPI_TX_OCTAL | SPI_RX_OCTAL;
922
+
ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
923
+
ctrl->setup = stm32_ospi_setup;
924
+
ctrl->bus_num = -1;
925
+
ctrl->mem_ops = &stm32_ospi_mem_ops;
926
+
ctrl->use_gpio_descriptors = true;
927
+
ctrl->transfer_one_message = stm32_ospi_transfer_one_message;
928
+
ctrl->num_chipselect = STM32_OSPI_MAX_NORCHIP;
929
+
ctrl->dev.of_node = dev->of_node;
930
+
931
+
pm_runtime_enable(ospi->dev);
932
+
pm_runtime_set_autosuspend_delay(ospi->dev, STM32_AUTOSUSPEND_DELAY);
933
+
pm_runtime_use_autosuspend(ospi->dev);
934
+
935
+
ret = pm_runtime_resume_and_get(ospi->dev);
936
+
if (ret < 0)
937
+
goto err_pm_enable;
938
+
939
+
if (ospi->rstc) {
940
+
reset_control_assert(ospi->rstc);
941
+
udelay(2);
942
+
reset_control_deassert(ospi->rstc);
943
+
}
944
+
945
+
ret = spi_register_controller(ctrl);
946
+
if (ret) {
947
+
/* Disable ospi */
948
+
writel_relaxed(0, ospi->regs_base + OSPI_CR);
949
+
goto err_pm_resume;
950
+
}
951
+
952
+
pm_runtime_mark_last_busy(ospi->dev);
953
+
pm_runtime_put_autosuspend(ospi->dev);
954
+
955
+
return 0;
956
+
957
+
err_pm_resume:
958
+
pm_runtime_put_sync_suspend(ospi->dev);
959
+
960
+
err_pm_enable:
961
+
pm_runtime_force_suspend(ospi->dev);
962
+
mutex_destroy(&ospi->lock);
963
+
964
+
return ret;
965
+
}
966
+
967
+
static void stm32_ospi_remove(struct platform_device *pdev)
968
+
{
969
+
struct stm32_ospi *ospi = platform_get_drvdata(pdev);
970
+
int ret;
971
+
972
+
ret = pm_runtime_resume_and_get(ospi->dev);
973
+
if (ret < 0)
974
+
return;
975
+
976
+
spi_unregister_controller(ospi->ctrl);
977
+
/* Disable ospi */
978
+
writel_relaxed(0, ospi->regs_base + OSPI_CR);
979
+
mutex_destroy(&ospi->lock);
980
+
981
+
if (ospi->dma_chtx)
982
+
dma_release_channel(ospi->dma_chtx);
983
+
if (ospi->dma_chrx)
984
+
dma_release_channel(ospi->dma_chrx);
985
+
986
+
pm_runtime_put_sync_suspend(ospi->dev);
987
+
pm_runtime_force_suspend(ospi->dev);
988
+
}
989
+
990
+
static int __maybe_unused stm32_ospi_suspend(struct device *dev)
991
+
{
992
+
struct stm32_ospi *ospi = dev_get_drvdata(dev);
993
+
994
+
pinctrl_pm_select_sleep_state(dev);
995
+
996
+
return pm_runtime_force_suspend(ospi->dev);
997
+
}
998
+
999
+
static int __maybe_unused stm32_ospi_resume(struct device *dev)
1000
+
{
1001
+
struct stm32_ospi *ospi = dev_get_drvdata(dev);
1002
+
void __iomem *regs_base = ospi->regs_base;
1003
+
int ret;
1004
+
1005
+
ret = pm_runtime_force_resume(ospi->dev);
1006
+
if (ret < 0)
1007
+
return ret;
1008
+
1009
+
pinctrl_pm_select_default_state(dev);
1010
+
1011
+
ret = pm_runtime_resume_and_get(ospi->dev);
1012
+
if (ret < 0)
1013
+
return ret;
1014
+
1015
+
writel_relaxed(ospi->cr_reg, regs_base + OSPI_CR);
1016
+
writel_relaxed(ospi->dcr_reg, regs_base + OSPI_DCR1);
1017
+
pm_runtime_mark_last_busy(ospi->dev);
1018
+
pm_runtime_put_autosuspend(ospi->dev);
1019
+
1020
+
return 0;
1021
+
}
1022
+
1023
+
static int __maybe_unused stm32_ospi_runtime_suspend(struct device *dev)
1024
+
{
1025
+
struct stm32_ospi *ospi = dev_get_drvdata(dev);
1026
+
1027
+
clk_disable_unprepare(ospi->clk);
1028
+
1029
+
return 0;
1030
+
}
1031
+
1032
+
static int __maybe_unused stm32_ospi_runtime_resume(struct device *dev)
1033
+
{
1034
+
struct stm32_ospi *ospi = dev_get_drvdata(dev);
1035
+
1036
+
return clk_prepare_enable(ospi->clk);
1037
+
}
1038
+
1039
+
static const struct dev_pm_ops stm32_ospi_pm_ops = {
1040
+
SET_SYSTEM_SLEEP_PM_OPS(stm32_ospi_suspend, stm32_ospi_resume)
1041
+
SET_RUNTIME_PM_OPS(stm32_ospi_runtime_suspend,
1042
+
stm32_ospi_runtime_resume, NULL)
1043
+
};
1044
+
1045
+
static const struct of_device_id stm32_ospi_of_match[] = {
1046
+
{ .compatible = "st,stm32mp25-ospi" },
1047
+
{},
1048
+
};
1049
+
MODULE_DEVICE_TABLE(of, stm32_ospi_of_match);
1050
+
1051
+
static struct platform_driver stm32_ospi_driver = {
1052
+
.probe = stm32_ospi_probe,
1053
+
.remove = stm32_ospi_remove,
1054
+
.driver = {
1055
+
.name = "stm32-ospi",
1056
+
.pm = &stm32_ospi_pm_ops,
1057
+
.of_match_table = stm32_ospi_of_match,
1058
+
},
1059
+
};
1060
+
module_platform_driver(stm32_ospi_driver);
1061
+
1062
+
MODULE_DESCRIPTION("STMicroelectronics STM32 OCTO SPI driver");
1063
+
MODULE_LICENSE("GPL");
-5
drivers/spi/spi-stm32-qspi.c
-5
drivers/spi/spi-stm32-qspi.c
···
362
362
u32 ccr, cr;
363
363
int timeout, err = 0, err_poll_status = 0;
364
364
365
-
dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
366
-
op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
367
-
op->dummy.buswidth, op->data.buswidth,
368
-
op->addr.val, op->data.nbytes);
369
-
370
365
cr = readl_relaxed(qspi->io_base + QSPI_CR);
371
366
cr &= ~CR_PRESC_MASK & ~CR_FSEL;
372
367
cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
-4
drivers/spi/spi-zynq-qspi.c
-4
drivers/spi/spi-zynq-qspi.c
···
540
540
int err = 0, i;
541
541
u8 *tmpbuf;
542
542
543
-
dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
544
-
op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
545
-
op->dummy.buswidth, op->data.buswidth);
546
-
547
543
zynq_qspi_chipselect(mem->spi, true);
548
544
zynq_qspi_config_op(xqspi, mem->spi, op);
549
545
+77
-96
drivers/spi/spi-zynqmp-gqspi.c
+77
-96
drivers/spi/spi-zynqmp-gqspi.c
···
82
82
#define GQSPI_GENFIFO_RX 0x00020000
83
83
#define GQSPI_GENFIFO_STRIPE 0x00040000
84
84
#define GQSPI_GENFIFO_POLL 0x00080000
85
-
#define GQSPI_GENFIFO_EXP_START 0x00000100
86
85
#define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
87
86
#define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
88
87
#define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
···
579
580
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
580
581
zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
581
582
}
583
+
584
+
dev_dbg(xqspi->dev, "config speed %u\n", req_speed_hz);
582
585
return 0;
583
586
}
584
587
···
671
670
static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
672
671
u32 genfifoentry)
673
672
{
674
-
u32 transfer_len = 0;
673
+
u32 transfer_len, tempcount, exponent;
674
+
u8 imm_data;
675
675
676
-
if (xqspi->txbuf) {
677
-
genfifoentry &= ~GQSPI_GENFIFO_RX;
678
-
genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
679
-
genfifoentry |= GQSPI_GENFIFO_TX;
680
-
transfer_len = xqspi->bytes_to_transfer;
681
-
} else if (xqspi->rxbuf) {
682
-
genfifoentry &= ~GQSPI_GENFIFO_TX;
683
-
genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
676
+
genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
677
+
if (xqspi->rxbuf) {
684
678
genfifoentry |= GQSPI_GENFIFO_RX;
685
679
if (xqspi->mode == GQSPI_MODE_DMA)
686
680
transfer_len = xqspi->dma_rx_bytes;
687
681
else
688
682
transfer_len = xqspi->bytes_to_receive;
689
683
} else {
690
-
/* Sending dummy circles here */
691
-
genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);
692
-
genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
693
684
transfer_len = xqspi->bytes_to_transfer;
694
685
}
686
+
687
+
if (xqspi->txbuf)
688
+
genfifoentry |= GQSPI_GENFIFO_TX;
689
+
695
690
genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
696
691
xqspi->genfifoentry = genfifoentry;
692
+
dev_dbg(xqspi->dev, "genfifo %05x transfer_len %u\n",
693
+
genfifoentry, transfer_len);
697
694
698
-
if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
699
-
genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
700
-
genfifoentry |= transfer_len;
701
-
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
702
-
} else {
703
-
int tempcount = transfer_len;
704
-
u32 exponent = 8; /* 2^8 = 256 */
705
-
u8 imm_data = tempcount & 0xFF;
706
-
707
-
tempcount &= ~(tempcount & 0xFF);
708
-
/* Immediate entry */
709
-
if (tempcount != 0) {
710
-
/* Exponent entries */
711
-
genfifoentry |= GQSPI_GENFIFO_EXP;
712
-
while (tempcount != 0) {
713
-
if (tempcount & GQSPI_GENFIFO_EXP_START) {
714
-
genfifoentry &=
715
-
~GQSPI_GENFIFO_IMM_DATA_MASK;
716
-
genfifoentry |= exponent;
717
-
zynqmp_gqspi_write(xqspi,
718
-
GQSPI_GEN_FIFO_OFST,
719
-
genfifoentry);
720
-
}
721
-
tempcount = tempcount >> 1;
722
-
exponent++;
723
-
}
724
-
}
725
-
if (imm_data != 0) {
726
-
genfifoentry &= ~GQSPI_GENFIFO_EXP;
727
-
genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
728
-
genfifoentry |= (u8)(imm_data & 0xFF);
695
+
/* Exponent entries */
696
+
imm_data = transfer_len;
697
+
tempcount = transfer_len >> 8;
698
+
exponent = 8;
699
+
genfifoentry |= GQSPI_GENFIFO_EXP;
700
+
while (tempcount) {
701
+
if (tempcount & 1)
729
702
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
730
-
genfifoentry);
731
-
}
703
+
genfifoentry | exponent);
704
+
tempcount >>= 1;
705
+
exponent++;
732
706
}
733
-
if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {
734
-
/* Dummy generic FIFO entry */
735
-
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
736
-
}
707
+
708
+
/* Immediate entry */
709
+
genfifoentry &= ~GQSPI_GENFIFO_EXP;
710
+
if (imm_data)
711
+
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
712
+
genfifoentry | imm_data);
713
+
714
+
/* Dummy generic FIFO entry */
715
+
if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf)
716
+
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0);
717
+
}
718
+
719
+
/**
720
+
* zynqmp_qspi_disable_dma() - Disable DMA mode
721
+
* @xqspi: GQSPI instance
722
+
*/
723
+
static void zynqmp_qspi_disable_dma(struct zynqmp_qspi *xqspi)
724
+
{
725
+
u32 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
726
+
727
+
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
728
+
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
729
+
xqspi->mode = GQSPI_MODE_IO;
730
+
}
731
+
732
+
/**
733
+
* zynqmp_qspi_enable_dma() - Enable DMA mode
734
+
* @xqspi: GQSPI instance
735
+
*/
736
+
static void zynqmp_qspi_enable_dma(struct zynqmp_qspi *xqspi)
737
+
{
738
+
u32 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
739
+
740
+
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
741
+
config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
742
+
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
743
+
xqspi->mode = GQSPI_MODE_DMA;
737
744
}
738
745
739
746
/**
···
753
744
*/
754
745
static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
755
746
{
756
-
u32 config_reg, genfifoentry;
747
+
u32 genfifoentry;
757
748
758
749
dma_unmap_single(xqspi->dev, xqspi->dma_addr,
759
750
xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
···
767
758
768
759
if (xqspi->bytes_to_receive > 0) {
769
760
/* Switch to IO mode,for remaining bytes to receive */
770
-
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
771
-
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
772
-
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
761
+
zynqmp_qspi_disable_dma(xqspi);
773
762
774
763
/* Initiate the transfer of remaining bytes */
775
764
genfifoentry = xqspi->genfifoentry;
···
806
799
static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
807
800
{
808
801
struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
809
-
irqreturn_t ret = IRQ_NONE;
810
802
u32 status, mask, dma_status = 0;
811
803
812
804
status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
···
820
814
dma_status);
821
815
}
822
816
823
-
if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
824
-
zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
825
-
ret = IRQ_HANDLED;
826
-
}
817
+
if (!mask && !dma_status)
818
+
return IRQ_NONE;
827
819
828
-
if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
820
+
if (mask & GQSPI_ISR_TXNOT_FULL_MASK)
821
+
zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
822
+
823
+
if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK)
829
824
zynqmp_process_dma_irq(xqspi);
830
-
ret = IRQ_HANDLED;
831
-
} else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
832
-
(mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
825
+
else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
826
+
(mask & GQSPI_IER_GENFIFOEMPTY_MASK))
833
827
zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
834
-
ret = IRQ_HANDLED;
835
-
}
836
828
837
829
if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
838
830
((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
839
831
zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
840
832
complete(&xqspi->data_completion);
841
-
ret = IRQ_HANDLED;
842
833
}
843
-
return ret;
834
+
return IRQ_HANDLED;
844
835
}
845
836
846
837
/**
···
848
845
*/
849
846
static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
850
847
{
851
-
u32 rx_bytes, rx_rem, config_reg;
848
+
u32 rx_bytes, rx_rem;
852
849
dma_addr_t addr;
853
850
u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
854
851
855
852
if (xqspi->bytes_to_receive < 8 ||
856
853
((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
857
854
/* Setting to IO mode */
858
-
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
859
-
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
860
-
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
861
-
xqspi->mode = GQSPI_MODE_IO;
855
+
zynqmp_qspi_disable_dma(xqspi);
862
856
xqspi->dma_rx_bytes = 0;
863
857
return 0;
864
858
}
···
878
878
zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
879
879
((u32)addr) & 0xfff);
880
880
881
-
/* Enabling the DMA mode */
882
-
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
883
-
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
884
-
config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
885
-
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
886
-
887
-
/* Switch to DMA mode */
888
-
xqspi->mode = GQSPI_MODE_DMA;
881
+
zynqmp_qspi_enable_dma(xqspi);
889
882
890
883
/* Write the number of bytes to transfer */
891
884
zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
···
898
905
static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
899
906
u32 genfifoentry)
900
907
{
901
-
u32 config_reg;
902
-
903
908
zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
904
909
zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
905
-
if (xqspi->mode == GQSPI_MODE_DMA) {
906
-
config_reg = zynqmp_gqspi_read(xqspi,
907
-
GQSPI_CONFIG_OFST);
908
-
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
909
-
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
910
-
config_reg);
911
-
xqspi->mode = GQSPI_MODE_IO;
912
-
}
910
+
if (xqspi->mode == GQSPI_MODE_DMA)
911
+
zynqmp_qspi_disable_dma(xqspi);
913
912
}
914
913
915
914
/**
···
1044
1059
static int zynqmp_qspi_exec_op(struct spi_mem *mem,
1045
1060
const struct spi_mem_op *op)
1046
1061
{
1047
-
struct zynqmp_qspi *xqspi = spi_controller_get_devdata
1048
-
(mem->spi->controller);
1062
+
struct zynqmp_qspi *xqspi =
1063
+
spi_controller_get_devdata(mem->spi->controller);
1049
1064
unsigned long timeout;
1050
1065
int err = 0, i;
1051
1066
u32 genfifoentry = 0;
1052
1067
u16 opcode = op->cmd.opcode;
1053
1068
u64 opaddr;
1054
-
1055
-
dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
1056
-
op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
1057
-
op->dummy.buswidth, op->data.buswidth);
1058
1069
1059
1070
mutex_lock(&xqspi->op_lock);
1060
1071
zynqmp_qspi_config_op(xqspi, op);
+58
-53
drivers/spi/spi.c
+58
-53
drivers/spi/spi.c
···
31
31
#include <linux/ptp_clock_kernel.h>
32
32
#include <linux/sched/rt.h>
33
33
#include <linux/slab.h>
34
+
#include <linux/spi/offload/types.h>
34
35
#include <linux/spi/spi.h>
35
36
#include <linux/spi/spi-mem.h>
36
37
#include <uapi/linux/sched/types.h>
···
43
42
44
43
#include "internals.h"
45
44
46
-
static DEFINE_IDR(spi_master_idr);
45
+
static DEFINE_IDR(spi_controller_idr);
47
46
48
47
static void spidev_release(struct device *dev)
49
48
{
···
306
305
.attrs = spi_controller_statistics_attrs,
307
306
};
308
307
309
-
static const struct attribute_group *spi_master_groups[] = {
308
+
static const struct attribute_group *spi_controller_groups[] = {
310
309
&spi_controller_statistics_group,
311
310
NULL,
312
311
};
···
1107
1106
spi_toggle_csgpiod(spi, idx, enable, activate);
1108
1107
}
1109
1108
}
1110
-
/* Some SPI masters need both GPIO CS & slave_select */
1109
+
/* Some SPI controllers need both GPIO CS & ->set_cs() */
1111
1110
if ((spi->controller->flags & SPI_CONTROLLER_GPIO_SS) &&
1112
1111
spi->controller->set_cs)
1113
1112
spi->controller->set_cs(spi, !enable);
···
1496
1495
} else {
1497
1496
u32 us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
1498
1497
1499
-
if (us <= 10)
1500
-
udelay(us);
1501
-
else
1502
-
usleep_range(us, us + DIV_ROUND_UP(us, 10));
1498
+
fsleep(us);
1503
1499
}
1504
1500
}
1505
1501
···
2532
2534
* @ctlr: Pointer to spi_controller device
2533
2535
*
2534
2536
* Registers an spi_device for each child node of controller node which
2535
-
* represents a valid SPI slave.
2537
+
* represents a valid SPI target device.
2536
2538
*/
2537
2539
static void of_register_spi_devices(struct spi_controller *ctlr)
2538
2540
{
···
2817
2819
if (!lookup.max_speed_hz &&
2818
2820
ACPI_SUCCESS(acpi_get_parent(adev->handle, &parent_handle)) &&
2819
2821
device_match_acpi_handle(lookup.ctlr->dev.parent, parent_handle)) {
2820
-
/* Apple does not use _CRS but nested devices for SPI slaves */
2822
+
/* Apple does not use _CRS but nested devices for SPI target devices */
2821
2823
acpi_spi_parse_apple_properties(adev, &lookup);
2822
2824
}
2823
2825
···
2909
2911
SPI_ACPI_ENUMERATE_MAX_DEPTH,
2910
2912
acpi_spi_add_device, NULL, ctlr, NULL);
2911
2913
if (ACPI_FAILURE(status))
2912
-
dev_warn(&ctlr->dev, "failed to enumerate SPI slaves\n");
2914
+
dev_warn(&ctlr->dev, "failed to enumerate SPI target devices\n");
2913
2915
}
2914
2916
#else
2915
2917
static inline void acpi_register_spi_devices(struct spi_controller *ctlr) {}
···
2923
2925
kfree(ctlr);
2924
2926
}
2925
2927
2926
-
static const struct class spi_master_class = {
2928
+
static const struct class spi_controller_class = {
2927
2929
.name = "spi_master",
2928
2930
.dev_release = spi_controller_release,
2929
-
.dev_groups = spi_master_groups,
2931
+
.dev_groups = spi_controller_groups,
2930
2932
};
2931
2933
2932
2934
#ifdef CONFIG_SPI_SLAVE
2933
2935
/**
2934
-
* spi_target_abort - abort the ongoing transfer request on an SPI slave
2935
-
* controller
2936
+
* spi_target_abort - abort the ongoing transfer request on an SPI target controller
2936
2937
* @spi: device used for the current transfer
2937
2938
*/
2938
2939
int spi_target_abort(struct spi_device *spi)
···
2976
2979
2977
2980
child = device_find_any_child(&ctlr->dev);
2978
2981
if (child) {
2979
-
/* Remove registered slave */
2982
+
/* Remove registered target device */
2980
2983
device_unregister(child);
2981
2984
put_device(child);
2982
2985
}
2983
2986
2984
2987
if (strcmp(name, "(null)")) {
2985
-
/* Register new slave */
2988
+
/* Register new target device */
2986
2989
spi = spi_alloc_device(ctlr);
2987
2990
if (!spi)
2988
2991
return -ENOMEM;
···
3001
3004
3002
3005
static DEVICE_ATTR_RW(slave);
3003
3006
3004
-
static struct attribute *spi_slave_attrs[] = {
3007
+
static struct attribute *spi_target_attrs[] = {
3005
3008
&dev_attr_slave.attr,
3006
3009
NULL,
3007
3010
};
3008
3011
3009
-
static const struct attribute_group spi_slave_group = {
3010
-
.attrs = spi_slave_attrs,
3012
+
static const struct attribute_group spi_target_group = {
3013
+
.attrs = spi_target_attrs,
3011
3014
};
3012
3015
3013
-
static const struct attribute_group *spi_slave_groups[] = {
3016
+
static const struct attribute_group *spi_target_groups[] = {
3014
3017
&spi_controller_statistics_group,
3015
-
&spi_slave_group,
3018
+
&spi_target_group,
3016
3019
NULL,
3017
3020
};
3018
3021
3019
-
static const struct class spi_slave_class = {
3022
+
static const struct class spi_target_class = {
3020
3023
.name = "spi_slave",
3021
3024
.dev_release = spi_controller_release,
3022
-
.dev_groups = spi_slave_groups,
3025
+
.dev_groups = spi_target_groups,
3023
3026
};
3024
3027
#else
3025
-
extern struct class spi_slave_class; /* dummy */
3028
+
extern struct class spi_target_class; /* dummy */
3026
3029
#endif
3027
3030
3028
3031
/**
3029
-
* __spi_alloc_controller - allocate an SPI master or slave controller
3032
+
* __spi_alloc_controller - allocate an SPI host or target controller
3030
3033
* @dev: the controller, possibly using the platform_bus
3031
3034
* @size: how much zeroed driver-private data to allocate; the pointer to this
3032
3035
* memory is in the driver_data field of the returned device, accessible
3033
3036
* with spi_controller_get_devdata(); the memory is cacheline aligned;
3034
3037
* drivers granting DMA access to portions of their private data need to
3035
3038
* round up @size using ALIGN(size, dma_get_cache_alignment()).
3036
-
* @slave: flag indicating whether to allocate an SPI master (false) or SPI
3037
-
* slave (true) controller
3039
+
* @target: flag indicating whether to allocate an SPI host (false) or SPI target (true)
3040
+
* controller
3038
3041
* Context: can sleep
3039
3042
*
3040
3043
* This call is used only by SPI controller drivers, which are the
···
3051
3054
* Return: the SPI controller structure on success, else NULL.
3052
3055
*/
3053
3056
struct spi_controller *__spi_alloc_controller(struct device *dev,
3054
-
unsigned int size, bool slave)
3057
+
unsigned int size, bool target)
3055
3058
{
3056
3059
struct spi_controller *ctlr;
3057
3060
size_t ctlr_size = ALIGN(sizeof(*ctlr), dma_get_cache_alignment());
···
3072
3075
mutex_init(&ctlr->add_lock);
3073
3076
ctlr->bus_num = -1;
3074
3077
ctlr->num_chipselect = 1;
3075
-
ctlr->slave = slave;
3076
-
if (IS_ENABLED(CONFIG_SPI_SLAVE) && slave)
3077
-
ctlr->dev.class = &spi_slave_class;
3078
+
ctlr->target = target;
3079
+
if (IS_ENABLED(CONFIG_SPI_SLAVE) && target)
3080
+
ctlr->dev.class = &spi_target_class;
3078
3081
else
3079
-
ctlr->dev.class = &spi_master_class;
3082
+
ctlr->dev.class = &spi_controller_class;
3080
3083
ctlr->dev.parent = dev;
3081
3084
pm_suspend_ignore_children(&ctlr->dev, true);
3082
3085
spi_controller_set_devdata(ctlr, (void *)ctlr + ctlr_size);
···
3094
3097
* __devm_spi_alloc_controller - resource-managed __spi_alloc_controller()
3095
3098
* @dev: physical device of SPI controller
3096
3099
* @size: how much zeroed driver-private data to allocate
3097
-
* @slave: whether to allocate an SPI master (false) or SPI slave (true)
3100
+
* @target: whether to allocate an SPI host (false) or SPI target (true) controller
3098
3101
* Context: can sleep
3099
3102
*
3100
3103
* Allocate an SPI controller and automatically release a reference on it
···
3107
3110
*/
3108
3111
struct spi_controller *__devm_spi_alloc_controller(struct device *dev,
3109
3112
unsigned int size,
3110
-
bool slave)
3113
+
bool target)
3111
3114
{
3112
3115
struct spi_controller **ptr, *ctlr;
3113
3116
···
3116
3119
if (!ptr)
3117
3120
return NULL;
3118
3121
3119
-
ctlr = __spi_alloc_controller(dev, size, slave);
3122
+
ctlr = __spi_alloc_controller(dev, size, target);
3120
3123
if (ctlr) {
3121
3124
ctlr->devm_allocated = true;
3122
3125
*ptr = ctlr;
···
3130
3133
EXPORT_SYMBOL_GPL(__devm_spi_alloc_controller);
3131
3134
3132
3135
/**
3133
-
* spi_get_gpio_descs() - grab chip select GPIOs for the master
3134
-
* @ctlr: The SPI master to grab GPIO descriptors for
3136
+
* spi_get_gpio_descs() - grab chip select GPIOs for the controller
3137
+
* @ctlr: The SPI controller to grab GPIO descriptors for
3135
3138
*/
3136
3139
static int spi_get_gpio_descs(struct spi_controller *ctlr)
3137
3140
{
···
3229
3232
int id;
3230
3233
3231
3234
mutex_lock(&board_lock);
3232
-
id = idr_alloc(&spi_master_idr, ctlr, start, end, GFP_KERNEL);
3235
+
id = idr_alloc(&spi_controller_idr, ctlr, start, end, GFP_KERNEL);
3233
3236
mutex_unlock(&board_lock);
3234
3237
if (WARN(id < 0, "couldn't get idr"))
3235
3238
return id == -ENOSPC ? -EBUSY : id;
···
3378
3381
spi_destroy_queue(ctlr);
3379
3382
free_bus_id:
3380
3383
mutex_lock(&board_lock);
3381
-
idr_remove(&spi_master_idr, ctlr->bus_num);
3384
+
idr_remove(&spi_controller_idr, ctlr->bus_num);
3382
3385
mutex_unlock(&board_lock);
3383
3386
return status;
3384
3387
}
···
3390
3393
}
3391
3394
3392
3395
/**
3393
-
* devm_spi_register_controller - register managed SPI host or target
3394
-
* controller
3396
+
* devm_spi_register_controller - register managed SPI host or target controller
3395
3397
* @dev: device managing SPI controller
3396
3398
* @ctlr: initialized controller, originally from spi_alloc_host() or
3397
3399
* spi_alloc_target()
···
3430
3434
}
3431
3435
3432
3436
/**
3433
-
* spi_unregister_controller - unregister SPI master or slave controller
3437
+
* spi_unregister_controller - unregister SPI host or target controller
3434
3438
* @ctlr: the controller being unregistered
3435
3439
* Context: can sleep
3436
3440
*
···
3454
3458
3455
3459
/* First make sure that this controller was ever added */
3456
3460
mutex_lock(&board_lock);
3457
-
found = idr_find(&spi_master_idr, id);
3461
+
found = idr_find(&spi_controller_idr, id);
3458
3462
mutex_unlock(&board_lock);
3459
3463
if (ctlr->queued) {
3460
3464
if (spi_destroy_queue(ctlr))
···
3469
3473
/* Free bus id */
3470
3474
mutex_lock(&board_lock);
3471
3475
if (found == ctlr)
3472
-
idr_remove(&spi_master_idr, id);
3476
+
idr_remove(&spi_controller_idr, id);
3473
3477
mutex_unlock(&board_lock);
3474
3478
3475
3479
if (IS_ENABLED(CONFIG_SPI_DYNAMIC))
···
4158
4162
4159
4163
if (_spi_xfer_word_delay_update(xfer, spi))
4160
4164
return -EINVAL;
4165
+
4166
+
/* Make sure controller supports required offload features. */
4167
+
if (xfer->offload_flags) {
4168
+
if (!message->offload)
4169
+
return -EINVAL;
4170
+
4171
+
if (xfer->offload_flags & ~message->offload->xfer_flags)
4172
+
return -EINVAL;
4173
+
}
4161
4174
}
4162
4175
4163
4176
message->status = -EINPROGRESS;
···
4622
4617
4623
4618
/**
4624
4619
* spi_bus_lock - obtain a lock for exclusive SPI bus usage
4625
-
* @ctlr: SPI bus master that should be locked for exclusive bus access
4620
+
* @ctlr: SPI bus controller that should be locked for exclusive bus access
4626
4621
* Context: can sleep
4627
4622
*
4628
4623
* This call may only be used from a context that may sleep. The sleep
···
4653
4648
4654
4649
/**
4655
4650
* spi_bus_unlock - release the lock for exclusive SPI bus usage
4656
-
* @ctlr: SPI bus master that was locked for exclusive bus access
4651
+
* @ctlr: SPI bus controller that was locked for exclusive bus access
4657
4652
* Context: can sleep
4658
4653
*
4659
4654
* This call may only be used from a context that may sleep. The sleep
···
4770
4765
{
4771
4766
struct device *dev;
4772
4767
4773
-
dev = class_find_device_by_of_node(&spi_master_class, node);
4768
+
dev = class_find_device_by_of_node(&spi_controller_class, node);
4774
4769
if (!dev && IS_ENABLED(CONFIG_SPI_SLAVE))
4775
-
dev = class_find_device_by_of_node(&spi_slave_class, node);
4770
+
dev = class_find_device_by_of_node(&spi_target_class, node);
4776
4771
if (!dev)
4777
4772
return NULL;
4778
4773
···
4852
4847
{
4853
4848
struct device *dev;
4854
4849
4855
-
dev = class_find_device(&spi_master_class, NULL, adev,
4850
+
dev = class_find_device(&spi_controller_class, NULL, adev,
4856
4851
spi_acpi_controller_match);
4857
4852
if (!dev && IS_ENABLED(CONFIG_SPI_SLAVE))
4858
-
dev = class_find_device(&spi_slave_class, NULL, adev,
4853
+
dev = class_find_device(&spi_target_class, NULL, adev,
4859
4854
spi_acpi_controller_match);
4860
4855
if (!dev)
4861
4856
return NULL;
···
4925
4920
if (status < 0)
4926
4921
goto err1;
4927
4922
4928
-
status = class_register(&spi_master_class);
4923
+
status = class_register(&spi_controller_class);
4929
4924
if (status < 0)
4930
4925
goto err2;
4931
4926
4932
4927
if (IS_ENABLED(CONFIG_SPI_SLAVE)) {
4933
-
status = class_register(&spi_slave_class);
4928
+
status = class_register(&spi_target_class);
4934
4929
if (status < 0)
4935
4930
goto err3;
4936
4931
}
···
4943
4938
return 0;
4944
4939
4945
4940
err3:
4946
-
class_unregister(&spi_master_class);
4941
+
class_unregister(&spi_controller_class);
4947
4942
err2:
4948
4943
bus_unregister(&spi_bus_type);
4949
4944
err1:
+2
drivers/spi/spidev.c
+2
drivers/spi/spidev.c
···
706
706
{ .name = /* cisco */ "spi-petra" },
707
707
{ .name = /* dh */ "dhcom-board" },
708
708
{ .name = /* elgin */ "jg10309-01" },
709
+
{ .name = /* gocontroll */ "moduline-module-slot"},
709
710
{ .name = /* lineartechnology */ "ltc2488" },
710
711
{ .name = /* lwn */ "bk4" },
711
712
{ .name = /* lwn */ "bk4-spi" },
···
738
737
{ .compatible = "cisco,spi-petra", .data = &spidev_of_check },
739
738
{ .compatible = "dh,dhcom-board", .data = &spidev_of_check },
740
739
{ .compatible = "elgin,jg10309-01", .data = &spidev_of_check },
740
+
{ .compatible = "gocontroll,moduline-module-slot", .data = &spidev_of_check},
741
741
{ .compatible = "lineartechnology,ltc2488", .data = &spidev_of_check },
742
742
{ .compatible = "lwn,bk4", .data = &spidev_of_check },
743
743
{ .compatible = "lwn,bk4-spi", .data = &spidev_of_check },
+7
include/linux/mtd/nand-qpic-common.h
+7
include/linux/mtd/nand-qpic-common.h
···
325
325
__le32 read_location_last1;
326
326
__le32 read_location_last2;
327
327
__le32 read_location_last3;
328
+
__le32 spi_cfg;
329
+
__le32 num_addr_cycle;
330
+
__le32 busy_wait_cnt;
331
+
__le32 flash_feature;
328
332
329
333
__le32 erased_cw_detect_cfg_clr;
330
334
__le32 erased_cw_detect_cfg_set;
···
343
339
*
344
340
* @core_clk: controller clock
345
341
* @aon_clk: another controller clock
342
+
* @iomacro_clk: io macro clock
346
343
*
347
344
* @regs: a contiguous chunk of memory for DMA register
348
345
* writes. contains the register values to be
···
353
348
* initialized via DT match data
354
349
*
355
350
* @controller: base controller structure
351
+
* @qspi: qpic spi structure
356
352
* @host_list: list containing all the chips attached to the
357
353
* controller
358
354
*
···
398
392
const struct qcom_nandc_props *props;
399
393
400
394
struct nand_controller *controller;
395
+
struct qpic_spi_nand *qspi;
401
396
struct list_head host_list;
402
397
403
398
union {
+39
include/linux/spi/offload/consumer.h
+39
include/linux/spi/offload/consumer.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (C) 2024 Analog Devices Inc.
4
+
* Copyright (C) 2024 BayLibre, SAS
5
+
*/
6
+
7
+
#ifndef __LINUX_SPI_OFFLOAD_CONSUMER_H
8
+
#define __LINUX_SPI_OFFLOAD_CONSUMER_H
9
+
10
+
#include <linux/module.h>
11
+
#include <linux/spi/offload/types.h>
12
+
#include <linux/types.h>
13
+
14
+
MODULE_IMPORT_NS("SPI_OFFLOAD");
15
+
16
+
struct device;
17
+
struct spi_device;
18
+
19
+
struct spi_offload *devm_spi_offload_get(struct device *dev, struct spi_device *spi,
20
+
const struct spi_offload_config *config);
21
+
22
+
struct spi_offload_trigger
23
+
*devm_spi_offload_trigger_get(struct device *dev,
24
+
struct spi_offload *offload,
25
+
enum spi_offload_trigger_type type);
26
+
int spi_offload_trigger_validate(struct spi_offload_trigger *trigger,
27
+
struct spi_offload_trigger_config *config);
28
+
int spi_offload_trigger_enable(struct spi_offload *offload,
29
+
struct spi_offload_trigger *trigger,
30
+
struct spi_offload_trigger_config *config);
31
+
void spi_offload_trigger_disable(struct spi_offload *offload,
32
+
struct spi_offload_trigger *trigger);
33
+
34
+
struct dma_chan *devm_spi_offload_tx_stream_request_dma_chan(struct device *dev,
35
+
struct spi_offload *offload);
36
+
struct dma_chan *devm_spi_offload_rx_stream_request_dma_chan(struct device *dev,
37
+
struct spi_offload *offload);
38
+
39
+
#endif /* __LINUX_SPI_OFFLOAD_CONSUMER_H */
+47
include/linux/spi/offload/provider.h
+47
include/linux/spi/offload/provider.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (C) 2024 Analog Devices Inc.
4
+
* Copyright (C) 2024 BayLibre, SAS
5
+
*/
6
+
7
+
#ifndef __LINUX_SPI_OFFLOAD_PROVIDER_H
8
+
#define __LINUX_SPI_OFFLOAD_PROVIDER_H
9
+
10
+
#include <linux/module.h>
11
+
#include <linux/spi/offload/types.h>
12
+
#include <linux/types.h>
13
+
14
+
MODULE_IMPORT_NS("SPI_OFFLOAD");
15
+
16
+
struct device;
17
+
struct spi_offload_trigger;
18
+
19
+
struct spi_offload *devm_spi_offload_alloc(struct device *dev, size_t priv_size);
20
+
21
+
struct spi_offload_trigger_ops {
22
+
bool (*match)(struct spi_offload_trigger *trigger,
23
+
enum spi_offload_trigger_type type, u64 *args, u32 nargs);
24
+
int (*request)(struct spi_offload_trigger *trigger,
25
+
enum spi_offload_trigger_type type, u64 *args, u32 nargs);
26
+
void (*release)(struct spi_offload_trigger *trigger);
27
+
int (*validate)(struct spi_offload_trigger *trigger,
28
+
struct spi_offload_trigger_config *config);
29
+
int (*enable)(struct spi_offload_trigger *trigger,
30
+
struct spi_offload_trigger_config *config);
31
+
void (*disable)(struct spi_offload_trigger *trigger);
32
+
};
33
+
34
+
struct spi_offload_trigger_info {
35
+
/** @fwnode: Provider fwnode, used to match to consumer. */
36
+
struct fwnode_handle *fwnode;
37
+
/** @ops: Provider-specific callbacks. */
38
+
const struct spi_offload_trigger_ops *ops;
39
+
/** Provider-specific state to be used in callbacks. */
40
+
void *priv;
41
+
};
42
+
43
+
int devm_spi_offload_trigger_register(struct device *dev,
44
+
struct spi_offload_trigger_info *info);
45
+
void *spi_offload_trigger_get_priv(struct spi_offload_trigger *trigger);
46
+
47
+
#endif /* __LINUX_SPI_OFFLOAD_PROVIDER_H */
+100
include/linux/spi/offload/types.h
+100
include/linux/spi/offload/types.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (C) 2024 Analog Devices Inc.
4
+
* Copyright (C) 2024 BayLibre, SAS
5
+
*/
6
+
7
+
#ifndef __LINUX_SPI_OFFLOAD_TYPES_H
8
+
#define __LINUX_SPI_OFFLOAD_TYPES_H
9
+
10
+
#include <linux/bits.h>
11
+
#include <linux/types.h>
12
+
13
+
struct device;
14
+
15
+
/* This is write xfer but TX uses external data stream rather than tx_buf. */
16
+
#define SPI_OFFLOAD_XFER_TX_STREAM BIT(0)
17
+
/* This is read xfer but RX uses external data stream rather than rx_buf. */
18
+
#define SPI_OFFLOAD_XFER_RX_STREAM BIT(1)
19
+
20
+
/* Offload can be triggered by external hardware event. */
21
+
#define SPI_OFFLOAD_CAP_TRIGGER BIT(0)
22
+
/* Offload can record and then play back TX data when triggered. */
23
+
#define SPI_OFFLOAD_CAP_TX_STATIC_DATA BIT(1)
24
+
/* Offload can get TX data from an external stream source. */
25
+
#define SPI_OFFLOAD_CAP_TX_STREAM_DMA BIT(2)
26
+
/* Offload can send RX data to an external stream sink. */
27
+
#define SPI_OFFLOAD_CAP_RX_STREAM_DMA BIT(3)
28
+
29
+
/**
30
+
* struct spi_offload_config - offload configuration
31
+
*
32
+
* This is used to request an offload with specific configuration.
33
+
*/
34
+
struct spi_offload_config {
35
+
/** @capability_flags: required capabilities. See %SPI_OFFLOAD_CAP_* */
36
+
u32 capability_flags;
37
+
};
38
+
39
+
/**
40
+
* struct spi_offload - offload instance
41
+
*/
42
+
struct spi_offload {
43
+
/** @provider_dev: for get/put reference counting */
44
+
struct device *provider_dev;
45
+
/** @priv: provider driver private data */
46
+
void *priv;
47
+
/** @ops: callbacks for offload support */
48
+
const struct spi_offload_ops *ops;
49
+
/** @xfer_flags: %SPI_OFFLOAD_XFER_* flags supported by provider */
50
+
u32 xfer_flags;
51
+
};
52
+
53
+
enum spi_offload_trigger_type {
54
+
/* Indication from SPI peripheral that data is read to read. */
55
+
SPI_OFFLOAD_TRIGGER_DATA_READY,
56
+
/* Trigger comes from a periodic source such as a clock. */
57
+
SPI_OFFLOAD_TRIGGER_PERIODIC,
58
+
};
59
+
60
+
struct spi_offload_trigger_periodic {
61
+
u64 frequency_hz;
62
+
};
63
+
64
+
struct spi_offload_trigger_config {
65
+
/** @type: type discriminator for union */
66
+
enum spi_offload_trigger_type type;
67
+
union {
68
+
struct spi_offload_trigger_periodic periodic;
69
+
};
70
+
};
71
+
72
+
/**
73
+
* struct spi_offload_ops - callbacks implemented by offload providers
74
+
*/
75
+
struct spi_offload_ops {
76
+
/**
77
+
* @trigger_enable: Optional callback to enable the trigger for the
78
+
* given offload instance.
79
+
*/
80
+
int (*trigger_enable)(struct spi_offload *offload);
81
+
/**
82
+
* @trigger_disable: Optional callback to disable the trigger for the
83
+
* given offload instance.
84
+
*/
85
+
void (*trigger_disable)(struct spi_offload *offload);
86
+
/**
87
+
* @tx_stream_request_dma_chan: Optional callback for controllers that
88
+
* have an offload where the TX data stream is connected directly to a
89
+
* DMA channel.
90
+
*/
91
+
struct dma_chan *(*tx_stream_request_dma_chan)(struct spi_offload *offload);
92
+
/**
93
+
* @rx_stream_request_dma_chan: Optional callback for controllers that
94
+
* have an offload where the RX data stream is connected directly to a
95
+
* DMA channel.
96
+
*/
97
+
struct dma_chan *(*rx_stream_request_dma_chan)(struct spi_offload *offload);
98
+
};
99
+
100
+
#endif /* __LINUX_SPI_OFFLOAD_TYPES_H */
+39
-17
include/linux/spi/spi.h
+39
-17
include/linux/spi/spi.h
···
31
31
struct spi_controller_mem_ops;
32
32
struct spi_controller_mem_caps;
33
33
struct spi_message;
34
+
struct spi_offload;
35
+
struct spi_offload_config;
34
36
35
37
/*
36
-
* INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
38
+
* INTERFACES between SPI controller-side drivers and SPI target protocol handlers,
37
39
* and SPI infrastructure.
38
40
*/
39
41
extern const struct bus_type spi_bus_type;
···
130
128
struct spi_transfer *xfer);
131
129
132
130
/**
133
-
* struct spi_device - Controller side proxy for an SPI slave device
131
+
* struct spi_device - Controller side proxy for an SPI target device
134
132
* @dev: Driver model representation of the device.
135
133
* @controller: SPI controller used with the device.
136
134
* @max_speed_hz: Maximum clock rate to be used with this chip
···
174
172
* @pcpu_statistics: statistics for the spi_device
175
173
* @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array
176
174
*
177
-
* A @spi_device is used to interchange data between an SPI slave
175
+
* A @spi_device is used to interchange data between an SPI target device
178
176
* (usually a discrete chip) and CPU memory.
179
177
*
180
178
* In @dev, the platform_data is used to hold information about this
···
388
386
spi_unregister_driver)
389
387
390
388
/**
391
-
* struct spi_controller - interface to SPI master or slave controller
389
+
* struct spi_controller - interface to SPI host or target controller
392
390
* @dev: device interface to this driver
393
391
* @list: link with the global spi_controller list
394
392
* @bus_num: board-specific (and often SOC-specific) identifier for a
395
393
* given SPI controller.
396
394
* @num_chipselect: chipselects are used to distinguish individual
397
-
* SPI slaves, and are numbered from zero to num_chipselects.
398
-
* each slave has a chipselect signal, but it's common that not
399
-
* every chipselect is connected to a slave.
395
+
* SPI targets, and are numbered from zero to num_chipselects.
396
+
* each target has a chipselect signal, but it's common that not
397
+
* every chipselect is connected to a target.
400
398
* @dma_alignment: SPI controller constraint on DMA buffers alignment.
401
399
* @mode_bits: flags understood by this controller driver
402
400
* @buswidth_override_bits: flags to override for this controller driver
···
425
423
* must fail if an unrecognized or unsupported mode is requested.
426
424
* It's always safe to call this unless transfers are pending on
427
425
* the device whose settings are being modified.
428
-
* @set_cs_timing: optional hook for SPI devices to request SPI master
426
+
* @set_cs_timing: optional hook for SPI devices to request SPI
429
427
* controller for configuring specific CS setup time, hold time and inactive
430
-
* delay interms of clock counts
428
+
* delay in terms of clock counts
431
429
* @transfer: adds a message to the controller's transfer queue.
432
430
* @cleanup: frees controller-specific state
433
431
* @can_dma: determine whether this controller supports DMA
···
498
496
* @mem_ops: optimized/dedicated operations for interactions with SPI memory.
499
497
* This field is optional and should only be implemented if the
500
498
* controller has native support for memory like operations.
499
+
* @get_offload: callback for controllers with offload support to get matching
500
+
* offload instance. Implementations should return -ENODEV if no match is
501
+
* found.
502
+
* @put_offload: release the offload instance acquired by @get_offload.
501
503
* @mem_caps: controller capabilities for the handling of memory operations.
502
504
* @unprepare_message: undo any work done by prepare_message().
503
505
* @target_abort: abort the ongoing transfer request on an SPI target controller
···
547
541
*
548
542
* The driver for an SPI controller manages access to those devices through
549
543
* a queue of spi_message transactions, copying data between CPU memory and
550
-
* an SPI slave device. For each such message it queues, it calls the
544
+
* an SPI target device. For each such message it queues, it calls the
551
545
* message's completion function when the transaction completes.
552
546
*/
553
547
struct spi_controller {
···
597
591
#define SPI_CONTROLLER_NO_TX BIT(2) /* Can't do buffer write */
598
592
#define SPI_CONTROLLER_MUST_RX BIT(3) /* Requires rx */
599
593
#define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */
600
-
#define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must select slave */
594
+
#define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must select target device */
601
595
#define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently suspended */
602
596
/*
603
597
* The spi-controller has multi chip select capability and can
···
664
658
* + To a given spi_device, message queueing is pure FIFO
665
659
*
666
660
* + The controller's main job is to process its message queue,
667
-
* selecting a chip (for masters), then transferring data
661
+
* selecting a chip (for controllers), then transferring data
668
662
* + If there are multiple spi_device children, the i/o queue
669
663
* arbitration algorithm is unspecified (round robin, FIFO,
670
664
* priority, reservations, preemption, etc)
···
745
739
/* Optimized handlers for SPI memory-like operations. */
746
740
const struct spi_controller_mem_ops *mem_ops;
747
741
const struct spi_controller_mem_caps *mem_caps;
742
+
743
+
struct spi_offload *(*get_offload)(struct spi_device *spi,
744
+
const struct spi_offload_config *config);
745
+
void (*put_offload)(struct spi_offload *offload);
748
746
749
747
/* GPIO chip select */
750
748
struct gpio_desc **cs_gpiods;
···
832
822
833
823
/* The SPI driver core manages memory for the spi_controller classdev */
834
824
extern struct spi_controller *__spi_alloc_controller(struct device *host,
835
-
unsigned int size, bool slave);
825
+
unsigned int size, bool target);
836
826
837
827
static inline struct spi_controller *spi_alloc_host(struct device *dev,
838
828
unsigned int size)
···
851
841
852
842
struct spi_controller *__devm_spi_alloc_controller(struct device *dev,
853
843
unsigned int size,
854
-
bool slave);
844
+
bool target);
855
845
856
846
static inline struct spi_controller *devm_spi_alloc_host(struct device *dev,
857
847
unsigned int size)
···
973
963
* @rx_sg_mapped: If true, the @rx_sg is mapped for DMA
974
964
* @tx_sg: Scatterlist for transmit, currently not for client use
975
965
* @rx_sg: Scatterlist for receive, currently not for client use
966
+
* @offload_flags: Flags that are only applicable to specialized SPI offload
967
+
* transfers. See %SPI_OFFLOAD_XFER_* in spi-offload.h.
976
968
* @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset
977
969
* within @tx_buf for which the SPI device is requesting that the time
978
970
* snapshot for this transfer begins. Upon completing the SPI transfer,
···
989
977
* purposefully (instead of setting to spi_transfer->len - 1) to denote
990
978
* that a transfer-level snapshot taken from within the driver may still
991
979
* be of higher quality.
992
-
* @ptp_sts: Pointer to a memory location held by the SPI slave device where a
980
+
* @ptp_sts: Pointer to a memory location held by the SPI target device where a
993
981
* PTP system timestamp structure may lie. If drivers use PIO or their
994
982
* hardware has some sort of assist for retrieving exact transfer timing,
995
983
* they can (and should) assert @ptp_sts_supported and populate this
996
984
* structure using the ptp_read_system_*ts helper functions.
997
-
* The timestamp must represent the time at which the SPI slave device has
985
+
* The timestamp must represent the time at which the SPI target device has
998
986
* processed the word, i.e. the "pre" timestamp should be taken before
999
987
* transmitting the "pre" word, and the "post" timestamp after receiving
1000
988
* transmit confirmation from the controller for the "post" word.
···
1095
1083
1096
1084
u32 effective_speed_hz;
1097
1085
1086
+
/* Use %SPI_OFFLOAD_XFER_* from spi-offload.h */
1087
+
unsigned int offload_flags;
1088
+
1098
1089
unsigned int ptp_sts_word_pre;
1099
1090
unsigned int ptp_sts_word_post;
1100
1091
···
1123
1108
* @state: for use by whichever driver currently owns the message
1124
1109
* @opt_state: for use by whichever driver currently owns the message
1125
1110
* @resources: for resource management when the SPI message is processed
1111
+
* @offload: (optional) offload instance used by this message
1126
1112
*
1127
1113
* A @spi_message is used to execute an atomic sequence of data transfers,
1128
1114
* each represented by a struct spi_transfer. The sequence is "atomic"
···
1183
1167
* __spi_optimize_message() and __spi_unoptimize_message().
1184
1168
*/
1185
1169
void *opt_state;
1170
+
1171
+
/*
1172
+
* Optional offload instance used by this message. This must be set
1173
+
* by the peripheral driver before calling spi_optimize_message().
1174
+
*/
1175
+
struct spi_offload *offload;
1186
1176
1187
1177
/* List of spi_res resources when the SPI message is processed */
1188
1178
struct list_head resources;
···
1622
1600
* bus_num is board specific and matches the bus_num of some
1623
1601
* spi_controller that will probably be registered later.
1624
1602
*
1625
-
* chip_select reflects how this chip is wired to that master;
1603
+
* chip_select reflects how this chip is wired to that controller;
1626
1604
* it's less than num_chipselect.
1627
1605
*/
1628
1606
u16 bus_num;