Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'loongarch-fixes-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
Pull LoongArch fixes from Huacai Chen:
"Remove redundant code in head.S, fix PMU counter allocation for mixed-
type event groups, fix a lot of dts build warnings, and fix kvm_device
memory leaks"
* tag 'loongarch-fixes-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson:
LoongArch: KVM: Fix kvm_device leak in kvm_pch_pic_destroy()
LoongArch: KVM: Fix kvm_device leak in kvm_eiointc_destroy()
LoongArch: KVM: Fix kvm_device leak in kvm_ipi_destroy()
LoongArch: dts: loongson-2k1000: Fix i2c-gpio node names
LoongArch: dts: loongson-2k2000: Add default interrupt controller address cells
LoongArch: dts: loongson-2k1000: Add default interrupt controller address cells
LoongArch: dts: loongson-2k0500: Add default interrupt controller address cells
LoongArch: dts: Describe PCI sideband IRQ through interrupt-extended
LoongArch: Fix PMU counter allocation for mixed-type event groups
LoongArch: Remove redundant code in head.S
+52
-49
+3
arch/loongarch/boot/dts/loongson-2k0500.dtsi
+3
arch/loongarch/boot/dts/loongson-2k0500.dtsi
···
131
131
reg-names = "main", "isr0";
132
132
133
133
interrupt-controller;
134
+
#address-cells = <0>;
134
135
#interrupt-cells = <2>;
135
136
interrupt-parent = <&cpuintc>;
136
137
interrupts = <2>;
···
150
149
reg-names = "main", "isr0";
151
150
152
151
interrupt-controller;
152
+
#address-cells = <0>;
153
153
#interrupt-cells = <2>;
154
154
interrupt-parent = <&cpuintc>;
155
155
interrupts = <4>;
···
166
164
compatible = "loongson,ls2k0500-eiointc";
167
165
reg = <0x0 0x1fe11600 0x0 0xea00>;
168
166
interrupt-controller;
167
+
#address-cells = <0>;
169
168
#interrupt-cells = <1>;
170
169
interrupt-parent = <&cpuintc>;
171
170
interrupts = <3>;
+13
-18
arch/loongarch/boot/dts/loongson-2k1000.dtsi
+13
-18
arch/loongarch/boot/dts/loongson-2k1000.dtsi
···
46
46
};
47
47
48
48
/* i2c of the dvi eeprom edid */
49
-
i2c-gpio-0 {
49
+
i2c-0 {
50
50
compatible = "i2c-gpio";
51
51
scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
52
52
sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
···
57
57
};
58
58
59
59
/* i2c of the eeprom edid */
60
-
i2c-gpio-1 {
60
+
i2c-1 {
61
61
compatible = "i2c-gpio";
62
62
scl-gpios = <&gpio0 33 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
63
63
sda-gpios = <&gpio0 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
···
114
114
<0x0 0x1fe01140 0x0 0x8>;
115
115
reg-names = "main", "isr0", "isr1";
116
116
interrupt-controller;
117
+
#address-cells = <0>;
117
118
#interrupt-cells = <2>;
118
119
interrupt-parent = <&cpuintc>;
119
120
interrupts = <2>;
···
132
131
<0x0 0x1fe01148 0x0 0x8>;
133
132
reg-names = "main", "isr0", "isr1";
134
133
interrupt-controller;
134
+
#address-cells = <0>;
135
135
#interrupt-cells = <2>;
136
136
interrupt-parent = <&cpuintc>;
137
137
interrupts = <3>;
···
439
437
440
438
gmac0: ethernet@3,0 {
441
439
reg = <0x1800 0x0 0x0 0x0 0x0>;
442
-
interrupt-parent = <&liointc0>;
443
-
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
444
-
<13 IRQ_TYPE_LEVEL_HIGH>;
440
+
interrupts-extended = <&liointc0 12 IRQ_TYPE_LEVEL_HIGH>,
441
+
<&liointc0 13 IRQ_TYPE_LEVEL_HIGH>;
445
442
interrupt-names = "macirq", "eth_lpi";
446
443
status = "disabled";
447
444
};
448
445
449
446
gmac1: ethernet@3,1 {
450
447
reg = <0x1900 0x0 0x0 0x0 0x0>;
451
-
interrupt-parent = <&liointc0>;
452
-
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
453
-
<15 IRQ_TYPE_LEVEL_HIGH>;
448
+
interrupts-extended = <&liointc0 14 IRQ_TYPE_LEVEL_HIGH>,
449
+
<&liointc0 15 IRQ_TYPE_LEVEL_HIGH>;
454
450
interrupt-names = "macirq", "eth_lpi";
455
451
status = "disabled";
456
452
};
457
453
458
454
ehci0: usb@4,1 {
459
455
reg = <0x2100 0x0 0x0 0x0 0x0>;
460
-
interrupt-parent = <&liointc1>;
461
-
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
456
+
interrupts-extended = <&liointc1 18 IRQ_TYPE_LEVEL_HIGH>;
462
457
status = "disabled";
463
458
};
464
459
465
460
ohci0: usb@4,2 {
466
461
reg = <0x2200 0x0 0x0 0x0 0x0>;
467
-
interrupt-parent = <&liointc1>;
468
-
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
462
+
interrupts-extended = <&liointc1 19 IRQ_TYPE_LEVEL_HIGH>;
469
463
status = "disabled";
470
464
};
471
465
472
466
display@6,0 {
473
467
reg = <0x3000 0x0 0x0 0x0 0x0>;
474
-
interrupt-parent = <&liointc0>;
475
-
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
468
+
interrupts-extended = <&liointc0 28 IRQ_TYPE_LEVEL_HIGH>;
476
469
status = "disabled";
477
470
};
478
471
479
472
hda@7,0 {
480
473
reg = <0x3800 0x0 0x0 0x0 0x0>;
481
-
interrupt-parent = <&liointc0>;
482
-
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
474
+
interrupts-extended = <&liointc0 4 IRQ_TYPE_LEVEL_HIGH>;
483
475
status = "disabled";
484
476
};
485
477
486
478
sata: sata@8,0 {
487
479
reg = <0x4000 0x0 0x0 0x0 0x0>;
488
-
interrupt-parent = <&liointc0>;
489
-
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
480
+
interrupts-extended = <&liointc0 19 IRQ_TYPE_LEVEL_HIGH>;
490
481
status = "disabled";
491
482
};
492
483
+15
-20
arch/loongarch/boot/dts/loongson-2k2000.dtsi
+15
-20
arch/loongarch/boot/dts/loongson-2k2000.dtsi
···
126
126
reg = <0x0 0x1fe01400 0x0 0x64>;
127
127
128
128
interrupt-controller;
129
+
#address-cells = <0>;
129
130
#interrupt-cells = <2>;
130
131
interrupt-parent = <&cpuintc>;
131
132
interrupts = <2>;
···
141
140
compatible = "loongson,ls2k2000-eiointc";
142
141
reg = <0x0 0x1fe01600 0x0 0xea00>;
143
142
interrupt-controller;
143
+
#address-cells = <0>;
144
144
#interrupt-cells = <1>;
145
145
interrupt-parent = <&cpuintc>;
146
146
interrupts = <3>;
···
151
149
compatible = "loongson,pch-pic-1.0";
152
150
reg = <0x0 0x10000000 0x0 0x400>;
153
151
interrupt-controller;
152
+
#address-cells = <0>;
154
153
#interrupt-cells = <2>;
155
154
loongson,pic-base-vec = <0>;
156
155
interrupt-parent = <&eiointc>;
···
294
291
295
292
gmac0: ethernet@3,0 {
296
293
reg = <0x1800 0x0 0x0 0x0 0x0>;
297
-
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
298
-
<13 IRQ_TYPE_LEVEL_HIGH>;
294
+
interrupts-extended = <&pic 12 IRQ_TYPE_LEVEL_HIGH>,
295
+
<&pic 13 IRQ_TYPE_LEVEL_HIGH>;
299
296
interrupt-names = "macirq", "eth_lpi";
300
-
interrupt-parent = <&pic>;
301
297
status = "disabled";
302
298
};
303
299
304
300
gmac1: ethernet@3,1 {
305
301
reg = <0x1900 0x0 0x0 0x0 0x0>;
306
-
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
307
-
<15 IRQ_TYPE_LEVEL_HIGH>;
302
+
interrupts-extended = <&pic 14 IRQ_TYPE_LEVEL_HIGH>,
303
+
<&pic 15 IRQ_TYPE_LEVEL_HIGH>;
308
304
interrupt-names = "macirq", "eth_lpi";
309
-
interrupt-parent = <&pic>;
310
305
status = "disabled";
311
306
};
312
307
313
308
gmac2: ethernet@3,2 {
314
309
reg = <0x1a00 0x0 0x0 0x0 0x0>;
315
-
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
316
-
<18 IRQ_TYPE_LEVEL_HIGH>;
310
+
interrupts-extended = <&pic 17 IRQ_TYPE_LEVEL_HIGH>,
311
+
<&pic 18 IRQ_TYPE_LEVEL_HIGH>;
317
312
interrupt-names = "macirq", "eth_lpi";
318
-
interrupt-parent = <&pic>;
319
313
status = "disabled";
320
314
};
321
315
322
316
xhci0: usb@4,0 {
323
317
reg = <0x2000 0x0 0x0 0x0 0x0>;
324
-
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
325
-
interrupt-parent = <&pic>;
318
+
interrupts-extended = <&pic 48 IRQ_TYPE_LEVEL_HIGH>;
326
319
status = "disabled";
327
320
};
328
321
329
322
xhci1: usb@19,0 {
330
323
reg = <0xc800 0x0 0x0 0x0 0x0>;
331
-
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
332
-
interrupt-parent = <&pic>;
324
+
interrupts-extended = <&pic 22 IRQ_TYPE_LEVEL_HIGH>;
333
325
status = "disabled";
334
326
};
335
327
336
328
display@6,1 {
337
329
reg = <0x3100 0x0 0x0 0x0 0x0>;
338
-
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
339
-
interrupt-parent = <&pic>;
330
+
interrupts-extended = <&pic 28 IRQ_TYPE_LEVEL_HIGH>;
340
331
status = "disabled";
341
332
};
342
333
343
334
i2s@7,0 {
344
335
reg = <0x3800 0x0 0x0 0x0 0x0>;
345
-
interrupts = <78 IRQ_TYPE_LEVEL_HIGH>,
346
-
<79 IRQ_TYPE_LEVEL_HIGH>;
336
+
interrupts-extended = <&pic 78 IRQ_TYPE_LEVEL_HIGH>,
337
+
<&pic 79 IRQ_TYPE_LEVEL_HIGH>;
347
338
interrupt-names = "tx", "rx";
348
-
interrupt-parent = <&pic>;
349
339
status = "disabled";
350
340
};
351
341
352
342
sata: sata@8,0 {
353
343
reg = <0x4000 0x0 0x0 0x0 0x0>;
354
-
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
355
-
interrupt-parent = <&pic>;
344
+
interrupts-extended = <&pic 16 IRQ_TYPE_LEVEL_HIGH>;
356
345
status = "disabled";
357
346
};
358
347
-8
arch/loongarch/kernel/head.S
-8
arch/loongarch/kernel/head.S
···
126
126
LONG_LI t1, CSR_STFILL
127
127
csrxchg t0, t1, LOONGARCH_CSR_IMPCTL1
128
128
#endif
129
-
/* Enable PG */
130
-
li.w t0, 0xb0 # PLV=0, IE=0, PG=1
131
-
csrwr t0, LOONGARCH_CSR_CRMD
132
-
li.w t0, 0x04 # PLV=0, PIE=1, PWE=0
133
-
csrwr t0, LOONGARCH_CSR_PRMD
134
-
li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
135
-
csrwr t0, LOONGARCH_CSR_EUEN
136
-
137
129
la.pcrel t0, cpuboot_data
138
130
ld.d sp, t0, CPU_BOOT_STACK
139
131
ld.d tp, t0, CPU_BOOT_TINFO
+18
-3
arch/loongarch/kernel/perf_event.c
+18
-3
arch/loongarch/kernel/perf_event.c
···
626
626
return pev;
627
627
}
628
628
629
+
static inline bool loongarch_pmu_event_requires_counter(const struct perf_event *event)
630
+
{
631
+
switch (event->attr.type) {
632
+
case PERF_TYPE_HARDWARE:
633
+
case PERF_TYPE_HW_CACHE:
634
+
case PERF_TYPE_RAW:
635
+
return true;
636
+
default:
637
+
return false;
638
+
}
639
+
}
640
+
629
641
static int validate_group(struct perf_event *event)
630
642
{
631
643
struct cpu_hw_events fake_cpuc;
···
645
633
646
634
memset(&fake_cpuc, 0, sizeof(fake_cpuc));
647
635
648
-
if (loongarch_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
636
+
if (loongarch_pmu_event_requires_counter(leader) &&
637
+
loongarch_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
649
638
return -EINVAL;
650
639
651
640
for_each_sibling_event(sibling, leader) {
652
-
if (loongarch_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
641
+
if (loongarch_pmu_event_requires_counter(sibling) &&
642
+
loongarch_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
653
643
return -EINVAL;
654
644
}
655
645
656
-
if (loongarch_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
646
+
if (loongarch_pmu_event_requires_counter(event) &&
647
+
loongarch_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
657
648
return -EINVAL;
658
649
659
650
return 0;
+1
arch/loongarch/kvm/intc/eiointc.c
+1
arch/loongarch/kvm/intc/eiointc.c
+1
arch/loongarch/kvm/intc/ipi.c
+1
arch/loongarch/kvm/intc/ipi.c