Merge tag 'pinctrl-v5.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

+13 -13

drivers/pinctrl/intel/pinctrl-cherryview.c

··· 147 147 * @pctldesc: Pin controller description 148 148 * @pctldev: Pointer to the pin controller device 149 149 * @chip: GPIO chip in this pin controller 150 + * @irqchip: IRQ chip in this pin controller 150 151 * @regs: MMIO registers 151 152 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO 152 153 * offset (in GPIO number space) ··· 163 162 struct pinctrl_desc pctldesc; 164 163 struct pinctrl_dev *pctldev; 165 164 struct gpio_chip chip; 165 + struct irq_chip irqchip; 166 166 void __iomem *regs; 167 167 unsigned intr_lines[16]; 168 168 const struct chv_community *community; ··· 1468 1466 return 0; 1469 1467 } 1470 1468 1471 - static struct irq_chip chv_gpio_irqchip = { 1472 - .name = "chv-gpio", 1473 - .irq_startup = chv_gpio_irq_startup, 1474 - .irq_ack = chv_gpio_irq_ack, 1475 - .irq_mask = chv_gpio_irq_mask, 1476 - .irq_unmask = chv_gpio_irq_unmask, 1477 - .irq_set_type = chv_gpio_irq_type, 1478 - .flags = IRQCHIP_SKIP_SET_WAKE, 1479 - }; 1480 - 1481 1469 static void chv_gpio_irq_handler(struct irq_desc *desc) 1482 1470 { 1483 1471 struct gpio_chip *gc = irq_desc_get_handler_data(desc); ··· 1551 1559 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1552 1560 1553 1561 if (intsel >= community->nirqs) 1554 - clear_bit(i, valid_mask); 1562 + clear_bit(desc->number, valid_mask); 1555 1563 } 1556 1564 } 1557 1565 ··· 1617 1625 } 1618 1626 } 1619 1627 1620 - ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, 1628 + pctrl->irqchip.name = "chv-gpio"; 1629 + pctrl->irqchip.irq_startup = chv_gpio_irq_startup; 1630 + pctrl->irqchip.irq_ack = chv_gpio_irq_ack; 1631 + pctrl->irqchip.irq_mask = chv_gpio_irq_mask; 1632 + pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask; 1633 + pctrl->irqchip.irq_set_type = chv_gpio_irq_type; 1634 + pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE; 1635 + 1636 + ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0, 1621 1637 handle_bad_irq, IRQ_TYPE_NONE); 1622 1638 if (ret) { 1623 1639 dev_err(pctrl->dev, "failed to add IRQ chip\n"); ··· 1642 1642 } 1643 1643 } 1644 1644 1645 - gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, 1645 + gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq, 1646 1646 chv_gpio_irq_handler); 1647 1647 return 0; 1648 1648 }

+20 -1

drivers/pinctrl/intel/pinctrl-intel.c

··· 52 52 #define PADCFG0_GPIROUTNMI BIT(17) 53 53 #define PADCFG0_PMODE_SHIFT 10 54 54 #define PADCFG0_PMODE_MASK GENMASK(13, 10) 55 + #define PADCFG0_PMODE_GPIO 0 55 56 #define PADCFG0_GPIORXDIS BIT(9) 56 57 #define PADCFG0_GPIOTXDIS BIT(8) 57 58 #define PADCFG0_GPIORXSTATE BIT(1) ··· 333 332 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 334 333 335 334 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 336 - if (!mode) 335 + if (mode == PADCFG0_PMODE_GPIO) 337 336 seq_puts(s, "GPIO "); 338 337 else 339 338 seq_printf(s, "mode %d ", mode); ··· 459 458 writel(value, padcfg0); 460 459 } 461 460 461 + static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) 462 + { 463 + return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 464 + } 465 + 462 466 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 463 467 { 464 468 u32 value; ··· 497 491 } 498 492 499 493 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 494 + 495 + /* 496 + * If pin is already configured in GPIO mode, we assume that 497 + * firmware provides correct settings. In such case we avoid 498 + * potential glitches on the pin. Otherwise, for the pin in 499 + * alternative mode, consumer has to supply respective flags. 500 + */ 501 + if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) { 502 + raw_spin_unlock_irqrestore(&pctrl->lock, flags); 503 + return 0; 504 + } 505 + 500 506 intel_gpio_set_gpio_mode(padcfg0); 507 + 501 508 /* Disable TX buffer and enable RX (this will be input) */ 502 509 __intel_gpio_set_direction(padcfg0, true); 503 510

-14

drivers/pinctrl/pinctrl-stmfx.c

··· 585 585 return stmfx_function_enable(pctl->stmfx, func); 586 586 } 587 587 588 - static int stmfx_pinctrl_gpio_init_valid_mask(struct gpio_chip *gc, 589 - unsigned long *valid_mask, 590 - unsigned int ngpios) 591 - { 592 - struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 593 - u32 n; 594 - 595 - for_each_clear_bit(n, &pctl->gpio_valid_mask, ngpios) 596 - clear_bit(n, valid_mask); 597 - 598 - return 0; 599 - } 600 - 601 588 static int stmfx_pinctrl_probe(struct platform_device *pdev) 602 589 { 603 590 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); ··· 647 660 pctl->gpio_chip.ngpio = pctl->pctl_desc.npins; 648 661 pctl->gpio_chip.can_sleep = true; 649 662 pctl->gpio_chip.of_node = np; 650 - pctl->gpio_chip.init_valid_mask = stmfx_pinctrl_gpio_init_valid_mask; 651 663 652 664 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); 653 665 if (ret) {

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