Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2020-05-01' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Regular scheduled fixes for graphics. Nothing to extreme bunch of
amdgpu fixes, i915 and qxl fixes, along with some misc ones.
All seems to be progressing normally.
core:
- EDID off by one DTD fix
- DP mst write return code fix
dma-buf:
- fix SET_NAME ioctl uapi
- doc fixes
amdgpu:
- Fix a green screen on resume issue
- PM fixes for SR-IOV SDMA fix for navi
- Renoir display fixes
- Cursor and pageflip stuttering fixes
- Misc additional display fixes
- (uapi) Add additional DCC tiling flags for navi1x
i915:
- Fix selftest refcnt leak (Xiyu)
- Fix gem vma lock (Chris)
- Fix gt's i915_request.timeline acquire by checking if cacheline is
valid (Chris)
- Fix IRQ postinistall fault masks (Matt)
qxl:
- use after gree fix
- fix lost kunmap
- release leak fix
virtio:
- context destruction fix"
* tag 'drm-fixes-2020-05-01' of git://anongit.freedesktop.org/drm/drm: (26 commits)
dma-buf: fix documentation build warnings
drm/qxl: qxl_release use after free
drm/qxl: lost qxl_bo_kunmap_atomic_page in qxl_image_init_helper()
drm/i915: Use proper fault mask in interrupt postinstall too
drm/amd/display: Use cursor locking to prevent flip delays
drm/amd/display: Update downspread percent to match spreadsheet for DCN2.1
drm/amd/display: Defer cursor update around VUPDATE for all ASIC
drm/amd/display: fix rn soc bb update
drm/amd/display: check if REFCLK_CNTL register is present
drm/amdgpu: bump version for invalidate L2 before SDMA IBs
drm/amdgpu: invalidate L2 before SDMA IBs (v2)
drm/amdgpu: add tiling flags from Mesa
drm/amd/powerplay: avoid using pm_en before it is initialized revised
Revert "drm/amd/powerplay: avoid using pm_en before it is initialized"
drm/qxl: qxl_release leak in qxl_hw_surface_alloc()
drm/qxl: qxl_release leak in qxl_draw_dirty_fb()
drm/virtio: only destroy created contexts
drm/dp_mst: Fix drm_dp_send_dpcd_write() return code
drm/i915/gt: Check cacheline is valid before acquiring
drm/i915/gem: Hold obj->vma.lock over for_each_ggtt_vma()
...
+291
-155
+4
-3
drivers/dma-buf/dma-buf.c
+4
-3
drivers/dma-buf/dma-buf.c
···
388
388
389
389
return ret;
390
390
391
-
case DMA_BUF_SET_NAME:
391
+
case DMA_BUF_SET_NAME_A:
392
+
case DMA_BUF_SET_NAME_B:
392
393
return dma_buf_set_name(dmabuf, (const char __user *)arg);
393
394
394
395
default:
···
656
655
* calls attach() of dma_buf_ops to allow device-specific attach functionality
657
656
* @dmabuf: [in] buffer to attach device to.
658
657
* @dev: [in] device to be attached.
659
-
* @importer_ops [in] importer operations for the attachment
660
-
* @importer_priv [in] importer private pointer for the attachment
658
+
* @importer_ops: [in] importer operations for the attachment
659
+
* @importer_priv: [in] importer private pointer for the attachment
661
660
*
662
661
* Returns struct dma_buf_attachment pointer for this attachment. Attachments
663
662
* must be cleaned up by calling dma_buf_detach().
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
···
85
85
* - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
86
86
* - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
87
87
* - 3.36.0 - Allow reading more status registers on si/cik
88
+
* - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
88
89
*/
89
90
#define KMS_DRIVER_MAJOR 3
90
-
#define KMS_DRIVER_MINOR 36
91
+
#define KMS_DRIVER_MINOR 37
91
92
#define KMS_DRIVER_PATCHLEVEL 0
92
93
93
94
int amdgpu_vram_limit = 0;
+13
-1
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+13
-1
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
···
382
382
unsigned vmid = AMDGPU_JOB_GET_VMID(job);
383
383
uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
384
384
385
+
/* Invalidate L2, because if we don't do it, we might get stale cache
386
+
* lines from previous IBs.
387
+
*/
388
+
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
389
+
amdgpu_ring_write(ring, 0);
390
+
amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
391
+
SDMA_GCR_GL2_WB |
392
+
SDMA_GCR_GLM_INV |
393
+
SDMA_GCR_GLM_WB) << 16);
394
+
amdgpu_ring_write(ring, 0xffffff80);
395
+
amdgpu_ring_write(ring, 0xffff);
396
+
385
397
/* An IB packet must end on a 8 DW boundary--the next dword
386
398
* must be on a 8-dword boundary. Our IB packet below is 6
387
399
* dwords long, thus add x number of NOPs, such that, in
···
1607
1595
SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1608
1596
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1609
1597
10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1610
-
.emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */
1598
+
.emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1611
1599
.emit_ib = sdma_v5_0_ring_emit_ib,
1612
1600
.emit_fence = sdma_v5_0_ring_emit_fence,
1613
1601
.emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
+29
-9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+29
-9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
3340
3340
const union dc_tiling_info *tiling_info,
3341
3341
const uint64_t info,
3342
3342
struct dc_plane_dcc_param *dcc,
3343
-
struct dc_plane_address *address)
3343
+
struct dc_plane_address *address,
3344
+
bool force_disable_dcc)
3344
3345
{
3345
3346
struct dc *dc = adev->dm.dc;
3346
3347
struct dc_dcc_surface_param input;
···
3352
3351
3353
3352
memset(&input, 0, sizeof(input));
3354
3353
memset(&output, 0, sizeof(output));
3354
+
3355
+
if (force_disable_dcc)
3356
+
return 0;
3355
3357
3356
3358
if (!offset)
3357
3359
return 0;
···
3405
3401
union dc_tiling_info *tiling_info,
3406
3402
struct plane_size *plane_size,
3407
3403
struct dc_plane_dcc_param *dcc,
3408
-
struct dc_plane_address *address)
3404
+
struct dc_plane_address *address,
3405
+
bool force_disable_dcc)
3409
3406
{
3410
3407
const struct drm_framebuffer *fb = &afb->base;
3411
3408
int ret;
···
3512
3507
3513
3508
ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
3514
3509
plane_size, tiling_info,
3515
-
tiling_flags, dcc, address);
3510
+
tiling_flags, dcc, address,
3511
+
force_disable_dcc);
3516
3512
if (ret)
3517
3513
return ret;
3518
3514
}
···
3605
3599
const struct drm_plane_state *plane_state,
3606
3600
const uint64_t tiling_flags,
3607
3601
struct dc_plane_info *plane_info,
3608
-
struct dc_plane_address *address)
3602
+
struct dc_plane_address *address,
3603
+
bool force_disable_dcc)
3609
3604
{
3610
3605
const struct drm_framebuffer *fb = plane_state->fb;
3611
3606
const struct amdgpu_framebuffer *afb =
···
3688
3681
plane_info->rotation, tiling_flags,
3689
3682
&plane_info->tiling_info,
3690
3683
&plane_info->plane_size,
3691
-
&plane_info->dcc, address);
3684
+
&plane_info->dcc, address,
3685
+
force_disable_dcc);
3692
3686
if (ret)
3693
3687
return ret;
3694
3688
···
3712
3704
struct dc_plane_info plane_info;
3713
3705
uint64_t tiling_flags;
3714
3706
int ret;
3707
+
bool force_disable_dcc = false;
3715
3708
3716
3709
ret = fill_dc_scaling_info(plane_state, &scaling_info);
3717
3710
if (ret)
···
3727
3718
if (ret)
3728
3719
return ret;
3729
3720
3721
+
force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
3730
3722
ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
3731
3723
&plane_info,
3732
-
&dc_plane_state->address);
3724
+
&dc_plane_state->address,
3725
+
force_disable_dcc);
3733
3726
if (ret)
3734
3727
return ret;
3735
3728
···
5353
5342
uint64_t tiling_flags;
5354
5343
uint32_t domain;
5355
5344
int r;
5345
+
bool force_disable_dcc = false;
5356
5346
5357
5347
dm_plane_state_old = to_dm_plane_state(plane->state);
5358
5348
dm_plane_state_new = to_dm_plane_state(new_state);
···
5412
5400
dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
5413
5401
struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
5414
5402
5403
+
force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5415
5404
fill_plane_buffer_attributes(
5416
5405
adev, afb, plane_state->format, plane_state->rotation,
5417
5406
tiling_flags, &plane_state->tiling_info,
5418
5407
&plane_state->plane_size, &plane_state->dcc,
5419
-
&plane_state->address);
5408
+
&plane_state->address,
5409
+
force_disable_dcc);
5420
5410
}
5421
5411
5422
5412
return 0;
···
6690
6676
fill_dc_plane_info_and_addr(
6691
6677
dm->adev, new_plane_state, tiling_flags,
6692
6678
&bundle->plane_infos[planes_count],
6693
-
&bundle->flip_addrs[planes_count].address);
6679
+
&bundle->flip_addrs[planes_count].address,
6680
+
false);
6681
+
6682
+
DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n",
6683
+
new_plane_state->plane->index,
6684
+
bundle->plane_infos[planes_count].dcc.enable);
6694
6685
6695
6686
bundle->surface_updates[planes_count].plane_info =
6696
6687
&bundle->plane_infos[planes_count];
···
8115
8096
ret = fill_dc_plane_info_and_addr(
8116
8097
dm->adev, new_plane_state, tiling_flags,
8117
8098
plane_info,
8118
-
&flip_addr->address);
8099
+
&flip_addr->address,
8100
+
false);
8119
8101
if (ret)
8120
8102
goto cleanup;
8121
8103
+27
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+27
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
···
2911
2911
for (i = 0; i < MAX_PIPES; i++) {
2912
2912
pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2913
2913
if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2914
+
link->dc->hwss.blank_stream(pipe_ctx);
2915
+
}
2916
+
2917
+
for (i = 0; i < MAX_PIPES; i++) {
2918
+
pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2919
+
if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2914
2920
break;
2915
2921
}
2916
2922
···
2932
2926
2933
2927
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2934
2928
dc_link_reallocate_mst_payload(link);
2929
+
2930
+
for (i = 0; i < MAX_PIPES; i++) {
2931
+
pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2932
+
if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2933
+
link->dc->hwss.unblank_stream(pipe_ctx, &previous_link_settings);
2934
+
}
2935
2935
2936
2936
status = false;
2937
2937
if (out_link_loss)
···
4239
4227
void dpcd_set_source_specific_data(struct dc_link *link)
4240
4228
{
4241
4229
const uint32_t post_oui_delay = 30; // 30ms
4230
+
uint8_t dspc = 0;
4231
+
enum dc_status ret = DC_ERROR_UNEXPECTED;
4232
+
4233
+
ret = core_link_read_dpcd(link, DP_DOWN_STREAM_PORT_COUNT, &dspc,
4234
+
sizeof(dspc));
4235
+
4236
+
if (ret != DC_OK) {
4237
+
DC_LOG_ERROR("Error in DP aux read transaction,"
4238
+
" not writing source specific data\n");
4239
+
return;
4240
+
}
4241
+
4242
+
/* Return if OUI unsupported */
4243
+
if (!(dspc & DP_OUI_SUPPORT))
4244
+
return;
4242
4245
4243
4246
if (!link->dc->vendor_signature.is_valid) {
4244
4247
struct dpcd_amd_signature amd_signature;
+4
-36
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+4
-36
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
···
231
231
return dc_stream_get_status_from_state(dc->current_state, stream);
232
232
}
233
233
234
-
static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc *dc)
235
-
{
236
-
#if defined(CONFIG_DRM_AMD_DC_DCN)
237
-
unsigned int vupdate_line;
238
-
unsigned int lines_to_vupdate, us_to_vupdate, vpos, nvpos;
239
-
struct dc_stream_state *stream = pipe_ctx->stream;
240
-
unsigned int us_per_line;
241
-
242
-
if (stream->ctx->asic_id.chip_family == FAMILY_RV &&
243
-
ASICREV_IS_RAVEN(stream->ctx->asic_id.hw_internal_rev)) {
244
-
245
-
vupdate_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
246
-
if (!dc_stream_get_crtc_position(dc, &stream, 1, &vpos, &nvpos))
247
-
return;
248
-
249
-
if (vpos >= vupdate_line)
250
-
return;
251
-
252
-
us_per_line = stream->timing.h_total * 10000 / stream->timing.pix_clk_100hz;
253
-
lines_to_vupdate = vupdate_line - vpos;
254
-
us_to_vupdate = lines_to_vupdate * us_per_line;
255
-
256
-
/* 70 us is a conservative estimate of cursor update time*/
257
-
if (us_to_vupdate < 70)
258
-
udelay(us_to_vupdate);
259
-
}
260
-
#endif
261
-
}
262
234
263
235
/**
264
236
* dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
···
270
298
271
299
if (!pipe_to_program) {
272
300
pipe_to_program = pipe_ctx;
273
-
274
-
delay_cursor_until_vupdate(pipe_ctx, dc);
275
-
dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
301
+
dc->hwss.cursor_lock(dc, pipe_to_program, true);
276
302
}
277
303
278
304
dc->hwss.set_cursor_attribute(pipe_ctx);
···
279
309
}
280
310
281
311
if (pipe_to_program)
282
-
dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
312
+
dc->hwss.cursor_lock(dc, pipe_to_program, false);
283
313
284
314
return true;
285
315
}
···
319
349
320
350
if (!pipe_to_program) {
321
351
pipe_to_program = pipe_ctx;
322
-
323
-
delay_cursor_until_vupdate(pipe_ctx, dc);
324
-
dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
352
+
dc->hwss.cursor_lock(dc, pipe_to_program, true);
325
353
}
326
354
327
355
dc->hwss.set_cursor_position(pipe_ctx);
328
356
}
329
357
330
358
if (pipe_to_program)
331
-
dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
359
+
dc->hwss.cursor_lock(dc, pipe_to_program, false);
332
360
333
361
return true;
334
362
}
+1
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+1
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
···
2757
2757
.disable_plane = dce110_power_down_fe,
2758
2758
.pipe_control_lock = dce_pipe_control_lock,
2759
2759
.interdependent_update_lock = NULL,
2760
+
.cursor_lock = dce_pipe_control_lock,
2760
2761
.prepare_bandwidth = dce110_prepare_bandwidth,
2761
2762
.optimize_bandwidth = dce110_optimize_bandwidth,
2762
2763
.set_drr = set_drr,
+10
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+10
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
···
1625
1625
hws->funcs.verify_allow_pstate_change_high(dc);
1626
1626
}
1627
1627
1628
+
void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)
1629
+
{
1630
+
/* cursor lock is per MPCC tree, so only need to lock one pipe per stream */
1631
+
if (!pipe || pipe->top_pipe)
1632
+
return;
1633
+
1634
+
dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc,
1635
+
pipe->stream_res.opp->inst, lock);
1636
+
}
1637
+
1628
1638
static bool wait_for_reset_trigger_to_occur(
1629
1639
struct dc_context *dc_ctx,
1630
1640
struct timing_generator *tg)
+1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
···
50
50
.disable_audio_stream = dce110_disable_audio_stream,
51
51
.disable_plane = dcn10_disable_plane,
52
52
.pipe_control_lock = dcn10_pipe_control_lock,
53
+
.cursor_lock = dcn10_cursor_lock,
53
54
.interdependent_update_lock = dcn10_lock_all_pipes,
54
55
.prepare_bandwidth = dcn10_prepare_bandwidth,
55
56
.optimize_bandwidth = dcn10_optimize_bandwidth,
+15
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+15
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
···
223
223
REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
224
224
REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
225
225
226
+
/* Configure VUPDATE lock set for this MPCC to map to the OPP */
227
+
REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id);
228
+
226
229
/* update mpc tree mux setting */
227
230
if (tree->opp_list == insert_above_mpcc) {
228
231
/* insert the toppest mpcc */
···
321
318
REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
322
319
REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
323
320
REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
321
+
REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
324
322
325
323
/* mark this mpcc as not in use */
326
324
mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);
···
332
328
REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
333
329
REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
334
330
REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
331
+
REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
335
332
}
336
333
}
337
334
···
366
361
REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
367
362
REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
368
363
REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
364
+
REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
369
365
370
366
mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
371
367
}
···
387
381
REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
388
382
REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
389
383
REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
384
+
REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
390
385
391
386
mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
392
387
···
460
453
MPCC_BUSY, &s->busy);
461
454
}
462
455
456
+
void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)
457
+
{
458
+
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
459
+
460
+
REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0);
461
+
}
462
+
463
463
static const struct mpc_funcs dcn10_mpc_funcs = {
464
464
.read_mpcc_state = mpc1_read_mpcc_state,
465
465
.insert_plane = mpc1_insert_plane,
···
478
464
.assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
479
465
.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
480
466
.update_blending = mpc1_update_blending,
467
+
.cursor_lock = mpc1_cursor_lock,
481
468
.set_denorm = NULL,
482
469
.set_denorm_clamp = NULL,
483
470
.set_output_csc = NULL,
+14
-6
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+14
-6
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
···
39
39
SRII(MPCC_BG_G_Y, MPCC, inst),\
40
40
SRII(MPCC_BG_R_CR, MPCC, inst),\
41
41
SRII(MPCC_BG_B_CB, MPCC, inst),\
42
-
SRII(MPCC_BG_B_CB, MPCC, inst),\
43
-
SRII(MPCC_SM_CONTROL, MPCC, inst)
42
+
SRII(MPCC_SM_CONTROL, MPCC, inst),\
43
+
SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
44
44
45
45
#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \
46
-
SRII(MUX, MPC_OUT, inst)
46
+
SRII(MUX, MPC_OUT, inst),\
47
+
VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst)
47
48
48
49
#define MPC_COMMON_REG_VARIABLE_LIST \
49
50
uint32_t MPCC_TOP_SEL[MAX_MPCC]; \
···
56
55
uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
57
56
uint32_t MPCC_BG_B_CB[MAX_MPCC]; \
58
57
uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \
59
-
uint32_t MUX[MAX_OPP];
58
+
uint32_t MUX[MAX_OPP]; \
59
+
uint32_t MPCC_UPDATE_LOCK_SEL[MAX_MPCC]; \
60
+
uint32_t CUR[MAX_OPP];
60
61
61
62
#define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
62
63
SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
···
81
78
SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\
82
79
SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\
83
80
SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\
84
-
SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh)
81
+
SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\
82
+
SF(MPCC0_MPCC_UPDATE_LOCK_SEL, MPCC_UPDATE_LOCK_SEL, mask_sh)
85
83
86
84
#define MPC_REG_FIELD_LIST(type) \
87
85
type MPCC_TOP_SEL;\
···
105
101
type MPCC_SM_FIELD_ALT;\
106
102
type MPCC_SM_FORCE_NEXT_FRAME_POL;\
107
103
type MPCC_SM_FORCE_NEXT_TOP_POL;\
108
-
type MPC_OUT_MUX;
104
+
type MPC_OUT_MUX;\
105
+
type MPCC_UPDATE_LOCK_SEL;\
106
+
type CUR_VUPDATE_LOCK_SET;
109
107
110
108
struct dcn_mpc_registers {
111
109
MPC_COMMON_REG_VARIABLE_LIST
···
197
191
struct mpc *mpc,
198
192
int mpcc_inst,
199
193
struct mpcc_state *s);
194
+
195
+
void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
200
196
201
197
#endif
+12
-2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+12
-2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
···
181
181
.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
182
182
mm ## block ## id ## _ ## reg_name
183
183
184
+
#define VUPDATE_SRII(reg_name, block, id)\
185
+
.reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
186
+
mm ## reg_name ## 0 ## _ ## block ## id
187
+
188
+
/* set field/register/bitfield name */
189
+
#define SFRB(field_name, reg_name, bitfield, post_fix)\
190
+
.field_name = reg_name ## __ ## bitfield ## post_fix
191
+
184
192
/* NBIO */
185
193
#define NBIO_BASE_INNER(seg) \
186
194
NBIF_BASE__INST0_SEG ## seg
···
427
419
};
428
420
429
421
static const struct dcn_mpc_shift mpc_shift = {
430
-
MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
422
+
MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\
423
+
SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT)
431
424
};
432
425
433
426
static const struct dcn_mpc_mask mpc_mask = {
434
-
MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),
427
+
MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\
428
+
SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK)
435
429
};
436
430
437
431
#define tg_regs(id)\
+2
-1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+2
-1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
···
2294
2294
2295
2295
REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2296
2296
REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2297
-
REG_WRITE(REFCLK_CNTL, 0);
2297
+
if (REG(REFCLK_CNTL))
2298
+
REG_WRITE(REFCLK_CNTL, 0);
2298
2299
//
2299
2300
2300
2301
+1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
···
52
52
.disable_plane = dcn20_disable_plane,
53
53
.pipe_control_lock = dcn20_pipe_control_lock,
54
54
.interdependent_update_lock = dcn10_lock_all_pipes,
55
+
.cursor_lock = dcn10_cursor_lock,
55
56
.prepare_bandwidth = dcn20_prepare_bandwidth,
56
57
.optimize_bandwidth = dcn20_optimize_bandwidth,
57
58
.update_bandwidth = dcn20_update_bandwidth,
+1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
···
545
545
.mpc_init = mpc1_mpc_init,
546
546
.mpc_init_single_inst = mpc1_mpc_init_single_inst,
547
547
.update_blending = mpc2_update_blending,
548
+
.cursor_lock = mpc1_cursor_lock,
548
549
.get_mpcc_for_dpp = mpc2_get_mpcc_for_dpp,
549
550
.wait_for_idle = mpc2_assert_idle_mpcc,
550
551
.assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
+2
-1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
+2
-1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
···
179
179
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
180
180
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
181
181
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
182
-
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh)
182
+
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
183
+
SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
183
184
184
185
/*
185
186
* DCN2 MPC_OCSC debug status register:
+4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
···
508
508
.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
509
509
mm ## block ## id ## _ ## reg_name
510
510
511
+
#define VUPDATE_SRII(reg_name, block, id)\
512
+
.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
513
+
mm ## reg_name ## _ ## block ## id
514
+
511
515
/* NBIO */
512
516
#define NBIO_BASE_INNER(seg) \
513
517
NBIO_BASE__INST0_SEG ## seg
+1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
···
53
53
.disable_plane = dcn20_disable_plane,
54
54
.pipe_control_lock = dcn20_pipe_control_lock,
55
55
.interdependent_update_lock = dcn10_lock_all_pipes,
56
+
.cursor_lock = dcn10_cursor_lock,
56
57
.prepare_bandwidth = dcn20_prepare_bandwidth,
57
58
.optimize_bandwidth = dcn20_optimize_bandwidth,
58
59
.update_bandwidth = dcn20_update_bandwidth,
+32
-43
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+32
-43
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
···
284
284
.dram_channel_width_bytes = 4,
285
285
.fabric_datapath_to_dcn_data_return_bytes = 32,
286
286
.dcn_downspread_percent = 0.5,
287
-
.downspread_percent = 0.5,
287
+
.downspread_percent = 0.38,
288
288
.dram_page_open_time_ns = 50.0,
289
289
.dram_rw_turnaround_time_ns = 17.5,
290
290
.dram_return_buffer_per_channel_bytes = 8192,
···
339
339
#define DCCG_SRII(reg_name, block, id)\
340
340
.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
341
341
mm ## block ## id ## _ ## reg_name
342
+
343
+
#define VUPDATE_SRII(reg_name, block, id)\
344
+
.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
345
+
mm ## reg_name ## _ ## block ## id
342
346
343
347
/* NBIO */
344
348
#define NBIO_BASE_INNER(seg) \
···
1378
1374
{
1379
1375
struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1380
1376
struct clk_limit_table *clk_table = &bw_params->clk_table;
1381
-
unsigned int i, j, k;
1382
-
int closest_clk_lvl;
1377
+
struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1378
+
unsigned int i, j, closest_clk_lvl;
1383
1379
1384
1380
// Default clock levels are used for diags, which may lead to overclocking.
1385
-
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && !IS_DIAG_DC(dc->ctx->dce_environment)) {
1381
+
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
1386
1382
dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1387
1383
dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1388
1384
dcn2_1_soc.num_chans = bw_params->num_channels;
1389
1385
1390
-
/* Vmin: leave lowest DCN clocks, override with dcfclk, fclk, memclk from fuse */
1391
-
dcn2_1_soc.clock_limits[0].state = 0;
1392
-
dcn2_1_soc.clock_limits[0].dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
1393
-
dcn2_1_soc.clock_limits[0].fabricclk_mhz = clk_table->entries[0].fclk_mhz;
1394
-
dcn2_1_soc.clock_limits[0].socclk_mhz = clk_table->entries[0].socclk_mhz;
1395
-
dcn2_1_soc.clock_limits[0].dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
1396
-
1397
-
/*
1398
-
* Other levels: find closest DCN clocks that fit the given clock limit using dcfclk
1399
-
* as indicator
1400
-
*/
1401
-
1402
-
closest_clk_lvl = -1;
1403
-
/* index currently being filled */
1404
-
k = 1;
1405
-
for (i = 1; i < clk_table->num_entries; i++) {
1406
-
/* loop backwards, skip duplicate state*/
1407
-
for (j = dcn2_1_soc.num_states - 1; j >= k; j--) {
1386
+
ASSERT(clk_table->num_entries);
1387
+
for (i = 0; i < clk_table->num_entries; i++) {
1388
+
/* loop backwards*/
1389
+
for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
1408
1390
if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1409
1391
closest_clk_lvl = j;
1410
1392
break;
1411
1393
}
1412
1394
}
1413
1395
1414
-
/* if found a lvl that fits, use the DCN clks from it, if not, go to next clk limit*/
1415
-
if (closest_clk_lvl != -1) {
1416
-
dcn2_1_soc.clock_limits[k].state = i;
1417
-
dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1418
-
dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1419
-
dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
1420
-
dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1396
+
clock_limits[i].state = i;
1397
+
clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1398
+
clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1399
+
clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1400
+
clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1421
1401
1422
-
dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1423
-
dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1424
-
dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1425
-
dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1426
-
dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1427
-
dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1428
-
dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1429
-
k++;
1430
-
}
1402
+
clock_limits[i].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1403
+
clock_limits[i].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1404
+
clock_limits[i].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1405
+
clock_limits[i].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1406
+
clock_limits[i].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1407
+
clock_limits[i].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1408
+
clock_limits[i].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1431
1409
}
1432
-
dcn2_1_soc.num_states = k;
1410
+
for (i = 0; i < clk_table->num_entries; i++)
1411
+
dcn2_1_soc.clock_limits[i] = clock_limits[i];
1412
+
if (clk_table->num_entries) {
1413
+
dcn2_1_soc.num_states = clk_table->num_entries;
1414
+
/* duplicate last level */
1415
+
dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1416
+
dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
1417
+
}
1433
1418
}
1434
-
1435
-
/* duplicate last level */
1436
-
dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1437
-
dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
1438
1419
1439
1420
dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1440
1421
}
+16
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+16
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
···
210
210
struct mpcc_blnd_cfg *blnd_cfg,
211
211
int mpcc_id);
212
212
213
+
/*
214
+
* Lock cursor updates for the specified OPP.
215
+
* OPP defines the set of MPCC that are locked together for cursor.
216
+
*
217
+
* Parameters:
218
+
* [in] mpc - MPC context.
219
+
* [in] opp_id - The OPP to lock cursor updates on
220
+
* [in] lock - lock/unlock the OPP
221
+
*
222
+
* Return: void
223
+
*/
224
+
void (*cursor_lock)(
225
+
struct mpc *mpc,
226
+
int opp_id,
227
+
bool lock);
228
+
213
229
struct mpcc* (*get_mpcc_for_dpp)(
214
230
struct mpc_tree *tree,
215
231
int dpp_id);
+1
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+1
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
···
86
86
struct dc_state *context, bool lock);
87
87
void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx,
88
88
bool flip_immediate);
89
+
void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);
89
90
90
91
/* Timing Related */
91
92
void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
+5
-4
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+5
-4
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
···
1435
1435
if (!hwmgr)
1436
1436
return -EINVAL;
1437
1437
1438
-
if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_capability)
1438
+
if (!(hwmgr->not_vf && amdgpu_dpm) ||
1439
+
!hwmgr->hwmgr_func->get_asic_baco_capability)
1439
1440
return 0;
1440
1441
1441
1442
mutex_lock(&hwmgr->smu_lock);
···
1453
1452
if (!hwmgr)
1454
1453
return -EINVAL;
1455
1454
1456
-
if (!(hwmgr->not_vf && amdgpu_dpm) ||
1457
-
!hwmgr->hwmgr_func->get_asic_baco_state)
1455
+
if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state)
1458
1456
return 0;
1459
1457
1460
1458
mutex_lock(&hwmgr->smu_lock);
···
1470
1470
if (!hwmgr)
1471
1471
return -EINVAL;
1472
1472
1473
-
if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_asic_baco_state)
1473
+
if (!(hwmgr->not_vf && amdgpu_dpm) ||
1474
+
!hwmgr->hwmgr_func->set_asic_baco_state)
1474
1475
return 0;
1475
1476
1476
1477
mutex_lock(&hwmgr->smu_lock);
+6
-2
drivers/gpu/drm/drm_dp_mst_topology.c
+6
-2
drivers/gpu/drm/drm_dp_mst_topology.c
···
3442
3442
drm_dp_queue_down_tx(mgr, txmsg);
3443
3443
3444
3444
ret = drm_dp_mst_wait_tx_reply(mstb, txmsg);
3445
-
if (ret > 0 && txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK)
3446
-
ret = -EIO;
3445
+
if (ret > 0) {
3446
+
if (txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK)
3447
+
ret = -EIO;
3448
+
else
3449
+
ret = size;
3450
+
}
3447
3451
3448
3452
kfree(txmsg);
3449
3453
fail_put:
+1
-1
drivers/gpu/drm/drm_edid.c
+1
-1
drivers/gpu/drm/drm_edid.c
···
5111
5111
struct drm_display_mode *mode;
5112
5112
unsigned pixel_clock = (timings->pixel_clock[0] |
5113
5113
(timings->pixel_clock[1] << 8) |
5114
-
(timings->pixel_clock[2] << 16));
5114
+
(timings->pixel_clock[2] << 16)) + 1;
5115
5115
unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5116
5116
unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5117
5117
unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
+20
-4
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+20
-4
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
···
182
182
int tiling_mode, unsigned int stride)
183
183
{
184
184
struct i915_ggtt *ggtt = &to_i915(obj->base.dev)->ggtt;
185
-
struct i915_vma *vma;
185
+
struct i915_vma *vma, *vn;
186
+
LIST_HEAD(unbind);
186
187
int ret = 0;
187
188
188
189
if (tiling_mode == I915_TILING_NONE)
189
190
return 0;
190
191
191
192
mutex_lock(&ggtt->vm.mutex);
193
+
194
+
spin_lock(&obj->vma.lock);
192
195
for_each_ggtt_vma(vma, obj) {
196
+
GEM_BUG_ON(vma->vm != &ggtt->vm);
197
+
193
198
if (i915_vma_fence_prepare(vma, tiling_mode, stride))
194
199
continue;
195
200
196
-
ret = __i915_vma_unbind(vma);
197
-
if (ret)
198
-
break;
201
+
list_move(&vma->vm_link, &unbind);
199
202
}
203
+
spin_unlock(&obj->vma.lock);
204
+
205
+
list_for_each_entry_safe(vma, vn, &unbind, vm_link) {
206
+
ret = __i915_vma_unbind(vma);
207
+
if (ret) {
208
+
/* Restore the remaining vma on an error */
209
+
list_splice(&unbind, &ggtt->vm.bound_list);
210
+
break;
211
+
}
212
+
}
213
+
200
214
mutex_unlock(&ggtt->vm.mutex);
201
215
202
216
return ret;
···
282
268
}
283
269
mutex_unlock(&obj->mm.lock);
284
270
271
+
spin_lock(&obj->vma.lock);
285
272
for_each_ggtt_vma(vma, obj) {
286
273
vma->fence_size =
287
274
i915_gem_fence_size(i915, vma->size, tiling, stride);
···
293
278
if (vma->fence)
294
279
vma->fence->dirty = true;
295
280
}
281
+
spin_unlock(&obj->vma.lock);
296
282
297
283
obj->tiling_and_stride = tiling | stride;
298
284
i915_gem_object_unlock(obj);
+8
-4
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+8
-4
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
···
1477
1477
unsigned int page_size = BIT(first);
1478
1478
1479
1479
obj = i915_gem_object_create_internal(dev_priv, page_size);
1480
-
if (IS_ERR(obj))
1481
-
return PTR_ERR(obj);
1480
+
if (IS_ERR(obj)) {
1481
+
err = PTR_ERR(obj);
1482
+
goto out_vm;
1483
+
}
1482
1484
1483
1485
vma = i915_vma_instance(obj, vm, NULL);
1484
1486
if (IS_ERR(vma)) {
···
1533
1531
}
1534
1532
1535
1533
obj = i915_gem_object_create_internal(dev_priv, PAGE_SIZE);
1536
-
if (IS_ERR(obj))
1537
-
return PTR_ERR(obj);
1534
+
if (IS_ERR(obj)) {
1535
+
err = PTR_ERR(obj);
1536
+
goto out_vm;
1537
+
}
1538
1538
1539
1539
vma = i915_vma_instance(obj, vm, NULL);
1540
1540
if (IS_ERR(vma)) {
+2
drivers/gpu/drm/i915/gt/intel_timeline.c
+2
drivers/gpu/drm/i915/gt/intel_timeline.c
···
521
521
522
522
rcu_read_lock();
523
523
cl = rcu_dereference(from->hwsp_cacheline);
524
+
if (i915_request_completed(from)) /* confirm cacheline is valid */
525
+
goto unlock;
524
526
if (unlikely(!i915_active_acquire_if_busy(&cl->active)))
525
527
goto unlock; /* seqno wrapped and completed! */
526
528
if (unlikely(i915_request_completed(from)))
+2
-4
drivers/gpu/drm/i915/i915_irq.c
+2
-4
drivers/gpu/drm/i915/i915_irq.c
···
3358
3358
{
3359
3359
struct intel_uncore *uncore = &dev_priv->uncore;
3360
3360
3361
-
u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3361
+
u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
3362
+
GEN8_PIPE_CDCLK_CRC_DONE;
3362
3363
u32 de_pipe_enables;
3363
3364
u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3364
3365
u32 de_port_enables;
···
3370
3369
de_misc_masked |= GEN8_DE_MISC_GSE;
3371
3370
3372
3371
if (INTEL_GEN(dev_priv) >= 9) {
3373
-
de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3374
3372
de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3375
3373
GEN9_AUX_CHANNEL_D;
3376
3374
if (IS_GEN9_LP(dev_priv))
3377
3375
de_port_masked |= BXT_DE_PORT_GMBUS;
3378
-
} else {
3379
-
de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3380
3376
}
3381
3377
3382
3378
if (INTEL_GEN(dev_priv) >= 11)
+6
-4
drivers/gpu/drm/i915/i915_vma.c
+6
-4
drivers/gpu/drm/i915/i915_vma.c
···
158
158
159
159
GEM_BUG_ON(!IS_ALIGNED(vma->size, I915_GTT_PAGE_SIZE));
160
160
161
+
spin_lock(&obj->vma.lock);
162
+
161
163
if (i915_is_ggtt(vm)) {
162
164
if (unlikely(overflows_type(vma->size, u32)))
163
-
goto err_vma;
165
+
goto err_unlock;
164
166
165
167
vma->fence_size = i915_gem_fence_size(vm->i915, vma->size,
166
168
i915_gem_object_get_tiling(obj),
167
169
i915_gem_object_get_stride(obj));
168
170
if (unlikely(vma->fence_size < vma->size || /* overflow */
169
171
vma->fence_size > vm->total))
170
-
goto err_vma;
172
+
goto err_unlock;
171
173
172
174
GEM_BUG_ON(!IS_ALIGNED(vma->fence_size, I915_GTT_MIN_ALIGNMENT));
173
175
···
180
178
181
179
__set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(vma));
182
180
}
183
-
184
-
spin_lock(&obj->vma.lock);
185
181
186
182
rb = NULL;
187
183
p = &obj->vma.tree.rb_node;
···
225
225
226
226
return vma;
227
227
228
+
err_unlock:
229
+
spin_unlock(&obj->vma.lock);
228
230
err_vma:
229
231
i915_vma_free(vma);
230
232
return ERR_PTR(-E2BIG);
+5
-5
drivers/gpu/drm/qxl/qxl_cmd.c
+5
-5
drivers/gpu/drm/qxl/qxl_cmd.c
···
480
480
return ret;
481
481
482
482
ret = qxl_release_reserve_list(release, true);
483
-
if (ret)
483
+
if (ret) {
484
+
qxl_release_free(qdev, release);
484
485
return ret;
485
-
486
+
}
486
487
cmd = (struct qxl_surface_cmd *)qxl_release_map(qdev, release);
487
488
cmd->type = QXL_SURFACE_CMD_CREATE;
488
489
cmd->flags = QXL_SURF_FLAG_KEEP_DATA;
···
500
499
/* no need to add a release to the fence for this surface bo,
501
500
since it is only released when we ask to destroy the surface
502
501
and it would never signal otherwise */
503
-
qxl_push_command_ring_release(qdev, release, QXL_CMD_SURFACE, false);
504
502
qxl_release_fence_buffer_objects(release);
503
+
qxl_push_command_ring_release(qdev, release, QXL_CMD_SURFACE, false);
505
504
506
505
surf->hw_surf_alloc = true;
507
506
spin_lock(&qdev->surf_id_idr_lock);
···
543
542
cmd->surface_id = id;
544
543
qxl_release_unmap(qdev, release, &cmd->release_info);
545
544
546
-
qxl_push_command_ring_release(qdev, release, QXL_CMD_SURFACE, false);
547
-
548
545
qxl_release_fence_buffer_objects(release);
546
+
qxl_push_command_ring_release(qdev, release, QXL_CMD_SURFACE, false);
549
547
550
548
return 0;
551
549
}
+3
-3
drivers/gpu/drm/qxl/qxl_display.c
+3
-3
drivers/gpu/drm/qxl/qxl_display.c
···
510
510
cmd->u.set.visible = 1;
511
511
qxl_release_unmap(qdev, release, &cmd->release_info);
512
512
513
-
qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
514
513
qxl_release_fence_buffer_objects(release);
514
+
qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
515
515
516
516
return ret;
517
517
···
652
652
cmd->u.position.y = plane->state->crtc_y + fb->hot_y;
653
653
654
654
qxl_release_unmap(qdev, release, &cmd->release_info);
655
-
qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
656
655
qxl_release_fence_buffer_objects(release);
656
+
qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
657
657
658
658
if (old_cursor_bo != NULL)
659
659
qxl_bo_unpin(old_cursor_bo);
···
700
700
cmd->type = QXL_CURSOR_HIDE;
701
701
qxl_release_unmap(qdev, release, &cmd->release_info);
702
702
703
-
qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
704
703
qxl_release_fence_buffer_objects(release);
704
+
qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
705
705
}
706
706
707
707
static void qxl_update_dumb_head(struct qxl_device *qdev,
+4
-3
drivers/gpu/drm/qxl/qxl_draw.c
+4
-3
drivers/gpu/drm/qxl/qxl_draw.c
···
209
209
goto out_release_backoff;
210
210
211
211
rects = drawable_set_clipping(qdev, num_clips, clips_bo);
212
-
if (!rects)
212
+
if (!rects) {
213
+
ret = -EINVAL;
213
214
goto out_release_backoff;
214
-
215
+
}
215
216
drawable = (struct qxl_drawable *)qxl_release_map(qdev, release);
216
217
217
218
drawable->clip.type = SPICE_CLIP_TYPE_RECTS;
···
243
242
}
244
243
qxl_bo_kunmap(clips_bo);
245
244
246
-
qxl_push_command_ring_release(qdev, release, QXL_CMD_DRAW, false);
247
245
qxl_release_fence_buffer_objects(release);
246
+
qxl_push_command_ring_release(qdev, release, QXL_CMD_DRAW, false);
248
247
249
248
out_release_backoff:
250
249
if (ret)
+2
-1
drivers/gpu/drm/qxl/qxl_image.c
+2
-1
drivers/gpu/drm/qxl/qxl_image.c
···
212
212
break;
213
213
default:
214
214
DRM_ERROR("unsupported image bit depth\n");
215
-
return -EINVAL; /* TODO: cleanup */
215
+
qxl_bo_kunmap_atomic_page(qdev, image_bo, ptr);
216
+
return -EINVAL;
216
217
}
217
218
image->u.bitmap.flags = QXL_BITMAP_TOP_DOWN;
218
219
image->u.bitmap.x = width;
+1
-4
drivers/gpu/drm/qxl/qxl_ioctl.c
+1
-4
drivers/gpu/drm/qxl/qxl_ioctl.c
···
261
261
apply_surf_reloc(qdev, &reloc_info[i]);
262
262
}
263
263
264
+
qxl_release_fence_buffer_objects(release);
264
265
ret = qxl_push_command_ring_release(qdev, release, cmd->type, true);
265
-
if (ret)
266
-
qxl_release_backoff_reserve_list(release);
267
-
else
268
-
qxl_release_fence_buffer_objects(release);
269
266
270
267
out_free_bos:
271
268
out_free_release:
+6
-11
drivers/gpu/drm/virtio/virtgpu_kms.c
+6
-11
drivers/gpu/drm/virtio/virtgpu_kms.c
···
53
53
events_clear, &events_clear);
54
54
}
55
55
56
-
static void virtio_gpu_context_destroy(struct virtio_gpu_device *vgdev,
57
-
uint32_t ctx_id)
58
-
{
59
-
virtio_gpu_cmd_context_destroy(vgdev, ctx_id);
60
-
virtio_gpu_notify(vgdev);
61
-
ida_free(&vgdev->ctx_id_ida, ctx_id - 1);
62
-
}
63
-
64
56
static void virtio_gpu_init_vq(struct virtio_gpu_queue *vgvq,
65
57
void (*work_func)(struct work_struct *work))
66
58
{
···
267
275
void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file)
268
276
{
269
277
struct virtio_gpu_device *vgdev = dev->dev_private;
270
-
struct virtio_gpu_fpriv *vfpriv;
278
+
struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
271
279
272
280
if (!vgdev->has_virgl_3d)
273
281
return;
274
282
275
-
vfpriv = file->driver_priv;
283
+
if (vfpriv->context_created) {
284
+
virtio_gpu_cmd_context_destroy(vgdev, vfpriv->ctx_id);
285
+
virtio_gpu_notify(vgdev);
286
+
}
276
287
277
-
virtio_gpu_context_destroy(vgdev, vfpriv->ctx_id);
288
+
ida_free(&vgdev->ctx_id_ida, vfpriv->ctx_id - 1);
278
289
mutex_destroy(&vfpriv->context_lock);
279
290
kfree(vfpriv);
280
291
file->driver_priv = NULL;
+1
-2
include/linux/dma-buf.h
+1
-2
include/linux/dma-buf.h
···
329
329
330
330
/**
331
331
* struct dma_buf_attach_ops - importer operations for an attachment
332
-
* @move_notify: [optional] notification that the DMA-buf is moving
333
332
*
334
333
* Attachment operations implemented by the importer.
335
334
*/
336
335
struct dma_buf_attach_ops {
337
336
/**
338
-
* @move_notify
337
+
* @move_notify: [optional] notification that the DMA-buf is moving
339
338
*
340
339
* If this callback is provided the framework can avoid pinning the
341
340
* backing store while mappings exists.
+4
include/uapi/drm/amdgpu_drm.h
+4
include/uapi/drm/amdgpu_drm.h
···
346
346
#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
347
347
#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
348
348
#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
349
+
#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
350
+
#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
351
+
#define AMDGPU_TILING_SCANOUT_SHIFT 63
352
+
#define AMDGPU_TILING_SCANOUT_MASK 0x1
349
353
350
354
/* Set/Get helpers for tiling flags. */
351
355
#define AMDGPU_TILING_SET(field, value) \
+6
include/uapi/linux/dma-buf.h
+6
include/uapi/linux/dma-buf.h
···
39
39
40
40
#define DMA_BUF_BASE 'b'
41
41
#define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync)
42
+
43
+
/* 32/64bitness of this uapi was botched in android, there's no difference
44
+
* between them in actual uapi, they're just different numbers.
45
+
*/
42
46
#define DMA_BUF_SET_NAME _IOW(DMA_BUF_BASE, 1, const char *)
47
+
#define DMA_BUF_SET_NAME_A _IOW(DMA_BUF_BASE, 1, u32)
48
+
#define DMA_BUF_SET_NAME_B _IOW(DMA_BUF_BASE, 1, u64)
43
49
44
50
#endif