+2 -2

Documentation/devicetree/bindings/arm/fsl.yaml

reviewed

··· 1222 1222 - description: 1223 1223 Freescale Vybrid Platform Device Tree Bindings 1224 1224 1225 1225 - For the Vybrid SoC familiy all variants with DDR controller are supported, 1225 1225 + For the Vybrid SoC family all variants with DDR controller are supported, 1226 1226 which is the VF5xx and VF6xx series. Out of historical reasons, in most 1227 1227 - places the kernel uses vf610 to refer to the whole familiy. 1227 1227 + places the kernel uses vf610 to refer to the whole family. 1228 1228 The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 1229 1229 core support. 1230 1230 items:

+4 -4

Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt

reviewed

··· 21 21 number of clocks: 22 22 23 23 - a set of core clocks 24 24 - - a set of gatable clocks 24 24 + - a set of gateable clocks 25 25 26 26 Those clocks can be referenced by other Device Tree nodes using two 27 27 cells: 28 28 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the 29 29 - gatable clocks. 30 30 - - The second cell identifies the particular core clock or gatable 29 29 + gateable clocks. 30 30 + - The second cell identifies the particular core clock or gateable 31 31 clocks. 32 32 33 33 The following clocks are available: ··· 38 38 - 0 3 Core 39 39 - 0 4 NAND core 40 40 - 0 5 SDIO core 41 41 - - Gatable clocks 41 41 + - Gateable clocks 42 42 - 1 0 Audio 43 43 - 1 1 Comm Unit 44 44 - 1 2 NAND

+1 -1

Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt

reviewed

··· 16 16 17 17 The mipi0a controller also uses the common power domain from 18 18 Documentation/devicetree/bindings/soc/mediatek/scpsys.txt 19 19 - The available power doamins are defined in dt-bindings/power/mt*-power.h. 19 19 + The available power domains are defined in dt-bindings/power/mt*-power.h. 20 20 21 21 Example: 22 22

+1 -1

Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt

reviewed

··· 15 15 16 16 The vcodecsys controller also uses the common power domain from 17 17 Documentation/devicetree/bindings/soc/mediatek/scpsys.txt 18 18 - The available power doamins are defined in dt-bindings/power/mt*-power.h. 18 18 + The available power domains are defined in dt-bindings/power/mt*-power.h. 19 19 20 20 Example: 21 21

+2 -2

Documentation/devicetree/bindings/arm/sunxi.yaml

reviewed

··· 541 541 - const: msi,primo81 542 542 - const: allwinner,sun6i-a31s 543 543 544 544 - - description: Emlid Neutis N5 Developper Board 544 544 + - description: Emlid Neutis N5 Developer Board 545 545 items: 546 546 - const: emlid,neutis-n5-devboard 547 547 - const: emlid,neutis-n5 548 548 - const: allwinner,sun50i-h5 549 549 550 550 - - description: Emlid Neutis N5H3 Developper Board 550 550 + - description: Emlid Neutis N5H3 Developer Board 551 551 items: 552 552 - const: emlid,neutis-n5h3-devboard 553 553 - const: emlid,neutis-n5h3

+1 -1

Documentation/devicetree/bindings/ata/pata-common.yaml

reviewed

··· 12 12 description: | 13 13 This document defines device tree properties common to most Parallel 14 14 ATA (PATA, also known as IDE) AT attachment storage devices. 15 15 - It doesn't constitue a device tree binding specification by itself but is 15 15 + It doesn't constitute a device tree binding specification by itself but is 16 16 meant to be referenced by device tree bindings. 17 17 18 18 The PATA (IDE) controller-specific device tree bindings are responsible for

+1 -1

Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml

reviewed

··· 43 43 brcm,gisb-arb-master-names: 44 44 $ref: /schemas/types.yaml#/definitions/string-array 45 45 description: > 46 46 - String list of the litteral name of the GISB masters. Should match the 46 46 + String list of the literal name of the GISB masters. Should match the 47 47 number of bits set in brcm,gisb-master-mask and the order in which they 48 48 appear from MSB to LSB. 49 49

+2 -2

Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml

reviewed

··· 7 7 title: NVIDIA Tegra ACONNECT Bus 8 8 9 9 description: | 10 10 - The Tegra ACONNECT bus is an AXI switch which is used to connnect various 10 10 + The Tegra ACONNECT bus is an AXI switch which is used to connect various 11 11 components inside the Audio Processing Engine (APE). All CPU accesses to 12 12 the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All 13 13 - devices accessed via the ACONNNECT are described by child-nodes. 13 13 + devices accessed via the ACONNECT are described by child-nodes. 14 14 15 15 maintainers: 16 16 - Jon Hunter <jonathanh@nvidia.com>

+1 -1

Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-osc-clk.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Allwinner A10 Gatable Oscillator Clock 7 7 + title: Allwinner A10 Gateable Oscillator Clock 8 8 9 9 maintainers: 10 10 - Chen-Yu Tsai <wens@csie.org>

+2 -2

Documentation/devicetree/bindings/clock/alphascale,acc.txt

reviewed

··· 1 1 Alphascale Clock Controller 2 2 3 3 - The ACC (Alphascale Clock Controller) is responsible of choising proper 4 4 - clock source, setting deviders and clock gates. 3 3 + The ACC (Alphascale Clock Controller) is responsible for choosing proper 4 4 + clock source, setting dividers and clock gates. 5 5 6 6 Required properties for the ACC node: 7 7 - compatible: must be "alphascale,asm9260-clock-controller"

+1 -1

Documentation/devicetree/bindings/clock/keystone-pll.txt

reviewed

··· 14 14 - #clock-cells : from common clock binding; shall be set to 0. 15 15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" 16 16 - clocks : parent clock phandle 17 17 - - reg - pll control0 and pll multipler registers 17 17 + - reg - pll control0 and pll multiplier registers 18 18 - reg-names : control, multiplier and post-divider. The multiplier and 19 19 post-divider registers are applicable only for main pll clock 20 20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits

+1 -1

Documentation/devicetree/bindings/clock/lpc1850-ccu.txt

reviewed

··· 68 68 "base_ssp0_clk", "base_sdio_clk"; 69 69 }; 70 70 71 71 - /* A user of CCU brach clocks */ 71 71 + /* A user of CCU branch clocks */ 72 72 uart1: serial@40082000 { 73 73 ... 74 74 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;

+2 -2

Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt

reviewed

··· 5 5 32 kHz oscillator driver with power up/down and clock gating. Next 6 6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc. 7 7 8 8 - These clocks are used by the RTC and the Event Router peripherials. 9 9 - The 32 kHz can also be routed to other peripherials to enable low 8 8 + These clocks are used by the RTC and the Event Router peripherals. 9 9 + The 32 kHz can also be routed to other peripherals to enable low 10 10 power modes. 11 11 12 12 This binding uses the common clock binding:

+1 -1

Documentation/devicetree/bindings/clock/maxim,max9485.txt

reviewed

··· 12 12 13 13 Required properties: 14 14 - compatible: "maxim,max9485" 15 15 - - clocks: Input clock, must provice 27.000 MHz 15 15 + - clocks: Input clock, must provide 27.000 MHz 16 16 - clock-names: Must be set to "xclk" 17 17 - #clock-cells: From common clock binding; shall be set to 1 18 18

+1 -1

Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml

reviewed

··· 25 25 - description: Sleep clock source 26 26 - description: PCIE 0 Pipe clock source (Optional clock) 27 27 - description: PCIE 1 Pipe clock source (Optional clock) 28 28 - - description: PCIE 1 Phy Auxillary clock source (Optional clock) 28 28 + - description: PCIE 1 Phy Auxiliary clock source (Optional clock) 29 29 - description: UFS Phy Rx symbol 0 clock source (Optional clock) 30 30 - description: UFS Phy Rx symbol 1 clock source (Optional clock) 31 31 - description: UFS Phy Tx symbol 0 clock source (Optional clock)

+1 -1

Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml

reviewed

··· 14 14 There is one ACC register region per CPU within the KPSS remapped region as 15 15 well as an alias register region that remaps accesses to the ACC associated 16 16 with the CPU accessing the region. ACC v1 is currently used as a 17 17 - clock-controller for enabling the cpu and hanling the aux clocks. 17 17 + clock-controller for enabling the cpu and handling the aux clocks. 18 18 19 19 properties: 20 20 compatible:

+1 -1

Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml

reviewed

··· 66 66 else: 67 67 description: | 68 68 Other SC9863a clock nodes should be the child of a syscon node in 69 69 - which compatible string shoule be: 69 69 + which compatible string should be: 70 70 "sprd,sc9863a-glbregs", "syscon", "simple-mfd" 71 71 72 72 The 'reg' property for the clock node is also required if there is a sub

+1 -1

Documentation/devicetree/bindings/clock/ti/mux.txt

reviewed

··· 8 8 gate or adjust the parent rate via a divider or multiplier. 9 9 10 10 By default the "clocks" property lists the parents in the same order 11 11 - as they are programmed into the regster. E.g: 11 11 + as they are programmed into the register. E.g: 12 12 13 13 clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>; 14 14

+1 -1

Documentation/devicetree/bindings/clock/vf610-clock.txt

reviewed

··· 9 9 - clocks: list of clock identifiers which are external input clocks to the 10 10 given clock controller. Please refer the next section to find 11 11 the input clocks for a given controller. 12 12 - - clock-names: list of names of clocks which are exteral input clocks to the 12 12 + - clock-names: list of names of clocks which are external input clocks to the 13 13 given clock controller. 14 14 15 15 Input clocks for top clock controller:

+1 -1

Documentation/devicetree/bindings/connector/usb-connector.yaml

reviewed

··· 227 227 state as defined in 7.4.2 Sink Electrical Parameters of USB Power Delivery Specification 228 228 Revision 3.0, Version 1.2. When the property is set, the port requests pSnkStby(2.5W - 229 229 5V@500mA) upon entering SNK_DISCOVERY(instead of 3A or the 1.5A, Rp current advertised, during 230 230 - SNK_DISCOVERY) and the actual currrent limit after reception of PS_Ready for PD link or during 230 230 + SNK_DISCOVERY) and the actual current limit after reception of PS_Ready for PD link or during 231 231 SNK_READY for non-pd link. 232 232 type: boolean 233 233

+1 -1

Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml

reviewed

··· 18 18 each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The 19 19 Exynos PPMU driver uses the devfreq-event class to provide event data to 20 20 various devfreq devices. The devfreq devices would use the event data when 21 21 - derterming the current state of each IP. 21 21 + determining the current state of each IP. 22 22 23 23 properties: 24 24 compatible:

+1 -1

Documentation/devicetree/bindings/display/atmel/hlcdc-dc.txt

reviewed

··· 12 12 13 13 Required children nodes: 14 14 Children nodes are encoding available output ports and their connections 15 15 - to external devices using the OF graph reprensentation (see ../graph.txt). 15 15 + to external devices using the OF graph representation (see ../graph.txt). 16 16 At least one port node is required. 17 17 18 18 Optional properties in grandchild nodes:

+1 -1

Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml

reviewed

··· 11 11 12 12 description: | 13 13 This document defines device tree properties for the Synopsys DesignWare MIPI 14 14 - DSI host controller. It doesn't constitue a device tree binding specification 14 14 + DSI host controller. It doesn't constitute a device tree binding specification 15 15 by itself but is meant to be referenced by platform-specific device tree 16 16 bindings. 17 17

+1 -1

Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt

reviewed

··· 1 1 - * Currus Logic CLPS711X Framebuffer 1 1 + * Cirrus Logic CLPS711X Framebuffer 2 2 3 3 Required properties: 4 4 - compatible: Shall contain "cirrus,ep7209-fb".

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml

reviewed

··· 11 11 - Rob Clark <robdclark@gmail.com> 12 12 13 13 description: 14 14 - This is the bindings documentation for the Mobile Display Subsytem(MDSS) that 14 14 + This is the bindings documentation for the Mobile Display Subsystem(MDSS) that 15 15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc. 16 16 17 17 properties:

+1 -1

Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino.yaml

reviewed

··· 20 20 The panel itself contains: 21 21 - AT24C16C EEPROM holding panel identification and timing requirements 22 22 - AR1021 resistive touch screen controller (optional) 23 23 - - FT5x6 capacitive touch screnn controller (optional) 23 23 + - FT5x6 capacitive touch screen controller (optional) 24 24 - GT911/GT928 capacitive touch screen controller (optional) 25 25 26 26 The above chips share same I2C bus. The EEPROM is factory preprogrammed with

+1 -1

Documentation/devicetree/bindings/display/panel/panel-common.yaml

reviewed

··· 12 12 13 13 description: | 14 14 This document defines device tree properties common to several classes of 15 15 - display panels. It doesn't constitue a device tree binding specification by 15 15 + display panels. It doesn't constitute a device tree binding specification by 16 16 itself but is meant to be referenced by device tree bindings. 17 17 18 18 When referenced from panel device tree bindings the properties defined in this

+1 -1

Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml

reviewed

··· 97 97 98 98 # optional when driving an eDP output 99 99 nvidia,dpaux: 100 100 - description: phandle to a DispayPort AUX interface 100 100 + description: phandle to a DisplayPort AUX interface 101 101 $ref: /schemas/types.yaml#/definitions/phandle 102 102 103 103 allOf:

+1 -1

Documentation/devicetree/bindings/dma/ingenic,dma.yaml

reviewed

··· 68 68 $ref: /schemas/types.yaml#/definitions/uint32 69 69 description: > 70 70 Bitmask of channels to reserve for devices that need a specific 71 71 - channel. These channels will only be assigned when explicitely 71 71 + channel. These channels will only be assigned when explicitly 72 72 requested by a client. The primary use for this is channels 0 and 73 73 1, which can be configured to have special behaviour for NAND/BCH 74 74 when using programmable firmware.

+1 -1

Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.txt

reviewed

··· 2 2 3 3 Required properties: 4 4 - compatible: Should be "nvidia,<chip>-apbdma" 5 5 - - reg: Should contain DMA registers location and length. This shuld include 5 5 + - reg: Should contain DMA registers location and length. This should include 6 6 all of the per-channel registers. 7 7 - interrupts: Should contain all of the per-channel DMA interrupts. 8 8 - clocks: Must contain one entry, for the module clock.

+1 -1

Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml

reviewed

··· 48 48 qcom,controlled-remotely: 49 49 type: boolean 50 50 description: 51 51 - Indicates that the bam is controlled by remote proccessor i.e. execution 51 51 + Indicates that the bam is controlled by remote processor i.e. execution 52 52 environment. 53 53 54 54 qcom,ee:

+1 -1

Documentation/devicetree/bindings/dma/stericsson,dma40.yaml

reviewed

··· 148 148 memcpy-channels: 149 149 $ref: /schemas/types.yaml#/definitions/uint32-array 150 150 description: Array of u32 elements indicating which channels on the DMA 151 151 - engine are elegible for memcpy transfers 151 151 + engine are eligible for memcpy transfers 152 152 153 153 required: 154 154 - "#dma-cells"

+2 -2

Documentation/devicetree/bindings/fpga/fpga-region.txt

reviewed

··· 63 63 will be disabled. 64 64 * During Partial Reconfiguration of a specific region, that region's bridge 65 65 will be used to gate the busses. Traffic to other regions is not affected. 66 66 - * In some implementations, the FPGA Manager transparantly handles gating the 66 66 + * In some implementations, the FPGA Manager transparently handles gating the 67 67 buses, eliminating the need to show the hardware FPGA bridges in the 68 68 device tree. 69 69 * An FPGA image may create a set of reprogrammable regions, each having its ··· 466 466 constraints required to make partial reconfiguration work[1] [2] [3], but a few 467 467 deserve quick mention. 468 468 469 469 - A persona must have boundary connections that line up with those of the partion 469 469 + A persona must have boundary connections that line up with those of the partition 470 470 or region it is designed to go into. 471 471 472 472 During programming, transactions through those connections must be stopped and

+1 -1

Documentation/devicetree/bindings/gpio/gpio-xgene-sb.txt

reviewed

··· 27 27 - gpio-controller: Marks the device node as a GPIO controller. 28 28 - interrupts: The EXT_INT_0 parent interrupt resource must be listed first. 29 29 - interrupt-cells: Should be two. 30 30 - - first cell is 0-N coresponding for EXT_INT_0 to EXT_INT_N. 30 30 + - first cell is 0-N corresponding for EXT_INT_0 to EXT_INT_N. 31 31 - second cell is used to specify flags. 32 32 - interrupt-controller: Marks the device node as an interrupt controller. 33 33 - apm,nr-gpios: Optional, specify number of gpios pin.

+1 -1

Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml

reviewed

··· 9 9 description: | 10 10 Synopsys DesignWare GPIO controllers have a configurable number of ports, 11 11 each of which are intended to be represented as child nodes with the generic 12 12 - GPIO-controller properties as desribed in this bindings file. 12 12 + GPIO-controller properties as described in this bindings file. 13 13 14 14 maintainers: 15 15 - Hoan Tran <hoan@os.amperecomputing.com>

+2 -2

Documentation/devicetree/bindings/gpio/ti,omap-gpio.yaml

reviewed

··· 58 58 deprecated: true 59 59 description: 60 60 Name of the hwmod associated with the GPIO. Needed on some legacy OMAP 61 61 - SoCs which have not been converted to the ti,sysc interconnect hierarachy. 61 61 + SoCs which have not been converted to the ti,sysc interconnect hierarchy. 62 62 63 63 ti,no-reset-on-init: 64 64 $ref: /schemas/types.yaml#/definitions/flag 65 65 deprecated: true 66 66 description: 67 67 Do not reset on init. Used with ti,hwmods on some legacy OMAP SoCs which 68 68 - have not been converted to the ti,sysc interconnect hierarachy. 68 68 + have not been converted to the ti,sysc interconnect hierarchy. 69 69 70 70 patternProperties: 71 71 "^(.+-hog(-[0-9]+)?)$":

+1 -1

Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml

reviewed

··· 27 27 28 28 shunt-resistor-micro-ohms: 29 29 description: 30 30 - The value of curent sense resistor in microohms. If not provided, 30 30 + The value of current sense resistor in microohms. If not provided, 31 31 the current reading and overcurrent alert is disabled. 32 32 33 33 adi,shutdown-threshold-microamp:

+1 -1

Documentation/devicetree/bindings/hwmon/adi,axi-fan-control.yaml

reviewed

··· 11 11 - Nuno Sá <nuno.sa@analog.com> 12 12 13 13 description: |+ 14 14 - Bindings for the Analog Devices AXI FAN Control driver. Spefications of the 14 14 + Bindings for the Analog Devices AXI FAN Control driver. Specifications of the 15 15 core can be found in: 16 16 17 17 https://wiki.analog.com/resources/fpga/docs/axi_fan_control

+1 -1

Documentation/devicetree/bindings/hwmon/adi,ltc2992.yaml

reviewed

··· 46 46 47 47 shunt-resistor-micro-ohms: 48 48 description: 49 49 - The value of curent sense resistor in microohms. 49 49 + The value of current sense resistor in microohms. 50 50 51 51 required: 52 52 - compatible

+1 -1

Documentation/devicetree/bindings/hwmon/aspeed-pwm-tacho.txt

reviewed

··· 45 45 - aspeed,fan-tach-ch : should specify the Fan tach input channel. 46 46 integer value in the range 0 through 15, with 0 indicating 47 47 Fan tach channel 0 and 15 indicating Fan tach channel 15. 48 48 - Atleast one Fan tach input channel is required. 48 48 + At least one Fan tach input channel is required. 49 49 50 50 Examples: 51 51

+1 -1

Documentation/devicetree/bindings/hwmon/lm87.txt

reviewed

··· 18 18 in7. Otherwise the pin is set as FAN2 input. 19 19 20 20 - vcc-supply: a Phandle for the regulator supplying power, can be 21 21 - cofigured to measure 5.0V power supply. Default is 3.3V. 21 21 + configured to measure 5.0V power supply. Default is 3.3V. 22 22 23 23 Example: 24 24

+1 -1

Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt

reviewed

··· 1 1 - Lantiq cpu temperatur sensor 1 1 + Lantiq cpu temperature sensor 2 2 3 3 Requires node properties: 4 4 - compatible value :

+1 -1

Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml

reviewed

··· 42 42 reg: 43 43 items: 44 44 - description: PVT common registers 45 45 - - description: PVT temprature sensor registers 45 45 + - description: PVT temperature sensor registers 46 46 - description: PVT process detector registers 47 47 - description: PVT voltage monitor registers 48 48

+1 -1

Documentation/devicetree/bindings/hwmon/npcm750-pwm-fan.txt

reviewed

··· 23 23 fan subnode format: 24 24 =================== 25 25 Under fan subnode can be upto 8 child nodes, each child node representing a fan. 26 26 - Each fan subnode must have one PWM channel and atleast one Fan tach channel. 26 26 + Each fan subnode must have one PWM channel and at least one Fan tach channel. 27 27 28 28 For PWM channel can be configured cooling-levels to create cooling device. 29 29 Cooling device could be bound to a thermal zone for the thermal control.

+1 -1

Documentation/devicetree/bindings/hwmon/sensirion,shtc1.yaml

reviewed

··· 13 13 The SHTC1, SHTW1 and SHTC3 are digital humidity and temperature sensors 14 14 designed especially for battery-driven high-volume consumer electronics 15 15 applications. 16 16 - For further information refere to Documentation/hwmon/shtc1.rst 16 16 + For further information refer to Documentation/hwmon/shtc1.rst 17 17 18 18 This binding document describes the binding for the hardware monitor 19 19 portion of the driver.

+1 -1

Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml

reviewed

··· 33 33 34 34 shunt-resistor-micro-ohms: 35 35 description: | 36 36 - If 0, the calibration process will be skiped and the current and power 36 36 + If 0, the calibration process will be skipped and the current and power 37 37 measurement engine will not work. Temperature and voltage measurement 38 38 will continue to work. The shunt value also need to respect: 39 39 rshunt <= pga-gain * 40 * 1000 * 1000.

+1 -1

Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml

reviewed

··· 26 26 maxItems: 1 27 27 28 28 shunt-resistor-micro-ohms: 29 29 - description: The value of curent sense resistor in microohms. 29 29 + description: The value of current sense resistor in microohms. 30 30 default: 255000 31 31 minimum: 250000 32 32 maximum: 255000

+1 -1

Documentation/devicetree/bindings/i2c/i2c-sprd.txt

reviewed

··· 10 10 "source" for I2C source (parent) clock, 11 11 "enable" for I2C module enable clock. 12 12 - clocks: Should contain a clock specifier for each entry in clock-names. 13 13 - - clock-frequency: Constains desired I2C bus clock frequency in Hz. 13 13 + - clock-frequency: Contains desired I2C bus clock frequency in Hz. 14 14 - #address-cells: Should be 1 to describe address cells for I2C device address. 15 15 - #size-cells: Should be 0 means no size cell for I2C device address. 16 16

+1 -1

Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml

reviewed

··· 57 57 |27 |FPD Internal voltage measurement, VCC_PSINTFP (supply5). |Voltage 58 58 |28 |PS Auxiliary voltage measurement (supply6). |Voltage 59 59 |29 |PL VCCADC voltage measurement (vccams). |Voltage 60 60 - |30 |Differential analog input signal voltage measurment. |Voltage 60 60 + |30 |Differential analog input signal voltage measurement. |Voltage 61 61 |31 |VUser0 voltage measurement (supply7). |Voltage 62 62 |32 |VUser1 voltage measurement (supply8). |Voltage 63 63 |33 |VUser2 voltage measurement (supply9). |Voltage

+1 -1

Documentation/devicetree/bindings/iio/cdc/adi,ad7150.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/iio/cdc/adi,ad7150.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Analog device AD7150 and similar capacitance to digital convertors. 7 7 + title: Analog device AD7150 and similar capacitance to digital converters. 8 8 9 9 maintainers: 10 10 - Jonathan Cameron <jic23@kernel.org>

+1 -1

Documentation/devicetree/bindings/iio/common.yaml

reviewed

··· 12 12 13 13 description: | 14 14 This document defines device tree properties common to several iio 15 15 - sensors. It doesn't constitue a device tree binding specification by itself but 15 15 + sensors. It doesn't constitute a device tree binding specification by itself but 16 16 is meant to be referenced by device tree bindings. 17 17 18 18 When referenced from sensor tree bindings the properties defined in this

+1 -1

Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml

reviewed

··· 33 33 items: 34 34 - const: lo_in 35 35 description: 36 36 - External clock that provides the Local Oscilator input. 36 36 + External clock that provides the Local Oscillator input. 37 37 38 38 vcm-supply: 39 39 description:

+1 -1

Documentation/devicetree/bindings/iio/humidity/ti,hdc2010.yaml

reviewed

··· 10 10 - Eugene Zaikonnikov <ez@norophonic.com> 11 11 12 12 description: | 13 13 - Relative humidity and tempereature sensors on I2C bus 13 13 + Relative humidity and temperature sensors on I2C bus 14 14 15 15 Datasheets are available at: 16 16 http://www.ti.com/product/HDC2010/datasheet

+1 -1

Documentation/devicetree/bindings/iio/pressure/honeywell,mprls0025pa.yaml

reviewed

··· 47 47 reset-gpios: 48 48 description: 49 49 Optional GPIO for resetting the device. 50 50 - If not present the device is not resetted during the probe. 50 50 + If not present the device is not reset during the probe. 51 51 maxItems: 1 52 52 53 53 honeywell,pmin-pascal:

+1 -1

Documentation/devicetree/bindings/iio/proximity/ams,as3935.yaml

reviewed

··· 10 10 - Matt Ranostay <matt.ranostay@konsulko.com> 11 11 12 12 description: 13 13 - This lightening distance sensor uses an I2C or SPI interface. The 13 13 + This lightning distance sensor uses an I2C or SPI interface. The 14 14 binding currently only covers the SPI option. 15 15 16 16 properties:

+1 -1

Documentation/devicetree/bindings/iio/st,st-sensors.yaml

reviewed

··· 97 97 98 98 interrupts: 99 99 description: interrupt line(s) connected to the DRDY line(s) and/or the 100 100 - Intertial interrupt lines INT1 and INT2 if these exist. This means up to 100 100 + Inertial interrupt lines INT1 and INT2 if these exist. This means up to 101 101 three interrupts, and the DRDY must be the first one if it exists on 102 102 the package. The trigger edge of the interrupts is sometimes software 103 103 configurable in the hardware so the operating system should parse this

+2 -2

Documentation/devicetree/bindings/input/rmi4/rmi_2d_sensor.txt

reviewed

··· 34 34 mode. 35 35 - syna,sensor-type: Set the sensor type. 1 for touchscreen 2 for touchpad. 36 36 - syna,disable-report-mask: Mask for disabling posiiton reporting. Used to 37 37 - disable reporing absolute position data. 38 38 - - syna,rezero-wait-ms: Time in miliseconds to wait after issuing a rezero 37 37 + disable reporting absolute position data. 38 38 + - syna,rezero-wait-ms: Time in milliseconds to wait after issuing a rezero 39 39 command. 40 40 41 41

+1 -1

Documentation/devicetree/bindings/input/touchscreen/tsc2007.txt

reviewed

··· 6 6 - ti,x-plate-ohms: X-plate resistance in ohms. 7 7 8 8 Optional properties: 9 9 - - gpios: the interrupt gpio the chip is connected to (trough the penirq pin). 9 9 + - gpios: the interrupt gpio the chip is connected to (through the penirq pin). 10 10 The penirq pin goes to low when the panel is touched. 11 11 (see GPIO binding[1] for more details). 12 12 - interrupts: (gpio) interrupt to which the chip is connected

+1 -1

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

reviewed

··· 49 49 50 50 The 2nd cell contains the interrupt number for the interrupt type. 51 51 SPI interrupts are in the range [0-987]. PPI interrupts are in the 52 52 - range [0-15]. Extented SPI interrupts are in the range [0-1023]. 52 52 + range [0-15]. Extended SPI interrupts are in the range [0-1023]. 53 53 Extended PPI interrupts are in the range [0-127]. 54 54 55 55 The 3rd cell is the flags, encoded as follows:

+1 -1

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt

reviewed

··· 70 70 25: DMA9 71 71 26: DMA10 72 72 27: DMA11-14 - shared interrupt for DMA 11 to 14 73 73 - 28: DMAALL - triggers on all dma interrupts (including chanel 15) 73 73 + 28: DMAALL - triggers on all dma interrupts (including channel 15) 74 74 29: AUX 75 75 30: ARM 76 76 31: VPUDMA

+1 -1

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml

reviewed

··· 59 59 .. 60 60 31 ........................ X 61 61 62 62 - The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms 62 62 + The BCM3380 Level 1 / Level 2 interrupt controller shows up in various forms 63 63 on many BCM338x/BCM63xx chipsets. It has the following properties: 64 64 65 65 - outputs a single interrupt signal to its interrupt controller parent

+1 -1

Documentation/devicetree/bindings/leds/backlight/mediatek,mt6370-backlight.yaml

reviewed

··· 66 66 67 67 mediatek,bled-ocp-shutdown: 68 68 description: | 69 69 - Enable the backlight shutdown when OCP level triggerred. 69 69 + Enable the backlight shutdown when OCP level triggered. 70 70 type: boolean 71 71 72 72 mediatek,bled-ocp-microamp:

+2 -2

Documentation/devicetree/bindings/leds/leds-lp55xx.yaml

reviewed

··· 106 106 107 107 max-cur: 108 108 $ref: /schemas/types.yaml#/definitions/uint8 109 109 - description: Maximun current at each LED channel. 109 109 + description: Maximum current at each LED channel. 110 110 111 111 reg: 112 112 maximum: 8 ··· 129 129 130 130 max-cur: 131 131 $ref: /schemas/types.yaml#/definitions/uint8 132 132 - description: Maximun current at each LED channel. 132 132 + description: Maximum current at each LED channel. 133 133 134 134 reg: 135 135 description: |

+1 -1

Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml

reviewed

··· 56 56 description: > 57 57 A list of integer pairs, where each pair represent the dtest line the 58 58 particular channel should be connected to and the flags denoting how the 59 59 - value should be outputed, as defined in the datasheet. The number of 59 59 + value should be outputted, as defined in the datasheet. The number of 60 60 pairs should be the same as the number of channels. 61 61 items: 62 62 items:

+1 -1

Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt

reviewed

··· 29 29 where N is the value specified by 2nd cell above. If FlexRM 30 30 does not get required number of completion messages in time 31 31 specified by this cell then it will inject one MSI interrupt 32 32 - to CPU provided atleast one completion message is available. 32 32 + to CPU provided at least one completion message is available. 33 33 34 34 Optional properties: 35 35 --------------------

+1 -1

Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml

reviewed

··· 159 159 a corresponding sysc interconnect node. 160 160 161 161 This property is only needed on some legacy OMAP SoCs which have not 162 162 - yet been converted to the ti,sysc interconnect hierarachy, but is 162 162 + yet been converted to the ti,sysc interconnect hierarchy, but is 163 163 otherwise considered obsolete. 164 164 165 165 patternProperties:

+1 -1

Documentation/devicetree/bindings/media/i2c/toshiba,tc358746.yaml

reviewed

··· 12 12 description: |- 13 13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2 14 14 stream. The direction can be either parallel-in -> csi-out or csi-in -> 15 15 - parallel-out The chip is programmable trough I2C and SPI but the SPI 15 15 + parallel-out The chip is programmable through I2C and SPI but the SPI 16 16 interface is only supported in parallel-in -> csi-out mode. 17 17 18 18 Note that the current device tree bindings only support the

+1 -1

Documentation/devicetree/bindings/media/i2c/tvp5150.txt

reviewed

··· 53 53 ============================== 54 54 55 55 - sdtv-standards: Set the possible signals to which the hardware tries to lock 56 56 - instead of using the autodetection mechnism. Please look at 56 56 + instead of using the autodetection mechanism. Please look at 57 57 [1] for more information. 58 58 59 59 [1] Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml.

+1 -1

Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml

reviewed

··· 36 36 controls the information of each hardware independent which include clk/power/irq. 37 37 38 38 There are two workqueues in parent device: lat workqueue and core workqueue. They are used 39 39 - to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer, 39 39 + to lat and core hardware decoder. Lat workqueue need to get input bitstream and lat buffer, 40 40 then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode 41 41 done. Core workqueue need to get lat buffer and output buffer, then enable core to decode, 42 42 writing the result to output buffer, disable hardware when core decode done. These two

+1 -1

Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml

reviewed

··· 67 67 minimum: 0 68 68 maximum: 31 69 69 description: the hardware id of this larb. It's only required when this 70 70 - hardward id is not consecutive from its M4U point of view. 70 70 + hardware id is not consecutive from its M4U point of view. 71 71 72 72 required: 73 73 - compatible

+2 -2

Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml

reviewed

··· 152 152 $ref: /schemas/types.yaml#/definitions/uint32 153 153 description: 154 154 When the DRAM type is DDR3, this parameter defines the phy side CA line 155 155 - (incluing command line, address line and clock line) drive strength. 155 155 + (including command line, address line and clock line) drive strength. 156 156 default: 40 157 157 158 158 rockchip,phy_ddr3_dq_drv: ··· 305 305 description: 306 306 Defines the self-refresh power down idle period in which memories are 307 307 placed into self-refresh power down mode if bus is idle for 308 308 - srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only. 308 308 + srpd_lite_idle nanoseconds. This parameter is for LPDDR4 only. 309 309 310 310 rockchip,standby-idle-ns: 311 311 description:

+1 -1

Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml

reviewed

··· 12 12 13 13 description: 14 14 The Zynq DDR ECC controller has an optional ECC support in half-bus width 15 15 - (16-bit) configuration. It is cappable of correcting single bit ECC errors 15 15 + (16-bit) configuration. It is capable of correcting single bit ECC errors 16 16 and detecting double bit ECC errors. 17 17 18 18 properties:

+1 -1

Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml

reviewed

··· 27 27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART 28 28 management and bus snoop configuration. 29 29 30 30 - * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom 30 30 + * A set of SuperIO[3] scratch registers enabling implementation of e.g. custom 31 31 hardware management protocols for handover between the host and baseboard 32 32 management controller. 33 33

+2 -2

Documentation/devicetree/bindings/mfd/rohm,bd9576-pmic.yaml

reviewed

··· 34 34 BD9576 and BD9573 VOUT1 regulator enable state can be individually 35 35 controlled by a GPIO. This is dictated by state of vout1-en pin during 36 36 the PMIC startup. If vout1-en is LOW during PMIC startup then the VOUT1 37 37 - enable sate is controlled via this pin. Set this property if vout1-en 37 37 + enable state is controlled via this pin. Set this property if vout1-en 38 38 is wired to be down at PMIC start-up. 39 39 type: boolean 40 40 ··· 61 61 rohm,hw-timeout-ms: 62 62 maxItems: 2 63 63 description: 64 64 - Watchog timeout in milliseconds. If single value is given it is 64 64 + Watchdog timeout in milliseconds. If single value is given it is 65 65 the maximum timeout. Eg. if pinging watchdog is not done within this time 66 66 limit the watchdog will be triggered. If two values are given watchdog 67 67 is configured in "window mode". Then first value is limit for short-ping

+8 -8

Documentation/devicetree/bindings/mfd/stericsson,ab8500.yaml

reviewed

··· 313 313 - const: audioclk 314 314 315 315 stericsson,earpeice-cmv: 316 316 - description: Earpeice voltage 316 316 + description: Earpiece voltage 317 317 $ref: /schemas/types.yaml#/definitions/uint32 318 318 enum: [ 950, 1100, 1270, 1580 ] 319 319 ··· 337 337 with power. 338 338 339 339 ab8500_ldo_aux1: 340 340 - description: The voltage for the auxilary LDO regulator 1 340 340 + description: The voltage for the auxiliary LDO regulator 1 341 341 type: object 342 342 $ref: ../regulator/regulator.yaml# 343 343 unevaluatedProperties: false 344 344 345 345 ab8500_ldo_aux2: 346 346 - description: The voltage for the auxilary LDO regulator 2 346 346 + description: The voltage for the auxiliary LDO regulator 2 347 347 type: object 348 348 $ref: ../regulator/regulator.yaml# 349 349 unevaluatedProperties: false 350 350 351 351 ab8500_ldo_aux3: 352 352 - description: The voltage for the auxilary LDO regulator 3 352 352 + description: The voltage for the auxiliary LDO regulator 3 353 353 type: object 354 354 $ref: ../regulator/regulator.yaml# 355 355 unevaluatedProperties: false 356 356 357 357 ab8500_ldo_aux4: 358 358 - description: The voltage for the auxilary LDO regulator 4 358 358 + description: The voltage for the auxiliary LDO regulator 4 359 359 only present on AB8505 360 360 type: object 361 361 $ref: ../regulator/regulator.yaml# 362 362 unevaluatedProperties: false 363 363 364 364 ab8500_ldo_aux5: 365 365 - description: The voltage for the auxilary LDO regulator 5 365 365 + description: The voltage for the auxiliary LDO regulator 5 366 366 only present on AB8505 367 367 type: object 368 368 $ref: ../regulator/regulator.yaml# 369 369 unevaluatedProperties: false 370 370 371 371 ab8500_ldo_aux6: 372 372 - description: The voltage for the auxilary LDO regulator 6 372 372 + description: The voltage for the auxiliary LDO regulator 6 373 373 only present on AB8505 374 374 type: object 375 375 $ref: ../regulator/regulator.yaml# ··· 378 378 # There is never any AUX7 regulator which is confusing 379 379 380 380 ab8500_ldo_aux8: 381 381 - description: The voltage for the auxilary LDO regulator 8 381 381 + description: The voltage for the auxiliary LDO regulator 8 382 382 only present on AB8505 383 383 type: object 384 384 $ref: ../regulator/regulator.yaml#

+1 -1

Documentation/devicetree/bindings/mfd/stericsson,db8500-prcmu.yaml

reviewed

··· 107 107 $ref: ../regulator/regulator.yaml# 108 108 109 109 db8500_vrf1: 110 110 - description: RF transciever voltage regulator. 110 110 + description: RF transceiver voltage regulator. 111 111 type: object 112 112 $ref: ../regulator/regulator.yaml# 113 113

+1 -1

Documentation/devicetree/bindings/mmc/pxa-mmc.txt

reviewed

··· 9 9 Optional properties: 10 10 - marvell,detect-delay-ms: sets the detection delay timeout in ms. 11 11 12 12 - In addition to the properties described in this docuent, the details 12 12 + In addition to the properties described in this document, the details 13 13 described in mmc.txt are supported. 14 14 15 15 Examples:

+1 -1

Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt

reviewed

··· 95 95 | card | -- CIRQ --> | hsmmc | -- IRQ --> | CPU | 96 96 ------ ------- ----- 97 97 98 98 - In suspend the fclk is off and the module is disfunctional. Even register reads 98 98 + In suspend the fclk is off and the module is dysfunctional. Even register reads 99 99 will fail. A small logic in the host will request fclk restore, when an 100 100 external event is detected. Once the clock is restored, the host detects the 101 101 event normally. Since am33xx doesn't have this line it never wakes from

+1 -1

Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt

reviewed

··· 1 1 - * Broadcom Starfighter 2 integrated swich 1 1 + * Broadcom Starfighter 2 integrated switch 2 2 3 3 See dsa/brcm,bcm7445-switch-v4.0.yaml for the documentation. 4 4

+1 -1

Documentation/devicetree/bindings/net/can/cc770.txt

reviewed

··· 26 26 will be disabled. 27 27 28 28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified, 29 29 - a resonable value will be calculated. 29 29 + a reasonable value will be calculated. 30 30 31 31 - bosch,disconnect-rx0-input : see data sheet. 32 32

+1 -1

Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/net/dsa/brcm,sf2.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Broadcom Starfighter 2 integrated swich 7 7 + title: Broadcom Starfighter 2 integrated switch 8 8 9 9 maintainers: 10 10 - Florian Fainelli <f.fainelli@gmail.com>

+1 -1

Documentation/devicetree/bindings/net/ethernet-phy.yaml

reviewed

··· 110 110 $ref: /schemas/types.yaml#/definitions/flag 111 111 description: 112 112 If set, indicates that PHY will disable swap of the 113 113 - TX/RX lanes. This property allows the PHY to work correcly after 113 113 + TX/RX lanes. This property allows the PHY to work correctly after 114 114 e.g. wrong bootstrap configuration caused by issues in PCB 115 115 layout design. 116 116

+1 -1

Documentation/devicetree/bindings/net/mediatek-dwmac.yaml

reviewed

··· 129 129 type: boolean 130 130 description: 131 131 If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled. 132 132 - Otherwise, PHY WOL is perferred. 132 132 + Otherwise, PHY WOL is preferred. 133 133 134 134 required: 135 135 - compatible

+1 -1

Documentation/devicetree/bindings/net/microchip,lan95xx.yaml

reviewed

··· 33 33 - usb424,9906 # SMSC9505A USB Ethernet Device (HAL) 34 34 - usb424,9907 # SMSC9500 USB Ethernet Device (Alternate ID) 35 35 - usb424,9908 # SMSC9500A USB Ethernet Device (Alternate ID) 36 36 - - usb424,9909 # SMSC9512/9514 USB Hub & Ethernet Devic. ID) 36 36 + - usb424,9909 # SMSC9512/9514 USB Hub & Ethernet Device ID) 37 37 - usb424,9e00 # SMSC9500A USB Ethernet Device 38 38 - usb424,9e01 # SMSC9505A USB Ethernet Device 39 39 - usb424,9e08 # SMSC LAN89530 USB Ethernet Device

+2 -2

Documentation/devicetree/bindings/net/nfc/marvell,nci.yaml

reviewed

··· 37 37 type: boolean 38 38 description: | 39 39 For I2C type of connection. Specifies that the chip read event shall be 40 40 - trigged on falling edge. 40 40 + triggered on falling edge. 41 41 42 42 i2c-int-rising: 43 43 type: boolean 44 44 description: | 45 45 For I2C type of connection. Specifies that the chip read event shall be 46 46 - trigged on rising edge. 46 46 + triggered on rising edge. 47 47 48 48 break-control: 49 49 type: boolean

+2 -2

Documentation/devicetree/bindings/net/samsung-sxgbe.txt

reviewed

··· 5 5 - reg: Address and length of the register set for the device 6 6 - interrupts: Should contain the SXGBE interrupts 7 7 These interrupts are ordered by fixed and follows variable 8 8 - trasmit DMA interrupts, receive DMA interrupts and lpi interrupt. 8 8 + transmit DMA interrupts, receive DMA interrupts and lpi interrupt. 9 9 index 0 - this is fixed common interrupt of SXGBE and it is always 10 10 available. 11 11 - index 1 to 25 - 8 variable trasmit interrupts, variable 16 receive interrupts 11 11 + index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts 12 12 and 1 optional lpi interrupt. 13 13 - phy-mode: String, operation mode of the PHY interface. 14 14 Supported values are: "sgmii", "xgmii".

+1 -1

Documentation/devicetree/bindings/net/snps,dwc-qos-ethernet.txt

reviewed

··· 110 110 It depends on the SoC configuration. 111 111 - snps,read-requests: Number of read requests that the AXI port can issue. 112 112 It depends on the SoC configuration. 113 113 - - snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB 113 113 + - snps,burst-map: Bitmap of allowed AXI burst lengths, with the LSB 114 114 representing 4, then 8 etc. 115 115 - snps,txpbl: DMA Programmable burst length for the TX DMA 116 116 - snps,rxpbl: DMA Programmable burst length for the RX DMA

+1 -1

Documentation/devicetree/bindings/net/sti-dwmac.txt

reviewed

··· 21 21 MAC can generate it. 22 22 - st,tx-retime-src: This specifies which clk is wired up to the mac for 23 23 retimeing tx lines. This is totally board dependent and can take one of the 24 24 - posssible values from "txclk", "clk_125" or "clkgen". 24 24 + possible values from "txclk", "clk_125" or "clkgen". 25 25 If not passed, the internal clock will be used by default. 26 26 - sti-ethclk: this is the phy clock. 27 27 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,

+1 -1

Documentation/devicetree/bindings/net/xilinx_gmii2rgmii.txt

reviewed

··· 7 7 This core can be used in all three modes of operation(10/100/1000 Mb/s). 8 8 The Management Data Input/Output (MDIO) interface is used to configure the 9 9 Speed of operation. This core can switch dynamically between the three 10 10 - Different speed modes by configuring the conveter register through mdio write. 10 10 + Different speed modes by configuring the converter register through mdio write. 11 11 12 12 This converter sits between the ethernet MAC and the external phy. 13 13 MAC <==> GMII2RGMII <==> RGMII_PHY

+1 -1

Documentation/devicetree/bindings/nios2/nios2.txt

reviewed

··· 23 23 - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB. 24 24 - altr,tlb-num-entries: Specifies the number of entries in the TLB. 25 25 - altr,tlb-ptr-sz: Specifies size of TLB pointer. 26 26 - - altr,has-mul: Specifies CPU hardware multipy support, should be 1. 26 26 + - altr,has-mul: Specifies CPU hardware multiply support, should be 1. 27 27 - altr,has-mmu: Specifies CPU support MMU support, should be 1. 28 28 - altr,has-initda: Specifies CPU support initda instruction, should be 1. 29 29 - altr,reset-addr: Specifies CPU reset address

+1 -1

Documentation/devicetree/bindings/nvmem/layouts/onie,tlv-layout.yaml

reviewed

··· 14 14 infrastructure shall provide a non-volatile memory with a table whose the 15 15 content is well specified and gives many information about the manufacturer 16 16 (name, country of manufacture, etc) as well as device caracteristics (serial 17 17 - number, hardware version, mac addresses, etc). The underlaying device type 17 17 + number, hardware version, mac addresses, etc). The underlying device type 18 18 (flash, EEPROM,...) is not specified. The exact location of each value is also 19 19 dynamic and should be discovered at run time because it depends on the 20 20 parameters the manufacturer decided to embed.

+1 -1

Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt

reviewed

··· 14 14 - #size-cells: Must be 0. 15 15 16 16 The INNO USB2 PHY device should be a child node of peripheral controller that 17 17 - contains the PHY configuration register, and each device suppports up to 2 PHY 17 17 + contains the PHY configuration register, and each device supports up to 2 PHY 18 18 ports which are represented as child nodes of INNO USB2 PHY device. 19 19 20 20 Required properties for PHY port node:

+1 -1

Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt

reviewed

··· 8 8 - clocks: Must contain an entry for each entry in clock-names. 9 9 See ../clock/clock-bindings.txt for details. 10 10 - clock-names: Must include "usb_phy". 11 11 - - img,cr-top: Must constain a phandle to the CR_TOP syscon node. 11 11 + - img,cr-top: Must contain a phandle to the CR_TOP syscon node. 12 12 - img,refclk: Indicates the reference clock source for the USB PHY. 13 13 See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values. 14 14

+1 -1

Documentation/devicetree/bindings/phy/pxa1928-usb-phy.txt

reviewed

··· 4 4 - compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy" 5 5 - reg: base address and length of the registers 6 6 - clocks - A single clock. From common clock binding. 7 7 - - #phys-cells: should be 0. From commmon phy binding. 7 7 + - #phys-cells: should be 0. From common phy binding. 8 8 - resets: reference to the reset controller 9 9 10 10 Example:

+1 -1

Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml

reviewed

··· 10 10 - Heiko Stuebner <heiko@sntech.de> 11 11 12 12 description: | 13 13 - The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP wich 13 13 + The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which 14 14 connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras. 15 15 16 16 properties:

+1 -1

Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml

reviewed

··· 59 59 description: 60 60 GPIO to signal Type-C cable orientation for lane swap. 61 61 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to 62 62 - achieve the funtionality of an external type-C plug flip mux. 62 62 + achieve the functionality of an external type-C plug flip mux. 63 63 64 64 typec-dir-debounce-ms: 65 65 minimum: 100

+1 -1

Documentation/devicetree/bindings/phy/ti-phy.txt

reviewed

··· 62 62 - ctrl-module : phandle of the control module used by PHY driver to power on 63 63 the PHY. 64 64 65 65 - Recommended properies: 65 65 + Recommended properties: 66 66 - syscon-phy-power : phandle/offset pair. Phandle to the system control 67 67 module and the register offset to power on/off the PHY. 68 68

+1 -1

Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml

reviewed

··· 97 97 # It's pretty scary, but the basic idea is that: 98 98 # - One node name can start with either s- or r- for PRCM nodes, 99 99 # - Then, the name itself can be any repetition of <string>- (to 100 100 - # accomodate with nodes like uart4-rts-cts-pins), where each 100 100 + # accommodate with nodes like uart4-rts-cts-pins), where each 101 101 # string can be either starting with 'p' but in a string longer 102 102 # than 3, or something that doesn't start with 'p', 103 103 # - Then, the bank name is optional and will be between pa and pg,

+1 -1

Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml

reviewed

··· 11 11 12 12 description: 13 13 The Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA) 14 14 - controller allows assiging any of 256 possible functions to any of 14 14 + controller allows assigning any of 256 possible functions to any of 15 15 48 IO pins of the SoC. Pin function configuration is performed on 16 16 a per-pin basis. 17 17

+1 -1

Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml

reviewed

··· 159 159 160 160 mediatek,pull-up-adv: 161 161 description: | 162 162 - Pull up setings for 2 pull resistors, R0 and R1. User can 162 162 + Pull up settings for 2 pull resistors, R0 and R1. User can 163 163 configure those special pins. Valid arguments are described as 164 164 below: 165 165 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

+1 -1

Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml

reviewed

··· 130 130 131 131 mediatek,pull-up-adv: 132 132 description: | 133 133 - Pull up setings for 2 pull resistors, R0 and R1. User can 133 133 + Pull up settings for 2 pull resistors, R0 and R1. User can 134 134 configure those special pins. Valid arguments are described as 135 135 below: 136 136 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

+2 -2

Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml

reviewed

··· 386 386 mediatek,pull-up-adv: 387 387 description: | 388 388 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 389 389 - Pull up setings for 2 pull resistors, R0 and R1. Valid arguments 389 389 + Pull up settings for 2 pull resistors, R0 and R1. Valid arguments 390 390 are described as below: 391 391 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 392 392 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. ··· 398 398 mediatek,pull-down-adv: 399 399 description: | 400 400 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 401 401 - Pull down setings for 2 pull resistors, R0 and R1. Valid arguments 401 401 + Pull down settings for 2 pull resistors, R0 and R1. Valid arguments 402 402 are described as below: 403 403 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 404 404 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

+2 -2

Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml

reviewed

··· 332 332 mediatek,pull-up-adv: 333 333 description: | 334 334 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 335 335 - Pull up setings for 2 pull resistors, R0 and R1. Valid arguments 335 335 + Pull up settings for 2 pull resistors, R0 and R1. Valid arguments 336 336 are described as below: 337 337 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 338 338 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. ··· 344 344 mediatek,pull-down-adv: 345 345 description: | 346 346 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 347 347 - Pull down setings for 2 pull resistors, R0 and R1. Valid arguments 347 347 + Pull down settings for 2 pull resistors, R0 and R1. Valid arguments 348 348 are described as below: 349 349 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 350 350 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

+1 -1

Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml

reviewed

··· 143 143 144 144 mediatek,pull-up-adv: 145 145 description: | 146 146 - Pull up setings for 2 pull resistors, R0 and R1. User can 146 146 + Pull up settings for 2 pull resistors, R0 and R1. User can 147 147 configure those special pins. Valid arguments are described as 148 148 below: 149 149 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

+1 -1

Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml

reviewed

··· 149 149 deprecated: true 150 150 description: | 151 151 DEPRECATED: Please use bias-pull-up instead. 152 152 - Pull up setings for 2 pull resistors, R0 and R1. User can 152 152 + Pull up settings for 2 pull resistors, R0 and R1. User can 153 153 configure those special pins. Valid arguments are described as 154 154 below: 155 155 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

+1 -1

Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt

reviewed

··· 38 38 gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in, 39 39 reference-out 40 40 41 41 - Theres is also customised properties for the GPIO1, GPIO2 and GPIO3. These 41 41 + There are also customised properties for the GPIO1, GPIO2 and GPIO3. These 42 42 customised properties are required to configure FPS configuration parameters 43 43 of these GPIOs. Please refer <devicetree/bindings/mfd/max77620.txt> for more 44 44 detail of Flexible Power Sequence (FPS).

+1 -1

Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt

reviewed

··· 40 40 41 41 Valid values for function properties are: gpio. 42 42 43 43 - Theres is also not customised properties for any GPIO. 43 43 + There are also not customised properties for any GPIO. 44 44 45 45 Example: 46 46 --------

+1 -1

Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt

reviewed

··· 8 8 pad driving level, system control select and so on ("domain pad 9 9 driving level": One pin can output 3.0v or 1.8v, depending on the 10 10 related domain pad driving selection, if the related domain pad 11 11 - slect 3.0v, then the pin can output 3.0v. "system control" is used 11 11 + select 3.0v, then the pin can output 3.0v. "system control" is used 12 12 to choose one function (like: UART0) for which system, since we 13 13 have several systems (AP/CP/CM4) on one SoC.). 14 14

+2 -2

Documentation/devicetree/bindings/pmem/pmem-region.txt

reviewed

··· 19 19 - compatible = "pmem-region" 20 20 21 21 - reg = <base, size>; 22 22 - The reg property should specificy an address range that is 22 22 + The reg property should specify an address range that is 23 23 translatable to a system physical address range. This address 24 24 range should be mappable as normal system memory would be 25 25 (i.e cacheable). ··· 30 30 node implies no special relationship between the two ranges. 31 31 32 32 Optional properties: 33 33 - - Any relevant NUMA assocativity properties for the target platform. 33 33 + - Any relevant NUMA associativity properties for the target platform. 34 34 35 35 - volatile; This property indicates that this region is actually 36 36 backed by non-persistent memory. This lets the OS know that it

+1 -1

Documentation/devicetree/bindings/power/renesas,sysc-rmobile.yaml

reviewed

··· 58 58 pd-node: 59 59 type: object 60 60 description: 61 61 - PM domain node representing a PM domain. This node hould be named by 61 61 + PM domain node representing a PM domain. This node should be named by 62 62 the real power area name, and thus its name should be unique. 63 63 64 64 properties:

+1 -1

Documentation/devicetree/bindings/power/supply/sbs,sbs-manager.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/power/supply/sbs,sbs-manager.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: SBS compliant manger 7 7 + title: SBS compliant manager 8 8 9 9 maintainers: 10 10 - Sebastian Reichel <sre@kernel.org>

+1 -1

Documentation/devicetree/bindings/powerpc/fsl/cpus.txt

reviewed

··· 28 28 Snoop ID Port Mapping registers, which are part of the CoreNet 29 29 Coherency fabric (CCF), provide a CoreNet Coherency Subdomain 30 30 ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from 31 31 - these registers should be set if the coresponding CPU should be 31 31 + these registers should be set if the corresponding CPU should be 32 32 snooped. This property defines a bitmask which selects the bit 33 33 that should be set if this cpu should be snooped.

+2 -2

Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt

reviewed

··· 185 185 with distinct functionality. 186 186 187 187 The first register range describes the CoreNet Debug Controller 188 188 - functionalty to perform transaction and transaction attribute matches. 188 188 + functionality to perform transaction and transaction attribute matches. 189 189 190 190 The second register range describes the CoreNet Debug Controller 191 191 - functionalty to trigger event notifications and debug traces. 191 191 + functionality to trigger event notifications and debug traces. 192 192 193 193 EXAMPLE 194 194 dcsr-corenet {

+1 -1

Documentation/devicetree/bindings/powerpc/fsl/raideng.txt

reviewed

··· 60 60 - fsl,liodn: Specifies the LIODN to be used for Job Ring. This 61 61 property is normally set by firmware. Value 62 62 is of 12-bits which is the LIODN number for this JR. 63 63 - This property is used by the IOMMU (PAMU) to distinquish 63 63 + This property is used by the IOMMU (PAMU) to distinguish 64 64 transactions from this JR and than be able to do address 65 65 translation & protection accordingly. 66 66

+1 -1

Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt

reviewed

··· 42 42 43 43 - compatible : should be "nintendo,flipper-pic" 44 44 45 45 - 1.c) The Digital Signal Procesor (DSP) node 45 45 + 1.c) The Digital Signal Processor (DSP) node 46 46 47 47 Represents the digital signal processor interface, designed to offload 48 48 audio related tasks.

+1 -1

Documentation/devicetree/bindings/powerpc/nintendo/wii.txt

reviewed

··· 53 53 - compatible : should be "nintendo,flipper-pic" 54 54 - interrupt-controller 55 55 56 56 - 1.c) The Digital Signal Procesor (DSP) node 56 56 + 1.c) The Digital Signal Processor (DSP) node 57 57 58 58 Represents the digital signal processor interface, designed to offload 59 59 audio related tasks.

+1 -1

Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml

reviewed

··· 18 18 19 19 The IP block has a version register so this can be used for detection 20 20 instead of having to encode the IP version number in the device tree 21 21 - comaptible. 21 21 + compatible. 22 22 23 23 allOf: 24 24 - $ref: pwm.yaml#

+1 -1

Documentation/devicetree/bindings/regulator/regulator-max77620.txt

reviewed

··· 35 35 nodes is defined using the standard binding for regulators found at 36 36 <Documentation/devicetree/bindings/regulator/regulator.txt>. 37 37 38 38 - Theres are also additional properties for SD/LDOs. These additional properties 38 38 + There are also additional properties for SD/LDOs. These additional properties 39 39 are required to configure FPS configuration parameters for SDs and LDOs. 40 40 Please refer <devicetree/bindings/mfd/max77620.txt> for more detail of Flexible 41 41 Power Sequence (FPS).

+4 -4

Documentation/devicetree/bindings/regulator/regulator.yaml

reviewed

··· 126 126 127 127 regulator-oc-error-microamp: 128 128 description: Set over current error limit. This is a limit where part of 129 129 - the hardware propably is malfunctional and damage prevention is requested. 129 129 + the hardware probably is malfunctional and damage prevention is requested. 130 130 Zero can be passed to disable error detection and value '1' indicates 131 131 that detection should be enabled but limit setting can be omitted. 132 132 ··· 146 146 147 147 regulator-ov-error-microvolt: 148 148 description: Set over voltage error limit. This is a limit where part of 149 149 - the hardware propably is malfunctional and damage prevention is requested 149 149 + the hardware probably is malfunctional and damage prevention is requested 150 150 Zero can be passed to disable error detection and value '1' indicates 151 151 that detection should be enabled but limit setting can be omitted. Limit 152 152 is given as microvolt offset from voltage set to regulator. ··· 168 168 169 169 regulator-uv-error-microvolt: 170 170 description: Set under voltage error limit. This is a limit where part of 171 171 - the hardware propably is malfunctional and damage prevention is requested 171 171 + the hardware probably is malfunctional and damage prevention is requested 172 172 Zero can be passed to disable error detection and value '1' indicates 173 173 that detection should be enabled but limit setting can be omitted. Limit 174 174 is given as microvolt offset from voltage set to regulator. ··· 189 189 190 190 regulator-temp-error-kelvin: 191 191 description: Set over temperature error limit. This is a limit where part of 192 192 - the hardware propably is malfunctional and damage prevention is requested 192 192 + the hardware probably is malfunctional and damage prevention is requested 193 193 Zero can be passed to disable error detection and value '1' indicates 194 194 that detection should be enabled but limit setting can be omitted. 195 195

+1 -1

Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml

reviewed

··· 11 11 12 12 description: | 13 13 The RT5190A integrates 1 channel buck controller, 3 channels high efficiency 14 14 - synchronous buck converters, 1 LDO, I2C control interface and peripherial 14 14 + synchronous buck converters, 1 LDO, I2C control interface and peripheral 15 15 logical control. 16 16 17 17 It also supports mute AC OFF depop sound and quick setting storage while

+1 -1

Documentation/devicetree/bindings/regulator/vctrl.txt

reviewed

··· 21 21 margin from the expected value for a given control 22 22 voltage. On larger voltage decreases this can occur 23 23 undesiredly since the output voltage does not adjust 24 24 - inmediately to changes in the control voltage. To 24 24 + immediately to changes in the control voltage. To 25 25 avoid this situation the vctrl driver breaks down 26 26 larger voltage decreases into multiple steps, where 27 27 each step is within the OVP threshold.

+1 -1

Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml

reviewed

··· 102 102 caches. Each of the TCMs can be enabled or disabled independently and 103 103 either of them can be configured to appear at that R5F's address 0x0. 104 104 105 105 - The cores do not use an MMU, but has a Region Address Translater 105 105 + The cores do not use an MMU, but has a Region Address Translator 106 106 (RAT) module that is accessible only from the R5Fs for providing 107 107 translations between 32-bit CPU addresses into larger system bus 108 108 addresses. Cache and memory access settings are provided through a

+1 -1

Documentation/devicetree/bindings/reset/ti-syscon-reset.txt

reviewed

··· 43 43 Cell #6 : bit position of the reset in the 44 44 reset status register 45 45 Cell #7 : Flags used to control reset behavior, 46 46 - availible flags defined in the DT include 46 46 + available flags defined in the DT include 47 47 file <dt-bindings/reset/ti-syscon.h> 48 48 49 49 SysCon Reset Consumer Nodes

+2 -2

Documentation/devicetree/bindings/rng/omap_rng.yaml

reviewed

··· 30 30 clocks: 31 31 minItems: 1 32 32 items: 33 33 - - description: EIP150 gatable clock 34 34 - - description: Main gatable clock 33 33 + - description: EIP150 gateable clock 34 34 + - description: Main gateable clock 35 35 36 36 clock-names: 37 37 minItems: 1

+1 -1

Documentation/devicetree/bindings/rtc/rtc-cmos.txt

reviewed

··· 10 10 - ctrl-reg : Contains the initial value of the control register also 11 11 called "Register B". 12 12 - freq-reg : Contains the initial value of the frequency register also 13 13 - called "Regsiter A". 13 13 + called "Register A". 14 14 15 15 "Register A" and "B" are usually initialized by the firmware (BIOS for 16 16 instance). If this is not done, it can be performed by the driver.

+1 -1

Documentation/devicetree/bindings/serial/st-asc.txt

reviewed

··· 8 8 9 9 Optional properties: 10 10 - st,hw-flow-ctrl bool flag to enable hardware flow control. 11 11 - - st,force-m1 bool flat to force asc to be in Mode-1 recommeded 11 11 + - st,force-m1 bool flat to force asc to be in Mode-1 recommended 12 12 for high bit rates (above 19.2K) 13 13 Example: 14 14 serial@fe440000{

+1 -1

Documentation/devicetree/bindings/soc/mediatek/mediatek,mt7986-wo-ccif.yaml

reviewed

··· 12 12 13 13 description: 14 14 The MediaTek wo-ccif provides a configuration interface for WED WO 15 15 - controller used to perfrom offload rx packet processing (e.g. 802.11 15 15 + controller used to perform offload rx packet processing (e.g. 802.11 16 16 aggregation packet reordering or rx header translation) on MT7986 soc. 17 17 18 18 properties:

+1 -1

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml

reviewed

··· 12 12 description: | 13 13 PolarFire SoC devices include a microcontroller acting as the system controller, 14 14 which provides "services" to the main processor and to the FPGA fabric. These 15 15 - services include hardware rng, reprogramming of the FPGA and verfification of the 15 15 + services include hardware rng, reprogramming of the FPGA and verification of the 16 16 eNVM contents etc. More information on these services can be found online, at 17 17 https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html 18 18

+1 -1

Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml

reviewed

··· 77 77 description: 78 78 The AOSS side channel also provides the controls for three cooling devices, 79 79 these are expressed as subnodes of the QMP node. The name of the node is 80 80 - used to identify the resource and must therefor be "cx", "mx" or "ebi". 80 80 + used to identify the resource and must therefore be "cx", "mx" or "ebi". 81 81 82 82 properties: 83 83 "#cooling-cells":

+1 -1

Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt

reviewed

··· 29 29 IN2 +---o--+------------+--o---+ OUT2 30 30 loop2 relays 31 31 32 32 - The 'loop1' gpio pin controlls two relays, which are either in loop position, 32 32 + The 'loop1' gpio pin controls two relays, which are either in loop position, 33 33 meaning that input and output are directly connected, or they are in mixer 34 34 position, meaning that the signal is passed through the 'Sum' mixer. Similarly 35 35 for 'loop2'.

+1 -1

Documentation/devicetree/bindings/sound/cs35l35.txt

reviewed

··· 110 110 111 111 See Sections 4.8.2 through 4.8.4 Serial-Port Control in the Datasheet 112 112 113 113 - -cirrus,monitor-signal-format : Sub-node for the Monitor Signaling Formating 113 113 + -cirrus,monitor-signal-format : Sub-node for the Monitor Signaling Formatting 114 114 on the I2S Port. Each of the 3 8 bit values in the array contain the settings 115 115 for depth, location, and frame. 116 116

+1 -1

Documentation/devicetree/bindings/sound/cs35l36.txt

reviewed

··· 33 33 one amplifier in the system. If more than one it is best to Hi-Z the ASP 34 34 port to prevent bus contention on the output signal 35 35 36 36 - - cirrus,boost-ctl-select : Boost conerter control source selection. 36 36 + - cirrus,boost-ctl-select : Boost converter control source selection. 37 37 Selects the source of the BST_CTL target VBST voltage for the boost 38 38 converter to generate. 39 39 0x00 - Control Port Value

+1 -1

Documentation/devicetree/bindings/sound/cs53l30.txt

reviewed

··· 30 30 * frame using two different ways: 31 31 * 1) Normal I2S mode on two data pins -- each SDOUT 32 32 * carries 2-channel data in the same time. 33 33 - * 2) TDM mode on one signle data pin -- SDOUT1 carries 33 33 + * 2) TDM mode on one single data pin -- SDOUT1 carries 34 34 * 4-channel data per frame. 35 35 36 36 Example:

+1 -1

Documentation/devicetree/bindings/sound/fsl,esai.txt

reviewed

··· 44 44 - fsl,esai-synchronous: This is a boolean property. If present, indicating 45 45 that ESAI would work in the synchronous mode, which 46 46 means all the settings for Receiving would be 47 47 - duplicated from Transmition related registers. 47 47 + duplicated from Transmission related registers. 48 48 49 49 Optional properties: 50 50

+1 -1

Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml

reviewed

··· 135 135 maxItems: 16 136 136 description: 137 137 This is a list of channel IDs which should be disabled. 138 138 - By default, all data received from ETDM pins will be outputed to 138 138 + By default, all data received from ETDM pins will be outputted to 139 139 memory. etdm in supports disable_out in direct mode(w/o interconn), 140 140 so user can disable the specified channels by the property. 141 141 uniqueItems: true

+1 -1

Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt

reviewed

··· 1 1 Mediatek AFE PCM controller for mt2701 2 2 3 3 Required properties: 4 4 - - compatible: should be one of the followings. 4 4 + - compatible: should be one of the following. 5 5 - "mediatek,mt2701-audio" 6 6 - "mediatek,mt7622-audio" 7 7 - interrupts: should contain AFE and ASYS interrupts

+2 -2

Documentation/devicetree/bindings/sound/mt8195-afe-pcm.yaml

reviewed

··· 111 111 $ref: /schemas/types.yaml#/definitions/uint32 112 112 description: | 113 113 etdm modules can share the same external clock pin. Specify 114 114 - which etdm clock source is required by this etdm in moudule. 114 114 + which etdm clock source is required by this etdm in module. 115 115 enum: 116 116 - 0 # etdm1_in 117 117 - 1 # etdm2_in ··· 122 122 $ref: /schemas/types.yaml#/definitions/uint32 123 123 description: | 124 124 etdm modules can share the same external clock pin. Specify 125 125 - which etdm clock source is required by this etdm out moudule. 125 125 + which etdm clock source is required by this etdm out module. 126 126 enum: 127 127 - 0 # etdm1_in 128 128 - 1 # etdm2_in

+1 -1

Documentation/devicetree/bindings/sound/renesas,rsnd.txt

reviewed

··· 94 94 [xx]ch [yy]ch 95 95 ------> [CTU] --------> 96 96 97 97 - CTU can convert [xx]ch to [yy]ch, or exchange outputed channel. 97 97 + CTU can convert [xx]ch to [yy]ch, or exchange outputted channel. 98 98 CTU conversion needs matrix settings. 99 99 For more detail information, see below 100 100

+1 -1

Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt

reviewed

··· 12 12 source. For this driver the first string should always be 13 13 "Analog". 14 14 15 15 - Optionnal properties: 15 15 + Optional properties: 16 16 - rockchip,hp-en-gpios = The phandle of the GPIO that power up/down the 17 17 headphone (when the analog output is an headphone). 18 18 - rockchip,hp-det-gpios = The phandle of the GPIO that detects the headphone

+1 -1

Documentation/devicetree/bindings/sound/rt5663.txt

reviewed

··· 28 28 If the value is 0, it means the impedance sensing is not supported. 29 29 - "realtek,impedance_sensing_table" 30 30 The matrix rows of the impedance sensing table are consisted by impedance 31 31 - minimum, impedance maximun, volume, DC offset w/o and w/ mic of each L and 31 31 + minimum, impedance maximum, volume, DC offset w/o and w/ mic of each L and 32 32 R channel accordingly. Example is shown as following. 33 33 < 0 300 7 0xffd160 0xffd1c0 0xff8a10 0xff8ab0 34 34 301 65535 4 0xffe470 0xffe470 0xffb8e0 0xffb8e0>

+1 -1

Documentation/devicetree/bindings/sound/serial-midi.yaml

reviewed

··· 20 20 parent serial device. If the standard MIDI baud of 31.25 kBaud is needed 21 21 (as would be the case if interfacing with arbitrary external MIDI devices), 22 22 configure the clocks of the parent serial device so that a requested baud of 38.4 kBaud 23 23 - resuts in the standard MIDI baud rate, and set the 'current-speed' property to 38400 (default) 23 23 + results in the standard MIDI baud rate, and set the 'current-speed' property to 38400 (default) 24 24 25 25 properties: 26 26 compatible:

+1 -1

Documentation/devicetree/bindings/sound/sprd-pcm.txt

reviewed

··· 1 1 - * Spreadtrum DMA platfrom bindings 1 1 + * Spreadtrum DMA platform bindings 2 2 3 3 Required properties: 4 4 - compatible: Should be "sprd,pcm-platform".

+1 -1

Documentation/devicetree/bindings/sound/st,stm32-sai.yaml

reviewed

··· 63 63 additionalProperties: false 64 64 description: 65 65 Two subnodes corresponding to SAI sub-block instances A et B 66 66 - can be defined. Subnode can be omitted for unsused sub-block. 66 66 + can be defined. Subnode can be omitted for unused sub-block. 67 67 68 68 properties: 69 69 compatible:

+1 -1

Documentation/devicetree/bindings/sound/ti,j721e-cpb-ivi-audio.yaml

reviewed

··· 13 13 14 14 description: | 15 15 The Infotainment board plugs into the Common Processor Board, the support of the 16 16 - extension board is extending the CPB audio support, decribed in: 16 16 + extension board is extending the CPB audio support, described in: 17 17 sound/ti,j721e-cpb-audio.txt 18 18 19 19 The audio support on the Infotainment Expansion Board consists of McASP0

+1 -1

Documentation/devicetree/bindings/sound/ti,tas2781.yaml

reviewed

··· 29 29 reg: 30 30 description: 31 31 I2C address, in multiple tas2781s case, all the i2c address 32 32 - aggreate as one Audio Device to support multiple audio slots. 32 32 + aggregate as one Audio Device to support multiple audio slots. 33 33 maxItems: 8 34 34 minItems: 1 35 35 items:

+1 -1

Documentation/devicetree/bindings/sound/tlv320adcx140.yaml

reviewed

··· 32 32 reg: 33 33 maxItems: 1 34 34 description: | 35 35 - I2C addresss of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f 35 35 + I2C address of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f 36 36 37 37 reset-gpios: 38 38 maxItems: 1

+2 -2

Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml

reviewed

··· 159 159 qcom,ports-hstart: 160 160 $ref: /schemas/types.yaml#/definitions/uint8-array 161 161 description: 162 162 - Identifying lowerst numbered coloum in SoundWire Frame, 162 162 + Identifying lowerst numbered column in SoundWire Frame, 163 163 i.e. left edge of the Transport sub-frame for each port. 164 164 Out ports followed by In ports. 165 165 Value of 0xff indicates that this option is not implemented ··· 176 176 qcom,ports-hstop: 177 177 $ref: /schemas/types.yaml#/definitions/uint8-array 178 178 description: 179 179 - Identifying highest numbered coloum in SoundWire Frame, 179 179 + Identifying highest numbered column in SoundWire Frame, 180 180 i.e. the right edge of the Transport 181 181 sub-frame for each port. Out ports followed by In ports. 182 182 Value of 0xff indicates that this option is not implemented

+2 -2

Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt

reviewed

··· 1 1 - Broadcom BCM2835 auxiliar SPI1/2 controller 1 1 + Broadcom BCM2835 auxiliary SPI1/2 controller 2 2 3 3 The BCM2835 contains two forms of SPI master controller, one known simply as 4 4 SPI0, and the other known as the "Universal SPI Master"; part of the ··· 9 9 - reg: Should contain register location and length for the spi block 10 10 - interrupts: Should contain shared interrupt of the aux block 11 11 - clocks: The clock feeding the SPI controller - needs to 12 12 - point to the auxiliar clock driver of the bcm2835, 12 12 + point to the auxiliary clock driver of the bcm2835, 13 13 as this clock will enable the output gate for the specific 14 14 clock. 15 15 - cs-gpios: the cs-gpios (native cs is NOT supported)

+2 -2

Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml

reviewed

··· 12 12 13 13 description: | 14 14 The Broadcom SPI controller is a SPI master found on various SOCs, including 15 15 - BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits 15 15 + BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists 16 16 of: 17 17 MSPI : SPI master controller can read and write to a SPI slave device 18 18 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration ··· 20 20 io with 3-byte and 4-byte addressing support. 21 21 22 22 Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. 23 23 - MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance 23 23 + MSPI master can be used without BSPI. BRCMSTB SoCs have an additional instance 24 24 of a MSPI master without the BSPI to use with non flash slave devices that 25 25 use SPI protocol. 26 26

+1 -1

Documentation/devicetree/bindings/spi/omap-spi.yaml

reviewed

··· 68 68 dma-names: 69 69 description: 70 70 List of DMA request names. These strings correspond 1:1 with 71 71 - the DMA sepecifiers listed in dmas. The string names is to be 71 71 + the DMA specifiers listed in dmas. The string names is to be 72 72 "rxN" and "txN" for RX and TX requests, respectively. Where N 73 73 is the chip select number. 74 74 minItems: 1

+1 -1

Documentation/devicetree/bindings/timer/snps,arc-timer.txt

reviewed

··· 1 1 Synopsys ARC Local Timer with Interrupt Capabilities 2 2 - Found on all ARC CPUs (ARC700/ARCHS) 3 3 - Can be optionally programmed to interrupt on Limit 4 4 - - Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically 4 4 + - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically 5 5 TIMER0 used as clockevent provider (true for all ARC cores) 6 6 TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) 7 7

+4 -4

Documentation/devicetree/bindings/trivial-devices.yaml

reviewed

··· 193 193 - maxim,max1237 194 194 # Temperature Sensor, I2C interface 195 195 - maxim,max1619 196 196 - # 10-bit 10 kOhm linear programable voltage divider 196 196 + # 10-bit 10 kOhm linear programmable voltage divider 197 197 - maxim,max5481 198 198 - # 10-bit 50 kOhm linear programable voltage divider 198 198 + # 10-bit 50 kOhm linear programmable voltage divider 199 199 - maxim,max5482 200 200 - # 10-bit 10 kOhm linear programable variable resistor 200 200 + # 10-bit 10 kOhm linear programmable variable resistor 201 201 - maxim,max5483 202 202 - # 10-bit 50 kOhm linear programable variable resistor 202 202 + # 10-bit 50 kOhm linear programmable variable resistor 203 203 - maxim,max5484 204 204 # PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion 205 205 - maxim,max6621

+1 -1

Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml

reviewed

··· 167 167 at RTL is 0, so this property only affects siTD. 168 168 169 169 If this property is not set, the max packet size is 1023 bytes, and 170 170 - if the total of packet size for pervious transactions are more than 170 170 + if the total of packet size for previous transactions are more than 171 171 256 bytes, it can't accept any transactions within this frame. The 172 172 use case is single transaction, but higher frame rate. 173 173

+1 -1

Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml

reviewed

··· 52 52 fsl,permanently-attached: 53 53 type: boolean 54 54 description: 55 55 - Indicates if the device atached to a downstream port is 55 55 + Indicates if the device attached to a downstream port is 56 56 permanently attached. 57 57 58 58 fsl,disable-port-power-control:

+1 -1

Documentation/devicetree/bindings/usb/msm-hsusb.txt

reviewed

··· 53 53 - dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" 54 54 55 55 - switch-gpio: A phandle + gpio-specifier pair. Some boards are using Dual 56 56 - SPDT USB Switch, witch is cotrolled by GPIO to de/multiplex 56 56 + SPDT USB Switch, witch is controlled by GPIO to de/multiplex 57 57 D+/D- USB lines between connectors. 58 58 59 59 - qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device

+1 -1

Documentation/devicetree/bindings/usb/richtek,rt1719.yaml

reviewed

··· 10 10 - ChiYuan Huang <cy_huang@richtek.com> 11 11 12 12 description: | 13 13 - The RT1719 is a sink-only USB Type-C contoller that complies with the latest 13 13 + The RT1719 is a sink-only USB Type-C controller that complies with the latest 14 14 USB Type-C and PD standards. It does the USB Type-C detection including attach 15 15 and orientation. It integrates the physical layer of the USB BMC power 16 16 delivery protocol to allow up to 100W of power. The BMC PD block enables full