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drm/bridge: cdns-dsi: Wait for Clk and Data Lanes to be ready

Once the DSI Link and DSI Phy are initialized, the code needs to wait
for Clk and Data Lanes to be ready, before continuing configuration.
This is in accordance with the DSI Start-up procedure, found in the
Technical Reference Manual of Texas Instrument's J721E SoC[0] which
houses this DSI TX controller.

If the previous bridge (or crtc/encoder) are configured pre-maturely,
the input signal FIFO gets corrupt. This introduces a color-shift on the
display.

Allow the driver to wait for the clk and data lanes to get ready during
DSI enable.

[0]: See section 12.6.5.7.3 "Start-up Procedure" in J721E SoC TRM
TRM Link: http://www.ti.com/lit/pdf/spruil1

Fixes: e19233955d9e ("drm/bridge: Add Cadence DSI driver")
Cc: stable@vger.kernel.org
Tested-by: Dominik Haller <d.haller@phytec.de>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Tested-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Signed-off-by: Aradhya Bhatia <aradhya.bhatia@linux.dev>
Link: https://lore.kernel.org/r/20250329113925.68204-6-aradhya.bhatia@linux.dev
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Aradhya Bhatia and committed by
Dmitry Baryshkov 47c03e66 c6a7ef0d

+14 -1
+14 -1
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
··· 776 776 struct drm_connector *connector; 777 777 unsigned long tx_byte_period; 778 778 struct cdns_dsi_cfg dsi_cfg; 779 - u32 tmp, reg_wakeup, div; 779 + u32 tmp, reg_wakeup, div, status; 780 780 int nlanes; 781 781 782 782 if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0)) ··· 795 795 796 796 cdns_dsi_hs_init(dsi); 797 797 cdns_dsi_init_link(dsi); 798 + 799 + /* 800 + * Now that the DSI Link and DSI Phy are initialized, 801 + * wait for the CLK and Data Lanes to be ready. 802 + */ 803 + tmp = CLK_LANE_RDY; 804 + for (int i = 0; i < nlanes; i++) 805 + tmp |= DATA_LANE_RDY(i); 806 + 807 + if (readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status, 808 + (tmp == (status & tmp)), 100, 500000)) 809 + dev_err(dsi->base.dev, 810 + "Timed Out: DSI-DPhy Clock and Data Lanes not ready.\n"); 798 811 799 812 writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa), 800 813 dsi->regs + VID_HSIZE1);