Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
MIPS: Fix CONFIG_FLATMEM version of pfn_valid()
MIPS: Reorganize Cavium OCTEON PCI support.
Update Yoichi Yuasa's e-mail address
MIPS: Allow suspend and hibernation again on uniprocessor kernels.
MIPS: 64-bit: Fix o32 core dump
MIPS: BC47xx: Fix SSB irq setup
MIPS: CMP: Update sync-r4k for current kernel
MIPS: CMP: Move gcmp_probe to before the SMP ops
MIPS: CMP: activate CMP support
MIPS: CMP: Extend IPI handling to CPU number
MIPS: CMP: Extend the GIC IPI interrupts beyond 32
MIPS: Define __arch_swab64 for all mips r2 cpus
MIPS: Update VR41xx GPIO driver to use gpiolib
MIPS: Hookup new syscalls sys_rt_tgsigqueueinfo and sys_perf_counter_open.
MIPS: Malta: Remove unnecessary function prototypes
MIPS: MT: Remove unnecessary semicolons
MIPS: Add support for Texas Instruments AR7 System-on-a-Chip
+4413
-1158
+25
-4
arch/mips/Kconfig
+25
-4
arch/mips/Kconfig
···
22
22
config MACH_ALCHEMY
23
23
bool "Alchemy processor based machines"
24
24
25
+
config AR7
26
+
bool "Texas Instruments AR7"
27
+
select BOOT_ELF32
28
+
select DMA_NONCOHERENT
29
+
select CEVT_R4K
30
+
select CSRC_R4K
31
+
select IRQ_CPU
32
+
select NO_EXCEPT_FILL
33
+
select SWAP_IO_SPACE
34
+
select SYS_HAS_CPU_MIPS32_R1
35
+
select SYS_HAS_EARLY_PRINTK
36
+
select SYS_SUPPORTS_32BIT_KERNEL
37
+
select SYS_SUPPORTS_LITTLE_ENDIAN
38
+
select GENERIC_GPIO
39
+
select GCD
40
+
select VLYNQ
41
+
help
42
+
Support for the Texas Instruments AR7 System-on-a-Chip
43
+
family: TNETD7100, 7200 and 7300.
44
+
25
45
config BASLER_EXCITE
26
46
bool "Basler eXcite smart camera"
27
47
select CEVT_R4K
···
229
209
select SYS_SUPPORTS_64BIT_KERNEL
230
210
select SYS_SUPPORTS_BIG_ENDIAN
231
211
select SYS_SUPPORTS_LITTLE_ENDIAN
232
-
select SYS_SUPPORTS_MIPS_CMP if BROKEN # because SYNC_R4K is broken
212
+
select SYS_SUPPORTS_MIPS_CMP
233
213
select SYS_SUPPORTS_MULTITHREADING
234
214
select SYS_SUPPORTS_SMARTMIPS
235
215
help
···
267
247
select CEVT_R4K
268
248
select CSRC_R4K
269
249
select SYS_HAS_CPU_VR41XX
250
+
select ARCH_REQUIRE_GPIOLIB
270
251
271
252
config NXP_STB220
272
253
bool "NXP STB220 board"
···
1656
1635
config MIPS_CMP
1657
1636
bool "MIPS CMP framework support"
1658
1637
depends on SYS_SUPPORTS_MIPS_CMP
1659
-
select SYNC_R4K if BROKEN
1638
+
select SYNC_R4K
1660
1639
select SYS_SUPPORTS_SMP
1661
1640
select SYS_SUPPORTS_SCHED_SMT if SMP
1662
1641
select WEAK_ORDERING
···
2168
2147
2169
2148
config ARCH_HIBERNATION_POSSIBLE
2170
2149
def_bool y
2171
-
depends on SYS_SUPPORTS_HOTPLUG_CPU
2150
+
depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2172
2151
2173
2152
config ARCH_SUSPEND_POSSIBLE
2174
2153
def_bool y
2175
-
depends on SYS_SUPPORTS_HOTPLUG_CPU
2154
+
depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2176
2155
2177
2156
source "kernel/power/Kconfig"
2178
2157
+7
arch/mips/Makefile
+7
arch/mips/Makefile
···
173
173
#
174
174
175
175
#
176
+
# Texas Instruments AR7
177
+
#
178
+
core-$(CONFIG_AR7) += arch/mips/ar7/
179
+
cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7
180
+
load-$(CONFIG_AR7) += 0xffffffff94100000
181
+
182
+
#
176
183
# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
177
184
#
178
185
core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
+10
arch/mips/ar7/Makefile
+10
arch/mips/ar7/Makefile
+440
arch/mips/ar7/clock.c
+440
arch/mips/ar7/clock.c
···
1
+
/*
2
+
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
3
+
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License as published by
7
+
* the Free Software Foundation; either version 2 of the License, or
8
+
* (at your option) any later version.
9
+
*
10
+
* This program is distributed in the hope that it will be useful,
11
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
12
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13
+
* GNU General Public License for more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License
16
+
* along with this program; if not, write to the Free Software
17
+
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18
+
*/
19
+
20
+
#include <linux/kernel.h>
21
+
#include <linux/init.h>
22
+
#include <linux/types.h>
23
+
#include <linux/module.h>
24
+
#include <linux/delay.h>
25
+
#include <linux/gcd.h>
26
+
#include <linux/io.h>
27
+
28
+
#include <asm/addrspace.h>
29
+
#include <asm/mach-ar7/ar7.h>
30
+
31
+
#define BOOT_PLL_SOURCE_MASK 0x3
32
+
#define CPU_PLL_SOURCE_SHIFT 16
33
+
#define BUS_PLL_SOURCE_SHIFT 14
34
+
#define USB_PLL_SOURCE_SHIFT 18
35
+
#define DSP_PLL_SOURCE_SHIFT 22
36
+
#define BOOT_PLL_SOURCE_AFE 0
37
+
#define BOOT_PLL_SOURCE_BUS 0
38
+
#define BOOT_PLL_SOURCE_REF 1
39
+
#define BOOT_PLL_SOURCE_XTAL 2
40
+
#define BOOT_PLL_SOURCE_CPU 3
41
+
#define BOOT_PLL_BYPASS 0x00000020
42
+
#define BOOT_PLL_ASYNC_MODE 0x02000000
43
+
#define BOOT_PLL_2TO1_MODE 0x00008000
44
+
45
+
#define TNETD7200_CLOCK_ID_CPU 0
46
+
#define TNETD7200_CLOCK_ID_DSP 1
47
+
#define TNETD7200_CLOCK_ID_USB 2
48
+
49
+
#define TNETD7200_DEF_CPU_CLK 211000000
50
+
#define TNETD7200_DEF_DSP_CLK 125000000
51
+
#define TNETD7200_DEF_USB_CLK 48000000
52
+
53
+
struct tnetd7300_clock {
54
+
u32 ctrl;
55
+
#define PREDIV_MASK 0x001f0000
56
+
#define PREDIV_SHIFT 16
57
+
#define POSTDIV_MASK 0x0000001f
58
+
u32 unused1[3];
59
+
u32 pll;
60
+
#define MUL_MASK 0x0000f000
61
+
#define MUL_SHIFT 12
62
+
#define PLL_MODE_MASK 0x00000001
63
+
#define PLL_NDIV 0x00000800
64
+
#define PLL_DIV 0x00000002
65
+
#define PLL_STATUS 0x00000001
66
+
u32 unused2[3];
67
+
};
68
+
69
+
struct tnetd7300_clocks {
70
+
struct tnetd7300_clock bus;
71
+
struct tnetd7300_clock cpu;
72
+
struct tnetd7300_clock usb;
73
+
struct tnetd7300_clock dsp;
74
+
};
75
+
76
+
struct tnetd7200_clock {
77
+
u32 ctrl;
78
+
u32 unused1[3];
79
+
#define DIVISOR_ENABLE_MASK 0x00008000
80
+
u32 mul;
81
+
u32 prediv;
82
+
u32 postdiv;
83
+
u32 postdiv2;
84
+
u32 unused2[6];
85
+
u32 cmd;
86
+
u32 status;
87
+
u32 cmden;
88
+
u32 padding[15];
89
+
};
90
+
91
+
struct tnetd7200_clocks {
92
+
struct tnetd7200_clock cpu;
93
+
struct tnetd7200_clock dsp;
94
+
struct tnetd7200_clock usb;
95
+
};
96
+
97
+
int ar7_cpu_clock = 150000000;
98
+
EXPORT_SYMBOL(ar7_cpu_clock);
99
+
int ar7_bus_clock = 125000000;
100
+
EXPORT_SYMBOL(ar7_bus_clock);
101
+
int ar7_dsp_clock;
102
+
EXPORT_SYMBOL(ar7_dsp_clock);
103
+
104
+
static void approximate(int base, int target, int *prediv,
105
+
int *postdiv, int *mul)
106
+
{
107
+
int i, j, k, freq, res = target;
108
+
for (i = 1; i <= 16; i++)
109
+
for (j = 1; j <= 32; j++)
110
+
for (k = 1; k <= 32; k++) {
111
+
freq = abs(base / j * i / k - target);
112
+
if (freq < res) {
113
+
res = freq;
114
+
*mul = i;
115
+
*prediv = j;
116
+
*postdiv = k;
117
+
}
118
+
}
119
+
}
120
+
121
+
static void calculate(int base, int target, int *prediv, int *postdiv,
122
+
int *mul)
123
+
{
124
+
int tmp_gcd, tmp_base, tmp_freq;
125
+
126
+
for (*prediv = 1; *prediv <= 32; (*prediv)++) {
127
+
tmp_base = base / *prediv;
128
+
tmp_gcd = gcd(target, tmp_base);
129
+
*mul = target / tmp_gcd;
130
+
*postdiv = tmp_base / tmp_gcd;
131
+
if ((*mul < 1) || (*mul >= 16))
132
+
continue;
133
+
if ((*postdiv > 0) & (*postdiv <= 32))
134
+
break;
135
+
}
136
+
137
+
if (base / *prediv * *mul / *postdiv != target) {
138
+
approximate(base, target, prediv, postdiv, mul);
139
+
tmp_freq = base / *prediv * *mul / *postdiv;
140
+
printk(KERN_WARNING
141
+
"Adjusted requested frequency %d to %d\n",
142
+
target, tmp_freq);
143
+
}
144
+
145
+
printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
146
+
*prediv, *postdiv, *mul);
147
+
}
148
+
149
+
static int tnetd7300_dsp_clock(void)
150
+
{
151
+
u32 didr1, didr2;
152
+
u8 rev = ar7_chip_rev();
153
+
didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
154
+
didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
155
+
if (didr2 & (1 << 23))
156
+
return 0;
157
+
if ((rev >= 0x23) && (rev != 0x57))
158
+
return 250000000;
159
+
if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
160
+
> 4208000)
161
+
return 250000000;
162
+
return 0;
163
+
}
164
+
165
+
static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
166
+
u32 *bootcr, u32 bus_clock)
167
+
{
168
+
int product;
169
+
int base_clock = AR7_REF_CLOCK;
170
+
u32 ctrl = readl(&clock->ctrl);
171
+
u32 pll = readl(&clock->pll);
172
+
int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
173
+
int postdiv = (ctrl & POSTDIV_MASK) + 1;
174
+
int divisor = prediv * postdiv;
175
+
int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
176
+
177
+
switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
178
+
case BOOT_PLL_SOURCE_BUS:
179
+
base_clock = bus_clock;
180
+
break;
181
+
case BOOT_PLL_SOURCE_REF:
182
+
base_clock = AR7_REF_CLOCK;
183
+
break;
184
+
case BOOT_PLL_SOURCE_XTAL:
185
+
base_clock = AR7_XTAL_CLOCK;
186
+
break;
187
+
case BOOT_PLL_SOURCE_CPU:
188
+
base_clock = ar7_cpu_clock;
189
+
break;
190
+
}
191
+
192
+
if (*bootcr & BOOT_PLL_BYPASS)
193
+
return base_clock / divisor;
194
+
195
+
if ((pll & PLL_MODE_MASK) == 0)
196
+
return (base_clock >> (mul / 16 + 1)) / divisor;
197
+
198
+
if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
199
+
product = (mul & 1) ?
200
+
(base_clock * mul) >> 1 :
201
+
(base_clock * (mul - 1)) >> 2;
202
+
return product / divisor;
203
+
}
204
+
205
+
if (mul == 16)
206
+
return base_clock / divisor;
207
+
208
+
return base_clock * mul / divisor;
209
+
}
210
+
211
+
static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
212
+
u32 *bootcr, u32 frequency)
213
+
{
214
+
int prediv, postdiv, mul;
215
+
int base_clock = ar7_bus_clock;
216
+
217
+
switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
218
+
case BOOT_PLL_SOURCE_BUS:
219
+
base_clock = ar7_bus_clock;
220
+
break;
221
+
case BOOT_PLL_SOURCE_REF:
222
+
base_clock = AR7_REF_CLOCK;
223
+
break;
224
+
case BOOT_PLL_SOURCE_XTAL:
225
+
base_clock = AR7_XTAL_CLOCK;
226
+
break;
227
+
case BOOT_PLL_SOURCE_CPU:
228
+
base_clock = ar7_cpu_clock;
229
+
break;
230
+
}
231
+
232
+
calculate(base_clock, frequency, &prediv, &postdiv, &mul);
233
+
234
+
writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
235
+
msleep(1);
236
+
writel(4, &clock->pll);
237
+
while (readl(&clock->pll) & PLL_STATUS)
238
+
;
239
+
writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
240
+
msleep(75);
241
+
}
242
+
243
+
static void __init tnetd7300_init_clocks(void)
244
+
{
245
+
u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
246
+
struct tnetd7300_clocks *clocks =
247
+
ioremap_nocache(UR8_REGS_CLOCKS,
248
+
sizeof(struct tnetd7300_clocks));
249
+
250
+
ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
251
+
&clocks->bus, bootcr, AR7_AFE_CLOCK);
252
+
253
+
if (*bootcr & BOOT_PLL_ASYNC_MODE)
254
+
ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
255
+
&clocks->cpu, bootcr, AR7_AFE_CLOCK);
256
+
else
257
+
ar7_cpu_clock = ar7_bus_clock;
258
+
259
+
if (ar7_dsp_clock == 250000000)
260
+
tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
261
+
bootcr, ar7_dsp_clock);
262
+
263
+
iounmap(clocks);
264
+
iounmap(bootcr);
265
+
}
266
+
267
+
static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
268
+
u32 *bootcr, u32 bus_clock)
269
+
{
270
+
int divisor = ((readl(&clock->prediv) & 0x1f) + 1) *
271
+
((readl(&clock->postdiv) & 0x1f) + 1);
272
+
273
+
if (*bootcr & BOOT_PLL_BYPASS)
274
+
return base / divisor;
275
+
276
+
return base * ((readl(&clock->mul) & 0xf) + 1) / divisor;
277
+
}
278
+
279
+
280
+
static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
281
+
int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
282
+
{
283
+
printk(KERN_INFO
284
+
"Clocks: base = %d, frequency = %u, prediv = %d, "
285
+
"postdiv = %d, postdiv2 = %d, mul = %d\n",
286
+
base, frequency, prediv, postdiv, postdiv2, mul);
287
+
288
+
writel(0, &clock->ctrl);
289
+
writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);
290
+
writel((mul - 1) & 0xF, &clock->mul);
291
+
292
+
while (readl(&clock->status) & 0x1)
293
+
; /* nop */
294
+
295
+
writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);
296
+
297
+
writel(readl(&clock->cmden) | 1, &clock->cmden);
298
+
writel(readl(&clock->cmd) | 1, &clock->cmd);
299
+
300
+
while (readl(&clock->status) & 0x1)
301
+
; /* nop */
302
+
303
+
writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
304
+
305
+
writel(readl(&clock->cmden) | 1, &clock->cmden);
306
+
writel(readl(&clock->cmd) | 1, &clock->cmd);
307
+
308
+
while (readl(&clock->status) & 0x1)
309
+
; /* nop */
310
+
311
+
writel(readl(&clock->ctrl) | 1, &clock->ctrl);
312
+
}
313
+
314
+
static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
315
+
{
316
+
if (*bootcr & BOOT_PLL_ASYNC_MODE)
317
+
/* Async */
318
+
switch (clock_id) {
319
+
case TNETD7200_CLOCK_ID_DSP:
320
+
return AR7_REF_CLOCK;
321
+
default:
322
+
return AR7_AFE_CLOCK;
323
+
}
324
+
else
325
+
/* Sync */
326
+
if (*bootcr & BOOT_PLL_2TO1_MODE)
327
+
/* 2:1 */
328
+
switch (clock_id) {
329
+
case TNETD7200_CLOCK_ID_DSP:
330
+
return AR7_REF_CLOCK;
331
+
default:
332
+
return AR7_AFE_CLOCK;
333
+
}
334
+
else
335
+
/* 1:1 */
336
+
return AR7_REF_CLOCK;
337
+
}
338
+
339
+
340
+
static void __init tnetd7200_init_clocks(void)
341
+
{
342
+
u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
343
+
struct tnetd7200_clocks *clocks =
344
+
ioremap_nocache(AR7_REGS_CLOCKS,
345
+
sizeof(struct tnetd7200_clocks));
346
+
int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
347
+
int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
348
+
int usb_base, usb_mul, usb_prediv, usb_postdiv;
349
+
350
+
cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
351
+
dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
352
+
353
+
if (*bootcr & BOOT_PLL_ASYNC_MODE) {
354
+
printk(KERN_INFO "Clocks: Async mode\n");
355
+
356
+
printk(KERN_INFO "Clocks: Setting DSP clock\n");
357
+
calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
358
+
&dsp_prediv, &dsp_postdiv, &dsp_mul);
359
+
ar7_bus_clock =
360
+
((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
361
+
tnetd7200_set_clock(dsp_base, &clocks->dsp,
362
+
dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
363
+
ar7_bus_clock);
364
+
365
+
printk(KERN_INFO "Clocks: Setting CPU clock\n");
366
+
calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
367
+
&cpu_postdiv, &cpu_mul);
368
+
ar7_cpu_clock =
369
+
((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
370
+
tnetd7200_set_clock(cpu_base, &clocks->cpu,
371
+
cpu_prediv, cpu_postdiv, -1, cpu_mul,
372
+
ar7_cpu_clock);
373
+
374
+
} else
375
+
if (*bootcr & BOOT_PLL_2TO1_MODE) {
376
+
printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
377
+
378
+
printk(KERN_INFO "Clocks: Setting CPU clock\n");
379
+
calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
380
+
&cpu_postdiv, &cpu_mul);
381
+
ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul)
382
+
/ cpu_postdiv;
383
+
tnetd7200_set_clock(cpu_base, &clocks->cpu,
384
+
cpu_prediv, cpu_postdiv, -1, cpu_mul,
385
+
ar7_cpu_clock);
386
+
387
+
printk(KERN_INFO "Clocks: Setting DSP clock\n");
388
+
calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
389
+
&dsp_postdiv, &dsp_mul);
390
+
ar7_bus_clock = ar7_cpu_clock / 2;
391
+
tnetd7200_set_clock(dsp_base, &clocks->dsp,
392
+
dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
393
+
dsp_mul * 2, ar7_bus_clock);
394
+
} else {
395
+
printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
396
+
397
+
printk(KERN_INFO "Clocks: Setting DSP clock\n");
398
+
calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
399
+
&dsp_postdiv, &dsp_mul);
400
+
ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul)
401
+
/ dsp_postdiv;
402
+
tnetd7200_set_clock(dsp_base, &clocks->dsp,
403
+
dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
404
+
dsp_mul * 2, ar7_bus_clock);
405
+
406
+
ar7_cpu_clock = ar7_bus_clock;
407
+
}
408
+
409
+
printk(KERN_INFO "Clocks: Setting USB clock\n");
410
+
usb_base = ar7_bus_clock;
411
+
calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
412
+
&usb_postdiv, &usb_mul);
413
+
tnetd7200_set_clock(usb_base, &clocks->usb,
414
+
usb_prediv, usb_postdiv, -1, usb_mul,
415
+
TNETD7200_DEF_USB_CLK);
416
+
417
+
ar7_dsp_clock = ar7_cpu_clock;
418
+
419
+
iounmap(clocks);
420
+
iounmap(bootcr);
421
+
}
422
+
423
+
int __init ar7_init_clocks(void)
424
+
{
425
+
switch (ar7_chip_id()) {
426
+
case AR7_CHIP_7100:
427
+
case AR7_CHIP_7200:
428
+
tnetd7200_init_clocks();
429
+
break;
430
+
case AR7_CHIP_7300:
431
+
ar7_dsp_clock = tnetd7300_dsp_clock();
432
+
tnetd7300_init_clocks();
433
+
break;
434
+
default:
435
+
break;
436
+
}
437
+
438
+
return 0;
439
+
}
440
+
arch_initcall(ar7_init_clocks);
+48
arch/mips/ar7/gpio.c
+48
arch/mips/ar7/gpio.c
···
1
+
/*
2
+
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
3
+
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License as published by
7
+
* the Free Software Foundation; either version 2 of the License, or
8
+
* (at your option) any later version.
9
+
*
10
+
* This program is distributed in the hope that it will be useful,
11
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
12
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13
+
* GNU General Public License for more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License
16
+
* along with this program; if not, write to the Free Software
17
+
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18
+
*/
19
+
20
+
#include <linux/module.h>
21
+
22
+
#include <asm/mach-ar7/gpio.h>
23
+
24
+
static const char *ar7_gpio_list[AR7_GPIO_MAX];
25
+
26
+
int gpio_request(unsigned gpio, const char *label)
27
+
{
28
+
if (gpio >= AR7_GPIO_MAX)
29
+
return -EINVAL;
30
+
31
+
if (ar7_gpio_list[gpio])
32
+
return -EBUSY;
33
+
34
+
if (label)
35
+
ar7_gpio_list[gpio] = label;
36
+
else
37
+
ar7_gpio_list[gpio] = "busy";
38
+
39
+
return 0;
40
+
}
41
+
EXPORT_SYMBOL(gpio_request);
42
+
43
+
void gpio_free(unsigned gpio)
44
+
{
45
+
BUG_ON(!ar7_gpio_list[gpio]);
46
+
ar7_gpio_list[gpio] = NULL;
47
+
}
48
+
EXPORT_SYMBOL(gpio_free);
+176
arch/mips/ar7/irq.c
+176
arch/mips/ar7/irq.c
···
1
+
/*
2
+
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
3
+
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License as published by
7
+
* the Free Software Foundation; either version 2 of the License, or
8
+
* (at your option) any later version.
9
+
*
10
+
* This program is distributed in the hope that it will be useful,
11
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
12
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13
+
* GNU General Public License for more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License
16
+
* along with this program; if not, write to the Free Software
17
+
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18
+
*/
19
+
20
+
#include <linux/interrupt.h>
21
+
#include <linux/io.h>
22
+
23
+
#include <asm/irq_cpu.h>
24
+
#include <asm/mipsregs.h>
25
+
#include <asm/mach-ar7/ar7.h>
26
+
27
+
#define EXCEPT_OFFSET 0x80
28
+
#define PACE_OFFSET 0xA0
29
+
#define CHNLS_OFFSET 0x200
30
+
31
+
#define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
32
+
#define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
33
+
#define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
34
+
#define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
35
+
#define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
36
+
#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
37
+
#define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
38
+
#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
39
+
#define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
40
+
#define PIR_OFFSET (0x40)
41
+
#define MSR_OFFSET (0x44)
42
+
#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
43
+
#define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
44
+
45
+
#define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
46
+
47
+
#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
48
+
49
+
static int ar7_irq_base;
50
+
51
+
static void ar7_unmask_irq(unsigned int irq)
52
+
{
53
+
writel(1 << ((irq - ar7_irq_base) % 32),
54
+
REG(ESR_OFFSET(irq - ar7_irq_base)));
55
+
}
56
+
57
+
static void ar7_mask_irq(unsigned int irq)
58
+
{
59
+
writel(1 << ((irq - ar7_irq_base) % 32),
60
+
REG(ECR_OFFSET(irq - ar7_irq_base)));
61
+
}
62
+
63
+
static void ar7_ack_irq(unsigned int irq)
64
+
{
65
+
writel(1 << ((irq - ar7_irq_base) % 32),
66
+
REG(CR_OFFSET(irq - ar7_irq_base)));
67
+
}
68
+
69
+
static void ar7_unmask_sec_irq(unsigned int irq)
70
+
{
71
+
writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
72
+
}
73
+
74
+
static void ar7_mask_sec_irq(unsigned int irq)
75
+
{
76
+
writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
77
+
}
78
+
79
+
static void ar7_ack_sec_irq(unsigned int irq)
80
+
{
81
+
writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
82
+
}
83
+
84
+
static struct irq_chip ar7_irq_type = {
85
+
.name = "AR7",
86
+
.unmask = ar7_unmask_irq,
87
+
.mask = ar7_mask_irq,
88
+
.ack = ar7_ack_irq
89
+
};
90
+
91
+
static struct irq_chip ar7_sec_irq_type = {
92
+
.name = "AR7",
93
+
.unmask = ar7_unmask_sec_irq,
94
+
.mask = ar7_mask_sec_irq,
95
+
.ack = ar7_ack_sec_irq,
96
+
};
97
+
98
+
static struct irqaction ar7_cascade_action = {
99
+
.handler = no_action,
100
+
.name = "AR7 cascade interrupt"
101
+
};
102
+
103
+
static void __init ar7_irq_init(int base)
104
+
{
105
+
int i;
106
+
/*
107
+
* Disable interrupts and clear pending
108
+
*/
109
+
writel(0xffffffff, REG(ECR_OFFSET(0)));
110
+
writel(0xff, REG(ECR_OFFSET(32)));
111
+
writel(0xffffffff, REG(SEC_ECR_OFFSET));
112
+
writel(0xffffffff, REG(CR_OFFSET(0)));
113
+
writel(0xff, REG(CR_OFFSET(32)));
114
+
writel(0xffffffff, REG(SEC_CR_OFFSET));
115
+
116
+
ar7_irq_base = base;
117
+
118
+
for (i = 0; i < 40; i++) {
119
+
writel(i, REG(CHNL_OFFSET(i)));
120
+
/* Primary IRQ's */
121
+
set_irq_chip_and_handler(base + i, &ar7_irq_type,
122
+
handle_level_irq);
123
+
/* Secondary IRQ's */
124
+
if (i < 32)
125
+
set_irq_chip_and_handler(base + i + 40,
126
+
&ar7_sec_irq_type,
127
+
handle_level_irq);
128
+
}
129
+
130
+
setup_irq(2, &ar7_cascade_action);
131
+
setup_irq(ar7_irq_base, &ar7_cascade_action);
132
+
set_c0_status(IE_IRQ0);
133
+
}
134
+
135
+
void __init arch_init_irq(void)
136
+
{
137
+
mips_cpu_irq_init();
138
+
ar7_irq_init(8);
139
+
}
140
+
141
+
static void ar7_cascade(void)
142
+
{
143
+
u32 status;
144
+
int i, irq;
145
+
146
+
/* Primary IRQ's */
147
+
irq = readl(REG(PIR_OFFSET)) & 0x3f;
148
+
if (irq) {
149
+
do_IRQ(ar7_irq_base + irq);
150
+
return;
151
+
}
152
+
153
+
/* Secondary IRQ's are cascaded through primary '0' */
154
+
writel(1, REG(CR_OFFSET(irq)));
155
+
status = readl(REG(SEC_SR_OFFSET));
156
+
for (i = 0; i < 32; i++) {
157
+
if (status & 1) {
158
+
do_IRQ(ar7_irq_base + i + 40);
159
+
return;
160
+
}
161
+
status >>= 1;
162
+
}
163
+
164
+
spurious_interrupt();
165
+
}
166
+
167
+
asmlinkage void plat_irq_dispatch(void)
168
+
{
169
+
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
170
+
if (pending & STATUSF_IP7) /* cpu timer */
171
+
do_IRQ(7);
172
+
else if (pending & STATUSF_IP2) /* int0 hardware line */
173
+
ar7_cascade();
174
+
else
175
+
spurious_interrupt();
176
+
}
+72
arch/mips/ar7/memory.c
+72
arch/mips/ar7/memory.c
···
1
+
/*
2
+
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
3
+
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License as published by
7
+
* the Free Software Foundation; either version 2 of the License, or
8
+
* (at your option) any later version.
9
+
*
10
+
* This program is distributed in the hope that it will be useful,
11
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
12
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13
+
* GNU General Public License for more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License
16
+
* along with this program; if not, write to the Free Software
17
+
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18
+
*/
19
+
#include <linux/bootmem.h>
20
+
#include <linux/init.h>
21
+
#include <linux/mm.h>
22
+
#include <linux/module.h>
23
+
#include <linux/pfn.h>
24
+
#include <linux/proc_fs.h>
25
+
#include <linux/string.h>
26
+
#include <linux/swap.h>
27
+
28
+
#include <asm/bootinfo.h>
29
+
#include <asm/page.h>
30
+
#include <asm/sections.h>
31
+
32
+
#include <asm/mach-ar7/ar7.h>
33
+
#include <asm/mips-boards/prom.h>
34
+
35
+
static int __init memsize(void)
36
+
{
37
+
u32 size = (64 << 20);
38
+
u32 *addr = (u32 *)KSEG1ADDR(AR7_SDRAM_BASE + size - 4);
39
+
u32 *kernel_end = (u32 *)KSEG1ADDR(CPHYSADDR((u32)&_end));
40
+
u32 *tmpaddr = addr;
41
+
42
+
while (tmpaddr > kernel_end) {
43
+
*tmpaddr = (u32)tmpaddr;
44
+
size >>= 1;
45
+
tmpaddr -= size >> 2;
46
+
}
47
+
48
+
do {
49
+
tmpaddr += size >> 2;
50
+
if (*tmpaddr != (u32)tmpaddr)
51
+
break;
52
+
size <<= 1;
53
+
} while (size < (64 << 20));
54
+
55
+
writel(tmpaddr, &addr);
56
+
57
+
return size;
58
+
}
59
+
60
+
void __init prom_meminit(void)
61
+
{
62
+
unsigned long pages;
63
+
64
+
pages = memsize() >> PAGE_SHIFT;
65
+
add_memory_region(PHYS_OFFSET, pages << PAGE_SHIFT,
66
+
BOOT_MEM_RAM);
67
+
}
68
+
69
+
void __init prom_free_prom_memory(void)
70
+
{
71
+
/* Nothing to free */
72
+
}
+555
arch/mips/ar7/platform.c
+555
arch/mips/ar7/platform.c
···
1
+
/*
2
+
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
3
+
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License as published by
7
+
* the Free Software Foundation; either version 2 of the License, or
8
+
* (at your option) any later version.
9
+
*
10
+
* This program is distributed in the hope that it will be useful,
11
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
12
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13
+
* GNU General Public License for more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License
16
+
* along with this program; if not, write to the Free Software
17
+
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18
+
*/
19
+
20
+
#include <linux/init.h>
21
+
#include <linux/types.h>
22
+
#include <linux/module.h>
23
+
#include <linux/delay.h>
24
+
#include <linux/dma-mapping.h>
25
+
#include <linux/platform_device.h>
26
+
#include <linux/mtd/physmap.h>
27
+
#include <linux/serial.h>
28
+
#include <linux/serial_8250.h>
29
+
#include <linux/ioport.h>
30
+
#include <linux/io.h>
31
+
#include <linux/version.h>
32
+
#include <linux/vlynq.h>
33
+
#include <linux/leds.h>
34
+
#include <linux/string.h>
35
+
#include <linux/etherdevice.h>
36
+
37
+
#include <asm/addrspace.h>
38
+
#include <asm/mach-ar7/ar7.h>
39
+
#include <asm/mach-ar7/gpio.h>
40
+
#include <asm/mach-ar7/prom.h>
41
+
42
+
struct plat_vlynq_data {
43
+
struct plat_vlynq_ops ops;
44
+
int gpio_bit;
45
+
int reset_bit;
46
+
};
47
+
48
+
49
+
static int vlynq_on(struct vlynq_device *dev)
50
+
{
51
+
int result;
52
+
struct plat_vlynq_data *pdata = dev->dev.platform_data;
53
+
54
+
result = gpio_request(pdata->gpio_bit, "vlynq");
55
+
if (result)
56
+
goto out;
57
+
58
+
ar7_device_reset(pdata->reset_bit);
59
+
60
+
result = ar7_gpio_disable(pdata->gpio_bit);
61
+
if (result)
62
+
goto out_enabled;
63
+
64
+
result = ar7_gpio_enable(pdata->gpio_bit);
65
+
if (result)
66
+
goto out_enabled;
67
+
68
+
result = gpio_direction_output(pdata->gpio_bit, 0);
69
+
if (result)
70
+
goto out_gpio_enabled;
71
+
72
+
msleep(50);
73
+
74
+
gpio_set_value(pdata->gpio_bit, 1);
75
+
msleep(50);
76
+
77
+
return 0;
78
+
79
+
out_gpio_enabled:
80
+
ar7_gpio_disable(pdata->gpio_bit);
81
+
out_enabled:
82
+
ar7_device_disable(pdata->reset_bit);
83
+
gpio_free(pdata->gpio_bit);
84
+
out:
85
+
return result;
86
+
}
87
+
88
+
static void vlynq_off(struct vlynq_device *dev)
89
+
{
90
+
struct plat_vlynq_data *pdata = dev->dev.platform_data;
91
+
ar7_gpio_disable(pdata->gpio_bit);
92
+
gpio_free(pdata->gpio_bit);
93
+
ar7_device_disable(pdata->reset_bit);
94
+
}
95
+
96
+
static struct resource physmap_flash_resource = {
97
+
.name = "mem",
98
+
.flags = IORESOURCE_MEM,
99
+
.start = 0x10000000,
100
+
.end = 0x107fffff,
101
+
};
102
+
103
+
static struct resource cpmac_low_res[] = {
104
+
{
105
+
.name = "regs",
106
+
.flags = IORESOURCE_MEM,
107
+
.start = AR7_REGS_MAC0,
108
+
.end = AR7_REGS_MAC0 + 0x7ff,
109
+
},
110
+
{
111
+
.name = "irq",
112
+
.flags = IORESOURCE_IRQ,
113
+
.start = 27,
114
+
.end = 27,
115
+
},
116
+
};
117
+
118
+
static struct resource cpmac_high_res[] = {
119
+
{
120
+
.name = "regs",
121
+
.flags = IORESOURCE_MEM,
122
+
.start = AR7_REGS_MAC1,
123
+
.end = AR7_REGS_MAC1 + 0x7ff,
124
+
},
125
+
{
126
+
.name = "irq",
127
+
.flags = IORESOURCE_IRQ,
128
+
.start = 41,
129
+
.end = 41,
130
+
},
131
+
};
132
+
133
+
static struct resource vlynq_low_res[] = {
134
+
{
135
+
.name = "regs",
136
+
.flags = IORESOURCE_MEM,
137
+
.start = AR7_REGS_VLYNQ0,
138
+
.end = AR7_REGS_VLYNQ0 + 0xff,
139
+
},
140
+
{
141
+
.name = "irq",
142
+
.flags = IORESOURCE_IRQ,
143
+
.start = 29,
144
+
.end = 29,
145
+
},
146
+
{
147
+
.name = "mem",
148
+
.flags = IORESOURCE_MEM,
149
+
.start = 0x04000000,
150
+
.end = 0x04ffffff,
151
+
},
152
+
{
153
+
.name = "devirq",
154
+
.flags = IORESOURCE_IRQ,
155
+
.start = 80,
156
+
.end = 111,
157
+
},
158
+
};
159
+
160
+
static struct resource vlynq_high_res[] = {
161
+
{
162
+
.name = "regs",
163
+
.flags = IORESOURCE_MEM,
164
+
.start = AR7_REGS_VLYNQ1,
165
+
.end = AR7_REGS_VLYNQ1 + 0xff,
166
+
},
167
+
{
168
+
.name = "irq",
169
+
.flags = IORESOURCE_IRQ,
170
+
.start = 33,
171
+
.end = 33,
172
+
},
173
+
{
174
+
.name = "mem",
175
+
.flags = IORESOURCE_MEM,
176
+
.start = 0x0c000000,
177
+
.end = 0x0cffffff,
178
+
},
179
+
{
180
+
.name = "devirq",
181
+
.flags = IORESOURCE_IRQ,
182
+
.start = 112,
183
+
.end = 143,
184
+
},
185
+
};
186
+
187
+
static struct resource usb_res[] = {
188
+
{
189
+
.name = "regs",
190
+
.flags = IORESOURCE_MEM,
191
+
.start = AR7_REGS_USB,
192
+
.end = AR7_REGS_USB + 0xff,
193
+
},
194
+
{
195
+
.name = "irq",
196
+
.flags = IORESOURCE_IRQ,
197
+
.start = 32,
198
+
.end = 32,
199
+
},
200
+
{
201
+
.name = "mem",
202
+
.flags = IORESOURCE_MEM,
203
+
.start = 0x03400000,
204
+
.end = 0x034001fff,
205
+
},
206
+
};
207
+
208
+
static struct physmap_flash_data physmap_flash_data = {
209
+
.width = 2,
210
+
};
211
+
212
+
static struct plat_cpmac_data cpmac_low_data = {
213
+
.reset_bit = 17,
214
+
.power_bit = 20,
215
+
.phy_mask = 0x80000000,
216
+
};
217
+
218
+
static struct plat_cpmac_data cpmac_high_data = {
219
+
.reset_bit = 21,
220
+
.power_bit = 22,
221
+
.phy_mask = 0x7fffffff,
222
+
};
223
+
224
+
static struct plat_vlynq_data vlynq_low_data = {
225
+
.ops.on = vlynq_on,
226
+
.ops.off = vlynq_off,
227
+
.reset_bit = 20,
228
+
.gpio_bit = 18,
229
+
};
230
+
231
+
static struct plat_vlynq_data vlynq_high_data = {
232
+
.ops.on = vlynq_on,
233
+
.ops.off = vlynq_off,
234
+
.reset_bit = 16,
235
+
.gpio_bit = 19,
236
+
};
237
+
238
+
static struct platform_device physmap_flash = {
239
+
.id = 0,
240
+
.name = "physmap-flash",
241
+
.dev.platform_data = &physmap_flash_data,
242
+
.resource = &physmap_flash_resource,
243
+
.num_resources = 1,
244
+
};
245
+
246
+
static u64 cpmac_dma_mask = DMA_32BIT_MASK;
247
+
static struct platform_device cpmac_low = {
248
+
.id = 0,
249
+
.name = "cpmac",
250
+
.dev = {
251
+
.dma_mask = &cpmac_dma_mask,
252
+
.coherent_dma_mask = DMA_32BIT_MASK,
253
+
.platform_data = &cpmac_low_data,
254
+
},
255
+
.resource = cpmac_low_res,
256
+
.num_resources = ARRAY_SIZE(cpmac_low_res),
257
+
};
258
+
259
+
static struct platform_device cpmac_high = {
260
+
.id = 1,
261
+
.name = "cpmac",
262
+
.dev = {
263
+
.dma_mask = &cpmac_dma_mask,
264
+
.coherent_dma_mask = DMA_32BIT_MASK,
265
+
.platform_data = &cpmac_high_data,
266
+
},
267
+
.resource = cpmac_high_res,
268
+
.num_resources = ARRAY_SIZE(cpmac_high_res),
269
+
};
270
+
271
+
static struct platform_device vlynq_low = {
272
+
.id = 0,
273
+
.name = "vlynq",
274
+
.dev.platform_data = &vlynq_low_data,
275
+
.resource = vlynq_low_res,
276
+
.num_resources = ARRAY_SIZE(vlynq_low_res),
277
+
};
278
+
279
+
static struct platform_device vlynq_high = {
280
+
.id = 1,
281
+
.name = "vlynq",
282
+
.dev.platform_data = &vlynq_high_data,
283
+
.resource = vlynq_high_res,
284
+
.num_resources = ARRAY_SIZE(vlynq_high_res),
285
+
};
286
+
287
+
288
+
static struct gpio_led default_leds[] = {
289
+
{
290
+
.name = "status",
291
+
.gpio = 8,
292
+
.active_low = 1,
293
+
},
294
+
};
295
+
296
+
static struct gpio_led dsl502t_leds[] = {
297
+
{
298
+
.name = "status",
299
+
.gpio = 9,
300
+
.active_low = 1,
301
+
},
302
+
{
303
+
.name = "ethernet",
304
+
.gpio = 7,
305
+
.active_low = 1,
306
+
},
307
+
{
308
+
.name = "usb",
309
+
.gpio = 12,
310
+
.active_low = 1,
311
+
},
312
+
};
313
+
314
+
static struct gpio_led dg834g_leds[] = {
315
+
{
316
+
.name = "ppp",
317
+
.gpio = 6,
318
+
.active_low = 1,
319
+
},
320
+
{
321
+
.name = "status",
322
+
.gpio = 7,
323
+
.active_low = 1,
324
+
},
325
+
{
326
+
.name = "adsl",
327
+
.gpio = 8,
328
+
.active_low = 1,
329
+
},
330
+
{
331
+
.name = "wifi",
332
+
.gpio = 12,
333
+
.active_low = 1,
334
+
},
335
+
{
336
+
.name = "power",
337
+
.gpio = 14,
338
+
.active_low = 1,
339
+
.default_trigger = "default-on",
340
+
},
341
+
};
342
+
343
+
static struct gpio_led fb_sl_leds[] = {
344
+
{
345
+
.name = "1",
346
+
.gpio = 7,
347
+
},
348
+
{
349
+
.name = "2",
350
+
.gpio = 13,
351
+
.active_low = 1,
352
+
},
353
+
{
354
+
.name = "3",
355
+
.gpio = 10,
356
+
.active_low = 1,
357
+
},
358
+
{
359
+
.name = "4",
360
+
.gpio = 12,
361
+
.active_low = 1,
362
+
},
363
+
{
364
+
.name = "5",
365
+
.gpio = 9,
366
+
.active_low = 1,
367
+
},
368
+
};
369
+
370
+
static struct gpio_led fb_fon_leds[] = {
371
+
{
372
+
.name = "1",
373
+
.gpio = 8,
374
+
},
375
+
{
376
+
.name = "2",
377
+
.gpio = 3,
378
+
.active_low = 1,
379
+
},
380
+
{
381
+
.name = "3",
382
+
.gpio = 5,
383
+
},
384
+
{
385
+
.name = "4",
386
+
.gpio = 4,
387
+
.active_low = 1,
388
+
},
389
+
{
390
+
.name = "5",
391
+
.gpio = 11,
392
+
.active_low = 1,
393
+
},
394
+
};
395
+
396
+
static struct gpio_led_platform_data ar7_led_data;
397
+
398
+
static struct platform_device ar7_gpio_leds = {
399
+
.name = "leds-gpio",
400
+
.id = -1,
401
+
.dev = {
402
+
.platform_data = &ar7_led_data,
403
+
}
404
+
};
405
+
406
+
static struct platform_device ar7_udc = {
407
+
.id = -1,
408
+
.name = "ar7_udc",
409
+
.resource = usb_res,
410
+
.num_resources = ARRAY_SIZE(usb_res),
411
+
};
412
+
413
+
static inline unsigned char char2hex(char h)
414
+
{
415
+
switch (h) {
416
+
case '0': case '1': case '2': case '3': case '4':
417
+
case '5': case '6': case '7': case '8': case '9':
418
+
return h - '0';
419
+
case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
420
+
return h - 'A' + 10;
421
+
case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
422
+
return h - 'a' + 10;
423
+
default:
424
+
return 0;
425
+
}
426
+
}
427
+
428
+
static void cpmac_get_mac(int instance, unsigned char *dev_addr)
429
+
{
430
+
int i;
431
+
char name[5], default_mac[ETH_ALEN], *mac;
432
+
433
+
mac = NULL;
434
+
sprintf(name, "mac%c", 'a' + instance);
435
+
mac = prom_getenv(name);
436
+
if (!mac) {
437
+
sprintf(name, "mac%c", 'a');
438
+
mac = prom_getenv(name);
439
+
}
440
+
if (!mac) {
441
+
random_ether_addr(default_mac);
442
+
mac = default_mac;
443
+
}
444
+
for (i = 0; i < 6; i++)
445
+
dev_addr[i] = (char2hex(mac[i * 3]) << 4) +
446
+
char2hex(mac[i * 3 + 1]);
447
+
}
448
+
449
+
static void __init detect_leds(void)
450
+
{
451
+
char *prid, *usb_prod;
452
+
453
+
/* Default LEDs */
454
+
ar7_led_data.num_leds = ARRAY_SIZE(default_leds);
455
+
ar7_led_data.leds = default_leds;
456
+
457
+
/* FIXME: the whole thing is unreliable */
458
+
prid = prom_getenv("ProductID");
459
+
usb_prod = prom_getenv("usb_prod");
460
+
461
+
/* If we can't get the product id from PROM, use the default LEDs */
462
+
if (!prid)
463
+
return;
464
+
465
+
if (strstr(prid, "Fritz_Box_FON")) {
466
+
ar7_led_data.num_leds = ARRAY_SIZE(fb_fon_leds);
467
+
ar7_led_data.leds = fb_fon_leds;
468
+
} else if (strstr(prid, "Fritz_Box_")) {
469
+
ar7_led_data.num_leds = ARRAY_SIZE(fb_sl_leds);
470
+
ar7_led_data.leds = fb_sl_leds;
471
+
} else if ((!strcmp(prid, "AR7RD") || !strcmp(prid, "AR7DB"))
472
+
&& usb_prod != NULL && strstr(usb_prod, "DSL-502T")) {
473
+
ar7_led_data.num_leds = ARRAY_SIZE(dsl502t_leds);
474
+
ar7_led_data.leds = dsl502t_leds;
475
+
} else if (strstr(prid, "DG834")) {
476
+
ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
477
+
ar7_led_data.leds = dg834g_leds;
478
+
}
479
+
}
480
+
481
+
static int __init ar7_register_devices(void)
482
+
{
483
+
int res;
484
+
static struct uart_port uart_port[2];
485
+
486
+
memset(uart_port, 0, sizeof(struct uart_port) * 2);
487
+
488
+
uart_port[0].type = PORT_16550A;
489
+
uart_port[0].line = 0;
490
+
uart_port[0].irq = AR7_IRQ_UART0;
491
+
uart_port[0].uartclk = ar7_bus_freq() / 2;
492
+
uart_port[0].iotype = UPIO_MEM32;
493
+
uart_port[0].mapbase = AR7_REGS_UART0;
494
+
uart_port[0].membase = ioremap(uart_port[0].mapbase, 256);
495
+
uart_port[0].regshift = 2;
496
+
res = early_serial_setup(&uart_port[0]);
497
+
if (res)
498
+
return res;
499
+
500
+
501
+
/* Only TNETD73xx have a second serial port */
502
+
if (ar7_has_second_uart()) {
503
+
uart_port[1].type = PORT_16550A;
504
+
uart_port[1].line = 1;
505
+
uart_port[1].irq = AR7_IRQ_UART1;
506
+
uart_port[1].uartclk = ar7_bus_freq() / 2;
507
+
uart_port[1].iotype = UPIO_MEM32;
508
+
uart_port[1].mapbase = UR8_REGS_UART1;
509
+
uart_port[1].membase = ioremap(uart_port[1].mapbase, 256);
510
+
uart_port[1].regshift = 2;
511
+
res = early_serial_setup(&uart_port[1]);
512
+
if (res)
513
+
return res;
514
+
}
515
+
516
+
res = platform_device_register(&physmap_flash);
517
+
if (res)
518
+
return res;
519
+
520
+
ar7_device_disable(vlynq_low_data.reset_bit);
521
+
res = platform_device_register(&vlynq_low);
522
+
if (res)
523
+
return res;
524
+
525
+
if (ar7_has_high_vlynq()) {
526
+
ar7_device_disable(vlynq_high_data.reset_bit);
527
+
res = platform_device_register(&vlynq_high);
528
+
if (res)
529
+
return res;
530
+
}
531
+
532
+
if (ar7_has_high_cpmac()) {
533
+
cpmac_get_mac(1, cpmac_high_data.dev_addr);
534
+
res = platform_device_register(&cpmac_high);
535
+
if (res)
536
+
return res;
537
+
} else {
538
+
cpmac_low_data.phy_mask = 0xffffffff;
539
+
}
540
+
541
+
cpmac_get_mac(0, cpmac_low_data.dev_addr);
542
+
res = platform_device_register(&cpmac_low);
543
+
if (res)
544
+
return res;
545
+
546
+
detect_leds();
547
+
res = platform_device_register(&ar7_gpio_leds);
548
+
if (res)
549
+
return res;
550
+
551
+
res = platform_device_register(&ar7_udc);
552
+
553
+
return res;
554
+
}
555
+
arch_initcall(ar7_register_devices);
+297
arch/mips/ar7/prom.c
+297
arch/mips/ar7/prom.c
···
1
+
/*
2
+
* Carsten Langgaard, carstenl@mips.com
3
+
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4
+
*
5
+
* This program is free software; you can distribute it and/or modify it
6
+
* under the terms of the GNU General Public License (Version 2) as
7
+
* published by the Free Software Foundation.
8
+
*
9
+
* This program is distributed in the hope it will be useful, but WITHOUT
10
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12
+
* for more details.
13
+
*
14
+
* You should have received a copy of the GNU General Public License along
15
+
* with this program; if not, write to the Free Software Foundation, Inc.,
16
+
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17
+
*
18
+
* Putting things on the screen/serial line using YAMONs facilities.
19
+
*/
20
+
#include <linux/init.h>
21
+
#include <linux/kernel.h>
22
+
#include <linux/serial_reg.h>
23
+
#include <linux/spinlock.h>
24
+
#include <linux/module.h>
25
+
#include <linux/string.h>
26
+
#include <linux/io.h>
27
+
#include <asm/bootinfo.h>
28
+
29
+
#include <asm/mach-ar7/ar7.h>
30
+
#include <asm/mach-ar7/prom.h>
31
+
32
+
#define MAX_ENTRY 80
33
+
34
+
struct env_var {
35
+
char *name;
36
+
char *value;
37
+
};
38
+
39
+
static struct env_var adam2_env[MAX_ENTRY];
40
+
41
+
char *prom_getenv(const char *name)
42
+
{
43
+
int i;
44
+
for (i = 0; (i < MAX_ENTRY) && adam2_env[i].name; i++)
45
+
if (!strcmp(name, adam2_env[i].name))
46
+
return adam2_env[i].value;
47
+
48
+
return NULL;
49
+
}
50
+
EXPORT_SYMBOL(prom_getenv);
51
+
52
+
char * __init prom_getcmdline(void)
53
+
{
54
+
return &(arcs_cmdline[0]);
55
+
}
56
+
57
+
static void __init ar7_init_cmdline(int argc, char *argv[])
58
+
{
59
+
char *cp;
60
+
int actr;
61
+
62
+
actr = 1; /* Always ignore argv[0] */
63
+
64
+
cp = &(arcs_cmdline[0]);
65
+
while (actr < argc) {
66
+
strcpy(cp, argv[actr]);
67
+
cp += strlen(argv[actr]);
68
+
*cp++ = ' ';
69
+
actr++;
70
+
}
71
+
if (cp != &(arcs_cmdline[0])) {
72
+
/* get rid of trailing space */
73
+
--cp;
74
+
*cp = '\0';
75
+
}
76
+
}
77
+
78
+
struct psbl_rec {
79
+
u32 psbl_size;
80
+
u32 env_base;
81
+
u32 env_size;
82
+
u32 ffs_base;
83
+
u32 ffs_size;
84
+
};
85
+
86
+
static __initdata char psp_env_version[] = "TIENV0.8";
87
+
88
+
struct psp_env_chunk {
89
+
u8 num;
90
+
u8 ctrl;
91
+
u16 csum;
92
+
u8 len;
93
+
char data[11];
94
+
} __attribute__ ((packed));
95
+
96
+
struct psp_var_map_entry {
97
+
u8 num;
98
+
char *value;
99
+
};
100
+
101
+
static struct psp_var_map_entry psp_var_map[] = {
102
+
{ 1, "cpufrequency" },
103
+
{ 2, "memsize" },
104
+
{ 3, "flashsize" },
105
+
{ 4, "modetty0" },
106
+
{ 5, "modetty1" },
107
+
{ 8, "maca" },
108
+
{ 9, "macb" },
109
+
{ 28, "sysfrequency" },
110
+
{ 38, "mipsfrequency" },
111
+
};
112
+
113
+
/*
114
+
115
+
Well-known variable (num is looked up in table above for matching variable name)
116
+
Example: cpufrequency=211968000
117
+
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
118
+
| 01 |CTRL|CHECKSUM | 01 | _2 | _1 | _1 | _9 | _6 | _8 | _0 | _0 | _0 | \0 | FF
119
+
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
120
+
121
+
Name=Value pair in a single chunk
122
+
Example: NAME=VALUE
123
+
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
124
+
| 00 |CTRL|CHECKSUM | 01 | _N | _A | _M | _E | _0 | _V | _A | _L | _U | _E | \0
125
+
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
126
+
127
+
Name=Value pair in 2 chunks (len is the number of chunks)
128
+
Example: bootloaderVersion=1.3.7.15
129
+
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
130
+
| 00 |CTRL|CHECKSUM | 02 | _b | _o | _o | _t | _l | _o | _a | _d | _e | _r | _V
131
+
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
132
+
| _e | _r | _s | _i | _o | _n | \0 | _1 | _. | _3 | _. | _7 | _. | _1 | _5 | \0
133
+
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
134
+
135
+
Data is padded with 0xFF
136
+
137
+
*/
138
+
139
+
#define PSP_ENV_SIZE 4096
140
+
141
+
static char psp_env_data[PSP_ENV_SIZE] = { 0, };
142
+
143
+
static char * __init lookup_psp_var_map(u8 num)
144
+
{
145
+
int i;
146
+
147
+
for (i = 0; i < sizeof(psp_var_map); i++)
148
+
if (psp_var_map[i].num == num)
149
+
return psp_var_map[i].value;
150
+
151
+
return NULL;
152
+
}
153
+
154
+
static void __init add_adam2_var(char *name, char *value)
155
+
{
156
+
int i;
157
+
for (i = 0; i < MAX_ENTRY; i++) {
158
+
if (!adam2_env[i].name) {
159
+
adam2_env[i].name = name;
160
+
adam2_env[i].value = value;
161
+
return;
162
+
} else if (!strcmp(adam2_env[i].name, name)) {
163
+
adam2_env[i].value = value;
164
+
return;
165
+
}
166
+
}
167
+
}
168
+
169
+
static int __init parse_psp_env(void *psp_env_base)
170
+
{
171
+
int i, n;
172
+
char *name, *value;
173
+
struct psp_env_chunk *chunks = (struct psp_env_chunk *)psp_env_data;
174
+
175
+
memcpy_fromio(chunks, psp_env_base, PSP_ENV_SIZE);
176
+
177
+
i = 1;
178
+
n = PSP_ENV_SIZE / sizeof(struct psp_env_chunk);
179
+
while (i < n) {
180
+
if ((chunks[i].num == 0xff) || ((i + chunks[i].len) > n))
181
+
break;
182
+
value = chunks[i].data;
183
+
if (chunks[i].num) {
184
+
name = lookup_psp_var_map(chunks[i].num);
185
+
} else {
186
+
name = value;
187
+
value += strlen(name) + 1;
188
+
}
189
+
if (name)
190
+
add_adam2_var(name, value);
191
+
i += chunks[i].len;
192
+
}
193
+
return 0;
194
+
}
195
+
196
+
static void __init ar7_init_env(struct env_var *env)
197
+
{
198
+
int i;
199
+
struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x14000300));
200
+
void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
201
+
202
+
if (strcmp(psp_env, psp_env_version) == 0) {
203
+
parse_psp_env(psp_env);
204
+
} else {
205
+
for (i = 0; i < MAX_ENTRY; i++, env++)
206
+
if (env->name)
207
+
add_adam2_var(env->name, env->value);
208
+
}
209
+
}
210
+
211
+
static void __init console_config(void)
212
+
{
213
+
#ifdef CONFIG_SERIAL_8250_CONSOLE
214
+
char console_string[40];
215
+
int baud = 0;
216
+
char parity = '\0', bits = '\0', flow = '\0';
217
+
char *s, *p;
218
+
219
+
if (strstr(prom_getcmdline(), "console="))
220
+
return;
221
+
222
+
#ifdef CONFIG_KGDB
223
+
if (!strstr(prom_getcmdline(), "nokgdb")) {
224
+
strcat(prom_getcmdline(), " console=kgdb");
225
+
kgdb_enabled = 1;
226
+
return;
227
+
}
228
+
#endif
229
+
230
+
s = prom_getenv("modetty0");
231
+
if (s) {
232
+
baud = simple_strtoul(s, &p, 10);
233
+
s = p;
234
+
if (*s == ',')
235
+
s++;
236
+
if (*s)
237
+
parity = *s++;
238
+
if (*s == ',')
239
+
s++;
240
+
if (*s)
241
+
bits = *s++;
242
+
if (*s == ',')
243
+
s++;
244
+
if (*s == 'h')
245
+
flow = 'r';
246
+
}
247
+
248
+
if (baud == 0)
249
+
baud = 38400;
250
+
if (parity != 'n' && parity != 'o' && parity != 'e')
251
+
parity = 'n';
252
+
if (bits != '7' && bits != '8')
253
+
bits = '8';
254
+
255
+
if (flow == 'r')
256
+
sprintf(console_string, " console=ttyS0,%d%c%c%c", baud,
257
+
parity, bits, flow);
258
+
else
259
+
sprintf(console_string, " console=ttyS0,%d%c%c", baud, parity,
260
+
bits);
261
+
strcat(prom_getcmdline(), console_string);
262
+
#endif
263
+
}
264
+
265
+
void __init prom_init(void)
266
+
{
267
+
ar7_init_cmdline(fw_arg0, (char **)fw_arg1);
268
+
ar7_init_env((struct env_var *)fw_arg2);
269
+
console_config();
270
+
}
271
+
272
+
#define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4)))
273
+
static inline unsigned int serial_in(int offset)
274
+
{
275
+
return readl((void *)PORT(offset));
276
+
}
277
+
278
+
static inline void serial_out(int offset, int value)
279
+
{
280
+
writel(value, (void *)PORT(offset));
281
+
}
282
+
283
+
char prom_getchar(void)
284
+
{
285
+
while (!(serial_in(UART_LSR) & UART_LSR_DR))
286
+
;
287
+
return serial_in(UART_RX);
288
+
}
289
+
290
+
int prom_putchar(char c)
291
+
{
292
+
while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0)
293
+
;
294
+
serial_out(UART_TX, c);
295
+
return 1;
296
+
}
297
+
+94
arch/mips/ar7/setup.c
+94
arch/mips/ar7/setup.c
···
1
+
/*
2
+
* Carsten Langgaard, carstenl@mips.com
3
+
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4
+
*
5
+
* This program is free software; you can distribute it and/or modify it
6
+
* under the terms of the GNU General Public License (Version 2) as
7
+
* published by the Free Software Foundation.
8
+
*
9
+
* This program is distributed in the hope it will be useful, but WITHOUT
10
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12
+
* for more details.
13
+
*
14
+
* You should have received a copy of the GNU General Public License along
15
+
* with this program; if not, write to the Free Software Foundation, Inc.,
16
+
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17
+
*/
18
+
#include <linux/version.h>
19
+
#include <linux/init.h>
20
+
#include <linux/ioport.h>
21
+
#include <linux/pm.h>
22
+
#include <linux/time.h>
23
+
24
+
#include <asm/reboot.h>
25
+
#include <asm/mach-ar7/ar7.h>
26
+
#include <asm/mach-ar7/prom.h>
27
+
28
+
static void ar7_machine_restart(char *command)
29
+
{
30
+
u32 *softres_reg = ioremap(AR7_REGS_RESET +
31
+
AR7_RESET_SOFTWARE, 1);
32
+
writel(1, softres_reg);
33
+
}
34
+
35
+
static void ar7_machine_halt(void)
36
+
{
37
+
while (1)
38
+
;
39
+
}
40
+
41
+
static void ar7_machine_power_off(void)
42
+
{
43
+
u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1);
44
+
u32 power_state = readl(power_reg) | (3 << 30);
45
+
writel(power_state, power_reg);
46
+
ar7_machine_halt();
47
+
}
48
+
49
+
const char *get_system_type(void)
50
+
{
51
+
u16 chip_id = ar7_chip_id();
52
+
switch (chip_id) {
53
+
case AR7_CHIP_7300:
54
+
return "TI AR7 (TNETD7300)";
55
+
case AR7_CHIP_7100:
56
+
return "TI AR7 (TNETD7100)";
57
+
case AR7_CHIP_7200:
58
+
return "TI AR7 (TNETD7200)";
59
+
default:
60
+
return "TI AR7 (Unknown)";
61
+
}
62
+
}
63
+
64
+
static int __init ar7_init_console(void)
65
+
{
66
+
return 0;
67
+
}
68
+
console_initcall(ar7_init_console);
69
+
70
+
/*
71
+
* Initializes basic routines and structures pointers, memory size (as
72
+
* given by the bios and saves the command line.
73
+
*/
74
+
75
+
void __init plat_mem_setup(void)
76
+
{
77
+
unsigned long io_base;
78
+
79
+
_machine_restart = ar7_machine_restart;
80
+
_machine_halt = ar7_machine_halt;
81
+
pm_power_off = ar7_machine_power_off;
82
+
panic_timeout = 3;
83
+
84
+
io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);
85
+
if (!io_base)
86
+
panic("Can't remap IO base!\n");
87
+
set_io_port_base(io_base);
88
+
89
+
prom_meminit();
90
+
91
+
printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n",
92
+
get_system_type(),
93
+
ar7_chip_id(), ar7_chip_rev());
94
+
}
+30
arch/mips/ar7/time.c
+30
arch/mips/ar7/time.c
···
1
+
/*
2
+
* Carsten Langgaard, carstenl@mips.com
3
+
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4
+
*
5
+
* This program is free software; you can distribute it and/or modify it
6
+
* under the terms of the GNU General Public License (Version 2) as
7
+
* published by the Free Software Foundation.
8
+
*
9
+
* This program is distributed in the hope it will be useful, but WITHOUT
10
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12
+
* for more details.
13
+
*
14
+
* You should have received a copy of the GNU General Public License along
15
+
* with this program; if not, write to the Free Software Foundation, Inc.,
16
+
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17
+
*
18
+
* Setting up the clock on the MIPS boards.
19
+
*/
20
+
21
+
#include <linux/init.h>
22
+
#include <linux/time.h>
23
+
24
+
#include <asm/time.h>
25
+
#include <asm/mach-ar7/ar7.h>
26
+
27
+
void __init plat_time_init(void)
28
+
{
29
+
mips_hpt_frequency = ar7_cpu_freq() / 2;
30
+
}
-4
arch/mips/cavium-octeon/Makefile
-4
arch/mips/cavium-octeon/Makefile
+1
-1
arch/mips/cavium-octeon/dma-octeon.c
+1
-1
arch/mips/cavium-octeon/dma-octeon.c
+28
-28
arch/mips/cavium-octeon/msi.c
arch/mips/pci/msi-octeon.c
+28
-28
arch/mips/cavium-octeon/msi.c
arch/mips/pci/msi-octeon.c
···
3
3
* License. See the file "COPYING" in the main directory of this archive
4
4
* for more details.
5
5
*
6
-
* Copyright (C) 2005-2007 Cavium Networks
6
+
* Copyright (C) 2005-2009 Cavium Networks
7
7
*/
8
8
#include <linux/kernel.h>
9
9
#include <linux/init.h>
···
16
16
#include <asm/octeon/cvmx-pci-defs.h>
17
17
#include <asm/octeon/cvmx-npei-defs.h>
18
18
#include <asm/octeon/cvmx-pexp-defs.h>
19
-
20
-
#include "pci-common.h"
19
+
#include <asm/octeon/pci-octeon.h>
21
20
22
21
/*
23
22
* Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
···
46
47
* programming the MSI control bits [6:4] before calling
47
48
* pci_enable_msi().
48
49
*
49
-
* @param dev Device requesting MSI interrupts
50
-
* @param desc MSI descriptor
50
+
* @dev: Device requesting MSI interrupts
51
+
* @desc: MSI descriptor
51
52
*
52
53
* Returns 0 on success.
53
54
*/
···
212
213
}
213
214
214
215
215
-
/**
216
+
/*
216
217
* Called by the interrupt handling code when an MSI interrupt
217
218
* occurs.
218
-
*
219
-
* @param cpl
220
-
* @param dev_id
221
-
*
222
-
* @return
223
219
*/
224
220
static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
225
221
{
···
250
256
}
251
257
252
258
253
-
/**
259
+
/*
254
260
* Initializes the MSI interrupt handling code
255
-
*
256
-
* @return
257
261
*/
258
262
int octeon_msi_initialize(void)
259
263
{
260
-
int r;
261
264
if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
262
-
r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
265
+
if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
263
266
IRQF_SHARED,
264
-
"MSI[0:63]", octeon_msi_interrupt);
267
+
"MSI[0:63]", octeon_msi_interrupt))
268
+
panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
265
269
} else if (octeon_is_pci_host()) {
266
-
r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
270
+
if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
267
271
IRQF_SHARED,
268
-
"MSI[0:15]", octeon_msi_interrupt);
269
-
r += request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
270
-
IRQF_SHARED,
271
-
"MSI[16:31]", octeon_msi_interrupt);
272
-
r += request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
273
-
IRQF_SHARED,
274
-
"MSI[32:47]", octeon_msi_interrupt);
275
-
r += request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
276
-
IRQF_SHARED,
277
-
"MSI[48:63]", octeon_msi_interrupt);
272
+
"MSI[0:15]", octeon_msi_interrupt))
273
+
panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
274
+
275
+
if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
276
+
IRQF_SHARED,
277
+
"MSI[16:31]", octeon_msi_interrupt))
278
+
panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
279
+
280
+
if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
281
+
IRQF_SHARED,
282
+
"MSI[32:47]", octeon_msi_interrupt))
283
+
panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
284
+
285
+
if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
286
+
IRQF_SHARED,
287
+
"MSI[48:63]", octeon_msi_interrupt))
288
+
panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
289
+
278
290
}
279
291
return 0;
280
292
}
-137
arch/mips/cavium-octeon/pci-common.c
-137
arch/mips/cavium-octeon/pci-common.c
···
1
-
/*
2
-
* This file is subject to the terms and conditions of the GNU General Public
3
-
* License. See the file "COPYING" in the main directory of this archive
4
-
* for more details.
5
-
*
6
-
* Copyright (C) 2005-2007 Cavium Networks
7
-
*/
8
-
#include <linux/kernel.h>
9
-
#include <linux/init.h>
10
-
#include <linux/pci.h>
11
-
#include <linux/interrupt.h>
12
-
#include <linux/time.h>
13
-
#include <linux/delay.h>
14
-
#include "pci-common.h"
15
-
16
-
typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
17
-
enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
18
-
19
-
/**
20
-
* Map a PCI device to the appropriate interrupt line
21
-
*
22
-
* @param dev The Linux PCI device structure for the device to map
23
-
* @param slot The slot number for this device on __BUS 0__. Linux
24
-
* enumerates through all the bridges and figures out the
25
-
* slot on Bus 0 where this device eventually hooks to.
26
-
* @param pin The PCI interrupt pin read from the device, then swizzled
27
-
* as it goes through each bridge.
28
-
* @return Interrupt number for the device
29
-
*/
30
-
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
31
-
{
32
-
if (octeon_pcibios_map_irq)
33
-
return octeon_pcibios_map_irq(dev, slot, pin);
34
-
else
35
-
panic("octeon_pcibios_map_irq doesn't point to a "
36
-
"pcibios_map_irq() function");
37
-
}
38
-
39
-
40
-
/**
41
-
* Called to perform platform specific PCI setup
42
-
*
43
-
* @param dev
44
-
* @return
45
-
*/
46
-
int pcibios_plat_dev_init(struct pci_dev *dev)
47
-
{
48
-
uint16_t config;
49
-
uint32_t dconfig;
50
-
int pos;
51
-
/*
52
-
* Force the Cache line setting to 64 bytes. The standard
53
-
* Linux bus scan doesn't seem to set it. Octeon really has
54
-
* 128 byte lines, but Intel bridges get really upset if you
55
-
* try and set values above 64 bytes. Value is specified in
56
-
* 32bit words.
57
-
*/
58
-
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
59
-
/* Set latency timers for all devices */
60
-
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
61
-
62
-
/* Enable reporting System errors and parity errors on all devices */
63
-
/* Enable parity checking and error reporting */
64
-
pci_read_config_word(dev, PCI_COMMAND, &config);
65
-
config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
66
-
pci_write_config_word(dev, PCI_COMMAND, config);
67
-
68
-
if (dev->subordinate) {
69
-
/* Set latency timers on sub bridges */
70
-
pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
71
-
/* More bridge error detection */
72
-
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
73
-
config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
74
-
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
75
-
}
76
-
77
-
/* Enable the PCIe normal error reporting */
78
-
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
79
-
if (pos) {
80
-
/* Update Device Control */
81
-
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
82
-
/* Correctable Error Reporting */
83
-
config |= PCI_EXP_DEVCTL_CERE;
84
-
/* Non-Fatal Error Reporting */
85
-
config |= PCI_EXP_DEVCTL_NFERE;
86
-
/* Fatal Error Reporting */
87
-
config |= PCI_EXP_DEVCTL_FERE;
88
-
/* Unsupported Request */
89
-
config |= PCI_EXP_DEVCTL_URRE;
90
-
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
91
-
}
92
-
93
-
/* Find the Advanced Error Reporting capability */
94
-
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
95
-
if (pos) {
96
-
/* Clear Uncorrectable Error Status */
97
-
pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
98
-
&dconfig);
99
-
pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
100
-
dconfig);
101
-
/* Enable reporting of all uncorrectable errors */
102
-
/* Uncorrectable Error Mask - turned on bits disable errors */
103
-
pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
104
-
/*
105
-
* Leave severity at HW default. This only controls if
106
-
* errors are reported as uncorrectable or
107
-
* correctable, not if the error is reported.
108
-
*/
109
-
/* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
110
-
/* Clear Correctable Error Status */
111
-
pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
112
-
pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
113
-
/* Enable reporting of all correctable errors */
114
-
/* Correctable Error Mask - turned on bits disable errors */
115
-
pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
116
-
/* Advanced Error Capabilities */
117
-
pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
118
-
/* ECRC Generation Enable */
119
-
if (config & PCI_ERR_CAP_ECRC_GENC)
120
-
config |= PCI_ERR_CAP_ECRC_GENE;
121
-
/* ECRC Check Enable */
122
-
if (config & PCI_ERR_CAP_ECRC_CHKC)
123
-
config |= PCI_ERR_CAP_ECRC_CHKE;
124
-
pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
125
-
/* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
126
-
/* Report all errors to the root complex */
127
-
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
128
-
PCI_ERR_ROOT_CMD_COR_EN |
129
-
PCI_ERR_ROOT_CMD_NONFATAL_EN |
130
-
PCI_ERR_ROOT_CMD_FATAL_EN);
131
-
/* Clear the Root status register */
132
-
pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
133
-
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
134
-
}
135
-
136
-
return 0;
137
-
}
+18
-12
arch/mips/cavium-octeon/pci-common.h
arch/mips/include/asm/octeon/pci-octeon.h
+18
-12
arch/mips/cavium-octeon/pci-common.h
arch/mips/include/asm/octeon/pci-octeon.h
···
3
3
* License. See the file "COPYING" in the main directory of this archive
4
4
* for more details.
5
5
*
6
-
* Copyright (C) 2005-2007 Cavium Networks
6
+
* Copyright (C) 2005-2009 Cavium Networks
7
7
*/
8
-
#ifndef __OCTEON_PCI_COMMON_H__
9
-
#define __OCTEON_PCI_COMMON_H__
8
+
9
+
#ifndef __PCI_OCTEON_H__
10
+
#define __PCI_OCTEON_H__
10
11
11
12
#include <linux/pci.h>
12
13
13
14
/* Some PCI cards require delays when accessing config space. */
14
15
#define PCI_CONFIG_SPACE_DELAY 10000
15
16
16
-
/* pcibios_map_irq() is defined inside pci-common.c. All it does is call the
17
-
Octeon specific version pointed to by this variable. This function needs to
18
-
change for PCI or PCIe based hosts */
19
-
extern typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
17
+
/*
18
+
* pcibios_map_irq() is defined inside pci-octeon.c. All it does is
19
+
* call the Octeon specific version pointed to by this variable. This
20
+
* function needs to change for PCI or PCIe based hosts.
21
+
*/
22
+
extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
23
+
u8 slot, u8 pin);
20
24
21
-
/* The following defines are only used when octeon_dma_bar_type =
22
-
OCTEON_DMA_BAR_TYPE_BIG */
25
+
/*
26
+
* The following defines are used when octeon_dma_bar_type =
27
+
* OCTEON_DMA_BAR_TYPE_BIG
28
+
*/
23
29
#define OCTEON_PCI_BAR1_HOLE_BITS 5
24
30
#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
25
31
···
36
30
OCTEON_DMA_BAR_TYPE_PCIE
37
31
};
38
32
39
-
/**
40
-
* This is a variable to tell the DMA mapping system in dma-octeon.c
41
-
* how to map PCI DMA addresses.
33
+
/*
34
+
* This tells the DMA mapping system in dma-octeon.c how to map PCI
35
+
* DMA addresses.
42
36
*/
43
37
extern enum octeon_dma_bar_type octeon_dma_bar_type;
44
38
+127
-20
arch/mips/cavium-octeon/pci.c
arch/mips/pci/pci-octeon.c
+127
-20
arch/mips/cavium-octeon/pci.c
arch/mips/pci/pci-octeon.c
···
3
3
* License. See the file "COPYING" in the main directory of this archive
4
4
* for more details.
5
5
*
6
-
* Copyright (C) 2005-2007 Cavium Networks
6
+
* Copyright (C) 2005-2009 Cavium Networks
7
7
*/
8
8
#include <linux/kernel.h>
9
9
#include <linux/init.h>
···
17
17
#include <asm/octeon/octeon.h>
18
18
#include <asm/octeon/cvmx-npi-defs.h>
19
19
#include <asm/octeon/cvmx-pci-defs.h>
20
-
21
-
#include "pci-common.h"
20
+
#include <asm/octeon/pci-octeon.h>
22
21
23
22
#define USE_OCTEON_INTERNAL_ARBITER
24
23
···
52
53
uint64_t reg:8;
53
54
} s;
54
55
};
56
+
57
+
int __initdata (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
58
+
u8 slot, u8 pin);
59
+
enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
60
+
61
+
/**
62
+
* Map a PCI device to the appropriate interrupt line
63
+
*
64
+
* @dev: The Linux PCI device structure for the device to map
65
+
* @slot: The slot number for this device on __BUS 0__. Linux
66
+
* enumerates through all the bridges and figures out the
67
+
* slot on Bus 0 where this device eventually hooks to.
68
+
* @pin: The PCI interrupt pin read from the device, then swizzled
69
+
* as it goes through each bridge.
70
+
* Returns Interrupt number for the device
71
+
*/
72
+
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
73
+
{
74
+
if (octeon_pcibios_map_irq)
75
+
return octeon_pcibios_map_irq(dev, slot, pin);
76
+
else
77
+
panic("octeon_pcibios_map_irq not set.");
78
+
}
79
+
80
+
81
+
/*
82
+
* Called to perform platform specific PCI setup
83
+
*/
84
+
int pcibios_plat_dev_init(struct pci_dev *dev)
85
+
{
86
+
uint16_t config;
87
+
uint32_t dconfig;
88
+
int pos;
89
+
/*
90
+
* Force the Cache line setting to 64 bytes. The standard
91
+
* Linux bus scan doesn't seem to set it. Octeon really has
92
+
* 128 byte lines, but Intel bridges get really upset if you
93
+
* try and set values above 64 bytes. Value is specified in
94
+
* 32bit words.
95
+
*/
96
+
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
97
+
/* Set latency timers for all devices */
98
+
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
99
+
100
+
/* Enable reporting System errors and parity errors on all devices */
101
+
/* Enable parity checking and error reporting */
102
+
pci_read_config_word(dev, PCI_COMMAND, &config);
103
+
config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
104
+
pci_write_config_word(dev, PCI_COMMAND, config);
105
+
106
+
if (dev->subordinate) {
107
+
/* Set latency timers on sub bridges */
108
+
pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
109
+
/* More bridge error detection */
110
+
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
111
+
config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
112
+
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
113
+
}
114
+
115
+
/* Enable the PCIe normal error reporting */
116
+
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
117
+
if (pos) {
118
+
/* Update Device Control */
119
+
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
120
+
/* Correctable Error Reporting */
121
+
config |= PCI_EXP_DEVCTL_CERE;
122
+
/* Non-Fatal Error Reporting */
123
+
config |= PCI_EXP_DEVCTL_NFERE;
124
+
/* Fatal Error Reporting */
125
+
config |= PCI_EXP_DEVCTL_FERE;
126
+
/* Unsupported Request */
127
+
config |= PCI_EXP_DEVCTL_URRE;
128
+
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
129
+
}
130
+
131
+
/* Find the Advanced Error Reporting capability */
132
+
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
133
+
if (pos) {
134
+
/* Clear Uncorrectable Error Status */
135
+
pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
136
+
&dconfig);
137
+
pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
138
+
dconfig);
139
+
/* Enable reporting of all uncorrectable errors */
140
+
/* Uncorrectable Error Mask - turned on bits disable errors */
141
+
pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
142
+
/*
143
+
* Leave severity at HW default. This only controls if
144
+
* errors are reported as uncorrectable or
145
+
* correctable, not if the error is reported.
146
+
*/
147
+
/* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
148
+
/* Clear Correctable Error Status */
149
+
pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
150
+
pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
151
+
/* Enable reporting of all correctable errors */
152
+
/* Correctable Error Mask - turned on bits disable errors */
153
+
pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
154
+
/* Advanced Error Capabilities */
155
+
pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
156
+
/* ECRC Generation Enable */
157
+
if (config & PCI_ERR_CAP_ECRC_GENC)
158
+
config |= PCI_ERR_CAP_ECRC_GENE;
159
+
/* ECRC Check Enable */
160
+
if (config & PCI_ERR_CAP_ECRC_CHKC)
161
+
config |= PCI_ERR_CAP_ECRC_CHKE;
162
+
pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
163
+
/* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
164
+
/* Report all errors to the root complex */
165
+
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
166
+
PCI_ERR_ROOT_CMD_COR_EN |
167
+
PCI_ERR_ROOT_CMD_NONFATAL_EN |
168
+
PCI_ERR_ROOT_CMD_FATAL_EN);
169
+
/* Clear the Root status register */
170
+
pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
171
+
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
172
+
}
173
+
174
+
return 0;
175
+
}
55
176
56
177
/**
57
178
* Return the mapping of PCI device number to IRQ line. Each
···
255
136
}
256
137
257
138
258
-
/**
139
+
/*
259
140
* Read a value from configuration space
260
-
*
261
141
*/
262
142
static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
263
143
int reg, int size, u32 *val)
···
292
174
}
293
175
294
176
295
-
/**
177
+
/*
296
178
* Write a value to PCI configuration space
297
-
*
298
-
* @bus:
299
-
* @devfn:
300
-
* @reg:
301
-
* @size:
302
-
* @val:
303
-
* Returns
304
179
*/
305
180
static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
306
181
int reg, int size, u32 val)
···
362
251
};
363
252
364
253
365
-
/**
254
+
/*
366
255
* Low level initialize the Octeon PCI controller
367
-
*
368
-
* Returns
369
256
*/
370
257
static void octeon_pci_initialize(void)
371
258
{
···
507
398
pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */
508
399
cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
509
400
}
510
-
#endif /* USE_OCTEON_INTERNAL_ARBITER */
401
+
#endif /* USE_OCTEON_INTERNAL_ARBITER */
511
402
512
403
/*
513
404
* Preferrably written to 1 to set MLTD. [RDSATI,TRTAE,
···
566
457
}
567
458
568
459
569
-
/**
460
+
/*
570
461
* Initialize the Octeon PCI controller
571
-
*
572
-
* Returns
573
462
*/
574
463
static int __init octeon_pci_setup(void)
575
464
{
+18
-19
arch/mips/cavium-octeon/pcie.c
arch/mips/pci/pcie-octeon.c
+18
-19
arch/mips/cavium-octeon/pcie.c
arch/mips/pci/pcie-octeon.c
···
18
18
#include <asm/octeon/cvmx-pescx-defs.h>
19
19
#include <asm/octeon/cvmx-pexp-defs.h>
20
20
#include <asm/octeon/cvmx-helper-errata.h>
21
-
22
-
#include "pci-common.h"
21
+
#include <asm/octeon/pci-octeon.h>
23
22
24
23
union cvmx_pcie_address {
25
24
uint64_t u64;
···
975
976
/**
976
977
* Map a PCI device to the appropriate interrupt line
977
978
*
978
-
* @param dev The Linux PCI device structure for the device to map
979
-
* @param slot The slot number for this device on __BUS 0__. Linux
979
+
* @dev: The Linux PCI device structure for the device to map
980
+
* @slot: The slot number for this device on __BUS 0__. Linux
980
981
* enumerates through all the bridges and figures out the
981
982
* slot on Bus 0 where this device eventually hooks to.
982
-
* @param pin The PCI interrupt pin read from the device, then swizzled
983
+
* @pin: The PCI interrupt pin read from the device, then swizzled
983
984
* as it goes through each bridge.
984
-
* @return Interrupt number for the device
985
+
* Returns Interrupt number for the device
985
986
*/
986
987
int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
987
988
u8 slot, u8 pin)
···
1024
1025
/**
1025
1026
* Read a value from configuration space
1026
1027
*
1027
-
* @param bus
1028
-
* @param devfn
1029
-
* @param reg
1030
-
* @param size
1031
-
* @param val
1032
-
* @return
1028
+
* @bus:
1029
+
* @devfn:
1030
+
* @reg:
1031
+
* @size:
1032
+
* @val:
1033
+
* Returns
1033
1034
*/
1034
1035
static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
1035
1036
unsigned int devfn, int reg, int size,
···
1155
1156
/**
1156
1157
* Write a value to PCI configuration space
1157
1158
*
1158
-
* @param bus
1159
-
* @param devfn
1160
-
* @param reg
1161
-
* @param size
1162
-
* @param val
1163
-
* @return
1159
+
* @bus:
1160
+
* @devfn:
1161
+
* @reg:
1162
+
* @size:
1163
+
* @val:
1164
+
* Returns
1164
1165
*/
1165
1166
static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
1166
1167
unsigned int devfn, int reg,
···
1253
1254
/**
1254
1255
* Initialize the Octeon PCIe controllers
1255
1256
*
1256
-
* @return
1257
+
* Returns
1257
1258
*/
1258
1259
static int __init octeon_pcie_setup(void)
1259
1260
{
+1
-1
arch/mips/cobalt/lcd.c
+1
-1
arch/mips/cobalt/lcd.c
···
1
1
/*
2
2
* Registration of Cobalt LCD platform device.
3
3
*
4
-
* Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/cobalt/led.c
+1
-1
arch/mips/cobalt/led.c
···
1
1
/*
2
2
* Registration of Cobalt LED platform device.
3
3
*
4
-
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/cobalt/mtd.c
+1
-1
arch/mips/cobalt/mtd.c
···
1
1
/*
2
2
* Registration of Cobalt MTD device.
3
3
*
4
-
* Copyright (C) 2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2006 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/cobalt/rtc.c
+1
-1
arch/mips/cobalt/rtc.c
···
1
1
/*
2
2
* Registration of Cobalt RTC platform device.
3
3
*
4
-
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/cobalt/serial.c
+1
-1
arch/mips/cobalt/serial.c
···
1
1
/*
2
2
* Registration of Cobalt UART platform device.
3
3
*
4
-
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/cobalt/time.c
+1
-1
arch/mips/cobalt/time.c
···
1
1
/*
2
2
* Cobalt time initialization.
3
3
*
4
-
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1182
arch/mips/configs/ar7_defconfig
+1182
arch/mips/configs/ar7_defconfig
···
1
+
#
2
+
# Automatically generated make config: don't edit
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+
# Linux kernel version: 2.6.30
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# Wed Jun 24 14:08:59 2009
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#
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CONFIG_MIPS=y
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+
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#
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# Machine selection
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#
11
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# CONFIG_MACH_ALCHEMY is not set
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CONFIG_AR7=y
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+
# CONFIG_BASLER_EXCITE is not set
14
+
# CONFIG_BCM47XX is not set
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+
# CONFIG_MIPS_COBALT is not set
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+
# CONFIG_MACH_DECSTATION is not set
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+
# CONFIG_MACH_JAZZ is not set
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+
# CONFIG_LASAT is not set
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+
# CONFIG_LEMOTE_FULONG is not set
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+
# CONFIG_MIPS_MALTA is not set
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+
# CONFIG_MIPS_SIM is not set
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+
# CONFIG_NEC_MARKEINS is not set
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+
# CONFIG_MACH_VR41XX is not set
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+
# CONFIG_NXP_STB220 is not set
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+
# CONFIG_NXP_STB225 is not set
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+
# CONFIG_PNX8550_JBS is not set
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+
# CONFIG_PNX8550_STB810 is not set
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+
# CONFIG_PMC_MSP is not set
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+
# CONFIG_PMC_YOSEMITE is not set
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+
# CONFIG_SGI_IP22 is not set
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+
# CONFIG_SGI_IP27 is not set
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+
# CONFIG_SGI_IP28 is not set
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+
# CONFIG_SGI_IP32 is not set
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+
# CONFIG_SIBYTE_CRHINE is not set
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+
# CONFIG_SIBYTE_CARMEL is not set
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+
# CONFIG_SIBYTE_CRHONE is not set
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+
# CONFIG_SIBYTE_RHONE is not set
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+
# CONFIG_SIBYTE_SWARM is not set
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+
# CONFIG_SIBYTE_LITTLESUR is not set
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+
# CONFIG_SIBYTE_SENTOSA is not set
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+
# CONFIG_SIBYTE_BIGSUR is not set
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+
# CONFIG_SNI_RM is not set
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+
# CONFIG_MACH_TX39XX is not set
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+
# CONFIG_MACH_TX49XX is not set
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+
# CONFIG_MIKROTIK_RB532 is not set
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+
# CONFIG_WR_PPMC is not set
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+
# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
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+
# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
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+
# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
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CONFIG_RWSEM_GENERIC_SPINLOCK=y
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+
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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+
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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CONFIG_ARCH_SUPPORTS_OPROFILE=y
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CONFIG_GENERIC_FIND_NEXT_BIT=y
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CONFIG_GENERIC_HWEIGHT=y
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CONFIG_GENERIC_CALIBRATE_DELAY=y
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+
CONFIG_GENERIC_CLOCKEVENTS=y
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+
CONFIG_GENERIC_TIME=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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+
CONFIG_SCHED_OMIT_FRAME_POINTER=y
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+
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
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CONFIG_CEVT_R4K_LIB=y
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CONFIG_CEVT_R4K=y
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CONFIG_CSRC_R4K_LIB=y
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CONFIG_CSRC_R4K=y
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CONFIG_DMA_NONCOHERENT=y
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+
CONFIG_DMA_NEED_PCI_MAP_STATE=y
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+
CONFIG_EARLY_PRINTK=y
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+
CONFIG_SYS_HAS_EARLY_PRINTK=y
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+
# CONFIG_HOTPLUG_CPU is not set
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# CONFIG_NO_IOPORT is not set
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CONFIG_GENERIC_GPIO=y
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+
# CONFIG_CPU_BIG_ENDIAN is not set
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
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CONFIG_IRQ_CPU=y
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CONFIG_NO_EXCEPT_FILL=y
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CONFIG_SWAP_IO_SPACE=y
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CONFIG_BOOT_ELF32=y
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CONFIG_MIPS_L1_CACHE_SHIFT=5
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+
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#
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# CPU selection
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#
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# CONFIG_CPU_LOONGSON2 is not set
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CONFIG_CPU_MIPS32_R1=y
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+
# CONFIG_CPU_MIPS32_R2 is not set
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+
# CONFIG_CPU_MIPS64_R1 is not set
89
+
# CONFIG_CPU_MIPS64_R2 is not set
90
+
# CONFIG_CPU_R3000 is not set
91
+
# CONFIG_CPU_TX39XX is not set
92
+
# CONFIG_CPU_VR41XX is not set
93
+
# CONFIG_CPU_R4300 is not set
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+
# CONFIG_CPU_R4X00 is not set
95
+
# CONFIG_CPU_TX49XX is not set
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+
# CONFIG_CPU_R5000 is not set
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+
# CONFIG_CPU_R5432 is not set
98
+
# CONFIG_CPU_R5500 is not set
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+
# CONFIG_CPU_R6000 is not set
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# CONFIG_CPU_NEVADA is not set
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# CONFIG_CPU_R8000 is not set
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# CONFIG_CPU_R10000 is not set
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# CONFIG_CPU_RM7000 is not set
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# CONFIG_CPU_RM9000 is not set
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# CONFIG_CPU_SB1 is not set
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# CONFIG_CPU_CAVIUM_OCTEON is not set
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_CPU_MIPS32=y
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CONFIG_CPU_MIPSR1=y
110
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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+
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#
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# Kernel type
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#
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CONFIG_32BIT=y
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+
# CONFIG_64BIT is not set
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CONFIG_PAGE_SIZE_4KB=y
120
+
# CONFIG_PAGE_SIZE_8KB is not set
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# CONFIG_PAGE_SIZE_16KB is not set
122
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# CONFIG_PAGE_SIZE_32KB is not set
123
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# CONFIG_PAGE_SIZE_64KB is not set
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CONFIG_CPU_HAS_PREFETCH=y
125
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CONFIG_MIPS_MT_DISABLED=y
126
+
# CONFIG_MIPS_MT_SMP is not set
127
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# CONFIG_MIPS_MT_SMTC is not set
128
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CONFIG_CPU_HAS_LLSC=y
129
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CONFIG_CPU_HAS_SYNC=y
130
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CONFIG_GENERIC_HARDIRQS=y
131
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CONFIG_GENERIC_IRQ_PROBE=y
132
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
133
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CONFIG_ARCH_FLATMEM_ENABLE=y
134
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CONFIG_ARCH_POPULATES_NODE_MAP=y
135
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CONFIG_SELECT_MEMORY_MODEL=y
136
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CONFIG_FLATMEM_MANUAL=y
137
+
# CONFIG_DISCONTIGMEM_MANUAL is not set
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+
# CONFIG_SPARSEMEM_MANUAL is not set
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CONFIG_FLATMEM=y
140
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CONFIG_FLAT_NODE_MEM_MAP=y
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CONFIG_PAGEFLAGS_EXTENDED=y
142
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CONFIG_SPLIT_PTLOCK_CPUS=4
143
+
# CONFIG_PHYS_ADDR_T_64BIT is not set
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CONFIG_ZONE_DMA_FLAG=0
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CONFIG_VIRT_TO_BUS=y
146
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CONFIG_HAVE_MLOCK=y
147
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CONFIG_HAVE_MLOCKED_PAGE_BIT=y
148
+
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
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CONFIG_TICK_ONESHOT=y
150
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# CONFIG_NO_HZ is not set
151
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CONFIG_HIGH_RES_TIMERS=y
152
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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# CONFIG_HZ_48 is not set
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CONFIG_HZ_100=y
155
+
# CONFIG_HZ_128 is not set
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+
# CONFIG_HZ_250 is not set
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+
# CONFIG_HZ_256 is not set
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+
# CONFIG_HZ_1000 is not set
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# CONFIG_HZ_1024 is not set
160
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
161
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CONFIG_HZ=100
162
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CONFIG_PREEMPT_NONE=y
163
+
# CONFIG_PREEMPT_VOLUNTARY is not set
164
+
# CONFIG_PREEMPT is not set
165
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CONFIG_KEXEC=y
166
+
# CONFIG_SECCOMP is not set
167
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CONFIG_LOCKDEP_SUPPORT=y
168
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CONFIG_STACKTRACE_SUPPORT=y
169
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CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
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+
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#
172
+
# General setup
173
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#
174
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CONFIG_EXPERIMENTAL=y
175
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CONFIG_BROKEN_ON_SMP=y
176
+
CONFIG_INIT_ENV_ARG_LIMIT=32
177
+
CONFIG_LOCALVERSION=""
178
+
# CONFIG_LOCALVERSION_AUTO is not set
179
+
CONFIG_SWAP=y
180
+
CONFIG_SYSVIPC=y
181
+
CONFIG_SYSVIPC_SYSCTL=y
182
+
# CONFIG_POSIX_MQUEUE is not set
183
+
CONFIG_BSD_PROCESS_ACCT=y
184
+
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
185
+
# CONFIG_TASKSTATS is not set
186
+
# CONFIG_AUDIT is not set
187
+
188
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#
189
+
# RCU Subsystem
190
+
#
191
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CONFIG_CLASSIC_RCU=y
192
+
# CONFIG_TREE_RCU is not set
193
+
# CONFIG_PREEMPT_RCU is not set
194
+
# CONFIG_TREE_RCU_TRACE is not set
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+
# CONFIG_PREEMPT_RCU_TRACE is not set
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+
# CONFIG_IKCONFIG is not set
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CONFIG_LOG_BUF_SHIFT=14
198
+
# CONFIG_GROUP_SCHED is not set
199
+
# CONFIG_CGROUPS is not set
200
+
CONFIG_SYSFS_DEPRECATED=y
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+
CONFIG_SYSFS_DEPRECATED_V2=y
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+
CONFIG_RELAY=y
203
+
# CONFIG_NAMESPACES is not set
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+
CONFIG_BLK_DEV_INITRD=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_RD_GZIP=y
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+
# CONFIG_RD_BZIP2 is not set
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CONFIG_RD_LZMA=y
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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+
CONFIG_SYSCTL=y
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CONFIG_ANON_INODES=y
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CONFIG_EMBEDDED=y
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CONFIG_SYSCTL_SYSCALL=y
214
+
# CONFIG_KALLSYMS is not set
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+
CONFIG_HOTPLUG=y
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+
CONFIG_PRINTK=y
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+
CONFIG_BUG=y
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+
# CONFIG_ELF_CORE is not set
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+
# CONFIG_PCSPKR_PLATFORM is not set
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CONFIG_BASE_FULL=y
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+
CONFIG_FUTEX=y
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CONFIG_EPOLL=y
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CONFIG_SIGNALFD=y
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+
CONFIG_TIMERFD=y
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CONFIG_EVENTFD=y
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CONFIG_SHMEM=y
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CONFIG_AIO=y
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+
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#
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+
# Performance Counters
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+
#
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+
# CONFIG_VM_EVENT_COUNTERS is not set
233
+
CONFIG_STRIP_ASM_SYMS=y
234
+
# CONFIG_COMPAT_BRK is not set
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+
CONFIG_SLAB=y
236
+
# CONFIG_SLUB is not set
237
+
# CONFIG_SLOB is not set
238
+
# CONFIG_PROFILING is not set
239
+
# CONFIG_MARKERS is not set
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+
CONFIG_HAVE_OPROFILE=y
241
+
# CONFIG_SLOW_WORK is not set
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+
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
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+
CONFIG_SLABINFO=y
244
+
CONFIG_RT_MUTEXES=y
245
+
CONFIG_BASE_SMALL=0
246
+
CONFIG_MODULES=y
247
+
# CONFIG_MODULE_FORCE_LOAD is not set
248
+
CONFIG_MODULE_UNLOAD=y
249
+
# CONFIG_MODULE_FORCE_UNLOAD is not set
250
+
# CONFIG_MODVERSIONS is not set
251
+
# CONFIG_MODULE_SRCVERSION_ALL is not set
252
+
CONFIG_BLOCK=y
253
+
# CONFIG_LBD is not set
254
+
# CONFIG_BLK_DEV_BSG is not set
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+
# CONFIG_BLK_DEV_INTEGRITY is not set
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+
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+
#
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+
# IO Schedulers
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#
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+
CONFIG_IOSCHED_NOOP=y
261
+
# CONFIG_IOSCHED_AS is not set
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+
CONFIG_IOSCHED_DEADLINE=y
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+
# CONFIG_IOSCHED_CFQ is not set
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+
# CONFIG_DEFAULT_AS is not set
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+
CONFIG_DEFAULT_DEADLINE=y
266
+
# CONFIG_DEFAULT_CFQ is not set
267
+
# CONFIG_DEFAULT_NOOP is not set
268
+
CONFIG_DEFAULT_IOSCHED="deadline"
269
+
CONFIG_PROBE_INITRD_HEADER=y
270
+
# CONFIG_FREEZER is not set
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+
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+
#
273
+
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
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+
#
275
+
# CONFIG_ARCH_SUPPORTS_MSI is not set
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+
CONFIG_MMU=y
277
+
# CONFIG_PCCARD is not set
278
+
279
+
#
280
+
# Executable file formats
281
+
#
282
+
CONFIG_BINFMT_ELF=y
283
+
# CONFIG_HAVE_AOUT is not set
284
+
# CONFIG_BINFMT_MISC is not set
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+
CONFIG_TRAD_SIGNALS=y
286
+
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+
#
288
+
# Power management options
289
+
#
290
+
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
291
+
CONFIG_ARCH_SUSPEND_POSSIBLE=y
292
+
# CONFIG_PM is not set
293
+
CONFIG_NET=y
294
+
295
+
#
296
+
# Networking options
297
+
#
298
+
CONFIG_PACKET=y
299
+
CONFIG_PACKET_MMAP=y
300
+
CONFIG_UNIX=y
301
+
# CONFIG_NET_KEY is not set
302
+
CONFIG_INET=y
303
+
CONFIG_IP_MULTICAST=y
304
+
CONFIG_IP_ADVANCED_ROUTER=y
305
+
CONFIG_ASK_IP_FIB_HASH=y
306
+
# CONFIG_IP_FIB_TRIE is not set
307
+
CONFIG_IP_FIB_HASH=y
308
+
CONFIG_IP_MULTIPLE_TABLES=y
309
+
CONFIG_IP_ROUTE_MULTIPATH=y
310
+
CONFIG_IP_ROUTE_VERBOSE=y
311
+
# CONFIG_IP_PNP is not set
312
+
# CONFIG_NET_IPIP is not set
313
+
# CONFIG_NET_IPGRE is not set
314
+
CONFIG_IP_MROUTE=y
315
+
# CONFIG_IP_PIMSM_V1 is not set
316
+
# CONFIG_IP_PIMSM_V2 is not set
317
+
CONFIG_ARPD=y
318
+
CONFIG_SYN_COOKIES=y
319
+
# CONFIG_INET_AH is not set
320
+
# CONFIG_INET_ESP is not set
321
+
# CONFIG_INET_IPCOMP is not set
322
+
# CONFIG_INET_XFRM_TUNNEL is not set
323
+
# CONFIG_INET_TUNNEL is not set
324
+
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
325
+
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
326
+
# CONFIG_INET_XFRM_MODE_BEET is not set
327
+
# CONFIG_INET_LRO is not set
328
+
# CONFIG_INET_DIAG is not set
329
+
CONFIG_TCP_CONG_ADVANCED=y
330
+
# CONFIG_TCP_CONG_BIC is not set
331
+
# CONFIG_TCP_CONG_CUBIC is not set
332
+
CONFIG_TCP_CONG_WESTWOOD=y
333
+
# CONFIG_TCP_CONG_HTCP is not set
334
+
# CONFIG_TCP_CONG_HSTCP is not set
335
+
# CONFIG_TCP_CONG_HYBLA is not set
336
+
# CONFIG_TCP_CONG_VEGAS is not set
337
+
# CONFIG_TCP_CONG_SCALABLE is not set
338
+
# CONFIG_TCP_CONG_LP is not set
339
+
# CONFIG_TCP_CONG_VENO is not set
340
+
# CONFIG_TCP_CONG_YEAH is not set
341
+
# CONFIG_TCP_CONG_ILLINOIS is not set
342
+
# CONFIG_DEFAULT_BIC is not set
343
+
# CONFIG_DEFAULT_CUBIC is not set
344
+
# CONFIG_DEFAULT_HTCP is not set
345
+
# CONFIG_DEFAULT_VEGAS is not set
346
+
CONFIG_DEFAULT_WESTWOOD=y
347
+
# CONFIG_DEFAULT_RENO is not set
348
+
CONFIG_DEFAULT_TCP_CONG="westwood"
349
+
# CONFIG_TCP_MD5SIG is not set
350
+
# CONFIG_IPV6 is not set
351
+
# CONFIG_NETWORK_SECMARK is not set
352
+
CONFIG_NETFILTER=y
353
+
# CONFIG_NETFILTER_DEBUG is not set
354
+
CONFIG_NETFILTER_ADVANCED=y
355
+
# CONFIG_BRIDGE_NETFILTER is not set
356
+
357
+
#
358
+
# Core Netfilter Configuration
359
+
#
360
+
# CONFIG_NETFILTER_NETLINK_QUEUE is not set
361
+
# CONFIG_NETFILTER_NETLINK_LOG is not set
362
+
CONFIG_NF_CONNTRACK=m
363
+
# CONFIG_NF_CT_ACCT is not set
364
+
CONFIG_NF_CONNTRACK_MARK=y
365
+
# CONFIG_NF_CONNTRACK_EVENTS is not set
366
+
# CONFIG_NF_CT_PROTO_DCCP is not set
367
+
# CONFIG_NF_CT_PROTO_SCTP is not set
368
+
# CONFIG_NF_CT_PROTO_UDPLITE is not set
369
+
# CONFIG_NF_CONNTRACK_AMANDA is not set
370
+
CONFIG_NF_CONNTRACK_FTP=m
371
+
# CONFIG_NF_CONNTRACK_H323 is not set
372
+
CONFIG_NF_CONNTRACK_IRC=m
373
+
# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
374
+
# CONFIG_NF_CONNTRACK_PPTP is not set
375
+
# CONFIG_NF_CONNTRACK_SANE is not set
376
+
# CONFIG_NF_CONNTRACK_SIP is not set
377
+
CONFIG_NF_CONNTRACK_TFTP=m
378
+
# CONFIG_NF_CT_NETLINK is not set
379
+
# CONFIG_NETFILTER_TPROXY is not set
380
+
CONFIG_NETFILTER_XTABLES=m
381
+
# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
382
+
# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
383
+
# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
384
+
# CONFIG_NETFILTER_XT_TARGET_HL is not set
385
+
# CONFIG_NETFILTER_XT_TARGET_LED is not set
386
+
# CONFIG_NETFILTER_XT_TARGET_MARK is not set
387
+
# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
388
+
# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
389
+
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
390
+
# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
391
+
# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
392
+
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
393
+
# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
394
+
# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
395
+
# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
396
+
# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
397
+
# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
398
+
# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
399
+
# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
400
+
# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
401
+
# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
402
+
# CONFIG_NETFILTER_XT_MATCH_ESP is not set
403
+
# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
404
+
# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
405
+
# CONFIG_NETFILTER_XT_MATCH_HL is not set
406
+
# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
407
+
# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
408
+
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
409
+
CONFIG_NETFILTER_XT_MATCH_MAC=m
410
+
# CONFIG_NETFILTER_XT_MATCH_MARK is not set
411
+
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
412
+
# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
413
+
# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
414
+
# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
415
+
# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
416
+
# CONFIG_NETFILTER_XT_MATCH_REALM is not set
417
+
# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
418
+
# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
419
+
CONFIG_NETFILTER_XT_MATCH_STATE=m
420
+
# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
421
+
# CONFIG_NETFILTER_XT_MATCH_STRING is not set
422
+
# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
423
+
# CONFIG_NETFILTER_XT_MATCH_TIME is not set
424
+
# CONFIG_NETFILTER_XT_MATCH_U32 is not set
425
+
# CONFIG_IP_VS is not set
426
+
427
+
#
428
+
# IP: Netfilter Configuration
429
+
#
430
+
CONFIG_NF_DEFRAG_IPV4=m
431
+
CONFIG_NF_CONNTRACK_IPV4=m
432
+
CONFIG_NF_CONNTRACK_PROC_COMPAT=y
433
+
# CONFIG_IP_NF_QUEUE is not set
434
+
CONFIG_IP_NF_IPTABLES=m
435
+
# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
436
+
# CONFIG_IP_NF_MATCH_AH is not set
437
+
# CONFIG_IP_NF_MATCH_ECN is not set
438
+
# CONFIG_IP_NF_MATCH_TTL is not set
439
+
CONFIG_IP_NF_FILTER=m
440
+
CONFIG_IP_NF_TARGET_REJECT=m
441
+
CONFIG_IP_NF_TARGET_LOG=m
442
+
# CONFIG_IP_NF_TARGET_ULOG is not set
443
+
CONFIG_NF_NAT=m
444
+
CONFIG_NF_NAT_NEEDED=y
445
+
CONFIG_IP_NF_TARGET_MASQUERADE=m
446
+
# CONFIG_IP_NF_TARGET_NETMAP is not set
447
+
# CONFIG_IP_NF_TARGET_REDIRECT is not set
448
+
# CONFIG_NF_NAT_SNMP_BASIC is not set
449
+
CONFIG_NF_NAT_FTP=m
450
+
CONFIG_NF_NAT_IRC=m
451
+
CONFIG_NF_NAT_TFTP=m
452
+
# CONFIG_NF_NAT_AMANDA is not set
453
+
# CONFIG_NF_NAT_PPTP is not set
454
+
# CONFIG_NF_NAT_H323 is not set
455
+
# CONFIG_NF_NAT_SIP is not set
456
+
CONFIG_IP_NF_MANGLE=m
457
+
# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
458
+
# CONFIG_IP_NF_TARGET_ECN is not set
459
+
# CONFIG_IP_NF_TARGET_TTL is not set
460
+
CONFIG_IP_NF_RAW=m
461
+
# CONFIG_IP_NF_ARPTABLES is not set
462
+
# CONFIG_IP_DCCP is not set
463
+
# CONFIG_IP_SCTP is not set
464
+
# CONFIG_TIPC is not set
465
+
CONFIG_ATM=m
466
+
# CONFIG_ATM_CLIP is not set
467
+
# CONFIG_ATM_LANE is not set
468
+
CONFIG_ATM_BR2684=m
469
+
CONFIG_ATM_BR2684_IPFILTER=y
470
+
CONFIG_STP=y
471
+
CONFIG_BRIDGE=y
472
+
# CONFIG_NET_DSA is not set
473
+
CONFIG_VLAN_8021Q=y
474
+
# CONFIG_VLAN_8021Q_GVRP is not set
475
+
# CONFIG_DECNET is not set
476
+
CONFIG_LLC=y
477
+
# CONFIG_LLC2 is not set
478
+
# CONFIG_IPX is not set
479
+
# CONFIG_ATALK is not set
480
+
# CONFIG_X25 is not set
481
+
# CONFIG_LAPB is not set
482
+
# CONFIG_ECONET is not set
483
+
# CONFIG_WAN_ROUTER is not set
484
+
# CONFIG_PHONET is not set
485
+
# CONFIG_IEEE802154 is not set
486
+
CONFIG_NET_SCHED=y
487
+
488
+
#
489
+
# Queueing/Scheduling
490
+
#
491
+
# CONFIG_NET_SCH_CBQ is not set
492
+
# CONFIG_NET_SCH_HTB is not set
493
+
# CONFIG_NET_SCH_HFSC is not set
494
+
# CONFIG_NET_SCH_ATM is not set
495
+
# CONFIG_NET_SCH_PRIO is not set
496
+
# CONFIG_NET_SCH_MULTIQ is not set
497
+
# CONFIG_NET_SCH_RED is not set
498
+
# CONFIG_NET_SCH_SFQ is not set
499
+
# CONFIG_NET_SCH_TEQL is not set
500
+
# CONFIG_NET_SCH_TBF is not set
501
+
# CONFIG_NET_SCH_GRED is not set
502
+
# CONFIG_NET_SCH_DSMARK is not set
503
+
# CONFIG_NET_SCH_NETEM is not set
504
+
# CONFIG_NET_SCH_DRR is not set
505
+
# CONFIG_NET_SCH_INGRESS is not set
506
+
507
+
#
508
+
# Classification
509
+
#
510
+
# CONFIG_NET_CLS_BASIC is not set
511
+
# CONFIG_NET_CLS_TCINDEX is not set
512
+
# CONFIG_NET_CLS_ROUTE4 is not set
513
+
# CONFIG_NET_CLS_FW is not set
514
+
# CONFIG_NET_CLS_U32 is not set
515
+
# CONFIG_NET_CLS_RSVP is not set
516
+
# CONFIG_NET_CLS_RSVP6 is not set
517
+
# CONFIG_NET_CLS_FLOW is not set
518
+
# CONFIG_NET_EMATCH is not set
519
+
CONFIG_NET_CLS_ACT=y
520
+
CONFIG_NET_ACT_POLICE=y
521
+
# CONFIG_NET_ACT_GACT is not set
522
+
# CONFIG_NET_ACT_MIRRED is not set
523
+
# CONFIG_NET_ACT_IPT is not set
524
+
# CONFIG_NET_ACT_NAT is not set
525
+
# CONFIG_NET_ACT_PEDIT is not set
526
+
# CONFIG_NET_ACT_SIMP is not set
527
+
# CONFIG_NET_ACT_SKBEDIT is not set
528
+
CONFIG_NET_SCH_FIFO=y
529
+
# CONFIG_DCB is not set
530
+
531
+
#
532
+
# Network testing
533
+
#
534
+
# CONFIG_NET_PKTGEN is not set
535
+
CONFIG_HAMRADIO=y
536
+
537
+
#
538
+
# Packet Radio protocols
539
+
#
540
+
# CONFIG_AX25 is not set
541
+
# CONFIG_CAN is not set
542
+
# CONFIG_IRDA is not set
543
+
# CONFIG_BT is not set
544
+
# CONFIG_AF_RXRPC is not set
545
+
CONFIG_FIB_RULES=y
546
+
CONFIG_WIRELESS=y
547
+
CONFIG_CFG80211=m
548
+
# CONFIG_CFG80211_REG_DEBUG is not set
549
+
# CONFIG_CFG80211_DEBUGFS is not set
550
+
# CONFIG_WIRELESS_OLD_REGULATORY is not set
551
+
CONFIG_WIRELESS_EXT=y
552
+
CONFIG_WIRELESS_EXT_SYSFS=y
553
+
# CONFIG_LIB80211 is not set
554
+
CONFIG_MAC80211=m
555
+
CONFIG_MAC80211_DEFAULT_PS=y
556
+
CONFIG_MAC80211_DEFAULT_PS_VALUE=1
557
+
558
+
#
559
+
# Rate control algorithm selection
560
+
#
561
+
CONFIG_MAC80211_RC_PID=y
562
+
CONFIG_MAC80211_RC_MINSTREL=y
563
+
CONFIG_MAC80211_RC_DEFAULT_PID=y
564
+
# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
565
+
CONFIG_MAC80211_RC_DEFAULT="pid"
566
+
# CONFIG_MAC80211_MESH is not set
567
+
# CONFIG_MAC80211_LEDS is not set
568
+
# CONFIG_MAC80211_DEBUGFS is not set
569
+
# CONFIG_MAC80211_DEBUG_MENU is not set
570
+
# CONFIG_WIMAX is not set
571
+
# CONFIG_RFKILL is not set
572
+
# CONFIG_NET_9P is not set
573
+
574
+
#
575
+
# Device Drivers
576
+
#
577
+
578
+
#
579
+
# Generic Driver Options
580
+
#
581
+
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
582
+
CONFIG_STANDALONE=y
583
+
CONFIG_PREVENT_FIRMWARE_BUILD=y
584
+
CONFIG_FW_LOADER=y
585
+
# CONFIG_FIRMWARE_IN_KERNEL is not set
586
+
CONFIG_EXTRA_FIRMWARE=""
587
+
# CONFIG_SYS_HYPERVISOR is not set
588
+
# CONFIG_CONNECTOR is not set
589
+
CONFIG_MTD=y
590
+
# CONFIG_MTD_DEBUG is not set
591
+
# CONFIG_MTD_CONCAT is not set
592
+
CONFIG_MTD_PARTITIONS=y
593
+
# CONFIG_MTD_TESTS is not set
594
+
# CONFIG_MTD_REDBOOT_PARTS is not set
595
+
# CONFIG_MTD_CMDLINE_PARTS is not set
596
+
# CONFIG_MTD_AR7_PARTS is not set
597
+
598
+
#
599
+
# User Modules And Translation Layers
600
+
#
601
+
CONFIG_MTD_CHAR=y
602
+
CONFIG_MTD_BLKDEVS=y
603
+
CONFIG_MTD_BLOCK=y
604
+
# CONFIG_FTL is not set
605
+
# CONFIG_NFTL is not set
606
+
# CONFIG_INFTL is not set
607
+
# CONFIG_RFD_FTL is not set
608
+
# CONFIG_SSFDC is not set
609
+
# CONFIG_MTD_OOPS is not set
610
+
611
+
#
612
+
# RAM/ROM/Flash chip drivers
613
+
#
614
+
CONFIG_MTD_CFI=y
615
+
# CONFIG_MTD_JEDECPROBE is not set
616
+
CONFIG_MTD_GEN_PROBE=y
617
+
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
618
+
CONFIG_MTD_MAP_BANK_WIDTH_1=y
619
+
CONFIG_MTD_MAP_BANK_WIDTH_2=y
620
+
CONFIG_MTD_MAP_BANK_WIDTH_4=y
621
+
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
622
+
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
623
+
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
624
+
CONFIG_MTD_CFI_I1=y
625
+
CONFIG_MTD_CFI_I2=y
626
+
# CONFIG_MTD_CFI_I4 is not set
627
+
# CONFIG_MTD_CFI_I8 is not set
628
+
CONFIG_MTD_CFI_INTELEXT=y
629
+
CONFIG_MTD_CFI_AMDSTD=y
630
+
CONFIG_MTD_CFI_STAA=y
631
+
CONFIG_MTD_CFI_UTIL=y
632
+
# CONFIG_MTD_RAM is not set
633
+
# CONFIG_MTD_ROM is not set
634
+
# CONFIG_MTD_ABSENT is not set
635
+
636
+
#
637
+
# Mapping drivers for chip access
638
+
#
639
+
CONFIG_MTD_COMPLEX_MAPPINGS=y
640
+
CONFIG_MTD_PHYSMAP=y
641
+
# CONFIG_MTD_PHYSMAP_COMPAT is not set
642
+
# CONFIG_MTD_PLATRAM is not set
643
+
644
+
#
645
+
# Self-contained MTD device drivers
646
+
#
647
+
# CONFIG_MTD_SLRAM is not set
648
+
# CONFIG_MTD_PHRAM is not set
649
+
# CONFIG_MTD_MTDRAM is not set
650
+
# CONFIG_MTD_BLOCK2MTD is not set
651
+
652
+
#
653
+
# Disk-On-Chip Device Drivers
654
+
#
655
+
# CONFIG_MTD_DOC2000 is not set
656
+
# CONFIG_MTD_DOC2001 is not set
657
+
# CONFIG_MTD_DOC2001PLUS is not set
658
+
# CONFIG_MTD_NAND is not set
659
+
# CONFIG_MTD_ONENAND is not set
660
+
661
+
#
662
+
# LPDDR flash memory drivers
663
+
#
664
+
# CONFIG_MTD_LPDDR is not set
665
+
666
+
#
667
+
# UBI - Unsorted block images
668
+
#
669
+
# CONFIG_MTD_UBI is not set
670
+
# CONFIG_PARPORT is not set
671
+
CONFIG_BLK_DEV=y
672
+
# CONFIG_BLK_DEV_COW_COMMON is not set
673
+
# CONFIG_BLK_DEV_LOOP is not set
674
+
# CONFIG_BLK_DEV_NBD is not set
675
+
# CONFIG_BLK_DEV_RAM is not set
676
+
# CONFIG_CDROM_PKTCDVD is not set
677
+
# CONFIG_ATA_OVER_ETH is not set
678
+
# CONFIG_BLK_DEV_HD is not set
679
+
CONFIG_MISC_DEVICES=y
680
+
# CONFIG_ENCLOSURE_SERVICES is not set
681
+
# CONFIG_C2PORT is not set
682
+
683
+
#
684
+
# EEPROM support
685
+
#
686
+
# CONFIG_EEPROM_93CX6 is not set
687
+
CONFIG_HAVE_IDE=y
688
+
# CONFIG_IDE is not set
689
+
690
+
#
691
+
# SCSI device support
692
+
#
693
+
# CONFIG_RAID_ATTRS is not set
694
+
# CONFIG_SCSI is not set
695
+
# CONFIG_SCSI_DMA is not set
696
+
# CONFIG_SCSI_NETLINK is not set
697
+
# CONFIG_ATA is not set
698
+
# CONFIG_MD is not set
699
+
CONFIG_NETDEVICES=y
700
+
# CONFIG_IFB is not set
701
+
# CONFIG_DUMMY is not set
702
+
# CONFIG_BONDING is not set
703
+
# CONFIG_MACVLAN is not set
704
+
# CONFIG_EQUALIZER is not set
705
+
# CONFIG_TUN is not set
706
+
# CONFIG_VETH is not set
707
+
CONFIG_PHYLIB=y
708
+
709
+
#
710
+
# MII PHY device drivers
711
+
#
712
+
# CONFIG_MARVELL_PHY is not set
713
+
# CONFIG_DAVICOM_PHY is not set
714
+
# CONFIG_QSEMI_PHY is not set
715
+
# CONFIG_LXT_PHY is not set
716
+
# CONFIG_CICADA_PHY is not set
717
+
# CONFIG_VITESSE_PHY is not set
718
+
# CONFIG_SMSC_PHY is not set
719
+
# CONFIG_BROADCOM_PHY is not set
720
+
# CONFIG_ICPLUS_PHY is not set
721
+
# CONFIG_REALTEK_PHY is not set
722
+
# CONFIG_NATIONAL_PHY is not set
723
+
# CONFIG_STE10XP is not set
724
+
# CONFIG_LSI_ET1011C_PHY is not set
725
+
CONFIG_FIXED_PHY=y
726
+
# CONFIG_MDIO_BITBANG is not set
727
+
CONFIG_NET_ETHERNET=y
728
+
CONFIG_MII=y
729
+
# CONFIG_AX88796 is not set
730
+
# CONFIG_SMC91X is not set
731
+
# CONFIG_DM9000 is not set
732
+
# CONFIG_ETHOC is not set
733
+
# CONFIG_DNET is not set
734
+
# CONFIG_IBM_NEW_EMAC_ZMII is not set
735
+
# CONFIG_IBM_NEW_EMAC_RGMII is not set
736
+
# CONFIG_IBM_NEW_EMAC_TAH is not set
737
+
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
738
+
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
739
+
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
740
+
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
741
+
# CONFIG_B44 is not set
742
+
# CONFIG_KS8842 is not set
743
+
CONFIG_CPMAC=y
744
+
# CONFIG_NETDEV_1000 is not set
745
+
# CONFIG_NETDEV_10000 is not set
746
+
747
+
#
748
+
# Wireless LAN
749
+
#
750
+
# CONFIG_WLAN_PRE80211 is not set
751
+
CONFIG_WLAN_80211=y
752
+
# CONFIG_LIBERTAS is not set
753
+
# CONFIG_LIBERTAS_THINFIRM is not set
754
+
# CONFIG_MAC80211_HWSIM is not set
755
+
# CONFIG_P54_COMMON is not set
756
+
# CONFIG_HOSTAP is not set
757
+
# CONFIG_B43 is not set
758
+
# CONFIG_B43LEGACY is not set
759
+
# CONFIG_RT2X00 is not set
760
+
761
+
#
762
+
# Enable WiMAX (Networking options) to see the WiMAX drivers
763
+
#
764
+
# CONFIG_WAN is not set
765
+
CONFIG_ATM_DRIVERS=y
766
+
# CONFIG_ATM_DUMMY is not set
767
+
# CONFIG_ATM_TCP is not set
768
+
CONFIG_PPP=m
769
+
CONFIG_PPP_MULTILINK=y
770
+
CONFIG_PPP_FILTER=y
771
+
CONFIG_PPP_ASYNC=m
772
+
# CONFIG_PPP_SYNC_TTY is not set
773
+
# CONFIG_PPP_DEFLATE is not set
774
+
# CONFIG_PPP_BSDCOMP is not set
775
+
# CONFIG_PPP_MPPE is not set
776
+
CONFIG_PPPOE=m
777
+
CONFIG_PPPOATM=m
778
+
# CONFIG_PPPOL2TP is not set
779
+
# CONFIG_SLIP is not set
780
+
CONFIG_SLHC=m
781
+
# CONFIG_NETCONSOLE is not set
782
+
# CONFIG_NETPOLL is not set
783
+
# CONFIG_NET_POLL_CONTROLLER is not set
784
+
# CONFIG_ISDN is not set
785
+
# CONFIG_PHONE is not set
786
+
787
+
#
788
+
# Input device support
789
+
#
790
+
# CONFIG_INPUT is not set
791
+
792
+
#
793
+
# Hardware I/O ports
794
+
#
795
+
# CONFIG_SERIO is not set
796
+
# CONFIG_GAMEPORT is not set
797
+
798
+
#
799
+
# Character devices
800
+
#
801
+
# CONFIG_VT is not set
802
+
# CONFIG_DEVKMEM is not set
803
+
# CONFIG_SERIAL_NONSTANDARD is not set
804
+
805
+
#
806
+
# Serial drivers
807
+
#
808
+
CONFIG_SERIAL_8250=y
809
+
CONFIG_SERIAL_8250_CONSOLE=y
810
+
CONFIG_SERIAL_8250_NR_UARTS=2
811
+
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
812
+
# CONFIG_SERIAL_8250_EXTENDED is not set
813
+
814
+
#
815
+
# Non-8250 serial port support
816
+
#
817
+
CONFIG_SERIAL_CORE=y
818
+
CONFIG_SERIAL_CORE_CONSOLE=y
819
+
CONFIG_UNIX98_PTYS=y
820
+
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
821
+
# CONFIG_LEGACY_PTYS is not set
822
+
# CONFIG_IPMI_HANDLER is not set
823
+
CONFIG_HW_RANDOM=y
824
+
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
825
+
# CONFIG_R3964 is not set
826
+
# CONFIG_RAW_DRIVER is not set
827
+
# CONFIG_TCG_TPM is not set
828
+
# CONFIG_I2C is not set
829
+
# CONFIG_SPI is not set
830
+
# CONFIG_W1 is not set
831
+
# CONFIG_POWER_SUPPLY is not set
832
+
# CONFIG_HWMON is not set
833
+
# CONFIG_THERMAL is not set
834
+
# CONFIG_THERMAL_HWMON is not set
835
+
CONFIG_WATCHDOG=y
836
+
# CONFIG_WATCHDOG_NOWAYOUT is not set
837
+
838
+
#
839
+
# Watchdog Device Drivers
840
+
#
841
+
# CONFIG_SOFT_WATCHDOG is not set
842
+
CONFIG_AR7_WDT=y
843
+
CONFIG_SSB_POSSIBLE=y
844
+
845
+
#
846
+
# Sonics Silicon Backplane
847
+
#
848
+
CONFIG_SSB=y
849
+
# CONFIG_SSB_SILENT is not set
850
+
# CONFIG_SSB_DEBUG is not set
851
+
CONFIG_SSB_SERIAL=y
852
+
CONFIG_SSB_DRIVER_MIPS=y
853
+
CONFIG_SSB_EMBEDDED=y
854
+
CONFIG_SSB_DRIVER_EXTIF=y
855
+
856
+
#
857
+
# Multifunction device drivers
858
+
#
859
+
# CONFIG_MFD_CORE is not set
860
+
# CONFIG_MFD_SM501 is not set
861
+
# CONFIG_HTC_PASIC3 is not set
862
+
# CONFIG_MFD_TMIO is not set
863
+
# CONFIG_REGULATOR is not set
864
+
# CONFIG_MEDIA_SUPPORT is not set
865
+
866
+
#
867
+
# Graphics support
868
+
#
869
+
# CONFIG_VGASTATE is not set
870
+
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
871
+
# CONFIG_FB is not set
872
+
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
873
+
874
+
#
875
+
# Display device support
876
+
#
877
+
# CONFIG_DISPLAY_SUPPORT is not set
878
+
# CONFIG_SOUND is not set
879
+
# CONFIG_USB_SUPPORT is not set
880
+
# CONFIG_MMC is not set
881
+
# CONFIG_MEMSTICK is not set
882
+
CONFIG_NEW_LEDS=y
883
+
CONFIG_LEDS_CLASS=y
884
+
885
+
#
886
+
# LED drivers
887
+
#
888
+
# CONFIG_LEDS_GPIO is not set
889
+
890
+
#
891
+
# LED Triggers
892
+
#
893
+
CONFIG_LEDS_TRIGGERS=y
894
+
CONFIG_LEDS_TRIGGER_TIMER=y
895
+
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
896
+
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
897
+
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
898
+
899
+
#
900
+
# iptables trigger is under Netfilter config (LED target)
901
+
#
902
+
# CONFIG_ACCESSIBILITY is not set
903
+
CONFIG_RTC_LIB=y
904
+
# CONFIG_RTC_CLASS is not set
905
+
# CONFIG_DMADEVICES is not set
906
+
# CONFIG_AUXDISPLAY is not set
907
+
# CONFIG_UIO is not set
908
+
909
+
#
910
+
# TI VLYNQ
911
+
#
912
+
CONFIG_VLYNQ=y
913
+
# CONFIG_STAGING is not set
914
+
915
+
#
916
+
# File systems
917
+
#
918
+
# CONFIG_EXT2_FS is not set
919
+
# CONFIG_EXT3_FS is not set
920
+
# CONFIG_EXT4_FS is not set
921
+
# CONFIG_REISERFS_FS is not set
922
+
# CONFIG_JFS_FS is not set
923
+
# CONFIG_FS_POSIX_ACL is not set
924
+
# CONFIG_XFS_FS is not set
925
+
# CONFIG_OCFS2_FS is not set
926
+
# CONFIG_BTRFS_FS is not set
927
+
CONFIG_FILE_LOCKING=y
928
+
CONFIG_FSNOTIFY=y
929
+
# CONFIG_DNOTIFY is not set
930
+
# CONFIG_INOTIFY is not set
931
+
CONFIG_INOTIFY_USER=y
932
+
# CONFIG_QUOTA is not set
933
+
# CONFIG_AUTOFS_FS is not set
934
+
# CONFIG_AUTOFS4_FS is not set
935
+
# CONFIG_FUSE_FS is not set
936
+
937
+
#
938
+
# Caches
939
+
#
940
+
# CONFIG_FSCACHE is not set
941
+
942
+
#
943
+
# CD-ROM/DVD Filesystems
944
+
#
945
+
# CONFIG_ISO9660_FS is not set
946
+
# CONFIG_UDF_FS is not set
947
+
948
+
#
949
+
# DOS/FAT/NT Filesystems
950
+
#
951
+
# CONFIG_MSDOS_FS is not set
952
+
# CONFIG_VFAT_FS is not set
953
+
# CONFIG_NTFS_FS is not set
954
+
955
+
#
956
+
# Pseudo filesystems
957
+
#
958
+
CONFIG_PROC_FS=y
959
+
CONFIG_PROC_KCORE=y
960
+
CONFIG_PROC_SYSCTL=y
961
+
# CONFIG_PROC_PAGE_MONITOR is not set
962
+
CONFIG_SYSFS=y
963
+
CONFIG_TMPFS=y
964
+
# CONFIG_TMPFS_POSIX_ACL is not set
965
+
# CONFIG_HUGETLB_PAGE is not set
966
+
# CONFIG_CONFIGFS_FS is not set
967
+
CONFIG_MISC_FILESYSTEMS=y
968
+
# CONFIG_ADFS_FS is not set
969
+
# CONFIG_AFFS_FS is not set
970
+
# CONFIG_HFS_FS is not set
971
+
# CONFIG_HFSPLUS_FS is not set
972
+
# CONFIG_BEFS_FS is not set
973
+
# CONFIG_BFS_FS is not set
974
+
# CONFIG_EFS_FS is not set
975
+
CONFIG_JFFS2_FS=y
976
+
CONFIG_JFFS2_FS_DEBUG=0
977
+
CONFIG_JFFS2_FS_WRITEBUFFER=y
978
+
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
979
+
CONFIG_JFFS2_SUMMARY=y
980
+
# CONFIG_JFFS2_FS_XATTR is not set
981
+
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
982
+
CONFIG_JFFS2_ZLIB=y
983
+
# CONFIG_JFFS2_LZO is not set
984
+
CONFIG_JFFS2_RTIME=y
985
+
# CONFIG_JFFS2_RUBIN is not set
986
+
# CONFIG_JFFS2_CMODE_NONE is not set
987
+
CONFIG_JFFS2_CMODE_PRIORITY=y
988
+
# CONFIG_JFFS2_CMODE_SIZE is not set
989
+
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
990
+
# CONFIG_CRAMFS is not set
991
+
CONFIG_SQUASHFS=y
992
+
# CONFIG_SQUASHFS_EMBEDDED is not set
993
+
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
994
+
# CONFIG_VXFS_FS is not set
995
+
# CONFIG_MINIX_FS is not set
996
+
# CONFIG_OMFS_FS is not set
997
+
# CONFIG_HPFS_FS is not set
998
+
# CONFIG_QNX4FS_FS is not set
999
+
# CONFIG_ROMFS_FS is not set
1000
+
# CONFIG_SYSV_FS is not set
1001
+
# CONFIG_UFS_FS is not set
1002
+
# CONFIG_NILFS2_FS is not set
1003
+
CONFIG_NETWORK_FILESYSTEMS=y
1004
+
# CONFIG_NFS_FS is not set
1005
+
# CONFIG_NFSD is not set
1006
+
# CONFIG_SMB_FS is not set
1007
+
# CONFIG_CIFS is not set
1008
+
# CONFIG_NCP_FS is not set
1009
+
# CONFIG_CODA_FS is not set
1010
+
# CONFIG_AFS_FS is not set
1011
+
1012
+
#
1013
+
# Partition Types
1014
+
#
1015
+
CONFIG_PARTITION_ADVANCED=y
1016
+
# CONFIG_ACORN_PARTITION is not set
1017
+
# CONFIG_OSF_PARTITION is not set
1018
+
# CONFIG_AMIGA_PARTITION is not set
1019
+
# CONFIG_ATARI_PARTITION is not set
1020
+
# CONFIG_MAC_PARTITION is not set
1021
+
CONFIG_MSDOS_PARTITION=y
1022
+
CONFIG_BSD_DISKLABEL=y
1023
+
# CONFIG_MINIX_SUBPARTITION is not set
1024
+
# CONFIG_SOLARIS_X86_PARTITION is not set
1025
+
# CONFIG_UNIXWARE_DISKLABEL is not set
1026
+
# CONFIG_LDM_PARTITION is not set
1027
+
# CONFIG_SGI_PARTITION is not set
1028
+
# CONFIG_ULTRIX_PARTITION is not set
1029
+
# CONFIG_SUN_PARTITION is not set
1030
+
# CONFIG_KARMA_PARTITION is not set
1031
+
# CONFIG_EFI_PARTITION is not set
1032
+
# CONFIG_SYSV68_PARTITION is not set
1033
+
# CONFIG_NLS is not set
1034
+
# CONFIG_DLM is not set
1035
+
1036
+
#
1037
+
# Kernel hacking
1038
+
#
1039
+
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1040
+
# CONFIG_PRINTK_TIME is not set
1041
+
CONFIG_ENABLE_WARN_DEPRECATED=y
1042
+
# CONFIG_ENABLE_MUST_CHECK is not set
1043
+
CONFIG_FRAME_WARN=1024
1044
+
# CONFIG_MAGIC_SYSRQ is not set
1045
+
# CONFIG_UNUSED_SYMBOLS is not set
1046
+
CONFIG_DEBUG_FS=y
1047
+
# CONFIG_HEADERS_CHECK is not set
1048
+
# CONFIG_DEBUG_KERNEL is not set
1049
+
# CONFIG_DEBUG_MEMORY_INIT is not set
1050
+
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1051
+
CONFIG_SYSCTL_SYSCALL_CHECK=y
1052
+
CONFIG_TRACING_SUPPORT=y
1053
+
# CONFIG_FTRACE is not set
1054
+
# CONFIG_DYNAMIC_DEBUG is not set
1055
+
# CONFIG_SAMPLES is not set
1056
+
CONFIG_HAVE_ARCH_KGDB=y
1057
+
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
1058
+
1059
+
#
1060
+
# Security options
1061
+
#
1062
+
# CONFIG_KEYS is not set
1063
+
# CONFIG_SECURITY is not set
1064
+
# CONFIG_SECURITYFS is not set
1065
+
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1066
+
CONFIG_CRYPTO=y
1067
+
1068
+
#
1069
+
# Crypto core or helper
1070
+
#
1071
+
# CONFIG_CRYPTO_FIPS is not set
1072
+
CONFIG_CRYPTO_ALGAPI=m
1073
+
CONFIG_CRYPTO_ALGAPI2=m
1074
+
CONFIG_CRYPTO_AEAD2=m
1075
+
CONFIG_CRYPTO_BLKCIPHER=m
1076
+
CONFIG_CRYPTO_BLKCIPHER2=m
1077
+
CONFIG_CRYPTO_HASH2=m
1078
+
CONFIG_CRYPTO_RNG2=m
1079
+
CONFIG_CRYPTO_PCOMP=m
1080
+
CONFIG_CRYPTO_MANAGER=m
1081
+
CONFIG_CRYPTO_MANAGER2=m
1082
+
# CONFIG_CRYPTO_GF128MUL is not set
1083
+
# CONFIG_CRYPTO_NULL is not set
1084
+
CONFIG_CRYPTO_WORKQUEUE=m
1085
+
# CONFIG_CRYPTO_CRYPTD is not set
1086
+
# CONFIG_CRYPTO_AUTHENC is not set
1087
+
# CONFIG_CRYPTO_TEST is not set
1088
+
1089
+
#
1090
+
# Authenticated Encryption with Associated Data
1091
+
#
1092
+
# CONFIG_CRYPTO_CCM is not set
1093
+
# CONFIG_CRYPTO_GCM is not set
1094
+
# CONFIG_CRYPTO_SEQIV is not set
1095
+
1096
+
#
1097
+
# Block modes
1098
+
#
1099
+
# CONFIG_CRYPTO_CBC is not set
1100
+
# CONFIG_CRYPTO_CTR is not set
1101
+
# CONFIG_CRYPTO_CTS is not set
1102
+
CONFIG_CRYPTO_ECB=m
1103
+
# CONFIG_CRYPTO_LRW is not set
1104
+
# CONFIG_CRYPTO_PCBC is not set
1105
+
# CONFIG_CRYPTO_XTS is not set
1106
+
1107
+
#
1108
+
# Hash modes
1109
+
#
1110
+
# CONFIG_CRYPTO_HMAC is not set
1111
+
# CONFIG_CRYPTO_XCBC is not set
1112
+
1113
+
#
1114
+
# Digest
1115
+
#
1116
+
# CONFIG_CRYPTO_CRC32C is not set
1117
+
# CONFIG_CRYPTO_MD4 is not set
1118
+
# CONFIG_CRYPTO_MD5 is not set
1119
+
# CONFIG_CRYPTO_MICHAEL_MIC is not set
1120
+
# CONFIG_CRYPTO_RMD128 is not set
1121
+
# CONFIG_CRYPTO_RMD160 is not set
1122
+
# CONFIG_CRYPTO_RMD256 is not set
1123
+
# CONFIG_CRYPTO_RMD320 is not set
1124
+
# CONFIG_CRYPTO_SHA1 is not set
1125
+
# CONFIG_CRYPTO_SHA256 is not set
1126
+
# CONFIG_CRYPTO_SHA512 is not set
1127
+
# CONFIG_CRYPTO_TGR192 is not set
1128
+
# CONFIG_CRYPTO_WP512 is not set
1129
+
1130
+
#
1131
+
# Ciphers
1132
+
#
1133
+
CONFIG_CRYPTO_AES=m
1134
+
# CONFIG_CRYPTO_ANUBIS is not set
1135
+
CONFIG_CRYPTO_ARC4=m
1136
+
# CONFIG_CRYPTO_BLOWFISH is not set
1137
+
# CONFIG_CRYPTO_CAMELLIA is not set
1138
+
# CONFIG_CRYPTO_CAST5 is not set
1139
+
# CONFIG_CRYPTO_CAST6 is not set
1140
+
# CONFIG_CRYPTO_DES is not set
1141
+
# CONFIG_CRYPTO_FCRYPT is not set
1142
+
# CONFIG_CRYPTO_KHAZAD is not set
1143
+
# CONFIG_CRYPTO_SALSA20 is not set
1144
+
# CONFIG_CRYPTO_SEED is not set
1145
+
# CONFIG_CRYPTO_SERPENT is not set
1146
+
# CONFIG_CRYPTO_TEA is not set
1147
+
# CONFIG_CRYPTO_TWOFISH is not set
1148
+
1149
+
#
1150
+
# Compression
1151
+
#
1152
+
# CONFIG_CRYPTO_DEFLATE is not set
1153
+
# CONFIG_CRYPTO_ZLIB is not set
1154
+
# CONFIG_CRYPTO_LZO is not set
1155
+
1156
+
#
1157
+
# Random Number Generation
1158
+
#
1159
+
# CONFIG_CRYPTO_ANSI_CPRNG is not set
1160
+
# CONFIG_CRYPTO_HW is not set
1161
+
# CONFIG_BINARY_PRINTF is not set
1162
+
1163
+
#
1164
+
# Library routines
1165
+
#
1166
+
CONFIG_BITREVERSE=y
1167
+
CONFIG_GENERIC_FIND_LAST_BIT=y
1168
+
CONFIG_CRC_CCITT=m
1169
+
# CONFIG_CRC16 is not set
1170
+
# CONFIG_CRC_T10DIF is not set
1171
+
# CONFIG_CRC_ITU_T is not set
1172
+
CONFIG_CRC32=y
1173
+
# CONFIG_CRC7 is not set
1174
+
# CONFIG_LIBCRC32C is not set
1175
+
CONFIG_ZLIB_INFLATE=y
1176
+
CONFIG_ZLIB_DEFLATE=y
1177
+
CONFIG_DECOMPRESS_GZIP=y
1178
+
CONFIG_DECOMPRESS_LZMA=y
1179
+
CONFIG_HAS_IOMEM=y
1180
+
CONFIG_HAS_IOPORT=y
1181
+
CONFIG_HAS_DMA=y
1182
+
CONFIG_NLATTR=y
+1
-1
arch/mips/gt64120/wrppmc/serial.c
+1
-1
arch/mips/gt64120/wrppmc/serial.c
···
1
1
/*
2
2
* Registration of WRPPMC UART platform device.
3
3
*
4
-
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+7
arch/mips/include/asm/amon.h
+7
arch/mips/include/asm/amon.h
+1
-1
arch/mips/include/asm/ds1287.h
+1
-1
arch/mips/include/asm/ds1287.h
···
1
1
/*
2
2
* DS1287 timer functions.
3
3
*
4
-
* Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+4
arch/mips/include/asm/elf.h
+4
arch/mips/include/asm/elf.h
···
316
316
extern int dump_task_regs(struct task_struct *, elf_gregset_t *);
317
317
extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
318
318
319
+
#ifndef ELF_CORE_COPY_REGS
319
320
#define ELF_CORE_COPY_REGS(elf_regs, regs) \
320
321
elf_dump_regs((elf_greg_t *)&(elf_regs), regs);
322
+
#endif
323
+
#ifndef ELF_CORE_COPY_TASK_REGS
321
324
#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
325
+
#endif
322
326
#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
323
327
dump_task_fpu(tsk, elf_fpregs)
324
328
+2
arch/mips/include/asm/gcmpregs.h
+2
arch/mips/include/asm/gcmpregs.h
+6
arch/mips/include/asm/gic.h
+6
arch/mips/include/asm/gic.h
···
20
20
#define GIC_TRIG_EDGE 1
21
21
#define GIC_TRIG_LEVEL 0
22
22
23
+
#if CONFIG_SMP
24
+
#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
25
+
#else
23
26
#define GIC_NUM_INTRS 32
27
+
#endif
24
28
25
29
#define MSK(n) ((1 << (n)) - 1)
26
30
#define REG32(addr) (*(volatile unsigned int *) (addr))
···
487
483
488
484
extern unsigned int gic_get_int(void);
489
485
extern void gic_send_ipi(unsigned int intr);
486
+
extern unsigned int plat_ipi_call_int_xlate(unsigned int);
487
+
extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
490
488
491
489
#endif /* _ASM_GICREGS_H */
+1
-1
arch/mips/include/asm/irq_gt641xx.h
+1
-1
arch/mips/include/asm/irq_gt641xx.h
···
1
1
/*
2
2
* Galileo/Marvell GT641xx IRQ definitions.
3
3
*
4
-
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+178
arch/mips/include/asm/mach-ar7/ar7.h
+178
arch/mips/include/asm/mach-ar7/ar7.h
···
1
+
/*
2
+
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
3
+
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License as published by
7
+
* the Free Software Foundation; either version 2 of the License, or
8
+
* (at your option) any later version.
9
+
*
10
+
* This program is distributed in the hope that it will be useful,
11
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
12
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13
+
* GNU General Public License for more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License
16
+
* along with this program; if not, write to the Free Software
17
+
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18
+
*/
19
+
20
+
#ifndef __AR7_H__
21
+
#define __AR7_H__
22
+
23
+
#include <linux/delay.h>
24
+
#include <linux/io.h>
25
+
#include <linux/errno.h>
26
+
27
+
#include <asm/addrspace.h>
28
+
29
+
#define AR7_SDRAM_BASE 0x14000000
30
+
31
+
#define AR7_REGS_BASE 0x08610000
32
+
33
+
#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
34
+
#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
35
+
/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
36
+
#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
37
+
#define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
38
+
#define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
39
+
#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
40
+
#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
41
+
#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
42
+
#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
43
+
#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
44
+
#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
45
+
#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
46
+
#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
47
+
#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
48
+
49
+
#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
50
+
#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
51
+
#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
52
+
53
+
#define AR7_RESET_PEREPHERIAL 0x0
54
+
#define AR7_RESET_SOFTWARE 0x4
55
+
#define AR7_RESET_STATUS 0x8
56
+
57
+
#define AR7_RESET_BIT_CPMAC_LO 17
58
+
#define AR7_RESET_BIT_CPMAC_HI 21
59
+
#define AR7_RESET_BIT_MDIO 22
60
+
#define AR7_RESET_BIT_EPHY 26
61
+
62
+
/* GPIO control registers */
63
+
#define AR7_GPIO_INPUT 0x0
64
+
#define AR7_GPIO_OUTPUT 0x4
65
+
#define AR7_GPIO_DIR 0x8
66
+
#define AR7_GPIO_ENABLE 0xc
67
+
68
+
#define AR7_CHIP_7100 0x18
69
+
#define AR7_CHIP_7200 0x2b
70
+
#define AR7_CHIP_7300 0x05
71
+
72
+
/* Interrupts */
73
+
#define AR7_IRQ_UART0 15
74
+
#define AR7_IRQ_UART1 16
75
+
76
+
/* Clocks */
77
+
#define AR7_AFE_CLOCK 35328000
78
+
#define AR7_REF_CLOCK 25000000
79
+
#define AR7_XTAL_CLOCK 24000000
80
+
81
+
struct plat_cpmac_data {
82
+
int reset_bit;
83
+
int power_bit;
84
+
u32 phy_mask;
85
+
char dev_addr[6];
86
+
};
87
+
88
+
struct plat_dsl_data {
89
+
int reset_bit_dsl;
90
+
int reset_bit_sar;
91
+
};
92
+
93
+
extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
94
+
95
+
static inline u16 ar7_chip_id(void)
96
+
{
97
+
return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
98
+
}
99
+
100
+
static inline u8 ar7_chip_rev(void)
101
+
{
102
+
return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
103
+
}
104
+
105
+
static inline int ar7_cpu_freq(void)
106
+
{
107
+
return ar7_cpu_clock;
108
+
}
109
+
110
+
static inline int ar7_bus_freq(void)
111
+
{
112
+
return ar7_bus_clock;
113
+
}
114
+
115
+
static inline int ar7_vbus_freq(void)
116
+
{
117
+
return ar7_bus_clock / 2;
118
+
}
119
+
#define ar7_cpmac_freq ar7_vbus_freq
120
+
121
+
static inline int ar7_dsp_freq(void)
122
+
{
123
+
return ar7_dsp_clock;
124
+
}
125
+
126
+
static inline int ar7_has_high_cpmac(void)
127
+
{
128
+
u16 chip_id = ar7_chip_id();
129
+
switch (chip_id) {
130
+
case AR7_CHIP_7100:
131
+
case AR7_CHIP_7200:
132
+
return 0;
133
+
case AR7_CHIP_7300:
134
+
return 1;
135
+
default:
136
+
return -ENXIO;
137
+
}
138
+
}
139
+
#define ar7_has_high_vlynq ar7_has_high_cpmac
140
+
#define ar7_has_second_uart ar7_has_high_cpmac
141
+
142
+
static inline void ar7_device_enable(u32 bit)
143
+
{
144
+
void *reset_reg =
145
+
(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
146
+
writel(readl(reset_reg) | (1 << bit), reset_reg);
147
+
msleep(20);
148
+
}
149
+
150
+
static inline void ar7_device_disable(u32 bit)
151
+
{
152
+
void *reset_reg =
153
+
(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
154
+
writel(readl(reset_reg) & ~(1 << bit), reset_reg);
155
+
msleep(20);
156
+
}
157
+
158
+
static inline void ar7_device_reset(u32 bit)
159
+
{
160
+
ar7_device_disable(bit);
161
+
ar7_device_enable(bit);
162
+
}
163
+
164
+
static inline void ar7_device_on(u32 bit)
165
+
{
166
+
void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
167
+
writel(readl(power_reg) | (1 << bit), power_reg);
168
+
msleep(20);
169
+
}
170
+
171
+
static inline void ar7_device_off(u32 bit)
172
+
{
173
+
void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
174
+
writel(readl(power_reg) & ~(1 << bit), power_reg);
175
+
msleep(20);
176
+
}
177
+
178
+
#endif /* __AR7_H__ */
+110
arch/mips/include/asm/mach-ar7/gpio.h
+110
arch/mips/include/asm/mach-ar7/gpio.h
···
1
+
/*
2
+
* Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify
5
+
* it under the terms of the GNU General Public License as published by
6
+
* the Free Software Foundation; either version 2 of the License, or
7
+
* (at your option) any later version.
8
+
*
9
+
* This program is distributed in the hope that it will be useful,
10
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
11
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12
+
* GNU General Public License for more details.
13
+
*
14
+
* You should have received a copy of the GNU General Public License
15
+
* along with this program; if not, write to the Free Software
16
+
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17
+
*/
18
+
19
+
#ifndef __AR7_GPIO_H__
20
+
#define __AR7_GPIO_H__
21
+
22
+
#include <asm/mach-ar7/ar7.h>
23
+
24
+
#define AR7_GPIO_MAX 32
25
+
26
+
extern int gpio_request(unsigned gpio, const char *label);
27
+
extern void gpio_free(unsigned gpio);
28
+
29
+
/* Common GPIO layer */
30
+
static inline int gpio_get_value(unsigned gpio)
31
+
{
32
+
void __iomem *gpio_in =
33
+
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT);
34
+
35
+
return readl(gpio_in) & (1 << gpio);
36
+
}
37
+
38
+
static inline void gpio_set_value(unsigned gpio, int value)
39
+
{
40
+
void __iomem *gpio_out =
41
+
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT);
42
+
unsigned tmp;
43
+
44
+
tmp = readl(gpio_out) & ~(1 << gpio);
45
+
if (value)
46
+
tmp |= 1 << gpio;
47
+
writel(tmp, gpio_out);
48
+
}
49
+
50
+
static inline int gpio_direction_input(unsigned gpio)
51
+
{
52
+
void __iomem *gpio_dir =
53
+
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
54
+
55
+
if (gpio >= AR7_GPIO_MAX)
56
+
return -EINVAL;
57
+
58
+
writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
59
+
60
+
return 0;
61
+
}
62
+
63
+
static inline int gpio_direction_output(unsigned gpio, int value)
64
+
{
65
+
void __iomem *gpio_dir =
66
+
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
67
+
68
+
if (gpio >= AR7_GPIO_MAX)
69
+
return -EINVAL;
70
+
71
+
gpio_set_value(gpio, value);
72
+
writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
73
+
74
+
return 0;
75
+
}
76
+
77
+
static inline int gpio_to_irq(unsigned gpio)
78
+
{
79
+
return -EINVAL;
80
+
}
81
+
82
+
static inline int irq_to_gpio(unsigned irq)
83
+
{
84
+
return -EINVAL;
85
+
}
86
+
87
+
/* Board specific GPIO functions */
88
+
static inline int ar7_gpio_enable(unsigned gpio)
89
+
{
90
+
void __iomem *gpio_en =
91
+
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
92
+
93
+
writel(readl(gpio_en) | (1 << gpio), gpio_en);
94
+
95
+
return 0;
96
+
}
97
+
98
+
static inline int ar7_gpio_disable(unsigned gpio)
99
+
{
100
+
void __iomem *gpio_en =
101
+
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
102
+
103
+
writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
104
+
105
+
return 0;
106
+
}
107
+
108
+
#include <asm-generic/gpio.h>
109
+
110
+
#endif
+16
arch/mips/include/asm/mach-ar7/irq.h
+16
arch/mips/include/asm/mach-ar7/irq.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Shamelessly copied from asm-mips/mach-emma2rh/
7
+
* Copyright (C) 2003 by Ralf Baechle
8
+
*/
9
+
#ifndef __ASM_AR7_IRQ_H
10
+
#define __ASM_AR7_IRQ_H
11
+
12
+
#define NR_IRQS 256
13
+
14
+
#include_next <irq.h>
15
+
16
+
#endif /* __ASM_AR7_IRQ_H */
+25
arch/mips/include/asm/mach-ar7/prom.h
+25
arch/mips/include/asm/mach-ar7/prom.h
···
1
+
/*
2
+
* Copyright (C) 2006, 2007 Florian Fainelli <florian@openwrt.org>
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify
5
+
* it under the terms of the GNU General Public License as published by
6
+
* the Free Software Foundation; either version 2 of the License, or
7
+
* (at your option) any later version.
8
+
*
9
+
* This program is distributed in the hope that it will be useful,
10
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
11
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12
+
* GNU General Public License for more details.
13
+
*
14
+
* You should have received a copy of the GNU General Public License
15
+
* along with this program; if not, write to the Free Software
16
+
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17
+
*/
18
+
19
+
#ifndef __PROM_H__
20
+
#define __PROM_H__
21
+
22
+
extern char *prom_getenv(const char *name);
23
+
extern void prom_meminit(void);
24
+
25
+
#endif /* __PROM_H__ */
+22
arch/mips/include/asm/mach-ar7/spaces.h
+22
arch/mips/include/asm/mach-ar7/spaces.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
7
+
* Copyright (C) 2000, 2002 Maciej W. Rozycki
8
+
* Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
9
+
*/
10
+
#ifndef _ASM_AR7_SPACES_H
11
+
#define _ASM_AR7_SPACES_H
12
+
13
+
/*
14
+
* This handles the memory map.
15
+
* We handle pages at KSEG0 for kernels with 32 bit address space.
16
+
*/
17
+
#define PAGE_OFFSET 0x94000000UL
18
+
#define PHYS_OFFSET 0x14000000UL
19
+
20
+
#include <asm/mach-generic/spaces.h>
21
+
22
+
#endif /* __ASM_AR7_SPACES_H */
+25
arch/mips/include/asm/mach-ar7/war.h
+25
arch/mips/include/asm/mach-ar7/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_AR7_WAR_H
9
+
#define __ASM_MIPS_MACH_AR7_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_AR7_WAR_H */
+1
-1
arch/mips/include/asm/mach-cobalt/irq.h
+1
-1
arch/mips/include/asm/mach-cobalt/irq.h
···
8
8
* Copyright (C) 1997 Cobalt Microserver
9
9
* Copyright (C) 1997, 2003 Ralf Baechle
10
10
* Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
11
-
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
11
+
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
12
12
*/
13
13
#ifndef _ASM_COBALT_IRQ_H
14
14
#define _ASM_COBALT_IRQ_H
+1
-1
arch/mips/include/asm/mach-cobalt/mach-gt64120.h
+1
-1
arch/mips/include/asm/mach-cobalt/mach-gt64120.h
+8
-1
arch/mips/include/asm/page.h
+8
-1
arch/mips/include/asm/page.h
···
165
165
166
166
#ifdef CONFIG_FLATMEM
167
167
168
-
#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr)
168
+
#define pfn_valid(pfn) \
169
+
({ \
170
+
unsigned long __pfn = (pfn); \
171
+
/* avoid <linux/bootmem.h> include hell */ \
172
+
extern unsigned long min_low_pfn; \
173
+
\
174
+
__pfn >= min_low_pfn && __pfn < max_mapnr; \
175
+
})
169
176
170
177
#elif defined(CONFIG_SPARSEMEM)
171
178
+1
-1
arch/mips/include/asm/reg.h
+1
-1
arch/mips/include/asm/reg.h
+6
-2
arch/mips/include/asm/swab.h
+6
-2
arch/mips/include/asm/swab.h
···
38
38
}
39
39
#define __arch_swab32 __arch_swab32
40
40
41
-
#ifdef CONFIG_CPU_MIPS64_R2
41
+
/*
42
+
* Having already checked for CONFIG_CPU_MIPSR2, enable the
43
+
* optimized version for 64-bit kernel on r2 CPUs.
44
+
*/
45
+
#ifdef CONFIG_64BIT
42
46
static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
43
47
{
44
48
__asm__(
···
54
50
return x;
55
51
}
56
52
#define __arch_swab64 __arch_swab64
57
-
#endif /* CONFIG_CPU_MIPS64_R2 */
53
+
#endif /* CONFIG_64BIT */
58
54
#endif /* CONFIG_CPU_MIPSR2 */
59
55
#endif /* _ASM_SWAB_H */
+12
-6
arch/mips/include/asm/unistd.h
+12
-6
arch/mips/include/asm/unistd.h
···
352
352
#define __NR_inotify_init1 (__NR_Linux + 329)
353
353
#define __NR_preadv (__NR_Linux + 330)
354
354
#define __NR_pwritev (__NR_Linux + 331)
355
+
#define __NR_rt_tgsigqueueinfo (__NR_Linux + 332)
356
+
#define __NR_perf_counter_open (__NR_Linux + 333)
355
357
356
358
/*
357
359
* Offset of the last Linux o32 flavoured syscall
358
360
*/
359
-
#define __NR_Linux_syscalls 331
361
+
#define __NR_Linux_syscalls 333
360
362
361
363
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
362
364
363
365
#define __NR_O32_Linux 4000
364
-
#define __NR_O32_Linux_syscalls 331
366
+
#define __NR_O32_Linux_syscalls 333
365
367
366
368
#if _MIPS_SIM == _MIPS_SIM_ABI64
367
369
···
662
660
#define __NR_inotify_init1 (__NR_Linux + 288)
663
661
#define __NR_preadv (__NR_Linux + 289)
664
662
#define __NR_pwritev (__NR_Linux + 290)
663
+
#define __NR_rt_tgsigqueueinfo (__NR_Linux + 291)
664
+
#define __NR_perf_counter_open (__NR_Linux + 292)
665
665
666
666
/*
667
667
* Offset of the last Linux 64-bit flavoured syscall
668
668
*/
669
-
#define __NR_Linux_syscalls 290
669
+
#define __NR_Linux_syscalls 292
670
670
671
671
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
672
672
673
673
#define __NR_64_Linux 5000
674
-
#define __NR_64_Linux_syscalls 290
674
+
#define __NR_64_Linux_syscalls 292
675
675
676
676
#if _MIPS_SIM == _MIPS_SIM_NABI32
677
677
···
976
972
#define __NR_inotify_init1 (__NR_Linux + 292)
977
973
#define __NR_preadv (__NR_Linux + 293)
978
974
#define __NR_pwritev (__NR_Linux + 294)
975
+
#define __NR_rt_tgsigqueueinfo (__NR_Linux + 295)
976
+
#define __NR_perf_counter_open (__NR_Linux + 296)
979
977
980
978
/*
981
979
* Offset of the last N32 flavoured syscall
982
980
*/
983
-
#define __NR_Linux_syscalls 294
981
+
#define __NR_Linux_syscalls 296
984
982
985
983
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
986
984
987
985
#define __NR_N32_Linux 6000
988
-
#define __NR_N32_Linux_syscalls 294
986
+
#define __NR_N32_Linux_syscalls 296
989
987
990
988
#ifdef __KERNEL__
991
989
+1
-1
arch/mips/include/asm/vr41xx/capcella.h
+1
-1
arch/mips/include/asm/vr41xx/capcella.h
···
1
1
/*
2
2
* capcella.h, Include file for ZAO Networks Capcella.
3
3
*
4
-
* Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+3
-19
arch/mips/include/asm/vr41xx/giu.h
+3
-19
arch/mips/include/asm/vr41xx/giu.h
···
1
1
/*
2
2
* Include file for NEC VR4100 series General-purpose I/O Unit.
3
3
*
4
-
* Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2005-2009 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
···
41
41
IRQ_SIGNAL_HOLD,
42
42
} irq_signal_t;
43
43
44
-
extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal);
44
+
extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
45
+
irq_signal_t signal);
45
46
46
47
typedef enum {
47
48
IRQ_LEVEL_LOW,
···
50
49
} irq_level_t;
51
50
52
51
extern void vr41xx_set_irq_level(unsigned int pin, irq_level_t level);
53
-
54
-
typedef enum {
55
-
GPIO_DATA_LOW,
56
-
GPIO_DATA_HIGH,
57
-
GPIO_DATA_INVAL,
58
-
} gpio_data_t;
59
-
60
-
extern gpio_data_t vr41xx_gpio_get_pin(unsigned int pin);
61
-
extern int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data);
62
-
63
-
typedef enum {
64
-
GPIO_INPUT,
65
-
GPIO_OUTPUT,
66
-
GPIO_OUTPUT_DISABLE,
67
-
} gpio_direction_t;
68
-
69
-
extern int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir);
70
52
71
53
typedef enum {
72
54
GPIO_PULL_DOWN,
+1
-1
arch/mips/include/asm/vr41xx/irq.h
+1
-1
arch/mips/include/asm/vr41xx/irq.h
···
7
7
* Copyright (C) 2001, 2002 Paul Mundt
8
8
* Copyright (C) 2002 MontaVista Software, Inc.
9
9
* Copyright (C) 2002 TimeSys Corp.
10
-
* Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
10
+
* Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
11
11
*
12
12
* This program is free software; you can redistribute it and/or modify it
13
13
* under the terms of the GNU General Public License as published by the
+1
-1
arch/mips/include/asm/vr41xx/mpc30x.h
+1
-1
arch/mips/include/asm/vr41xx/mpc30x.h
···
1
1
/*
2
2
* mpc30x.h, Include file for Victor MP-C303/304.
3
3
*
4
-
* Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/include/asm/vr41xx/pci.h
+1
-1
arch/mips/include/asm/vr41xx/pci.h
···
1
1
/*
2
2
* Include file for NEC VR4100 series PCI Control Unit.
3
3
*
4
-
* Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/include/asm/vr41xx/siu.h
+1
-1
arch/mips/include/asm/vr41xx/siu.h
···
1
1
/*
2
2
* Include file for NEC VR4100 series Serial Interface Unit.
3
3
*
4
-
* Copyright (C) 2005-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2005-2008 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/include/asm/vr41xx/tb0219.h
+1
-1
arch/mips/include/asm/vr41xx/tb0219.h
···
1
1
/*
2
2
* tb0219.h, Include file for TANBAC TB0219.
3
3
*
4
-
* Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* Modified for TANBAC TB0219:
7
7
* Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>
+1
-1
arch/mips/include/asm/vr41xx/tb0226.h
+1
-1
arch/mips/include/asm/vr41xx/tb0226.h
···
1
1
/*
2
2
* tb0226.h, Include file for TANBAC TB0226.
3
3
*
4
-
* Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/include/asm/vr41xx/vr41xx.h
+1
-1
arch/mips/include/asm/vr41xx/vr41xx.h
···
7
7
* Copyright (C) 2001, 2002 Paul Mundt
8
8
* Copyright (C) 2002 MontaVista Software, Inc.
9
9
* Copyright (C) 2002 TimeSys Corp.
10
-
* Copyright (C) 2003-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
10
+
* Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
11
11
*
12
12
* This program is free software; you can redistribute it and/or modify it
13
13
* under the terms of the GNU General Public License as published by the
+17
-3
arch/mips/kernel/binfmt_elfo32.c
+17
-3
arch/mips/kernel/binfmt_elfo32.c
···
53
53
#define ELF_ET_DYN_BASE (TASK32_SIZE / 3 * 2)
54
54
55
55
#include <asm/processor.h>
56
+
57
+
/*
58
+
* When this file is selected, we are definitely running a 64bit kernel.
59
+
* So using the right regs define in asm/reg.h
60
+
*/
61
+
#define WANT_COMPAT_REG_H
62
+
63
+
/* These MUST be defined before elf.h gets included */
64
+
extern void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs);
65
+
#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs);
66
+
#define ELF_CORE_COPY_TASK_REGS(_tsk, _dest) \
67
+
({ \
68
+
int __res = 1; \
69
+
elf32_core_copy_regs(*(_dest), task_pt_regs(_tsk)); \
70
+
__res; \
71
+
})
72
+
56
73
#include <linux/module.h>
57
74
#include <linux/elfcore.h>
58
75
#include <linux/compat.h>
···
126
109
value->tv_sec = div_u64_rem(nsec, NSEC_PER_SEC, &rem);
127
110
value->tv_usec = rem / NSEC_PER_USEC;
128
111
}
129
-
130
-
#undef ELF_CORE_COPY_REGS
131
-
#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs);
132
112
133
113
void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs)
134
114
{
+1
-1
arch/mips/kernel/cevt-ds1287.c
+1
-1
arch/mips/kernel/cevt-ds1287.c
···
1
1
/*
2
2
* DS1287 clockevent driver
3
3
*
4
-
* Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/kernel/cevt-gt641xx.c
+1
-1
arch/mips/kernel/cevt-gt641xx.c
···
1
1
/*
2
2
* GT641xx clockevent routines.
3
3
*
4
-
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/kernel/csrc-ioasic.c
+1
-1
arch/mips/kernel/csrc-ioasic.c
···
1
1
/*
2
2
* DEC I/O ASIC's counter clocksource
3
3
*
4
-
* Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+8
-11
arch/mips/kernel/irq-gic.c
+8
-11
arch/mips/kernel/irq-gic.c
···
107
107
{
108
108
pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
109
109
irq -= _irqbase;
110
-
/* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */
111
-
GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))),
112
-
1 << (irq % 32));
110
+
GIC_SET_INTR_MASK(irq, 1);
113
111
return 0;
114
112
}
115
113
···
118
120
#endif
119
121
pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
120
122
irq -= _irqbase;
121
-
GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))),
122
-
1 << (irq % 32));
123
+
GIC_CLR_INTR_MASK(irq, 1);
123
124
124
125
if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) {
125
126
if (!gic_wedgeb2bok)
···
135
138
{
136
139
pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
137
140
irq -= _irqbase;
138
-
/* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */
139
-
GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))),
140
-
1 << (irq % 32));
141
+
GIC_CLR_INTR_MASK(irq, 1);
141
142
}
142
143
143
144
static void gic_unmask_irq(unsigned int irq)
144
145
{
145
146
pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
146
147
irq -= _irqbase;
147
-
/* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */
148
-
GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))),
149
-
1 << (irq % 32));
148
+
GIC_SET_INTR_MASK(irq, 1);
150
149
}
151
150
152
151
#ifdef CONFIG_SMP
···
245
252
for (i = 0; i < _mapsize; i++) {
246
253
cpu = _intrmap[i].cpunum;
247
254
if (cpu == X)
255
+
continue;
256
+
257
+
if (cpu == 0 && i != 0 && _intrmap[i].intrnum == 0 &&
258
+
_intrmap[i].ipiflag == 0)
248
259
continue;
249
260
250
261
setup_intr(_intrmap[i].intrnum,
+1
-1
arch/mips/kernel/irq-gt641xx.c
+1
-1
arch/mips/kernel/irq-gt641xx.c
···
1
1
/*
2
2
* GT641xx IRQ routines.
3
3
*
4
-
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+2
arch/mips/kernel/scall32-o32.S
+2
arch/mips/kernel/scall32-o32.S
+2
arch/mips/kernel/scall64-64.S
+2
arch/mips/kernel/scall64-64.S
+2
arch/mips/kernel/scall64-n32.S
+2
arch/mips/kernel/scall64-n32.S
+2
arch/mips/kernel/scall64-o32.S
+2
arch/mips/kernel/scall64-o32.S
+5
-61
arch/mips/kernel/smp-cmp.c
+5
-61
arch/mips/kernel/smp-cmp.c
···
37
37
#include <asm/mipsregs.h>
38
38
#include <asm/mipsmtregs.h>
39
39
#include <asm/mips_mt.h>
40
-
41
-
/*
42
-
* Crude manipulation of the CPU masks to control which
43
-
* which CPU's are brought online during initialisation
44
-
*
45
-
* Beware... this needs to be called after CPU discovery
46
-
* but before CPU bringup
47
-
*/
48
-
static int __init allowcpus(char *str)
49
-
{
50
-
cpumask_t cpu_allow_map;
51
-
char buf[256];
52
-
int len;
53
-
54
-
cpus_clear(cpu_allow_map);
55
-
if (cpulist_parse(str, &cpu_allow_map) == 0) {
56
-
cpu_set(0, cpu_allow_map);
57
-
cpus_and(cpu_possible_map, cpu_possible_map, cpu_allow_map);
58
-
len = cpulist_scnprintf(buf, sizeof(buf)-1, &cpu_possible_map);
59
-
buf[len] = '\0';
60
-
pr_debug("Allowable CPUs: %s\n", buf);
61
-
return 1;
62
-
} else
63
-
return 0;
64
-
}
65
-
__setup("allowcpus=", allowcpus);
40
+
#include <asm/amon.h>
41
+
#include <asm/gic.h>
66
42
67
43
static void ipi_call_function(unsigned int cpu)
68
44
{
69
-
unsigned int action = 0;
70
-
71
45
pr_debug("CPU%d: %s cpu %d status %08x\n",
72
46
smp_processor_id(), __func__, cpu, read_c0_status());
73
47
74
-
switch (cpu) {
75
-
case 0:
76
-
action = GIC_IPI_EXT_INTR_CALLFNC_VPE0;
77
-
break;
78
-
case 1:
79
-
action = GIC_IPI_EXT_INTR_CALLFNC_VPE1;
80
-
break;
81
-
case 2:
82
-
action = GIC_IPI_EXT_INTR_CALLFNC_VPE2;
83
-
break;
84
-
case 3:
85
-
action = GIC_IPI_EXT_INTR_CALLFNC_VPE3;
86
-
break;
87
-
}
88
-
gic_send_ipi(action);
48
+
gic_send_ipi(plat_ipi_call_int_xlate(cpu));
89
49
}
90
50
91
51
92
52
static void ipi_resched(unsigned int cpu)
93
53
{
94
-
unsigned int action = 0;
95
-
96
54
pr_debug("CPU%d: %s cpu %d status %08x\n",
97
55
smp_processor_id(), __func__, cpu, read_c0_status());
98
56
99
-
switch (cpu) {
100
-
case 0:
101
-
action = GIC_IPI_EXT_INTR_RESCHED_VPE0;
102
-
break;
103
-
case 1:
104
-
action = GIC_IPI_EXT_INTR_RESCHED_VPE1;
105
-
break;
106
-
case 2:
107
-
action = GIC_IPI_EXT_INTR_RESCHED_VPE2;
108
-
break;
109
-
case 3:
110
-
action = GIC_IPI_EXT_INTR_RESCHED_VPE3;
111
-
break;
112
-
}
113
-
gic_send_ipi(action);
57
+
gic_send_ipi(plat_ipi_resched_int_xlate(cpu));
114
58
}
115
59
116
60
/*
···
150
206
(unsigned long)(gp + sizeof(struct thread_info)));
151
207
#endif
152
208
153
-
amon_cpu_start(cpu, pc, sp, gp, a0);
209
+
amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0);
154
210
}
155
211
156
212
/*
+16
-15
arch/mips/kernel/sync-r4k.c
+16
-15
arch/mips/kernel/sync-r4k.c
···
1
1
/*
2
2
* Count register synchronisation.
3
3
*
4
-
* All CPUs will have their count registers synchronised to the CPU0 expirelo
4
+
* All CPUs will have their count registers synchronised to the CPU0 next time
5
5
* value. This can cause a small timewarp for CPU0. All other CPU's should
6
6
* not have done anything significant (but they may have had interrupts
7
7
* enabled briefly - prom_smp_finish() should not be responsible for enabling
···
13
13
#include <linux/kernel.h>
14
14
#include <linux/init.h>
15
15
#include <linux/irqflags.h>
16
-
#include <linux/r4k-timer.h>
16
+
#include <linux/cpumask.h>
17
17
18
+
#include <asm/r4k-timer.h>
18
19
#include <asm/atomic.h>
19
20
#include <asm/barrier.h>
20
-
#include <asm/cpumask.h>
21
21
#include <asm/mipsregs.h>
22
22
23
-
static atomic_t __initdata count_start_flag = ATOMIC_INIT(0);
24
-
static atomic_t __initdata count_count_start = ATOMIC_INIT(0);
25
-
static atomic_t __initdata count_count_stop = ATOMIC_INIT(0);
23
+
static atomic_t __cpuinitdata count_start_flag = ATOMIC_INIT(0);
24
+
static atomic_t __cpuinitdata count_count_start = ATOMIC_INIT(0);
25
+
static atomic_t __cpuinitdata count_count_stop = ATOMIC_INIT(0);
26
+
static atomic_t __cpuinitdata count_reference = ATOMIC_INIT(0);
26
27
27
28
#define COUNTON 100
28
29
#define NR_LOOPS 5
29
30
30
-
void __init synchronise_count_master(void)
31
+
void __cpuinit synchronise_count_master(void)
31
32
{
32
33
int i;
33
34
unsigned long flags;
···
43
42
return;
44
43
#endif
45
44
46
-
pr_info("Checking COUNT synchronization across %u CPUs: ",
47
-
num_online_cpus());
45
+
printk(KERN_INFO "Synchronize counters across %u CPUs: ",
46
+
num_online_cpus());
48
47
49
48
local_irq_save(flags);
50
49
51
50
/*
52
51
* Notify the slaves that it's time to start
53
52
*/
53
+
atomic_set(&count_reference, read_c0_count());
54
54
atomic_set(&count_start_flag, 1);
55
55
smp_wmb();
56
56
57
-
/* Count will be initialised to expirelo for all CPU's */
58
-
initcount = expirelo;
57
+
/* Count will be initialised to current timer for all CPU's */
58
+
initcount = read_c0_count();
59
59
60
60
/*
61
61
* We loop a few times to get a primed instruction cache,
···
108
106
printk("done.\n");
109
107
}
110
108
111
-
void __init synchronise_count_slave(void)
109
+
void __cpuinit synchronise_count_slave(void)
112
110
{
113
111
int i;
114
112
unsigned long flags;
···
133
131
while (!atomic_read(&count_start_flag))
134
132
mb();
135
133
136
-
/* Count will be initialised to expirelo for all CPU's */
137
-
initcount = expirelo;
134
+
/* Count will be initialised to next expire for all CPU's */
135
+
initcount = atomic_read(&count_reference);
138
136
139
137
ncpus = num_online_cpus();
140
138
for (i = 0; i < NR_LOOPS; i++) {
···
158
156
local_irq_restore(flags);
159
157
}
160
158
#undef NR_LOOPS
161
-
#endif
+1
-1
arch/mips/kernel/vpe.c
+1
-1
arch/mips/kernel/vpe.c
+13
-1
arch/mips/mti-malta/malta-init.c
+13
-1
arch/mips/mti-malta/malta-init.c
···
30
30
#include <asm/cacheflush.h>
31
31
#include <asm/traps.h>
32
32
33
+
#include <asm/gcmpregs.h>
33
34
#include <asm/mips-boards/prom.h>
34
35
#include <asm/mips-boards/generic.h>
35
36
#include <asm/mips-boards/bonito64.h>
···
193
192
194
193
void __init prom_init(void)
195
194
{
195
+
int result;
196
+
196
197
prom_argc = fw_arg0;
197
198
_prom_argv = (int *) fw_arg1;
198
199
_prom_envp = (int *) fw_arg2;
···
361
358
#ifdef CONFIG_SERIAL_8250_CONSOLE
362
359
console_config();
363
360
#endif
361
+
/* Early detection of CMP support */
362
+
result = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
363
+
364
364
#ifdef CONFIG_MIPS_CMP
365
-
register_smp_ops(&cmp_smp_ops);
365
+
if (result)
366
+
register_smp_ops(&cmp_smp_ops);
366
367
#endif
367
368
#ifdef CONFIG_MIPS_MT_SMP
369
+
#ifdef CONFIG_MIPS_CMP
370
+
if (!result)
371
+
register_smp_ops(&vsmp_smp_ops);
372
+
#else
368
373
register_smp_ops(&vsmp_smp_ops);
374
+
#endif
369
375
#endif
370
376
#ifdef CONFIG_MIPS_MT_SMTC
371
377
register_smp_ops(&msmtc_smp_ops);
+47
-42
arch/mips/mti-malta/malta-int.c
+47
-42
arch/mips/mti-malta/malta-int.c
···
331
331
.flags = IRQF_DISABLED|IRQF_PERCPU,
332
332
.name = "IPI_call"
333
333
};
334
+
335
+
static int gic_resched_int_base;
336
+
static int gic_call_int_base;
337
+
#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
338
+
#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
339
+
340
+
unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
341
+
{
342
+
return GIC_CALL_INT(cpu);
343
+
}
344
+
345
+
unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
346
+
{
347
+
return GIC_RESCHED_INT(cpu);
348
+
}
334
349
#endif /* CONFIG_MIPS_MT_SMP */
335
350
336
351
static struct irqaction i8259irq = {
···
385
370
* Interrupts and CPUs/Core Interrupts. The nature of the External
386
371
* Interrupts is also defined here - polarity/trigger.
387
372
*/
388
-
static struct gic_intr_map gic_intr_map[] = {
373
+
static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
389
374
{ GIC_EXT_INTR(0), X, X, X, X, 0 },
390
375
{ GIC_EXT_INTR(1), X, X, X, X, 0 },
391
376
{ GIC_EXT_INTR(2), X, X, X, X, 0 },
···
402
387
{ GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
403
388
{ GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
404
389
{ GIC_EXT_INTR(15), X, X, X, X, 0 },
405
-
{ GIC_EXT_INTR(16), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
406
-
{ GIC_EXT_INTR(17), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
407
-
{ GIC_EXT_INTR(18), 1, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
408
-
{ GIC_EXT_INTR(19), 1, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
409
-
{ GIC_EXT_INTR(20), 2, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
410
-
{ GIC_EXT_INTR(21), 2, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
411
-
{ GIC_EXT_INTR(22), 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
412
-
{ GIC_EXT_INTR(23), 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
390
+
/* This is the end of the general interrupts now we do IPI ones */
413
391
};
414
392
#endif
415
393
416
394
/*
417
395
* GCMP needs to be detected before any SMP initialisation
418
396
*/
419
-
static int __init gcmp_probe(unsigned long addr, unsigned long size)
397
+
int __init gcmp_probe(unsigned long addr, unsigned long size)
420
398
{
421
399
if (gcmp_present >= 0)
422
400
return gcmp_present;
···
424
416
}
425
417
426
418
#if defined(CONFIG_MIPS_MT_SMP)
419
+
static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
420
+
{
421
+
int intr = baseintr + cpu;
422
+
gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr);
423
+
gic_intr_map[intr].cpunum = cpu;
424
+
gic_intr_map[intr].pin = cpupin;
425
+
gic_intr_map[intr].polarity = GIC_POL_POS;
426
+
gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
427
+
gic_intr_map[intr].ipiflag = 1;
428
+
ipi_map[cpu] |= (1 << (cpupin + 2));
429
+
}
430
+
427
431
static void __init fill_ipi_map(void)
428
432
{
429
-
int i;
433
+
int cpu;
430
434
431
-
for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
432
-
if (gic_intr_map[i].ipiflag && (gic_intr_map[i].cpunum != X))
433
-
ipi_map[gic_intr_map[i].cpunum] |=
434
-
(1 << (gic_intr_map[i].pin + 2));
435
+
for (cpu = 0; cpu < NR_CPUS; cpu++) {
436
+
fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
437
+
fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
435
438
}
436
439
}
437
440
#endif
438
441
439
442
void __init arch_init_irq(void)
440
443
{
441
-
int gic_present, gcmp_present;
442
-
443
444
init_i8259_irqs();
444
445
445
446
if (!cpu_has_veic)
446
447
mips_cpu_irq_init();
447
448
448
-
gcmp_present = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
449
449
if (gcmp_present) {
450
450
GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
451
451
gic_present = 1;
···
530
514
if (gic_present) {
531
515
/* FIXME */
532
516
int i;
533
-
struct {
534
-
unsigned int resched;
535
-
unsigned int call;
536
-
} ipiirq[] = {
537
-
{
538
-
.resched = GIC_IPI_EXT_INTR_RESCHED_VPE0,
539
-
.call = GIC_IPI_EXT_INTR_CALLFNC_VPE0},
540
-
{
541
-
.resched = GIC_IPI_EXT_INTR_RESCHED_VPE1,
542
-
.call = GIC_IPI_EXT_INTR_CALLFNC_VPE1
543
-
}, {
544
-
.resched = GIC_IPI_EXT_INTR_RESCHED_VPE2,
545
-
.call = GIC_IPI_EXT_INTR_CALLFNC_VPE2
546
-
}, {
547
-
.resched = GIC_IPI_EXT_INTR_RESCHED_VPE3,
548
-
.call = GIC_IPI_EXT_INTR_CALLFNC_VPE3
549
-
}
550
-
};
517
+
518
+
gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
519
+
gic_resched_int_base = gic_call_int_base - NR_CPUS;
520
+
551
521
fill_ipi_map();
552
522
gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
553
523
if (!gcmp_present) {
···
555
553
printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
556
554
write_c0_status(0x1100dc00);
557
555
printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
558
-
for (i = 0; i < ARRAY_SIZE(ipiirq); i++) {
559
-
setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, &irq_resched);
560
-
setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].call, &irq_call);
561
-
562
-
set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, handle_percpu_irq);
563
-
set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].call, handle_percpu_irq);
556
+
for (i = 0; i < NR_CPUS; i++) {
557
+
setup_irq(MIPS_GIC_IRQ_BASE +
558
+
GIC_RESCHED_INT(i), &irq_resched);
559
+
setup_irq(MIPS_GIC_IRQ_BASE +
560
+
GIC_CALL_INT(i), &irq_call);
561
+
set_irq_handler(MIPS_GIC_IRQ_BASE +
562
+
GIC_RESCHED_INT(i), handle_percpu_irq);
563
+
set_irq_handler(MIPS_GIC_IRQ_BASE +
564
+
GIC_CALL_INT(i), handle_percpu_irq);
564
565
}
565
566
} else {
566
567
/* set up ipi interrupts */
-3
arch/mips/mti-malta/malta-reset.c
-3
arch/mips/mti-malta/malta-reset.c
+5
arch/mips/pci/Makefile
+5
arch/mips/pci/Makefile
···
52
52
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
53
53
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
54
54
obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
55
+
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
56
+
57
+
ifdef CONFIG_PCI_MSI
58
+
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
59
+
endif
+1
-1
arch/mips/pci/fixup-capcella.c
+1
-1
arch/mips/pci/fixup-capcella.c
···
1
1
/*
2
2
* fixup-cappcela.c, The ZAO Networks Capcella specific PCI fixups.
3
3
*
4
-
* Copyright (C) 2002,2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2002,2004 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/pci/fixup-mpc30x.c
+1
-1
arch/mips/pci/fixup-mpc30x.c
···
1
1
/*
2
2
* fixup-mpc30x.c, The Victor MP-C303/304 specific PCI fixups.
3
3
*
4
-
* Copyright (C) 2002,2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2002,2004 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/pci/fixup-tb0219.c
+1
-1
arch/mips/pci/fixup-tb0219.c
···
2
2
* fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups.
3
3
*
4
4
* Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>
5
-
* Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5
+
* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
6
6
*
7
7
* This program is free software; you can redistribute it and/or modify
8
8
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/pci/fixup-tb0226.c
+1
-1
arch/mips/pci/fixup-tb0226.c
···
1
1
/*
2
2
* fixup-tb0226.c, The TANBAC TB0226 specific PCI fixups.
3
3
*
4
-
* Copyright (C) 2002-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/pci/fixup-tb0287.c
+1
-1
arch/mips/pci/fixup-tb0287.c
···
1
1
/*
2
2
* fixup-tb0287.c, The TANBAC TB0287 specific PCI fixups.
3
3
*
4
-
* Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+3
-3
arch/mips/pci/ops-vr41xx.c
+3
-3
arch/mips/pci/ops-vr41xx.c
···
2
2
* ops-vr41xx.c, PCI configuration routines for the PCIU of NEC VR4100 series.
3
3
*
4
4
* Copyright (C) 2001-2003 MontaVista Software Inc.
5
-
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6
-
* Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5
+
* Author: Yoichi Yuasa <source@mvista.com>
6
+
* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
7
7
*
8
8
* This program is free software; you can redistribute it and/or modify
9
9
* it under the terms of the GNU General Public License as published by
···
21
21
*/
22
22
/*
23
23
* Changes:
24
-
* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
24
+
* MontaVista Software Inc. <source@mvista.com>
25
25
* - New creation, NEC VR4122 and VR4131 are supported.
26
26
*/
27
27
#include <linux/pci.h>
+3
-3
arch/mips/pci/pci-vr41xx.c
+3
-3
arch/mips/pci/pci-vr41xx.c
···
2
2
* pci-vr41xx.c, PCI Control Unit routines for the NEC VR4100 series.
3
3
*
4
4
* Copyright (C) 2001-2003 MontaVista Software Inc.
5
-
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6
-
* Copyright (C) 2004-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5
+
* Author: Yoichi Yuasa <source@mvista.com>
6
+
* Copyright (C) 2004-2008 Yoichi Yuasa <yuasa@linux-mips.org>
7
7
* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8
8
*
9
9
* This program is free software; you can redistribute it and/or modify
···
22
22
*/
23
23
/*
24
24
* Changes:
25
-
* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
25
+
* MontaVista Software Inc. <source@mvista.com>
26
26
* - New creation, NEC VR4122 and VR4131 are supported.
27
27
*/
28
28
#include <linux/init.h>
+2
-2
arch/mips/pci/pci-vr41xx.h
+2
-2
arch/mips/pci/pci-vr41xx.h
···
2
2
* pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series.
3
3
*
4
4
* Copyright (C) 2002 MontaVista Software Inc.
5
-
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6
-
* Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5
+
* Author: Yoichi Yuasa <source@mvista.com>
6
+
* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
7
7
*
8
8
* This program is free software; you can redistribute it and/or modify
9
9
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/vr41xx/casio-e55/setup.c
+1
-1
arch/mips/vr41xx/casio-e55/setup.c
···
1
1
/*
2
2
* setup.c, Setup for the CASIO CASSIOPEIA E-11/15/55/65.
3
3
*
4
-
* Copyright (C) 2002-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2002-2006 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+4
-4
arch/mips/vr41xx/common/bcu.c
+4
-4
arch/mips/vr41xx/common/bcu.c
···
2
2
* bcu.c, Bus Control Unit routines for the NEC VR4100 series.
3
3
*
4
4
* Copyright (C) 2002 MontaVista Software Inc.
5
-
* Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com>
6
-
* Copyright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5
+
* Author: Yoichi Yuasa <source@mvista.com>
6
+
* Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@linux-mips.org>
7
7
*
8
8
* This program is free software; you can redistribute it and/or modify
9
9
* it under the terms of the GNU General Public License as published by
···
21
21
*/
22
22
/*
23
23
* Changes:
24
-
* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
24
+
* MontaVista Software Inc. <source@mvista.com>
25
25
* - New creation, NEC VR4122 and VR4131 are supported.
26
26
* - Added support for NEC VR4111 and VR4121.
27
27
*
28
-
* Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
28
+
* Yoichi Yuasa <yuasa@linux-mips.org>
29
29
* - Added support for NEC VR4133.
30
30
*/
31
31
#include <linux/kernel.h>
+4
-4
arch/mips/vr41xx/common/cmu.c
+4
-4
arch/mips/vr41xx/common/cmu.c
···
2
2
* cmu.c, Clock Mask Unit routines for the NEC VR4100 series.
3
3
*
4
4
* Copyright (C) 2001-2002 MontaVista Software Inc.
5
-
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6
-
* Copuright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5
+
* Author: Yoichi Yuasa <source@mvista.com>
6
+
* Copuright (C) 2003-2005 Yoichi Yuasa <yuasa@linux-mips.org>
7
7
*
8
8
* This program is free software; you can redistribute it and/or modify
9
9
* it under the terms of the GNU General Public License as published by
···
21
21
*/
22
22
/*
23
23
* Changes:
24
-
* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
24
+
* MontaVista Software Inc. <source@mvista.com>
25
25
* - New creation, NEC VR4122 and VR4131 are supported.
26
26
* - Added support for NEC VR4111 and VR4121.
27
27
*
28
-
* Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
28
+
* Yoichi Yuasa <yuasa@linux-mips.org>
29
29
* - Added support for NEC VR4133.
30
30
*/
31
31
#include <linux/init.h>
+1
-1
arch/mips/vr41xx/common/giu.c
+1
-1
arch/mips/vr41xx/common/giu.c
···
1
1
/*
2
2
* NEC VR4100 series GIU platform device.
3
3
*
4
-
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+4
-4
arch/mips/vr41xx/common/icu.c
+4
-4
arch/mips/vr41xx/common/icu.c
···
2
2
* icu.c, Interrupt Control Unit routines for the NEC VR4100 series.
3
3
*
4
4
* Copyright (C) 2001-2002 MontaVista Software Inc.
5
-
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6
-
* Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5
+
* Author: Yoichi Yuasa <source@mvista.com>
6
+
* Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
7
7
*
8
8
* This program is free software; you can redistribute it and/or modify
9
9
* it under the terms of the GNU General Public License as published by
···
21
21
*/
22
22
/*
23
23
* Changes:
24
-
* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
24
+
* MontaVista Software Inc. <source@mvista.com>
25
25
* - New creation, NEC VR4122 and VR4131 are supported.
26
26
* - Added support for NEC VR4111 and VR4121.
27
27
*
28
-
* Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
28
+
* Yoichi Yuasa <yuasa@linux-mips.org>
29
29
* - Coped with INTASSIGN of NEC VR4133.
30
30
*/
31
31
#include <linux/errno.h>
+1
-1
arch/mips/vr41xx/common/init.c
+1
-1
arch/mips/vr41xx/common/init.c
···
1
1
/*
2
2
* init.c, Common initialization routines for NEC VR4100 series.
3
3
*
4
-
* Copyright (C) 2003-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/vr41xx/common/irq.c
+1
-1
arch/mips/vr41xx/common/irq.c
···
1
1
/*
2
2
* Interrupt handing routines for NEC VR4100 series.
3
3
*
4
-
* Copyright (C) 2005-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2005-2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/vr41xx/common/pmu.c
+1
-1
arch/mips/vr41xx/common/pmu.c
···
1
1
/*
2
2
* pmu.c, Power Management Unit routines for NEC VR4100 series.
3
3
*
4
-
* Copyright (C) 2003-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2003-2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/vr41xx/common/rtc.c
+1
-1
arch/mips/vr41xx/common/rtc.c
···
1
1
/*
2
2
* NEC VR4100 series RTC platform device.
3
3
*
4
-
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/vr41xx/common/siu.c
+1
-1
arch/mips/vr41xx/common/siu.c
···
1
1
/*
2
2
* NEC VR4100 series SIU platform device.
3
3
*
4
-
* Copyright (C) 2007-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007-2008 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/vr41xx/common/type.c
+1
-1
arch/mips/vr41xx/common/type.c
···
1
1
/*
2
2
* type.c, System type for NEC VR4100 series.
3
3
*
4
-
* Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+1
-1
arch/mips/vr41xx/ibm-workpad/setup.c
+1
-1
arch/mips/vr41xx/ibm-workpad/setup.c
···
1
1
/*
2
2
* setup.c, Setup for the IBM WorkPad z50.
3
3
*
4
-
* Copyright (C) 2002-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2002-2006 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
-4
drivers/char/Kconfig
-4
drivers/char/Kconfig
···
1029
1029
1030
1030
If compiled as a module, it will be called cs5535_gpio.
1031
1031
1032
-
config GPIO_VR41XX
1033
-
tristate "NEC VR4100 series General-purpose I/O Unit support"
1034
-
depends on CPU_VR41XX
1035
-
1036
1032
config RAW_DRIVER
1037
1033
tristate "RAW driver (/dev/raw/rawN)"
1038
1034
depends on BLOCK
-1
drivers/char/Makefile
-1
drivers/char/Makefile
+2
-2
drivers/char/tb0219.c
+2
-2
drivers/char/tb0219.c
···
1
1
/*
2
2
* Driver for TANBAC TB0219 base board.
3
3
*
4
-
* Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
···
28
28
#include <asm/vr41xx/giu.h>
29
29
#include <asm/vr41xx/tb0219.h>
30
30
31
-
MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
31
+
MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
32
32
MODULE_DESCRIPTION("TANBAC TB0219 base board driver");
33
33
MODULE_LICENSE("GPL");
34
34
-680
drivers/char/vr41xx_giu.c
-680
drivers/char/vr41xx_giu.c
···
1
-
/*
2
-
* Driver for NEC VR4100 series General-purpose I/O Unit.
3
-
*
4
-
* Copyright (C) 2002 MontaVista Software Inc.
5
-
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6
-
* Copyright (C) 2003-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
7
-
*
8
-
* This program is free software; you can redistribute it and/or modify
9
-
* it under the terms of the GNU General Public License as published by
10
-
* the Free Software Foundation; either version 2 of the License, or
11
-
* (at your option) any later version.
12
-
*
13
-
* This program is distributed in the hope that it will be useful,
14
-
* but WITHOUT ANY WARRANTY; without even the implied warranty of
15
-
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16
-
* GNU General Public License for more details.
17
-
*
18
-
* You should have received a copy of the GNU General Public License
19
-
* along with this program; if not, write to the Free Software
20
-
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21
-
*/
22
-
#include <linux/errno.h>
23
-
#include <linux/fs.h>
24
-
#include <linux/init.h>
25
-
#include <linux/interrupt.h>
26
-
#include <linux/irq.h>
27
-
#include <linux/kernel.h>
28
-
#include <linux/module.h>
29
-
#include <linux/platform_device.h>
30
-
#include <linux/smp_lock.h>
31
-
#include <linux/spinlock.h>
32
-
#include <linux/types.h>
33
-
34
-
#include <asm/io.h>
35
-
#include <asm/vr41xx/giu.h>
36
-
#include <asm/vr41xx/irq.h>
37
-
#include <asm/vr41xx/vr41xx.h>
38
-
39
-
MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
40
-
MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
41
-
MODULE_LICENSE("GPL");
42
-
43
-
static int major; /* default is dynamic major device number */
44
-
module_param(major, int, 0);
45
-
MODULE_PARM_DESC(major, "Major device number");
46
-
47
-
#define GIUIOSELL 0x00
48
-
#define GIUIOSELH 0x02
49
-
#define GIUPIODL 0x04
50
-
#define GIUPIODH 0x06
51
-
#define GIUINTSTATL 0x08
52
-
#define GIUINTSTATH 0x0a
53
-
#define GIUINTENL 0x0c
54
-
#define GIUINTENH 0x0e
55
-
#define GIUINTTYPL 0x10
56
-
#define GIUINTTYPH 0x12
57
-
#define GIUINTALSELL 0x14
58
-
#define GIUINTALSELH 0x16
59
-
#define GIUINTHTSELL 0x18
60
-
#define GIUINTHTSELH 0x1a
61
-
#define GIUPODATL 0x1c
62
-
#define GIUPODATEN 0x1c
63
-
#define GIUPODATH 0x1e
64
-
#define PIOEN0 0x0100
65
-
#define PIOEN1 0x0200
66
-
#define GIUPODAT 0x1e
67
-
#define GIUFEDGEINHL 0x20
68
-
#define GIUFEDGEINHH 0x22
69
-
#define GIUREDGEINHL 0x24
70
-
#define GIUREDGEINHH 0x26
71
-
72
-
#define GIUUSEUPDN 0x1e0
73
-
#define GIUTERMUPDN 0x1e2
74
-
75
-
#define GPIO_HAS_PULLUPDOWN_IO 0x0001
76
-
#define GPIO_HAS_OUTPUT_ENABLE 0x0002
77
-
#define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
78
-
79
-
static spinlock_t giu_lock;
80
-
static unsigned long giu_flags;
81
-
static unsigned int giu_nr_pins;
82
-
83
-
static void __iomem *giu_base;
84
-
85
-
#define giu_read(offset) readw(giu_base + (offset))
86
-
#define giu_write(offset, value) writew((value), giu_base + (offset))
87
-
88
-
#define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
89
-
#define GIUINT_HIGH_OFFSET 16
90
-
#define GIUINT_HIGH_MAX 32
91
-
92
-
static inline uint16_t giu_set(uint16_t offset, uint16_t set)
93
-
{
94
-
uint16_t data;
95
-
96
-
data = giu_read(offset);
97
-
data |= set;
98
-
giu_write(offset, data);
99
-
100
-
return data;
101
-
}
102
-
103
-
static inline uint16_t giu_clear(uint16_t offset, uint16_t clear)
104
-
{
105
-
uint16_t data;
106
-
107
-
data = giu_read(offset);
108
-
data &= ~clear;
109
-
giu_write(offset, data);
110
-
111
-
return data;
112
-
}
113
-
114
-
static void ack_giuint_low(unsigned int irq)
115
-
{
116
-
giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(irq));
117
-
}
118
-
119
-
static void mask_giuint_low(unsigned int irq)
120
-
{
121
-
giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
122
-
}
123
-
124
-
static void mask_ack_giuint_low(unsigned int irq)
125
-
{
126
-
unsigned int pin;
127
-
128
-
pin = GPIO_PIN_OF_IRQ(irq);
129
-
giu_clear(GIUINTENL, 1 << pin);
130
-
giu_write(GIUINTSTATL, 1 << pin);
131
-
}
132
-
133
-
static void unmask_giuint_low(unsigned int irq)
134
-
{
135
-
giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
136
-
}
137
-
138
-
static struct irq_chip giuint_low_irq_chip = {
139
-
.name = "GIUINTL",
140
-
.ack = ack_giuint_low,
141
-
.mask = mask_giuint_low,
142
-
.mask_ack = mask_ack_giuint_low,
143
-
.unmask = unmask_giuint_low,
144
-
};
145
-
146
-
static void ack_giuint_high(unsigned int irq)
147
-
{
148
-
giu_write(GIUINTSTATH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
149
-
}
150
-
151
-
static void mask_giuint_high(unsigned int irq)
152
-
{
153
-
giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
154
-
}
155
-
156
-
static void mask_ack_giuint_high(unsigned int irq)
157
-
{
158
-
unsigned int pin;
159
-
160
-
pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET;
161
-
giu_clear(GIUINTENH, 1 << pin);
162
-
giu_write(GIUINTSTATH, 1 << pin);
163
-
}
164
-
165
-
static void unmask_giuint_high(unsigned int irq)
166
-
{
167
-
giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
168
-
}
169
-
170
-
static struct irq_chip giuint_high_irq_chip = {
171
-
.name = "GIUINTH",
172
-
.ack = ack_giuint_high,
173
-
.mask = mask_giuint_high,
174
-
.mask_ack = mask_ack_giuint_high,
175
-
.unmask = unmask_giuint_high,
176
-
};
177
-
178
-
static int giu_get_irq(unsigned int irq)
179
-
{
180
-
uint16_t pendl, pendh, maskl, maskh;
181
-
int i;
182
-
183
-
pendl = giu_read(GIUINTSTATL);
184
-
pendh = giu_read(GIUINTSTATH);
185
-
maskl = giu_read(GIUINTENL);
186
-
maskh = giu_read(GIUINTENH);
187
-
188
-
maskl &= pendl;
189
-
maskh &= pendh;
190
-
191
-
if (maskl) {
192
-
for (i = 0; i < 16; i++) {
193
-
if (maskl & (1 << i))
194
-
return GIU_IRQ(i);
195
-
}
196
-
} else if (maskh) {
197
-
for (i = 0; i < 16; i++) {
198
-
if (maskh & (1 << i))
199
-
return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
200
-
}
201
-
}
202
-
203
-
printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
204
-
maskl, pendl, maskh, pendh);
205
-
206
-
atomic_inc(&irq_err_count);
207
-
208
-
return -EINVAL;
209
-
}
210
-
211
-
void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal)
212
-
{
213
-
uint16_t mask;
214
-
215
-
if (pin < GIUINT_HIGH_OFFSET) {
216
-
mask = 1 << pin;
217
-
if (trigger != IRQ_TRIGGER_LEVEL) {
218
-
giu_set(GIUINTTYPL, mask);
219
-
if (signal == IRQ_SIGNAL_HOLD)
220
-
giu_set(GIUINTHTSELL, mask);
221
-
else
222
-
giu_clear(GIUINTHTSELL, mask);
223
-
if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
224
-
switch (trigger) {
225
-
case IRQ_TRIGGER_EDGE_FALLING:
226
-
giu_set(GIUFEDGEINHL, mask);
227
-
giu_clear(GIUREDGEINHL, mask);
228
-
break;
229
-
case IRQ_TRIGGER_EDGE_RISING:
230
-
giu_clear(GIUFEDGEINHL, mask);
231
-
giu_set(GIUREDGEINHL, mask);
232
-
break;
233
-
default:
234
-
giu_set(GIUFEDGEINHL, mask);
235
-
giu_set(GIUREDGEINHL, mask);
236
-
break;
237
-
}
238
-
}
239
-
set_irq_chip_and_handler(GIU_IRQ(pin),
240
-
&giuint_low_irq_chip,
241
-
handle_edge_irq);
242
-
} else {
243
-
giu_clear(GIUINTTYPL, mask);
244
-
giu_clear(GIUINTHTSELL, mask);
245
-
set_irq_chip_and_handler(GIU_IRQ(pin),
246
-
&giuint_low_irq_chip,
247
-
handle_level_irq);
248
-
}
249
-
giu_write(GIUINTSTATL, mask);
250
-
} else if (pin < GIUINT_HIGH_MAX) {
251
-
mask = 1 << (pin - GIUINT_HIGH_OFFSET);
252
-
if (trigger != IRQ_TRIGGER_LEVEL) {
253
-
giu_set(GIUINTTYPH, mask);
254
-
if (signal == IRQ_SIGNAL_HOLD)
255
-
giu_set(GIUINTHTSELH, mask);
256
-
else
257
-
giu_clear(GIUINTHTSELH, mask);
258
-
if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
259
-
switch (trigger) {
260
-
case IRQ_TRIGGER_EDGE_FALLING:
261
-
giu_set(GIUFEDGEINHH, mask);
262
-
giu_clear(GIUREDGEINHH, mask);
263
-
break;
264
-
case IRQ_TRIGGER_EDGE_RISING:
265
-
giu_clear(GIUFEDGEINHH, mask);
266
-
giu_set(GIUREDGEINHH, mask);
267
-
break;
268
-
default:
269
-
giu_set(GIUFEDGEINHH, mask);
270
-
giu_set(GIUREDGEINHH, mask);
271
-
break;
272
-
}
273
-
}
274
-
set_irq_chip_and_handler(GIU_IRQ(pin),
275
-
&giuint_high_irq_chip,
276
-
handle_edge_irq);
277
-
} else {
278
-
giu_clear(GIUINTTYPH, mask);
279
-
giu_clear(GIUINTHTSELH, mask);
280
-
set_irq_chip_and_handler(GIU_IRQ(pin),
281
-
&giuint_high_irq_chip,
282
-
handle_level_irq);
283
-
}
284
-
giu_write(GIUINTSTATH, mask);
285
-
}
286
-
}
287
-
EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
288
-
289
-
void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
290
-
{
291
-
uint16_t mask;
292
-
293
-
if (pin < GIUINT_HIGH_OFFSET) {
294
-
mask = 1 << pin;
295
-
if (level == IRQ_LEVEL_HIGH)
296
-
giu_set(GIUINTALSELL, mask);
297
-
else
298
-
giu_clear(GIUINTALSELL, mask);
299
-
giu_write(GIUINTSTATL, mask);
300
-
} else if (pin < GIUINT_HIGH_MAX) {
301
-
mask = 1 << (pin - GIUINT_HIGH_OFFSET);
302
-
if (level == IRQ_LEVEL_HIGH)
303
-
giu_set(GIUINTALSELH, mask);
304
-
else
305
-
giu_clear(GIUINTALSELH, mask);
306
-
giu_write(GIUINTSTATH, mask);
307
-
}
308
-
}
309
-
EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
310
-
311
-
gpio_data_t vr41xx_gpio_get_pin(unsigned int pin)
312
-
{
313
-
uint16_t reg, mask;
314
-
315
-
if (pin >= giu_nr_pins)
316
-
return GPIO_DATA_INVAL;
317
-
318
-
if (pin < 16) {
319
-
reg = giu_read(GIUPIODL);
320
-
mask = (uint16_t)1 << pin;
321
-
} else if (pin < 32) {
322
-
reg = giu_read(GIUPIODH);
323
-
mask = (uint16_t)1 << (pin - 16);
324
-
} else if (pin < 48) {
325
-
reg = giu_read(GIUPODATL);
326
-
mask = (uint16_t)1 << (pin - 32);
327
-
} else {
328
-
reg = giu_read(GIUPODATH);
329
-
mask = (uint16_t)1 << (pin - 48);
330
-
}
331
-
332
-
if (reg & mask)
333
-
return GPIO_DATA_HIGH;
334
-
335
-
return GPIO_DATA_LOW;
336
-
}
337
-
EXPORT_SYMBOL_GPL(vr41xx_gpio_get_pin);
338
-
339
-
int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data)
340
-
{
341
-
uint16_t offset, mask, reg;
342
-
unsigned long flags;
343
-
344
-
if (pin >= giu_nr_pins)
345
-
return -EINVAL;
346
-
347
-
if (pin < 16) {
348
-
offset = GIUPIODL;
349
-
mask = (uint16_t)1 << pin;
350
-
} else if (pin < 32) {
351
-
offset = GIUPIODH;
352
-
mask = (uint16_t)1 << (pin - 16);
353
-
} else if (pin < 48) {
354
-
offset = GIUPODATL;
355
-
mask = (uint16_t)1 << (pin - 32);
356
-
} else {
357
-
offset = GIUPODATH;
358
-
mask = (uint16_t)1 << (pin - 48);
359
-
}
360
-
361
-
spin_lock_irqsave(&giu_lock, flags);
362
-
363
-
reg = giu_read(offset);
364
-
if (data == GPIO_DATA_HIGH)
365
-
reg |= mask;
366
-
else
367
-
reg &= ~mask;
368
-
giu_write(offset, reg);
369
-
370
-
spin_unlock_irqrestore(&giu_lock, flags);
371
-
372
-
return 0;
373
-
}
374
-
EXPORT_SYMBOL_GPL(vr41xx_gpio_set_pin);
375
-
376
-
int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir)
377
-
{
378
-
uint16_t offset, mask, reg;
379
-
unsigned long flags;
380
-
381
-
if (pin >= giu_nr_pins)
382
-
return -EINVAL;
383
-
384
-
if (pin < 16) {
385
-
offset = GIUIOSELL;
386
-
mask = (uint16_t)1 << pin;
387
-
} else if (pin < 32) {
388
-
offset = GIUIOSELH;
389
-
mask = (uint16_t)1 << (pin - 16);
390
-
} else {
391
-
if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
392
-
offset = GIUPODATEN;
393
-
mask = (uint16_t)1 << (pin - 32);
394
-
} else {
395
-
switch (pin) {
396
-
case 48:
397
-
offset = GIUPODATH;
398
-
mask = PIOEN0;
399
-
break;
400
-
case 49:
401
-
offset = GIUPODATH;
402
-
mask = PIOEN1;
403
-
break;
404
-
default:
405
-
return -EINVAL;
406
-
}
407
-
}
408
-
}
409
-
410
-
spin_lock_irqsave(&giu_lock, flags);
411
-
412
-
reg = giu_read(offset);
413
-
if (dir == GPIO_OUTPUT)
414
-
reg |= mask;
415
-
else
416
-
reg &= ~mask;
417
-
giu_write(offset, reg);
418
-
419
-
spin_unlock_irqrestore(&giu_lock, flags);
420
-
421
-
return 0;
422
-
}
423
-
EXPORT_SYMBOL_GPL(vr41xx_gpio_set_direction);
424
-
425
-
int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
426
-
{
427
-
uint16_t reg, mask;
428
-
unsigned long flags;
429
-
430
-
if ((giu_flags & GPIO_HAS_PULLUPDOWN_IO) != GPIO_HAS_PULLUPDOWN_IO)
431
-
return -EPERM;
432
-
433
-
if (pin >= 15)
434
-
return -EINVAL;
435
-
436
-
mask = (uint16_t)1 << pin;
437
-
438
-
spin_lock_irqsave(&giu_lock, flags);
439
-
440
-
if (pull == GPIO_PULL_UP || pull == GPIO_PULL_DOWN) {
441
-
reg = giu_read(GIUTERMUPDN);
442
-
if (pull == GPIO_PULL_UP)
443
-
reg |= mask;
444
-
else
445
-
reg &= ~mask;
446
-
giu_write(GIUTERMUPDN, reg);
447
-
448
-
reg = giu_read(GIUUSEUPDN);
449
-
reg |= mask;
450
-
giu_write(GIUUSEUPDN, reg);
451
-
} else {
452
-
reg = giu_read(GIUUSEUPDN);
453
-
reg &= ~mask;
454
-
giu_write(GIUUSEUPDN, reg);
455
-
}
456
-
457
-
spin_unlock_irqrestore(&giu_lock, flags);
458
-
459
-
return 0;
460
-
}
461
-
EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown);
462
-
463
-
static ssize_t gpio_read(struct file *file, char __user *buf, size_t len,
464
-
loff_t *ppos)
465
-
{
466
-
unsigned int pin;
467
-
char value = '0';
468
-
469
-
pin = iminor(file->f_path.dentry->d_inode);
470
-
if (pin >= giu_nr_pins)
471
-
return -EBADF;
472
-
473
-
if (vr41xx_gpio_get_pin(pin) == GPIO_DATA_HIGH)
474
-
value = '1';
475
-
476
-
if (len <= 0)
477
-
return -EFAULT;
478
-
479
-
if (put_user(value, buf))
480
-
return -EFAULT;
481
-
482
-
return 1;
483
-
}
484
-
485
-
static ssize_t gpio_write(struct file *file, const char __user *data,
486
-
size_t len, loff_t *ppos)
487
-
{
488
-
unsigned int pin;
489
-
size_t i;
490
-
char c;
491
-
int retval = 0;
492
-
493
-
pin = iminor(file->f_path.dentry->d_inode);
494
-
if (pin >= giu_nr_pins)
495
-
return -EBADF;
496
-
497
-
for (i = 0; i < len; i++) {
498
-
if (get_user(c, data + i))
499
-
return -EFAULT;
500
-
501
-
switch (c) {
502
-
case '0':
503
-
retval = vr41xx_gpio_set_pin(pin, GPIO_DATA_LOW);
504
-
break;
505
-
case '1':
506
-
retval = vr41xx_gpio_set_pin(pin, GPIO_DATA_HIGH);
507
-
break;
508
-
case 'D':
509
-
printk(KERN_INFO "GPIO%d: pull down\n", pin);
510
-
retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DOWN);
511
-
break;
512
-
case 'd':
513
-
printk(KERN_INFO "GPIO%d: pull up/down disable\n", pin);
514
-
retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DISABLE);
515
-
break;
516
-
case 'I':
517
-
printk(KERN_INFO "GPIO%d: input\n", pin);
518
-
retval = vr41xx_gpio_set_direction(pin, GPIO_INPUT);
519
-
break;
520
-
case 'O':
521
-
printk(KERN_INFO "GPIO%d: output\n", pin);
522
-
retval = vr41xx_gpio_set_direction(pin, GPIO_OUTPUT);
523
-
break;
524
-
case 'o':
525
-
printk(KERN_INFO "GPIO%d: output disable\n", pin);
526
-
retval = vr41xx_gpio_set_direction(pin, GPIO_OUTPUT_DISABLE);
527
-
break;
528
-
case 'P':
529
-
printk(KERN_INFO "GPIO%d: pull up\n", pin);
530
-
retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_UP);
531
-
break;
532
-
case 'p':
533
-
printk(KERN_INFO "GPIO%d: pull up/down disable\n", pin);
534
-
retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DISABLE);
535
-
break;
536
-
default:
537
-
break;
538
-
}
539
-
540
-
if (retval < 0)
541
-
break;
542
-
}
543
-
544
-
return i;
545
-
}
546
-
547
-
static int gpio_open(struct inode *inode, struct file *file)
548
-
{
549
-
unsigned int pin;
550
-
551
-
cycle_kernel_lock();
552
-
pin = iminor(inode);
553
-
if (pin >= giu_nr_pins)
554
-
return -EBADF;
555
-
556
-
return nonseekable_open(inode, file);
557
-
}
558
-
559
-
static int gpio_release(struct inode *inode, struct file *file)
560
-
{
561
-
unsigned int pin;
562
-
563
-
pin = iminor(inode);
564
-
if (pin >= giu_nr_pins)
565
-
return -EBADF;
566
-
567
-
return 0;
568
-
}
569
-
570
-
static const struct file_operations gpio_fops = {
571
-
.owner = THIS_MODULE,
572
-
.read = gpio_read,
573
-
.write = gpio_write,
574
-
.open = gpio_open,
575
-
.release = gpio_release,
576
-
};
577
-
578
-
static int __devinit giu_probe(struct platform_device *dev)
579
-
{
580
-
struct resource *res;
581
-
unsigned int trigger, i, pin;
582
-
struct irq_chip *chip;
583
-
int irq, retval;
584
-
585
-
switch (dev->id) {
586
-
case GPIO_50PINS_PULLUPDOWN:
587
-
giu_flags = GPIO_HAS_PULLUPDOWN_IO;
588
-
giu_nr_pins = 50;
589
-
break;
590
-
case GPIO_36PINS:
591
-
giu_nr_pins = 36;
592
-
break;
593
-
case GPIO_48PINS_EDGE_SELECT:
594
-
giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
595
-
giu_nr_pins = 48;
596
-
break;
597
-
default:
598
-
printk(KERN_ERR "GIU: unknown ID %d\n", dev->id);
599
-
return -ENODEV;
600
-
}
601
-
602
-
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
603
-
if (!res)
604
-
return -EBUSY;
605
-
606
-
giu_base = ioremap(res->start, res->end - res->start + 1);
607
-
if (!giu_base)
608
-
return -ENOMEM;
609
-
610
-
retval = register_chrdev(major, "GIU", &gpio_fops);
611
-
if (retval < 0) {
612
-
iounmap(giu_base);
613
-
giu_base = NULL;
614
-
return retval;
615
-
}
616
-
617
-
if (major == 0) {
618
-
major = retval;
619
-
printk(KERN_INFO "GIU: major number %d\n", major);
620
-
}
621
-
622
-
spin_lock_init(&giu_lock);
623
-
624
-
giu_write(GIUINTENL, 0);
625
-
giu_write(GIUINTENH, 0);
626
-
627
-
trigger = giu_read(GIUINTTYPH) << 16;
628
-
trigger |= giu_read(GIUINTTYPL);
629
-
for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
630
-
pin = GPIO_PIN_OF_IRQ(i);
631
-
if (pin < GIUINT_HIGH_OFFSET)
632
-
chip = &giuint_low_irq_chip;
633
-
else
634
-
chip = &giuint_high_irq_chip;
635
-
636
-
if (trigger & (1 << pin))
637
-
set_irq_chip_and_handler(i, chip, handle_edge_irq);
638
-
else
639
-
set_irq_chip_and_handler(i, chip, handle_level_irq);
640
-
641
-
}
642
-
643
-
irq = platform_get_irq(dev, 0);
644
-
if (irq < 0 || irq >= nr_irqs)
645
-
return -EBUSY;
646
-
647
-
return cascade_irq(irq, giu_get_irq);
648
-
}
649
-
650
-
static int __devexit giu_remove(struct platform_device *dev)
651
-
{
652
-
if (giu_base) {
653
-
iounmap(giu_base);
654
-
giu_base = NULL;
655
-
}
656
-
657
-
return 0;
658
-
}
659
-
660
-
static struct platform_driver giu_device_driver = {
661
-
.probe = giu_probe,
662
-
.remove = __devexit_p(giu_remove),
663
-
.driver = {
664
-
.name = "GIU",
665
-
.owner = THIS_MODULE,
666
-
},
667
-
};
668
-
669
-
static int __init vr41xx_giu_init(void)
670
-
{
671
-
return platform_driver_register(&giu_device_driver);
672
-
}
673
-
674
-
static void __exit vr41xx_giu_exit(void)
675
-
{
676
-
platform_driver_unregister(&giu_device_driver);
677
-
}
678
-
679
-
module_init(vr41xx_giu_init);
680
-
module_exit(vr41xx_giu_exit);
+6
drivers/gpio/Kconfig
+6
drivers/gpio/Kconfig
···
79
79
help
80
80
Say yes here to support the Xilinx FPGA GPIO device
81
81
82
+
config GPIO_VR41XX
83
+
tristate "NEC VR4100 series General-purpose I/O Uint support"
84
+
depends on CPU_VR41XX
85
+
help
86
+
Say yes here to support the NEC VR4100 series General-purpose I/O Uint
87
+
82
88
comment "I2C GPIO expanders:"
83
89
84
90
config GPIO_MAX732X
+1
drivers/gpio/Makefile
+1
drivers/gpio/Makefile
+586
drivers/gpio/vr41xx_giu.c
+586
drivers/gpio/vr41xx_giu.c
···
1
+
/*
2
+
* Driver for NEC VR4100 series General-purpose I/O Unit.
3
+
*
4
+
* Copyright (C) 2002 MontaVista Software Inc.
5
+
* Author: Yoichi Yuasa <source@mvista.com>
6
+
* Copyright (C) 2003-2009 Yoichi Yuasa <yuasa@linux-mips.org>
7
+
*
8
+
* This program is free software; you can redistribute it and/or modify
9
+
* it under the terms of the GNU General Public License as published by
10
+
* the Free Software Foundation; either version 2 of the License, or
11
+
* (at your option) any later version.
12
+
*
13
+
* This program is distributed in the hope that it will be useful,
14
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
15
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16
+
* GNU General Public License for more details.
17
+
*
18
+
* You should have received a copy of the GNU General Public License
19
+
* along with this program; if not, write to the Free Software
20
+
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21
+
*/
22
+
#include <linux/errno.h>
23
+
#include <linux/fs.h>
24
+
#include <linux/gpio.h>
25
+
#include <linux/init.h>
26
+
#include <linux/interrupt.h>
27
+
#include <linux/io.h>
28
+
#include <linux/irq.h>
29
+
#include <linux/kernel.h>
30
+
#include <linux/module.h>
31
+
#include <linux/platform_device.h>
32
+
#include <linux/smp_lock.h>
33
+
#include <linux/spinlock.h>
34
+
#include <linux/types.h>
35
+
36
+
#include <asm/vr41xx/giu.h>
37
+
#include <asm/vr41xx/irq.h>
38
+
#include <asm/vr41xx/vr41xx.h>
39
+
40
+
MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
41
+
MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
42
+
MODULE_LICENSE("GPL");
43
+
44
+
#define GIUIOSELL 0x00
45
+
#define GIUIOSELH 0x02
46
+
#define GIUPIODL 0x04
47
+
#define GIUPIODH 0x06
48
+
#define GIUINTSTATL 0x08
49
+
#define GIUINTSTATH 0x0a
50
+
#define GIUINTENL 0x0c
51
+
#define GIUINTENH 0x0e
52
+
#define GIUINTTYPL 0x10
53
+
#define GIUINTTYPH 0x12
54
+
#define GIUINTALSELL 0x14
55
+
#define GIUINTALSELH 0x16
56
+
#define GIUINTHTSELL 0x18
57
+
#define GIUINTHTSELH 0x1a
58
+
#define GIUPODATL 0x1c
59
+
#define GIUPODATEN 0x1c
60
+
#define GIUPODATH 0x1e
61
+
#define PIOEN0 0x0100
62
+
#define PIOEN1 0x0200
63
+
#define GIUPODAT 0x1e
64
+
#define GIUFEDGEINHL 0x20
65
+
#define GIUFEDGEINHH 0x22
66
+
#define GIUREDGEINHL 0x24
67
+
#define GIUREDGEINHH 0x26
68
+
69
+
#define GIUUSEUPDN 0x1e0
70
+
#define GIUTERMUPDN 0x1e2
71
+
72
+
#define GPIO_HAS_PULLUPDOWN_IO 0x0001
73
+
#define GPIO_HAS_OUTPUT_ENABLE 0x0002
74
+
#define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
75
+
76
+
enum {
77
+
GPIO_INPUT,
78
+
GPIO_OUTPUT,
79
+
};
80
+
81
+
static DEFINE_SPINLOCK(giu_lock);
82
+
static unsigned long giu_flags;
83
+
84
+
static void __iomem *giu_base;
85
+
86
+
#define giu_read(offset) readw(giu_base + (offset))
87
+
#define giu_write(offset, value) writew((value), giu_base + (offset))
88
+
89
+
#define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
90
+
#define GIUINT_HIGH_OFFSET 16
91
+
#define GIUINT_HIGH_MAX 32
92
+
93
+
static inline u16 giu_set(u16 offset, u16 set)
94
+
{
95
+
u16 data;
96
+
97
+
data = giu_read(offset);
98
+
data |= set;
99
+
giu_write(offset, data);
100
+
101
+
return data;
102
+
}
103
+
104
+
static inline u16 giu_clear(u16 offset, u16 clear)
105
+
{
106
+
u16 data;
107
+
108
+
data = giu_read(offset);
109
+
data &= ~clear;
110
+
giu_write(offset, data);
111
+
112
+
return data;
113
+
}
114
+
115
+
static void ack_giuint_low(unsigned int irq)
116
+
{
117
+
giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(irq));
118
+
}
119
+
120
+
static void mask_giuint_low(unsigned int irq)
121
+
{
122
+
giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
123
+
}
124
+
125
+
static void mask_ack_giuint_low(unsigned int irq)
126
+
{
127
+
unsigned int pin;
128
+
129
+
pin = GPIO_PIN_OF_IRQ(irq);
130
+
giu_clear(GIUINTENL, 1 << pin);
131
+
giu_write(GIUINTSTATL, 1 << pin);
132
+
}
133
+
134
+
static void unmask_giuint_low(unsigned int irq)
135
+
{
136
+
giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
137
+
}
138
+
139
+
static struct irq_chip giuint_low_irq_chip = {
140
+
.name = "GIUINTL",
141
+
.ack = ack_giuint_low,
142
+
.mask = mask_giuint_low,
143
+
.mask_ack = mask_ack_giuint_low,
144
+
.unmask = unmask_giuint_low,
145
+
};
146
+
147
+
static void ack_giuint_high(unsigned int irq)
148
+
{
149
+
giu_write(GIUINTSTATH,
150
+
1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
151
+
}
152
+
153
+
static void mask_giuint_high(unsigned int irq)
154
+
{
155
+
giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
156
+
}
157
+
158
+
static void mask_ack_giuint_high(unsigned int irq)
159
+
{
160
+
unsigned int pin;
161
+
162
+
pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET;
163
+
giu_clear(GIUINTENH, 1 << pin);
164
+
giu_write(GIUINTSTATH, 1 << pin);
165
+
}
166
+
167
+
static void unmask_giuint_high(unsigned int irq)
168
+
{
169
+
giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
170
+
}
171
+
172
+
static struct irq_chip giuint_high_irq_chip = {
173
+
.name = "GIUINTH",
174
+
.ack = ack_giuint_high,
175
+
.mask = mask_giuint_high,
176
+
.mask_ack = mask_ack_giuint_high,
177
+
.unmask = unmask_giuint_high,
178
+
};
179
+
180
+
static int giu_get_irq(unsigned int irq)
181
+
{
182
+
u16 pendl, pendh, maskl, maskh;
183
+
int i;
184
+
185
+
pendl = giu_read(GIUINTSTATL);
186
+
pendh = giu_read(GIUINTSTATH);
187
+
maskl = giu_read(GIUINTENL);
188
+
maskh = giu_read(GIUINTENH);
189
+
190
+
maskl &= pendl;
191
+
maskh &= pendh;
192
+
193
+
if (maskl) {
194
+
for (i = 0; i < 16; i++) {
195
+
if (maskl & (1 << i))
196
+
return GIU_IRQ(i);
197
+
}
198
+
} else if (maskh) {
199
+
for (i = 0; i < 16; i++) {
200
+
if (maskh & (1 << i))
201
+
return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
202
+
}
203
+
}
204
+
205
+
printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
206
+
maskl, pendl, maskh, pendh);
207
+
208
+
atomic_inc(&irq_err_count);
209
+
210
+
return -EINVAL;
211
+
}
212
+
213
+
void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
214
+
irq_signal_t signal)
215
+
{
216
+
u16 mask;
217
+
218
+
if (pin < GIUINT_HIGH_OFFSET) {
219
+
mask = 1 << pin;
220
+
if (trigger != IRQ_TRIGGER_LEVEL) {
221
+
giu_set(GIUINTTYPL, mask);
222
+
if (signal == IRQ_SIGNAL_HOLD)
223
+
giu_set(GIUINTHTSELL, mask);
224
+
else
225
+
giu_clear(GIUINTHTSELL, mask);
226
+
if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
227
+
switch (trigger) {
228
+
case IRQ_TRIGGER_EDGE_FALLING:
229
+
giu_set(GIUFEDGEINHL, mask);
230
+
giu_clear(GIUREDGEINHL, mask);
231
+
break;
232
+
case IRQ_TRIGGER_EDGE_RISING:
233
+
giu_clear(GIUFEDGEINHL, mask);
234
+
giu_set(GIUREDGEINHL, mask);
235
+
break;
236
+
default:
237
+
giu_set(GIUFEDGEINHL, mask);
238
+
giu_set(GIUREDGEINHL, mask);
239
+
break;
240
+
}
241
+
}
242
+
set_irq_chip_and_handler(GIU_IRQ(pin),
243
+
&giuint_low_irq_chip,
244
+
handle_edge_irq);
245
+
} else {
246
+
giu_clear(GIUINTTYPL, mask);
247
+
giu_clear(GIUINTHTSELL, mask);
248
+
set_irq_chip_and_handler(GIU_IRQ(pin),
249
+
&giuint_low_irq_chip,
250
+
handle_level_irq);
251
+
}
252
+
giu_write(GIUINTSTATL, mask);
253
+
} else if (pin < GIUINT_HIGH_MAX) {
254
+
mask = 1 << (pin - GIUINT_HIGH_OFFSET);
255
+
if (trigger != IRQ_TRIGGER_LEVEL) {
256
+
giu_set(GIUINTTYPH, mask);
257
+
if (signal == IRQ_SIGNAL_HOLD)
258
+
giu_set(GIUINTHTSELH, mask);
259
+
else
260
+
giu_clear(GIUINTHTSELH, mask);
261
+
if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
262
+
switch (trigger) {
263
+
case IRQ_TRIGGER_EDGE_FALLING:
264
+
giu_set(GIUFEDGEINHH, mask);
265
+
giu_clear(GIUREDGEINHH, mask);
266
+
break;
267
+
case IRQ_TRIGGER_EDGE_RISING:
268
+
giu_clear(GIUFEDGEINHH, mask);
269
+
giu_set(GIUREDGEINHH, mask);
270
+
break;
271
+
default:
272
+
giu_set(GIUFEDGEINHH, mask);
273
+
giu_set(GIUREDGEINHH, mask);
274
+
break;
275
+
}
276
+
}
277
+
set_irq_chip_and_handler(GIU_IRQ(pin),
278
+
&giuint_high_irq_chip,
279
+
handle_edge_irq);
280
+
} else {
281
+
giu_clear(GIUINTTYPH, mask);
282
+
giu_clear(GIUINTHTSELH, mask);
283
+
set_irq_chip_and_handler(GIU_IRQ(pin),
284
+
&giuint_high_irq_chip,
285
+
handle_level_irq);
286
+
}
287
+
giu_write(GIUINTSTATH, mask);
288
+
}
289
+
}
290
+
EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
291
+
292
+
void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
293
+
{
294
+
u16 mask;
295
+
296
+
if (pin < GIUINT_HIGH_OFFSET) {
297
+
mask = 1 << pin;
298
+
if (level == IRQ_LEVEL_HIGH)
299
+
giu_set(GIUINTALSELL, mask);
300
+
else
301
+
giu_clear(GIUINTALSELL, mask);
302
+
giu_write(GIUINTSTATL, mask);
303
+
} else if (pin < GIUINT_HIGH_MAX) {
304
+
mask = 1 << (pin - GIUINT_HIGH_OFFSET);
305
+
if (level == IRQ_LEVEL_HIGH)
306
+
giu_set(GIUINTALSELH, mask);
307
+
else
308
+
giu_clear(GIUINTALSELH, mask);
309
+
giu_write(GIUINTSTATH, mask);
310
+
}
311
+
}
312
+
EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
313
+
314
+
static int giu_set_direction(struct gpio_chip *chip, unsigned pin, int dir)
315
+
{
316
+
u16 offset, mask, reg;
317
+
unsigned long flags;
318
+
319
+
if (pin >= chip->ngpio)
320
+
return -EINVAL;
321
+
322
+
if (pin < 16) {
323
+
offset = GIUIOSELL;
324
+
mask = 1 << pin;
325
+
} else if (pin < 32) {
326
+
offset = GIUIOSELH;
327
+
mask = 1 << (pin - 16);
328
+
} else {
329
+
if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
330
+
offset = GIUPODATEN;
331
+
mask = 1 << (pin - 32);
332
+
} else {
333
+
switch (pin) {
334
+
case 48:
335
+
offset = GIUPODATH;
336
+
mask = PIOEN0;
337
+
break;
338
+
case 49:
339
+
offset = GIUPODATH;
340
+
mask = PIOEN1;
341
+
break;
342
+
default:
343
+
return -EINVAL;
344
+
}
345
+
}
346
+
}
347
+
348
+
spin_lock_irqsave(&giu_lock, flags);
349
+
350
+
reg = giu_read(offset);
351
+
if (dir == GPIO_OUTPUT)
352
+
reg |= mask;
353
+
else
354
+
reg &= ~mask;
355
+
giu_write(offset, reg);
356
+
357
+
spin_unlock_irqrestore(&giu_lock, flags);
358
+
359
+
return 0;
360
+
}
361
+
362
+
int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
363
+
{
364
+
u16 reg, mask;
365
+
unsigned long flags;
366
+
367
+
if ((giu_flags & GPIO_HAS_PULLUPDOWN_IO) != GPIO_HAS_PULLUPDOWN_IO)
368
+
return -EPERM;
369
+
370
+
if (pin >= 15)
371
+
return -EINVAL;
372
+
373
+
mask = 1 << pin;
374
+
375
+
spin_lock_irqsave(&giu_lock, flags);
376
+
377
+
if (pull == GPIO_PULL_UP || pull == GPIO_PULL_DOWN) {
378
+
reg = giu_read(GIUTERMUPDN);
379
+
if (pull == GPIO_PULL_UP)
380
+
reg |= mask;
381
+
else
382
+
reg &= ~mask;
383
+
giu_write(GIUTERMUPDN, reg);
384
+
385
+
reg = giu_read(GIUUSEUPDN);
386
+
reg |= mask;
387
+
giu_write(GIUUSEUPDN, reg);
388
+
} else {
389
+
reg = giu_read(GIUUSEUPDN);
390
+
reg &= ~mask;
391
+
giu_write(GIUUSEUPDN, reg);
392
+
}
393
+
394
+
spin_unlock_irqrestore(&giu_lock, flags);
395
+
396
+
return 0;
397
+
}
398
+
EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown);
399
+
400
+
static int vr41xx_gpio_get(struct gpio_chip *chip, unsigned pin)
401
+
{
402
+
u16 reg, mask;
403
+
404
+
if (pin >= chip->ngpio)
405
+
return -EINVAL;
406
+
407
+
if (pin < 16) {
408
+
reg = giu_read(GIUPIODL);
409
+
mask = 1 << pin;
410
+
} else if (pin < 32) {
411
+
reg = giu_read(GIUPIODH);
412
+
mask = 1 << (pin - 16);
413
+
} else if (pin < 48) {
414
+
reg = giu_read(GIUPODATL);
415
+
mask = 1 << (pin - 32);
416
+
} else {
417
+
reg = giu_read(GIUPODATH);
418
+
mask = 1 << (pin - 48);
419
+
}
420
+
421
+
if (reg & mask)
422
+
return 1;
423
+
424
+
return 0;
425
+
}
426
+
427
+
static void vr41xx_gpio_set(struct gpio_chip *chip, unsigned pin,
428
+
int value)
429
+
{
430
+
u16 offset, mask, reg;
431
+
unsigned long flags;
432
+
433
+
if (pin >= chip->ngpio)
434
+
return;
435
+
436
+
if (pin < 16) {
437
+
offset = GIUPIODL;
438
+
mask = 1 << pin;
439
+
} else if (pin < 32) {
440
+
offset = GIUPIODH;
441
+
mask = 1 << (pin - 16);
442
+
} else if (pin < 48) {
443
+
offset = GIUPODATL;
444
+
mask = 1 << (pin - 32);
445
+
} else {
446
+
offset = GIUPODATH;
447
+
mask = 1 << (pin - 48);
448
+
}
449
+
450
+
spin_lock_irqsave(&giu_lock, flags);
451
+
452
+
reg = giu_read(offset);
453
+
if (value)
454
+
reg |= mask;
455
+
else
456
+
reg &= ~mask;
457
+
giu_write(offset, reg);
458
+
459
+
spin_unlock_irqrestore(&giu_lock, flags);
460
+
}
461
+
462
+
463
+
static int vr41xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
464
+
{
465
+
return giu_set_direction(chip, offset, GPIO_INPUT);
466
+
}
467
+
468
+
static int vr41xx_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
469
+
int value)
470
+
{
471
+
vr41xx_gpio_set(chip, offset, value);
472
+
473
+
return giu_set_direction(chip, offset, GPIO_OUTPUT);
474
+
}
475
+
476
+
static int vr41xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
477
+
{
478
+
if (offset >= chip->ngpio)
479
+
return -EINVAL;
480
+
481
+
return GIU_IRQ_BASE + offset;
482
+
}
483
+
484
+
static struct gpio_chip vr41xx_gpio_chip = {
485
+
.label = "vr41xx",
486
+
.owner = THIS_MODULE,
487
+
.direction_input = vr41xx_gpio_direction_input,
488
+
.get = vr41xx_gpio_get,
489
+
.direction_output = vr41xx_gpio_direction_output,
490
+
.set = vr41xx_gpio_set,
491
+
.to_irq = vr41xx_gpio_to_irq,
492
+
};
493
+
494
+
static int __devinit giu_probe(struct platform_device *pdev)
495
+
{
496
+
struct resource *res;
497
+
unsigned int trigger, i, pin;
498
+
struct irq_chip *chip;
499
+
int irq, retval;
500
+
501
+
switch (pdev->id) {
502
+
case GPIO_50PINS_PULLUPDOWN:
503
+
giu_flags = GPIO_HAS_PULLUPDOWN_IO;
504
+
vr41xx_gpio_chip.ngpio = 50;
505
+
break;
506
+
case GPIO_36PINS:
507
+
vr41xx_gpio_chip.ngpio = 36;
508
+
break;
509
+
case GPIO_48PINS_EDGE_SELECT:
510
+
giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
511
+
vr41xx_gpio_chip.ngpio = 48;
512
+
break;
513
+
default:
514
+
dev_err(&pdev->dev, "GIU: unknown ID %d\n", pdev->id);
515
+
return -ENODEV;
516
+
}
517
+
518
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
519
+
if (!res)
520
+
return -EBUSY;
521
+
522
+
giu_base = ioremap(res->start, res->end - res->start + 1);
523
+
if (!giu_base)
524
+
return -ENOMEM;
525
+
526
+
vr41xx_gpio_chip.dev = &pdev->dev;
527
+
528
+
retval = gpiochip_add(&vr41xx_gpio_chip);
529
+
530
+
giu_write(GIUINTENL, 0);
531
+
giu_write(GIUINTENH, 0);
532
+
533
+
trigger = giu_read(GIUINTTYPH) << 16;
534
+
trigger |= giu_read(GIUINTTYPL);
535
+
for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
536
+
pin = GPIO_PIN_OF_IRQ(i);
537
+
if (pin < GIUINT_HIGH_OFFSET)
538
+
chip = &giuint_low_irq_chip;
539
+
else
540
+
chip = &giuint_high_irq_chip;
541
+
542
+
if (trigger & (1 << pin))
543
+
set_irq_chip_and_handler(i, chip, handle_edge_irq);
544
+
else
545
+
set_irq_chip_and_handler(i, chip, handle_level_irq);
546
+
547
+
}
548
+
549
+
irq = platform_get_irq(pdev, 0);
550
+
if (irq < 0 || irq >= nr_irqs)
551
+
return -EBUSY;
552
+
553
+
return cascade_irq(irq, giu_get_irq);
554
+
}
555
+
556
+
static int __devexit giu_remove(struct platform_device *pdev)
557
+
{
558
+
if (giu_base) {
559
+
iounmap(giu_base);
560
+
giu_base = NULL;
561
+
}
562
+
563
+
return 0;
564
+
}
565
+
566
+
static struct platform_driver giu_device_driver = {
567
+
.probe = giu_probe,
568
+
.remove = __devexit_p(giu_remove),
569
+
.driver = {
570
+
.name = "GIU",
571
+
.owner = THIS_MODULE,
572
+
},
573
+
};
574
+
575
+
static int __init vr41xx_giu_init(void)
576
+
{
577
+
return platform_driver_register(&giu_device_driver);
578
+
}
579
+
580
+
static void __exit vr41xx_giu_exit(void)
581
+
{
582
+
platform_driver_unregister(&giu_device_driver);
583
+
}
584
+
585
+
module_init(vr41xx_giu_init);
586
+
module_exit(vr41xx_giu_exit);
+2
-2
drivers/input/misc/cobalt_btns.c
+2
-2
drivers/input/misc/cobalt_btns.c
···
1
1
/*
2
2
* Cobalt button interface driver.
3
3
*
4
-
* Copyright (C) 2007-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007-2008 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
···
148
148
return 0;
149
149
}
150
150
151
-
MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
151
+
MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
152
152
MODULE_DESCRIPTION("Cobalt button interface driver");
153
153
MODULE_LICENSE("GPL");
154
154
/* work with hotplug and coldplug */
+1
-1
drivers/leds/leds-cobalt-raq.c
+1
-1
drivers/leds/leds-cobalt-raq.c
···
1
1
/*
2
2
* LEDs driver for the Cobalt Raq series.
3
3
*
4
-
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
+2
-2
drivers/pcmcia/vrc4171_card.c
+2
-2
drivers/pcmcia/vrc4171_card.c
···
1
1
/*
2
2
* vrc4171_card.c, NEC VRC4171 Card Controller driver for Socket Services.
3
3
*
4
-
* Copyright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
···
32
32
#include "i82365.h"
33
33
34
34
MODULE_DESCRIPTION("NEC VRC4171 Card Controllers driver for Socket Services");
35
-
MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
35
+
MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
36
36
MODULE_LICENSE("GPL");
37
37
38
38
#define CARD_MAX_SLOTS 2
+2
-2
drivers/pcmcia/vrc4173_cardu.c
+2
-2
drivers/pcmcia/vrc4173_cardu.c
···
6
6
* NEC VRC4173 CARDU driver for Socket Services
7
7
* (This device doesn't support CardBus. it is supporting only 16bit PC Card.)
8
8
*
9
-
* Copyright 2002,2003 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
9
+
* Copyright 2002,2003 Yoichi Yuasa <yuasa@linux-mips.org>
10
10
*
11
11
* This program is free software; you can redistribute it and/or modify it
12
12
* under the terms of the GNU General Public License as published by the
···
41
41
#include "vrc4173_cardu.h"
42
42
43
43
MODULE_DESCRIPTION("NEC VRC4173 CARDU driver for Socket Services");
44
-
MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
44
+
MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
45
45
MODULE_LICENSE("GPL");
46
46
47
47
static int vrc4173_cardu_slots;
+1
-1
drivers/pcmcia/vrc4173_cardu.h
+1
-1
drivers/pcmcia/vrc4173_cardu.h
···
5
5
* BRIEF MODULE DESCRIPTION
6
6
* Include file for NEC VRC4173 CARDU.
7
7
*
8
-
* Copyright 2002 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
8
+
* Copyright 2002 Yoichi Yuasa <yuasa@linux-mips.org>
9
9
*
10
10
* This program is free software; you can redistribute it and/or modify it
11
11
* under the terms of the GNU General Public License as published by the
+2
-2
drivers/rtc/rtc-vr41xx.c
+2
-2
drivers/rtc/rtc-vr41xx.c
···
1
1
/*
2
2
* Driver for NEC VR4100 series Real Time Clock unit.
3
3
*
4
-
* Copyright (C) 2003-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by
···
33
33
#include <asm/io.h>
34
34
#include <asm/uaccess.h>
35
35
36
-
MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
36
+
MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
37
37
MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
38
38
MODULE_LICENSE("GPL v2");
39
39
+1
-1
drivers/serial/vr41xx_siu.c
+1
-1
drivers/serial/vr41xx_siu.c
+75
-10
drivers/ssb/driver_mipscore.c
+75
-10
drivers/ssb/driver_mipscore.c
···
49
49
50
50
static inline u32 ssb_irqflag(struct ssb_device *dev)
51
51
{
52
-
return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
52
+
u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
53
+
if (tpsflag)
54
+
return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
55
+
else
56
+
/* not irq supported */
57
+
return 0x3f;
58
+
}
59
+
60
+
static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
61
+
{
62
+
struct ssb_bus *bus = rdev->bus;
63
+
int i;
64
+
for (i = 0; i < bus->nr_devices; i++) {
65
+
struct ssb_device *dev;
66
+
dev = &(bus->devices[i]);
67
+
if (ssb_irqflag(dev) == irqflag)
68
+
return dev;
69
+
}
70
+
return NULL;
53
71
}
54
72
55
73
/* Get the MIPS IRQ assignment for a specified device.
56
74
* If unassigned, 0 is returned.
75
+
* If disabled, 5 is returned.
76
+
* If not supported, 6 is returned.
57
77
*/
58
78
unsigned int ssb_mips_irq(struct ssb_device *dev)
59
79
{
60
80
struct ssb_bus *bus = dev->bus;
81
+
struct ssb_device *mdev = bus->mipscore.dev;
61
82
u32 irqflag;
62
83
u32 ipsflag;
63
84
u32 tmp;
64
85
unsigned int irq;
65
86
66
87
irqflag = ssb_irqflag(dev);
88
+
if (irqflag == 0x3f)
89
+
return 6;
67
90
ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
68
91
for (irq = 1; irq <= 4; irq++) {
69
92
tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
70
93
if (tmp == irqflag)
71
94
break;
72
95
}
73
-
if (irq == 5)
74
-
irq = 0;
96
+
if (irq == 5) {
97
+
if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
98
+
irq = 0;
99
+
}
75
100
76
101
return irq;
77
102
}
···
122
97
struct ssb_device *mdev = bus->mipscore.dev;
123
98
u32 irqflag = ssb_irqflag(dev);
124
99
100
+
BUG_ON(oldirq == 6);
101
+
125
102
dev->irq = irq + 2;
126
103
127
-
ssb_dprintk(KERN_INFO PFX
128
-
"set_irq: core 0x%04x, irq %d => %d\n",
129
-
dev->id.coreid, oldirq, irq);
130
104
/* clear the old irq */
131
105
if (oldirq == 0)
132
106
ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
133
-
else
107
+
else if (oldirq != 5)
134
108
clear_irq(bus, oldirq);
135
109
136
110
/* assign the new one */
137
111
if (irq == 0) {
138
112
ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
139
113
} else {
114
+
u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
115
+
if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
116
+
u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
117
+
struct ssb_device *olddev = find_device(dev, oldipsflag);
118
+
if (olddev)
119
+
set_irq(olddev, 0);
120
+
}
140
121
irqflag <<= ipsflag_irq_shift[irq];
141
-
irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
122
+
irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
142
123
ssb_write32(mdev, SSB_IPSFLAG, irqflag);
124
+
}
125
+
ssb_dprintk(KERN_INFO PFX
126
+
"set_irq: core 0x%04x, irq %d => %d\n",
127
+
dev->id.coreid, oldirq+2, irq+2);
128
+
}
129
+
130
+
static void print_irq(struct ssb_device *dev, unsigned int irq)
131
+
{
132
+
int i;
133
+
static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
134
+
ssb_dprintk(KERN_INFO PFX
135
+
"core 0x%04x, irq :", dev->id.coreid);
136
+
for (i = 0; i <= 6; i++) {
137
+
ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
138
+
}
139
+
ssb_dprintk("\n");
140
+
}
141
+
142
+
static void dump_irq(struct ssb_bus *bus)
143
+
{
144
+
int i;
145
+
for (i = 0; i < bus->nr_devices; i++) {
146
+
struct ssb_device *dev;
147
+
dev = &(bus->devices[i]);
148
+
print_irq(dev, ssb_mips_irq(dev));
143
149
}
144
150
}
145
151
···
253
197
254
198
/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
255
199
for (irq = 2, i = 0; i < bus->nr_devices; i++) {
200
+
int mips_irq;
256
201
dev = &(bus->devices[i]);
257
-
dev->irq = ssb_mips_irq(dev) + 2;
202
+
mips_irq = ssb_mips_irq(dev);
203
+
if (mips_irq > 4)
204
+
dev->irq = 0;
205
+
else
206
+
dev->irq = mips_irq + 2;
207
+
if (dev->irq > 5)
208
+
continue;
258
209
switch (dev->id.coreid) {
259
210
case SSB_DEV_USB11_HOST:
260
211
/* shouldn't need a separate irq line for non-4710, most of them have a proper
261
212
* external usb controller on the pci */
262
213
if ((bus->chip_id == 0x4710) && (irq <= 4)) {
263
214
set_irq(dev, irq++);
264
-
break;
265
215
}
216
+
break;
266
217
/* fallthrough */
267
218
case SSB_DEV_PCI:
268
219
case SSB_DEV_ETHERNET:
···
283
220
}
284
221
}
285
222
}
223
+
ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
224
+
dump_irq(bus);
286
225
287
226
ssb_mips_serial_init(mcore);
288
227
ssb_mips_flash_detect(mcore);
+1
-1
drivers/video/cobalt_lcdfb.c
+1
-1
drivers/video/cobalt_lcdfb.c
···
1
1
/*
2
2
* Cobalt server LCD frame buffer driver.
3
3
*
4
-
* Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
4
+
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
5
5
*
6
6
* This program is free software; you can redistribute it and/or modify
7
7
* it under the terms of the GNU General Public License as published by