Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'add-netc-timer-ptp-driver-and-add-ptp-support-for-i-mx95'
Wei Fang says:
====================
Add NETC Timer PTP driver and add PTP support for i.MX95
This series adds NETC Timer PTP clock driver, which supports precise
periodic pulse, time capture on external pulse and PTP synchronization.
It also adds PTP support to the enetc v4 driver for i.MX95 and optimizes
the PTP-related code in the enetc driver.
====================
Link: https://patch.msgid.link/20250829050615.1247468-1-wei.fang@nxp.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+1416
-107
+5
Documentation/devicetree/bindings/net/ethernet-controller.yaml
+5
Documentation/devicetree/bindings/net/ethernet-controller.yaml
···
108
108
$ref: "#/properties/phy-handle"
109
109
deprecated: true
110
110
111
+
ptp-timer:
112
+
$ref: /schemas/types.yaml#/definitions/phandle
113
+
description:
114
+
Specifies a reference to a node representing an IEEE 1588 PTP device.
115
+
111
116
rx-fifo-depth:
112
117
$ref: /schemas/types.yaml#/definitions/uint32
113
118
description:
-4
Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
-4
Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
···
81
81
An array of two references: the first is the FMan RX port and the second
82
82
is the TX port used by this MAC.
83
83
84
-
ptp-timer:
85
-
$ref: /schemas/types.yaml#/definitions/phandle
86
-
description: A reference to the IEEE1588 timer
87
-
88
84
phys:
89
85
description: A reference to the SerDes lane(s)
90
86
maxItems: 1
+63
Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml
+63
Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ptp/nxp,ptp-netc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP NETC V4 Timer PTP clock
8
+
9
+
description:
10
+
NETC V4 Timer provides current time with nanosecond resolution, precise
11
+
periodic pulse, pulse on timeout (alarm), and time capture on external
12
+
pulse support. And it supports time synchronization as required for
13
+
IEEE 1588 and IEEE 802.1AS-2020.
14
+
15
+
maintainers:
16
+
- Wei Fang <wei.fang@nxp.com>
17
+
- Clark Wang <xiaoning.wang@nxp.com>
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- pci1131,ee02
23
+
24
+
reg:
25
+
maxItems: 1
26
+
27
+
clocks:
28
+
maxItems: 1
29
+
description:
30
+
The reference clock of NETC Timer, can be selected between 3 different
31
+
clock sources using an integrated hardware mux TMR_CTRL[CK_SEL].
32
+
The "ccm" means the reference clock comes from CCM of SoC.
33
+
The "ext" means the reference clock comes from external IO pins.
34
+
If not present, indicates that the system clock of NETC IP is selected
35
+
as the reference clock.
36
+
37
+
clock-names:
38
+
enum:
39
+
- ccm
40
+
- ext
41
+
42
+
required:
43
+
- compatible
44
+
- reg
45
+
46
+
allOf:
47
+
- $ref: /schemas/pci/pci-device.yaml
48
+
49
+
unevaluatedProperties: false
50
+
51
+
examples:
52
+
- |
53
+
pcie {
54
+
#address-cells = <3>;
55
+
#size-cells = <2>;
56
+
57
+
ptp-timer@18,0 {
58
+
compatible = "pci1131,ee02";
59
+
reg = <0x00c000 0 0 0 0>;
60
+
clocks = <&scmi_clk 18>;
61
+
clock-names = "ccm";
62
+
};
63
+
};
+9
MAINTAINERS
+9
MAINTAINERS
···
18292
18292
F: drivers/clk/imx/
18293
18293
F: include/dt-bindings/clock/*imx*
18294
18294
18295
+
NXP NETC TIMER PTP CLOCK DRIVER
18296
+
M: Wei Fang <wei.fang@nxp.com>
18297
+
M: Clark Wang <xiaoning.wang@nxp.com>
18298
+
L: imx@lists.linux.dev
18299
+
L: netdev@vger.kernel.org
18300
+
S: Maintained
18301
+
F: Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml
18302
+
F: drivers/ptp/ptp_netc.c
18303
+
18295
18304
NXP PF8100/PF8121A/PF8200 PMIC REGULATOR DEVICE DRIVER
18296
18305
M: Jagan Teki <jagan@amarulasolutions.com>
18297
18306
S: Maintained
+3
drivers/net/ethernet/freescale/enetc/Kconfig
+3
drivers/net/ethernet/freescale/enetc/Kconfig
···
28
28
29
29
config FSL_ENETC
30
30
tristate "ENETC PF driver"
31
+
depends on PTP_1588_CLOCK_OPTIONAL
31
32
depends on PCI_MSI
32
33
select FSL_ENETC_CORE
33
34
select FSL_ENETC_IERB
···
46
45
47
46
config NXP_ENETC4
48
47
tristate "ENETC4 PF driver"
48
+
depends on PTP_1588_CLOCK_OPTIONAL
49
49
depends on PCI_MSI
50
50
select FSL_ENETC_CORE
51
51
select FSL_ENETC_MDIO
···
64
62
65
63
config FSL_ENETC_VF
66
64
tristate "ENETC VF driver"
65
+
depends on PTP_1588_CLOCK_OPTIONAL
67
66
depends on PCI_MSI
68
67
select FSL_ENETC_CORE
69
68
select FSL_ENETC_MDIO
+123
-86
drivers/net/ethernet/freescale/enetc/enetc.c
+123
-86
drivers/net/ethernet/freescale/enetc/enetc.c
···
221
221
}
222
222
}
223
223
224
+
static void enetc_set_one_step_ts(struct enetc_si *si, bool udp, int offset)
225
+
{
226
+
u32 val = ENETC_PM0_SINGLE_STEP_EN;
227
+
228
+
val |= ENETC_SET_SINGLE_STEP_OFFSET(offset);
229
+
if (udp)
230
+
val |= ENETC_PM0_SINGLE_STEP_CH;
231
+
232
+
/* The "Correction" field of a packet is updated based on the
233
+
* current time and the timestamp provided
234
+
*/
235
+
enetc_port_mac_wr(si, ENETC_PM0_SINGLE_STEP, val);
236
+
}
237
+
238
+
static void enetc4_set_one_step_ts(struct enetc_si *si, bool udp, int offset)
239
+
{
240
+
u32 val = PM_SINGLE_STEP_EN;
241
+
242
+
val |= PM_SINGLE_STEP_OFFSET_SET(offset);
243
+
if (udp)
244
+
val |= PM_SINGLE_STEP_CH;
245
+
246
+
enetc_port_mac_wr(si, ENETC4_PM_SINGLE_STEP(0), val);
247
+
}
248
+
249
+
static u32 enetc_update_ptp_sync_msg(struct enetc_ndev_priv *priv,
250
+
struct sk_buff *skb, bool csum_offload)
251
+
{
252
+
struct enetc_skb_cb *enetc_cb = ENETC_SKB_CB(skb);
253
+
u16 tstamp_off = enetc_cb->origin_tstamp_off;
254
+
u16 corr_off = enetc_cb->correction_off;
255
+
struct enetc_si *si = priv->si;
256
+
struct enetc_hw *hw = &si->hw;
257
+
__be32 new_sec_l, new_nsec;
258
+
__be16 new_sec_h;
259
+
u32 lo, hi, nsec;
260
+
u8 *data;
261
+
u64 sec;
262
+
263
+
lo = enetc_rd_hot(hw, ENETC_SICTR0);
264
+
hi = enetc_rd_hot(hw, ENETC_SICTR1);
265
+
sec = (u64)hi << 32 | lo;
266
+
nsec = do_div(sec, 1000000000);
267
+
268
+
/* Update originTimestamp field of Sync packet
269
+
* - 48 bits seconds field
270
+
* - 32 bits nanseconds field
271
+
*
272
+
* In addition, if csum_offload is false, the UDP checksum needs
273
+
* to be updated by software after updating originTimestamp field,
274
+
* otherwise the hardware will calculate the wrong checksum when
275
+
* updating the correction field and update it to the packet.
276
+
*/
277
+
278
+
data = skb_mac_header(skb);
279
+
new_sec_h = htons((sec >> 32) & 0xffff);
280
+
new_sec_l = htonl(sec & 0xffffffff);
281
+
new_nsec = htonl(nsec);
282
+
if (enetc_cb->udp && !csum_offload) {
283
+
struct udphdr *uh = udp_hdr(skb);
284
+
__be32 old_sec_l, old_nsec;
285
+
__be16 old_sec_h;
286
+
287
+
old_sec_h = *(__be16 *)(data + tstamp_off);
288
+
inet_proto_csum_replace2(&uh->check, skb, old_sec_h,
289
+
new_sec_h, false);
290
+
291
+
old_sec_l = *(__be32 *)(data + tstamp_off + 2);
292
+
inet_proto_csum_replace4(&uh->check, skb, old_sec_l,
293
+
new_sec_l, false);
294
+
295
+
old_nsec = *(__be32 *)(data + tstamp_off + 6);
296
+
inet_proto_csum_replace4(&uh->check, skb, old_nsec,
297
+
new_nsec, false);
298
+
}
299
+
300
+
*(__be16 *)(data + tstamp_off) = new_sec_h;
301
+
*(__be32 *)(data + tstamp_off + 2) = new_sec_l;
302
+
*(__be32 *)(data + tstamp_off + 6) = new_nsec;
303
+
304
+
/* Configure single-step register */
305
+
if (is_enetc_rev1(si))
306
+
enetc_set_one_step_ts(si, enetc_cb->udp, corr_off);
307
+
else
308
+
enetc4_set_one_step_ts(si, enetc_cb->udp, corr_off);
309
+
310
+
return lo & ENETC_TXBD_TSTAMP;
311
+
}
312
+
224
313
static int enetc_map_tx_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb)
225
314
{
226
315
bool do_vlan, do_onestep_tstamp = false, do_twostep_tstamp = false;
227
316
struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev);
228
-
struct enetc_hw *hw = &priv->si->hw;
317
+
struct enetc_skb_cb *enetc_cb = ENETC_SKB_CB(skb);
229
318
struct enetc_tx_swbd *tx_swbd;
230
319
int len = skb_headlen(skb);
231
320
union enetc_tx_bd temp_bd;
232
-
u8 msgtype, twostep, udp;
321
+
bool csum_offload = false;
233
322
union enetc_tx_bd *txbd;
234
-
u16 offset1, offset2;
235
323
int i, count = 0;
236
324
skb_frag_t *frag;
237
325
unsigned int f;
238
326
dma_addr_t dma;
239
327
u8 flags = 0;
328
+
u32 tstamp;
240
329
241
330
enetc_clear_tx_bd(&temp_bd);
242
331
if (skb->ip_summed == CHECKSUM_PARTIAL) {
···
345
256
temp_bd.l4_aux = FIELD_PREP(ENETC_TX_BD_L4T,
346
257
ENETC_TXBD_L4T_UDP);
347
258
flags |= ENETC_TXBD_FLAGS_CSUM_LSO | ENETC_TXBD_FLAGS_L4CS;
259
+
csum_offload = true;
348
260
} else if (skb_checksum_help(skb)) {
349
261
return 0;
350
262
}
263
+
}
264
+
265
+
if (enetc_cb->flag & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
266
+
do_onestep_tstamp = true;
267
+
tstamp = enetc_update_ptp_sync_msg(priv, skb, csum_offload);
268
+
} else if (enetc_cb->flag & ENETC_F_TX_TSTAMP) {
269
+
do_twostep_tstamp = true;
351
270
}
352
271
353
272
i = tx_ring->next_to_use;
···
377
280
count++;
378
281
379
282
do_vlan = skb_vlan_tag_present(skb);
380
-
if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
381
-
if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep, &offset1,
382
-
&offset2) ||
383
-
msgtype != PTP_MSGTYPE_SYNC || twostep)
384
-
WARN_ONCE(1, "Bad packet for one-step timestamping\n");
385
-
else
386
-
do_onestep_tstamp = true;
387
-
} else if (skb->cb[0] & ENETC_F_TX_TSTAMP) {
388
-
do_twostep_tstamp = true;
389
-
}
390
-
391
283
tx_swbd->do_twostep_tstamp = do_twostep_tstamp;
392
284
tx_swbd->qbv_en = !!(priv->active_offloads & ENETC_F_QBV);
393
285
tx_swbd->check_wb = tx_swbd->do_twostep_tstamp || tx_swbd->qbv_en;
···
419
333
}
420
334
421
335
if (do_onestep_tstamp) {
422
-
__be32 new_sec_l, new_nsec;
423
-
u32 lo, hi, nsec, val;
424
-
__be16 new_sec_h;
425
-
u8 *data;
426
-
u64 sec;
427
-
428
-
lo = enetc_rd_hot(hw, ENETC_SICTR0);
429
-
hi = enetc_rd_hot(hw, ENETC_SICTR1);
430
-
sec = (u64)hi << 32 | lo;
431
-
nsec = do_div(sec, 1000000000);
432
-
433
336
/* Configure extension BD */
434
-
temp_bd.ext.tstamp = cpu_to_le32(lo & 0x3fffffff);
337
+
temp_bd.ext.tstamp = cpu_to_le32(tstamp);
435
338
e_flags |= ENETC_TXBD_E_FLAGS_ONE_STEP_PTP;
436
-
437
-
/* Update originTimestamp field of Sync packet
438
-
* - 48 bits seconds field
439
-
* - 32 bits nanseconds field
440
-
*
441
-
* In addition, the UDP checksum needs to be updated
442
-
* by software after updating originTimestamp field,
443
-
* otherwise the hardware will calculate the wrong
444
-
* checksum when updating the correction field and
445
-
* update it to the packet.
446
-
*/
447
-
data = skb_mac_header(skb);
448
-
new_sec_h = htons((sec >> 32) & 0xffff);
449
-
new_sec_l = htonl(sec & 0xffffffff);
450
-
new_nsec = htonl(nsec);
451
-
if (udp) {
452
-
struct udphdr *uh = udp_hdr(skb);
453
-
__be32 old_sec_l, old_nsec;
454
-
__be16 old_sec_h;
455
-
456
-
old_sec_h = *(__be16 *)(data + offset2);
457
-
inet_proto_csum_replace2(&uh->check, skb, old_sec_h,
458
-
new_sec_h, false);
459
-
460
-
old_sec_l = *(__be32 *)(data + offset2 + 2);
461
-
inet_proto_csum_replace4(&uh->check, skb, old_sec_l,
462
-
new_sec_l, false);
463
-
464
-
old_nsec = *(__be32 *)(data + offset2 + 6);
465
-
inet_proto_csum_replace4(&uh->check, skb, old_nsec,
466
-
new_nsec, false);
467
-
}
468
-
469
-
*(__be16 *)(data + offset2) = new_sec_h;
470
-
*(__be32 *)(data + offset2 + 2) = new_sec_l;
471
-
*(__be32 *)(data + offset2 + 6) = new_nsec;
472
-
473
-
/* Configure single-step register */
474
-
val = ENETC_PM0_SINGLE_STEP_EN;
475
-
val |= ENETC_SET_SINGLE_STEP_OFFSET(offset1);
476
-
if (udp)
477
-
val |= ENETC_PM0_SINGLE_STEP_CH;
478
-
479
-
enetc_port_mac_wr(priv->si, ENETC_PM0_SINGLE_STEP,
480
-
val);
481
339
} else if (do_twostep_tstamp) {
482
340
skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
483
341
e_flags |= ENETC_TXBD_E_FLAGS_TWO_STEP_PTP;
···
968
938
static netdev_tx_t enetc_start_xmit(struct sk_buff *skb,
969
939
struct net_device *ndev)
970
940
{
941
+
struct enetc_skb_cb *enetc_cb = ENETC_SKB_CB(skb);
971
942
struct enetc_ndev_priv *priv = netdev_priv(ndev);
972
943
struct enetc_bdr *tx_ring;
973
944
int count;
974
945
975
946
/* Queue one-step Sync packet if already locked */
976
-
if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
947
+
if (enetc_cb->flag & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
977
948
if (test_and_set_bit_lock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS,
978
949
&priv->flags)) {
979
950
skb_queue_tail(&priv->tx_skbs, skb);
···
1036
1005
1037
1006
netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev)
1038
1007
{
1008
+
struct enetc_skb_cb *enetc_cb = ENETC_SKB_CB(skb);
1039
1009
struct enetc_ndev_priv *priv = netdev_priv(ndev);
1040
1010
u8 udp, msgtype, twostep;
1041
1011
u16 offset1, offset2;
1042
1012
1043
-
/* Mark tx timestamp type on skb->cb[0] if requires */
1013
+
/* Mark tx timestamp type on enetc_cb->flag if requires */
1044
1014
if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1045
-
(priv->active_offloads & ENETC_F_TX_TSTAMP_MASK)) {
1046
-
skb->cb[0] = priv->active_offloads & ENETC_F_TX_TSTAMP_MASK;
1047
-
} else {
1048
-
skb->cb[0] = 0;
1049
-
}
1015
+
(priv->active_offloads & ENETC_F_TX_TSTAMP_MASK))
1016
+
enetc_cb->flag = priv->active_offloads & ENETC_F_TX_TSTAMP_MASK;
1017
+
else
1018
+
enetc_cb->flag = 0;
1050
1019
1051
1020
/* Fall back to two-step timestamp if not one-step Sync packet */
1052
-
if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
1021
+
if (enetc_cb->flag & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
1053
1022
if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep,
1054
1023
&offset1, &offset2) ||
1055
-
msgtype != PTP_MSGTYPE_SYNC || twostep != 0)
1056
-
skb->cb[0] = ENETC_F_TX_TSTAMP;
1024
+
msgtype != PTP_MSGTYPE_SYNC || twostep != 0) {
1025
+
enetc_cb->flag = ENETC_F_TX_TSTAMP;
1026
+
} else {
1027
+
enetc_cb->udp = !!udp;
1028
+
enetc_cb->correction_off = offset1;
1029
+
enetc_cb->origin_tstamp_off = offset2;
1030
+
}
1057
1031
}
1058
1032
1059
1033
return enetc_start_xmit(skb, ndev);
···
1250
1214
if (xdp_frame) {
1251
1215
xdp_return_frame(xdp_frame);
1252
1216
} else if (skb) {
1253
-
if (unlikely(skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP)) {
1217
+
struct enetc_skb_cb *enetc_cb = ENETC_SKB_CB(skb);
1218
+
1219
+
if (unlikely(enetc_cb->flag & ENETC_F_TX_ONESTEP_SYNC_TSTAMP)) {
1254
1220
/* Start work to release lock for next one-step
1255
1221
* timestamping packet. And send one skb in
1256
1222
* tx_skbs queue if has.
···
1435
1397
__vlan_hwaccel_put_tag(skb, tpid, le16_to_cpu(rxbd->r.vlan_opt));
1436
1398
}
1437
1399
1438
-
if (IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK) &&
1439
-
(priv->active_offloads & ENETC_F_RX_TSTAMP))
1400
+
if (priv->active_offloads & ENETC_F_RX_TSTAMP)
1440
1401
enetc_get_rx_tstamp(rx_ring->ndev, rxbd, skb);
1441
1402
}
1442
1403
···
3338
3301
struct enetc_ndev_priv *priv = netdev_priv(ndev);
3339
3302
int err, new_offloads = priv->active_offloads;
3340
3303
3341
-
if (!IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK))
3304
+
if (!enetc_ptp_clock_is_enabled(priv->si))
3342
3305
return -EOPNOTSUPP;
3343
3306
3344
3307
switch (config->tx_type) {
···
3388
3351
{
3389
3352
struct enetc_ndev_priv *priv = netdev_priv(ndev);
3390
3353
3391
-
if (!IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK))
3354
+
if (!enetc_ptp_clock_is_enabled(priv->si))
3392
3355
return -EOPNOTSUPP;
3393
3356
3394
3357
if (priv->active_offloads & ENETC_F_TX_ONESTEP_SYNC_TSTAMP)
+19
-2
drivers/net/ethernet/freescale/enetc/enetc.h
+19
-2
drivers/net/ethernet/freescale/enetc/enetc.h
···
54
54
u8 qbv_en:1;
55
55
};
56
56
57
+
struct enetc_skb_cb {
58
+
u8 flag;
59
+
bool udp;
60
+
u16 correction_off;
61
+
u16 origin_tstamp_off;
62
+
};
63
+
64
+
#define ENETC_SKB_CB(skb) ((struct enetc_skb_cb *)((skb)->cb))
65
+
57
66
struct enetc_lso_t {
58
67
bool ipv6;
59
68
bool tcp;
···
226
217
{
227
218
int hw_idx = i;
228
219
229
-
if (IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK) && rx_ring->ext_en)
220
+
if (rx_ring->ext_en)
230
221
hw_idx = 2 * i;
231
222
232
223
return &(((union enetc_rx_bd *)rx_ring->bd_base)[hw_idx]);
···
240
231
241
232
new_rxbd++;
242
233
243
-
if (IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK) && rx_ring->ext_en)
234
+
if (rx_ring->ext_en)
244
235
new_rxbd++;
245
236
246
237
if (unlikely(++new_index == rx_ring->bd_count)) {
···
597
588
598
589
void enetc_reset_ptcmsdur(struct enetc_hw *hw);
599
590
void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *queue_max_sdu);
591
+
592
+
static inline bool enetc_ptp_clock_is_enabled(struct enetc_si *si)
593
+
{
594
+
if (is_enetc_rev1(si))
595
+
return IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK);
596
+
597
+
return IS_ENABLED(CONFIG_PTP_NETC_V4_TIMER);
598
+
}
600
599
601
600
#ifdef CONFIG_FSL_ENETC_QOS
602
601
int enetc_qos_query_caps(struct net_device *ndev, void *type_data);
+6
drivers/net/ethernet/freescale/enetc/enetc4_hw.h
+6
drivers/net/ethernet/freescale/enetc/enetc4_hw.h
···
171
171
/* Port MAC 0/1 Pause Quanta Threshold Register */
172
172
#define ENETC4_PM_PAUSE_THRESH(mac) (0x5064 + (mac) * 0x400)
173
173
174
+
#define ENETC4_PM_SINGLE_STEP(mac) (0x50c0 + (mac) * 0x400)
175
+
#define PM_SINGLE_STEP_CH BIT(6)
176
+
#define PM_SINGLE_STEP_OFFSET GENMASK(15, 7)
177
+
#define PM_SINGLE_STEP_OFFSET_SET(o) FIELD_PREP(PM_SINGLE_STEP_OFFSET, o)
178
+
#define PM_SINGLE_STEP_EN BIT(31)
179
+
174
180
/* Port MAC 0 Interface Mode Control Register */
175
181
#define ENETC4_PM_IF_MODE(mac) (0x5300 + (mac) * 0x400)
176
182
#define PM_IF_MODE_IFMODE GENMASK(2, 0)
+3
drivers/net/ethernet/freescale/enetc/enetc4_pf.c
+3
drivers/net/ethernet/freescale/enetc/enetc4_pf.c
···
569
569
.ndo_set_features = enetc4_pf_set_features,
570
570
.ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
571
571
.ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
572
+
.ndo_eth_ioctl = enetc_ioctl,
573
+
.ndo_hwtstamp_get = enetc_hwtstamp_get,
574
+
.ndo_hwtstamp_set = enetc_hwtstamp_set,
572
575
};
573
576
574
577
static struct phylink_pcs *
+80
-15
drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
+80
-15
drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
···
4
4
#include <linux/ethtool_netlink.h>
5
5
#include <linux/net_tstamp.h>
6
6
#include <linux/module.h>
7
+
#include <linux/of.h>
8
+
#include <linux/ptp_clock_kernel.h>
9
+
7
10
#include "enetc.h"
8
11
9
12
static const u32 enetc_si_regs[] = {
···
880
877
return 0;
881
878
}
882
879
883
-
static int enetc_get_ts_info(struct net_device *ndev,
884
-
struct kernel_ethtool_ts_info *info)
880
+
static int enetc4_get_phc_index_by_pdev(struct enetc_si *si)
881
+
{
882
+
struct pci_bus *bus = si->pdev->bus;
883
+
struct pci_dev *timer_pdev;
884
+
unsigned int devfn;
885
+
int phc_index;
886
+
887
+
switch (si->revision) {
888
+
case ENETC_REV_4_1:
889
+
devfn = PCI_DEVFN(24, 0);
890
+
break;
891
+
default:
892
+
return -1;
893
+
}
894
+
895
+
timer_pdev = pci_get_slot(bus, devfn);
896
+
if (!timer_pdev)
897
+
return -1;
898
+
899
+
phc_index = ptp_clock_index_by_dev(&timer_pdev->dev);
900
+
pci_dev_put(timer_pdev);
901
+
902
+
return phc_index;
903
+
}
904
+
905
+
static int enetc4_get_phc_index(struct enetc_si *si)
906
+
{
907
+
struct device_node *np = si->pdev->dev.of_node;
908
+
struct device_node *timer_np;
909
+
int phc_index;
910
+
911
+
if (!np)
912
+
return enetc4_get_phc_index_by_pdev(si);
913
+
914
+
timer_np = of_parse_phandle(np, "ptp-timer", 0);
915
+
if (!timer_np)
916
+
return enetc4_get_phc_index_by_pdev(si);
917
+
918
+
phc_index = ptp_clock_index_by_of_node(timer_np);
919
+
of_node_put(timer_np);
920
+
921
+
return phc_index;
922
+
}
923
+
924
+
static void enetc_get_ts_generic_info(struct net_device *ndev,
925
+
struct kernel_ethtool_ts_info *info)
885
926
{
886
927
struct enetc_ndev_priv *priv = netdev_priv(ndev);
887
-
int *phc_idx;
888
-
889
-
phc_idx = symbol_get(enetc_phc_index);
890
-
if (phc_idx) {
891
-
info->phc_index = *phc_idx;
892
-
symbol_put(enetc_phc_index);
893
-
}
894
-
895
-
if (!IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK)) {
896
-
info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE;
897
-
898
-
return 0;
899
-
}
900
928
901
929
info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
902
930
SOF_TIMESTAMPING_RX_HARDWARE |
···
942
908
943
909
info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
944
910
(1 << HWTSTAMP_FILTER_ALL);
911
+
}
912
+
913
+
static int enetc_get_ts_info(struct net_device *ndev,
914
+
struct kernel_ethtool_ts_info *info)
915
+
{
916
+
struct enetc_ndev_priv *priv = netdev_priv(ndev);
917
+
struct enetc_si *si = priv->si;
918
+
int *phc_idx;
919
+
920
+
if (!enetc_ptp_clock_is_enabled(si))
921
+
goto timestamp_tx_sw;
922
+
923
+
if (is_enetc_rev1(si)) {
924
+
phc_idx = symbol_get(enetc_phc_index);
925
+
if (phc_idx) {
926
+
info->phc_index = *phc_idx;
927
+
symbol_put(enetc_phc_index);
928
+
}
929
+
} else {
930
+
info->phc_index = enetc4_get_phc_index(si);
931
+
if (info->phc_index < 0)
932
+
goto timestamp_tx_sw;
933
+
}
934
+
935
+
enetc_get_ts_generic_info(ndev, info);
936
+
937
+
return 0;
938
+
939
+
timestamp_tx_sw:
940
+
info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE;
945
941
946
942
return 0;
947
943
}
···
1360
1296
.get_rxfh = enetc_get_rxfh,
1361
1297
.set_rxfh = enetc_set_rxfh,
1362
1298
.get_rxfh_fields = enetc_get_rxfh_fields,
1299
+
.get_ts_info = enetc_get_ts_info,
1363
1300
};
1364
1301
1365
1302
void enetc_set_ethtool_ops(struct net_device *ndev)
+1
drivers/net/ethernet/freescale/enetc/enetc_hw.h
+1
drivers/net/ethernet/freescale/enetc/enetc_hw.h
+11
drivers/ptp/Kconfig
+11
drivers/ptp/Kconfig
···
252
252
driver provides the raw clock value without the delta to
253
253
userspace. That way userspace programs like chrony could steer
254
254
the kernel clock.
255
+
256
+
config PTP_NETC_V4_TIMER
257
+
tristate "NXP NETC V4 Timer PTP Driver"
258
+
depends on PTP_1588_CLOCK
259
+
depends on PCI_MSI
260
+
help
261
+
This driver adds support for using the NXP NETC V4 Timer as a PTP
262
+
clock, the clock is used by ENETC V4 or NETC V4 Switch for PTP time
263
+
synchronization. It also supports periodic output signal (e.g. PPS)
264
+
and external trigger timestamping.
265
+
255
266
endmenu
+1
drivers/ptp/Makefile
+1
drivers/ptp/Makefile
+53
drivers/ptp/ptp_clock.c
+53
drivers/ptp/ptp_clock.c
···
11
11
#include <linux/module.h>
12
12
#include <linux/posix-clock.h>
13
13
#include <linux/pps_kernel.h>
14
+
#include <linux/property.h>
14
15
#include <linux/slab.h>
15
16
#include <linux/syscalls.h>
16
17
#include <linux/uaccess.h>
···
488
487
return ptp->index;
489
488
}
490
489
EXPORT_SYMBOL(ptp_clock_index);
490
+
491
+
static int ptp_clock_of_node_match(struct device *dev, const void *data)
492
+
{
493
+
const struct device_node *parent_np = data;
494
+
495
+
return (dev->parent && dev_of_node(dev->parent) == parent_np);
496
+
}
497
+
498
+
int ptp_clock_index_by_of_node(struct device_node *np)
499
+
{
500
+
struct ptp_clock *ptp;
501
+
struct device *dev;
502
+
int phc_index;
503
+
504
+
dev = class_find_device(&ptp_class, NULL, np,
505
+
ptp_clock_of_node_match);
506
+
if (!dev)
507
+
return -1;
508
+
509
+
ptp = dev_get_drvdata(dev);
510
+
phc_index = ptp_clock_index(ptp);
511
+
put_device(dev);
512
+
513
+
return phc_index;
514
+
}
515
+
EXPORT_SYMBOL_GPL(ptp_clock_index_by_of_node);
516
+
517
+
static int ptp_clock_dev_match(struct device *dev, const void *data)
518
+
{
519
+
const struct device *parent = data;
520
+
521
+
return dev->parent == parent;
522
+
}
523
+
524
+
int ptp_clock_index_by_dev(struct device *parent)
525
+
{
526
+
struct ptp_clock *ptp;
527
+
struct device *dev;
528
+
int phc_index;
529
+
530
+
dev = class_find_device(&ptp_class, NULL, parent,
531
+
ptp_clock_dev_match);
532
+
if (!dev)
533
+
return -1;
534
+
535
+
ptp = dev_get_drvdata(dev);
536
+
phc_index = ptp_clock_index(ptp);
537
+
put_device(dev);
538
+
539
+
return phc_index;
540
+
}
541
+
EXPORT_SYMBOL_GPL(ptp_clock_index_by_dev);
491
542
492
543
int ptp_find_pin(struct ptp_clock *ptp,
493
544
enum ptp_pin_function func, unsigned int chan)
+1017
drivers/ptp/ptp_netc.c
+1017
drivers/ptp/ptp_netc.c
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2
+
/*
3
+
* NXP NETC V4 Timer driver
4
+
* Copyright 2025 NXP
5
+
*/
6
+
7
+
#include <linux/bitfield.h>
8
+
#include <linux/clk.h>
9
+
#include <linux/fsl/netc_global.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of.h>
12
+
#include <linux/of_platform.h>
13
+
#include <linux/pci.h>
14
+
#include <linux/ptp_clock_kernel.h>
15
+
16
+
#define NETC_TMR_PCI_VENDOR_NXP 0x1131
17
+
18
+
#define NETC_TMR_CTRL 0x0080
19
+
#define TMR_CTRL_CK_SEL GENMASK(1, 0)
20
+
#define TMR_CTRL_TE BIT(2)
21
+
#define TMR_ETEP(i) BIT(8 + (i))
22
+
#define TMR_COMP_MODE BIT(15)
23
+
#define TMR_CTRL_TCLK_PERIOD GENMASK(25, 16)
24
+
#define TMR_CTRL_FS BIT(28)
25
+
26
+
#define NETC_TMR_TEVENT 0x0084
27
+
#define TMR_TEVNET_PPEN(i) BIT(7 - (i))
28
+
#define TMR_TEVENT_PPEN_ALL GENMASK(7, 5)
29
+
#define TMR_TEVENT_ALMEN(i) BIT(16 + (i))
30
+
#define TMR_TEVENT_ETS_THREN(i) BIT(20 + (i))
31
+
#define TMR_TEVENT_ETSEN(i) BIT(24 + (i))
32
+
#define TMR_TEVENT_ETS_OVEN(i) BIT(28 + (i))
33
+
#define TMR_TEVENT_ETS(i) (TMR_TEVENT_ETS_THREN(i) | \
34
+
TMR_TEVENT_ETSEN(i) | \
35
+
TMR_TEVENT_ETS_OVEN(i))
36
+
37
+
#define NETC_TMR_TEMASK 0x0088
38
+
#define NETC_TMR_STAT 0x0094
39
+
#define TMR_STAT_ETS_VLD(i) BIT(24 + (i))
40
+
41
+
#define NETC_TMR_CNT_L 0x0098
42
+
#define NETC_TMR_CNT_H 0x009c
43
+
#define NETC_TMR_ADD 0x00a0
44
+
#define NETC_TMR_PRSC 0x00a8
45
+
#define NETC_TMR_ECTRL 0x00ac
46
+
#define NETC_TMR_OFF_L 0x00b0
47
+
#define NETC_TMR_OFF_H 0x00b4
48
+
49
+
/* i = 0, 1, i indicates the index of TMR_ALARM */
50
+
#define NETC_TMR_ALARM_L(i) (0x00b8 + (i) * 8)
51
+
#define NETC_TMR_ALARM_H(i) (0x00bc + (i) * 8)
52
+
53
+
/* i = 0, 1, 2. i indicates the index of TMR_FIPER. */
54
+
#define NETC_TMR_FIPER(i) (0x00d0 + (i) * 4)
55
+
56
+
#define NETC_TMR_FIPER_CTRL 0x00dc
57
+
#define FIPER_CTRL_DIS(i) (BIT(7) << (i) * 8)
58
+
#define FIPER_CTRL_PG(i) (BIT(6) << (i) * 8)
59
+
#define FIPER_CTRL_FS_ALARM(i) (BIT(5) << (i) * 8)
60
+
#define FIPER_CTRL_PW(i) (GENMASK(4, 0) << (i) * 8)
61
+
#define FIPER_CTRL_SET_PW(i, v) (((v) & GENMASK(4, 0)) << 8 * (i))
62
+
63
+
/* i = 0, 1, i indicates the index of TMR_ETTS */
64
+
#define NETC_TMR_ETTS_L(i) (0x00e0 + (i) * 8)
65
+
#define NETC_TMR_ETTS_H(i) (0x00e4 + (i) * 8)
66
+
#define NETC_TMR_CUR_TIME_L 0x00f0
67
+
#define NETC_TMR_CUR_TIME_H 0x00f4
68
+
69
+
#define NETC_TMR_REGS_BAR 0
70
+
#define NETC_GLOBAL_OFFSET 0x10000
71
+
#define NETC_GLOBAL_IPBRR0 0xbf8
72
+
#define IPBRR0_IP_REV GENMASK(15, 0)
73
+
#define NETC_REV_4_1 0x0401
74
+
75
+
#define NETC_TMR_FIPER_NUM 3
76
+
#define NETC_TMR_INVALID_CHANNEL NETC_TMR_FIPER_NUM
77
+
#define NETC_TMR_DEFAULT_PRSC 2
78
+
#define NETC_TMR_DEFAULT_ALARM GENMASK_ULL(63, 0)
79
+
#define NETC_TMR_DEFAULT_FIPER GENMASK(31, 0)
80
+
#define NETC_TMR_FIPER_MAX_PW GENMASK(4, 0)
81
+
#define NETC_TMR_ALARM_NUM 2
82
+
#define NETC_TMR_DEFAULT_ETTF_THR 7
83
+
84
+
/* 1588 timer reference clock source select */
85
+
#define NETC_TMR_CCM_TIMER1 0 /* enet_timer1_clk_root, from CCM */
86
+
#define NETC_TMR_SYSTEM_CLK 1 /* enet_clk_root/2, from CCM */
87
+
#define NETC_TMR_EXT_OSC 2 /* tmr_1588_clk, from IO pins */
88
+
89
+
#define NETC_TMR_SYSCLK_333M 333333333U
90
+
91
+
enum netc_pp_type {
92
+
NETC_PP_PPS = 1,
93
+
NETC_PP_PEROUT,
94
+
};
95
+
96
+
struct netc_pp {
97
+
enum netc_pp_type type;
98
+
bool enabled;
99
+
int alarm_id;
100
+
u32 period; /* pulse period, ns */
101
+
u64 stime; /* start time, ns */
102
+
};
103
+
104
+
struct netc_timer {
105
+
void __iomem *base;
106
+
struct pci_dev *pdev;
107
+
spinlock_t lock; /* Prevent concurrent access to registers */
108
+
109
+
struct ptp_clock *clock;
110
+
struct ptp_clock_info caps;
111
+
u32 clk_select;
112
+
u32 clk_freq;
113
+
u32 oclk_prsc;
114
+
/* High 32-bit is integer part, low 32-bit is fractional part */
115
+
u64 period;
116
+
117
+
int irq;
118
+
char irq_name[24];
119
+
int revision;
120
+
u32 tmr_emask;
121
+
u8 pps_channel;
122
+
u8 fs_alarm_num;
123
+
u8 fs_alarm_bitmap;
124
+
struct netc_pp pp[NETC_TMR_FIPER_NUM]; /* periodic pulse */
125
+
};
126
+
127
+
#define netc_timer_rd(p, o) netc_read((p)->base + (o))
128
+
#define netc_timer_wr(p, o, v) netc_write((p)->base + (o), v)
129
+
#define ptp_to_netc_timer(ptp) container_of((ptp), struct netc_timer, caps)
130
+
131
+
static const char *const timer_clk_src[] = {
132
+
"ccm",
133
+
"ext"
134
+
};
135
+
136
+
static void netc_timer_cnt_write(struct netc_timer *priv, u64 ns)
137
+
{
138
+
u32 tmr_cnt_h = upper_32_bits(ns);
139
+
u32 tmr_cnt_l = lower_32_bits(ns);
140
+
141
+
/* Writes to the TMR_CNT_L register copies the written value
142
+
* into the shadow TMR_CNT_L register. Writes to the TMR_CNT_H
143
+
* register copies the values written into the shadow TMR_CNT_H
144
+
* register. Contents of the shadow registers are copied into
145
+
* the TMR_CNT_L and TMR_CNT_H registers following a write into
146
+
* the TMR_CNT_H register. So the user must writes to TMR_CNT_L
147
+
* register first. Other H/L registers should have the same
148
+
* behavior.
149
+
*/
150
+
netc_timer_wr(priv, NETC_TMR_CNT_L, tmr_cnt_l);
151
+
netc_timer_wr(priv, NETC_TMR_CNT_H, tmr_cnt_h);
152
+
}
153
+
154
+
static u64 netc_timer_offset_read(struct netc_timer *priv)
155
+
{
156
+
u32 tmr_off_l, tmr_off_h;
157
+
u64 offset;
158
+
159
+
tmr_off_l = netc_timer_rd(priv, NETC_TMR_OFF_L);
160
+
tmr_off_h = netc_timer_rd(priv, NETC_TMR_OFF_H);
161
+
offset = (((u64)tmr_off_h) << 32) | tmr_off_l;
162
+
163
+
return offset;
164
+
}
165
+
166
+
static void netc_timer_offset_write(struct netc_timer *priv, u64 offset)
167
+
{
168
+
u32 tmr_off_h = upper_32_bits(offset);
169
+
u32 tmr_off_l = lower_32_bits(offset);
170
+
171
+
netc_timer_wr(priv, NETC_TMR_OFF_L, tmr_off_l);
172
+
netc_timer_wr(priv, NETC_TMR_OFF_H, tmr_off_h);
173
+
}
174
+
175
+
static u64 netc_timer_cur_time_read(struct netc_timer *priv)
176
+
{
177
+
u32 time_h, time_l;
178
+
u64 ns;
179
+
180
+
/* The user should read NETC_TMR_CUR_TIME_L first to
181
+
* get correct current time.
182
+
*/
183
+
time_l = netc_timer_rd(priv, NETC_TMR_CUR_TIME_L);
184
+
time_h = netc_timer_rd(priv, NETC_TMR_CUR_TIME_H);
185
+
ns = (u64)time_h << 32 | time_l;
186
+
187
+
return ns;
188
+
}
189
+
190
+
static void netc_timer_alarm_write(struct netc_timer *priv,
191
+
u64 alarm, int index)
192
+
{
193
+
u32 alarm_h = upper_32_bits(alarm);
194
+
u32 alarm_l = lower_32_bits(alarm);
195
+
196
+
netc_timer_wr(priv, NETC_TMR_ALARM_L(index), alarm_l);
197
+
netc_timer_wr(priv, NETC_TMR_ALARM_H(index), alarm_h);
198
+
}
199
+
200
+
static u32 netc_timer_get_integral_period(struct netc_timer *priv)
201
+
{
202
+
u32 tmr_ctrl, integral_period;
203
+
204
+
tmr_ctrl = netc_timer_rd(priv, NETC_TMR_CTRL);
205
+
integral_period = FIELD_GET(TMR_CTRL_TCLK_PERIOD, tmr_ctrl);
206
+
207
+
return integral_period;
208
+
}
209
+
210
+
static u32 netc_timer_calculate_fiper_pw(struct netc_timer *priv,
211
+
u32 fiper)
212
+
{
213
+
u64 divisor, pulse_width;
214
+
215
+
/* Set the FIPER pulse width to half FIPER interval by default.
216
+
* pulse_width = (fiper / 2) / TMR_GCLK_period,
217
+
* TMR_GCLK_period = NSEC_PER_SEC / TMR_GCLK_freq,
218
+
* TMR_GCLK_freq = (clk_freq / oclk_prsc) Hz,
219
+
* so pulse_width = fiper * clk_freq / (2 * NSEC_PER_SEC * oclk_prsc).
220
+
*/
221
+
divisor = mul_u32_u32(2 * NSEC_PER_SEC, priv->oclk_prsc);
222
+
pulse_width = div64_u64(mul_u32_u32(fiper, priv->clk_freq), divisor);
223
+
224
+
/* The FIPER_PW field only has 5 bits, need to update oclk_prsc */
225
+
if (pulse_width > NETC_TMR_FIPER_MAX_PW)
226
+
pulse_width = NETC_TMR_FIPER_MAX_PW;
227
+
228
+
return pulse_width;
229
+
}
230
+
231
+
static void netc_timer_set_pps_alarm(struct netc_timer *priv, int channel,
232
+
u32 integral_period)
233
+
{
234
+
struct netc_pp *pp = &priv->pp[channel];
235
+
u64 alarm;
236
+
237
+
/* Get the alarm value */
238
+
alarm = netc_timer_cur_time_read(priv) + NSEC_PER_MSEC;
239
+
alarm = roundup_u64(alarm, NSEC_PER_SEC);
240
+
alarm = roundup_u64(alarm, integral_period);
241
+
242
+
netc_timer_alarm_write(priv, alarm, pp->alarm_id);
243
+
}
244
+
245
+
static void netc_timer_set_perout_alarm(struct netc_timer *priv, int channel,
246
+
u32 integral_period)
247
+
{
248
+
u64 cur_time = netc_timer_cur_time_read(priv);
249
+
struct netc_pp *pp = &priv->pp[channel];
250
+
u64 alarm, delta, min_time;
251
+
u32 period = pp->period;
252
+
u64 stime = pp->stime;
253
+
254
+
min_time = cur_time + NSEC_PER_MSEC + period;
255
+
if (stime < min_time) {
256
+
delta = min_time - stime;
257
+
stime += roundup_u64(delta, period);
258
+
}
259
+
260
+
alarm = roundup_u64(stime - period, integral_period);
261
+
netc_timer_alarm_write(priv, alarm, pp->alarm_id);
262
+
}
263
+
264
+
static int netc_timer_get_alarm_id(struct netc_timer *priv)
265
+
{
266
+
int i;
267
+
268
+
for (i = 0; i < priv->fs_alarm_num; i++) {
269
+
if (!(priv->fs_alarm_bitmap & BIT(i))) {
270
+
priv->fs_alarm_bitmap |= BIT(i);
271
+
break;
272
+
}
273
+
}
274
+
275
+
return i;
276
+
}
277
+
278
+
static u64 netc_timer_get_gclk_period(struct netc_timer *priv)
279
+
{
280
+
/* TMR_GCLK_freq = (clk_freq / oclk_prsc) Hz.
281
+
* TMR_GCLK_period = NSEC_PER_SEC / TMR_GCLK_freq.
282
+
* TMR_GCLK_period = (NSEC_PER_SEC * oclk_prsc) / clk_freq
283
+
*/
284
+
285
+
return div_u64(mul_u32_u32(NSEC_PER_SEC, priv->oclk_prsc),
286
+
priv->clk_freq);
287
+
}
288
+
289
+
static void netc_timer_enable_periodic_pulse(struct netc_timer *priv,
290
+
u8 channel)
291
+
{
292
+
u32 fiper_pw, fiper, fiper_ctrl, integral_period;
293
+
struct netc_pp *pp = &priv->pp[channel];
294
+
int alarm_id = pp->alarm_id;
295
+
296
+
integral_period = netc_timer_get_integral_period(priv);
297
+
/* Set to desired FIPER interval in ns - TCLK_PERIOD */
298
+
fiper = pp->period - integral_period;
299
+
fiper_pw = netc_timer_calculate_fiper_pw(priv, fiper);
300
+
301
+
fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
302
+
fiper_ctrl &= ~(FIPER_CTRL_DIS(channel) | FIPER_CTRL_PW(channel) |
303
+
FIPER_CTRL_FS_ALARM(channel));
304
+
fiper_ctrl |= FIPER_CTRL_SET_PW(channel, fiper_pw);
305
+
fiper_ctrl |= alarm_id ? FIPER_CTRL_FS_ALARM(channel) : 0;
306
+
307
+
priv->tmr_emask |= TMR_TEVNET_PPEN(channel) |
308
+
TMR_TEVENT_ALMEN(alarm_id);
309
+
310
+
if (pp->type == NETC_PP_PPS)
311
+
netc_timer_set_pps_alarm(priv, channel, integral_period);
312
+
else
313
+
netc_timer_set_perout_alarm(priv, channel, integral_period);
314
+
315
+
netc_timer_wr(priv, NETC_TMR_TEMASK, priv->tmr_emask);
316
+
netc_timer_wr(priv, NETC_TMR_FIPER(channel), fiper);
317
+
netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
318
+
}
319
+
320
+
static void netc_timer_disable_periodic_pulse(struct netc_timer *priv,
321
+
u8 channel)
322
+
{
323
+
struct netc_pp *pp = &priv->pp[channel];
324
+
int alarm_id = pp->alarm_id;
325
+
u32 fiper_ctrl;
326
+
327
+
if (!pp->enabled)
328
+
return;
329
+
330
+
priv->tmr_emask &= ~(TMR_TEVNET_PPEN(channel) |
331
+
TMR_TEVENT_ALMEN(alarm_id));
332
+
333
+
fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
334
+
fiper_ctrl |= FIPER_CTRL_DIS(channel);
335
+
336
+
netc_timer_alarm_write(priv, NETC_TMR_DEFAULT_ALARM, alarm_id);
337
+
netc_timer_wr(priv, NETC_TMR_TEMASK, priv->tmr_emask);
338
+
netc_timer_wr(priv, NETC_TMR_FIPER(channel), NETC_TMR_DEFAULT_FIPER);
339
+
netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
340
+
}
341
+
342
+
static u8 netc_timer_select_pps_channel(struct netc_timer *priv)
343
+
{
344
+
int i;
345
+
346
+
for (i = 0; i < NETC_TMR_FIPER_NUM; i++) {
347
+
if (!priv->pp[i].enabled)
348
+
return i;
349
+
}
350
+
351
+
return NETC_TMR_INVALID_CHANNEL;
352
+
}
353
+
354
+
/* Note that users should not use this API to output PPS signal on
355
+
* external pins, because PTP_CLK_REQ_PPS trigger internal PPS event
356
+
* for input into kernel PPS subsystem. See:
357
+
* https://lore.kernel.org/r/20201117213826.18235-1-a.fatoum@pengutronix.de
358
+
*/
359
+
static int netc_timer_enable_pps(struct netc_timer *priv,
360
+
struct ptp_clock_request *rq, int on)
361
+
{
362
+
struct device *dev = &priv->pdev->dev;
363
+
unsigned long flags;
364
+
struct netc_pp *pp;
365
+
int err = 0;
366
+
367
+
spin_lock_irqsave(&priv->lock, flags);
368
+
369
+
if (on) {
370
+
int alarm_id;
371
+
u8 channel;
372
+
373
+
if (priv->pps_channel < NETC_TMR_FIPER_NUM) {
374
+
channel = priv->pps_channel;
375
+
} else {
376
+
channel = netc_timer_select_pps_channel(priv);
377
+
if (channel == NETC_TMR_INVALID_CHANNEL) {
378
+
dev_err(dev, "No available FIPERs\n");
379
+
err = -EBUSY;
380
+
goto unlock_spinlock;
381
+
}
382
+
}
383
+
384
+
pp = &priv->pp[channel];
385
+
if (pp->enabled)
386
+
goto unlock_spinlock;
387
+
388
+
alarm_id = netc_timer_get_alarm_id(priv);
389
+
if (alarm_id == priv->fs_alarm_num) {
390
+
dev_err(dev, "No available ALARMs\n");
391
+
err = -EBUSY;
392
+
goto unlock_spinlock;
393
+
}
394
+
395
+
pp->enabled = true;
396
+
pp->type = NETC_PP_PPS;
397
+
pp->alarm_id = alarm_id;
398
+
pp->period = NSEC_PER_SEC;
399
+
priv->pps_channel = channel;
400
+
401
+
netc_timer_enable_periodic_pulse(priv, channel);
402
+
} else {
403
+
/* pps_channel is invalid if PPS is not enabled, so no
404
+
* processing is needed.
405
+
*/
406
+
if (priv->pps_channel >= NETC_TMR_FIPER_NUM)
407
+
goto unlock_spinlock;
408
+
409
+
netc_timer_disable_periodic_pulse(priv, priv->pps_channel);
410
+
pp = &priv->pp[priv->pps_channel];
411
+
priv->fs_alarm_bitmap &= ~BIT(pp->alarm_id);
412
+
memset(pp, 0, sizeof(*pp));
413
+
priv->pps_channel = NETC_TMR_INVALID_CHANNEL;
414
+
}
415
+
416
+
unlock_spinlock:
417
+
spin_unlock_irqrestore(&priv->lock, flags);
418
+
419
+
return err;
420
+
}
421
+
422
+
static int net_timer_enable_perout(struct netc_timer *priv,
423
+
struct ptp_clock_request *rq, int on)
424
+
{
425
+
struct device *dev = &priv->pdev->dev;
426
+
u32 channel = rq->perout.index;
427
+
unsigned long flags;
428
+
struct netc_pp *pp;
429
+
int err = 0;
430
+
431
+
spin_lock_irqsave(&priv->lock, flags);
432
+
433
+
pp = &priv->pp[channel];
434
+
if (pp->type == NETC_PP_PPS) {
435
+
dev_err(dev, "FIPER%u is being used for PPS\n", channel);
436
+
err = -EBUSY;
437
+
goto unlock_spinlock;
438
+
}
439
+
440
+
if (on) {
441
+
u64 period_ns, gclk_period, max_period, min_period;
442
+
struct timespec64 period, stime;
443
+
u32 integral_period;
444
+
int alarm_id;
445
+
446
+
period.tv_sec = rq->perout.period.sec;
447
+
period.tv_nsec = rq->perout.period.nsec;
448
+
period_ns = timespec64_to_ns(&period);
449
+
450
+
integral_period = netc_timer_get_integral_period(priv);
451
+
max_period = (u64)NETC_TMR_DEFAULT_FIPER + integral_period;
452
+
gclk_period = netc_timer_get_gclk_period(priv);
453
+
min_period = gclk_period * 4 + integral_period;
454
+
if (period_ns > max_period || period_ns < min_period) {
455
+
dev_err(dev, "The period range is %llu ~ %llu\n",
456
+
min_period, max_period);
457
+
err = -EINVAL;
458
+
goto unlock_spinlock;
459
+
}
460
+
461
+
if (pp->enabled) {
462
+
alarm_id = pp->alarm_id;
463
+
} else {
464
+
alarm_id = netc_timer_get_alarm_id(priv);
465
+
if (alarm_id == priv->fs_alarm_num) {
466
+
dev_err(dev, "No available ALARMs\n");
467
+
err = -EBUSY;
468
+
goto unlock_spinlock;
469
+
}
470
+
471
+
pp->type = NETC_PP_PEROUT;
472
+
pp->enabled = true;
473
+
pp->alarm_id = alarm_id;
474
+
}
475
+
476
+
stime.tv_sec = rq->perout.start.sec;
477
+
stime.tv_nsec = rq->perout.start.nsec;
478
+
pp->stime = timespec64_to_ns(&stime);
479
+
pp->period = period_ns;
480
+
481
+
netc_timer_enable_periodic_pulse(priv, channel);
482
+
} else {
483
+
netc_timer_disable_periodic_pulse(priv, channel);
484
+
priv->fs_alarm_bitmap &= ~BIT(pp->alarm_id);
485
+
memset(pp, 0, sizeof(*pp));
486
+
}
487
+
488
+
unlock_spinlock:
489
+
spin_unlock_irqrestore(&priv->lock, flags);
490
+
491
+
return err;
492
+
}
493
+
494
+
static void netc_timer_handle_etts_event(struct netc_timer *priv, int index,
495
+
bool update_event)
496
+
{
497
+
struct ptp_clock_event event;
498
+
u32 etts_l = 0, etts_h = 0;
499
+
500
+
while (netc_timer_rd(priv, NETC_TMR_STAT) & TMR_STAT_ETS_VLD(index)) {
501
+
etts_l = netc_timer_rd(priv, NETC_TMR_ETTS_L(index));
502
+
etts_h = netc_timer_rd(priv, NETC_TMR_ETTS_H(index));
503
+
}
504
+
505
+
/* Invalid time stamp */
506
+
if (!etts_l && !etts_h)
507
+
return;
508
+
509
+
if (update_event) {
510
+
event.type = PTP_CLOCK_EXTTS;
511
+
event.index = index;
512
+
event.timestamp = (u64)etts_h << 32;
513
+
event.timestamp |= etts_l;
514
+
ptp_clock_event(priv->clock, &event);
515
+
}
516
+
}
517
+
518
+
static int netc_timer_enable_extts(struct netc_timer *priv,
519
+
struct ptp_clock_request *rq, int on)
520
+
{
521
+
int index = rq->extts.index;
522
+
unsigned long flags;
523
+
u32 tmr_ctrl;
524
+
525
+
/* Reject requests to enable time stamping on both edges */
526
+
if ((rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
527
+
return -EOPNOTSUPP;
528
+
529
+
spin_lock_irqsave(&priv->lock, flags);
530
+
531
+
netc_timer_handle_etts_event(priv, rq->extts.index, false);
532
+
if (on) {
533
+
tmr_ctrl = netc_timer_rd(priv, NETC_TMR_CTRL);
534
+
if (rq->extts.flags & PTP_FALLING_EDGE)
535
+
tmr_ctrl |= TMR_ETEP(index);
536
+
else
537
+
tmr_ctrl &= ~TMR_ETEP(index);
538
+
539
+
netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl);
540
+
priv->tmr_emask |= TMR_TEVENT_ETS(index);
541
+
} else {
542
+
priv->tmr_emask &= ~TMR_TEVENT_ETS(index);
543
+
}
544
+
545
+
netc_timer_wr(priv, NETC_TMR_TEMASK, priv->tmr_emask);
546
+
547
+
spin_unlock_irqrestore(&priv->lock, flags);
548
+
549
+
return 0;
550
+
}
551
+
552
+
static void netc_timer_disable_fiper(struct netc_timer *priv)
553
+
{
554
+
u32 fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
555
+
int i;
556
+
557
+
for (i = 0; i < NETC_TMR_FIPER_NUM; i++) {
558
+
if (!priv->pp[i].enabled)
559
+
continue;
560
+
561
+
fiper_ctrl |= FIPER_CTRL_DIS(i);
562
+
netc_timer_wr(priv, NETC_TMR_FIPER(i), NETC_TMR_DEFAULT_FIPER);
563
+
}
564
+
565
+
netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
566
+
}
567
+
568
+
static void netc_timer_enable_fiper(struct netc_timer *priv)
569
+
{
570
+
u32 integral_period = netc_timer_get_integral_period(priv);
571
+
u32 fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
572
+
int i;
573
+
574
+
for (i = 0; i < NETC_TMR_FIPER_NUM; i++) {
575
+
struct netc_pp *pp = &priv->pp[i];
576
+
u32 fiper;
577
+
578
+
if (!pp->enabled)
579
+
continue;
580
+
581
+
fiper_ctrl &= ~FIPER_CTRL_DIS(i);
582
+
583
+
if (pp->type == NETC_PP_PPS)
584
+
netc_timer_set_pps_alarm(priv, i, integral_period);
585
+
else if (pp->type == NETC_PP_PEROUT)
586
+
netc_timer_set_perout_alarm(priv, i, integral_period);
587
+
588
+
fiper = pp->period - integral_period;
589
+
netc_timer_wr(priv, NETC_TMR_FIPER(i), fiper);
590
+
}
591
+
592
+
netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
593
+
}
594
+
595
+
static int netc_timer_enable(struct ptp_clock_info *ptp,
596
+
struct ptp_clock_request *rq, int on)
597
+
{
598
+
struct netc_timer *priv = ptp_to_netc_timer(ptp);
599
+
600
+
switch (rq->type) {
601
+
case PTP_CLK_REQ_PPS:
602
+
return netc_timer_enable_pps(priv, rq, on);
603
+
case PTP_CLK_REQ_PEROUT:
604
+
return net_timer_enable_perout(priv, rq, on);
605
+
case PTP_CLK_REQ_EXTTS:
606
+
return netc_timer_enable_extts(priv, rq, on);
607
+
default:
608
+
return -EOPNOTSUPP;
609
+
}
610
+
}
611
+
612
+
static void netc_timer_adjust_period(struct netc_timer *priv, u64 period)
613
+
{
614
+
u32 fractional_period = lower_32_bits(period);
615
+
u32 integral_period = upper_32_bits(period);
616
+
u32 tmr_ctrl, old_tmr_ctrl;
617
+
unsigned long flags;
618
+
619
+
spin_lock_irqsave(&priv->lock, flags);
620
+
621
+
old_tmr_ctrl = netc_timer_rd(priv, NETC_TMR_CTRL);
622
+
tmr_ctrl = u32_replace_bits(old_tmr_ctrl, integral_period,
623
+
TMR_CTRL_TCLK_PERIOD);
624
+
if (tmr_ctrl != old_tmr_ctrl) {
625
+
netc_timer_disable_fiper(priv);
626
+
netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl);
627
+
netc_timer_enable_fiper(priv);
628
+
}
629
+
630
+
netc_timer_wr(priv, NETC_TMR_ADD, fractional_period);
631
+
632
+
spin_unlock_irqrestore(&priv->lock, flags);
633
+
}
634
+
635
+
static int netc_timer_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
636
+
{
637
+
struct netc_timer *priv = ptp_to_netc_timer(ptp);
638
+
u64 new_period;
639
+
640
+
new_period = adjust_by_scaled_ppm(priv->period, scaled_ppm);
641
+
netc_timer_adjust_period(priv, new_period);
642
+
643
+
return 0;
644
+
}
645
+
646
+
static int netc_timer_adjtime(struct ptp_clock_info *ptp, s64 delta)
647
+
{
648
+
struct netc_timer *priv = ptp_to_netc_timer(ptp);
649
+
unsigned long flags;
650
+
s64 tmr_off;
651
+
652
+
spin_lock_irqsave(&priv->lock, flags);
653
+
654
+
netc_timer_disable_fiper(priv);
655
+
656
+
/* Adjusting TMROFF instead of TMR_CNT is that the timer
657
+
* counter keeps increasing during reading and writing
658
+
* TMR_CNT, which will cause latency.
659
+
*/
660
+
tmr_off = netc_timer_offset_read(priv);
661
+
tmr_off += delta;
662
+
netc_timer_offset_write(priv, tmr_off);
663
+
664
+
netc_timer_enable_fiper(priv);
665
+
666
+
spin_unlock_irqrestore(&priv->lock, flags);
667
+
668
+
return 0;
669
+
}
670
+
671
+
static int netc_timer_gettimex64(struct ptp_clock_info *ptp,
672
+
struct timespec64 *ts,
673
+
struct ptp_system_timestamp *sts)
674
+
{
675
+
struct netc_timer *priv = ptp_to_netc_timer(ptp);
676
+
unsigned long flags;
677
+
u64 ns;
678
+
679
+
spin_lock_irqsave(&priv->lock, flags);
680
+
681
+
ptp_read_system_prets(sts);
682
+
ns = netc_timer_cur_time_read(priv);
683
+
ptp_read_system_postts(sts);
684
+
685
+
spin_unlock_irqrestore(&priv->lock, flags);
686
+
687
+
*ts = ns_to_timespec64(ns);
688
+
689
+
return 0;
690
+
}
691
+
692
+
static int netc_timer_settime64(struct ptp_clock_info *ptp,
693
+
const struct timespec64 *ts)
694
+
{
695
+
struct netc_timer *priv = ptp_to_netc_timer(ptp);
696
+
u64 ns = timespec64_to_ns(ts);
697
+
unsigned long flags;
698
+
699
+
spin_lock_irqsave(&priv->lock, flags);
700
+
701
+
netc_timer_disable_fiper(priv);
702
+
netc_timer_offset_write(priv, 0);
703
+
netc_timer_cnt_write(priv, ns);
704
+
netc_timer_enable_fiper(priv);
705
+
706
+
spin_unlock_irqrestore(&priv->lock, flags);
707
+
708
+
return 0;
709
+
}
710
+
711
+
static const struct ptp_clock_info netc_timer_ptp_caps = {
712
+
.owner = THIS_MODULE,
713
+
.name = "NETC Timer PTP clock",
714
+
.max_adj = 500000000,
715
+
.n_pins = 0,
716
+
.n_alarm = 2,
717
+
.pps = 1,
718
+
.n_per_out = 3,
719
+
.n_ext_ts = 2,
720
+
.supported_extts_flags = PTP_RISING_EDGE | PTP_FALLING_EDGE |
721
+
PTP_STRICT_FLAGS,
722
+
.adjfine = netc_timer_adjfine,
723
+
.adjtime = netc_timer_adjtime,
724
+
.gettimex64 = netc_timer_gettimex64,
725
+
.settime64 = netc_timer_settime64,
726
+
.enable = netc_timer_enable,
727
+
};
728
+
729
+
static void netc_timer_init(struct netc_timer *priv)
730
+
{
731
+
u32 fractional_period = lower_32_bits(priv->period);
732
+
u32 integral_period = upper_32_bits(priv->period);
733
+
u32 tmr_ctrl, fiper_ctrl;
734
+
struct timespec64 now;
735
+
u64 ns;
736
+
int i;
737
+
738
+
/* Software must enable timer first and the clock selected must be
739
+
* active, otherwise, the registers which are in the timer clock
740
+
* domain are not accessible.
741
+
*/
742
+
tmr_ctrl = FIELD_PREP(TMR_CTRL_CK_SEL, priv->clk_select) |
743
+
TMR_CTRL_TE | TMR_CTRL_FS;
744
+
netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl);
745
+
netc_timer_wr(priv, NETC_TMR_PRSC, priv->oclk_prsc);
746
+
747
+
/* Disable FIPER by default */
748
+
fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL);
749
+
for (i = 0; i < NETC_TMR_FIPER_NUM; i++) {
750
+
fiper_ctrl |= FIPER_CTRL_DIS(i);
751
+
fiper_ctrl &= ~FIPER_CTRL_PG(i);
752
+
}
753
+
netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
754
+
netc_timer_wr(priv, NETC_TMR_ECTRL, NETC_TMR_DEFAULT_ETTF_THR);
755
+
756
+
ktime_get_real_ts64(&now);
757
+
ns = timespec64_to_ns(&now);
758
+
netc_timer_cnt_write(priv, ns);
759
+
760
+
/* Allow atomic writes to TCLK_PERIOD and TMR_ADD, An update to
761
+
* TCLK_PERIOD does not take effect until TMR_ADD is written.
762
+
*/
763
+
tmr_ctrl |= FIELD_PREP(TMR_CTRL_TCLK_PERIOD, integral_period) |
764
+
TMR_COMP_MODE;
765
+
netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl);
766
+
netc_timer_wr(priv, NETC_TMR_ADD, fractional_period);
767
+
}
768
+
769
+
static int netc_timer_pci_probe(struct pci_dev *pdev)
770
+
{
771
+
struct device *dev = &pdev->dev;
772
+
struct netc_timer *priv;
773
+
int err;
774
+
775
+
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
776
+
if (!priv)
777
+
return -ENOMEM;
778
+
779
+
pcie_flr(pdev);
780
+
err = pci_enable_device_mem(pdev);
781
+
if (err)
782
+
return dev_err_probe(dev, err, "Failed to enable device\n");
783
+
784
+
dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
785
+
err = pci_request_mem_regions(pdev, KBUILD_MODNAME);
786
+
if (err) {
787
+
dev_err(dev, "pci_request_regions() failed, err:%pe\n",
788
+
ERR_PTR(err));
789
+
goto disable_dev;
790
+
}
791
+
792
+
pci_set_master(pdev);
793
+
794
+
priv->pdev = pdev;
795
+
priv->base = pci_ioremap_bar(pdev, NETC_TMR_REGS_BAR);
796
+
if (!priv->base) {
797
+
err = -ENOMEM;
798
+
goto release_mem_regions;
799
+
}
800
+
801
+
pci_set_drvdata(pdev, priv);
802
+
803
+
return 0;
804
+
805
+
release_mem_regions:
806
+
pci_release_mem_regions(pdev);
807
+
disable_dev:
808
+
pci_disable_device(pdev);
809
+
810
+
return err;
811
+
}
812
+
813
+
static void netc_timer_pci_remove(struct pci_dev *pdev)
814
+
{
815
+
struct netc_timer *priv = pci_get_drvdata(pdev);
816
+
817
+
iounmap(priv->base);
818
+
pci_release_mem_regions(pdev);
819
+
pci_disable_device(pdev);
820
+
}
821
+
822
+
static int netc_timer_get_reference_clk_source(struct netc_timer *priv)
823
+
{
824
+
struct device *dev = &priv->pdev->dev;
825
+
struct clk *clk;
826
+
int i;
827
+
828
+
/* Select NETC system clock as the reference clock by default */
829
+
priv->clk_select = NETC_TMR_SYSTEM_CLK;
830
+
priv->clk_freq = NETC_TMR_SYSCLK_333M;
831
+
832
+
/* Update the clock source of the reference clock if the clock
833
+
* is specified in DT node.
834
+
*/
835
+
for (i = 0; i < ARRAY_SIZE(timer_clk_src); i++) {
836
+
clk = devm_clk_get_optional_enabled(dev, timer_clk_src[i]);
837
+
if (IS_ERR(clk))
838
+
return dev_err_probe(dev, PTR_ERR(clk),
839
+
"Failed to enable clock\n");
840
+
841
+
if (clk) {
842
+
priv->clk_freq = clk_get_rate(clk);
843
+
priv->clk_select = i ? NETC_TMR_EXT_OSC :
844
+
NETC_TMR_CCM_TIMER1;
845
+
break;
846
+
}
847
+
}
848
+
849
+
/* The period is a 64-bit number, the high 32-bit is the integer
850
+
* part of the period, the low 32-bit is the fractional part of
851
+
* the period. In order to get the desired 32-bit fixed-point
852
+
* format, multiply the numerator of the fraction by 2^32.
853
+
*/
854
+
priv->period = div_u64((u64)NSEC_PER_SEC << 32, priv->clk_freq);
855
+
856
+
return 0;
857
+
}
858
+
859
+
static int netc_timer_parse_dt(struct netc_timer *priv)
860
+
{
861
+
return netc_timer_get_reference_clk_source(priv);
862
+
}
863
+
864
+
static irqreturn_t netc_timer_isr(int irq, void *data)
865
+
{
866
+
struct netc_timer *priv = data;
867
+
struct ptp_clock_event event;
868
+
u32 tmr_event;
869
+
870
+
spin_lock(&priv->lock);
871
+
872
+
tmr_event = netc_timer_rd(priv, NETC_TMR_TEVENT);
873
+
tmr_event &= priv->tmr_emask;
874
+
/* Clear interrupts status */
875
+
netc_timer_wr(priv, NETC_TMR_TEVENT, tmr_event);
876
+
877
+
if (tmr_event & TMR_TEVENT_ALMEN(0))
878
+
netc_timer_alarm_write(priv, NETC_TMR_DEFAULT_ALARM, 0);
879
+
880
+
if (tmr_event & TMR_TEVENT_ALMEN(1))
881
+
netc_timer_alarm_write(priv, NETC_TMR_DEFAULT_ALARM, 1);
882
+
883
+
if (tmr_event & TMR_TEVENT_PPEN_ALL) {
884
+
event.type = PTP_CLOCK_PPS;
885
+
ptp_clock_event(priv->clock, &event);
886
+
}
887
+
888
+
if (tmr_event & TMR_TEVENT_ETS(0))
889
+
netc_timer_handle_etts_event(priv, 0, true);
890
+
891
+
if (tmr_event & TMR_TEVENT_ETS(1))
892
+
netc_timer_handle_etts_event(priv, 1, true);
893
+
894
+
spin_unlock(&priv->lock);
895
+
896
+
return IRQ_HANDLED;
897
+
}
898
+
899
+
static int netc_timer_init_msix_irq(struct netc_timer *priv)
900
+
{
901
+
struct pci_dev *pdev = priv->pdev;
902
+
int err, n;
903
+
904
+
n = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
905
+
if (n != 1) {
906
+
err = (n < 0) ? n : -EPERM;
907
+
dev_err(&pdev->dev, "pci_alloc_irq_vectors() failed\n");
908
+
return err;
909
+
}
910
+
911
+
priv->irq = pci_irq_vector(pdev, 0);
912
+
err = request_irq(priv->irq, netc_timer_isr, 0, priv->irq_name, priv);
913
+
if (err) {
914
+
dev_err(&pdev->dev, "request_irq() failed\n");
915
+
pci_free_irq_vectors(pdev);
916
+
917
+
return err;
918
+
}
919
+
920
+
return 0;
921
+
}
922
+
923
+
static void netc_timer_free_msix_irq(struct netc_timer *priv)
924
+
{
925
+
struct pci_dev *pdev = priv->pdev;
926
+
927
+
disable_irq(priv->irq);
928
+
free_irq(priv->irq, priv);
929
+
pci_free_irq_vectors(pdev);
930
+
}
931
+
932
+
static int netc_timer_get_global_ip_rev(struct netc_timer *priv)
933
+
{
934
+
u32 val;
935
+
936
+
val = netc_timer_rd(priv, NETC_GLOBAL_OFFSET + NETC_GLOBAL_IPBRR0);
937
+
938
+
return val & IPBRR0_IP_REV;
939
+
}
940
+
941
+
static int netc_timer_probe(struct pci_dev *pdev,
942
+
const struct pci_device_id *id)
943
+
{
944
+
struct device *dev = &pdev->dev;
945
+
struct netc_timer *priv;
946
+
int err;
947
+
948
+
err = netc_timer_pci_probe(pdev);
949
+
if (err)
950
+
return err;
951
+
952
+
priv = pci_get_drvdata(pdev);
953
+
priv->revision = netc_timer_get_global_ip_rev(priv);
954
+
if (priv->revision == NETC_REV_4_1)
955
+
priv->fs_alarm_num = 1;
956
+
else
957
+
priv->fs_alarm_num = NETC_TMR_ALARM_NUM;
958
+
959
+
err = netc_timer_parse_dt(priv);
960
+
if (err)
961
+
goto timer_pci_remove;
962
+
963
+
priv->caps = netc_timer_ptp_caps;
964
+
priv->oclk_prsc = NETC_TMR_DEFAULT_PRSC;
965
+
priv->pps_channel = NETC_TMR_INVALID_CHANNEL;
966
+
spin_lock_init(&priv->lock);
967
+
snprintf(priv->irq_name, sizeof(priv->irq_name), "ptp-netc %s",
968
+
pci_name(pdev));
969
+
970
+
err = netc_timer_init_msix_irq(priv);
971
+
if (err)
972
+
goto timer_pci_remove;
973
+
974
+
netc_timer_init(priv);
975
+
priv->clock = ptp_clock_register(&priv->caps, dev);
976
+
if (IS_ERR(priv->clock)) {
977
+
err = PTR_ERR(priv->clock);
978
+
goto free_msix_irq;
979
+
}
980
+
981
+
return 0;
982
+
983
+
free_msix_irq:
984
+
netc_timer_free_msix_irq(priv);
985
+
timer_pci_remove:
986
+
netc_timer_pci_remove(pdev);
987
+
988
+
return err;
989
+
}
990
+
991
+
static void netc_timer_remove(struct pci_dev *pdev)
992
+
{
993
+
struct netc_timer *priv = pci_get_drvdata(pdev);
994
+
995
+
netc_timer_wr(priv, NETC_TMR_TEMASK, 0);
996
+
netc_timer_wr(priv, NETC_TMR_CTRL, 0);
997
+
ptp_clock_unregister(priv->clock);
998
+
netc_timer_free_msix_irq(priv);
999
+
netc_timer_pci_remove(pdev);
1000
+
}
1001
+
1002
+
static const struct pci_device_id netc_timer_id_table[] = {
1003
+
{ PCI_DEVICE(NETC_TMR_PCI_VENDOR_NXP, 0xee02) },
1004
+
{ }
1005
+
};
1006
+
MODULE_DEVICE_TABLE(pci, netc_timer_id_table);
1007
+
1008
+
static struct pci_driver netc_timer_driver = {
1009
+
.name = KBUILD_MODNAME,
1010
+
.id_table = netc_timer_id_table,
1011
+
.probe = netc_timer_probe,
1012
+
.remove = netc_timer_remove,
1013
+
};
1014
+
module_pci_driver(netc_timer_driver);
1015
+
1016
+
MODULE_DESCRIPTION("NXP NETC Timer PTP Driver");
1017
+
MODULE_LICENSE("Dual BSD/GPL");
+22
include/linux/ptp_clock_kernel.h
+22
include/linux/ptp_clock_kernel.h
···
361
361
extern int ptp_clock_index(struct ptp_clock *ptp);
362
362
363
363
/**
364
+
* ptp_clock_index_by_of_node() - obtain the device index of
365
+
* a PTP clock based on the PTP device of_node
366
+
*
367
+
* @np: The device of_node pointer of the PTP device.
368
+
* Return: The PHC index on success or -1 on failure.
369
+
*/
370
+
int ptp_clock_index_by_of_node(struct device_node *np);
371
+
372
+
/**
373
+
* ptp_clock_index_by_dev() - obtain the device index of
374
+
* a PTP clock based on the PTP device.
375
+
*
376
+
* @parent: The parent device (PTP device) pointer of the PTP clock.
377
+
* Return: The PHC index on success or -1 on failure.
378
+
*/
379
+
int ptp_clock_index_by_dev(struct device *parent);
380
+
381
+
/**
364
382
* ptp_find_pin() - obtain the pin index of a given auxiliary function
365
383
*
366
384
* The caller must hold ptp_clock::pincfg_mux. Drivers do not have
···
442
424
struct ptp_clock_event *event)
443
425
{ }
444
426
static inline int ptp_clock_index(struct ptp_clock *ptp)
427
+
{ return -1; }
428
+
static inline int ptp_clock_index_by_of_node(struct device_node *np)
429
+
{ return -1; }
430
+
static inline int ptp_clock_index_by_dev(struct device *parent)
445
431
{ return -1; }
446
432
static inline int ptp_find_pin(struct ptp_clock *ptp,
447
433
enum ptp_pin_function func, unsigned int chan)