Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'net-stmmac-start-to-shrink-memory-usage'
Russell King says:
====================
net: stmmac: start to shrink memory usage
Start shrinking stmmac's memory usage by avoiding using "int" for
members that are only used for 0/1 (boolean) values, or values that
can't be larger than 255.
In addition, as struct stmmac_dma_cfg is approximately a cache line,
shrinks below a cache line as a result of this patch set, and is
required, there is no point separately allocating this from
struct plat_stmmacenet_data. Embed it into the end of this struct
and set the existing pointer to avoid large wide-spread changes.
Lastly, add documentation for struct stmmac_dma_cfg, and document
the stmmac clocks as best we can given the driver history.
====================
Link: https://patch.msgid.link/aa6VEsmBK-S9eNYU@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+240
-201
+2
-2
drivers/net/ethernet/stmicro/stmmac/common.h
+2
-2
drivers/net/ethernet/stmicro/stmmac/common.h
···
446
446
unsigned int number_rx_channel;
447
447
unsigned int number_tx_channel;
448
448
/* TX and RX number of queues */
449
-
unsigned int number_rx_queues;
450
-
unsigned int number_tx_queues;
449
+
u8 number_rx_queues;
450
+
u8 number_tx_queues;
451
451
/* PPS output */
452
452
unsigned int pps_out_num;
453
453
/* Number of Traffic Classes */
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
+1
-6
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+1
-6
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
···
566
566
/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
567
567
plat->clk_csr = STMMAC_CSR_20_35M;
568
568
plat->core_type = DWMAC_CORE_GMAC;
569
-
plat->force_sf_dma_mode = 1;
569
+
plat->force_sf_dma_mode = true;
570
570
571
571
plat->mdio_bus_data->needs_reset = true;
572
572
}
···
1249
1249
sizeof(*plat->mdio_bus_data),
1250
1250
GFP_KERNEL);
1251
1251
if (!plat->mdio_bus_data)
1252
-
return -ENOMEM;
1253
-
1254
-
plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
1255
-
GFP_KERNEL);
1256
-
if (!plat->dma_cfg)
1257
1252
return -ENOMEM;
1258
1253
1259
1254
plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
+1
-5
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+1
-5
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
···
94
94
/* clk_csr_i = 100-150MHz & MDC = clk_csr_i/62 */
95
95
plat->clk_csr = STMMAC_CSR_100_150M;
96
96
plat->core_type = DWMAC_CORE_GMAC;
97
-
plat->force_sf_dma_mode = 1;
97
+
plat->force_sf_dma_mode = true;
98
98
99
99
/* Increase the default value for multicast hash bins */
100
100
plat->multicast_filter_bins = 256;
···
511
511
sizeof(*plat->mdio_bus_data),
512
512
GFP_KERNEL);
513
513
if (!plat->mdio_bus_data)
514
-
return -ENOMEM;
515
-
516
-
plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL);
517
-
if (!plat->dma_cfg)
518
514
return -ENOMEM;
519
515
520
516
ld = devm_kzalloc(&pdev->dev, sizeof(*ld), GFP_KERNEL);
+4
-4
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
+4
-4
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
···
93
93
const char * const *clk_list;
94
94
int num_clks;
95
95
96
-
u32 dma_bit_mask;
97
96
u32 rx_delay_max;
98
97
u32 tx_delay_max;
98
+
u8 dma_bit_mask;
99
99
};
100
100
101
101
/* list of clocks required for mac */
···
268
268
.dwmac_set_delay = mt2712_set_delay,
269
269
.clk_list = mt2712_dwmac_clk_l,
270
270
.num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l),
271
-
.dma_bit_mask = 33,
272
271
.rx_delay_max = 17600,
273
272
.tx_delay_max = 17600,
273
+
.dma_bit_mask = 33,
274
274
};
275
275
276
276
static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,
···
418
418
.dwmac_set_delay = mt8195_set_delay,
419
419
.clk_list = mt8195_dwmac_clk_l,
420
420
.num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l),
421
-
.dma_bit_mask = 35,
422
421
.rx_delay_max = 9280,
423
422
.tx_delay_max = 9280,
423
+
.dma_bit_mask = 35,
424
424
};
425
425
426
426
static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
···
564
564
plat->flags &= ~STMMAC_FLAG_USE_PHY_WOL;
565
565
else
566
566
plat->flags |= STMMAC_FLAG_USE_PHY_WOL;
567
-
plat->riwt_off = 1;
567
+
plat->riwt_off = true;
568
568
plat->maxmtu = ETH_DATA_LEN;
569
569
plat->host_dma_width = priv_plat->variant->dma_bit_mask;
570
570
plat->bsp_priv = priv_plat;
-4
drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c
-4
drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c
···
218
218
if (!plat->mdio_bus_data)
219
219
return NULL;
220
220
221
-
plat->dma_cfg = devm_kzalloc(dev, sizeof(*plat->dma_cfg), GFP_KERNEL);
222
-
if (!plat->dma_cfg)
223
-
return NULL;
224
-
225
221
plat->axi = devm_kzalloc(dev, sizeof(*plat->axi), GFP_KERNEL);
226
222
if (!plat->axi)
227
223
return NULL;
+2
-2
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+2
-2
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
···
91
91
unsigned int num_rgmii_por;
92
92
bool rgmii_config_loopback_en;
93
93
bool has_emac_ge_3;
94
+
u8 dma_addr_width;
94
95
const char *link_clk_name;
95
-
u32 dma_addr_width;
96
96
struct dwmac4_addrs dwmac4_addrs;
97
97
bool needs_sgmii_loopback;
98
98
};
···
817
817
plat_dat->core_type = DWMAC_CORE_GMAC4;
818
818
if (ethqos->has_emac_ge_3)
819
819
plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
820
-
plat_dat->pmt = 1;
820
+
plat_dat->pmt = true;
821
821
if (of_property_read_bool(np, "snps,tso"))
822
822
plat_dat->flags |= STMMAC_FLAG_TSO_EN;
823
823
if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+2
-2
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+2
-2
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
···
718
718
719
719
static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
720
720
unsigned int duplex, unsigned int fc,
721
-
unsigned int pause_time, u32 tx_cnt)
721
+
unsigned int pause_time, u8 tx_cnt)
722
722
{
723
723
void __iomem *ioaddr = hw->pcsr;
724
724
u32 v;
···
1179
1179
* hardware features were copied from Allwinner drivers.
1180
1180
*/
1181
1181
plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
1182
-
plat_dat->tx_coe = 1;
1182
+
plat_dat->tx_coe = true;
1183
1183
plat_dat->flags |= STMMAC_FLAG_HAS_SUN8I;
1184
1184
plat_dat->bsp_priv = gmac;
1185
1185
plat_dat->init = sun8i_dwmac_init;
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
···
135
135
136
136
/* platform data specifying hardware features and callbacks.
137
137
* hardware features were copied from Allwinner drivers. */
138
-
plat_dat->tx_coe = 1;
138
+
plat_dat->tx_coe = true;
139
139
plat_dat->core_type = DWMAC_CORE_GMAC;
140
140
plat_dat->bsp_priv = gmac;
141
141
plat_dat->init = sun7i_gmac_init;
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
+2
-2
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+2
-2
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
···
547
547
548
548
static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
549
549
unsigned int fc, unsigned int pause_time,
550
-
u32 tx_cnt)
550
+
u8 tx_cnt)
551
551
{
552
552
void __iomem *ioaddr = hw->pcsr;
553
553
unsigned int flow = 0;
554
-
u32 queue = 0;
554
+
u8 queue;
555
555
556
556
pr_debug("GMAC Flow-Control:\n");
557
557
if (fc & FLOW_RX) {
+2
-2
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+2
-2
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
···
355
355
356
356
static void dwxgmac2_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
357
357
unsigned int fc, unsigned int pause_time,
358
-
u32 tx_cnt)
358
+
u8 tx_cnt)
359
359
{
360
360
void __iomem *ioaddr = hw->pcsr;
361
-
u32 i;
361
+
u8 i;
362
362
363
363
if (fc & FLOW_RX)
364
364
writel(XGMAC_RFE, ioaddr + XGMAC_RX_FLOW_CTRL);
+1
-1
drivers/net/ethernet/stmicro/stmmac/hwif.h
+1
-1
drivers/net/ethernet/stmicro/stmmac/hwif.h
···
352
352
void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
353
353
/* Flow control setting */
354
354
void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
355
-
unsigned int fc, unsigned int pause_time, u32 tx_cnt);
355
+
unsigned int fc, unsigned int pause_time, u8 tx_cnt);
356
356
/* Set power management mode (e.g. magic frame) */
357
357
void (*pmt)(struct mac_device_info *hw, unsigned long mode);
358
358
/* Set/Get Unicast MAC addresses */
+1
-1
drivers/net/ethernet/stmicro/stmmac/stmmac.h
+1
-1
drivers/net/ethernet/stmicro/stmmac/stmmac.h
···
407
407
int stmmac_dvr_probe(struct device *device,
408
408
struct plat_stmmacenet_data *plat_dat,
409
409
struct stmmac_resources *res);
410
-
int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
410
+
int stmmac_reinit_queues(struct net_device *dev, u8 rx_cnt, u8 tx_cnt);
411
411
int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
412
412
int stmmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
413
413
phy_interface_t interface, int speed);
+115
-112
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+115
-112
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
···
264
264
265
265
static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
266
266
{
267
-
u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
268
-
u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
269
-
u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
270
-
u32 queue;
267
+
u8 rx_queues_cnt = priv->plat->rx_queues_to_use;
268
+
u8 tx_queues_cnt = priv->plat->tx_queues_to_use;
269
+
u8 maxq = max(rx_queues_cnt, tx_queues_cnt);
270
+
u8 queue;
271
271
272
272
for (queue = 0; queue < maxq; queue++) {
273
273
struct stmmac_channel *ch = &priv->channel[queue];
···
291
291
*/
292
292
static void stmmac_disable_all_queues(struct stmmac_priv *priv)
293
293
{
294
-
u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
294
+
u8 rx_queues_cnt = priv->plat->rx_queues_to_use;
295
295
struct stmmac_rx_queue *rx_q;
296
-
u32 queue;
296
+
u8 queue;
297
297
298
298
/* synchronize_rcu() needed for pending XDP buffers to drain */
299
299
for (queue = 0; queue < rx_queues_cnt; queue++) {
···
313
313
*/
314
314
static void stmmac_enable_all_queues(struct stmmac_priv *priv)
315
315
{
316
-
u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
317
-
u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
318
-
u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
319
-
u32 queue;
316
+
u8 rx_queues_cnt = priv->plat->rx_queues_to_use;
317
+
u8 tx_queues_cnt = priv->plat->tx_queues_to_use;
318
+
u8 maxq = max(rx_queues_cnt, tx_queues_cnt);
319
+
u8 queue;
320
320
321
321
for (queue = 0; queue < maxq; queue++) {
322
322
struct stmmac_channel *ch = &priv->channel[queue];
···
377
377
378
378
static bool stmmac_eee_tx_busy(struct stmmac_priv *priv)
379
379
{
380
-
u32 tx_cnt = priv->plat->tx_queues_to_use;
381
-
u32 queue;
380
+
u8 tx_cnt = priv->plat->tx_queues_to_use;
381
+
u8 queue;
382
382
383
383
/* check if all TX queues have the work finished */
384
384
for (queue = 0; queue < tx_cnt; queue++) {
···
909
909
static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex,
910
910
unsigned int flow_ctrl)
911
911
{
912
-
u32 tx_cnt = priv->plat->tx_queues_to_use;
912
+
u8 tx_cnt = priv->plat->tx_queues_to_use;
913
913
914
914
stmmac_flow_ctrl(priv, priv->hw, duplex, flow_ctrl, priv->pause_time,
915
915
tx_cnt);
···
1410
1410
static void stmmac_display_rx_rings(struct stmmac_priv *priv,
1411
1411
struct stmmac_dma_conf *dma_conf)
1412
1412
{
1413
-
u32 rx_cnt = priv->plat->rx_queues_to_use;
1413
+
u8 rx_cnt = priv->plat->rx_queues_to_use;
1414
1414
unsigned int desc_size;
1415
1415
void *head_rx;
1416
-
u32 queue;
1416
+
u8 queue;
1417
1417
1418
1418
/* Display RX rings */
1419
1419
for (queue = 0; queue < rx_cnt; queue++) {
···
1438
1438
static void stmmac_display_tx_rings(struct stmmac_priv *priv,
1439
1439
struct stmmac_dma_conf *dma_conf)
1440
1440
{
1441
-
u32 tx_cnt = priv->plat->tx_queues_to_use;
1441
+
u8 tx_cnt = priv->plat->tx_queues_to_use;
1442
1442
unsigned int desc_size;
1443
1443
void *head_tx;
1444
-
u32 queue;
1444
+
u8 queue;
1445
1445
1446
1446
/* Display TX rings */
1447
1447
for (queue = 0; queue < tx_cnt; queue++) {
···
1571
1571
static void stmmac_clear_descriptors(struct stmmac_priv *priv,
1572
1572
struct stmmac_dma_conf *dma_conf)
1573
1573
{
1574
-
u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1575
-
u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1576
-
u32 queue;
1574
+
u8 rx_queue_cnt = priv->plat->rx_queues_to_use;
1575
+
u8 tx_queue_cnt = priv->plat->tx_queues_to_use;
1576
+
u8 queue;
1577
1577
1578
1578
/* Clear the RX descriptors */
1579
1579
for (queue = 0; queue < rx_queue_cnt; queue++)
···
1891
1891
gfp_t flags)
1892
1892
{
1893
1893
struct stmmac_priv *priv = netdev_priv(dev);
1894
-
u32 rx_count = priv->plat->rx_queues_to_use;
1894
+
u8 rx_count = priv->plat->rx_queues_to_use;
1895
1895
int queue;
1896
1896
int ret;
1897
1897
···
1985
1985
struct stmmac_dma_conf *dma_conf)
1986
1986
{
1987
1987
struct stmmac_priv *priv = netdev_priv(dev);
1988
-
u32 tx_queue_cnt;
1989
-
u32 queue;
1988
+
u8 tx_queue_cnt;
1989
+
u8 queue;
1990
1990
1991
1991
tx_queue_cnt = priv->plat->tx_queues_to_use;
1992
1992
···
2057
2057
*/
2058
2058
static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
2059
2059
{
2060
-
u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
2061
-
u32 queue;
2060
+
u8 tx_queue_cnt = priv->plat->tx_queues_to_use;
2061
+
u8 queue;
2062
2062
2063
2063
for (queue = 0; queue < tx_queue_cnt; queue++)
2064
2064
dma_free_tx_skbufs(priv, &priv->dma_conf, queue);
···
2106
2106
static void free_dma_rx_desc_resources(struct stmmac_priv *priv,
2107
2107
struct stmmac_dma_conf *dma_conf)
2108
2108
{
2109
-
u32 rx_count = priv->plat->rx_queues_to_use;
2110
-
u32 queue;
2109
+
u8 rx_count = priv->plat->rx_queues_to_use;
2110
+
u8 queue;
2111
2111
2112
2112
/* Free RX queue resources */
2113
2113
for (queue = 0; queue < rx_count; queue++)
···
2153
2153
static void free_dma_tx_desc_resources(struct stmmac_priv *priv,
2154
2154
struct stmmac_dma_conf *dma_conf)
2155
2155
{
2156
-
u32 tx_count = priv->plat->tx_queues_to_use;
2157
-
u32 queue;
2156
+
u8 tx_count = priv->plat->tx_queues_to_use;
2157
+
u8 queue;
2158
2158
2159
2159
/* Free TX queue resources */
2160
2160
for (queue = 0; queue < tx_count; queue++)
···
2255
2255
static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv,
2256
2256
struct stmmac_dma_conf *dma_conf)
2257
2257
{
2258
-
u32 rx_count = priv->plat->rx_queues_to_use;
2259
-
u32 queue;
2258
+
u8 rx_count = priv->plat->rx_queues_to_use;
2259
+
u8 queue;
2260
2260
int ret;
2261
2261
2262
2262
/* RX queues buffers and DMA */
···
2331
2331
static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv,
2332
2332
struct stmmac_dma_conf *dma_conf)
2333
2333
{
2334
-
u32 tx_count = priv->plat->tx_queues_to_use;
2335
-
u32 queue;
2334
+
u8 tx_count = priv->plat->tx_queues_to_use;
2335
+
u8 queue;
2336
2336
int ret;
2337
2337
2338
2338
/* TX queues buffers and DMA */
···
2396
2396
*/
2397
2397
static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
2398
2398
{
2399
-
u32 rx_queues_count = priv->plat->rx_queues_to_use;
2400
-
int queue;
2399
+
u8 rx_queues_count = priv->plat->rx_queues_to_use;
2400
+
u8 queue;
2401
2401
u8 mode;
2402
2402
2403
2403
for (queue = 0; queue < rx_queues_count; queue++) {
···
2460
2460
2461
2461
static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv)
2462
2462
{
2463
-
u32 rx_channels_count = priv->plat->rx_queues_to_use;
2464
-
u32 tx_channels_count = priv->plat->tx_queues_to_use;
2465
-
u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2466
-
u32 chan;
2463
+
u8 rx_channels_count = priv->plat->rx_queues_to_use;
2464
+
u8 tx_channels_count = priv->plat->tx_queues_to_use;
2465
+
u8 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2466
+
u8 chan;
2467
2467
2468
2468
for (chan = 0; chan < dma_csr_ch; chan++) {
2469
2469
struct stmmac_channel *ch = &priv->channel[chan];
···
2483
2483
*/
2484
2484
static void stmmac_start_all_dma(struct stmmac_priv *priv)
2485
2485
{
2486
-
u32 rx_channels_count = priv->plat->rx_queues_to_use;
2487
-
u32 tx_channels_count = priv->plat->tx_queues_to_use;
2488
-
u32 chan = 0;
2486
+
u8 rx_channels_count = priv->plat->rx_queues_to_use;
2487
+
u8 tx_channels_count = priv->plat->tx_queues_to_use;
2488
+
u8 chan;
2489
2489
2490
2490
for (chan = 0; chan < rx_channels_count; chan++)
2491
2491
stmmac_start_rx_dma(priv, chan);
···
2502
2502
*/
2503
2503
static void stmmac_stop_all_dma(struct stmmac_priv *priv)
2504
2504
{
2505
-
u32 rx_channels_count = priv->plat->rx_queues_to_use;
2506
-
u32 tx_channels_count = priv->plat->tx_queues_to_use;
2507
-
u32 chan = 0;
2505
+
u8 rx_channels_count = priv->plat->rx_queues_to_use;
2506
+
u8 tx_channels_count = priv->plat->tx_queues_to_use;
2507
+
u8 chan;
2508
2508
2509
2509
for (chan = 0; chan < rx_channels_count; chan++)
2510
2510
stmmac_stop_rx_dma(priv, chan);
···
2521
2521
*/
2522
2522
static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
2523
2523
{
2524
-
u32 rx_channels_count = priv->plat->rx_queues_to_use;
2525
-
u32 tx_channels_count = priv->plat->tx_queues_to_use;
2524
+
u8 rx_channels_count = priv->plat->rx_queues_to_use;
2525
+
u8 tx_channels_count = priv->plat->tx_queues_to_use;
2526
2526
int rxfifosz = priv->plat->rx_fifo_size;
2527
2527
int txfifosz = priv->plat->tx_fifo_size;
2528
2528
u32 txmode = 0;
2529
2529
u32 rxmode = 0;
2530
-
u32 chan = 0;
2531
2530
u8 qmode = 0;
2531
+
u8 chan;
2532
2532
2533
2533
if (rxfifosz == 0)
2534
2534
rxfifosz = priv->dma_cap.rx_fifo_size;
···
3012
3012
{
3013
3013
u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
3014
3014
u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
3015
-
u32 rx_channels_count = priv->plat->rx_queues_to_use;
3016
-
u32 tx_channels_count = priv->plat->tx_queues_to_use;
3015
+
u8 rx_channels_count = priv->plat->rx_queues_to_use;
3016
+
u8 tx_channels_count = priv->plat->tx_queues_to_use;
3017
3017
int rxfifosz = priv->plat->rx_fifo_size;
3018
3018
int txfifosz = priv->plat->tx_fifo_size;
3019
3019
···
3088
3088
*/
3089
3089
static void stmmac_dma_interrupt(struct stmmac_priv *priv)
3090
3090
{
3091
-
u32 tx_channel_count = priv->plat->tx_queues_to_use;
3092
-
u32 rx_channel_count = priv->plat->rx_queues_to_use;
3093
-
u32 channels_to_check = tx_channel_count > rx_channel_count ?
3094
-
tx_channel_count : rx_channel_count;
3095
-
u32 chan;
3091
+
u8 tx_channel_count = priv->plat->tx_queues_to_use;
3092
+
u8 rx_channel_count = priv->plat->rx_queues_to_use;
3093
+
u8 channels_to_check = tx_channel_count > rx_channel_count ?
3094
+
tx_channel_count : rx_channel_count;
3096
3095
int status[MAX_T(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
3096
+
u8 chan;
3097
3097
3098
3098
/* Make sure we never check beyond our status buffer. */
3099
3099
if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
···
3237
3237
*/
3238
3238
static int stmmac_init_dma_engine(struct stmmac_priv *priv)
3239
3239
{
3240
-
u32 rx_channels_count = priv->plat->rx_queues_to_use;
3241
-
u32 tx_channels_count = priv->plat->tx_queues_to_use;
3242
-
u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
3240
+
u8 rx_channels_count = priv->plat->rx_queues_to_use;
3241
+
u8 tx_channels_count = priv->plat->tx_queues_to_use;
3242
+
u8 dma_csr_ch = max(rx_channels_count, tx_channels_count);
3243
3243
struct stmmac_rx_queue *rx_q;
3244
3244
struct stmmac_tx_queue *tx_q;
3245
-
u32 chan = 0;
3246
3245
int ret = 0;
3246
+
u8 chan;
3247
3247
3248
3248
ret = stmmac_prereset_configure(priv);
3249
3249
if (ret)
···
3359
3359
*/
3360
3360
static void stmmac_init_coalesce(struct stmmac_priv *priv)
3361
3361
{
3362
-
u32 tx_channel_count = priv->plat->tx_queues_to_use;
3363
-
u32 rx_channel_count = priv->plat->rx_queues_to_use;
3364
-
u32 chan;
3362
+
u8 tx_channel_count = priv->plat->tx_queues_to_use;
3363
+
u8 rx_channel_count = priv->plat->rx_queues_to_use;
3364
+
u8 chan;
3365
3365
3366
3366
for (chan = 0; chan < tx_channel_count; chan++) {
3367
3367
struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
···
3378
3378
3379
3379
static void stmmac_set_rings_length(struct stmmac_priv *priv)
3380
3380
{
3381
-
u32 rx_channels_count = priv->plat->rx_queues_to_use;
3382
-
u32 tx_channels_count = priv->plat->tx_queues_to_use;
3383
-
u32 chan;
3381
+
u8 rx_channels_count = priv->plat->rx_queues_to_use;
3382
+
u8 tx_channels_count = priv->plat->tx_queues_to_use;
3383
+
u8 chan;
3384
3384
3385
3385
/* set TX ring length */
3386
3386
for (chan = 0; chan < tx_channels_count; chan++)
···
3400
3400
*/
3401
3401
static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
3402
3402
{
3403
-
u32 tx_queues_count = priv->plat->tx_queues_to_use;
3403
+
u8 tx_queues_count = priv->plat->tx_queues_to_use;
3404
3404
u32 weight;
3405
-
u32 queue;
3405
+
u8 queue;
3406
3406
3407
3407
for (queue = 0; queue < tx_queues_count; queue++) {
3408
3408
weight = priv->plat->tx_queues_cfg[queue].weight;
···
3417
3417
*/
3418
3418
static void stmmac_configure_cbs(struct stmmac_priv *priv)
3419
3419
{
3420
-
u32 tx_queues_count = priv->plat->tx_queues_to_use;
3420
+
u8 tx_queues_count = priv->plat->tx_queues_to_use;
3421
3421
u32 mode_to_use;
3422
-
u32 queue;
3422
+
u8 queue;
3423
3423
3424
3424
/* queue 0 is reserved for legacy traffic */
3425
3425
for (queue = 1; queue < tx_queues_count; queue++) {
···
3443
3443
*/
3444
3444
static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
3445
3445
{
3446
-
u32 rx_queues_count = priv->plat->rx_queues_to_use;
3447
-
u32 queue;
3446
+
u8 rx_queues_count = priv->plat->rx_queues_to_use;
3447
+
u8 queue;
3448
3448
u32 chan;
3449
3449
3450
3450
for (queue = 0; queue < rx_queues_count; queue++) {
···
3460
3460
*/
3461
3461
static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
3462
3462
{
3463
-
u32 rx_queues_count = priv->plat->rx_queues_to_use;
3464
-
u32 queue;
3463
+
u8 rx_queues_count = priv->plat->rx_queues_to_use;
3464
+
u8 queue;
3465
3465
u32 prio;
3466
3466
3467
3467
for (queue = 0; queue < rx_queues_count; queue++) {
···
3480
3480
*/
3481
3481
static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
3482
3482
{
3483
-
u32 tx_queues_count = priv->plat->tx_queues_to_use;
3484
-
u32 queue;
3483
+
u8 tx_queues_count = priv->plat->tx_queues_to_use;
3484
+
u8 queue;
3485
3485
u32 prio;
3486
3486
3487
3487
for (queue = 0; queue < tx_queues_count; queue++) {
···
3500
3500
*/
3501
3501
static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
3502
3502
{
3503
-
u32 rx_queues_count = priv->plat->rx_queues_to_use;
3504
-
u32 queue;
3503
+
u8 rx_queues_count = priv->plat->rx_queues_to_use;
3505
3504
u8 packet;
3505
+
u8 queue;
3506
3506
3507
3507
for (queue = 0; queue < rx_queues_count; queue++) {
3508
3508
/* no specific packet type routing specified for the queue */
···
3537
3537
*/
3538
3538
static void stmmac_mtl_configuration(struct stmmac_priv *priv)
3539
3539
{
3540
-
u32 rx_queues_count = priv->plat->rx_queues_to_use;
3541
-
u32 tx_queues_count = priv->plat->tx_queues_to_use;
3540
+
u8 rx_queues_count = priv->plat->rx_queues_to_use;
3541
+
u8 tx_queues_count = priv->plat->tx_queues_to_use;
3542
3542
3543
3543
if (tx_queues_count > 1)
3544
3544
stmmac_set_tx_queue_weight(priv);
···
3606
3606
static int stmmac_hw_setup(struct net_device *dev)
3607
3607
{
3608
3608
struct stmmac_priv *priv = netdev_priv(dev);
3609
-
u32 rx_cnt = priv->plat->rx_queues_to_use;
3610
-
u32 tx_cnt = priv->plat->tx_queues_to_use;
3609
+
u8 rx_cnt = priv->plat->rx_queues_to_use;
3610
+
u8 tx_cnt = priv->plat->tx_queues_to_use;
3611
3611
bool sph_en;
3612
-
u32 chan;
3612
+
u8 chan;
3613
3613
int ret;
3614
3614
3615
3615
/* Make sure RX clock is enabled */
···
4001
4001
stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu)
4002
4002
{
4003
4003
struct stmmac_dma_conf *dma_conf;
4004
-
int chan, bfsize, ret;
4004
+
int bfsize, ret;
4005
+
u8 chan;
4005
4006
4006
4007
dma_conf = kzalloc_obj(*dma_conf);
4007
4008
if (!dma_conf) {
···
4077
4076
struct stmmac_dma_conf *dma_conf)
4078
4077
{
4079
4078
struct stmmac_priv *priv = netdev_priv(dev);
4080
-
u32 chan;
4079
+
u8 chan;
4081
4080
int ret;
4082
4081
4083
4082
for (int i = 0; i < MTL_MAX_TX_QUEUES; i++)
···
4176
4175
static void __stmmac_release(struct net_device *dev)
4177
4176
{
4178
4177
struct stmmac_priv *priv = netdev_priv(dev);
4179
-
u32 chan;
4178
+
u8 chan;
4180
4179
4181
4180
/* Stop and disconnect the PHY */
4182
4181
phylink_stop(priv->phylink);
···
6124
6123
6125
6124
if (priv->sph_capable) {
6126
6125
bool sph_en = (priv->hw->rx_csum > 0) && priv->sph_active;
6127
-
u32 chan;
6126
+
u8 chan;
6128
6127
6129
6128
for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
6130
6129
stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
···
6144
6143
6145
6144
static void stmmac_common_interrupt(struct stmmac_priv *priv)
6146
6145
{
6147
-
u32 rx_cnt = priv->plat->rx_queues_to_use;
6148
-
u32 tx_cnt = priv->plat->tx_queues_to_use;
6149
-
u32 queues_count;
6150
-
u32 queue;
6146
+
u8 rx_cnt = priv->plat->rx_queues_to_use;
6147
+
u8 tx_cnt = priv->plat->tx_queues_to_use;
6148
+
u8 queues_count;
6151
6149
bool xmac;
6150
+
u8 queue;
6152
6151
6153
6152
xmac = dwmac_is_xmac(priv->plat->core_type);
6154
6153
queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
···
6446
6445
{
6447
6446
struct net_device *dev = seq->private;
6448
6447
struct stmmac_priv *priv = netdev_priv(dev);
6449
-
u32 rx_count = priv->plat->rx_queues_to_use;
6450
-
u32 tx_count = priv->plat->tx_queues_to_use;
6451
-
u32 queue;
6448
+
u8 rx_count = priv->plat->rx_queues_to_use;
6449
+
u8 tx_count = priv->plat->tx_queues_to_use;
6450
+
u8 queue;
6452
6451
6453
6452
if ((dev->flags & IFF_UP) == 0)
6454
6453
return 0;
···
6573
6572
priv->dma_cap.number_rx_channel);
6574
6573
seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
6575
6574
priv->dma_cap.number_tx_channel);
6576
-
seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
6575
+
seq_printf(seq, "\tNumber of Additional RX queues: %u\n",
6577
6576
priv->dma_cap.number_rx_queues);
6578
-
seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
6577
+
seq_printf(seq, "\tNumber of Additional TX queues: %u\n",
6579
6578
priv->dma_cap.number_tx_queues);
6580
6579
seq_printf(seq, "\tEnhanced descriptors: %s\n",
6581
6580
(priv->dma_cap.enh_desc) ? "Y" : "N");
···
7044
7043
void stmmac_xdp_release(struct net_device *dev)
7045
7044
{
7046
7045
struct stmmac_priv *priv = netdev_priv(dev);
7047
-
u32 chan;
7046
+
u8 chan;
7048
7047
7049
7048
/* Ensure tx function is not running */
7050
7049
netif_tx_disable(dev);
···
7077
7076
int stmmac_xdp_open(struct net_device *dev)
7078
7077
{
7079
7078
struct stmmac_priv *priv = netdev_priv(dev);
7080
-
u32 rx_cnt = priv->plat->rx_queues_to_use;
7081
-
u32 tx_cnt = priv->plat->tx_queues_to_use;
7082
-
u32 dma_csr_ch = max(rx_cnt, tx_cnt);
7079
+
u8 rx_cnt = priv->plat->rx_queues_to_use;
7080
+
u8 tx_cnt = priv->plat->tx_queues_to_use;
7081
+
u8 dma_csr_ch = max(rx_cnt, tx_cnt);
7083
7082
struct stmmac_rx_queue *rx_q;
7084
7083
struct stmmac_tx_queue *tx_q;
7085
7084
u32 buf_size;
7086
7085
bool sph_en;
7087
-
u32 chan;
7086
+
u8 chan;
7088
7087
int ret;
7089
7088
7090
7089
ret = alloc_dma_desc_resources(priv, &priv->dma_conf);
···
7220
7219
static void stmmac_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7221
7220
{
7222
7221
struct stmmac_priv *priv = netdev_priv(dev);
7223
-
u32 tx_cnt = priv->plat->tx_queues_to_use;
7224
-
u32 rx_cnt = priv->plat->rx_queues_to_use;
7222
+
u8 tx_cnt = priv->plat->tx_queues_to_use;
7223
+
u8 rx_cnt = priv->plat->rx_queues_to_use;
7225
7224
unsigned int start;
7226
-
int q;
7225
+
u8 q;
7227
7226
7228
7227
for (q = 0; q < tx_cnt; q++) {
7229
7228
struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[q];
···
7402
7401
7403
7402
/* TXCOE doesn't work in thresh DMA mode */
7404
7403
if (priv->plat->force_thresh_dma_mode)
7405
-
priv->plat->tx_coe = 0;
7404
+
priv->plat->tx_coe = false;
7406
7405
else
7407
7406
priv->plat->tx_coe = priv->dma_cap.tx_coe;
7408
7407
···
7512
7511
static void stmmac_napi_add(struct net_device *dev)
7513
7512
{
7514
7513
struct stmmac_priv *priv = netdev_priv(dev);
7515
-
u32 queue, maxq;
7514
+
u8 queue, maxq;
7516
7515
7517
7516
maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
7518
7517
···
7541
7540
static void stmmac_napi_del(struct net_device *dev)
7542
7541
{
7543
7542
struct stmmac_priv *priv = netdev_priv(dev);
7544
-
u32 queue, maxq;
7543
+
u8 queue, maxq;
7545
7544
7546
7545
maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
7547
7546
···
7559
7558
}
7560
7559
}
7561
7560
7562
-
int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
7561
+
int stmmac_reinit_queues(struct net_device *dev, u8 rx_cnt, u8 tx_cnt)
7563
7562
{
7564
7563
struct stmmac_priv *priv = netdev_priv(dev);
7565
7564
int ret = 0, i;
···
7731
7730
if (!plat_dat)
7732
7731
return NULL;
7733
7732
7733
+
plat_dat->dma_cfg = &plat_dat->__dma_cfg;
7734
+
7734
7735
/* Set the defaults:
7735
7736
* - phy autodetection
7736
7737
* - determine GMII_Address CR field from CSR clock
···
7764
7761
{
7765
7762
struct net_device *ndev = NULL;
7766
7763
struct stmmac_priv *priv;
7767
-
u32 rxq;
7768
7764
int i, ret = 0;
7765
+
u8 rxq;
7769
7766
7770
7767
if (!plat_dat->dma_cfg || !plat_dat->dma_cfg->pbl) {
7771
7768
dev_err(device, "invalid DMA configuration\n");
···
8148
8145
{
8149
8146
struct net_device *ndev = dev_get_drvdata(dev);
8150
8147
struct stmmac_priv *priv = netdev_priv(ndev);
8151
-
u32 chan;
8148
+
u8 chan;
8152
8149
8153
8150
if (!ndev || !netif_running(ndev))
8154
8151
goto suspend_bsp;
···
8223
8220
*/
8224
8221
static void stmmac_reset_queues_param(struct stmmac_priv *priv)
8225
8222
{
8226
-
u32 rx_cnt = priv->plat->rx_queues_to_use;
8227
-
u32 tx_cnt = priv->plat->tx_queues_to_use;
8228
-
u32 queue;
8223
+
u8 rx_cnt = priv->plat->rx_queues_to_use;
8224
+
u8 tx_cnt = priv->plat->tx_queues_to_use;
8225
+
u8 queue;
8229
8226
8230
8227
for (queue = 0; queue < rx_cnt; queue++)
8231
8228
stmmac_reset_rx_queue(priv, queue);
+3
-8
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
+3
-8
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
···
25
25
/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
26
26
plat->clk_csr = STMMAC_CSR_20_35M;
27
27
plat->core_type = DWMAC_CORE_GMAC;
28
-
plat->force_sf_dma_mode = 1;
28
+
plat->force_sf_dma_mode = true;
29
29
30
30
plat->mdio_bus_data->needs_reset = true;
31
31
}
···
58
58
59
59
plat->clk_csr = STMMAC_CSR_250_300M;
60
60
plat->core_type = DWMAC_CORE_GMAC4;
61
-
plat->force_sf_dma_mode = 1;
61
+
plat->force_sf_dma_mode = true;
62
62
plat->flags |= STMMAC_FLAG_TSO_EN;
63
-
plat->pmt = 1;
63
+
plat->pmt = true;
64
64
65
65
/* Set default number of RX and TX queues to use */
66
66
plat->tx_queues_to_use = 4;
···
132
132
sizeof(*plat->mdio_bus_data),
133
133
GFP_KERNEL);
134
134
if (!plat->mdio_bus_data)
135
-
return -ENOMEM;
136
-
137
-
plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
138
-
GFP_KERNEL);
139
-
if (!plat->dma_cfg)
140
135
return -ENOMEM;
141
136
142
137
plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
+22
-21
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+22
-21
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
···
138
138
struct device_node *tx_node;
139
139
u8 queue = 0;
140
140
int ret = 0;
141
+
u32 value;
141
142
142
143
/* First Queue must always be in DCB mode. As MTL_QUEUE_DCB = 1 we need
143
144
* to always set this, otherwise Queue will be classified as AVB
···
158
157
}
159
158
160
159
/* Processing RX queues common config */
161
-
of_property_read_u32(rx_node, "snps,rx-queues-to-use",
162
-
&plat->rx_queues_to_use);
160
+
if (!of_property_read_u32(rx_node, "snps,rx-queues-to-use", &value)) {
161
+
if (value > U8_MAX)
162
+
value = U8_MAX;
163
+
plat->rx_queues_to_use = value;
164
+
}
163
165
164
166
if (of_property_read_bool(rx_node, "snps,rx-sched-sp"))
165
167
plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
···
212
208
}
213
209
214
210
/* Processing TX queues common config */
215
-
of_property_read_u32(tx_node, "snps,tx-queues-to-use",
216
-
&plat->tx_queues_to_use);
211
+
if (!of_property_read_u32(tx_node, "snps,tx-queues-to-use", &value)) {
212
+
if (value > U8_MAX)
213
+
value = U8_MAX;
214
+
plat->tx_queues_to_use = value;
215
+
}
217
216
218
217
if (of_property_read_bool(tx_node, "snps,tx-sched-wrr"))
219
218
plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
···
521
514
plat->multicast_filter_bins = dwmac1000_validate_mcast_bins(
522
515
&pdev->dev, plat->multicast_filter_bins);
523
516
plat->core_type = DWMAC_CORE_GMAC;
524
-
plat->pmt = 1;
517
+
plat->pmt = true;
525
518
}
526
519
527
520
if (of_device_is_compatible(np, "snps,dwmac-3.40a")) {
528
521
plat->core_type = DWMAC_CORE_GMAC;
529
-
plat->enh_desc = 1;
530
-
plat->tx_coe = 1;
531
-
plat->bugged_jumbo = 1;
532
-
plat->pmt = 1;
522
+
plat->enh_desc = true;
523
+
plat->tx_coe = true;
524
+
plat->bugged_jumbo = true;
525
+
plat->pmt = true;
533
526
}
534
527
535
528
if (of_device_compatible_match(np, stmmac_gmac4_compats)) {
536
529
plat->core_type = DWMAC_CORE_GMAC4;
537
-
plat->pmt = 1;
530
+
plat->pmt = true;
538
531
if (of_property_read_bool(np, "snps,tso"))
539
532
plat->flags |= STMMAC_FLAG_TSO_EN;
540
533
}
541
534
542
535
if (of_device_is_compatible(np, "snps,dwmac-3.610") ||
543
536
of_device_is_compatible(np, "snps,dwmac-3.710")) {
544
-
plat->enh_desc = 1;
545
-
plat->bugged_jumbo = 1;
546
-
plat->force_sf_dma_mode = 1;
537
+
plat->enh_desc = true;
538
+
plat->bugged_jumbo = true;
539
+
plat->force_sf_dma_mode = true;
547
540
}
548
541
549
542
if (of_device_is_compatible(np, "snps,dwxgmac")) {
550
543
plat->core_type = DWMAC_CORE_XGMAC;
551
-
plat->pmt = 1;
544
+
plat->pmt = true;
552
545
if (of_property_read_bool(np, "snps,tso"))
553
546
plat->flags |= STMMAC_FLAG_TSO_EN;
554
547
of_property_read_u32(np, "snps,multicast-filter-bins",
555
548
&plat->multicast_filter_bins);
556
549
}
557
550
558
-
dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg),
559
-
GFP_KERNEL);
560
-
if (!dma_cfg) {
561
-
ret = ERR_PTR(-ENOMEM);
562
-
goto error_put_mdio;
563
-
}
564
-
plat->dma_cfg = dma_cfg;
551
+
dma_cfg = plat->dma_cfg;
565
552
566
553
of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl);
567
554
if (!dma_cfg->pbl)
+74
-21
include/linux/stmmac.h
+74
-21
include/linux/stmmac.h
···
93
93
};
94
94
95
95
struct stmmac_dma_cfg {
96
+
/* pbl: programmable burst limit
97
+
* txpbl: transmit programmable burst limit
98
+
* rxpbl: receive programmable burst limit
99
+
* If txpbl or rxpbl are zero, the value of pbl will be substituted.
100
+
* Range 0 - 63.
101
+
*/
96
102
int pbl;
97
103
int txpbl;
98
104
int rxpbl;
105
+
/* pblx8: multiplies pbl, txpbl, rxpbl by a factor of 8 for dwmac >=
106
+
* 3.50a, or a factor of 4 for previous versions.
107
+
*/
99
108
bool pblx8;
109
+
/* fixed_burst:
110
+
* when set, AXI bursts defined by axi_blen_regval are permitted.
111
+
* AHB uses SINGLE, INCR4, INCR8 or INCR16 during burst transfers.
112
+
* when clear, AXI and AHB use SINGLE or INCR bursts.
113
+
*/
100
114
bool fixed_burst;
115
+
/* mixed_burst:
116
+
* when set and fixed_burst is clear, AHB uses INCR for bursts > 16
117
+
* and SINGLE or INCRx for bursts <= 16.
118
+
*/
101
119
bool mixed_burst;
120
+
/* aal: address aligned bursts for AHB and AXI master interface */
102
121
bool aal;
103
-
bool eame;
104
-
bool multi_msi_en;
105
122
bool dche;
123
+
bool eame;
124
+
/* multi_msi_en: stmmac core internal */
125
+
bool multi_msi_en;
126
+
/* atds: stmmac core internal */
106
127
bool atds;
107
128
};
108
129
109
130
#define AXI_BLEN 7
110
131
struct stmmac_axi {
111
-
bool axi_lpi_en;
112
-
bool axi_xit_frm;
113
132
u32 axi_wr_osr_lmt;
114
133
u32 axi_rd_osr_lmt;
115
-
bool axi_kbbe;
116
134
u32 axi_blen_regval;
135
+
bool axi_lpi_en;
136
+
bool axi_xit_frm;
137
+
bool axi_kbbe;
117
138
bool axi_fb;
118
139
bool axi_mb;
119
140
bool axi_rb;
120
141
};
121
142
122
143
struct stmmac_rxq_cfg {
123
-
u8 mode_to_use;
124
144
u32 chan;
145
+
u32 prio;
146
+
u8 mode_to_use;
125
147
u8 pkt_route;
126
148
bool use_prio;
127
-
u32 prio;
128
149
};
129
150
130
151
struct stmmac_txq_cfg {
131
152
u32 weight;
132
-
bool coe_unsupported;
133
-
u8 mode_to_use;
134
153
/* Credit Base Shaper parameters */
135
154
u32 send_slope;
136
155
u32 idle_slope;
137
156
u32 high_credit;
138
157
u32 low_credit;
139
-
bool use_prio;
140
158
u32 prio;
141
159
int tbs_en;
160
+
bool use_prio;
161
+
bool coe_unsupported;
162
+
u8 mode_to_use;
142
163
};
143
164
144
165
struct stmmac_safety_feature_cfg {
···
250
229
struct stmmac_dma_cfg *dma_cfg;
251
230
struct stmmac_safety_feature_cfg *safety_feat_cfg;
252
231
int clk_csr;
253
-
int enh_desc;
254
-
int tx_coe;
232
+
bool enh_desc;
233
+
bool tx_coe;
234
+
bool bugged_jumbo;
235
+
bool pmt;
236
+
bool force_sf_dma_mode;
237
+
bool force_thresh_dma_mode;
238
+
bool riwt_off;
255
239
int rx_coe;
256
-
int bugged_jumbo;
257
-
int pmt;
258
-
int force_sf_dma_mode;
259
-
int force_thresh_dma_mode;
260
-
int riwt_off;
261
240
int max_speed;
262
241
int maxmtu;
263
242
int multicast_filter_bins;
264
243
int unicast_filter_entries;
265
244
int tx_fifo_size;
266
245
int rx_fifo_size;
267
-
u32 host_dma_width;
268
-
u32 rx_queues_to_use;
269
-
u32 tx_queues_to_use;
246
+
u8 host_dma_width;
247
+
u8 rx_queues_to_use;
248
+
u8 tx_queues_to_use;
270
249
u8 rx_sched_algorithm;
271
250
u8 tx_sched_algorithm;
272
251
struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
···
300
279
struct phylink_pcs *(*select_pcs)(struct stmmac_priv *priv,
301
280
phy_interface_t interface);
302
281
void *bsp_priv;
282
+
283
+
/* stmmac clocks:
284
+
* stmmac_clk: CSR clock (which can be hclk_i, clk_csr_i, aclk_i,
285
+
* or clk_app_i depending on GMAC configuration). This clock
286
+
* generates the MDC clock.
287
+
*
288
+
* pclk: introduced for Imagination Technologies Pistachio board -
289
+
* see 5f9755d26fbf ("stmmac: Add an optional register interface
290
+
* clock"). This is probably used for cases where separate clocks
291
+
* are provided for the host interface and register interface. In
292
+
* this case, as the MDC clock is derived from stmmac_clk, pclk
293
+
* can only really be the "application clock" for the "host
294
+
* interface" and not the "register interface" aka CSR clock as
295
+
* it is never used when determining the divider for the MDC
296
+
* clock.
297
+
*
298
+
* clk_ptp_ref: optional PTP reference clock (clk_ptp_ref_i). When
299
+
* present, this clock increments the timestamp value. Otherwise,
300
+
* the rate of stmmac_clk will be used.
301
+
*
302
+
* clk_tx_i: MAC transmit clock, which will be 2.5MHz for 10M,
303
+
* 25MHz for 100M, or 125MHz for 1G irrespective of the interface
304
+
* mode. For the DWMAC PHY interface modes:
305
+
*
306
+
* GMII/MII PHY's transmit clock for 10M (2.5MHz) or 100M (25MHz),
307
+
* or 125MHz local clock for 1G mode
308
+
* RMII 50MHz RMII clock divided by 2 or 20.
309
+
* RGMII 125MHz local clock divided by 1, 5, or 50.
310
+
* SGMII 125MHz SerDes clock divided by 1, 5, or 50.
311
+
* TBI/RTBI 125MHz SerDes clock
312
+
*/
303
313
struct clk *stmmac_clk;
304
314
struct clk *pclk;
305
315
struct clk *clk_ptp_ref;
306
-
struct clk *clk_tx_i; /* clk_tx_i to MAC core */
316
+
struct clk *clk_tx_i;
307
317
unsigned long clk_ptp_rate;
308
318
unsigned long clk_ref_rate;
309
319
struct clk_bulk_data *clks;
···
358
306
int msi_tx_base_vec;
359
307
const struct dwmac4_addrs *dwmac4_addrs;
360
308
unsigned int flags;
309
+
struct stmmac_dma_cfg __dma_cfg;
361
310
};
362
311
#endif