Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mips-fixes_6.8_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS fixes from Thomas Bogendoerfer:
- fix boot issue on single core Lantiq Danube devices
- fix boot issue on Loongson64 platforms
- fix improper FPU setup
- fix missing prototypes issues
* tag 'mips-fixes_6.8_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
mips: Call lose_fpu(0) before initializing fcr31 in mips_set_personality_nan
MIPS: loongson64: set nid for reserved memblock region
Revert "MIPS: loongson64: set nid for reserved memblock region"
MIPS: lantiq: register smp_ops on non-smp platforms
MIPS: loongson64: set nid for reserved memblock region
MIPS: reserve exception vector space ONLY ONCE
MIPS: BCM63XX: Fix missing prototypes
MIPS: sgi-ip32: Fix missing prototypes
MIPS: sgi-ip30: Fix missing prototypes
MIPS: fw arc: Fix missing prototypes
MIPS: sgi-ip27: Fix missing prototypes
MIPS: Alchemy: Fix missing prototypes
MIPS: Cobalt: Fix missing prototypes
+83
-230
+1
arch/mips/alchemy/common/prom.c
+1
arch/mips/alchemy/common/prom.c
+1
-3
arch/mips/alchemy/common/setup.c
+1
-3
arch/mips/alchemy/common/setup.c
···
30
30
#include <linux/mm.h>
31
31
#include <linux/dma-map-ops.h> /* for dma_default_coherent */
32
32
33
+
#include <asm/bootinfo.h>
33
34
#include <asm/mipsregs.h>
34
35
35
36
#include <au1000.h>
36
-
37
-
extern void __init board_setup(void);
38
-
extern void __init alchemy_set_lpj(void);
39
37
40
38
static bool alchemy_dma_coherent(void)
41
39
{
+1
-1
arch/mips/bcm63xx/boards/board_bcm963xx.c
+1
-1
arch/mips/bcm63xx/boards/board_bcm963xx.c
···
702
702
.boardflags_hi = 0x0000,
703
703
};
704
704
705
-
int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
705
+
static int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
706
706
{
707
707
if (bus->bustype == SSB_BUSTYPE_PCI) {
708
708
memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));
+1
-1
arch/mips/bcm63xx/dev-rng.c
+1
-1
arch/mips/bcm63xx/dev-rng.c
+1
arch/mips/bcm63xx/dev-uart.c
+1
arch/mips/bcm63xx/dev-uart.c
+1
-1
arch/mips/bcm63xx/dev-wdt.c
+1
-1
arch/mips/bcm63xx/dev-wdt.c
+1
-1
arch/mips/bcm63xx/irq.c
+1
-1
arch/mips/bcm63xx/irq.c
+1
-1
arch/mips/bcm63xx/setup.c
+1
-1
arch/mips/bcm63xx/setup.c
+1
-1
arch/mips/bcm63xx/timer.c
+1
-1
arch/mips/bcm63xx/timer.c
-3
arch/mips/cobalt/setup.c
-3
arch/mips/cobalt/setup.c
+1
-1
arch/mips/fw/arc/memory.c
+1
-1
arch/mips/fw/arc/memory.c
···
37
37
*/
38
38
#define ARC_PAGE_SHIFT 12
39
39
40
-
struct linux_mdesc * __init ArcGetMemoryDescriptor(struct linux_mdesc *Current)
40
+
static struct linux_mdesc * __init ArcGetMemoryDescriptor(struct linux_mdesc *Current)
41
41
{
42
42
return (struct linux_mdesc *) ARC_CALL1(get_mdesc, Current);
43
43
}
+3
arch/mips/include/asm/mach-au1x00/au1000.h
+3
arch/mips/include/asm/mach-au1x00/au1000.h
+3
arch/mips/include/asm/mach-cobalt/cobalt.h
+3
arch/mips/include/asm/mach-cobalt/cobalt.h
+6
arch/mips/kernel/elf.c
+6
arch/mips/kernel/elf.c
···
11
11
12
12
#include <asm/cpu-features.h>
13
13
#include <asm/cpu-info.h>
14
+
#include <asm/fpu.h>
14
15
15
16
#ifdef CONFIG_MIPS_FP_SUPPORT
16
17
···
309
308
{
310
309
struct cpuinfo_mips *c = &boot_cpu_data;
311
310
struct task_struct *t = current;
311
+
312
+
/* Do this early so t->thread.fpu.fcr31 won't be clobbered in case
313
+
* we are preempted before the lose_fpu(0) in start_thread.
314
+
*/
315
+
lose_fpu(0);
312
316
313
317
t->thread.fpu.fcr31 = c->fpu_csr31;
314
318
switch (state->nan_2008) {
+7
-1
arch/mips/kernel/traps.c
+7
-1
arch/mips/kernel/traps.c
···
2007
2007
2008
2008
void reserve_exception_space(phys_addr_t addr, unsigned long size)
2009
2009
{
2010
-
memblock_reserve(addr, size);
2010
+
/*
2011
+
* reserve exception space on CPUs other than CPU0
2012
+
* is too late, since memblock is unavailable when APs
2013
+
* up
2014
+
*/
2015
+
if (smp_processor_id() == 0)
2016
+
memblock_reserve(addr, size);
2011
2017
}
2012
2018
2013
2019
void __init *set_except_vector(int n, void *addr)
+3
-4
arch/mips/lantiq/prom.c
+3
-4
arch/mips/lantiq/prom.c
···
108
108
prom_init_cmdline();
109
109
110
110
#if defined(CONFIG_MIPS_MT_SMP)
111
-
if (cpu_has_mipsmt) {
112
-
lantiq_smp_ops = vsmp_smp_ops;
111
+
lantiq_smp_ops = vsmp_smp_ops;
112
+
if (cpu_has_mipsmt)
113
113
lantiq_smp_ops.init_secondary = lantiq_init_secondary;
114
-
register_smp_ops(&lantiq_smp_ops);
115
-
}
114
+
register_smp_ops(&lantiq_smp_ops);
116
115
#endif
117
116
}
+3
arch/mips/loongson64/init.c
+3
arch/mips/loongson64/init.c
···
103
103
if (loongson_sysconf.vgabios_addr)
104
104
memblock_reserve(virt_to_phys((void *)loongson_sysconf.vgabios_addr),
105
105
SZ_256K);
106
+
/* set nid for reserved memory */
107
+
memblock_set_node((u64)node << 44, (u64)(node + 1) << 44,
108
+
&memblock.reserved, node);
106
109
}
107
110
108
111
#ifndef CONFIG_NUMA
+2
arch/mips/loongson64/numa.c
+2
arch/mips/loongson64/numa.c
+1
-1
arch/mips/sgi-ip27/Makefile
+1
-1
arch/mips/sgi-ip27/Makefile
+3
-1
arch/mips/sgi-ip27/ip27-berr.c
+3
-1
arch/mips/sgi-ip27/ip27-berr.c
···
22
22
#include <asm/traps.h>
23
23
#include <linux/uaccess.h>
24
24
25
+
#include "ip27-common.h"
26
+
25
27
static void dump_hub_information(unsigned long errst0, unsigned long errst1)
26
28
{
27
29
static char *err_type[2][8] = {
···
59
57
[st0.pi_stat0_fmt.s0_err_type] ? : "invalid");
60
58
}
61
59
62
-
int ip27_be_handler(struct pt_regs *regs, int is_fixup)
60
+
static int ip27_be_handler(struct pt_regs *regs, int is_fixup)
63
61
{
64
62
unsigned long errst0, errst1;
65
63
int data = regs->cp0_cause & 4;
+2
arch/mips/sgi-ip27/ip27-common.h
+2
arch/mips/sgi-ip27/ip27-common.h
···
10
10
extern void hub_rtc_init(nasid_t nasid);
11
11
extern void install_cpu_nmi_handler(int slice);
12
12
extern void install_ipi(void);
13
+
extern void ip27_be_init(void);
13
14
extern void ip27_reboot_setup(void);
14
15
extern const struct plat_smp_ops ip27_smp_ops;
15
16
extern unsigned long node_getfirstfree(nasid_t nasid);
16
17
extern void per_cpu_init(void);
17
18
extern void replicate_kernel_text(void);
18
19
extern void setup_replication_mask(void);
20
+
19
21
20
22
#endif /* __IP27_COMMON_H */
-185
arch/mips/sgi-ip27/ip27-hubio.c
-185
arch/mips/sgi-ip27/ip27-hubio.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc.
4
-
* Copyright (C) 2004 Christoph Hellwig.
5
-
*
6
-
* Support functions for the HUB ASIC - mostly PIO mapping related.
7
-
*/
8
-
9
-
#include <linux/bitops.h>
10
-
#include <linux/string.h>
11
-
#include <linux/mmzone.h>
12
-
#include <asm/sn/addrs.h>
13
-
#include <asm/sn/arch.h>
14
-
#include <asm/sn/agent.h>
15
-
#include <asm/sn/io.h>
16
-
#include <asm/xtalk/xtalk.h>
17
-
18
-
19
-
static int force_fire_and_forget = 1;
20
-
21
-
/**
22
-
* hub_pio_map - establish a HUB PIO mapping
23
-
*
24
-
* @nasid: nasid to perform PIO mapping on
25
-
* @widget: widget ID to perform PIO mapping for
26
-
* @xtalk_addr: xtalk_address that needs to be mapped
27
-
* @size: size of the PIO mapping
28
-
*
29
-
**/
30
-
unsigned long hub_pio_map(nasid_t nasid, xwidgetnum_t widget,
31
-
unsigned long xtalk_addr, size_t size)
32
-
{
33
-
unsigned i;
34
-
35
-
/* use small-window mapping if possible */
36
-
if ((xtalk_addr % SWIN_SIZE) + size <= SWIN_SIZE)
37
-
return NODE_SWIN_BASE(nasid, widget) + (xtalk_addr % SWIN_SIZE);
38
-
39
-
if ((xtalk_addr % BWIN_SIZE) + size > BWIN_SIZE) {
40
-
printk(KERN_WARNING "PIO mapping at hub %d widget %d addr 0x%lx"
41
-
" too big (%ld)\n",
42
-
nasid, widget, xtalk_addr, size);
43
-
return 0;
44
-
}
45
-
46
-
xtalk_addr &= ~(BWIN_SIZE-1);
47
-
for (i = 0; i < HUB_NUM_BIG_WINDOW; i++) {
48
-
if (test_and_set_bit(i, hub_data(nasid)->h_bigwin_used))
49
-
continue;
50
-
51
-
/*
52
-
* The code below does a PIO write to setup an ITTE entry.
53
-
*
54
-
* We need to prevent other CPUs from seeing our updated
55
-
* memory shadow of the ITTE (in the piomap) until the ITTE
56
-
* entry is actually set up; otherwise, another CPU might
57
-
* attempt a PIO prematurely.
58
-
*
59
-
* Also, the only way we can know that an entry has been
60
-
* received by the hub and can be used by future PIO reads/
61
-
* writes is by reading back the ITTE entry after writing it.
62
-
*
63
-
* For these two reasons, we PIO read back the ITTE entry
64
-
* after we write it.
65
-
*/
66
-
IIO_ITTE_PUT(nasid, i, HUB_PIO_MAP_TO_MEM, widget, xtalk_addr);
67
-
__raw_readq(IIO_ITTE_GET(nasid, i));
68
-
69
-
return NODE_BWIN_BASE(nasid, widget) + (xtalk_addr % BWIN_SIZE);
70
-
}
71
-
72
-
printk(KERN_WARNING "unable to establish PIO mapping for at"
73
-
" hub %d widget %d addr 0x%lx\n",
74
-
nasid, widget, xtalk_addr);
75
-
return 0;
76
-
}
77
-
78
-
79
-
/*
80
-
* hub_setup_prb(nasid, prbnum, credits, conveyor)
81
-
*
82
-
* Put a PRB into fire-and-forget mode if conveyor isn't set. Otherwise,
83
-
* put it into conveyor belt mode with the specified number of credits.
84
-
*/
85
-
static void hub_setup_prb(nasid_t nasid, int prbnum, int credits)
86
-
{
87
-
union iprb_u prb;
88
-
int prb_offset;
89
-
90
-
/*
91
-
* Get the current register value.
92
-
*/
93
-
prb_offset = IIO_IOPRB(prbnum);
94
-
prb.iprb_regval = REMOTE_HUB_L(nasid, prb_offset);
95
-
96
-
/*
97
-
* Clear out some fields.
98
-
*/
99
-
prb.iprb_ovflow = 1;
100
-
prb.iprb_bnakctr = 0;
101
-
prb.iprb_anakctr = 0;
102
-
103
-
/*
104
-
* Enable or disable fire-and-forget mode.
105
-
*/
106
-
prb.iprb_ff = force_fire_and_forget ? 1 : 0;
107
-
108
-
/*
109
-
* Set the appropriate number of PIO credits for the widget.
110
-
*/
111
-
prb.iprb_xtalkctr = credits;
112
-
113
-
/*
114
-
* Store the new value to the register.
115
-
*/
116
-
REMOTE_HUB_S(nasid, prb_offset, prb.iprb_regval);
117
-
}
118
-
119
-
/**
120
-
* hub_set_piomode - set pio mode for a given hub
121
-
*
122
-
* @nasid: physical node ID for the hub in question
123
-
*
124
-
* Put the hub into either "PIO conveyor belt" mode or "fire-and-forget" mode.
125
-
* To do this, we have to make absolutely sure that no PIOs are in progress
126
-
* so we turn off access to all widgets for the duration of the function.
127
-
*
128
-
* XXX - This code should really check what kind of widget we're talking
129
-
* to. Bridges can only handle three requests, but XG will do more.
130
-
* How many can crossbow handle to widget 0? We're assuming 1.
131
-
*
132
-
* XXX - There is a bug in the crossbow that link reset PIOs do not
133
-
* return write responses. The easiest solution to this problem is to
134
-
* leave widget 0 (xbow) in fire-and-forget mode at all times. This
135
-
* only affects pio's to xbow registers, which should be rare.
136
-
**/
137
-
static void hub_set_piomode(nasid_t nasid)
138
-
{
139
-
u64 ii_iowa;
140
-
union hubii_wcr_u ii_wcr;
141
-
unsigned i;
142
-
143
-
ii_iowa = REMOTE_HUB_L(nasid, IIO_OUTWIDGET_ACCESS);
144
-
REMOTE_HUB_S(nasid, IIO_OUTWIDGET_ACCESS, 0);
145
-
146
-
ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid, IIO_WCR);
147
-
148
-
if (ii_wcr.iwcr_dir_con) {
149
-
/*
150
-
* Assume a bridge here.
151
-
*/
152
-
hub_setup_prb(nasid, 0, 3);
153
-
} else {
154
-
/*
155
-
* Assume a crossbow here.
156
-
*/
157
-
hub_setup_prb(nasid, 0, 1);
158
-
}
159
-
160
-
/*
161
-
* XXX - Here's where we should take the widget type into
162
-
* when account assigning credits.
163
-
*/
164
-
for (i = HUB_WIDGET_ID_MIN; i <= HUB_WIDGET_ID_MAX; i++)
165
-
hub_setup_prb(nasid, i, 3);
166
-
167
-
REMOTE_HUB_S(nasid, IIO_OUTWIDGET_ACCESS, ii_iowa);
168
-
}
169
-
170
-
/*
171
-
* hub_pio_init - PIO-related hub initialization
172
-
*
173
-
* @hub: hubinfo structure for our hub
174
-
*/
175
-
void hub_pio_init(nasid_t nasid)
176
-
{
177
-
unsigned i;
178
-
179
-
/* initialize big window piomaps for this hub */
180
-
bitmap_zero(hub_data(nasid)->h_bigwin_used, HUB_NUM_BIG_WINDOW);
181
-
for (i = 0; i < HUB_NUM_BIG_WINDOW; i++)
182
-
IIO_ITTE_DISABLE(nasid, i);
183
-
184
-
hub_set_piomode(nasid);
185
-
}
+2
arch/mips/sgi-ip27/ip27-irq.c
+2
arch/mips/sgi-ip27/ip27-irq.c
+1
arch/mips/sgi-ip27/ip27-memory.c
+1
arch/mips/sgi-ip27/ip27-memory.c
+8
-17
arch/mips/sgi-ip27/ip27-nmi.c
+8
-17
arch/mips/sgi-ip27/ip27-nmi.c
···
11
11
#include <asm/sn/arch.h>
12
12
#include <asm/sn/agent.h>
13
13
14
+
#include "ip27-common.h"
15
+
14
16
#if 0
15
17
#define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n)
16
18
#else
···
25
23
typedef unsigned long machreg_t;
26
24
27
25
static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED;
28
-
29
-
/*
30
-
* Let's see what else we need to do here. Set up sp, gp?
31
-
*/
32
-
void nmi_dump(void)
33
-
{
34
-
void cont_nmi_dump(void);
35
-
36
-
cont_nmi_dump();
37
-
}
26
+
static void nmi_dump(void);
38
27
39
28
void install_cpu_nmi_handler(int slice)
40
29
{
···
46
53
* into the eframe format for the node under consideration.
47
54
*/
48
55
49
-
void nmi_cpu_eframe_save(nasid_t nasid, int slice)
56
+
static void nmi_cpu_eframe_save(nasid_t nasid, int slice)
50
57
{
51
58
struct reg_struct *nr;
52
59
int i;
···
122
129
pr_emerg("\n");
123
130
}
124
131
125
-
void nmi_dump_hub_irq(nasid_t nasid, int slice)
132
+
static void nmi_dump_hub_irq(nasid_t nasid, int slice)
126
133
{
127
134
u64 mask0, mask1, pend0, pend1;
128
135
···
146
153
* Copy the cpu registers which have been saved in the IP27prom format
147
154
* into the eframe format for the node under consideration.
148
155
*/
149
-
void nmi_node_eframe_save(nasid_t nasid)
156
+
static void nmi_node_eframe_save(nasid_t nasid)
150
157
{
151
158
int slice;
152
159
···
163
170
/*
164
171
* Save the nmi cpu registers for all cpus in the system.
165
172
*/
166
-
void
167
-
nmi_eframes_save(void)
173
+
static void nmi_eframes_save(void)
168
174
{
169
175
nasid_t nasid;
170
176
···
171
179
nmi_node_eframe_save(nasid);
172
180
}
173
181
174
-
void
175
-
cont_nmi_dump(void)
182
+
static void nmi_dump(void)
176
183
{
177
184
#ifndef REAL_NMI_SIGNAL
178
185
static atomic_t nmied_cpus = ATOMIC_INIT(0);
+1
arch/mips/sgi-ip30/ip30-console.c
+1
arch/mips/sgi-ip30/ip30-console.c
+1
arch/mips/sgi-ip30/ip30-setup.c
+1
arch/mips/sgi-ip30/ip30-setup.c
+4
-2
arch/mips/sgi-ip32/crime.c
+4
-2
arch/mips/sgi-ip32/crime.c
···
18
18
#include <asm/ip32/crime.h>
19
19
#include <asm/ip32/mace.h>
20
20
21
+
#include "ip32-common.h"
22
+
21
23
struct sgi_crime __iomem *crime;
22
24
struct sgi_mace __iomem *mace;
23
25
···
41
39
id, rev, field, (unsigned long) CRIME_BASE);
42
40
}
43
41
44
-
irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id)
42
+
irqreturn_t crime_memerr_intr(int irq, void *dev_id)
45
43
{
46
44
unsigned long stat, addr;
47
45
int fatal = 0;
···
92
90
return IRQ_HANDLED;
93
91
}
94
92
95
-
irqreturn_t crime_cpuerr_intr(unsigned int irq, void *dev_id)
93
+
irqreturn_t crime_cpuerr_intr(int irq, void *dev_id)
96
94
{
97
95
unsigned long stat = crime->cpu_error_stat & CRIME_CPU_ERROR_MASK;
98
96
unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK;
+2
arch/mips/sgi-ip32/ip32-berr.c
+2
arch/mips/sgi-ip32/ip32-berr.c
+15
arch/mips/sgi-ip32/ip32-common.h
+15
arch/mips/sgi-ip32/ip32-common.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
3
+
#ifndef __IP32_COMMON_H
4
+
#define __IP32_COMMON_H
5
+
6
+
#include <linux/init.h>
7
+
#include <linux/interrupt.h>
8
+
9
+
void __init crime_init(void);
10
+
irqreturn_t crime_memerr_intr(int irq, void *dev_id);
11
+
irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
12
+
void __init ip32_be_init(void);
13
+
void ip32_prepare_poweroff(void);
14
+
15
+
#endif /* __IP32_COMMON_H */
+2
-4
arch/mips/sgi-ip32/ip32-irq.c
+2
-4
arch/mips/sgi-ip32/ip32-irq.c
···
28
28
#include <asm/ip32/mace.h>
29
29
#include <asm/ip32/ip32_ints.h>
30
30
31
+
#include "ip32-common.h"
32
+
31
33
/* issue a PIO read to make sure no PIO writes are pending */
32
34
static inline void flush_crime_bus(void)
33
35
{
···
108
106
* different IRQ map than IRIX uses, but that's OK as Linux irq handling
109
107
* is quite different anyway.
110
108
*/
111
-
112
-
/* Some initial interrupts to set up */
113
-
extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
114
-
extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
115
109
116
110
/*
117
111
* This is for pure CRIME interrupts - ie not MACE. The advantage?
+1
arch/mips/sgi-ip32/ip32-memory.c
+1
arch/mips/sgi-ip32/ip32-memory.c
+2
arch/mips/sgi-ip32/ip32-reset.c
+2
arch/mips/sgi-ip32/ip32-reset.c