Merge tag 'drm-fixes-2024-03-30' of https://gitlab.freedesktop.org/drm/kernel

+3 -3

drivers/dma-buf/st-dma-fence-chain.c

··· 84 84 return -ENOMEM; 85 85 86 86 chain = mock_chain(NULL, f, 1); 87 - if (!chain) 87 + if (chain) 88 + dma_fence_enable_sw_signaling(chain); 89 + else 88 90 err = -ENOMEM; 89 - 90 - dma_fence_enable_sw_signaling(chain); 91 91 92 92 dma_fence_signal(f); 93 93 dma_fence_put(f);

+2

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

··· 4539 4539 if (r) 4540 4540 goto unprepare; 4541 4541 4542 + flush_delayed_work(&adev->gfx.gfx_off_delay_work); 4543 + 4542 4544 for (i = 0; i < adev->num_ip_blocks; i++) { 4543 4545 if (!adev->ip_blocks[i].status.valid) 4544 4546 continue;

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

··· 2237 2237 { 2238 2238 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2239 2239 case IP_VERSION(4, 0, 5): 2240 + case IP_VERSION(4, 0, 6): 2240 2241 if (amdgpu_umsch_mm & 0x1) { 2241 2242 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2242 2243 adev->enable_umsch_mm = true;

+29 -17

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

··· 524 524 { 525 525 struct amdgpu_ring *ring = file_inode(f)->i_private; 526 526 volatile u32 *mqd; 527 - int r; 527 + u32 *kbuf; 528 + int r, i; 528 529 uint32_t value, result; 529 530 530 531 if (*pos & 3 || size & 3) 531 532 return -EINVAL; 532 533 533 - result = 0; 534 + kbuf = kmalloc(ring->mqd_size, GFP_KERNEL); 535 + if (!kbuf) 536 + return -ENOMEM; 534 537 535 538 r = amdgpu_bo_reserve(ring->mqd_obj, false); 536 539 if (unlikely(r != 0)) 537 - return r; 540 + goto err_free; 538 541 539 542 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&mqd); 540 - if (r) { 541 - amdgpu_bo_unreserve(ring->mqd_obj); 542 - return r; 543 - } 543 + if (r) 544 + goto err_unreserve; 544 545 546 + /* 547 + * Copy to local buffer to avoid put_user(), which might fault 548 + * and acquire mmap_sem, under reservation_ww_class_mutex. 549 + */ 550 + for (i = 0; i < ring->mqd_size/sizeof(u32); i++) 551 + kbuf[i] = mqd[i]; 552 + 553 + amdgpu_bo_kunmap(ring->mqd_obj); 554 + amdgpu_bo_unreserve(ring->mqd_obj); 555 + 556 + result = 0; 545 557 while (size) { 546 558 if (*pos >= ring->mqd_size) 547 - goto done; 559 + break; 548 560 549 - value = mqd[*pos/4]; 561 + value = kbuf[*pos/4]; 550 562 r = put_user(value, (uint32_t *)buf); 551 563 if (r) 552 - goto done; 564 + goto err_free; 553 565 buf += 4; 554 566 result += 4; 555 567 size -= 4; 556 568 *pos += 4; 557 569 } 558 570 559 - done: 560 - amdgpu_bo_kunmap(ring->mqd_obj); 561 - mqd = NULL; 562 - amdgpu_bo_unreserve(ring->mqd_obj); 563 - if (r) 564 - return r; 565 - 571 + kfree(kbuf); 566 572 return result; 573 + 574 + err_unreserve: 575 + amdgpu_bo_unreserve(ring->mqd_obj); 576 + err_free: 577 + kfree(kbuf); 578 + return r; 567 579 } 568 580 569 581 static const struct file_operations amdgpu_debugfs_mqd_fops = {

+10 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c

··· 189 189 mqd->rptr_val = 0; 190 190 mqd->unmapped = 1; 191 191 192 + if (adev->vpe.collaborate_mode) 193 + memcpy(++mqd, test->mqd_data_cpu_addr, sizeof(struct MQD_INFO)); 194 + 192 195 qinfo->mqd_addr = test->mqd_data_gpu_addr; 193 196 qinfo->csa_addr = test->ctx_data_gpu_addr + 194 197 offsetof(struct umsch_mm_test_ctx_data, vpe_ctx_csa); 195 - qinfo->doorbell_offset_0 = (adev->doorbell_index.vpe_ring + 1) << 1; 198 + qinfo->doorbell_offset_0 = 0; 196 199 qinfo->doorbell_offset_1 = 0; 197 200 } 198 201 ··· 290 287 ring[5] = 0; 291 288 292 289 mqd->wptr_val = (6 << 2); 293 - // WDOORBELL32(adev->umsch_mm.agdb_index[CONTEXT_PRIORITY_LEVEL_NORMAL], mqd->wptr_val); 290 + if (adev->vpe.collaborate_mode) 291 + (++mqd)->wptr_val = (6 << 2); 292 + 293 + WDOORBELL32(adev->umsch_mm.agdb_index[CONTEXT_PRIORITY_LEVEL_NORMAL], mqd->wptr_val); 294 294 295 295 for (i = 0; i < adev->usec_timeout; i++) { 296 296 if (*fence == test_pattern) ··· 577 571 578 572 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 579 573 case IP_VERSION(4, 0, 5): 574 + case IP_VERSION(4, 0, 6): 580 575 fw_name = "amdgpu/umsch_mm_4_0_0.bin"; 581 576 break; 582 577 default: ··· 757 750 758 751 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 759 752 case IP_VERSION(4, 0, 5): 753 + case IP_VERSION(4, 0, 6): 760 754 umsch_mm_v4_0_set_funcs(&adev->umsch_mm); 761 755 break; 762 756 default:

+10 -10

drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h

··· 33 33 UMSCH_SWIP_ENGINE_TYPE_MAX 34 34 }; 35 35 36 - enum UMSCH_SWIP_AFFINITY_TYPE { 37 - UMSCH_SWIP_AFFINITY_TYPE_ANY = 0, 38 - UMSCH_SWIP_AFFINITY_TYPE_VCN0 = 1, 39 - UMSCH_SWIP_AFFINITY_TYPE_VCN1 = 2, 40 - UMSCH_SWIP_AFFINITY_TYPE_MAX 41 - }; 42 - 43 36 enum UMSCH_CONTEXT_PRIORITY_LEVEL { 44 37 CONTEXT_PRIORITY_LEVEL_IDLE = 0, 45 38 CONTEXT_PRIORITY_LEVEL_NORMAL = 1, ··· 44 51 struct umsch_mm_set_resource_input { 45 52 uint32_t vmid_mask_mm_vcn; 46 53 uint32_t vmid_mask_mm_vpe; 54 + uint32_t collaboration_mask_vpe; 47 55 uint32_t logging_vmid; 48 56 uint32_t engine_mask; 49 57 union { 50 58 struct { 51 59 uint32_t disable_reset : 1; 52 60 uint32_t disable_umsch_mm_log : 1; 53 - uint32_t reserved : 30; 61 + uint32_t use_rs64mem_for_proc_ctx_csa : 1; 62 + uint32_t reserved : 29; 54 63 }; 55 64 uint32_t uint32_all; 56 65 }; ··· 73 78 uint32_t doorbell_offset_1; 74 79 enum UMSCH_SWIP_ENGINE_TYPE engine_type; 75 80 uint32_t affinity; 76 - enum UMSCH_SWIP_AFFINITY_TYPE affinity_type; 77 81 uint64_t mqd_addr; 78 82 uint64_t h_context; 79 83 uint64_t h_queue; 80 84 uint32_t vm_context_cntl; 81 85 86 + uint32_t process_csa_array_index; 87 + uint32_t context_csa_array_index; 88 + 82 89 struct { 83 90 uint32_t is_context_suspended : 1; 84 - uint32_t reserved : 31; 91 + uint32_t collaboration_mode : 1; 92 + uint32_t reserved : 30; 85 93 }; 86 94 }; 87 95 ··· 92 94 uint32_t doorbell_offset_0; 93 95 uint32_t doorbell_offset_1; 94 96 uint64_t context_csa_addr; 97 + uint32_t context_csa_array_index; 95 98 }; 96 99 97 100 struct MQD_INFO { ··· 102 103 uint32_t wptr_val; 103 104 uint32_t rptr_val; 104 105 uint32_t unmapped; 106 + uint32_t vmid; 105 107 }; 106 108 107 109 struct amdgpu_umsch_mm;

+6

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

··· 396 396 struct amdgpu_vpe *vpe = &adev->vpe; 397 397 int ret; 398 398 399 + /* Power on VPE */ 400 + ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, 401 + AMD_PG_STATE_UNGATE); 402 + if (ret) 403 + return ret; 404 + 399 405 ret = vpe_load_microcode(vpe); 400 406 if (ret) 401 407 return ret;

+5 -2

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

··· 60 60 61 61 umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr; 62 62 63 - if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) { 63 + if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) { 64 64 WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG, 65 65 1 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT); 66 66 SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS, ··· 248 248 data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0); 249 249 WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data); 250 250 251 - if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) { 251 + if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) { 252 252 WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG, 253 253 2 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT); 254 254 SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS, ··· 271 271 272 272 set_hw_resources.vmid_mask_mm_vcn = umsch->vmid_mask_mm_vcn; 273 273 set_hw_resources.vmid_mask_mm_vpe = umsch->vmid_mask_mm_vpe; 274 + set_hw_resources.collaboration_mask_vpe = 275 + adev->vpe.collaborate_mode ? 0x3 : 0x0; 274 276 set_hw_resources.engine_mask = umsch->engine_mask; 275 277 276 278 set_hw_resources.vcn0_hqd_mask[0] = umsch->vcn0_hqd_mask; ··· 348 346 add_queue.h_queue = input_ptr->h_queue; 349 347 add_queue.vm_context_cntl = input_ptr->vm_context_cntl; 350 348 add_queue.is_context_suspended = input_ptr->is_context_suspended; 349 + add_queue.collaboration_mode = adev->vpe.collaborate_mode ? 1 : 0; 351 350 352 351 add_queue.api_status.api_completion_fence_addr = umsch->ring.fence_drv.gpu_addr; 353 352 add_queue.api_status.api_completion_fence_value = ++umsch->ring.fence_drv.sync_seq;

+2 -2

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

··· 1523 1523 1524 1524 /* Find a KFD GPU device that supports the get_dmabuf_info query */ 1525 1525 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++) 1526 - if (dev) 1526 + if (dev && !kfd_devcgroup_check_permission(dev)) 1527 1527 break; 1528 1528 if (!dev) 1529 1529 return -EINVAL; ··· 1545 1545 if (xcp_id >= 0) 1546 1546 args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id; 1547 1547 else 1548 - args->gpu_id = dmabuf_adev->kfd.dev->nodes[0]->id; 1548 + args->gpu_id = dev->id; 1549 1549 args->flags = flags; 1550 1550 1551 1551 /* Copy metadata buffer to user mode */

+2 -1

drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c

··· 339 339 break; 340 340 } 341 341 kfd_signal_event_interrupt(pasid, context_id0 & 0x7fffff, 23); 342 - } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) { 342 + } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && 343 + KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) { 343 344 kfd_set_dbg_ev_from_interrupt(dev, pasid, 344 345 KFD_DEBUG_DOORBELL_ID(context_id0), 345 346 KFD_EC_MASK(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0)),

+2 -1

drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c

··· 328 328 /* CP */ 329 329 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) 330 330 kfd_signal_event_interrupt(pasid, context_id0, 32); 331 - else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) 331 + else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && 332 + KFD_DBG_EC_TYPE_IS_PACKET(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0))) 332 333 kfd_set_dbg_ev_from_interrupt(dev, pasid, 333 334 KFD_CTXID0_DOORBELL_ID(context_id0), 334 335 KFD_EC_MASK(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0)),

+2 -1

drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c

··· 388 388 break; 389 389 } 390 390 kfd_signal_event_interrupt(pasid, sq_int_data, 24); 391 - } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) { 391 + } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && 392 + KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) { 392 393 kfd_set_dbg_ev_from_interrupt(dev, pasid, 393 394 KFD_DEBUG_DOORBELL_ID(context_id0), 394 395 KFD_EC_MASK(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0)),

+1 -1

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

··· 1473 1473 1474 1474 static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev) 1475 1475 { 1476 - return KFD_GC_VERSION(dev) > IP_VERSION(9, 4, 2) || 1476 + return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 2) || 1477 1477 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) || 1478 1478 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0); 1479 1479 }

+3 -5

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 6305 6305 6306 6306 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 6307 6307 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 6308 - else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 6309 - stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 6310 - stream->signal == SIGNAL_TYPE_EDP) { 6308 + 6309 + if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) { 6311 6310 // 6312 6311 // should decide stream support vsc sdp colorimetry capability 6313 6312 // before building vsc info packet ··· 6322 6323 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) 6323 6324 tf = TRANSFER_FUNC_GAMMA_22; 6324 6325 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); 6326 + aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 6325 6327 6326 - if (stream->link->psr_settings.psr_feature_enabled) 6327 - aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 6328 6328 } 6329 6329 finish: 6330 6330 dc_sink_release(sink);

+5 -3

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

··· 141 141 * amdgpu_dm_psr_enable() - enable psr f/w 142 142 * @stream: stream state 143 143 * 144 - * Return: true if success 145 144 */ 146 - bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) 145 + void amdgpu_dm_psr_enable(struct dc_stream_state *stream) 147 146 { 148 147 struct dc_link *link = stream->link; 149 148 unsigned int vsync_rate_hz = 0; ··· 189 190 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) 190 191 power_opt |= psr_power_opt_z10_static_screen; 191 192 192 - return dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt); 193 + dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt); 194 + 195 + if (link->ctx->dc->caps.ips_support) 196 + dc_allow_idle_optimizations(link->ctx->dc, true); 193 197 } 194 198 195 199 /*

+1 -1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h

··· 32 32 #define AMDGPU_DM_PSR_ENTRY_DELAY 5 33 33 34 34 void amdgpu_dm_set_psr_caps(struct dc_link *link); 35 - bool amdgpu_dm_psr_enable(struct dc_stream_state *stream); 35 + void amdgpu_dm_psr_enable(struct dc_stream_state *stream); 36 36 bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream); 37 37 bool amdgpu_dm_psr_disable(struct dc_stream_state *stream); 38 38 bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);

+6 -1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

··· 73 73 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L 74 74 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L 75 75 76 + #define SMU_VER_THRESHOLD 0x5D4A00 //93.74.0 77 + 76 78 #define REG(reg_name) \ 77 79 (ctx->clk_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 78 80 ··· 413 411 414 412 static void init_clk_states(struct clk_mgr *clk_mgr) 415 413 { 414 + struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); 416 415 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; 417 416 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 418 417 418 + if (clk_mgr_int->smu_ver >= SMU_VER_THRESHOLD) 419 + clk_mgr->clks.dtbclk_en = true; // request DTBCLK disable on first commit 419 420 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk 420 421 clk_mgr->clks.p_state_change_support = true; 421 422 clk_mgr->clks.prev_p_state_change_support = true; ··· 714 709 clock_table->NumFclkLevelsEnabled; 715 710 max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq, num_fclk); 716 711 717 - num_dcfclk = (clock_table->NumFclkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS : 712 + num_dcfclk = (clock_table->NumDcfClkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS : 718 713 clock_table->NumDcfClkLevelsEnabled; 719 714 for (i = 0; i < num_dcfclk; i++) { 720 715 int j;

+4 -2

drivers/gpu/drm/amd/display/dc/core/dc.c

··· 3024 3024 scratch->blend_tf[i] = *status->plane_states[i]->blend_tf; 3025 3025 } 3026 3026 scratch->stream_state = *stream; 3027 - scratch->out_transfer_func = *stream->out_transfer_func; 3027 + if (stream->out_transfer_func) 3028 + scratch->out_transfer_func = *stream->out_transfer_func; 3028 3029 } 3029 3030 3030 3031 static void restore_planes_and_stream_state( ··· 3047 3046 *status->plane_states[i]->blend_tf = scratch->blend_tf[i]; 3048 3047 } 3049 3048 *stream = scratch->stream_state; 3050 - *stream->out_transfer_func = scratch->out_transfer_func; 3049 + if (stream->out_transfer_func) 3050 + *stream->out_transfer_func = scratch->out_transfer_func; 3051 3051 } 3052 3052 3053 3053 static bool update_planes_and_stream_state(struct dc *dc,

+32 -22

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c

··· 44 44 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) 45 45 46 46 47 + void mpc3_mpc_init(struct mpc *mpc) 48 + { 49 + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 50 + int opp_id; 51 + 52 + mpc1_mpc_init(mpc); 53 + 54 + for (opp_id = 0; opp_id < MAX_OPP; opp_id++) { 55 + if (REG(MUX[opp_id])) 56 + /* disable mpc out rate and flow control */ 57 + REG_UPDATE_2(MUX[opp_id], MPC_OUT_RATE_CONTROL_DISABLE, 58 + 1, MPC_OUT_FLOW_CONTROL_COUNT, 0); 59 + } 60 + } 61 + 62 + void mpc3_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) 63 + { 64 + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 65 + 66 + mpc1_mpc_init_single_inst(mpc, mpcc_id); 67 + 68 + /* assuming mpc out mux is connected to opp with the same index at this 69 + * point in time (e.g. transitioning from vbios to driver) 70 + */ 71 + if (mpcc_id < MAX_OPP && REG(MUX[mpcc_id])) 72 + /* disable mpc out rate and flow control */ 73 + REG_UPDATE_2(MUX[mpcc_id], MPC_OUT_RATE_CONTROL_DISABLE, 74 + 1, MPC_OUT_FLOW_CONTROL_COUNT, 0); 75 + } 76 + 47 77 bool mpc3_is_dwb_idle( 48 78 struct mpc *mpc, 49 79 int dwb_id) ··· 108 78 109 79 REG_SET(DWB_MUX[dwb_id], 0, 110 80 MPC_DWB0_MUX, 0xf); 111 - } 112 - 113 - void mpc3_set_out_rate_control( 114 - struct mpc *mpc, 115 - int opp_id, 116 - bool enable, 117 - bool rate_2x_mode, 118 - struct mpc_dwb_flow_control *flow_control) 119 - { 120 - struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 121 - 122 - REG_UPDATE_2(MUX[opp_id], 123 - MPC_OUT_RATE_CONTROL_DISABLE, !enable, 124 - MPC_OUT_RATE_CONTROL, rate_2x_mode); 125 - 126 - if (flow_control) 127 - REG_UPDATE_2(MUX[opp_id], 128 - MPC_OUT_FLOW_CONTROL_MODE, flow_control->flow_ctrl_mode, 129 - MPC_OUT_FLOW_CONTROL_COUNT, flow_control->flow_ctrl_cnt1); 130 81 } 131 82 132 83 enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) ··· 1501 1490 .read_mpcc_state = mpc3_read_mpcc_state, 1502 1491 .insert_plane = mpc1_insert_plane, 1503 1492 .remove_mpcc = mpc1_remove_mpcc, 1504 - .mpc_init = mpc1_mpc_init, 1505 - .mpc_init_single_inst = mpc1_mpc_init_single_inst, 1493 + .mpc_init = mpc3_mpc_init, 1494 + .mpc_init_single_inst = mpc3_mpc_init_single_inst, 1506 1495 .update_blending = mpc2_update_blending, 1507 1496 .cursor_lock = mpc1_cursor_lock, 1508 1497 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, ··· 1519 1508 .set_dwb_mux = mpc3_set_dwb_mux, 1520 1509 .disable_dwb_mux = mpc3_disable_dwb_mux, 1521 1510 .is_dwb_idle = mpc3_is_dwb_idle, 1522 - .set_out_rate_control = mpc3_set_out_rate_control, 1523 1511 .set_gamut_remap = mpc3_set_gamut_remap, 1524 1512 .program_shaper = mpc3_program_shaper, 1525 1513 .acquire_rmu = mpcc3_acquire_rmu,

+7 -7

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h

··· 1007 1007 int num_mpcc, 1008 1008 int num_rmu); 1009 1009 1010 + void mpc3_mpc_init( 1011 + struct mpc *mpc); 1012 + 1013 + void mpc3_mpc_init_single_inst( 1014 + struct mpc *mpc, 1015 + unsigned int mpcc_id); 1016 + 1010 1017 bool mpc3_program_shaper( 1011 1018 struct mpc *mpc, 1012 1019 const struct pwl_params *params, ··· 1084 1077 bool mpc3_is_dwb_idle( 1085 1078 struct mpc *mpc, 1086 1079 int dwb_id); 1087 - 1088 - void mpc3_set_out_rate_control( 1089 - struct mpc *mpc, 1090 - int opp_id, 1091 - bool enable, 1092 - bool rate_2x_mode, 1093 - struct mpc_dwb_flow_control *flow_control); 1094 1080 1095 1081 void mpc3_power_on_ogam_lut( 1096 1082 struct mpc *mpc, int mpcc_id,

+2 -3

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c

··· 47 47 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 48 48 int mpcc_id; 49 49 50 - mpc1_mpc_init(mpc); 50 + mpc3_mpc_init(mpc); 51 51 52 52 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { 53 53 if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) { ··· 991 991 .insert_plane = mpc1_insert_plane, 992 992 .remove_mpcc = mpc1_remove_mpcc, 993 993 .mpc_init = mpc32_mpc_init, 994 - .mpc_init_single_inst = mpc1_mpc_init_single_inst, 994 + .mpc_init_single_inst = mpc3_mpc_init_single_inst, 995 995 .update_blending = mpc2_update_blending, 996 996 .cursor_lock = mpc1_cursor_lock, 997 997 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, ··· 1008 1008 .set_dwb_mux = mpc3_set_dwb_mux, 1009 1009 .disable_dwb_mux = mpc3_disable_dwb_mux, 1010 1010 .is_dwb_idle = mpc3_is_dwb_idle, 1011 - .set_out_rate_control = mpc3_set_out_rate_control, 1012 1011 .set_gamut_remap = mpc3_set_gamut_remap, 1013 1012 .program_shaper = mpc32_program_shaper, 1014 1013 .program_3dlut = mpc32_program_3dlut,

+2 -2

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

··· 166 166 .num_states = 5, 167 167 .sr_exit_time_us = 28.0, 168 168 .sr_enter_plus_exit_time_us = 30.0, 169 - .sr_exit_z8_time_us = 210.0, 170 - .sr_enter_plus_exit_z8_time_us = 320.0, 169 + .sr_exit_z8_time_us = 250.0, 170 + .sr_enter_plus_exit_z8_time_us = 350.0, 171 171 .fclk_change_latency_us = 24.0, 172 172 .usr_retraining_latency_us = 2, 173 173 .writeback_latency_us = 12.0,

+84 -19

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

··· 98 98 .clock_limits = { 99 99 { 100 100 .state = 0, 101 - .dispclk_mhz = 1200.0, 102 - .dppclk_mhz = 1200.0, 101 + .dcfclk_mhz = 400.0, 102 + .fabricclk_mhz = 400.0, 103 + .socclk_mhz = 600.0, 104 + .dram_speed_mts = 3200.0, 105 + .dispclk_mhz = 600.0, 106 + .dppclk_mhz = 600.0, 103 107 .phyclk_mhz = 600.0, 104 108 .phyclk_d18_mhz = 667.0, 105 - .dscclk_mhz = 186.0, 109 + .dscclk_mhz = 200.0, 106 110 .dtbclk_mhz = 600.0, 107 111 }, 108 112 { 109 113 .state = 1, 110 - .dispclk_mhz = 1200.0, 111 - .dppclk_mhz = 1200.0, 114 + .dcfclk_mhz = 600.0, 115 + .fabricclk_mhz = 1000.0, 116 + .socclk_mhz = 733.0, 117 + .dram_speed_mts = 6400.0, 118 + .dispclk_mhz = 800.0, 119 + .dppclk_mhz = 800.0, 112 120 .phyclk_mhz = 810.0, 113 121 .phyclk_d18_mhz = 667.0, 114 - .dscclk_mhz = 209.0, 122 + .dscclk_mhz = 266.7, 115 123 .dtbclk_mhz = 600.0, 116 124 }, 117 125 { 118 126 .state = 2, 119 - .dispclk_mhz = 1200.0, 120 - .dppclk_mhz = 1200.0, 127 + .dcfclk_mhz = 738.0, 128 + .fabricclk_mhz = 1200.0, 129 + .socclk_mhz = 880.0, 130 + .dram_speed_mts = 7500.0, 131 + .dispclk_mhz = 800.0, 132 + .dppclk_mhz = 800.0, 121 133 .phyclk_mhz = 810.0, 122 134 .phyclk_d18_mhz = 667.0, 123 - .dscclk_mhz = 209.0, 135 + .dscclk_mhz = 266.7, 124 136 .dtbclk_mhz = 600.0, 125 137 }, 126 138 { 127 139 .state = 3, 128 - .dispclk_mhz = 1200.0, 129 - .dppclk_mhz = 1200.0, 140 + .dcfclk_mhz = 800.0, 141 + .fabricclk_mhz = 1400.0, 142 + .socclk_mhz = 978.0, 143 + .dram_speed_mts = 7500.0, 144 + .dispclk_mhz = 960.0, 145 + .dppclk_mhz = 960.0, 130 146 .phyclk_mhz = 810.0, 131 147 .phyclk_d18_mhz = 667.0, 132 - .dscclk_mhz = 371.0, 148 + .dscclk_mhz = 320.0, 133 149 .dtbclk_mhz = 600.0, 134 150 }, 135 151 { 136 152 .state = 4, 153 + .dcfclk_mhz = 873.0, 154 + .fabricclk_mhz = 1600.0, 155 + .socclk_mhz = 1100.0, 156 + .dram_speed_mts = 8533.0, 157 + .dispclk_mhz = 1066.7, 158 + .dppclk_mhz = 1066.7, 159 + .phyclk_mhz = 810.0, 160 + .phyclk_d18_mhz = 667.0, 161 + .dscclk_mhz = 355.6, 162 + .dtbclk_mhz = 600.0, 163 + }, 164 + { 165 + .state = 5, 166 + .dcfclk_mhz = 960.0, 167 + .fabricclk_mhz = 1700.0, 168 + .socclk_mhz = 1257.0, 169 + .dram_speed_mts = 8533.0, 137 170 .dispclk_mhz = 1200.0, 138 171 .dppclk_mhz = 1200.0, 139 172 .phyclk_mhz = 810.0, 140 173 .phyclk_d18_mhz = 667.0, 141 - .dscclk_mhz = 417.0, 174 + .dscclk_mhz = 400.0, 175 + .dtbclk_mhz = 600.0, 176 + }, 177 + { 178 + .state = 6, 179 + .dcfclk_mhz = 1067.0, 180 + .fabricclk_mhz = 1850.0, 181 + .socclk_mhz = 1257.0, 182 + .dram_speed_mts = 8533.0, 183 + .dispclk_mhz = 1371.4, 184 + .dppclk_mhz = 1371.4, 185 + .phyclk_mhz = 810.0, 186 + .phyclk_d18_mhz = 667.0, 187 + .dscclk_mhz = 457.1, 188 + .dtbclk_mhz = 600.0, 189 + }, 190 + { 191 + .state = 7, 192 + .dcfclk_mhz = 1200.0, 193 + .fabricclk_mhz = 2000.0, 194 + .socclk_mhz = 1467.0, 195 + .dram_speed_mts = 8533.0, 196 + .dispclk_mhz = 1600.0, 197 + .dppclk_mhz = 1600.0, 198 + .phyclk_mhz = 810.0, 199 + .phyclk_d18_mhz = 667.0, 200 + .dscclk_mhz = 533.3, 142 201 .dtbclk_mhz = 600.0, 143 202 }, 144 203 }, 145 - .num_states = 5, 204 + .num_states = 8, 146 205 .sr_exit_time_us = 28.0, 147 206 .sr_enter_plus_exit_time_us = 30.0, 148 - .sr_exit_z8_time_us = 210.0, 149 - .sr_enter_plus_exit_z8_time_us = 320.0, 207 + .sr_exit_z8_time_us = 250.0, 208 + .sr_enter_plus_exit_z8_time_us = 350.0, 150 209 .fclk_change_latency_us = 24.0, 151 210 .usr_retraining_latency_us = 2, 152 211 .writeback_latency_us = 12.0, ··· 236 177 .do_urgent_latency_adjustment = 0, 237 178 .urgent_latency_adjustment_fabric_clock_component_us = 0, 238 179 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 180 + .num_chans = 4, 181 + .dram_clock_change_latency_us = 11.72, 182 + .dispclk_dppclk_vco_speed_mhz = 2400.0, 239 183 }; 240 184 241 185 /* ··· 402 340 clock_limits[i].socclk_mhz; 403 341 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz = 404 342 clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio; 343 + dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz = 344 + clock_limits[i].dtbclk_mhz; 405 345 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = 406 346 clk_table->num_entries; 407 347 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = ··· 415 351 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels = 416 352 clk_table->num_entries; 417 353 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = 354 + clk_table->num_entries; 355 + dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels = 418 356 clk_table->num_entries; 419 357 } 420 358 } ··· 617 551 if (context->res_ctx.pipe_ctx[i].plane_state) 618 552 plane_count++; 619 553 } 554 + 620 555 /*dcn351 does not support z9/z10*/ 621 556 if (context->stream_count == 0 || plane_count == 0) { 622 557 support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY; ··· 631 564 dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000; 632 565 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; 633 566 634 - 635 567 /*for psr1/psr-su, we allow z8 and z10 based on latency, for replay with IPS enabled, it will enter ips2*/ 636 - if (is_pwrseq0 && (is_psr || is_replay)) 568 + if (is_pwrseq0 && (is_psr || is_replay)) 637 569 support = allow_z8 ? allow_z8 : DCN_ZSTATE_SUPPORT_DISALLOW; 638 - 639 570 } 640 571 context->bw_ctx.bw.dcn.clk.zstate_support = support; 641 572 }

+1 -5

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c

··· 228 228 break; 229 229 230 230 case dml_project_dcn35: 231 + case dml_project_dcn351: 231 232 out->num_chans = 4; 232 233 out->round_trip_ping_latency_dcfclk_cycles = 106; 233 234 out->smn_latency_us = 2; 234 235 out->dispclk_dppclk_vco_speed_mhz = 3600; 235 236 break; 236 237 237 - case dml_project_dcn351: 238 - out->num_chans = 16; 239 - out->round_trip_ping_latency_dcfclk_cycles = 1100; 240 - out->smn_latency_us = 2; 241 - break; 242 238 } 243 239 /* ---Overrides if available--- */ 244 240 if (dml2->config.bbox_overrides.dram_num_chan)

+2 -1

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

··· 1185 1185 if (dccg) { 1186 1186 dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); 1187 1187 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); 1188 - dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 1188 + if (dccg && dccg->funcs->set_dtbclk_dto) 1189 + dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 1189 1190 } 1190 1191 } else if (dccg && dccg->funcs->disable_symclk_se) { 1191 1192 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

-41

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

··· 69 69 #define FN(reg_name, field_name) \ 70 70 hws->shifts->field_name, hws->masks->field_name 71 71 72 - static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 73 - int opp_cnt) 74 - { 75 - bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 76 - int flow_ctrl_cnt; 77 - 78 - if (opp_cnt >= 2) 79 - hblank_halved = true; 80 - 81 - flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 82 - stream->timing.h_border_left - 83 - stream->timing.h_border_right; 84 - 85 - if (hblank_halved) 86 - flow_ctrl_cnt /= 2; 87 - 88 - /* ODM combine 4:1 case */ 89 - if (opp_cnt == 4) 90 - flow_ctrl_cnt /= 2; 91 - 92 - return flow_ctrl_cnt; 93 - } 94 - 95 72 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 96 73 { 97 74 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; ··· 160 183 struct pipe_ctx *odm_pipe; 161 184 int opp_cnt = 0; 162 185 int opp_inst[MAX_PIPES] = {0}; 163 - bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 164 - struct mpc_dwb_flow_control flow_control; 165 - struct mpc *mpc = dc->res_pool->mpc; 166 - int i; 167 186 168 187 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 169 188 ··· 171 198 else 172 199 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 173 200 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 174 - 175 - rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 176 - flow_control.flow_ctrl_mode = 0; 177 - flow_control.flow_ctrl_cnt0 = 0x80; 178 - flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 179 - if (mpc->funcs->set_out_rate_control) { 180 - for (i = 0; i < opp_cnt; ++i) { 181 - mpc->funcs->set_out_rate_control( 182 - mpc, opp_inst[i], 183 - true, 184 - rate_control_2x_pclk, 185 - &flow_control); 186 - } 187 - } 188 201 189 202 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 190 203 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(

-41

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

··· 966 966 } 967 967 } 968 968 969 - static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 970 - int opp_cnt) 971 - { 972 - bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 973 - int flow_ctrl_cnt; 974 - 975 - if (opp_cnt >= 2) 976 - hblank_halved = true; 977 - 978 - flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 979 - stream->timing.h_border_left - 980 - stream->timing.h_border_right; 981 - 982 - if (hblank_halved) 983 - flow_ctrl_cnt /= 2; 984 - 985 - /* ODM combine 4:1 case */ 986 - if (opp_cnt == 4) 987 - flow_ctrl_cnt /= 2; 988 - 989 - return flow_ctrl_cnt; 990 - } 991 - 992 969 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 993 970 { 994 971 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; ··· 1080 1103 struct pipe_ctx *odm_pipe; 1081 1104 int opp_cnt = 0; 1082 1105 int opp_inst[MAX_PIPES] = {0}; 1083 - bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 1084 - struct mpc_dwb_flow_control flow_control; 1085 - struct mpc *mpc = dc->res_pool->mpc; 1086 - int i; 1087 1106 1088 1107 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 1089 1108 ··· 1091 1118 else 1092 1119 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1093 1120 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1094 - 1095 - rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 1096 - flow_control.flow_ctrl_mode = 0; 1097 - flow_control.flow_ctrl_cnt0 = 0x80; 1098 - flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 1099 - if (mpc->funcs->set_out_rate_control) { 1100 - for (i = 0; i < opp_cnt; ++i) { 1101 - mpc->funcs->set_out_rate_control( 1102 - mpc, opp_inst[i], 1103 - true, 1104 - rate_control_2x_pclk, 1105 - &flow_control); 1106 - } 1107 - } 1108 1121 1109 1122 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1110 1123 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(

-41

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

··· 358 358 } 359 359 } 360 360 361 - static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 362 - int opp_cnt) 363 - { 364 - bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 365 - int flow_ctrl_cnt; 366 - 367 - if (opp_cnt >= 2) 368 - hblank_halved = true; 369 - 370 - flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 371 - stream->timing.h_border_left - 372 - stream->timing.h_border_right; 373 - 374 - if (hblank_halved) 375 - flow_ctrl_cnt /= 2; 376 - 377 - /* ODM combine 4:1 case */ 378 - if (opp_cnt == 4) 379 - flow_ctrl_cnt /= 2; 380 - 381 - return flow_ctrl_cnt; 382 - } 383 - 384 361 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 385 362 { 386 363 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; ··· 451 474 struct pipe_ctx *odm_pipe; 452 475 int opp_cnt = 0; 453 476 int opp_inst[MAX_PIPES] = {0}; 454 - bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 455 - struct mpc_dwb_flow_control flow_control; 456 - struct mpc *mpc = dc->res_pool->mpc; 457 - int i; 458 477 459 478 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 460 479 ··· 462 489 else 463 490 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 464 491 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 465 - 466 - rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 467 - flow_control.flow_ctrl_mode = 0; 468 - flow_control.flow_ctrl_cnt0 = 0x80; 469 - flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 470 - if (mpc->funcs->set_out_rate_control) { 471 - for (i = 0; i < opp_cnt; ++i) { 472 - mpc->funcs->set_out_rate_control( 473 - mpc, opp_inst[i], 474 - true, 475 - rate_control_2x_pclk, 476 - &flow_control); 477 - } 478 - } 479 492 480 493 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 481 494 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(

+1 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

··· 67 67 .prepare_bandwidth = dcn35_prepare_bandwidth, 68 68 .optimize_bandwidth = dcn35_optimize_bandwidth, 69 69 .update_bandwidth = dcn20_update_bandwidth, 70 - .set_drr = dcn10_set_drr, 70 + .set_drr = dcn35_set_drr, 71 71 .get_position = dcn10_get_position, 72 72 .set_static_screen_control = dcn35_set_static_screen_control, 73 73 .setup_stereo = dcn10_setup_stereo,

+8 -3

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

··· 700 700 .disable_dcc = DCC_ENABLE, 701 701 .disable_dpp_power_gate = true, 702 702 .disable_hubp_power_gate = true, 703 + .disable_optc_power_gate = true, /*should the same as above two*/ 704 + .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/ 703 705 .disable_clock_gate = false, 704 706 .disable_dsc_power_gate = true, 705 707 .vsr_support = true, ··· 744 742 }, 745 743 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT, 746 744 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ 745 + .minimum_z8_residency_time = 2100, 747 746 .using_dml2 = true, 748 747 .support_eDP1_5 = true, 749 748 .enable_hpo_pg_support = false, 750 749 .enable_legacy_fast_update = true, 751 750 .enable_single_display_2to1_odm_policy = true, 752 - .disable_idle_power_optimizations = true, 751 + .disable_idle_power_optimizations = false, 753 752 .dmcub_emulation = false, 754 753 .disable_boot_optimizations = false, 755 754 .disable_unbounded_requesting = false, ··· 761 758 .disable_z10 = true, 762 759 .ignore_pg = true, 763 760 .psp_disabled_wa = true, 764 - .ips2_eval_delay_us = 200, 765 - .ips2_entry_delay_us = 400 761 + .ips2_eval_delay_us = 2000, 762 + .ips2_entry_delay_us = 800, 763 + .disable_dmub_reallow_idle = true, 764 + .static_screen_wait_frames = 2, 766 765 }; 767 766 768 767 static const struct dc_panel_config panel_config_defaults = {

+5 -8

drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c

··· 147 147 } 148 148 149 149 /* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */ 150 - if (stream->link->psr_settings.psr_feature_enabled) { 151 - if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) 152 - vsc_packet_revision = vsc_packet_rev4; 153 - else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) 154 - vsc_packet_revision = vsc_packet_rev2; 155 - } 156 - 157 - if (stream->link->replay_settings.config.replay_supported) 150 + if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) 158 151 vsc_packet_revision = vsc_packet_rev4; 152 + else if (stream->link->replay_settings.config.replay_supported) 153 + vsc_packet_revision = vsc_packet_rev4; 154 + else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) 155 + vsc_packet_revision = vsc_packet_rev2; 159 156 160 157 /* Update to revision 5 for extended colorimetry support */ 161 158 if (stream->use_vsc_sdp_for_colorimetry)

+11 -2

drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h

··· 234 234 uint32_t enable_level_process_quantum_check : 1; 235 235 uint32_t is_vcn0_enabled : 1; 236 236 uint32_t is_vcn1_enabled : 1; 237 - uint32_t reserved : 27; 237 + uint32_t use_rs64mem_for_proc_ctx_csa : 1; 238 + uint32_t reserved : 26; 238 239 }; 239 240 uint32_t uint32_all; 240 241 }; ··· 298 297 299 298 struct { 300 299 uint32_t is_context_suspended : 1; 301 - uint32_t reserved : 31; 300 + uint32_t collaboration_mode : 1; 301 + uint32_t reserved : 30; 302 302 }; 303 303 struct UMSCH_API_STATUS api_status; 304 + uint32_t process_csa_array_index; 305 + uint32_t context_csa_array_index; 304 306 }; 305 307 306 308 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; ··· 318 314 uint64_t context_csa_addr; 319 315 320 316 struct UMSCH_API_STATUS api_status; 317 + uint32_t context_csa_array_index; 321 318 }; 322 319 323 320 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; ··· 342 337 uint32_t suspend_fence_value; 343 338 344 339 struct UMSCH_API_STATUS api_status; 340 + uint32_t context_csa_array_index; 345 341 }; 346 342 347 343 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; ··· 362 356 enum UMSCH_ENGINE_TYPE engine_type; 363 357 364 358 struct UMSCH_API_STATUS api_status; 359 + uint32_t context_csa_array_index; 365 360 }; 366 361 367 362 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; ··· 411 404 union UMSCH_AFFINITY affinity; 412 405 uint64_t context_csa_addr; 413 406 struct UMSCH_API_STATUS api_status; 407 + uint32_t context_csa_array_index; 414 408 }; 415 409 416 410 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; ··· 425 417 uint64_t context_quantum; 426 418 uint64_t context_csa_addr; 427 419 struct UMSCH_API_STATUS api_status; 420 + uint32_t context_csa_array_index; 428 421 }; 429 422 430 423 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

+14 -14

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h

··· 54 54 #define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team 55 55 #define PPSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version 56 56 #define PPSMC_MSG_GetDriverIfVersion 0x03 ///< Get PMFW_DRIVER_IF version 57 - #define PPSMC_MSG_SPARE0 0x04 ///< SPARE 58 - #define PPSMC_MSG_SPARE1 0x05 ///< SPARE 59 - #define PPSMC_MSG_PowerDownVcn 0x06 ///< Power down VCN 60 - #define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by default 61 - #define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless display 57 + #define PPSMC_MSG_PowerDownVcn1 0x04 ///< Power down VCN1 58 + #define PPSMC_MSG_PowerUpVcn1 0x05 ///< Power up VCN1; VCN1 is power gated by default 59 + #define PPSMC_MSG_PowerDownVcn0 0x06 ///< Power down VCN0 60 + #define PPSMC_MSG_PowerUpVcn0 0x07 ///< Power up VCN0; VCN0 is power gated by default 61 + #define PPSMC_MSG_SetHardMinVcn0 0x08 ///< For wireless display 62 62 #define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz 63 - #define PPSMC_MSG_SPARE2 0x0A ///< SPARE 64 - #define PPSMC_MSG_SPARE3 0x0B ///< SPARE 63 + #define PPSMC_MSG_SetHardMinVcn1 0x0A ///< For wireless display 64 + #define PPSMC_MSG_SetSoftMinVcn1 0x0B ///< Set soft min for VCN1 clocks (VCLK1 and DCLK1) 65 65 #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload 66 66 #define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of DRAM address for Driver table transfer 67 67 #define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer ··· 71 71 #define PPSMC_MSG_GetEnabledSmuFeatures 0x12 ///< Get enabled features in PMFW 72 72 #define PPSMC_MSG_SetHardMinSocclkByFreq 0x13 ///< Set hard min for SOC CLK 73 73 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK 74 - #define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK) 74 + #define PPSMC_MSG_SetSoftMinVcn0 0x15 ///< Set soft min for VCN0 clocks (VCLK0 and DCLK0) 75 75 76 76 #define PPSMC_MSG_EnableGfxImu 0x16 ///< Enable GFX IMU 77 77 ··· 84 84 85 85 #define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x1D ///< Set soft max for SOC CLK 86 86 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK 87 - #define PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK) 87 + #define PPSMC_MSG_SetSoftMaxVcn0 0x1F ///< Set soft max for VCN0 clocks (VCLK0 and DCLK0) 88 88 #define PPSMC_MSG_spare_0x20 0x20 89 - #define PPSMC_MSG_PowerDownJpeg 0x21 ///< Power down Jpeg 90 - #define PPSMC_MSG_PowerUpJpeg 0x22 ///< Power up Jpeg; VCN is power gated by default 89 + #define PPSMC_MSG_PowerDownJpeg0 0x21 ///< Power down Jpeg of VCN0 90 + #define PPSMC_MSG_PowerUpJpeg0 0x22 ///< Power up Jpeg of VCN0; VCN0 is power gated by default 91 91 92 92 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK 93 93 #define PPSMC_MSG_SetSoftMinSocclkByFreq 0x24 ///< Set soft min for SOC CLK 94 94 #define PPSMC_MSG_AllowZstates 0x25 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity 95 - #define PPSMC_MSG_Reserved 0x26 ///< Not used 96 - #define PPSMC_MSG_Reserved1 0x27 ///< Not used, previously PPSMC_MSG_RequestActiveWgp 97 - #define PPSMC_MSG_Reserved2 0x28 ///< Not used, previously PPSMC_MSG_QueryActiveWgp 95 + #define PPSMC_MSG_PowerDownJpeg1 0x26 ///< Power down Jpeg of VCN1 96 + #define PPSMC_MSG_PowerUpJpeg1 0x27 ///< Power up Jpeg of VCN1; VCN1 is power gated by default 97 + #define PPSMC_MSG_SetSoftMaxVcn1 0x28 ///< Set soft max for VCN1 clocks (VCLK1 and DCLK1) 98 98 #define PPSMC_MSG_PowerDownIspByTile 0x29 ///< ISP is power gated by default 99 99 #define PPSMC_MSG_PowerUpIspByTile 0x2A ///< This message is used to power up ISP tiles and enable the ISP DPM 100 100 #define PPSMC_MSG_SetHardMinIspiclkByFreq 0x2B ///< Set HardMin by frequency for ISPICLK

+10

drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h

··· 115 115 __SMU_DUMMY_MAP(PowerDownVcn), \ 116 116 __SMU_DUMMY_MAP(PowerUpJpeg), \ 117 117 __SMU_DUMMY_MAP(PowerDownJpeg), \ 118 + __SMU_DUMMY_MAP(PowerUpJpeg0), \ 119 + __SMU_DUMMY_MAP(PowerDownJpeg0), \ 120 + __SMU_DUMMY_MAP(PowerUpJpeg1), \ 121 + __SMU_DUMMY_MAP(PowerDownJpeg1), \ 118 122 __SMU_DUMMY_MAP(BacoAudioD3PME), \ 119 123 __SMU_DUMMY_MAP(ArmD3), \ 120 124 __SMU_DUMMY_MAP(RunDcBtc), \ ··· 139 135 __SMU_DUMMY_MAP(PowerUpSdma), \ 140 136 __SMU_DUMMY_MAP(SetHardMinIspclkByFreq), \ 141 137 __SMU_DUMMY_MAP(SetHardMinVcn), \ 138 + __SMU_DUMMY_MAP(SetHardMinVcn0), \ 139 + __SMU_DUMMY_MAP(SetHardMinVcn1), \ 142 140 __SMU_DUMMY_MAP(SetAllowFclkSwitch), \ 143 141 __SMU_DUMMY_MAP(SetMinVideoGfxclkFreq), \ 144 142 __SMU_DUMMY_MAP(ActiveProcessNotify), \ ··· 156 150 __SMU_DUMMY_MAP(SetPhyclkVoltageByFreq), \ 157 151 __SMU_DUMMY_MAP(SetDppclkVoltageByFreq), \ 158 152 __SMU_DUMMY_MAP(SetSoftMinVcn), \ 153 + __SMU_DUMMY_MAP(SetSoftMinVcn0), \ 154 + __SMU_DUMMY_MAP(SetSoftMinVcn1), \ 159 155 __SMU_DUMMY_MAP(EnablePostCode), \ 160 156 __SMU_DUMMY_MAP(GetGfxclkFrequency), \ 161 157 __SMU_DUMMY_MAP(GetFclkFrequency), \ ··· 169 161 __SMU_DUMMY_MAP(SetSoftMaxSocclkByFreq), \ 170 162 __SMU_DUMMY_MAP(SetSoftMaxFclkByFreq), \ 171 163 __SMU_DUMMY_MAP(SetSoftMaxVcn), \ 164 + __SMU_DUMMY_MAP(SetSoftMaxVcn0), \ 165 + __SMU_DUMMY_MAP(SetSoftMaxVcn1), \ 172 166 __SMU_DUMMY_MAP(PowerGateMmHub), \ 173 167 __SMU_DUMMY_MAP(UpdatePmeRestore), \ 174 168 __SMU_DUMMY_MAP(GpuChangeState), \

+44 -6

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

··· 1402 1402 if (adev->vcn.harvest_config & (1 << i)) 1403 1403 continue; 1404 1404 1405 - ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1406 - SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 1407 - i << 16U, NULL); 1405 + if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || 1406 + amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) { 1407 + if (i == 0) 1408 + ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1409 + SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0, 1410 + i << 16U, NULL); 1411 + else if (i == 1) 1412 + ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1413 + SMU_MSG_PowerUpVcn1 : SMU_MSG_PowerDownVcn1, 1414 + i << 16U, NULL); 1415 + } else { 1416 + ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1417 + SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 1418 + i << 16U, NULL); 1419 + } 1420 + 1408 1421 if (ret) 1409 1422 return ret; 1410 1423 } ··· 1428 1415 int smu_v14_0_set_jpeg_enable(struct smu_context *smu, 1429 1416 bool enable) 1430 1417 { 1431 - return smu_cmn_send_smc_msg_with_param(smu, enable ? 1432 - SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg, 1433 - 0, NULL); 1418 + struct amdgpu_device *adev = smu->adev; 1419 + int i, ret = 0; 1420 + 1421 + for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 1422 + if (adev->jpeg.harvest_config & (1 << i)) 1423 + continue; 1424 + 1425 + if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || 1426 + amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) { 1427 + if (i == 0) 1428 + ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1429 + SMU_MSG_PowerUpJpeg0 : SMU_MSG_PowerDownJpeg0, 1430 + i << 16U, NULL); 1431 + else if (i == 1 && amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) 1432 + ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1433 + SMU_MSG_PowerUpJpeg1 : SMU_MSG_PowerDownJpeg1, 1434 + i << 16U, NULL); 1435 + } else { 1436 + ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1437 + SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg, 1438 + i << 16U, NULL); 1439 + } 1440 + 1441 + if (ret) 1442 + return ret; 1443 + } 1444 + 1445 + return ret; 1434 1446 } 1435 1447 1436 1448 int smu_v14_0_run_btc(struct smu_context *smu)

+14 -7

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

··· 70 70 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 71 71 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetPmfwVersion, 1), 72 72 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 73 - MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 74 - MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 75 - MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 73 + MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0, 1), 74 + MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0, 1), 75 + MSG_MAP(SetHardMinVcn0, PPSMC_MSG_SetHardMinVcn0, 1), 76 + MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1, 1), 77 + MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1, 1), 78 + MSG_MAP(SetHardMinVcn1, PPSMC_MSG_SetHardMinVcn1, 1), 76 79 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 1), 77 80 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 78 81 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), ··· 86 83 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1), 87 84 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), 88 85 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 1), 89 - MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 86 + MSG_MAP(SetSoftMinVcn0, PPSMC_MSG_SetSoftMinVcn0, 1), 87 + MSG_MAP(SetSoftMinVcn1, PPSMC_MSG_SetSoftMinVcn1, 1), 90 88 MSG_MAP(EnableGfxImu, PPSMC_MSG_EnableGfxImu, 1), 91 89 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1), 92 90 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1), ··· 95 91 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 96 92 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), 97 93 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), 98 - MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 99 - MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 100 - MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 94 + MSG_MAP(SetSoftMaxVcn0, PPSMC_MSG_SetSoftMaxVcn0, 1), 95 + MSG_MAP(SetSoftMaxVcn1, PPSMC_MSG_SetSoftMaxVcn1, 1), 96 + MSG_MAP(PowerDownJpeg0, PPSMC_MSG_PowerDownJpeg0, 1), 97 + MSG_MAP(PowerUpJpeg0, PPSMC_MSG_PowerUpJpeg0, 1), 98 + MSG_MAP(PowerDownJpeg1, PPSMC_MSG_PowerDownJpeg1, 1), 99 + MSG_MAP(PowerUpJpeg1, PPSMC_MSG_PowerUpJpeg1, 1), 101 100 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), 102 101 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1), 103 102 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),

+7

drivers/gpu/drm/display/drm_dp_helper.c

··· 4111 4111 u32 overhead = 1000000; 4112 4112 int symbol_cycles; 4113 4113 4114 + if (lane_count == 0 || hactive == 0 || bpp_x16 == 0) { 4115 + DRM_DEBUG_KMS("Invalid BW overhead params: lane_count %d, hactive %d, bpp_x16 %d.%04d\n", 4116 + lane_count, hactive, 4117 + bpp_x16 >> 4, (bpp_x16 & 0xf) * 625); 4118 + return 0; 4119 + } 4120 + 4114 4121 /* 4115 4122 * DP Standard v2.1 2.6.4.1 4116 4123 * SSC downspread and ref clock variation margin:

-2

drivers/gpu/drm/i915/display/g4x_dp.c

··· 717 717 { 718 718 intel_enable_dp(state, encoder, pipe_config, conn_state); 719 719 intel_edp_backlight_on(pipe_config, conn_state); 720 - encoder->audio_enable(encoder, pipe_config, conn_state); 721 720 } 722 721 723 722 static void vlv_enable_dp(struct intel_atomic_state *state, ··· 725 726 const struct drm_connector_state *conn_state) 726 727 { 727 728 intel_edp_backlight_on(pipe_config, conn_state); 728 - encoder->audio_enable(encoder, pipe_config, conn_state); 729 729 } 730 730 731 731 static void g4x_pre_enable_dp(struct intel_atomic_state *state,

+2 -1

drivers/gpu/drm/i915/display/icl_dsi.c

··· 1155 1155 } 1156 1156 1157 1157 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1158 - intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1159 1158 1160 1159 /* ensure all panel commands dispatched before enabling transcoder */ 1161 1160 wait_for_cmds_dispatched_to_panel(encoder); ··· 1254 1255 1255 1256 /* step6d: enable dsi transcoder */ 1256 1257 gen11_dsi_enable_transcoder(encoder); 1258 + 1259 + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1257 1260 1258 1261 /* step7: enable backlight */ 1259 1262 intel_backlight_enable(crtc_state, conn_state);

+40 -6

drivers/gpu/drm/i915/display/intel_bios.c

··· 1955 1955 * these devices we split the init OTP sequence into a deassert sequence and 1956 1956 * the actual init OTP part. 1957 1957 */ 1958 - static void fixup_mipi_sequences(struct drm_i915_private *i915, 1959 - struct intel_panel *panel) 1958 + static void vlv_fixup_mipi_sequences(struct drm_i915_private *i915, 1959 + struct intel_panel *panel) 1960 1960 { 1961 1961 u8 *init_otp; 1962 1962 int len; 1963 - 1964 - /* Limit this to VLV for now. */ 1965 - if (!IS_VALLEYVIEW(i915)) 1966 - return; 1967 1963 1968 1964 /* Limit this to v1 vid-mode sequences */ 1969 1965 if (panel->vbt.dsi.config->is_cmd_mode || ··· 1994 1998 init_otp[len - 1] = MIPI_SEQ_INIT_OTP; 1995 1999 /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */ 1996 2000 panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1; 2001 + } 2002 + 2003 + /* 2004 + * Some machines (eg. Lenovo 82TQ) appear to have broken 2005 + * VBT sequences: 2006 + * - INIT_OTP is not present at all 2007 + * - what should be in INIT_OTP is in DISPLAY_ON 2008 + * - what should be in DISPLAY_ON is in BACKLIGHT_ON 2009 + * (along with the actual backlight stuff) 2010 + * 2011 + * To make those work we simply swap DISPLAY_ON and INIT_OTP. 2012 + * 2013 + * TODO: Do we need to limit this to specific machines, 2014 + * or examine the contents of the sequences to 2015 + * avoid false positives? 2016 + */ 2017 + static void icl_fixup_mipi_sequences(struct drm_i915_private *i915, 2018 + struct intel_panel *panel) 2019 + { 2020 + if (!panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] && 2021 + panel->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON]) { 2022 + drm_dbg_kms(&i915->drm, "Broken VBT: Swapping INIT_OTP and DISPLAY_ON sequences\n"); 2023 + 2024 + swap(panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP], 2025 + panel->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON]); 2026 + } 2027 + } 2028 + 2029 + static void fixup_mipi_sequences(struct drm_i915_private *i915, 2030 + struct intel_panel *panel) 2031 + { 2032 + if (DISPLAY_VER(i915) >= 11) 2033 + icl_fixup_mipi_sequences(i915, panel); 2034 + else if (IS_VALLEYVIEW(i915)) 2035 + vlv_fixup_mipi_sequences(i915, panel); 1997 2036 } 1998 2037 1999 2038 static void ··· 3381 3350 bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata) 3382 3351 { 3383 3352 const struct child_device_config *child = &devdata->child; 3353 + 3354 + if (!devdata) 3355 + return false; 3384 3356 3385 3357 if (!intel_bios_encoder_supports_dp(devdata) || 3386 3358 !intel_bios_encoder_supports_hdmi(devdata))

+1 -3

drivers/gpu/drm/i915/display/intel_cursor.c

··· 36 36 { 37 37 struct drm_i915_private *dev_priv = 38 38 to_i915(plane_state->uapi.plane->dev); 39 - const struct drm_framebuffer *fb = plane_state->hw.fb; 40 - struct drm_i915_gem_object *obj = intel_fb_obj(fb); 41 39 u32 base; 42 40 43 41 if (DISPLAY_INFO(dev_priv)->cursor_needs_physical) 44 - base = i915_gem_object_get_dma_address(obj, 0); 42 + base = plane_state->phys_dma_addr; 45 43 else 46 44 base = intel_plane_ggtt_offset(plane_state); 47 45

+1

drivers/gpu/drm/i915/display/intel_display_types.h

··· 727 727 #define PLANE_HAS_FENCE BIT(0) 728 728 729 729 struct intel_fb_view view; 730 + u32 phys_dma_addr; /* for cursor_needs_physical */ 730 731 731 732 /* Plane pxp decryption state */ 732 733 bool decrypt;

+2 -10

drivers/gpu/drm/i915/display/intel_dp.c

··· 67 67 #include "intel_dp_tunnel.h" 68 68 #include "intel_dpio_phy.h" 69 69 #include "intel_dpll.h" 70 + #include "intel_drrs.h" 70 71 #include "intel_fifo_underrun.h" 71 72 #include "intel_hdcp.h" 72 73 #include "intel_hdmi.h" ··· 2684 2683 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 2685 2684 } 2686 2685 2687 - static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915, 2688 - enum transcoder cpu_transcoder) 2689 - { 2690 - if (HAS_DOUBLE_BUFFERED_M_N(i915)) 2691 - return true; 2692 - 2693 - return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder); 2694 - } 2695 - 2696 2686 static bool can_enable_drrs(struct intel_connector *connector, 2697 2687 const struct intel_crtc_state *pipe_config, 2698 2688 const struct drm_display_mode *downclock_mode) ··· 2706 2714 if (pipe_config->has_pch_encoder) 2707 2715 return false; 2708 2716 2709 - if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder)) 2717 + if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder)) 2710 2718 return false; 2711 2719 2712 2720 return downclock_mode &&

+1 -1

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

··· 2554 2554 static bool 2555 2555 ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) 2556 2556 { 2557 - return (((IS_ELKHARTLAKE(i915) || IS_JASPERLAKE(i915)) && 2557 + return ((IS_ELKHARTLAKE(i915) && 2558 2558 IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) || 2559 2559 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) && 2560 2560 i915->display.dpll.ref_clks.nssc == 38400;

+11 -3

drivers/gpu/drm/i915/display/intel_drrs.c

··· 63 63 return str[drrs_type]; 64 64 } 65 65 66 + bool intel_cpu_transcoder_has_drrs(struct drm_i915_private *i915, 67 + enum transcoder cpu_transcoder) 68 + { 69 + if (HAS_DOUBLE_BUFFERED_M_N(i915)) 70 + return true; 71 + 72 + return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder); 73 + } 74 + 66 75 static void 67 76 intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc, 68 77 enum drrs_refresh_rate refresh_rate) ··· 321 312 mutex_lock(&crtc->drrs.mutex); 322 313 323 314 seq_printf(m, "DRRS capable: %s\n", 324 - str_yes_no(crtc_state->has_drrs || 325 - HAS_DOUBLE_BUFFERED_M_N(i915) || 326 - intel_cpu_transcoder_has_m2_n2(i915, crtc_state->cpu_transcoder))); 315 + str_yes_no(intel_cpu_transcoder_has_drrs(i915, 316 + crtc_state->cpu_transcoder))); 327 317 328 318 seq_printf(m, "DRRS enabled: %s\n", 329 319 str_yes_no(crtc_state->has_drrs));

+3

drivers/gpu/drm/i915/display/intel_drrs.h

··· 9 9 #include <linux/types.h> 10 10 11 11 enum drrs_type; 12 + enum transcoder; 12 13 struct drm_i915_private; 13 14 struct intel_atomic_state; 14 15 struct intel_crtc; 15 16 struct intel_crtc_state; 16 17 struct intel_connector; 17 18 19 + bool intel_cpu_transcoder_has_drrs(struct drm_i915_private *i915, 20 + enum transcoder cpu_transcoder); 18 21 const char *intel_drrs_type_str(enum drrs_type drrs_type); 19 22 bool intel_drrs_is_active(struct intel_crtc *crtc); 20 23 void intel_drrs_activate(const struct intel_crtc_state *crtc_state);

+14

drivers/gpu/drm/i915/display/intel_dsb.c

··· 340 340 return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode, latency)); 341 341 } 342 342 343 + static u32 dsb_chicken(struct intel_crtc *crtc) 344 + { 345 + if (crtc->mode_flags & I915_MODE_FLAG_VRR) 346 + return DSB_CTRL_WAIT_SAFE_WINDOW | 347 + DSB_CTRL_NO_WAIT_VBLANK | 348 + DSB_INST_WAIT_SAFE_WINDOW | 349 + DSB_INST_NO_WAIT_VBLANK; 350 + else 351 + return 0; 352 + } 353 + 343 354 static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, 344 355 int dewake_scanline) 345 356 { ··· 371 360 372 361 intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), 373 362 ctrl | DSB_ENABLE); 363 + 364 + intel_de_write_fw(dev_priv, DSB_CHICKEN(pipe, dsb->id), 365 + dsb_chicken(crtc)); 374 366 375 367 intel_de_write_fw(dev_priv, DSB_HEAD(pipe, dsb->id), 376 368 intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf));

+10

drivers/gpu/drm/i915/display/intel_fb_pin.c

··· 255 255 return PTR_ERR(vma); 256 256 257 257 plane_state->ggtt_vma = vma; 258 + 259 + /* 260 + * Pre-populate the dma address before we enter the vblank 261 + * evade critical section as i915_gem_object_get_dma_address() 262 + * will trigger might_sleep() even if it won't actually sleep, 263 + * which is the case when the fb has already been pinned. 264 + */ 265 + if (phys_cursor) 266 + plane_state->phys_dma_addr = 267 + i915_gem_object_get_dma_address(intel_fb_obj(fb), 0); 258 268 } else { 259 269 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 260 270

-4

drivers/gpu/drm/i915/display/intel_sdvo.c

··· 1842 1842 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1843 1843 u32 temp; 1844 1844 1845 - encoder->audio_disable(encoder, old_crtc_state, conn_state); 1846 - 1847 1845 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1848 1846 if (0) 1849 1847 intel_sdvo_set_encoder_power_state(intel_sdvo, ··· 1933 1935 intel_sdvo_set_encoder_power_state(intel_sdvo, 1934 1936 DRM_MODE_DPMS_ON); 1935 1937 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo_connector->output_flag); 1936 - 1937 - encoder->audio_enable(encoder, pipe_config, conn_state); 1938 1938 } 1939 1939 1940 1940 static enum drm_mode_status

+4 -3

drivers/gpu/drm/i915/display/intel_vrr.c

··· 187 187 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 188 188 189 189 /* 190 - * TRANS_SET_CONTEXT_LATENCY with VRR enabled 191 - * requires this chicken bit on ADL/DG2. 190 + * This bit seems to have two meanings depending on the platform: 191 + * TGL: generate VRR "safe window" for DSB vblank waits 192 + * ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR 192 193 */ 193 - if (DISPLAY_VER(dev_priv) == 13) 194 + if (IS_DISPLAY_VER(dev_priv, 12, 13)) 194 195 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 195 196 0, PIPE_VBLANK_WITH_DELAY); 196 197

+3

drivers/gpu/drm/i915/display/skl_universal_plane.c

··· 2295 2295 if (HAS_4TILE(i915)) 2296 2296 caps |= INTEL_PLANE_CAP_TILING_4; 2297 2297 2298 + if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(i915)) 2299 + return caps; 2300 + 2298 2301 if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) { 2299 2302 caps |= INTEL_PLANE_CAP_CCS_RC; 2300 2303 if (DISPLAY_VER(i915) >= 12)

-3

drivers/gpu/drm/i915/gt/intel_engine_pm.c

··· 279 279 intel_engine_park_heartbeat(engine); 280 280 intel_breadcrumbs_park(engine->breadcrumbs); 281 281 282 - /* Must be reset upon idling, or we may miss the busy wakeup. */ 283 - GEM_BUG_ON(engine->sched_engine->queue_priority_hint != INT_MIN); 284 - 285 282 if (engine->park) 286 283 engine->park(engine); 287 284

+3

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

··· 3272 3272 { 3273 3273 cancel_timer(&engine->execlists.timer); 3274 3274 cancel_timer(&engine->execlists.preempt); 3275 + 3276 + /* Reset upon idling, or we may delay the busy wakeup. */ 3277 + WRITE_ONCE(engine->sched_engine->queue_priority_hint, INT_MIN); 3275 3278 } 3276 3279 3277 3280 static void add_to_engine(struct i915_request *rq)

+1

drivers/gpu/drm/i915/gt/intel_workarounds.c

··· 1653 1653 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1654 1654 { 1655 1655 /* Wa_14018575942 / Wa_18018781329 */ 1656 + wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1656 1657 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1657 1658 1658 1659 /* Wa_22016670082 */

+1 -1

drivers/gpu/drm/i915/i915_driver.c

··· 800 800 goto out_cleanup_modeset2; 801 801 802 802 ret = intel_pxp_init(i915); 803 - if (ret != -ENODEV) 803 + if (ret && ret != -ENODEV) 804 804 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret); 805 805 806 806 ret = intel_display_driver_probe(i915);

+19 -18

drivers/gpu/drm/i915/i915_hwmon.c

··· 72 72 struct intel_uncore *uncore = ddat->uncore; 73 73 intel_wakeref_t wakeref; 74 74 75 - mutex_lock(&hwmon->hwmon_lock); 75 + with_intel_runtime_pm(uncore->rpm, wakeref) { 76 + mutex_lock(&hwmon->hwmon_lock); 76 77 77 - with_intel_runtime_pm(uncore->rpm, wakeref) 78 78 intel_uncore_rmw(uncore, reg, clear, set); 79 79 80 - mutex_unlock(&hwmon->hwmon_lock); 80 + mutex_unlock(&hwmon->hwmon_lock); 81 + } 81 82 } 82 83 83 84 /* ··· 137 136 else 138 137 rgaddr = hwmon->rg.energy_status_all; 139 138 140 - mutex_lock(&hwmon->hwmon_lock); 139 + with_intel_runtime_pm(uncore->rpm, wakeref) { 140 + mutex_lock(&hwmon->hwmon_lock); 141 141 142 - with_intel_runtime_pm(uncore->rpm, wakeref) 143 142 reg_val = intel_uncore_read(uncore, rgaddr); 144 143 145 - if (reg_val >= ei->reg_val_prev) 146 - ei->accum_energy += reg_val - ei->reg_val_prev; 147 - else 148 - ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val; 149 - ei->reg_val_prev = reg_val; 144 + if (reg_val >= ei->reg_val_prev) 145 + ei->accum_energy += reg_val - ei->reg_val_prev; 146 + else 147 + ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val; 148 + ei->reg_val_prev = reg_val; 150 149 151 - *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY, 152 - hwmon->scl_shift_energy); 153 - mutex_unlock(&hwmon->hwmon_lock); 150 + *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY, 151 + hwmon->scl_shift_energy); 152 + mutex_unlock(&hwmon->hwmon_lock); 153 + } 154 154 } 155 155 156 156 static ssize_t ··· 406 404 407 405 /* Block waiting for GuC reset to complete when needed */ 408 406 for (;;) { 407 + wakeref = intel_runtime_pm_get(ddat->uncore->rpm); 409 408 mutex_lock(&hwmon->hwmon_lock); 410 409 411 410 prepare_to_wait(&ddat->waitq, &wait, TASK_INTERRUPTIBLE); ··· 420 417 } 421 418 422 419 mutex_unlock(&hwmon->hwmon_lock); 420 + intel_runtime_pm_put(ddat->uncore->rpm, wakeref); 423 421 424 422 schedule(); 425 423 } 426 424 finish_wait(&ddat->waitq, &wait); 427 425 if (ret) 428 - goto unlock; 429 - 430 - wakeref = intel_runtime_pm_get(ddat->uncore->rpm); 426 + goto exit; 431 427 432 428 /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */ 433 429 if (val == PL1_DISABLE) { ··· 446 444 intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit, 447 445 PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, nval); 448 446 exit: 449 - intel_runtime_pm_put(ddat->uncore->rpm, wakeref); 450 - unlock: 451 447 mutex_unlock(&hwmon->hwmon_lock); 448 + intel_runtime_pm_put(ddat->uncore->rpm, wakeref); 452 449 return ret; 453 450 } 454 451

+2

drivers/gpu/drm/i915/i915_memcpy.c

··· 25 25 #include <linux/kernel.h> 26 26 #include <linux/string.h> 27 27 #include <linux/cpufeature.h> 28 + #include <linux/bug.h> 29 + #include <linux/build_bug.h> 28 30 #include <asm/fpu/api.h> 29 31 30 32 #include "i915_memcpy.h"

+1 -1

drivers/gpu/drm/i915/i915_reg.h

··· 4599 4599 #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ 4600 4600 _MTL_CHICKEN_TRANS_A, \ 4601 4601 _MTL_CHICKEN_TRANS_B) 4602 - #define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* ADL/DG2 */ 4602 + #define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */ 4603 4603 #define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */ 4604 4604 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 4605 4605 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)

+43 -7

drivers/gpu/drm/i915/i915_vma.c

··· 34 34 #include "gt/intel_engine.h" 35 35 #include "gt/intel_engine_heartbeat.h" 36 36 #include "gt/intel_gt.h" 37 + #include "gt/intel_gt_pm.h" 37 38 #include "gt/intel_gt_requests.h" 38 39 #include "gt/intel_tlb.h" 39 40 ··· 104 103 105 104 static int __i915_vma_active(struct i915_active *ref) 106 105 { 107 - return i915_vma_tryget(active_to_vma(ref)) ? 0 : -ENOENT; 106 + struct i915_vma *vma = active_to_vma(ref); 107 + 108 + if (!i915_vma_tryget(vma)) 109 + return -ENOENT; 110 + 111 + /* 112 + * Exclude global GTT VMA from holding a GT wakeref 113 + * while active, otherwise GPU never goes idle. 114 + */ 115 + if (!i915_vma_is_ggtt(vma)) { 116 + /* 117 + * Since we and our _retire() counterpart can be 118 + * called asynchronously, storing a wakeref tracking 119 + * handle inside struct i915_vma is not safe, and 120 + * there is no other good place for that. Hence, 121 + * use untracked variants of intel_gt_pm_get/put(). 122 + */ 123 + intel_gt_pm_get_untracked(vma->vm->gt); 124 + } 125 + 126 + return 0; 108 127 } 109 128 110 129 static void __i915_vma_retire(struct i915_active *ref) 111 130 { 112 - i915_vma_put(active_to_vma(ref)); 131 + struct i915_vma *vma = active_to_vma(ref); 132 + 133 + if (!i915_vma_is_ggtt(vma)) { 134 + /* 135 + * Since we can be called from atomic contexts, 136 + * use an async variant of intel_gt_pm_put(). 137 + */ 138 + intel_gt_pm_put_async_untracked(vma->vm->gt); 139 + } 140 + 141 + i915_vma_put(vma); 113 142 } 114 143 115 144 static struct i915_vma * ··· 1435 1404 struct i915_vma_work *work = NULL; 1436 1405 struct dma_fence *moving = NULL; 1437 1406 struct i915_vma_resource *vma_res = NULL; 1438 - intel_wakeref_t wakeref = 0; 1407 + intel_wakeref_t wakeref; 1439 1408 unsigned int bound; 1440 1409 int err; 1441 1410 ··· 1455 1424 if (err) 1456 1425 return err; 1457 1426 1458 - if (flags & PIN_GLOBAL) 1459 - wakeref = intel_runtime_pm_get(&vma->vm->i915->runtime_pm); 1427 + /* 1428 + * In case of a global GTT, we must hold a runtime-pm wakeref 1429 + * while global PTEs are updated. In other cases, we hold 1430 + * the rpm reference while the VMA is active. Since runtime 1431 + * resume may require allocations, which are forbidden inside 1432 + * vm->mutex, get the first rpm wakeref outside of the mutex. 1433 + */ 1434 + wakeref = intel_runtime_pm_get(&vma->vm->i915->runtime_pm); 1460 1435 1461 1436 if (flags & vma->vm->bind_async_flags) { 1462 1437 /* lock VM */ ··· 1598 1561 if (work) 1599 1562 dma_fence_work_commit_imm(&work->base); 1600 1563 err_rpm: 1601 - if (wakeref) 1602 - intel_runtime_pm_put(&vma->vm->i915->runtime_pm, wakeref); 1564 + intel_runtime_pm_put(&vma->vm->i915->runtime_pm, wakeref); 1603 1565 1604 1566 if (moving) 1605 1567 dma_fence_put(moving);

+6 -6

drivers/gpu/drm/nouveau/nouveau_dmem.c

··· 378 378 dma_addr_t *dma_addrs; 379 379 struct nouveau_fence *fence; 380 380 381 - src_pfns = kcalloc(npages, sizeof(*src_pfns), GFP_KERNEL); 382 - dst_pfns = kcalloc(npages, sizeof(*dst_pfns), GFP_KERNEL); 383 - dma_addrs = kcalloc(npages, sizeof(*dma_addrs), GFP_KERNEL); 381 + src_pfns = kvcalloc(npages, sizeof(*src_pfns), GFP_KERNEL | __GFP_NOFAIL); 382 + dst_pfns = kvcalloc(npages, sizeof(*dst_pfns), GFP_KERNEL | __GFP_NOFAIL); 383 + dma_addrs = kvcalloc(npages, sizeof(*dma_addrs), GFP_KERNEL | __GFP_NOFAIL); 384 384 385 385 migrate_device_range(src_pfns, chunk->pagemap.range.start >> PAGE_SHIFT, 386 386 npages); ··· 406 406 migrate_device_pages(src_pfns, dst_pfns, npages); 407 407 nouveau_dmem_fence_done(&fence); 408 408 migrate_device_finalize(src_pfns, dst_pfns, npages); 409 - kfree(src_pfns); 410 - kfree(dst_pfns); 409 + kvfree(src_pfns); 410 + kvfree(dst_pfns); 411 411 for (i = 0; i < npages; i++) 412 412 dma_unmap_page(chunk->drm->dev->dev, dma_addrs[i], PAGE_SIZE, DMA_BIDIRECTIONAL); 413 - kfree(dma_addrs); 413 + kvfree(dma_addrs); 414 414 } 415 415 416 416 void

-2

drivers/gpu/drm/qxl/qxl_cmd.c

··· 421 421 { 422 422 uint32_t handle; 423 423 int idr_ret; 424 - int count = 0; 425 424 again: 426 425 idr_preload(GFP_ATOMIC); 427 426 spin_lock(&qdev->surf_id_idr_lock); ··· 432 433 handle = idr_ret; 433 434 434 435 if (handle >= qdev->rom->n_surfaces) { 435 - count++; 436 436 spin_lock(&qdev->surf_id_idr_lock); 437 437 idr_remove(&qdev->surf_id_idr, handle); 438 438 spin_unlock(&qdev->surf_id_idr_lock);

+1 -3

drivers/gpu/drm/qxl/qxl_ioctl.c

··· 145 145 struct qxl_release *release; 146 146 struct qxl_bo *cmd_bo; 147 147 void *fb_cmd; 148 - int i, ret, num_relocs; 148 + int i, ret; 149 149 int unwritten; 150 150 151 151 switch (cmd->type) { ··· 200 200 } 201 201 202 202 /* fill out reloc info structs */ 203 - num_relocs = 0; 204 203 for (i = 0; i < cmd->relocs_num; ++i) { 205 204 struct drm_qxl_reloc reloc; 206 205 struct drm_qxl_reloc __user *u = u64_to_user_ptr(cmd->relocs); ··· 229 230 reloc_info[i].dst_bo = cmd_bo; 230 231 reloc_info[i].dst_offset = reloc.dst_offset + release->release_offset; 231 232 } 232 - num_relocs++; 233 233 234 234 /* reserve and validate the reloc dst bo */ 235 235 if (reloc.reloc_type == QXL_RELOC_TYPE_BO || reloc.src_handle) {

-2

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

··· 17 17 18 18 static const uint32_t formats_cluster[] = { 19 19 DRM_FORMAT_XRGB2101010, 20 - DRM_FORMAT_ARGB2101010, 21 20 DRM_FORMAT_XBGR2101010, 22 - DRM_FORMAT_ABGR2101010, 23 21 DRM_FORMAT_XRGB8888, 24 22 DRM_FORMAT_ARGB8888, 25 23 DRM_FORMAT_XBGR8888,

+9 -3

drivers/gpu/drm/scheduler/sched_entity.c

··· 71 71 entity->guilty = guilty; 72 72 entity->num_sched_list = num_sched_list; 73 73 entity->priority = priority; 74 + /* 75 + * It's perfectly valid to initialize an entity without having a valid 76 + * scheduler attached. It's just not valid to use the scheduler before it 77 + * is initialized itself. 78 + */ 74 79 entity->sched_list = num_sched_list > 1 ? sched_list : NULL; 75 80 RCU_INIT_POINTER(entity->last_scheduled, NULL); 76 81 RB_CLEAR_NODE(&entity->rb_tree_node); 77 82 78 - if (!sched_list[0]->sched_rq) { 79 - /* Warn drivers not to do this and to fix their DRM 80 - * calling order. 83 + if (num_sched_list && !sched_list[0]->sched_rq) { 84 + /* Since every entry covered by num_sched_list 85 + * should be non-NULL and therefore we warn drivers 86 + * not to do this and to fix their DRM calling order. 81 87 */ 82 88 pr_warn("%s: called with uninitialized scheduler\n", __func__); 83 89 } else if (num_sched_list) {

+9 -6

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

··· 1444 1444 root, "system_ttm"); 1445 1445 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM), 1446 1446 root, "vram_ttm"); 1447 - ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR), 1448 - root, "gmr_ttm"); 1449 - ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB), 1450 - root, "mob_ttm"); 1451 - ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM), 1452 - root, "system_mob_ttm"); 1447 + if (vmw->has_gmr) 1448 + ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR), 1449 + root, "gmr_ttm"); 1450 + if (vmw->has_mob) { 1451 + ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB), 1452 + root, "mob_ttm"); 1453 + ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM), 1454 + root, "system_mob_ttm"); 1455 + } 1453 1456 } 1454 1457 1455 1458 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,

+9 -50

drivers/gpu/drm/xe/xe_bo.c

··· 144 144 .mem_type = XE_PL_TT, 145 145 }; 146 146 *c += 1; 147 - 148 - if (bo->props.preferred_mem_type == XE_BO_PROPS_INVALID) 149 - bo->props.preferred_mem_type = XE_PL_TT; 150 147 } 151 148 } 152 149 ··· 178 181 } 179 182 places[*c] = place; 180 183 *c += 1; 181 - 182 - if (bo->props.preferred_mem_type == XE_BO_PROPS_INVALID) 183 - bo->props.preferred_mem_type = mem_type; 184 184 } 185 185 186 186 static void try_add_vram(struct xe_device *xe, struct xe_bo *bo, 187 187 u32 bo_flags, u32 *c) 188 188 { 189 - if (bo->props.preferred_gt == XE_GT1) { 190 - if (bo_flags & XE_BO_CREATE_VRAM1_BIT) 191 - add_vram(xe, bo, bo->placements, bo_flags, XE_PL_VRAM1, c); 192 - if (bo_flags & XE_BO_CREATE_VRAM0_BIT) 193 - add_vram(xe, bo, bo->placements, bo_flags, XE_PL_VRAM0, c); 194 - } else { 195 - if (bo_flags & XE_BO_CREATE_VRAM0_BIT) 196 - add_vram(xe, bo, bo->placements, bo_flags, XE_PL_VRAM0, c); 197 - if (bo_flags & XE_BO_CREATE_VRAM1_BIT) 198 - add_vram(xe, bo, bo->placements, bo_flags, XE_PL_VRAM1, c); 199 - } 189 + if (bo_flags & XE_BO_CREATE_VRAM0_BIT) 190 + add_vram(xe, bo, bo->placements, bo_flags, XE_PL_VRAM0, c); 191 + if (bo_flags & XE_BO_CREATE_VRAM1_BIT) 192 + add_vram(xe, bo, bo->placements, bo_flags, XE_PL_VRAM1, c); 200 193 } 201 194 202 195 static void try_add_stolen(struct xe_device *xe, struct xe_bo *bo, ··· 210 223 { 211 224 u32 c = 0; 212 225 213 - bo->props.preferred_mem_type = XE_BO_PROPS_INVALID; 214 - 215 - /* The order of placements should indicate preferred location */ 216 - 217 - if (bo->props.preferred_mem_class == DRM_XE_MEM_REGION_CLASS_SYSMEM) { 218 - try_add_system(xe, bo, bo_flags, &c); 219 - try_add_vram(xe, bo, bo_flags, &c); 220 - } else { 221 - try_add_vram(xe, bo, bo_flags, &c); 222 - try_add_system(xe, bo, bo_flags, &c); 223 - } 226 + try_add_vram(xe, bo, bo_flags, &c); 227 + try_add_system(xe, bo, bo_flags, &c); 224 228 try_add_stolen(xe, bo, bo_flags, &c); 225 229 226 230 if (!c) ··· 1104 1126 } 1105 1127 } 1106 1128 1107 - static bool should_migrate_to_system(struct xe_bo *bo) 1108 - { 1109 - struct xe_device *xe = xe_bo_device(bo); 1110 - 1111 - return xe_device_in_fault_mode(xe) && bo->props.cpu_atomic; 1112 - } 1113 - 1114 1129 static vm_fault_t xe_gem_fault(struct vm_fault *vmf) 1115 1130 { 1116 1131 struct ttm_buffer_object *tbo = vmf->vma->vm_private_data; ··· 1112 1141 struct xe_bo *bo = ttm_to_xe_bo(tbo); 1113 1142 bool needs_rpm = bo->flags & XE_BO_CREATE_VRAM_MASK; 1114 1143 vm_fault_t ret; 1115 - int idx, r = 0; 1144 + int idx; 1116 1145 1117 1146 if (needs_rpm) 1118 1147 xe_device_mem_access_get(xe); ··· 1124 1153 if (drm_dev_enter(ddev, &idx)) { 1125 1154 trace_xe_bo_cpu_fault(bo); 1126 1155 1127 - if (should_migrate_to_system(bo)) { 1128 - r = xe_bo_migrate(bo, XE_PL_TT); 1129 - if (r == -EBUSY || r == -ERESTARTSYS || r == -EINTR) 1130 - ret = VM_FAULT_NOPAGE; 1131 - else if (r) 1132 - ret = VM_FAULT_SIGBUS; 1133 - } 1134 - if (!ret) 1135 - ret = ttm_bo_vm_fault_reserved(vmf, 1136 - vmf->vma->vm_page_prot, 1137 - TTM_BO_VM_NUM_PREFAULT); 1156 + ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, 1157 + TTM_BO_VM_NUM_PREFAULT); 1138 1158 drm_dev_exit(idx); 1139 1159 } else { 1140 1160 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot); ··· 1253 1291 bo->flags = flags; 1254 1292 bo->cpu_caching = cpu_caching; 1255 1293 bo->ttm.base.funcs = &xe_gem_object_funcs; 1256 - bo->props.preferred_mem_class = XE_BO_PROPS_INVALID; 1257 - bo->props.preferred_gt = XE_BO_PROPS_INVALID; 1258 - bo->props.preferred_mem_type = XE_BO_PROPS_INVALID; 1259 1294 bo->ttm.priority = XE_BO_PRIORITY_NORMAL; 1260 1295 INIT_LIST_HEAD(&bo->pinned_link); 1261 1296 #ifdef CONFIG_PROC_FS

-19

drivers/gpu/drm/xe/xe_bo_types.h

··· 56 56 */ 57 57 struct list_head client_link; 58 58 #endif 59 - /** @props: BO user controlled properties */ 60 - struct { 61 - /** @preferred_mem: preferred memory class for this BO */ 62 - s16 preferred_mem_class; 63 - /** @prefered_gt: preferred GT for this BO */ 64 - s16 preferred_gt; 65 - /** @preferred_mem_type: preferred memory type */ 66 - s32 preferred_mem_type; 67 - /** 68 - * @cpu_atomic: the CPU expects to do atomics operations to 69 - * this BO 70 - */ 71 - bool cpu_atomic; 72 - /** 73 - * @device_atomic: the device expects to do atomics operations 74 - * to this BO 75 - */ 76 - bool device_atomic; 77 - } props; 78 59 /** @freed: List node for delayed put. */ 79 60 struct llist_node freed; 80 61 /** @created: Whether the bo has passed initial creation */

+2 -2

drivers/gpu/drm/xe/xe_device.h

··· 58 58 59 59 static inline struct xe_gt *xe_tile_get_gt(struct xe_tile *tile, u8 gt_id) 60 60 { 61 - if (drm_WARN_ON(&tile_to_xe(tile)->drm, gt_id > XE_MAX_GT_PER_TILE)) 61 + if (drm_WARN_ON(&tile_to_xe(tile)->drm, gt_id >= XE_MAX_GT_PER_TILE)) 62 62 gt_id = 0; 63 63 64 64 return gt_id ? tile->media_gt : tile->primary_gt; ··· 79 79 if (MEDIA_VER(xe) >= 13) { 80 80 gt = xe_tile_get_gt(root_tile, gt_id); 81 81 } else { 82 - if (drm_WARN_ON(&xe->drm, gt_id > XE_MAX_TILES_PER_DEVICE)) 82 + if (drm_WARN_ON(&xe->drm, gt_id >= XE_MAX_TILES_PER_DEVICE)) 83 83 gt_id = 0; 84 84 85 85 gt = xe->tiles[gt_id].primary_gt;

+1 -1

drivers/gpu/drm/xe/xe_exec_queue.c

··· 448 448 { 449 449 u32 idx; 450 450 451 - if (eci.engine_class > ARRAY_SIZE(user_to_xe_engine_class)) 451 + if (eci.engine_class >= ARRAY_SIZE(user_to_xe_engine_class)) 452 452 return NULL; 453 453 454 454 if (eci.gt_id >= xe->info.gt_count)

+1 -1

drivers/gpu/drm/xe/xe_guc_submit.c

··· 1220 1220 init_waitqueue_head(&ge->suspend_wait); 1221 1221 1222 1222 timeout = (q->vm && xe_vm_in_lr_mode(q->vm)) ? MAX_SCHEDULE_TIMEOUT : 1223 - q->sched_props.job_timeout_ms; 1223 + msecs_to_jiffies(q->sched_props.job_timeout_ms); 1224 1224 err = xe_sched_init(&ge->sched, &drm_sched_ops, &xe_sched_ops, 1225 1225 get_submit_wq(guc), 1226 1226 q->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, 64,

+9 -11

drivers/gpu/drm/xe/xe_lrc.c

··· 97 97 #define REG16(x) \ 98 98 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ 99 99 (((x) >> 2) & 0x7f) 100 - #define END 0 101 100 { 102 101 const u32 base = hwe->mmio_base; 103 102 ··· 167 168 REG16(0x274), 168 169 REG16(0x270), 169 170 170 - END 171 + 0 171 172 }; 172 173 173 174 static const u8 dg2_xcs_offsets[] = { ··· 201 202 REG16(0x274), 202 203 REG16(0x270), 203 204 204 - END 205 + 0 205 206 }; 206 207 207 208 static const u8 gen12_rcs_offsets[] = { ··· 297 298 REG(0x084), 298 299 NOP(1), 299 300 300 - END 301 + 0 301 302 }; 302 303 303 304 static const u8 xehp_rcs_offsets[] = { ··· 338 339 LRI(1, 0), 339 340 REG(0x0c8), 340 341 341 - END 342 + 0 342 343 }; 343 344 344 345 static const u8 dg2_rcs_offsets[] = { ··· 381 382 LRI(1, 0), 382 383 REG(0x0c8), 383 384 384 - END 385 + 0 385 386 }; 386 387 387 388 static const u8 mtl_rcs_offsets[] = { ··· 424 425 LRI(1, 0), 425 426 REG(0x0c8), 426 427 427 - END 428 + 0 428 429 }; 429 430 430 431 #define XE2_CTX_COMMON \ ··· 470 471 LRI(1, 0), /* [0x47] */ 471 472 REG(0x0c8), /* [0x48] R_PWR_CLK_STATE */ 472 473 473 - END 474 + 0 474 475 }; 475 476 476 477 static const u8 xe2_bcs_offsets[] = { ··· 481 482 REG16(0x200), /* [0x42] BCS_SWCTRL */ 482 483 REG16(0x204), /* [0x44] BLIT_CCTL */ 483 484 484 - END 485 + 0 485 486 }; 486 487 487 488 static const u8 xe2_xcs_offsets[] = { 488 489 XE2_CTX_COMMON, 489 490 490 - END 491 + 0 491 492 }; 492 493 493 - #undef END 494 494 #undef REG16 495 495 #undef REG 496 496 #undef LRI

+1 -1

drivers/gpu/drm/xe/xe_query.c

··· 132 132 return -EINVAL; 133 133 134 134 eci = &resp.eci; 135 - if (eci->gt_id > XE_MAX_GT_PER_TILE) 135 + if (eci->gt_id >= XE_MAX_GT_PER_TILE) 136 136 return -EINVAL; 137 137 138 138 gt = xe_device_get_gt(xe, eci->gt_id);

+3

drivers/video/fbdev/Kconfig

··· 494 494 select FB_CFB_COPYAREA 495 495 select FB_CFB_FILLRECT 496 496 select FB_CFB_IMAGEBLIT 497 + select FB_IOMEM_FOPS 497 498 498 499 config FB_BW2 499 500 bool "BWtwo support" ··· 515 514 depends on (FB = y) && (SPARC && FB_SBUS) 516 515 select FB_CFB_COPYAREA 517 516 select FB_CFB_IMAGEBLIT 517 + select FB_IOMEM_FOPS 518 518 help 519 519 This is the frame buffer device driver for the CGsix (GX, TurboGX) 520 520 frame buffer. ··· 525 523 depends on FB_SBUS && SPARC64 526 524 select FB_CFB_COPYAREA 527 525 select FB_CFB_IMAGEBLIT 526 + select FB_IOMEM_FOPS 528 527 help 529 528 This is the frame buffer device driver for the Creator, Creator3D, 530 529 and Elite3D graphics boards.

+14 -3

include/uapi/linux/kfd_ioctl.h

··· 913 913 KFD_EC_MASK(EC_DEVICE_NEW)) 914 914 #define KFD_EC_MASK_PROCESS (KFD_EC_MASK(EC_PROCESS_RUNTIME) | \ 915 915 KFD_EC_MASK(EC_PROCESS_DEVICE_REMOVE)) 916 + #define KFD_EC_MASK_PACKET (KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_DIM_INVALID) | \ 917 + KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID) | \ 918 + KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_CODE_INVALID) | \ 919 + KFD_EC_MASK(EC_QUEUE_PACKET_RESERVED) | \ 920 + KFD_EC_MASK(EC_QUEUE_PACKET_UNSUPPORTED) | \ 921 + KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID) | \ 922 + KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID) | \ 923 + KFD_EC_MASK(EC_QUEUE_PACKET_VENDOR_UNSUPPORTED)) 916 924 917 925 /* Checks for exception code types for KFD search */ 926 + #define KFD_DBG_EC_IS_VALID(ecode) (ecode > EC_NONE && ecode < EC_MAX) 918 927 #define KFD_DBG_EC_TYPE_IS_QUEUE(ecode) \ 919 - (!!(KFD_EC_MASK(ecode) & KFD_EC_MASK_QUEUE)) 928 + (KFD_DBG_EC_IS_VALID(ecode) && !!(KFD_EC_MASK(ecode) & KFD_EC_MASK_QUEUE)) 920 929 #define KFD_DBG_EC_TYPE_IS_DEVICE(ecode) \ 921 - (!!(KFD_EC_MASK(ecode) & KFD_EC_MASK_DEVICE)) 930 + (KFD_DBG_EC_IS_VALID(ecode) && !!(KFD_EC_MASK(ecode) & KFD_EC_MASK_DEVICE)) 922 931 #define KFD_DBG_EC_TYPE_IS_PROCESS(ecode) \ 923 - (!!(KFD_EC_MASK(ecode) & KFD_EC_MASK_PROCESS)) 932 + (KFD_DBG_EC_IS_VALID(ecode) && !!(KFD_EC_MASK(ecode) & KFD_EC_MASK_PROCESS)) 933 + #define KFD_DBG_EC_TYPE_IS_PACKET(ecode) \ 934 + (KFD_DBG_EC_IS_VALID(ecode) && !!(KFD_EC_MASK(ecode) & KFD_EC_MASK_PACKET)) 924 935 925 936 926 937 /* Runtime enable states */

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